1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * Copyright (c) 2014,2016 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This software was developed by Andrew Turner under 7 * the sponsorship of the FreeBSD Foundation. 8 * 9 * This software was developed by Semihalf under 10 * the sponsorship of the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* Generic ECAM PCIe driver FDT attachment */ 35 36 #include <sys/cdefs.h> 37 #include "opt_platform.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/kernel.h> 43 #include <sys/malloc.h> 44 #include <sys/module.h> 45 #include <sys/rman.h> 46 47 #if defined(INTRNG) 48 #include <machine/intr.h> 49 #endif 50 51 #include <dev/ofw/openfirm.h> 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 #include <dev/ofw/ofw_pci.h> 55 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcib_private.h> 59 #include <dev/pci/pci_host_generic.h> 60 #include <dev/pci/pci_host_generic_fdt.h> 61 62 #include <machine/intr.h> 63 64 #include "pcib_if.h" 65 66 #define SPACE_CODE_SHIFT 24 67 #define SPACE_CODE_MASK 0x3 68 #define SPACE_CODE_IO_SPACE 0x1 69 #define PROPS_CELL_SIZE 1 70 #define PCI_ADDR_CELL_SIZE 2 71 72 struct pci_ofw_devinfo { 73 STAILQ_ENTRY(pci_ofw_devinfo) pci_ofw_link; 74 struct ofw_bus_devinfo di_dinfo; 75 uint8_t slot; 76 uint8_t func; 77 uint8_t bus; 78 }; 79 80 /* Forward prototypes */ 81 82 static int generic_pcie_fdt_probe(device_t dev); 83 static int parse_pci_mem_ranges(device_t, struct generic_pcie_core_softc *); 84 static int generic_pcie_ofw_bus_attach(device_t); 85 static const struct ofw_bus_devinfo *generic_pcie_ofw_get_devinfo(device_t, 86 device_t); 87 88 static int 89 generic_pcie_fdt_probe(device_t dev) 90 { 91 92 if (!ofw_bus_status_okay(dev)) 93 return (ENXIO); 94 95 if (ofw_bus_is_compatible(dev, "pci-host-ecam-generic")) { 96 device_set_desc(dev, "Generic PCI host controller"); 97 return (BUS_PROBE_GENERIC); 98 } 99 if (ofw_bus_is_compatible(dev, "arm,gem5_pcie")) { 100 device_set_desc(dev, "GEM5 PCIe host controller"); 101 return (BUS_PROBE_DEFAULT); 102 } 103 104 return (ENXIO); 105 } 106 107 int 108 pci_host_generic_setup_fdt(device_t dev) 109 { 110 struct generic_pcie_fdt_softc *sc; 111 phandle_t node; 112 int error; 113 114 sc = device_get_softc(dev); 115 116 STAILQ_INIT(&sc->pci_ofw_devlist); 117 118 /* Retrieve 'ranges' property from FDT */ 119 if (bootverbose) 120 device_printf(dev, "parsing FDT for ECAM%d:\n", sc->base.ecam); 121 if (parse_pci_mem_ranges(dev, &sc->base)) 122 return (ENXIO); 123 124 /* Attach OFW bus */ 125 if (generic_pcie_ofw_bus_attach(dev) != 0) 126 return (ENXIO); 127 128 node = ofw_bus_get_node(dev); 129 if (sc->base.coherent == 0) { 130 sc->base.coherent = OF_hasprop(node, "dma-coherent"); 131 } 132 if (bootverbose) 133 device_printf(dev, "Bus is%s cache-coherent\n", 134 sc->base.coherent ? "" : " not"); 135 136 /* TODO parse FDT bus ranges */ 137 sc->base.bus_start = 0; 138 sc->base.bus_end = 0xFF; 139 140 /* 141 * ofw_pcib uses device unit as PCI domain number. 142 * Do the same. Some boards have multiple RCs handled 143 * by different drivers, this ensures that there are 144 * no collisions. 145 */ 146 sc->base.ecam = device_get_unit(dev); 147 148 error = pci_host_generic_core_attach(dev); 149 if (error != 0) 150 return (error); 151 152 if (ofw_bus_is_compatible(dev, "marvell,armada8k-pcie-ecam") || 153 ofw_bus_is_compatible(dev, "socionext,synquacer-pcie-ecam") || 154 ofw_bus_is_compatible(dev, "snps,dw-pcie-ecam")) { 155 device_set_desc(dev, "Synopsys DesignWare PCIe Controller"); 156 sc->base.quirks |= PCIE_ECAM_DESIGNWARE_QUIRK; 157 } 158 159 ofw_bus_setup_iinfo(node, &sc->pci_iinfo, sizeof(cell_t)); 160 161 return (0); 162 } 163 164 int 165 pci_host_generic_fdt_attach(device_t dev) 166 { 167 int error; 168 169 error = pci_host_generic_setup_fdt(dev); 170 if (error != 0) 171 return (error); 172 173 device_add_child(dev, "pci", -1); 174 return (bus_generic_attach(dev)); 175 } 176 177 static int 178 parse_pci_mem_ranges(device_t dev, struct generic_pcie_core_softc *sc) 179 { 180 pcell_t pci_addr_cells, parent_addr_cells; 181 pcell_t attributes, size_cells; 182 cell_t *base_ranges; 183 int nbase_ranges; 184 phandle_t node; 185 int i, j, k; 186 int tuple; 187 188 node = ofw_bus_get_node(dev); 189 190 OF_getencprop(node, "#address-cells", &pci_addr_cells, 191 sizeof(pci_addr_cells)); 192 OF_getencprop(node, "#size-cells", &size_cells, 193 sizeof(size_cells)); 194 OF_getencprop(OF_parent(node), "#address-cells", &parent_addr_cells, 195 sizeof(parent_addr_cells)); 196 197 if (parent_addr_cells > 2 || pci_addr_cells != 3 || size_cells > 2) { 198 device_printf(dev, 199 "Unexpected number of address or size cells in FDT\n"); 200 return (ENXIO); 201 } 202 203 nbase_ranges = OF_getproplen(node, "ranges"); 204 sc->nranges = nbase_ranges / sizeof(cell_t) / 205 (parent_addr_cells + pci_addr_cells + size_cells); 206 base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK); 207 OF_getencprop(node, "ranges", base_ranges, nbase_ranges); 208 209 for (i = 0, j = 0; i < sc->nranges; i++) { 210 attributes = (base_ranges[j++] >> SPACE_CODE_SHIFT) & \ 211 SPACE_CODE_MASK; 212 if (attributes == SPACE_CODE_IO_SPACE) { 213 sc->ranges[i].flags |= FLAG_TYPE_IO; 214 } else { 215 sc->ranges[i].flags |= FLAG_TYPE_MEM; 216 } 217 218 sc->ranges[i].pci_base = 0; 219 for (k = 0; k < (pci_addr_cells - 1); k++) { 220 sc->ranges[i].pci_base <<= 32; 221 sc->ranges[i].pci_base |= base_ranges[j++]; 222 } 223 sc->ranges[i].phys_base = 0; 224 for (k = 0; k < parent_addr_cells; k++) { 225 sc->ranges[i].phys_base <<= 32; 226 sc->ranges[i].phys_base |= base_ranges[j++]; 227 } 228 sc->ranges[i].size = 0; 229 for (k = 0; k < size_cells; k++) { 230 sc->ranges[i].size <<= 32; 231 sc->ranges[i].size |= base_ranges[j++]; 232 } 233 } 234 235 for (; i < MAX_RANGES_TUPLES; i++) { 236 /* zero-fill remaining tuples to mark empty elements in array */ 237 sc->ranges[i].pci_base = 0; 238 sc->ranges[i].phys_base = 0; 239 sc->ranges[i].size = 0; 240 } 241 242 if (bootverbose) { 243 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { 244 device_printf(dev, 245 "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx\n", 246 sc->ranges[tuple].pci_base, 247 sc->ranges[tuple].phys_base, 248 sc->ranges[tuple].size); 249 } 250 } 251 252 free(base_ranges, M_DEVBUF); 253 return (0); 254 } 255 256 static int 257 generic_pcie_fdt_route_interrupt(device_t bus, device_t dev, int pin) 258 { 259 struct generic_pcie_fdt_softc *sc; 260 struct ofw_pci_register reg; 261 uint32_t pintr, mintr[4]; 262 phandle_t iparent; 263 int intrcells; 264 265 sc = device_get_softc(bus); 266 pintr = pin; 267 268 bzero(®, sizeof(reg)); 269 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | 270 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | 271 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); 272 273 intrcells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), 274 &sc->pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr), 275 mintr, sizeof(mintr), &iparent); 276 if (intrcells) { 277 pintr = ofw_bus_map_intr(dev, iparent, intrcells, mintr); 278 return (pintr); 279 } 280 281 device_printf(bus, "could not route pin %d for device %d.%d\n", 282 pin, pci_get_slot(dev), pci_get_function(dev)); 283 return (PCI_INVALID_IRQ); 284 } 285 286 static int 287 generic_pcie_fdt_alloc_msi(device_t pci, device_t child, int count, 288 int maxcount, int *irqs) 289 { 290 #if defined(INTRNG) 291 phandle_t msi_parent; 292 int err; 293 294 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 295 &msi_parent, NULL); 296 if (err != 0) 297 return (err); 298 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount, 299 irqs)); 300 #else 301 return (ENXIO); 302 #endif 303 } 304 305 static int 306 generic_pcie_fdt_release_msi(device_t pci, device_t child, int count, int *irqs) 307 { 308 #if defined(INTRNG) 309 phandle_t msi_parent; 310 int err; 311 312 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 313 &msi_parent, NULL); 314 if (err != 0) 315 return (err); 316 return (intr_release_msi(pci, child, msi_parent, count, irqs)); 317 #else 318 return (ENXIO); 319 #endif 320 } 321 322 static int 323 generic_pcie_fdt_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 324 uint32_t *data) 325 { 326 #if defined(INTRNG) 327 phandle_t msi_parent; 328 int err; 329 330 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 331 &msi_parent, NULL); 332 if (err != 0) 333 return (err); 334 return (intr_map_msi(pci, child, msi_parent, irq, addr, data)); 335 #else 336 return (ENXIO); 337 #endif 338 } 339 340 static int 341 generic_pcie_fdt_alloc_msix(device_t pci, device_t child, int *irq) 342 { 343 #if defined(INTRNG) 344 phandle_t msi_parent; 345 int err; 346 347 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 348 &msi_parent, NULL); 349 if (err != 0) 350 return (err); 351 return (intr_alloc_msix(pci, child, msi_parent, irq)); 352 #else 353 return (ENXIO); 354 #endif 355 } 356 357 static int 358 generic_pcie_fdt_release_msix(device_t pci, device_t child, int irq) 359 { 360 #if defined(INTRNG) 361 phandle_t msi_parent; 362 int err; 363 364 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 365 &msi_parent, NULL); 366 if (err != 0) 367 return (err); 368 return (intr_release_msix(pci, child, msi_parent, irq)); 369 #else 370 return (ENXIO); 371 #endif 372 } 373 374 static int 375 generic_pcie_get_iommu(device_t pci, device_t child, uintptr_t *id) 376 { 377 struct pci_id_ofw_iommu *iommu; 378 uint32_t iommu_rid; 379 uint32_t iommu_xref; 380 uint16_t pci_rid; 381 phandle_t node; 382 int err; 383 384 node = ofw_bus_get_node(pci); 385 pci_rid = pci_get_rid(child); 386 387 iommu = (struct pci_id_ofw_iommu *)id; 388 389 err = ofw_bus_iommu_map(node, pci_rid, &iommu_xref, &iommu_rid); 390 if (err == 0) { 391 iommu->id = iommu_rid; 392 iommu->xref = iommu_xref; 393 } 394 395 return (err); 396 } 397 398 int 399 generic_pcie_get_id(device_t pci, device_t child, enum pci_id_type type, 400 uintptr_t *id) 401 { 402 phandle_t node; 403 int err; 404 uint32_t rid; 405 uint16_t pci_rid; 406 407 if (type == PCI_ID_OFW_IOMMU) 408 return (generic_pcie_get_iommu(pci, child, id)); 409 410 if (type != PCI_ID_MSI) 411 return (pcib_get_id(pci, child, type, id)); 412 413 node = ofw_bus_get_node(pci); 414 pci_rid = pci_get_rid(child); 415 416 err = ofw_bus_msimap(node, pci_rid, NULL, &rid); 417 if (err != 0) 418 return (err); 419 *id = rid; 420 421 return (0); 422 } 423 424 static const struct ofw_bus_devinfo * 425 generic_pcie_ofw_get_devinfo(device_t bus, device_t child) 426 { 427 struct generic_pcie_fdt_softc *sc; 428 struct pci_ofw_devinfo *di; 429 uint8_t slot, func, busno; 430 431 sc = device_get_softc(bus); 432 slot = pci_get_slot(child); 433 func = pci_get_function(child); 434 busno = pci_get_bus(child); 435 436 STAILQ_FOREACH(di, &sc->pci_ofw_devlist, pci_ofw_link) 437 if (slot == di->slot && func == di->func && busno == di->bus) 438 return (&di->di_dinfo); 439 440 return (NULL); 441 } 442 443 /* Helper functions */ 444 445 static int 446 generic_pcie_ofw_bus_attach(device_t dev) 447 { 448 struct generic_pcie_fdt_softc *sc; 449 struct pci_ofw_devinfo *di; 450 phandle_t parent, node; 451 pcell_t reg[5]; 452 ssize_t len; 453 454 sc = device_get_softc(dev); 455 parent = ofw_bus_get_node(dev); 456 if (parent == 0) 457 return (0); 458 459 /* Iterate through all bus subordinates */ 460 for (node = OF_child(parent); node > 0; node = OF_peer(node)) { 461 len = OF_getencprop(node, "reg", reg, sizeof(reg)); 462 if (len != 5 * sizeof(pcell_t)) 463 continue; 464 465 /* Allocate and populate devinfo. */ 466 di = malloc(sizeof(*di), M_DEVBUF, M_WAITOK | M_ZERO); 467 if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) { 468 free(di, M_DEVBUF); 469 continue; 470 } 471 di->func = OFW_PCI_PHYS_HI_FUNCTION(reg[0]); 472 di->slot = OFW_PCI_PHYS_HI_DEVICE(reg[0]); 473 di->bus = OFW_PCI_PHYS_HI_BUS(reg[0]); 474 STAILQ_INSERT_TAIL(&sc->pci_ofw_devlist, di, pci_ofw_link); 475 } 476 477 return (0); 478 } 479 480 static device_method_t generic_pcie_fdt_methods[] = { 481 DEVMETHOD(device_probe, generic_pcie_fdt_probe), 482 DEVMETHOD(device_attach, pci_host_generic_fdt_attach), 483 DEVMETHOD(bus_alloc_resource, pci_host_generic_core_alloc_resource), 484 DEVMETHOD(bus_release_resource, pci_host_generic_core_release_resource), 485 486 /* pcib interface */ 487 DEVMETHOD(pcib_route_interrupt, generic_pcie_fdt_route_interrupt), 488 DEVMETHOD(pcib_alloc_msi, generic_pcie_fdt_alloc_msi), 489 DEVMETHOD(pcib_release_msi, generic_pcie_fdt_release_msi), 490 DEVMETHOD(pcib_alloc_msix, generic_pcie_fdt_alloc_msix), 491 DEVMETHOD(pcib_release_msix, generic_pcie_fdt_release_msix), 492 DEVMETHOD(pcib_map_msi, generic_pcie_fdt_map_msi), 493 DEVMETHOD(pcib_get_id, generic_pcie_get_id), 494 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), 495 496 DEVMETHOD(ofw_bus_get_devinfo, generic_pcie_ofw_get_devinfo), 497 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 498 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 499 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 500 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 501 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 502 503 DEVMETHOD_END 504 }; 505 506 DEFINE_CLASS_1(pcib, generic_pcie_fdt_driver, generic_pcie_fdt_methods, 507 sizeof(struct generic_pcie_fdt_softc), generic_pcie_core_driver); 508 509 DRIVER_MODULE(pcib, simplebus, generic_pcie_fdt_driver, 0, 0); 510 DRIVER_MODULE(pcib, ofwbus, generic_pcie_fdt_driver, 0, 0); 511