1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * Copyright (c) 2014,2016 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This software was developed by Andrew Turner under 7 * the sponsorship of the FreeBSD Foundation. 8 * 9 * This software was developed by Semihalf under 10 * the sponsorship of the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* Generic ECAM PCIe driver FDT attachment */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include "opt_platform.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/rman.h> 48 49 #if defined(INTRNG) 50 #include <machine/intr.h> 51 #endif 52 53 #include <dev/ofw/openfirm.h> 54 #include <dev/ofw/ofw_bus.h> 55 #include <dev/ofw/ofw_bus_subr.h> 56 #include <dev/ofw/ofw_pci.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcib_private.h> 61 #include <dev/pci/pci_host_generic.h> 62 #include <dev/pci/pci_host_generic_fdt.h> 63 64 #include <machine/intr.h> 65 66 #include "pcib_if.h" 67 68 #define SPACE_CODE_SHIFT 24 69 #define SPACE_CODE_MASK 0x3 70 #define SPACE_CODE_IO_SPACE 0x1 71 #define PROPS_CELL_SIZE 1 72 #define PCI_ADDR_CELL_SIZE 2 73 74 struct pci_ofw_devinfo { 75 STAILQ_ENTRY(pci_ofw_devinfo) pci_ofw_link; 76 struct ofw_bus_devinfo di_dinfo; 77 uint8_t slot; 78 uint8_t func; 79 uint8_t bus; 80 }; 81 82 /* Forward prototypes */ 83 84 static int generic_pcie_fdt_probe(device_t dev); 85 static int parse_pci_mem_ranges(device_t, struct generic_pcie_core_softc *); 86 static int generic_pcie_ofw_bus_attach(device_t); 87 static const struct ofw_bus_devinfo *generic_pcie_ofw_get_devinfo(device_t, 88 device_t); 89 90 static int 91 generic_pcie_fdt_probe(device_t dev) 92 { 93 94 if (!ofw_bus_status_okay(dev)) 95 return (ENXIO); 96 97 if (ofw_bus_is_compatible(dev, "pci-host-ecam-generic")) { 98 device_set_desc(dev, "Generic PCI host controller"); 99 return (BUS_PROBE_GENERIC); 100 } 101 if (ofw_bus_is_compatible(dev, "arm,gem5_pcie")) { 102 device_set_desc(dev, "GEM5 PCIe host controller"); 103 return (BUS_PROBE_DEFAULT); 104 } 105 106 return (ENXIO); 107 } 108 109 int 110 pci_host_generic_setup_fdt(device_t dev) 111 { 112 struct generic_pcie_fdt_softc *sc; 113 phandle_t node; 114 int error; 115 116 sc = device_get_softc(dev); 117 118 STAILQ_INIT(&sc->pci_ofw_devlist); 119 120 /* Retrieve 'ranges' property from FDT */ 121 if (bootverbose) 122 device_printf(dev, "parsing FDT for ECAM%d:\n", sc->base.ecam); 123 if (parse_pci_mem_ranges(dev, &sc->base)) 124 return (ENXIO); 125 126 /* Attach OFW bus */ 127 if (generic_pcie_ofw_bus_attach(dev) != 0) 128 return (ENXIO); 129 130 node = ofw_bus_get_node(dev); 131 if (sc->base.coherent == 0) { 132 sc->base.coherent = OF_hasprop(node, "dma-coherent"); 133 } 134 if (bootverbose) 135 device_printf(dev, "Bus is%s cache-coherent\n", 136 sc->base.coherent ? "" : " not"); 137 138 /* TODO parse FDT bus ranges */ 139 sc->base.bus_start = 0; 140 sc->base.bus_end = 0xFF; 141 142 error = pci_host_generic_core_attach(dev); 143 if (error != 0) 144 return (error); 145 146 ofw_bus_setup_iinfo(node, &sc->pci_iinfo, sizeof(cell_t)); 147 148 return (0); 149 } 150 151 int 152 pci_host_generic_attach(device_t dev) 153 { 154 struct generic_pcie_fdt_softc *sc; 155 int error; 156 157 sc = device_get_softc(dev); 158 159 error = pci_host_generic_setup_fdt(dev); 160 if (error != 0) 161 return (error); 162 163 device_add_child(dev, "pci", -1); 164 return (bus_generic_attach(dev)); 165 } 166 167 static int 168 parse_pci_mem_ranges(device_t dev, struct generic_pcie_core_softc *sc) 169 { 170 pcell_t pci_addr_cells, parent_addr_cells; 171 pcell_t attributes, size_cells; 172 cell_t *base_ranges; 173 int nbase_ranges; 174 phandle_t node; 175 int i, j, k; 176 int tuple; 177 178 node = ofw_bus_get_node(dev); 179 180 OF_getencprop(node, "#address-cells", &pci_addr_cells, 181 sizeof(pci_addr_cells)); 182 OF_getencprop(node, "#size-cells", &size_cells, 183 sizeof(size_cells)); 184 OF_getencprop(OF_parent(node), "#address-cells", &parent_addr_cells, 185 sizeof(parent_addr_cells)); 186 187 if (parent_addr_cells > 2 || pci_addr_cells != 3 || size_cells > 2) { 188 device_printf(dev, 189 "Unexpected number of address or size cells in FDT\n"); 190 return (ENXIO); 191 } 192 193 nbase_ranges = OF_getproplen(node, "ranges"); 194 sc->nranges = nbase_ranges / sizeof(cell_t) / 195 (parent_addr_cells + pci_addr_cells + size_cells); 196 base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK); 197 OF_getencprop(node, "ranges", base_ranges, nbase_ranges); 198 199 for (i = 0, j = 0; i < sc->nranges; i++) { 200 attributes = (base_ranges[j++] >> SPACE_CODE_SHIFT) & \ 201 SPACE_CODE_MASK; 202 if (attributes == SPACE_CODE_IO_SPACE) { 203 sc->ranges[i].flags |= FLAG_TYPE_IO; 204 } else { 205 sc->ranges[i].flags |= FLAG_TYPE_MEM; 206 } 207 208 sc->ranges[i].pci_base = 0; 209 for (k = 0; k < (pci_addr_cells - 1); k++) { 210 sc->ranges[i].pci_base <<= 32; 211 sc->ranges[i].pci_base |= base_ranges[j++]; 212 } 213 sc->ranges[i].phys_base = 0; 214 for (k = 0; k < parent_addr_cells; k++) { 215 sc->ranges[i].phys_base <<= 32; 216 sc->ranges[i].phys_base |= base_ranges[j++]; 217 } 218 sc->ranges[i].size = 0; 219 for (k = 0; k < size_cells; k++) { 220 sc->ranges[i].size <<= 32; 221 sc->ranges[i].size |= base_ranges[j++]; 222 } 223 } 224 225 for (; i < MAX_RANGES_TUPLES; i++) { 226 /* zero-fill remaining tuples to mark empty elements in array */ 227 sc->ranges[i].pci_base = 0; 228 sc->ranges[i].phys_base = 0; 229 sc->ranges[i].size = 0; 230 } 231 232 if (bootverbose) { 233 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { 234 device_printf(dev, 235 "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx\n", 236 sc->ranges[tuple].pci_base, 237 sc->ranges[tuple].phys_base, 238 sc->ranges[tuple].size); 239 } 240 } 241 242 free(base_ranges, M_DEVBUF); 243 return (0); 244 } 245 246 static int 247 generic_pcie_fdt_route_interrupt(device_t bus, device_t dev, int pin) 248 { 249 struct generic_pcie_fdt_softc *sc; 250 struct ofw_pci_register reg; 251 uint32_t pintr, mintr[4]; 252 phandle_t iparent; 253 int intrcells; 254 255 sc = device_get_softc(bus); 256 pintr = pin; 257 258 bzero(®, sizeof(reg)); 259 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | 260 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | 261 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); 262 263 intrcells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), 264 &sc->pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr), 265 mintr, sizeof(mintr), &iparent); 266 if (intrcells) { 267 pintr = ofw_bus_map_intr(dev, iparent, intrcells, mintr); 268 return (pintr); 269 } 270 271 device_printf(bus, "could not route pin %d for device %d.%d\n", 272 pin, pci_get_slot(dev), pci_get_function(dev)); 273 return (PCI_INVALID_IRQ); 274 } 275 276 static int 277 generic_pcie_fdt_alloc_msi(device_t pci, device_t child, int count, 278 int maxcount, int *irqs) 279 { 280 #if defined(INTRNG) 281 phandle_t msi_parent; 282 int err; 283 284 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 285 &msi_parent, NULL); 286 if (err != 0) 287 return (err); 288 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount, 289 irqs)); 290 #else 291 return (ENXIO); 292 #endif 293 } 294 295 static int 296 generic_pcie_fdt_release_msi(device_t pci, device_t child, int count, int *irqs) 297 { 298 #if defined(INTRNG) 299 phandle_t msi_parent; 300 int err; 301 302 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 303 &msi_parent, NULL); 304 if (err != 0) 305 return (err); 306 return (intr_release_msi(pci, child, msi_parent, count, irqs)); 307 #else 308 return (ENXIO); 309 #endif 310 } 311 312 static int 313 generic_pcie_fdt_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 314 uint32_t *data) 315 { 316 #if defined(INTRNG) 317 phandle_t msi_parent; 318 int err; 319 320 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 321 &msi_parent, NULL); 322 if (err != 0) 323 return (err); 324 return (intr_map_msi(pci, child, msi_parent, irq, addr, data)); 325 #else 326 return (ENXIO); 327 #endif 328 } 329 330 static int 331 generic_pcie_fdt_alloc_msix(device_t pci, device_t child, int *irq) 332 { 333 #if defined(INTRNG) 334 phandle_t msi_parent; 335 int err; 336 337 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 338 &msi_parent, NULL); 339 if (err != 0) 340 return (err); 341 return (intr_alloc_msix(pci, child, msi_parent, irq)); 342 #else 343 return (ENXIO); 344 #endif 345 } 346 347 static int 348 generic_pcie_fdt_release_msix(device_t pci, device_t child, int irq) 349 { 350 #if defined(INTRNG) 351 phandle_t msi_parent; 352 int err; 353 354 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 355 &msi_parent, NULL); 356 if (err != 0) 357 return (err); 358 return (intr_release_msix(pci, child, msi_parent, irq)); 359 #else 360 return (ENXIO); 361 #endif 362 } 363 364 int 365 generic_pcie_get_id(device_t pci, device_t child, enum pci_id_type type, 366 uintptr_t *id) 367 { 368 phandle_t node; 369 int err; 370 uint32_t rid; 371 uint16_t pci_rid; 372 373 if (type != PCI_ID_MSI) 374 return (pcib_get_id(pci, child, type, id)); 375 376 node = ofw_bus_get_node(pci); 377 pci_rid = pci_get_rid(child); 378 379 err = ofw_bus_msimap(node, pci_rid, NULL, &rid); 380 if (err != 0) 381 return (err); 382 *id = rid; 383 384 return (0); 385 } 386 387 static const struct ofw_bus_devinfo * 388 generic_pcie_ofw_get_devinfo(device_t bus, device_t child) 389 { 390 struct generic_pcie_fdt_softc *sc; 391 struct pci_ofw_devinfo *di; 392 uint8_t slot, func, busno; 393 394 sc = device_get_softc(bus); 395 slot = pci_get_slot(child); 396 func = pci_get_function(child); 397 busno = pci_get_bus(child); 398 399 STAILQ_FOREACH(di, &sc->pci_ofw_devlist, pci_ofw_link) 400 if (slot == di->slot && func == di->func && busno == di->bus) 401 return (&di->di_dinfo); 402 403 return (NULL); 404 } 405 406 /* Helper functions */ 407 408 static int 409 generic_pcie_ofw_bus_attach(device_t dev) 410 { 411 struct generic_pcie_fdt_softc *sc; 412 struct pci_ofw_devinfo *di; 413 phandle_t parent, node; 414 pcell_t reg[5]; 415 ssize_t len; 416 417 sc = device_get_softc(dev); 418 parent = ofw_bus_get_node(dev); 419 if (parent == 0) 420 return (0); 421 422 /* Iterate through all bus subordinates */ 423 for (node = OF_child(parent); node > 0; node = OF_peer(node)) { 424 len = OF_getencprop(node, "reg", reg, sizeof(reg)); 425 if (len != 5 * sizeof(pcell_t)) 426 continue; 427 428 /* Allocate and populate devinfo. */ 429 di = malloc(sizeof(*di), M_DEVBUF, M_WAITOK | M_ZERO); 430 if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) { 431 free(di, M_DEVBUF); 432 continue; 433 } 434 di->func = OFW_PCI_PHYS_HI_FUNCTION(reg[0]); 435 di->slot = OFW_PCI_PHYS_HI_DEVICE(reg[0]); 436 di->bus = OFW_PCI_PHYS_HI_BUS(reg[0]); 437 STAILQ_INSERT_TAIL(&sc->pci_ofw_devlist, di, pci_ofw_link); 438 } 439 440 return (0); 441 } 442 443 static device_method_t generic_pcie_fdt_methods[] = { 444 DEVMETHOD(device_probe, generic_pcie_fdt_probe), 445 DEVMETHOD(device_attach, pci_host_generic_attach), 446 DEVMETHOD(bus_alloc_resource, pci_host_generic_core_alloc_resource), 447 DEVMETHOD(bus_release_resource, pci_host_generic_core_release_resource), 448 449 /* pcib interface */ 450 DEVMETHOD(pcib_route_interrupt, generic_pcie_fdt_route_interrupt), 451 DEVMETHOD(pcib_alloc_msi, generic_pcie_fdt_alloc_msi), 452 DEVMETHOD(pcib_release_msi, generic_pcie_fdt_release_msi), 453 DEVMETHOD(pcib_alloc_msix, generic_pcie_fdt_alloc_msix), 454 DEVMETHOD(pcib_release_msix, generic_pcie_fdt_release_msix), 455 DEVMETHOD(pcib_map_msi, generic_pcie_fdt_map_msi), 456 DEVMETHOD(pcib_get_id, generic_pcie_get_id), 457 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), 458 459 DEVMETHOD(ofw_bus_get_devinfo, generic_pcie_ofw_get_devinfo), 460 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 461 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 462 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 463 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 464 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 465 466 DEVMETHOD_END 467 }; 468 469 DEFINE_CLASS_1(pcib, generic_pcie_fdt_driver, generic_pcie_fdt_methods, 470 sizeof(struct generic_pcie_fdt_softc), generic_pcie_core_driver); 471 472 static devclass_t generic_pcie_fdt_devclass; 473 474 DRIVER_MODULE(pcib, simplebus, generic_pcie_fdt_driver, 475 generic_pcie_fdt_devclass, 0, 0); 476 DRIVER_MODULE(pcib, ofwbus, generic_pcie_fdt_driver, generic_pcie_fdt_devclass, 477 0, 0); 478