1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * Copyright (c) 2014,2016 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This software was developed by Andrew Turner under 7 * the sponsorship of the FreeBSD Foundation. 8 * 9 * This software was developed by Semihalf under 10 * the sponsorship of the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* Generic ECAM PCIe driver FDT attachment */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include "opt_platform.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/rman.h> 48 49 #if defined(INTRNG) 50 #include <machine/intr.h> 51 #endif 52 53 #include <dev/ofw/openfirm.h> 54 #include <dev/ofw/ofw_bus.h> 55 #include <dev/ofw/ofw_bus_subr.h> 56 #include <dev/ofw/ofw_pci.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcib_private.h> 61 #include <dev/pci/pci_host_generic.h> 62 #include <dev/pci/pci_host_generic_fdt.h> 63 64 #include <machine/intr.h> 65 66 #include "pcib_if.h" 67 68 #define SPACE_CODE_SHIFT 24 69 #define SPACE_CODE_MASK 0x3 70 #define SPACE_CODE_IO_SPACE 0x1 71 #define PROPS_CELL_SIZE 1 72 #define PCI_ADDR_CELL_SIZE 2 73 74 /* OFW bus interface */ 75 struct generic_pcie_ofw_devinfo { 76 struct ofw_bus_devinfo di_dinfo; 77 struct resource_list di_rl; 78 }; 79 80 /* Forward prototypes */ 81 82 static int generic_pcie_fdt_probe(device_t dev); 83 static int parse_pci_mem_ranges(device_t, struct generic_pcie_core_softc *); 84 static int generic_pcie_fdt_release_resource(device_t dev, device_t child, 85 int type, int rid, struct resource *res); 86 static int generic_pcie_ofw_bus_attach(device_t); 87 static const struct ofw_bus_devinfo *generic_pcie_ofw_get_devinfo(device_t, 88 device_t); 89 90 static __inline void 91 get_addr_size_cells(phandle_t node, pcell_t *addr_cells, pcell_t *size_cells) 92 { 93 94 *addr_cells = 2; 95 /* Find address cells if present */ 96 OF_getencprop(node, "#address-cells", addr_cells, sizeof(*addr_cells)); 97 98 *size_cells = 2; 99 /* Find size cells if present */ 100 OF_getencprop(node, "#size-cells", size_cells, sizeof(*size_cells)); 101 } 102 103 static int 104 generic_pcie_fdt_probe(device_t dev) 105 { 106 107 if (!ofw_bus_status_okay(dev)) 108 return (ENXIO); 109 110 if (ofw_bus_is_compatible(dev, "pci-host-ecam-generic")) { 111 device_set_desc(dev, "Generic PCI host controller"); 112 return (BUS_PROBE_GENERIC); 113 } 114 if (ofw_bus_is_compatible(dev, "arm,gem5_pcie")) { 115 device_set_desc(dev, "GEM5 PCIe host controller"); 116 return (BUS_PROBE_DEFAULT); 117 } 118 119 return (ENXIO); 120 } 121 122 int 123 pci_host_generic_attach(device_t dev) 124 { 125 struct generic_pcie_fdt_softc *sc; 126 phandle_t node; 127 int error; 128 129 sc = device_get_softc(dev); 130 131 /* Retrieve 'ranges' property from FDT */ 132 if (bootverbose) 133 device_printf(dev, "parsing FDT for ECAM%d:\n", sc->base.ecam); 134 if (parse_pci_mem_ranges(dev, &sc->base)) 135 return (ENXIO); 136 137 /* Attach OFW bus */ 138 if (generic_pcie_ofw_bus_attach(dev) != 0) 139 return (ENXIO); 140 141 node = ofw_bus_get_node(dev); 142 if (sc->base.coherent == 0) { 143 sc->base.coherent = OF_hasprop(node, "dma-coherent"); 144 } 145 if (bootverbose) 146 device_printf(dev, "Bus is%s cache-coherent\n", 147 sc->base.coherent ? "" : " not"); 148 149 /* TODO parse FDT bus ranges */ 150 sc->base.bus_start = 0; 151 sc->base.bus_end = 0xFF; 152 error = pci_host_generic_core_attach(dev); 153 if (error != 0) 154 return (error); 155 156 ofw_bus_setup_iinfo(node, &sc->pci_iinfo, sizeof(cell_t)); 157 158 device_add_child(dev, "pci", -1); 159 return (bus_generic_attach(dev)); 160 } 161 162 static int 163 parse_pci_mem_ranges(device_t dev, struct generic_pcie_core_softc *sc) 164 { 165 pcell_t pci_addr_cells, parent_addr_cells; 166 pcell_t attributes, size_cells; 167 cell_t *base_ranges; 168 int nbase_ranges; 169 phandle_t node; 170 int i, j, k; 171 int tuple; 172 173 node = ofw_bus_get_node(dev); 174 175 OF_getencprop(node, "#address-cells", &pci_addr_cells, 176 sizeof(pci_addr_cells)); 177 OF_getencprop(node, "#size-cells", &size_cells, 178 sizeof(size_cells)); 179 OF_getencprop(OF_parent(node), "#address-cells", &parent_addr_cells, 180 sizeof(parent_addr_cells)); 181 182 if (parent_addr_cells > 2 || pci_addr_cells != 3 || size_cells > 2) { 183 device_printf(dev, 184 "Unexpected number of address or size cells in FDT\n"); 185 return (ENXIO); 186 } 187 188 nbase_ranges = OF_getproplen(node, "ranges"); 189 sc->nranges = nbase_ranges / sizeof(cell_t) / 190 (parent_addr_cells + pci_addr_cells + size_cells); 191 base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK); 192 OF_getencprop(node, "ranges", base_ranges, nbase_ranges); 193 194 for (i = 0, j = 0; i < sc->nranges; i++) { 195 attributes = (base_ranges[j++] >> SPACE_CODE_SHIFT) & \ 196 SPACE_CODE_MASK; 197 if (attributes == SPACE_CODE_IO_SPACE) { 198 sc->ranges[i].flags |= FLAG_TYPE_IO; 199 } else { 200 sc->ranges[i].flags |= FLAG_TYPE_MEM; 201 } 202 203 sc->ranges[i].pci_base = 0; 204 for (k = 0; k < (pci_addr_cells - 1); k++) { 205 sc->ranges[i].pci_base <<= 32; 206 sc->ranges[i].pci_base |= base_ranges[j++]; 207 } 208 sc->ranges[i].phys_base = 0; 209 for (k = 0; k < parent_addr_cells; k++) { 210 sc->ranges[i].phys_base <<= 32; 211 sc->ranges[i].phys_base |= base_ranges[j++]; 212 } 213 sc->ranges[i].size = 0; 214 for (k = 0; k < size_cells; k++) { 215 sc->ranges[i].size <<= 32; 216 sc->ranges[i].size |= base_ranges[j++]; 217 } 218 } 219 220 for (; i < MAX_RANGES_TUPLES; i++) { 221 /* zero-fill remaining tuples to mark empty elements in array */ 222 sc->ranges[i].pci_base = 0; 223 sc->ranges[i].phys_base = 0; 224 sc->ranges[i].size = 0; 225 } 226 227 if (bootverbose) { 228 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { 229 device_printf(dev, 230 "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx\n", 231 sc->ranges[tuple].pci_base, 232 sc->ranges[tuple].phys_base, 233 sc->ranges[tuple].size); 234 } 235 } 236 237 free(base_ranges, M_DEVBUF); 238 return (0); 239 } 240 241 static int 242 generic_pcie_fdt_route_interrupt(device_t bus, device_t dev, int pin) 243 { 244 struct generic_pcie_fdt_softc *sc; 245 struct ofw_pci_register reg; 246 uint32_t pintr, mintr[4]; 247 phandle_t iparent; 248 int intrcells; 249 250 sc = device_get_softc(bus); 251 pintr = pin; 252 253 bzero(®, sizeof(reg)); 254 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | 255 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | 256 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); 257 258 intrcells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), 259 &sc->pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr), 260 mintr, sizeof(mintr), &iparent); 261 if (intrcells) { 262 pintr = ofw_bus_map_intr(dev, iparent, intrcells, mintr); 263 return (pintr); 264 } 265 266 device_printf(bus, "could not route pin %d for device %d.%d\n", 267 pin, pci_get_slot(dev), pci_get_function(dev)); 268 return (PCI_INVALID_IRQ); 269 } 270 271 static int 272 generic_pcie_fdt_release_resource(device_t dev, device_t child, int type, 273 int rid, struct resource *res) 274 { 275 276 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 277 if (type == PCI_RES_BUS) { 278 return (pci_host_generic_core_release_resource(dev, child, type, 279 rid, res)); 280 } 281 #endif 282 283 /* For PCIe devices that do not have FDT nodes, use PCIB method */ 284 if ((int)ofw_bus_get_node(child) <= 0) { 285 return (pci_host_generic_core_release_resource(dev, child, type, 286 rid, res)); 287 } 288 289 /* For other devices use OFW method */ 290 return (bus_generic_release_resource(dev, child, type, rid, res)); 291 } 292 293 struct resource * 294 pci_host_generic_alloc_resource(device_t dev, device_t child, int type, 295 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 296 { 297 struct generic_pcie_fdt_softc *sc; 298 struct generic_pcie_ofw_devinfo *di; 299 struct resource_list_entry *rle; 300 int i; 301 302 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 303 if (type == PCI_RES_BUS) { 304 return (pci_host_generic_core_alloc_resource(dev, child, type, rid, 305 start, end, count, flags)); 306 } 307 #endif 308 309 /* For PCIe devices that do not have FDT nodes, use PCIB method */ 310 if ((int)ofw_bus_get_node(child) <= 0) 311 return (pci_host_generic_core_alloc_resource(dev, child, type, 312 rid, start, end, count, flags)); 313 314 /* For other devices use OFW method */ 315 sc = device_get_softc(dev); 316 317 if (RMAN_IS_DEFAULT_RANGE(start, end)) { 318 if ((di = device_get_ivars(child)) == NULL) 319 return (NULL); 320 if (type == SYS_RES_IOPORT) 321 type = SYS_RES_MEMORY; 322 323 /* Find defaults for this rid */ 324 rle = resource_list_find(&di->di_rl, type, *rid); 325 if (rle == NULL) 326 return (NULL); 327 328 start = rle->start; 329 end = rle->end; 330 count = rle->count; 331 } 332 333 if (type == SYS_RES_MEMORY) { 334 /* Remap through ranges property */ 335 for (i = 0; i < MAX_RANGES_TUPLES; i++) { 336 if (start >= sc->base.ranges[i].phys_base && 337 end < (sc->base.ranges[i].pci_base + 338 sc->base.ranges[i].size)) { 339 start -= sc->base.ranges[i].phys_base; 340 start += sc->base.ranges[i].pci_base; 341 end -= sc->base.ranges[i].phys_base; 342 end += sc->base.ranges[i].pci_base; 343 break; 344 } 345 } 346 347 if (i == MAX_RANGES_TUPLES) { 348 device_printf(dev, "Could not map resource " 349 "%#jx-%#jx\n", start, end); 350 return (NULL); 351 } 352 } 353 354 return (bus_generic_alloc_resource(dev, child, type, rid, start, 355 end, count, flags)); 356 } 357 358 static int 359 generic_pcie_fdt_alloc_msi(device_t pci, device_t child, int count, 360 int maxcount, int *irqs) 361 { 362 #if defined(INTRNG) 363 phandle_t msi_parent; 364 int err; 365 366 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 367 &msi_parent, NULL); 368 if (err != 0) 369 return (err); 370 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount, 371 irqs)); 372 #else 373 return (ENXIO); 374 #endif 375 } 376 377 static int 378 generic_pcie_fdt_release_msi(device_t pci, device_t child, int count, int *irqs) 379 { 380 #if defined(INTRNG) 381 phandle_t msi_parent; 382 int err; 383 384 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 385 &msi_parent, NULL); 386 if (err != 0) 387 return (err); 388 return (intr_release_msi(pci, child, msi_parent, count, irqs)); 389 #else 390 return (ENXIO); 391 #endif 392 } 393 394 static int 395 generic_pcie_fdt_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 396 uint32_t *data) 397 { 398 #if defined(INTRNG) 399 phandle_t msi_parent; 400 int err; 401 402 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 403 &msi_parent, NULL); 404 if (err != 0) 405 return (err); 406 return (intr_map_msi(pci, child, msi_parent, irq, addr, data)); 407 #else 408 return (ENXIO); 409 #endif 410 } 411 412 static int 413 generic_pcie_fdt_alloc_msix(device_t pci, device_t child, int *irq) 414 { 415 #if defined(INTRNG) 416 phandle_t msi_parent; 417 int err; 418 419 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 420 &msi_parent, NULL); 421 if (err != 0) 422 return (err); 423 return (intr_alloc_msix(pci, child, msi_parent, irq)); 424 #else 425 return (ENXIO); 426 #endif 427 } 428 429 static int 430 generic_pcie_fdt_release_msix(device_t pci, device_t child, int irq) 431 { 432 #if defined(INTRNG) 433 phandle_t msi_parent; 434 int err; 435 436 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 437 &msi_parent, NULL); 438 if (err != 0) 439 return (err); 440 return (intr_release_msix(pci, child, msi_parent, irq)); 441 #else 442 return (ENXIO); 443 #endif 444 } 445 446 int 447 generic_pcie_get_id(device_t pci, device_t child, enum pci_id_type type, 448 uintptr_t *id) 449 { 450 phandle_t node; 451 int err; 452 uint32_t rid; 453 uint16_t pci_rid; 454 455 if (type != PCI_ID_MSI) 456 return (pcib_get_id(pci, child, type, id)); 457 458 node = ofw_bus_get_node(pci); 459 pci_rid = pci_get_rid(child); 460 461 err = ofw_bus_msimap(node, pci_rid, NULL, &rid); 462 if (err != 0) 463 return (err); 464 *id = rid; 465 466 return (0); 467 } 468 469 static const struct ofw_bus_devinfo * 470 generic_pcie_ofw_get_devinfo(device_t bus __unused, device_t child) 471 { 472 struct generic_pcie_ofw_devinfo *di; 473 474 di = device_get_ivars(child); 475 return (&di->di_dinfo); 476 } 477 478 /* Helper functions */ 479 480 static int 481 generic_pcie_ofw_bus_attach(device_t dev) 482 { 483 struct generic_pcie_ofw_devinfo *di; 484 device_t child; 485 phandle_t parent, node; 486 pcell_t addr_cells, size_cells; 487 488 parent = ofw_bus_get_node(dev); 489 if (parent > 0) { 490 get_addr_size_cells(parent, &addr_cells, &size_cells); 491 /* Iterate through all bus subordinates */ 492 for (node = OF_child(parent); node > 0; node = OF_peer(node)) { 493 494 /* Allocate and populate devinfo. */ 495 di = malloc(sizeof(*di), M_DEVBUF, M_WAITOK | M_ZERO); 496 if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) { 497 free(di, M_DEVBUF); 498 continue; 499 } 500 501 /* Initialize and populate resource list. */ 502 resource_list_init(&di->di_rl); 503 ofw_bus_reg_to_rl(dev, node, addr_cells, size_cells, 504 &di->di_rl); 505 ofw_bus_intr_to_rl(dev, node, &di->di_rl, NULL); 506 507 /* Add newbus device for this FDT node */ 508 child = device_add_child(dev, NULL, -1); 509 if (child == NULL) { 510 resource_list_free(&di->di_rl); 511 ofw_bus_gen_destroy_devinfo(&di->di_dinfo); 512 free(di, M_DEVBUF); 513 continue; 514 } 515 516 device_set_ivars(child, di); 517 } 518 } 519 520 return (0); 521 } 522 523 static device_method_t generic_pcie_fdt_methods[] = { 524 DEVMETHOD(device_probe, generic_pcie_fdt_probe), 525 DEVMETHOD(device_attach, pci_host_generic_attach), 526 DEVMETHOD(bus_alloc_resource, pci_host_generic_alloc_resource), 527 DEVMETHOD(bus_release_resource, generic_pcie_fdt_release_resource), 528 529 /* pcib interface */ 530 DEVMETHOD(pcib_route_interrupt, generic_pcie_fdt_route_interrupt), 531 DEVMETHOD(pcib_alloc_msi, generic_pcie_fdt_alloc_msi), 532 DEVMETHOD(pcib_release_msi, generic_pcie_fdt_release_msi), 533 DEVMETHOD(pcib_alloc_msix, generic_pcie_fdt_alloc_msix), 534 DEVMETHOD(pcib_release_msix, generic_pcie_fdt_release_msix), 535 DEVMETHOD(pcib_map_msi, generic_pcie_fdt_map_msi), 536 DEVMETHOD(pcib_get_id, generic_pcie_get_id), 537 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), 538 539 /* ofw_bus interface */ 540 DEVMETHOD(ofw_bus_get_devinfo, generic_pcie_ofw_get_devinfo), 541 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 542 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 543 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 544 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 545 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 546 547 DEVMETHOD_END 548 }; 549 550 DEFINE_CLASS_1(pcib, generic_pcie_fdt_driver, generic_pcie_fdt_methods, 551 sizeof(struct generic_pcie_fdt_softc), generic_pcie_core_driver); 552 553 static devclass_t generic_pcie_fdt_devclass; 554 555 DRIVER_MODULE(pcib, simplebus, generic_pcie_fdt_driver, 556 generic_pcie_fdt_devclass, 0, 0); 557 DRIVER_MODULE(pcib, ofwbus, generic_pcie_fdt_driver, generic_pcie_fdt_devclass, 558 0, 0); 559