1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * Copyright (c) 2014,2016 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This software was developed by Andrew Turner under 7 * the sponsorship of the FreeBSD Foundation. 8 * 9 * This software was developed by Semihalf under 10 * the sponsorship of the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* Generic ECAM PCIe driver FDT attachment */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include "opt_platform.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/rman.h> 48 49 #if defined(INTRNG) 50 #include <machine/intr.h> 51 #endif 52 53 #include <dev/ofw/openfirm.h> 54 #include <dev/ofw/ofw_bus.h> 55 #include <dev/ofw/ofw_bus_subr.h> 56 #include <dev/ofw/ofw_pci.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcib_private.h> 61 #include <dev/pci/pci_host_generic.h> 62 #include <dev/pci/pci_host_generic_fdt.h> 63 64 #include <machine/intr.h> 65 66 #include "pcib_if.h" 67 68 #define SPACE_CODE_SHIFT 24 69 #define SPACE_CODE_MASK 0x3 70 #define SPACE_CODE_IO_SPACE 0x1 71 #define PROPS_CELL_SIZE 1 72 #define PCI_ADDR_CELL_SIZE 2 73 74 /* OFW bus interface */ 75 struct generic_pcie_ofw_devinfo { 76 struct ofw_bus_devinfo di_dinfo; 77 struct resource_list di_rl; 78 }; 79 80 /* Forward prototypes */ 81 82 static int generic_pcie_fdt_probe(device_t dev); 83 static int parse_pci_mem_ranges(device_t, struct generic_pcie_core_softc *); 84 static int generic_pcie_fdt_release_resource(device_t dev, device_t child, 85 int type, int rid, struct resource *res); 86 static int generic_pcie_ofw_bus_attach(device_t); 87 static const struct ofw_bus_devinfo *generic_pcie_ofw_get_devinfo(device_t, 88 device_t); 89 90 static __inline void 91 get_addr_size_cells(phandle_t node, pcell_t *addr_cells, pcell_t *size_cells) 92 { 93 94 *addr_cells = 2; 95 /* Find address cells if present */ 96 OF_getencprop(node, "#address-cells", addr_cells, sizeof(*addr_cells)); 97 98 *size_cells = 2; 99 /* Find size cells if present */ 100 OF_getencprop(node, "#size-cells", size_cells, sizeof(*size_cells)); 101 } 102 103 static int 104 generic_pcie_fdt_probe(device_t dev) 105 { 106 107 if (!ofw_bus_status_okay(dev)) 108 return (ENXIO); 109 110 if (ofw_bus_is_compatible(dev, "pci-host-ecam-generic")) { 111 device_set_desc(dev, "Generic PCI host controller"); 112 return (BUS_PROBE_GENERIC); 113 } 114 if (ofw_bus_is_compatible(dev, "arm,gem5_pcie")) { 115 device_set_desc(dev, "GEM5 PCIe host controller"); 116 return (BUS_PROBE_DEFAULT); 117 } 118 119 return (ENXIO); 120 } 121 122 int 123 pci_host_generic_attach(device_t dev) 124 { 125 struct generic_pcie_fdt_softc *sc; 126 uint64_t phys_base; 127 uint64_t pci_base; 128 uint64_t size; 129 phandle_t node; 130 int error; 131 int tuple; 132 133 sc = device_get_softc(dev); 134 135 /* Retrieve 'ranges' property from FDT */ 136 if (bootverbose) 137 device_printf(dev, "parsing FDT for ECAM%d:\n", sc->base.ecam); 138 if (parse_pci_mem_ranges(dev, &sc->base)) 139 return (ENXIO); 140 141 /* Attach OFW bus */ 142 if (generic_pcie_ofw_bus_attach(dev) != 0) 143 return (ENXIO); 144 145 node = ofw_bus_get_node(dev); 146 if (sc->base.coherent == 0) { 147 sc->base.coherent = OF_hasprop(node, "dma-coherent"); 148 } 149 if (bootverbose) 150 device_printf(dev, "Bus is%s cache-coherent\n", 151 sc->base.coherent ? "" : " not"); 152 153 /* TODO parse FDT bus ranges */ 154 sc->base.bus_start = 0; 155 sc->base.bus_end = 0xFF; 156 error = pci_host_generic_core_attach(dev); 157 if (error != 0) 158 return (error); 159 160 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { 161 phys_base = sc->base.ranges[tuple].phys_base; 162 pci_base = sc->base.ranges[tuple].pci_base; 163 size = sc->base.ranges[tuple].size; 164 if (phys_base == 0 || size == 0) 165 continue; /* empty range element */ 166 if (sc->base.ranges[tuple].flags & FLAG_MEM) { 167 error = rman_manage_region(&sc->base.mem_rman, 168 pci_base, pci_base + size - 1); 169 } else if (sc->base.ranges[tuple].flags & FLAG_IO) { 170 error = rman_manage_region(&sc->base.io_rman, 171 pci_base, pci_base + size - 1); 172 } else 173 continue; 174 if (error) { 175 device_printf(dev, "rman_manage_region() failed." 176 "error = %d\n", error); 177 rman_fini(&sc->base.mem_rman); 178 return (error); 179 } 180 } 181 182 ofw_bus_setup_iinfo(node, &sc->pci_iinfo, sizeof(cell_t)); 183 184 device_add_child(dev, "pci", -1); 185 return (bus_generic_attach(dev)); 186 } 187 188 static int 189 parse_pci_mem_ranges(device_t dev, struct generic_pcie_core_softc *sc) 190 { 191 pcell_t pci_addr_cells, parent_addr_cells; 192 pcell_t attributes, size_cells; 193 cell_t *base_ranges; 194 int nbase_ranges; 195 phandle_t node; 196 int i, j, k; 197 int tuple; 198 199 node = ofw_bus_get_node(dev); 200 201 OF_getencprop(node, "#address-cells", &pci_addr_cells, 202 sizeof(pci_addr_cells)); 203 OF_getencprop(node, "#size-cells", &size_cells, 204 sizeof(size_cells)); 205 OF_getencprop(OF_parent(node), "#address-cells", &parent_addr_cells, 206 sizeof(parent_addr_cells)); 207 208 if (parent_addr_cells > 2 || pci_addr_cells != 3 || size_cells > 2) { 209 device_printf(dev, 210 "Unexpected number of address or size cells in FDT\n"); 211 return (ENXIO); 212 } 213 214 nbase_ranges = OF_getproplen(node, "ranges"); 215 sc->nranges = nbase_ranges / sizeof(cell_t) / 216 (parent_addr_cells + pci_addr_cells + size_cells); 217 base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK); 218 OF_getencprop(node, "ranges", base_ranges, nbase_ranges); 219 220 for (i = 0, j = 0; i < sc->nranges; i++) { 221 attributes = (base_ranges[j++] >> SPACE_CODE_SHIFT) & \ 222 SPACE_CODE_MASK; 223 if (attributes == SPACE_CODE_IO_SPACE) { 224 sc->ranges[i].flags |= FLAG_IO; 225 } else { 226 sc->ranges[i].flags |= FLAG_MEM; 227 } 228 229 sc->ranges[i].pci_base = 0; 230 for (k = 0; k < (pci_addr_cells - 1); k++) { 231 sc->ranges[i].pci_base <<= 32; 232 sc->ranges[i].pci_base |= base_ranges[j++]; 233 } 234 sc->ranges[i].phys_base = 0; 235 for (k = 0; k < parent_addr_cells; k++) { 236 sc->ranges[i].phys_base <<= 32; 237 sc->ranges[i].phys_base |= base_ranges[j++]; 238 } 239 sc->ranges[i].size = 0; 240 for (k = 0; k < size_cells; k++) { 241 sc->ranges[i].size <<= 32; 242 sc->ranges[i].size |= base_ranges[j++]; 243 } 244 } 245 246 for (; i < MAX_RANGES_TUPLES; i++) { 247 /* zero-fill remaining tuples to mark empty elements in array */ 248 sc->ranges[i].pci_base = 0; 249 sc->ranges[i].phys_base = 0; 250 sc->ranges[i].size = 0; 251 } 252 253 if (bootverbose) { 254 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { 255 device_printf(dev, 256 "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx\n", 257 sc->ranges[tuple].pci_base, 258 sc->ranges[tuple].phys_base, 259 sc->ranges[tuple].size); 260 } 261 } 262 263 free(base_ranges, M_DEVBUF); 264 return (0); 265 } 266 267 static int 268 generic_pcie_fdt_route_interrupt(device_t bus, device_t dev, int pin) 269 { 270 struct generic_pcie_fdt_softc *sc; 271 struct ofw_pci_register reg; 272 uint32_t pintr, mintr[4]; 273 phandle_t iparent; 274 int intrcells; 275 276 sc = device_get_softc(bus); 277 pintr = pin; 278 279 bzero(®, sizeof(reg)); 280 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | 281 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | 282 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); 283 284 intrcells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), 285 &sc->pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr), 286 mintr, sizeof(mintr), &iparent); 287 if (intrcells) { 288 pintr = ofw_bus_map_intr(dev, iparent, intrcells, mintr); 289 return (pintr); 290 } 291 292 device_printf(bus, "could not route pin %d for device %d.%d\n", 293 pin, pci_get_slot(dev), pci_get_function(dev)); 294 return (PCI_INVALID_IRQ); 295 } 296 297 static int 298 generic_pcie_fdt_release_resource(device_t dev, device_t child, int type, 299 int rid, struct resource *res) 300 { 301 302 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 303 if (type == PCI_RES_BUS) { 304 return (pci_host_generic_core_release_resource(dev, child, type, 305 rid, res)); 306 } 307 #endif 308 309 /* For PCIe devices that do not have FDT nodes, use PCIB method */ 310 if ((int)ofw_bus_get_node(child) <= 0) { 311 return (pci_host_generic_core_release_resource(dev, child, type, 312 rid, res)); 313 } 314 315 /* For other devices use OFW method */ 316 return (bus_generic_release_resource(dev, child, type, rid, res)); 317 } 318 319 struct resource * 320 pci_host_generic_alloc_resource(device_t dev, device_t child, int type, 321 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 322 { 323 struct generic_pcie_fdt_softc *sc; 324 struct generic_pcie_ofw_devinfo *di; 325 struct resource_list_entry *rle; 326 int i; 327 328 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 329 if (type == PCI_RES_BUS) { 330 return (pci_host_generic_core_alloc_resource(dev, child, type, rid, 331 start, end, count, flags)); 332 } 333 #endif 334 335 /* For PCIe devices that do not have FDT nodes, use PCIB method */ 336 if ((int)ofw_bus_get_node(child) <= 0) 337 return (pci_host_generic_core_alloc_resource(dev, child, type, 338 rid, start, end, count, flags)); 339 340 /* For other devices use OFW method */ 341 sc = device_get_softc(dev); 342 343 if (RMAN_IS_DEFAULT_RANGE(start, end)) { 344 if ((di = device_get_ivars(child)) == NULL) 345 return (NULL); 346 if (type == SYS_RES_IOPORT) 347 type = SYS_RES_MEMORY; 348 349 /* Find defaults for this rid */ 350 rle = resource_list_find(&di->di_rl, type, *rid); 351 if (rle == NULL) 352 return (NULL); 353 354 start = rle->start; 355 end = rle->end; 356 count = rle->count; 357 } 358 359 if (type == SYS_RES_MEMORY) { 360 /* Remap through ranges property */ 361 for (i = 0; i < MAX_RANGES_TUPLES; i++) { 362 if (start >= sc->base.ranges[i].phys_base && 363 end < (sc->base.ranges[i].pci_base + 364 sc->base.ranges[i].size)) { 365 start -= sc->base.ranges[i].phys_base; 366 start += sc->base.ranges[i].pci_base; 367 end -= sc->base.ranges[i].phys_base; 368 end += sc->base.ranges[i].pci_base; 369 break; 370 } 371 } 372 373 if (i == MAX_RANGES_TUPLES) { 374 device_printf(dev, "Could not map resource " 375 "%#jx-%#jx\n", start, end); 376 return (NULL); 377 } 378 } 379 380 return (bus_generic_alloc_resource(dev, child, type, rid, start, 381 end, count, flags)); 382 } 383 384 static int 385 generic_pcie_fdt_alloc_msi(device_t pci, device_t child, int count, 386 int maxcount, int *irqs) 387 { 388 #if defined(INTRNG) 389 phandle_t msi_parent; 390 int err; 391 392 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 393 &msi_parent, NULL); 394 if (err != 0) 395 return (err); 396 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount, 397 irqs)); 398 #else 399 return (ENXIO); 400 #endif 401 } 402 403 static int 404 generic_pcie_fdt_release_msi(device_t pci, device_t child, int count, int *irqs) 405 { 406 #if defined(INTRNG) 407 phandle_t msi_parent; 408 int err; 409 410 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 411 &msi_parent, NULL); 412 if (err != 0) 413 return (err); 414 return (intr_release_msi(pci, child, msi_parent, count, irqs)); 415 #else 416 return (ENXIO); 417 #endif 418 } 419 420 static int 421 generic_pcie_fdt_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 422 uint32_t *data) 423 { 424 #if defined(INTRNG) 425 phandle_t msi_parent; 426 int err; 427 428 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 429 &msi_parent, NULL); 430 if (err != 0) 431 return (err); 432 return (intr_map_msi(pci, child, msi_parent, irq, addr, data)); 433 #else 434 return (ENXIO); 435 #endif 436 } 437 438 static int 439 generic_pcie_fdt_alloc_msix(device_t pci, device_t child, int *irq) 440 { 441 #if defined(INTRNG) 442 phandle_t msi_parent; 443 int err; 444 445 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 446 &msi_parent, NULL); 447 if (err != 0) 448 return (err); 449 return (intr_alloc_msix(pci, child, msi_parent, irq)); 450 #else 451 return (ENXIO); 452 #endif 453 } 454 455 static int 456 generic_pcie_fdt_release_msix(device_t pci, device_t child, int irq) 457 { 458 #if defined(INTRNG) 459 phandle_t msi_parent; 460 int err; 461 462 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 463 &msi_parent, NULL); 464 if (err != 0) 465 return (err); 466 return (intr_release_msix(pci, child, msi_parent, irq)); 467 #else 468 return (ENXIO); 469 #endif 470 } 471 472 int 473 generic_pcie_get_id(device_t pci, device_t child, enum pci_id_type type, 474 uintptr_t *id) 475 { 476 phandle_t node; 477 int err; 478 uint32_t rid; 479 uint16_t pci_rid; 480 481 if (type != PCI_ID_MSI) 482 return (pcib_get_id(pci, child, type, id)); 483 484 node = ofw_bus_get_node(pci); 485 pci_rid = pci_get_rid(child); 486 487 err = ofw_bus_msimap(node, pci_rid, NULL, &rid); 488 if (err != 0) 489 return (err); 490 *id = rid; 491 492 return (0); 493 } 494 495 static const struct ofw_bus_devinfo * 496 generic_pcie_ofw_get_devinfo(device_t bus __unused, device_t child) 497 { 498 struct generic_pcie_ofw_devinfo *di; 499 500 di = device_get_ivars(child); 501 return (&di->di_dinfo); 502 } 503 504 /* Helper functions */ 505 506 static int 507 generic_pcie_ofw_bus_attach(device_t dev) 508 { 509 struct generic_pcie_ofw_devinfo *di; 510 device_t child; 511 phandle_t parent, node; 512 pcell_t addr_cells, size_cells; 513 514 parent = ofw_bus_get_node(dev); 515 if (parent > 0) { 516 get_addr_size_cells(parent, &addr_cells, &size_cells); 517 /* Iterate through all bus subordinates */ 518 for (node = OF_child(parent); node > 0; node = OF_peer(node)) { 519 520 /* Allocate and populate devinfo. */ 521 di = malloc(sizeof(*di), M_DEVBUF, M_WAITOK | M_ZERO); 522 if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) { 523 free(di, M_DEVBUF); 524 continue; 525 } 526 527 /* Initialize and populate resource list. */ 528 resource_list_init(&di->di_rl); 529 ofw_bus_reg_to_rl(dev, node, addr_cells, size_cells, 530 &di->di_rl); 531 ofw_bus_intr_to_rl(dev, node, &di->di_rl, NULL); 532 533 /* Add newbus device for this FDT node */ 534 child = device_add_child(dev, NULL, -1); 535 if (child == NULL) { 536 resource_list_free(&di->di_rl); 537 ofw_bus_gen_destroy_devinfo(&di->di_dinfo); 538 free(di, M_DEVBUF); 539 continue; 540 } 541 542 device_set_ivars(child, di); 543 } 544 } 545 546 return (0); 547 } 548 549 static device_method_t generic_pcie_fdt_methods[] = { 550 DEVMETHOD(device_probe, generic_pcie_fdt_probe), 551 DEVMETHOD(device_attach, pci_host_generic_attach), 552 DEVMETHOD(bus_alloc_resource, pci_host_generic_alloc_resource), 553 DEVMETHOD(bus_release_resource, generic_pcie_fdt_release_resource), 554 555 /* pcib interface */ 556 DEVMETHOD(pcib_route_interrupt, generic_pcie_fdt_route_interrupt), 557 DEVMETHOD(pcib_alloc_msi, generic_pcie_fdt_alloc_msi), 558 DEVMETHOD(pcib_release_msi, generic_pcie_fdt_release_msi), 559 DEVMETHOD(pcib_alloc_msix, generic_pcie_fdt_alloc_msix), 560 DEVMETHOD(pcib_release_msix, generic_pcie_fdt_release_msix), 561 DEVMETHOD(pcib_map_msi, generic_pcie_fdt_map_msi), 562 DEVMETHOD(pcib_get_id, generic_pcie_get_id), 563 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), 564 565 /* ofw_bus interface */ 566 DEVMETHOD(ofw_bus_get_devinfo, generic_pcie_ofw_get_devinfo), 567 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 568 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 569 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 570 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 571 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 572 573 DEVMETHOD_END 574 }; 575 576 DEFINE_CLASS_1(pcib, generic_pcie_fdt_driver, generic_pcie_fdt_methods, 577 sizeof(struct generic_pcie_fdt_softc), generic_pcie_core_driver); 578 579 static devclass_t generic_pcie_fdt_devclass; 580 581 DRIVER_MODULE(pcib, simplebus, generic_pcie_fdt_driver, 582 generic_pcie_fdt_devclass, 0, 0); 583 DRIVER_MODULE(pcib, ofwbus, generic_pcie_fdt_driver, generic_pcie_fdt_devclass, 584 0, 0); 585