1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * Copyright (c) 2014,2016 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This software was developed by Andrew Turner under 7 * the sponsorship of the FreeBSD Foundation. 8 * 9 * This software was developed by Semihalf under 10 * the sponsorship of the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* Generic ECAM PCIe driver FDT attachment */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include "opt_platform.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/rman.h> 48 49 #if defined(INTRNG) 50 #include <machine/intr.h> 51 #endif 52 53 #include <dev/ofw/openfirm.h> 54 #include <dev/ofw/ofw_bus.h> 55 #include <dev/ofw/ofw_bus_subr.h> 56 #include <dev/ofw/ofw_pci.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcib_private.h> 61 #include <dev/pci/pci_host_generic.h> 62 #include <dev/pci/pci_host_generic_fdt.h> 63 64 #include <machine/intr.h> 65 66 #include "pcib_if.h" 67 68 #define SPACE_CODE_SHIFT 24 69 #define SPACE_CODE_MASK 0x3 70 #define SPACE_CODE_IO_SPACE 0x1 71 #define PROPS_CELL_SIZE 1 72 #define PCI_ADDR_CELL_SIZE 2 73 74 struct pci_ofw_devinfo { 75 STAILQ_ENTRY(pci_ofw_devinfo) pci_ofw_link; 76 struct ofw_bus_devinfo di_dinfo; 77 uint8_t slot; 78 uint8_t func; 79 uint8_t bus; 80 }; 81 82 /* Forward prototypes */ 83 84 static int generic_pcie_fdt_probe(device_t dev); 85 static int parse_pci_mem_ranges(device_t, struct generic_pcie_core_softc *); 86 static int generic_pcie_ofw_bus_attach(device_t); 87 static const struct ofw_bus_devinfo *generic_pcie_ofw_get_devinfo(device_t, 88 device_t); 89 90 static int 91 generic_pcie_fdt_probe(device_t dev) 92 { 93 94 if (!ofw_bus_status_okay(dev)) 95 return (ENXIO); 96 97 if (ofw_bus_is_compatible(dev, "pci-host-ecam-generic")) { 98 device_set_desc(dev, "Generic PCI host controller"); 99 return (BUS_PROBE_GENERIC); 100 } 101 if (ofw_bus_is_compatible(dev, "arm,gem5_pcie")) { 102 device_set_desc(dev, "GEM5 PCIe host controller"); 103 return (BUS_PROBE_DEFAULT); 104 } 105 106 return (ENXIO); 107 } 108 109 int 110 pci_host_generic_setup_fdt(device_t dev) 111 { 112 struct generic_pcie_fdt_softc *sc; 113 phandle_t node; 114 int error; 115 116 sc = device_get_softc(dev); 117 118 STAILQ_INIT(&sc->pci_ofw_devlist); 119 120 /* Retrieve 'ranges' property from FDT */ 121 if (bootverbose) 122 device_printf(dev, "parsing FDT for ECAM%d:\n", sc->base.ecam); 123 if (parse_pci_mem_ranges(dev, &sc->base)) 124 return (ENXIO); 125 126 /* Attach OFW bus */ 127 if (generic_pcie_ofw_bus_attach(dev) != 0) 128 return (ENXIO); 129 130 node = ofw_bus_get_node(dev); 131 if (sc->base.coherent == 0) { 132 sc->base.coherent = OF_hasprop(node, "dma-coherent"); 133 } 134 if (bootverbose) 135 device_printf(dev, "Bus is%s cache-coherent\n", 136 sc->base.coherent ? "" : " not"); 137 138 /* TODO parse FDT bus ranges */ 139 sc->base.bus_start = 0; 140 sc->base.bus_end = 0xFF; 141 142 /* 143 * ofw_pcib uses device unit as PCI domain number. 144 * Do the same. Some boards have multiple RCs handled 145 * by different drivers, this ensures that there are 146 * no collisions. 147 */ 148 sc->base.ecam = device_get_unit(dev); 149 150 error = pci_host_generic_core_attach(dev); 151 if (error != 0) 152 return (error); 153 154 if (ofw_bus_is_compatible(dev, "marvell,armada8k-pcie-ecam") || 155 ofw_bus_is_compatible(dev, "socionext,synquacer-pcie-ecam") || 156 ofw_bus_is_compatible(dev, "snps,dw-pcie-ecam")) { 157 device_set_desc(dev, "Synopsys DesignWare PCIe Controller"); 158 sc->base.quirks |= PCIE_ECAM_DESIGNWARE_QUIRK; 159 } 160 161 ofw_bus_setup_iinfo(node, &sc->pci_iinfo, sizeof(cell_t)); 162 163 return (0); 164 } 165 166 int 167 pci_host_generic_attach(device_t dev) 168 { 169 struct generic_pcie_fdt_softc *sc; 170 int error; 171 172 sc = device_get_softc(dev); 173 174 error = pci_host_generic_setup_fdt(dev); 175 if (error != 0) 176 return (error); 177 178 device_add_child(dev, "pci", -1); 179 return (bus_generic_attach(dev)); 180 } 181 182 static int 183 parse_pci_mem_ranges(device_t dev, struct generic_pcie_core_softc *sc) 184 { 185 pcell_t pci_addr_cells, parent_addr_cells; 186 pcell_t attributes, size_cells; 187 cell_t *base_ranges; 188 int nbase_ranges; 189 phandle_t node; 190 int i, j, k; 191 int tuple; 192 193 node = ofw_bus_get_node(dev); 194 195 OF_getencprop(node, "#address-cells", &pci_addr_cells, 196 sizeof(pci_addr_cells)); 197 OF_getencprop(node, "#size-cells", &size_cells, 198 sizeof(size_cells)); 199 OF_getencprop(OF_parent(node), "#address-cells", &parent_addr_cells, 200 sizeof(parent_addr_cells)); 201 202 if (parent_addr_cells > 2 || pci_addr_cells != 3 || size_cells > 2) { 203 device_printf(dev, 204 "Unexpected number of address or size cells in FDT\n"); 205 return (ENXIO); 206 } 207 208 nbase_ranges = OF_getproplen(node, "ranges"); 209 sc->nranges = nbase_ranges / sizeof(cell_t) / 210 (parent_addr_cells + pci_addr_cells + size_cells); 211 base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK); 212 OF_getencprop(node, "ranges", base_ranges, nbase_ranges); 213 214 for (i = 0, j = 0; i < sc->nranges; i++) { 215 attributes = (base_ranges[j++] >> SPACE_CODE_SHIFT) & \ 216 SPACE_CODE_MASK; 217 if (attributes == SPACE_CODE_IO_SPACE) { 218 sc->ranges[i].flags |= FLAG_TYPE_IO; 219 } else { 220 sc->ranges[i].flags |= FLAG_TYPE_MEM; 221 } 222 223 sc->ranges[i].pci_base = 0; 224 for (k = 0; k < (pci_addr_cells - 1); k++) { 225 sc->ranges[i].pci_base <<= 32; 226 sc->ranges[i].pci_base |= base_ranges[j++]; 227 } 228 sc->ranges[i].phys_base = 0; 229 for (k = 0; k < parent_addr_cells; k++) { 230 sc->ranges[i].phys_base <<= 32; 231 sc->ranges[i].phys_base |= base_ranges[j++]; 232 } 233 sc->ranges[i].size = 0; 234 for (k = 0; k < size_cells; k++) { 235 sc->ranges[i].size <<= 32; 236 sc->ranges[i].size |= base_ranges[j++]; 237 } 238 } 239 240 for (; i < MAX_RANGES_TUPLES; i++) { 241 /* zero-fill remaining tuples to mark empty elements in array */ 242 sc->ranges[i].pci_base = 0; 243 sc->ranges[i].phys_base = 0; 244 sc->ranges[i].size = 0; 245 } 246 247 if (bootverbose) { 248 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { 249 device_printf(dev, 250 "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx\n", 251 sc->ranges[tuple].pci_base, 252 sc->ranges[tuple].phys_base, 253 sc->ranges[tuple].size); 254 } 255 } 256 257 free(base_ranges, M_DEVBUF); 258 return (0); 259 } 260 261 static int 262 generic_pcie_fdt_route_interrupt(device_t bus, device_t dev, int pin) 263 { 264 struct generic_pcie_fdt_softc *sc; 265 struct ofw_pci_register reg; 266 uint32_t pintr, mintr[4]; 267 phandle_t iparent; 268 int intrcells; 269 270 sc = device_get_softc(bus); 271 pintr = pin; 272 273 bzero(®, sizeof(reg)); 274 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | 275 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | 276 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); 277 278 intrcells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), 279 &sc->pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr), 280 mintr, sizeof(mintr), &iparent); 281 if (intrcells) { 282 pintr = ofw_bus_map_intr(dev, iparent, intrcells, mintr); 283 return (pintr); 284 } 285 286 device_printf(bus, "could not route pin %d for device %d.%d\n", 287 pin, pci_get_slot(dev), pci_get_function(dev)); 288 return (PCI_INVALID_IRQ); 289 } 290 291 static int 292 generic_pcie_fdt_alloc_msi(device_t pci, device_t child, int count, 293 int maxcount, int *irqs) 294 { 295 #if defined(INTRNG) 296 phandle_t msi_parent; 297 int err; 298 299 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 300 &msi_parent, NULL); 301 if (err != 0) 302 return (err); 303 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount, 304 irqs)); 305 #else 306 return (ENXIO); 307 #endif 308 } 309 310 static int 311 generic_pcie_fdt_release_msi(device_t pci, device_t child, int count, int *irqs) 312 { 313 #if defined(INTRNG) 314 phandle_t msi_parent; 315 int err; 316 317 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 318 &msi_parent, NULL); 319 if (err != 0) 320 return (err); 321 return (intr_release_msi(pci, child, msi_parent, count, irqs)); 322 #else 323 return (ENXIO); 324 #endif 325 } 326 327 static int 328 generic_pcie_fdt_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 329 uint32_t *data) 330 { 331 #if defined(INTRNG) 332 phandle_t msi_parent; 333 int err; 334 335 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 336 &msi_parent, NULL); 337 if (err != 0) 338 return (err); 339 return (intr_map_msi(pci, child, msi_parent, irq, addr, data)); 340 #else 341 return (ENXIO); 342 #endif 343 } 344 345 static int 346 generic_pcie_fdt_alloc_msix(device_t pci, device_t child, int *irq) 347 { 348 #if defined(INTRNG) 349 phandle_t msi_parent; 350 int err; 351 352 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 353 &msi_parent, NULL); 354 if (err != 0) 355 return (err); 356 return (intr_alloc_msix(pci, child, msi_parent, irq)); 357 #else 358 return (ENXIO); 359 #endif 360 } 361 362 static int 363 generic_pcie_fdt_release_msix(device_t pci, device_t child, int irq) 364 { 365 #if defined(INTRNG) 366 phandle_t msi_parent; 367 int err; 368 369 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 370 &msi_parent, NULL); 371 if (err != 0) 372 return (err); 373 return (intr_release_msix(pci, child, msi_parent, irq)); 374 #else 375 return (ENXIO); 376 #endif 377 } 378 379 int 380 generic_pcie_get_id(device_t pci, device_t child, enum pci_id_type type, 381 uintptr_t *id) 382 { 383 phandle_t node; 384 int err; 385 uint32_t rid; 386 uint16_t pci_rid; 387 388 if (type != PCI_ID_MSI) 389 return (pcib_get_id(pci, child, type, id)); 390 391 node = ofw_bus_get_node(pci); 392 pci_rid = pci_get_rid(child); 393 394 err = ofw_bus_msimap(node, pci_rid, NULL, &rid); 395 if (err != 0) 396 return (err); 397 *id = rid; 398 399 return (0); 400 } 401 402 static const struct ofw_bus_devinfo * 403 generic_pcie_ofw_get_devinfo(device_t bus, device_t child) 404 { 405 struct generic_pcie_fdt_softc *sc; 406 struct pci_ofw_devinfo *di; 407 uint8_t slot, func, busno; 408 409 sc = device_get_softc(bus); 410 slot = pci_get_slot(child); 411 func = pci_get_function(child); 412 busno = pci_get_bus(child); 413 414 STAILQ_FOREACH(di, &sc->pci_ofw_devlist, pci_ofw_link) 415 if (slot == di->slot && func == di->func && busno == di->bus) 416 return (&di->di_dinfo); 417 418 return (NULL); 419 } 420 421 /* Helper functions */ 422 423 static int 424 generic_pcie_ofw_bus_attach(device_t dev) 425 { 426 struct generic_pcie_fdt_softc *sc; 427 struct pci_ofw_devinfo *di; 428 phandle_t parent, node; 429 pcell_t reg[5]; 430 ssize_t len; 431 432 sc = device_get_softc(dev); 433 parent = ofw_bus_get_node(dev); 434 if (parent == 0) 435 return (0); 436 437 /* Iterate through all bus subordinates */ 438 for (node = OF_child(parent); node > 0; node = OF_peer(node)) { 439 len = OF_getencprop(node, "reg", reg, sizeof(reg)); 440 if (len != 5 * sizeof(pcell_t)) 441 continue; 442 443 /* Allocate and populate devinfo. */ 444 di = malloc(sizeof(*di), M_DEVBUF, M_WAITOK | M_ZERO); 445 if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) { 446 free(di, M_DEVBUF); 447 continue; 448 } 449 di->func = OFW_PCI_PHYS_HI_FUNCTION(reg[0]); 450 di->slot = OFW_PCI_PHYS_HI_DEVICE(reg[0]); 451 di->bus = OFW_PCI_PHYS_HI_BUS(reg[0]); 452 STAILQ_INSERT_TAIL(&sc->pci_ofw_devlist, di, pci_ofw_link); 453 } 454 455 return (0); 456 } 457 458 static device_method_t generic_pcie_fdt_methods[] = { 459 DEVMETHOD(device_probe, generic_pcie_fdt_probe), 460 DEVMETHOD(device_attach, pci_host_generic_attach), 461 DEVMETHOD(bus_alloc_resource, pci_host_generic_core_alloc_resource), 462 DEVMETHOD(bus_release_resource, pci_host_generic_core_release_resource), 463 464 /* pcib interface */ 465 DEVMETHOD(pcib_route_interrupt, generic_pcie_fdt_route_interrupt), 466 DEVMETHOD(pcib_alloc_msi, generic_pcie_fdt_alloc_msi), 467 DEVMETHOD(pcib_release_msi, generic_pcie_fdt_release_msi), 468 DEVMETHOD(pcib_alloc_msix, generic_pcie_fdt_alloc_msix), 469 DEVMETHOD(pcib_release_msix, generic_pcie_fdt_release_msix), 470 DEVMETHOD(pcib_map_msi, generic_pcie_fdt_map_msi), 471 DEVMETHOD(pcib_get_id, generic_pcie_get_id), 472 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), 473 474 DEVMETHOD(ofw_bus_get_devinfo, generic_pcie_ofw_get_devinfo), 475 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 476 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 477 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 478 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 479 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 480 481 DEVMETHOD_END 482 }; 483 484 DEFINE_CLASS_1(pcib, generic_pcie_fdt_driver, generic_pcie_fdt_methods, 485 sizeof(struct generic_pcie_fdt_softc), generic_pcie_core_driver); 486 487 static devclass_t generic_pcie_fdt_devclass; 488 489 DRIVER_MODULE(pcib, simplebus, generic_pcie_fdt_driver, 490 generic_pcie_fdt_devclass, 0, 0); 491 DRIVER_MODULE(pcib, ofwbus, generic_pcie_fdt_driver, generic_pcie_fdt_devclass, 492 0, 0); 493