1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * Copyright (c) 2014,2016 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This software was developed by Andrew Turner under 7 * the sponsorship of the FreeBSD Foundation. 8 * 9 * This software was developed by Semihalf under 10 * the sponsorship of the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* Generic ECAM PCIe driver FDT attachment */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include "opt_platform.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/rman.h> 48 49 #if defined(INTRNG) 50 #include <machine/intr.h> 51 #endif 52 53 #include <dev/ofw/openfirm.h> 54 #include <dev/ofw/ofw_bus.h> 55 #include <dev/ofw/ofw_bus_subr.h> 56 #include <dev/ofw/ofw_pci.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcib_private.h> 61 #include <dev/pci/pci_host_generic.h> 62 #include <dev/pci/pci_host_generic_fdt.h> 63 64 #include <machine/intr.h> 65 66 #include "pcib_if.h" 67 68 #define SPACE_CODE_SHIFT 24 69 #define SPACE_CODE_MASK 0x3 70 #define SPACE_CODE_IO_SPACE 0x1 71 #define PROPS_CELL_SIZE 1 72 #define PCI_ADDR_CELL_SIZE 2 73 74 struct pci_ofw_devinfo { 75 STAILQ_ENTRY(pci_ofw_devinfo) pci_ofw_link; 76 struct ofw_bus_devinfo di_dinfo; 77 uint8_t slot; 78 uint8_t func; 79 uint8_t bus; 80 }; 81 82 /* Forward prototypes */ 83 84 static int generic_pcie_fdt_probe(device_t dev); 85 static int parse_pci_mem_ranges(device_t, struct generic_pcie_core_softc *); 86 static int generic_pcie_ofw_bus_attach(device_t); 87 static const struct ofw_bus_devinfo *generic_pcie_ofw_get_devinfo(device_t, 88 device_t); 89 90 static int 91 generic_pcie_fdt_probe(device_t dev) 92 { 93 94 if (!ofw_bus_status_okay(dev)) 95 return (ENXIO); 96 97 if (ofw_bus_is_compatible(dev, "pci-host-ecam-generic")) { 98 device_set_desc(dev, "Generic PCI host controller"); 99 return (BUS_PROBE_GENERIC); 100 } 101 if (ofw_bus_is_compatible(dev, "arm,gem5_pcie")) { 102 device_set_desc(dev, "GEM5 PCIe host controller"); 103 return (BUS_PROBE_DEFAULT); 104 } 105 106 return (ENXIO); 107 } 108 109 int 110 pci_host_generic_setup_fdt(device_t dev) 111 { 112 struct generic_pcie_fdt_softc *sc; 113 phandle_t node; 114 int error; 115 116 sc = device_get_softc(dev); 117 118 STAILQ_INIT(&sc->pci_ofw_devlist); 119 120 /* Retrieve 'ranges' property from FDT */ 121 if (bootverbose) 122 device_printf(dev, "parsing FDT for ECAM%d:\n", sc->base.ecam); 123 if (parse_pci_mem_ranges(dev, &sc->base)) 124 return (ENXIO); 125 126 /* Attach OFW bus */ 127 if (generic_pcie_ofw_bus_attach(dev) != 0) 128 return (ENXIO); 129 130 node = ofw_bus_get_node(dev); 131 if (sc->base.coherent == 0) { 132 sc->base.coherent = OF_hasprop(node, "dma-coherent"); 133 } 134 if (bootverbose) 135 device_printf(dev, "Bus is%s cache-coherent\n", 136 sc->base.coherent ? "" : " not"); 137 138 /* TODO parse FDT bus ranges */ 139 sc->base.bus_start = 0; 140 sc->base.bus_end = 0xFF; 141 142 /* 143 * ofw_pcib uses device unit as PCI domain number. 144 * Do the same. Some boards have multiple RCs handled 145 * by different drivers, this ensures that there are 146 * no collisions. 147 */ 148 sc->base.ecam = device_get_unit(dev); 149 150 error = pci_host_generic_core_attach(dev); 151 if (error != 0) 152 return (error); 153 154 ofw_bus_setup_iinfo(node, &sc->pci_iinfo, sizeof(cell_t)); 155 156 return (0); 157 } 158 159 int 160 pci_host_generic_attach(device_t dev) 161 { 162 struct generic_pcie_fdt_softc *sc; 163 int error; 164 165 sc = device_get_softc(dev); 166 167 error = pci_host_generic_setup_fdt(dev); 168 if (error != 0) 169 return (error); 170 171 device_add_child(dev, "pci", -1); 172 return (bus_generic_attach(dev)); 173 } 174 175 static int 176 parse_pci_mem_ranges(device_t dev, struct generic_pcie_core_softc *sc) 177 { 178 pcell_t pci_addr_cells, parent_addr_cells; 179 pcell_t attributes, size_cells; 180 cell_t *base_ranges; 181 int nbase_ranges; 182 phandle_t node; 183 int i, j, k; 184 int tuple; 185 186 node = ofw_bus_get_node(dev); 187 188 OF_getencprop(node, "#address-cells", &pci_addr_cells, 189 sizeof(pci_addr_cells)); 190 OF_getencprop(node, "#size-cells", &size_cells, 191 sizeof(size_cells)); 192 OF_getencprop(OF_parent(node), "#address-cells", &parent_addr_cells, 193 sizeof(parent_addr_cells)); 194 195 if (parent_addr_cells > 2 || pci_addr_cells != 3 || size_cells > 2) { 196 device_printf(dev, 197 "Unexpected number of address or size cells in FDT\n"); 198 return (ENXIO); 199 } 200 201 nbase_ranges = OF_getproplen(node, "ranges"); 202 sc->nranges = nbase_ranges / sizeof(cell_t) / 203 (parent_addr_cells + pci_addr_cells + size_cells); 204 base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK); 205 OF_getencprop(node, "ranges", base_ranges, nbase_ranges); 206 207 for (i = 0, j = 0; i < sc->nranges; i++) { 208 attributes = (base_ranges[j++] >> SPACE_CODE_SHIFT) & \ 209 SPACE_CODE_MASK; 210 if (attributes == SPACE_CODE_IO_SPACE) { 211 sc->ranges[i].flags |= FLAG_TYPE_IO; 212 } else { 213 sc->ranges[i].flags |= FLAG_TYPE_MEM; 214 } 215 216 sc->ranges[i].pci_base = 0; 217 for (k = 0; k < (pci_addr_cells - 1); k++) { 218 sc->ranges[i].pci_base <<= 32; 219 sc->ranges[i].pci_base |= base_ranges[j++]; 220 } 221 sc->ranges[i].phys_base = 0; 222 for (k = 0; k < parent_addr_cells; k++) { 223 sc->ranges[i].phys_base <<= 32; 224 sc->ranges[i].phys_base |= base_ranges[j++]; 225 } 226 sc->ranges[i].size = 0; 227 for (k = 0; k < size_cells; k++) { 228 sc->ranges[i].size <<= 32; 229 sc->ranges[i].size |= base_ranges[j++]; 230 } 231 } 232 233 for (; i < MAX_RANGES_TUPLES; i++) { 234 /* zero-fill remaining tuples to mark empty elements in array */ 235 sc->ranges[i].pci_base = 0; 236 sc->ranges[i].phys_base = 0; 237 sc->ranges[i].size = 0; 238 } 239 240 if (bootverbose) { 241 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { 242 device_printf(dev, 243 "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx\n", 244 sc->ranges[tuple].pci_base, 245 sc->ranges[tuple].phys_base, 246 sc->ranges[tuple].size); 247 } 248 } 249 250 free(base_ranges, M_DEVBUF); 251 return (0); 252 } 253 254 static int 255 generic_pcie_fdt_route_interrupt(device_t bus, device_t dev, int pin) 256 { 257 struct generic_pcie_fdt_softc *sc; 258 struct ofw_pci_register reg; 259 uint32_t pintr, mintr[4]; 260 phandle_t iparent; 261 int intrcells; 262 263 sc = device_get_softc(bus); 264 pintr = pin; 265 266 bzero(®, sizeof(reg)); 267 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | 268 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | 269 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); 270 271 intrcells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), 272 &sc->pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr), 273 mintr, sizeof(mintr), &iparent); 274 if (intrcells) { 275 pintr = ofw_bus_map_intr(dev, iparent, intrcells, mintr); 276 return (pintr); 277 } 278 279 device_printf(bus, "could not route pin %d for device %d.%d\n", 280 pin, pci_get_slot(dev), pci_get_function(dev)); 281 return (PCI_INVALID_IRQ); 282 } 283 284 static int 285 generic_pcie_fdt_alloc_msi(device_t pci, device_t child, int count, 286 int maxcount, int *irqs) 287 { 288 #if defined(INTRNG) 289 phandle_t msi_parent; 290 int err; 291 292 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 293 &msi_parent, NULL); 294 if (err != 0) 295 return (err); 296 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount, 297 irqs)); 298 #else 299 return (ENXIO); 300 #endif 301 } 302 303 static int 304 generic_pcie_fdt_release_msi(device_t pci, device_t child, int count, int *irqs) 305 { 306 #if defined(INTRNG) 307 phandle_t msi_parent; 308 int err; 309 310 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 311 &msi_parent, NULL); 312 if (err != 0) 313 return (err); 314 return (intr_release_msi(pci, child, msi_parent, count, irqs)); 315 #else 316 return (ENXIO); 317 #endif 318 } 319 320 static int 321 generic_pcie_fdt_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 322 uint32_t *data) 323 { 324 #if defined(INTRNG) 325 phandle_t msi_parent; 326 int err; 327 328 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 329 &msi_parent, NULL); 330 if (err != 0) 331 return (err); 332 return (intr_map_msi(pci, child, msi_parent, irq, addr, data)); 333 #else 334 return (ENXIO); 335 #endif 336 } 337 338 static int 339 generic_pcie_fdt_alloc_msix(device_t pci, device_t child, int *irq) 340 { 341 #if defined(INTRNG) 342 phandle_t msi_parent; 343 int err; 344 345 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 346 &msi_parent, NULL); 347 if (err != 0) 348 return (err); 349 return (intr_alloc_msix(pci, child, msi_parent, irq)); 350 #else 351 return (ENXIO); 352 #endif 353 } 354 355 static int 356 generic_pcie_fdt_release_msix(device_t pci, device_t child, int irq) 357 { 358 #if defined(INTRNG) 359 phandle_t msi_parent; 360 int err; 361 362 err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 363 &msi_parent, NULL); 364 if (err != 0) 365 return (err); 366 return (intr_release_msix(pci, child, msi_parent, irq)); 367 #else 368 return (ENXIO); 369 #endif 370 } 371 372 int 373 generic_pcie_get_id(device_t pci, device_t child, enum pci_id_type type, 374 uintptr_t *id) 375 { 376 phandle_t node; 377 int err; 378 uint32_t rid; 379 uint16_t pci_rid; 380 381 if (type != PCI_ID_MSI) 382 return (pcib_get_id(pci, child, type, id)); 383 384 node = ofw_bus_get_node(pci); 385 pci_rid = pci_get_rid(child); 386 387 err = ofw_bus_msimap(node, pci_rid, NULL, &rid); 388 if (err != 0) 389 return (err); 390 *id = rid; 391 392 return (0); 393 } 394 395 static const struct ofw_bus_devinfo * 396 generic_pcie_ofw_get_devinfo(device_t bus, device_t child) 397 { 398 struct generic_pcie_fdt_softc *sc; 399 struct pci_ofw_devinfo *di; 400 uint8_t slot, func, busno; 401 402 sc = device_get_softc(bus); 403 slot = pci_get_slot(child); 404 func = pci_get_function(child); 405 busno = pci_get_bus(child); 406 407 STAILQ_FOREACH(di, &sc->pci_ofw_devlist, pci_ofw_link) 408 if (slot == di->slot && func == di->func && busno == di->bus) 409 return (&di->di_dinfo); 410 411 return (NULL); 412 } 413 414 /* Helper functions */ 415 416 static int 417 generic_pcie_ofw_bus_attach(device_t dev) 418 { 419 struct generic_pcie_fdt_softc *sc; 420 struct pci_ofw_devinfo *di; 421 phandle_t parent, node; 422 pcell_t reg[5]; 423 ssize_t len; 424 425 sc = device_get_softc(dev); 426 parent = ofw_bus_get_node(dev); 427 if (parent == 0) 428 return (0); 429 430 /* Iterate through all bus subordinates */ 431 for (node = OF_child(parent); node > 0; node = OF_peer(node)) { 432 len = OF_getencprop(node, "reg", reg, sizeof(reg)); 433 if (len != 5 * sizeof(pcell_t)) 434 continue; 435 436 /* Allocate and populate devinfo. */ 437 di = malloc(sizeof(*di), M_DEVBUF, M_WAITOK | M_ZERO); 438 if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) { 439 free(di, M_DEVBUF); 440 continue; 441 } 442 di->func = OFW_PCI_PHYS_HI_FUNCTION(reg[0]); 443 di->slot = OFW_PCI_PHYS_HI_DEVICE(reg[0]); 444 di->bus = OFW_PCI_PHYS_HI_BUS(reg[0]); 445 STAILQ_INSERT_TAIL(&sc->pci_ofw_devlist, di, pci_ofw_link); 446 } 447 448 return (0); 449 } 450 451 static device_method_t generic_pcie_fdt_methods[] = { 452 DEVMETHOD(device_probe, generic_pcie_fdt_probe), 453 DEVMETHOD(device_attach, pci_host_generic_attach), 454 DEVMETHOD(bus_alloc_resource, pci_host_generic_core_alloc_resource), 455 DEVMETHOD(bus_release_resource, pci_host_generic_core_release_resource), 456 457 /* pcib interface */ 458 DEVMETHOD(pcib_route_interrupt, generic_pcie_fdt_route_interrupt), 459 DEVMETHOD(pcib_alloc_msi, generic_pcie_fdt_alloc_msi), 460 DEVMETHOD(pcib_release_msi, generic_pcie_fdt_release_msi), 461 DEVMETHOD(pcib_alloc_msix, generic_pcie_fdt_alloc_msix), 462 DEVMETHOD(pcib_release_msix, generic_pcie_fdt_release_msix), 463 DEVMETHOD(pcib_map_msi, generic_pcie_fdt_map_msi), 464 DEVMETHOD(pcib_get_id, generic_pcie_get_id), 465 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), 466 467 DEVMETHOD(ofw_bus_get_devinfo, generic_pcie_ofw_get_devinfo), 468 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 469 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 470 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 471 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 472 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 473 474 DEVMETHOD_END 475 }; 476 477 DEFINE_CLASS_1(pcib, generic_pcie_fdt_driver, generic_pcie_fdt_methods, 478 sizeof(struct generic_pcie_fdt_softc), generic_pcie_core_driver); 479 480 static devclass_t generic_pcie_fdt_devclass; 481 482 DRIVER_MODULE(pcib, simplebus, generic_pcie_fdt_driver, 483 generic_pcie_fdt_devclass, 0, 0); 484 DRIVER_MODULE(pcib, ofwbus, generic_pcie_fdt_driver, generic_pcie_fdt_devclass, 485 0, 0); 486