1 /*- 2 * Copyright (c) 2022 Andrew Turner 3 * Copyright (c) 2023 Arm Ltd 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/bus.h> 30 #include <sys/kernel.h> 31 #include <sys/module.h> 32 #include <sys/rman.h> 33 34 #include <contrib/dev/acpica/include/acpi.h> 35 #include <contrib/dev/acpica/include/accommon.h> 36 37 #include <dev/acpica/acpivar.h> 38 #include <dev/acpica/acpi_pcibvar.h> 39 40 #include <dev/pci/pcivar.h> 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcib_private.h> 43 #include <dev/pci/pci_host_generic.h> 44 #include <dev/pci/pci_host_generic_acpi.h> 45 46 #include <dev/psci/psci.h> 47 48 #include "pcib_if.h" 49 50 static device_probe_t pci_host_acpi_smccc_probe; 51 static device_attach_t pci_host_acpi_smccc_attach; 52 static pcib_read_config_t pci_host_acpi_smccc_read_config; 53 static pcib_write_config_t pci_host_acpi_smccc_write_config; 54 55 static bool pci_host_acpi_smccc_pci_version(uint32_t *); 56 57 static int 58 pci_host_acpi_smccc_probe(device_t dev) 59 { 60 ACPI_DEVICE_INFO *devinfo; 61 struct resource *res; 62 ACPI_HANDLE h; 63 int rid, root; 64 65 if (acpi_disabled("pcib") || (h = acpi_get_handle(dev)) == NULL || 66 ACPI_FAILURE(AcpiGetObjectInfo(h, &devinfo))) 67 return (ENXIO); 68 root = (devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0; 69 AcpiOsFree(devinfo); 70 if (!root) 71 return (ENXIO); 72 73 /* 74 * Check we have memory resources. We may have a non-memory 75 * mapped device, e.g. using the Arm PCI Configuration Space 76 * Access Firmware Interface (DEN0115). 77 */ 78 res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 0); 79 if (res != NULL) { 80 bus_release_resource(dev, SYS_RES_MEMORY, rid, res); 81 return (ENXIO); 82 } 83 84 /* Check for the PCI_VERSION call */ 85 if (!pci_host_acpi_smccc_pci_version(NULL)) { 86 return (ENXIO); 87 } 88 89 device_set_desc(dev, "ARM PCI Firmware config space host controller"); 90 return (BUS_PROBE_SPECIFIC); 91 } 92 93 #define SMCCC_PCI_VERSION \ 94 SMCCC_FUNC_ID(SMCCC_FAST_CALL, SMCCC_32BIT_CALL, \ 95 SMCCC_STD_SECURE_SERVICE_CALLS, 0x130) 96 #define SMCCC_PCI_FEATURES \ 97 SMCCC_FUNC_ID(SMCCC_FAST_CALL, SMCCC_32BIT_CALL, \ 98 SMCCC_STD_SECURE_SERVICE_CALLS, 0x131) 99 #define SMCCC_PCI_READ \ 100 SMCCC_FUNC_ID(SMCCC_FAST_CALL, SMCCC_32BIT_CALL, \ 101 SMCCC_STD_SECURE_SERVICE_CALLS, 0x132) 102 #define SMCCC_PCI_WRITE \ 103 SMCCC_FUNC_ID(SMCCC_FAST_CALL, SMCCC_32BIT_CALL, \ 104 SMCCC_STD_SECURE_SERVICE_CALLS, 0x133) 105 #define SMCCC_PCI_GET_SEG_INFO \ 106 SMCCC_FUNC_ID(SMCCC_FAST_CALL, SMCCC_32BIT_CALL, \ 107 SMCCC_STD_SECURE_SERVICE_CALLS, 0x134) 108 109 CTASSERT(SMCCC_PCI_VERSION == 0x84000130); 110 CTASSERT(SMCCC_PCI_FEATURES == 0x84000131); 111 CTASSERT(SMCCC_PCI_READ == 0x84000132); 112 CTASSERT(SMCCC_PCI_WRITE == 0x84000133); 113 CTASSERT(SMCCC_PCI_GET_SEG_INFO == 0x84000134); 114 115 #define SMCCC_PCI_MAJOR(x) (((x) >> 16) & 0x7fff) 116 #define SMCCC_PCI_MINOR(x) ((x) & 0xffff) 117 118 #define SMCCC_PCI_SEG_END(x) (((x) >> 8) & 0xff) 119 #define SMCCC_PCI_SEG_START(x) ((x) & 0xff) 120 121 static bool 122 pci_host_acpi_smccc_has_feature(uint32_t pci_func_id) 123 { 124 struct arm_smccc_res result; 125 126 if (psci_callfn(SMCCC_PCI_FEATURES, pci_func_id, 0, 0, 0, 0, 0, 0, 127 &result) < 0) { 128 return (false); 129 } 130 131 return (true); 132 } 133 134 static bool 135 pci_host_acpi_smccc_pci_version(uint32_t *versionp) 136 { 137 struct arm_smccc_res result; 138 139 if (psci_callfn(SMCCC_PCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &result) < 0) { 140 return (false); 141 } 142 143 if (versionp != NULL) { 144 *versionp = result.a0; 145 } 146 147 return (true); 148 } 149 150 static int 151 pci_host_acpi_smccc_attach(device_t dev) 152 { 153 struct generic_pcie_acpi_softc *sc; 154 struct arm_smccc_res result; 155 uint32_t version; 156 int end, start; 157 int error; 158 159 sc = device_get_softc(dev); 160 sc->base.quirks |= PCIE_CUSTOM_CONFIG_SPACE_QUIRK; 161 162 MPASS(psci_callfn != NULL); 163 164 /* Read the version */ 165 if (!pci_host_acpi_smccc_pci_version(&version)) { 166 device_printf(dev, 167 "Failed to read the SMCCC PCI version\n"); 168 return (ENXIO); 169 } 170 171 if (bootverbose) { 172 device_printf(dev, "Firmware v%d.%d\n", 173 SMCCC_PCI_MAJOR(version), SMCCC_PCI_MINOR(version)); 174 } 175 176 if (!pci_host_acpi_smccc_has_feature(SMCCC_PCI_READ) || 177 !pci_host_acpi_smccc_has_feature(SMCCC_PCI_WRITE)) { 178 device_printf(dev, "Missing read/write functions\n"); 179 return (ENXIO); 180 } 181 182 error = pci_host_generic_acpi_init(dev); 183 if (error != 0) 184 return (error); 185 186 if (pci_host_acpi_smccc_has_feature(SMCCC_PCI_GET_SEG_INFO) && 187 psci_callfn(SMCCC_PCI_GET_SEG_INFO, sc->base.ecam, 0, 0, 0, 0, 0, 188 0, &result) == SMCCC_RET_SUCCESS) { 189 start = SMCCC_PCI_SEG_START(result.a1); 190 end = SMCCC_PCI_SEG_END(result.a1); 191 192 sc->base.bus_start = MAX(sc->base.bus_start, start); 193 sc->base.bus_end = MIN(sc->base.bus_end, end); 194 } 195 196 device_add_child(dev, "pci", -1); 197 return (bus_generic_attach(dev)); 198 } 199 200 static uint32_t 201 pci_host_acpi_smccc_read_config(device_t dev, u_int bus, u_int slot, 202 u_int func, u_int reg, int bytes) 203 { 204 struct generic_pcie_acpi_softc *sc; 205 struct arm_smccc_res result; 206 uint32_t addr; 207 208 sc = device_get_softc(dev); 209 210 if ((bus < sc->base.bus_start) || (bus > sc->base.bus_end)) 211 return (~0U); 212 if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || 213 (reg > PCIE_REGMAX)) 214 return (~0U); 215 216 addr = (sc->base.ecam << 16) | (bus << 8) | (slot << 3) | (func << 0); 217 if (psci_callfn(SMCCC_PCI_READ, addr, reg, bytes, 0, 0, 0, 0, 218 &result) < 0) { 219 return (~0U); 220 } 221 222 return (result.a1); 223 } 224 225 static void 226 pci_host_acpi_smccc_write_config(device_t dev, u_int bus, u_int slot, 227 u_int func, u_int reg, uint32_t val, int bytes) 228 { 229 struct generic_pcie_acpi_softc *sc; 230 struct arm_smccc_res result; 231 uint32_t addr; 232 233 sc = device_get_softc(dev); 234 235 if ((bus < sc->base.bus_start) || (bus > sc->base.bus_end)) 236 return; 237 if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || 238 (reg > PCIE_REGMAX)) 239 return; 240 241 addr = (sc->base.ecam << 16) | (bus << 8) | (slot << 3) | (func << 0); 242 psci_callfn(SMCCC_PCI_WRITE, addr, reg, bytes, val, 0, 0, 0, &result); 243 } 244 245 static device_method_t generic_pcie_acpi_smccc_methods[] = { 246 DEVMETHOD(device_probe, pci_host_acpi_smccc_probe), 247 DEVMETHOD(device_attach, pci_host_acpi_smccc_attach), 248 249 /* pcib interface */ 250 DEVMETHOD(pcib_read_config, pci_host_acpi_smccc_read_config), 251 DEVMETHOD(pcib_write_config, pci_host_acpi_smccc_write_config), 252 253 DEVMETHOD_END 254 }; 255 256 DEFINE_CLASS_1(pcib, generic_pcie_acpi_smccc_driver, 257 generic_pcie_acpi_smccc_methods, 258 sizeof(struct generic_pcie_acpi_softc), generic_pcie_acpi_driver); 259 260 DRIVER_MODULE(pcib_smccc, acpi, generic_pcie_acpi_smccc_driver, 0, 0); 261