1 /*- 2 * Copyright (C) 2018 Cavium Inc. 3 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 4 * Copyright (c) 2014 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * This software was developed by Semihalf under 8 * the sponsorship of the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* Generic ECAM PCIe driver */ 33 34 #include <sys/cdefs.h> 35 #include "opt_platform.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/kernel.h> 41 #include <sys/rman.h> 42 #include <sys/module.h> 43 #include <sys/bus.h> 44 #include <sys/endian.h> 45 #include <sys/cpuset.h> 46 #include <sys/rwlock.h> 47 48 #include <contrib/dev/acpica/include/acpi.h> 49 #include <contrib/dev/acpica/include/accommon.h> 50 51 #include <dev/acpica/acpivar.h> 52 #include <dev/acpica/acpi_pcibvar.h> 53 54 #include <dev/pci/pcivar.h> 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcib_private.h> 57 #include <dev/pci/pci_host_generic.h> 58 #include <dev/pci/pci_host_generic_acpi.h> 59 60 #include <machine/cpu.h> 61 #include <machine/bus.h> 62 #include <machine/intr.h> 63 64 #include "pcib_if.h" 65 #include "acpi_bus_if.h" 66 67 /* Assembling ECAM Configuration Address */ 68 #define PCIE_BUS_SHIFT 20 69 #define PCIE_SLOT_SHIFT 15 70 #define PCIE_FUNC_SHIFT 12 71 #define PCIE_BUS_MASK 0xFF 72 #define PCIE_SLOT_MASK 0x1F 73 #define PCIE_FUNC_MASK 0x07 74 #define PCIE_REG_MASK 0xFFF 75 76 #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \ 77 ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \ 78 (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \ 79 (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \ 80 ((reg) & PCIE_REG_MASK)) 81 82 #define PCI_IO_WINDOW_OFFSET 0x1000 83 84 #define SPACE_CODE_SHIFT 24 85 #define SPACE_CODE_MASK 0x3 86 #define SPACE_CODE_IO_SPACE 0x1 87 #define PROPS_CELL_SIZE 1 88 #define PCI_ADDR_CELL_SIZE 2 89 90 static struct { 91 char oem_id[ACPI_OEM_ID_SIZE + 1]; 92 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1]; 93 uint32_t quirks; 94 } pci_acpi_quirks[] = { 95 { "MRVL ", "CN9130 ", PCIE_ECAM_DESIGNWARE_QUIRK }, 96 { "MRVL ", "CN913X ", PCIE_ECAM_DESIGNWARE_QUIRK }, 97 { "MVEBU ", "ARMADA7K", PCIE_ECAM_DESIGNWARE_QUIRK }, 98 { "MVEBU ", "ARMADA8K", PCIE_ECAM_DESIGNWARE_QUIRK }, 99 { "MVEBU ", "CN9130 ", PCIE_ECAM_DESIGNWARE_QUIRK }, 100 { "MVEBU ", "CN9131 ", PCIE_ECAM_DESIGNWARE_QUIRK }, 101 { "MVEBU ", "CN9132 ", PCIE_ECAM_DESIGNWARE_QUIRK }, 102 }; 103 104 /* Forward prototypes */ 105 106 static int generic_pcie_acpi_probe(device_t dev); 107 static ACPI_STATUS pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *, void *); 108 static int generic_pcie_acpi_read_ivar(device_t, device_t, int, uintptr_t *); 109 110 /* 111 * generic_pcie_acpi_probe - look for root bridge flag 112 */ 113 static int 114 generic_pcie_acpi_probe(device_t dev) 115 { 116 ACPI_DEVICE_INFO *devinfo; 117 ACPI_HANDLE h; 118 int root; 119 120 if (acpi_disabled("pcib") || (h = acpi_get_handle(dev)) == NULL || 121 ACPI_FAILURE(AcpiGetObjectInfo(h, &devinfo))) 122 return (ENXIO); 123 root = (devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0; 124 AcpiOsFree(devinfo); 125 if (!root) 126 return (ENXIO); 127 128 device_set_desc(dev, "Generic PCI host controller"); 129 return (BUS_PROBE_GENERIC); 130 } 131 132 /* 133 * pci_host_generic_acpi_parse_resource - parse PCI memory, IO and bus spaces 134 * 'produced' by this bridge 135 */ 136 static ACPI_STATUS 137 pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *res, void *arg) 138 { 139 device_t dev = (device_t)arg; 140 struct generic_pcie_acpi_softc *sc; 141 rman_res_t min, max, off; 142 int r, restype; 143 144 sc = device_get_softc(dev); 145 r = sc->base.nranges; 146 switch (res->Type) { 147 case ACPI_RESOURCE_TYPE_ADDRESS16: 148 restype = res->Data.Address16.ResourceType; 149 min = res->Data.Address16.Address.Minimum; 150 max = res->Data.Address16.Address.Maximum; 151 break; 152 case ACPI_RESOURCE_TYPE_ADDRESS32: 153 restype = res->Data.Address32.ResourceType; 154 min = res->Data.Address32.Address.Minimum; 155 max = res->Data.Address32.Address.Maximum; 156 off = res->Data.Address32.Address.TranslationOffset; 157 break; 158 case ACPI_RESOURCE_TYPE_ADDRESS64: 159 restype = res->Data.Address64.ResourceType; 160 min = res->Data.Address64.Address.Minimum; 161 max = res->Data.Address64.Address.Maximum; 162 off = res->Data.Address64.Address.TranslationOffset; 163 break; 164 case ACPI_RESOURCE_TYPE_FIXED_MEMORY32: 165 /* 166 * The Microsoft Dev Kit 2023 uses a fixed memory region 167 * for some PCI controllers. For this memory the 168 * ResourceType is ACPI_IO_RANGE meaning we create an IO 169 * resource. As drivers expect it to be a memory resource 170 * force the type here. 171 */ 172 restype = ACPI_MEMORY_RANGE; 173 min = res->Data.FixedMemory32.Address; 174 max = res->Data.FixedMemory32.Address + 175 res->Data.FixedMemory32.AddressLength - 1; 176 off = 0; 177 break; 178 default: 179 return (AE_OK); 180 } 181 182 /* Save detected ranges */ 183 if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE || 184 res->Data.Address.ResourceType == ACPI_IO_RANGE) { 185 sc->base.ranges[r].pci_base = min; 186 sc->base.ranges[r].phys_base = min + off; 187 sc->base.ranges[r].size = max - min + 1; 188 if (restype == ACPI_MEMORY_RANGE) 189 sc->base.ranges[r].flags |= FLAG_TYPE_MEM; 190 else if (restype == ACPI_IO_RANGE) 191 sc->base.ranges[r].flags |= FLAG_TYPE_IO; 192 sc->base.nranges++; 193 } else if (res->Data.Address.ResourceType == ACPI_BUS_NUMBER_RANGE) { 194 sc->base.bus_start = min; 195 sc->base.bus_end = max; 196 } 197 return (AE_OK); 198 } 199 200 static void 201 pci_host_acpi_get_oem_quirks(struct generic_pcie_acpi_softc *sc, 202 ACPI_TABLE_HEADER *hdr) 203 { 204 size_t i; 205 206 for (i = 0; i < nitems(pci_acpi_quirks); i++) { 207 if (memcmp(hdr->OemId, pci_acpi_quirks[i].oem_id, 208 ACPI_OEM_ID_SIZE) != 0) 209 continue; 210 if (memcmp(hdr->OemTableId, pci_acpi_quirks[i].oem_table_id, 211 ACPI_OEM_TABLE_ID_SIZE) != 0) 212 continue; 213 sc->base.quirks |= pci_acpi_quirks[i].quirks; 214 } 215 } 216 217 static int 218 pci_host_acpi_get_ecam_resource(device_t dev) 219 { 220 struct generic_pcie_acpi_softc *sc; 221 struct acpi_device *ad; 222 struct resource_list *rl; 223 ACPI_TABLE_HEADER *hdr; 224 ACPI_MCFG_ALLOCATION *mcfg_entry, *mcfg_end; 225 ACPI_HANDLE handle; 226 ACPI_STATUS status; 227 rman_res_t base, start, end; 228 int found, val; 229 230 sc = device_get_softc(dev); 231 handle = acpi_get_handle(dev); 232 233 /* Try MCFG first */ 234 status = AcpiGetTable(ACPI_SIG_MCFG, 1, &hdr); 235 if (ACPI_SUCCESS(status)) { 236 found = FALSE; 237 mcfg_end = (ACPI_MCFG_ALLOCATION *)((char *)hdr + hdr->Length); 238 mcfg_entry = (ACPI_MCFG_ALLOCATION *)((ACPI_TABLE_MCFG *)hdr + 1); 239 while (mcfg_entry < mcfg_end && !found) { 240 if (mcfg_entry->PciSegment == sc->base.ecam && 241 mcfg_entry->StartBusNumber <= sc->base.bus_start && 242 mcfg_entry->EndBusNumber >= sc->base.bus_start) 243 found = TRUE; 244 else 245 mcfg_entry++; 246 } 247 if (found) { 248 if (mcfg_entry->EndBusNumber < sc->base.bus_end) 249 sc->base.bus_end = mcfg_entry->EndBusNumber; 250 base = mcfg_entry->Address; 251 } else { 252 device_printf(dev, "MCFG exists, but does not have bus %d-%d\n", 253 sc->base.bus_start, sc->base.bus_end); 254 return (ENXIO); 255 } 256 pci_host_acpi_get_oem_quirks(sc, hdr); 257 if (sc->base.quirks & PCIE_ECAM_DESIGNWARE_QUIRK) 258 device_set_desc(dev, "Synopsys DesignWare PCIe Controller"); 259 } else { 260 status = acpi_GetInteger(handle, "_CBA", &val); 261 if (ACPI_SUCCESS(status)) 262 base = val; 263 else 264 return (ENXIO); 265 } 266 267 /* add as MEM rid 0 */ 268 ad = device_get_ivars(dev); 269 rl = &ad->ad_rl; 270 start = base + (sc->base.bus_start << PCIE_BUS_SHIFT); 271 end = base + ((sc->base.bus_end + 1) << PCIE_BUS_SHIFT) - 1; 272 resource_list_add(rl, SYS_RES_MEMORY, 0, start, end, end - start + 1); 273 if (bootverbose) 274 device_printf(dev, "ECAM for bus %d-%d at mem %jx-%jx\n", 275 sc->base.bus_start, sc->base.bus_end, start, end); 276 return (0); 277 } 278 279 int 280 pci_host_generic_acpi_init(device_t dev) 281 { 282 struct generic_pcie_acpi_softc *sc; 283 ACPI_HANDLE handle; 284 ACPI_STATUS status; 285 int error; 286 287 sc = device_get_softc(dev); 288 handle = acpi_get_handle(dev); 289 290 acpi_pcib_osc(dev, &sc->osc_ctl, 0); 291 292 /* Get Start bus number for the PCI host bus is from _BBN method */ 293 status = acpi_GetInteger(handle, "_BBN", &sc->base.bus_start); 294 if (ACPI_FAILURE(status)) { 295 device_printf(dev, "No _BBN, using start bus 0\n"); 296 sc->base.bus_start = 0; 297 } 298 sc->base.bus_end = 255; 299 300 /* Get PCI Segment (domain) needed for MCFG lookup */ 301 status = acpi_GetInteger(handle, "_SEG", &sc->base.ecam); 302 if (ACPI_FAILURE(status)) { 303 device_printf(dev, "No _SEG for PCI Bus, using segment 0\n"); 304 sc->base.ecam = 0; 305 } 306 307 /* Bus decode ranges */ 308 status = AcpiWalkResources(handle, "_CRS", 309 pci_host_generic_acpi_parse_resource, (void *)dev); 310 if (ACPI_FAILURE(status)) 311 return (ENXIO); 312 313 /* Coherency attribute */ 314 if (ACPI_FAILURE(acpi_GetInteger(handle, "_CCA", &sc->base.coherent))) 315 sc->base.coherent = 0; 316 if (bootverbose) 317 device_printf(dev, "Bus is%s cache-coherent\n", 318 sc->base.coherent ? "" : " not"); 319 320 /* add config space resource */ 321 pci_host_acpi_get_ecam_resource(dev); 322 acpi_pcib_fetch_prt(dev, &sc->ap_prt); 323 324 error = pci_host_generic_core_attach(dev); 325 if (error != 0) 326 return (error); 327 328 return (0); 329 } 330 331 static int 332 pci_host_generic_acpi_attach(device_t dev) 333 { 334 int error; 335 336 error = pci_host_generic_acpi_init(dev); 337 if (error != 0) 338 return (error); 339 340 device_add_child(dev, "pci", DEVICE_UNIT_ANY); 341 bus_attach_children(dev); 342 return (0); 343 } 344 345 static int 346 generic_pcie_acpi_read_ivar(device_t dev, device_t child, int index, 347 uintptr_t *result) 348 { 349 ACPI_HANDLE handle; 350 351 switch (index) { 352 case ACPI_IVAR_HANDLE: 353 handle = acpi_get_handle(dev); 354 *result = (uintptr_t)handle; 355 return (0); 356 } 357 358 return (generic_pcie_read_ivar(dev, child, index, result)); 359 } 360 361 static int 362 generic_pcie_acpi_route_interrupt(device_t bus, device_t dev, int pin) 363 { 364 struct generic_pcie_acpi_softc *sc; 365 366 sc = device_get_softc(bus); 367 return (acpi_pcib_route_interrupt(bus, dev, pin, &sc->ap_prt)); 368 } 369 370 static u_int 371 generic_pcie_get_xref(device_t pci, device_t child) 372 { 373 struct generic_pcie_acpi_softc *sc; 374 uintptr_t rid; 375 u_int xref, devid; 376 int err; 377 378 sc = device_get_softc(pci); 379 err = pcib_get_id(pci, child, PCI_ID_RID, &rid); 380 if (err != 0) 381 return (ACPI_MSI_XREF); 382 err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid); 383 if (err != 0) 384 return (ACPI_MSI_XREF); 385 return (xref); 386 } 387 388 static u_int 389 generic_pcie_map_id(device_t pci, device_t child, uintptr_t *id) 390 { 391 struct generic_pcie_acpi_softc *sc; 392 uintptr_t rid; 393 u_int xref, devid; 394 int err; 395 396 sc = device_get_softc(pci); 397 err = pcib_get_id(pci, child, PCI_ID_RID, &rid); 398 if (err != 0) 399 return (err); 400 err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid); 401 if (err == 0) 402 *id = devid; 403 else 404 *id = rid; /* RID not in IORT, likely FW bug, ignore */ 405 return (0); 406 } 407 408 static int 409 generic_pcie_get_iommu(device_t pci, device_t child, uintptr_t *id) 410 { 411 struct generic_pcie_acpi_softc *sc; 412 struct pci_id_ofw_iommu *iommu; 413 u_int iommu_sid, iommu_xref; 414 uintptr_t rid; 415 int err; 416 417 iommu = (struct pci_id_ofw_iommu *)id; 418 419 sc = device_get_softc(pci); 420 err = pcib_get_id(pci, child, PCI_ID_RID, &rid); 421 if (err != 0) 422 return (err); 423 err = acpi_iort_map_pci_smmuv3(sc->base.ecam, rid, &iommu_xref, 424 &iommu_sid); 425 if (err == 0) { 426 iommu->id = iommu_sid; 427 iommu->xref = iommu_xref; 428 } 429 430 return (err); 431 } 432 433 static int 434 generic_pcie_acpi_alloc_msi(device_t pci, device_t child, int count, 435 int maxcount, int *irqs) 436 { 437 438 #if defined(INTRNG) 439 return (intr_alloc_msi(pci, child, generic_pcie_get_xref(pci, child), 440 count, maxcount, irqs)); 441 #else 442 return (ENXIO); 443 #endif 444 } 445 446 static int 447 generic_pcie_acpi_release_msi(device_t pci, device_t child, int count, 448 int *irqs) 449 { 450 451 #if defined(INTRNG) 452 return (intr_release_msi(pci, child, generic_pcie_get_xref(pci, child), 453 count, irqs)); 454 #else 455 return (ENXIO); 456 #endif 457 } 458 459 static int 460 generic_pcie_acpi_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 461 uint32_t *data) 462 { 463 464 #if defined(INTRNG) 465 return (intr_map_msi(pci, child, generic_pcie_get_xref(pci, child), irq, 466 addr, data)); 467 #else 468 return (ENXIO); 469 #endif 470 } 471 472 static int 473 generic_pcie_acpi_alloc_msix(device_t pci, device_t child, int *irq) 474 { 475 476 #if defined(INTRNG) 477 return (intr_alloc_msix(pci, child, generic_pcie_get_xref(pci, child), 478 irq)); 479 #else 480 return (ENXIO); 481 #endif 482 } 483 484 static int 485 generic_pcie_acpi_release_msix(device_t pci, device_t child, int irq) 486 { 487 488 #if defined(INTRNG) 489 return (intr_release_msix(pci, child, generic_pcie_get_xref(pci, child), 490 irq)); 491 #else 492 return (ENXIO); 493 #endif 494 } 495 496 static int 497 generic_pcie_acpi_get_id(device_t pci, device_t child, enum pci_id_type type, 498 uintptr_t *id) 499 { 500 if (type == PCI_ID_OFW_IOMMU) 501 return (generic_pcie_get_iommu(pci, child, id)); 502 503 if (type == PCI_ID_MSI) 504 return (generic_pcie_map_id(pci, child, id)); 505 506 return (pcib_get_id(pci, child, type, id)); 507 } 508 509 static int 510 generic_pcie_acpi_request_feature(device_t pcib, device_t dev, 511 enum pci_feature feature) 512 { 513 struct generic_pcie_acpi_softc *sc; 514 uint32_t osc_ctl; 515 516 sc = device_get_softc(pcib); 517 518 switch (feature) { 519 case PCI_FEATURE_HP: 520 osc_ctl = PCIM_OSC_CTL_PCIE_HP; 521 break; 522 case PCI_FEATURE_AER: 523 osc_ctl = PCIM_OSC_CTL_PCIE_AER; 524 break; 525 default: 526 return (EINVAL); 527 } 528 529 return (acpi_pcib_osc(pcib, &sc->osc_ctl, osc_ctl)); 530 } 531 532 533 static device_method_t generic_pcie_acpi_methods[] = { 534 DEVMETHOD(device_probe, generic_pcie_acpi_probe), 535 DEVMETHOD(device_attach, pci_host_generic_acpi_attach), 536 DEVMETHOD(bus_read_ivar, generic_pcie_acpi_read_ivar), 537 538 /* pcib interface */ 539 DEVMETHOD(pcib_route_interrupt, generic_pcie_acpi_route_interrupt), 540 DEVMETHOD(pcib_alloc_msi, generic_pcie_acpi_alloc_msi), 541 DEVMETHOD(pcib_release_msi, generic_pcie_acpi_release_msi), 542 DEVMETHOD(pcib_alloc_msix, generic_pcie_acpi_alloc_msix), 543 DEVMETHOD(pcib_release_msix, generic_pcie_acpi_release_msix), 544 DEVMETHOD(pcib_map_msi, generic_pcie_acpi_map_msi), 545 DEVMETHOD(pcib_get_id, generic_pcie_acpi_get_id), 546 DEVMETHOD(pcib_request_feature, generic_pcie_acpi_request_feature), 547 548 DEVMETHOD_END 549 }; 550 551 DEFINE_CLASS_1(pcib, generic_pcie_acpi_driver, generic_pcie_acpi_methods, 552 sizeof(struct generic_pcie_acpi_softc), generic_pcie_core_driver); 553 554 DRIVER_MODULE(pcib, acpi, generic_pcie_acpi_driver, 0, 0); 555