1 /*- 2 * Copyright (C) 2018 Cavium Inc. 3 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 4 * Copyright (c) 2014 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * This software was developed by Semihalf under 8 * the sponsorship of the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* Generic ECAM PCIe driver */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include "opt_platform.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/malloc.h> 42 #include <sys/kernel.h> 43 #include <sys/rman.h> 44 #include <sys/module.h> 45 #include <sys/bus.h> 46 #include <sys/endian.h> 47 #include <sys/cpuset.h> 48 #include <sys/rwlock.h> 49 50 #include <contrib/dev/acpica/include/acpi.h> 51 #include <contrib/dev/acpica/include/accommon.h> 52 53 #include <dev/acpica/acpivar.h> 54 #include <dev/acpica/acpi_pcibvar.h> 55 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcib_private.h> 59 #include <dev/pci/pci_host_generic.h> 60 #include <dev/pci/pci_host_generic_acpi.h> 61 62 #include <machine/cpu.h> 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include "pcib_if.h" 67 #include "acpi_bus_if.h" 68 69 /* Assembling ECAM Configuration Address */ 70 #define PCIE_BUS_SHIFT 20 71 #define PCIE_SLOT_SHIFT 15 72 #define PCIE_FUNC_SHIFT 12 73 #define PCIE_BUS_MASK 0xFF 74 #define PCIE_SLOT_MASK 0x1F 75 #define PCIE_FUNC_MASK 0x07 76 #define PCIE_REG_MASK 0xFFF 77 78 #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \ 79 ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \ 80 (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \ 81 (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \ 82 ((reg) & PCIE_REG_MASK)) 83 84 #define PCI_IO_WINDOW_OFFSET 0x1000 85 86 #define SPACE_CODE_SHIFT 24 87 #define SPACE_CODE_MASK 0x3 88 #define SPACE_CODE_IO_SPACE 0x1 89 #define PROPS_CELL_SIZE 1 90 #define PCI_ADDR_CELL_SIZE 2 91 92 /* Forward prototypes */ 93 94 static int generic_pcie_acpi_probe(device_t dev); 95 static ACPI_STATUS pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *, void *); 96 static int generic_pcie_acpi_read_ivar(device_t, device_t, int, uintptr_t *); 97 98 /* 99 * generic_pcie_acpi_probe - look for root bridge flag 100 */ 101 static int 102 generic_pcie_acpi_probe(device_t dev) 103 { 104 ACPI_DEVICE_INFO *devinfo; 105 ACPI_HANDLE h; 106 int root; 107 108 if (acpi_disabled("pcib") || (h = acpi_get_handle(dev)) == NULL || 109 ACPI_FAILURE(AcpiGetObjectInfo(h, &devinfo))) 110 return (ENXIO); 111 root = (devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0; 112 AcpiOsFree(devinfo); 113 if (!root) 114 return (ENXIO); 115 116 device_set_desc(dev, "Generic PCI host controller"); 117 return (BUS_PROBE_GENERIC); 118 } 119 120 /* 121 * pci_host_generic_acpi_parse_resource - parse PCI memory, IO and bus spaces 122 * 'produced' by this bridge 123 */ 124 static ACPI_STATUS 125 pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *res, void *arg) 126 { 127 device_t dev = (device_t)arg; 128 struct generic_pcie_acpi_softc *sc; 129 struct rman *rm; 130 rman_res_t min, max, off; 131 int r; 132 133 rm = NULL; 134 sc = device_get_softc(dev); 135 r = sc->base.nranges; 136 switch (res->Type) { 137 case ACPI_RESOURCE_TYPE_ADDRESS16: 138 min = res->Data.Address16.Address.Minimum; 139 max = res->Data.Address16.Address.Maximum; 140 break; 141 case ACPI_RESOURCE_TYPE_ADDRESS32: 142 min = res->Data.Address32.Address.Minimum; 143 max = res->Data.Address32.Address.Maximum; 144 off = res->Data.Address32.Address.TranslationOffset; 145 break; 146 case ACPI_RESOURCE_TYPE_ADDRESS64: 147 min = res->Data.Address64.Address.Minimum; 148 max = res->Data.Address64.Address.Maximum; 149 off = res->Data.Address64.Address.TranslationOffset; 150 break; 151 default: 152 return (AE_OK); 153 } 154 155 /* Save detected ranges */ 156 if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE || 157 res->Data.Address.ResourceType == ACPI_IO_RANGE) { 158 sc->base.ranges[r].pci_base = min; 159 sc->base.ranges[r].phys_base = min + off; 160 sc->base.ranges[r].size = max - min + 1; 161 if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE) 162 sc->base.ranges[r].flags |= FLAG_MEM; 163 else if (res->Data.Address.ResourceType == ACPI_IO_RANGE) 164 sc->base.ranges[r].flags |= FLAG_IO; 165 sc->base.nranges++; 166 } else if (res->Data.Address.ResourceType == ACPI_BUS_NUMBER_RANGE) { 167 sc->base.bus_start = min; 168 sc->base.bus_end = max; 169 } 170 return (AE_OK); 171 } 172 173 static int 174 pci_host_acpi_get_ecam_resource(device_t dev) 175 { 176 struct generic_pcie_acpi_softc *sc; 177 struct acpi_device *ad; 178 struct resource_list *rl; 179 ACPI_TABLE_HEADER *hdr; 180 ACPI_MCFG_ALLOCATION *mcfg_entry, *mcfg_end; 181 ACPI_HANDLE handle; 182 ACPI_STATUS status; 183 rman_res_t base, start, end; 184 int found, val; 185 186 sc = device_get_softc(dev); 187 handle = acpi_get_handle(dev); 188 189 /* Try MCFG first */ 190 status = AcpiGetTable(ACPI_SIG_MCFG, 1, &hdr); 191 if (ACPI_SUCCESS(status)) { 192 found = FALSE; 193 mcfg_end = (ACPI_MCFG_ALLOCATION *)((char *)hdr + hdr->Length); 194 mcfg_entry = (ACPI_MCFG_ALLOCATION *)((ACPI_TABLE_MCFG *)hdr + 1); 195 while (mcfg_entry < mcfg_end && !found) { 196 if (mcfg_entry->PciSegment == sc->base.ecam && 197 mcfg_entry->StartBusNumber <= sc->base.bus_start && 198 mcfg_entry->EndBusNumber >= sc->base.bus_start) 199 found = TRUE; 200 else 201 mcfg_entry++; 202 } 203 if (found) { 204 sc->base.bus_end = mcfg_entry->EndBusNumber; 205 base = mcfg_entry->Address; 206 } else { 207 device_printf(dev, "MCFG exists, but does not have bus %d-%d\n", 208 sc->base.bus_start, sc->base.bus_end); 209 return (ENXIO); 210 } 211 } else { 212 status = acpi_GetInteger(handle, "_CBA", &val); 213 if (ACPI_SUCCESS(status)) { 214 base = val; 215 sc->base.bus_end = 255; 216 } else 217 return (ENXIO); 218 } 219 220 /* add as MEM rid 0 */ 221 ad = device_get_ivars(dev); 222 rl = &ad->ad_rl; 223 start = base + (sc->base.bus_start << PCIE_BUS_SHIFT); 224 end = base + ((sc->base.bus_end + 1) << PCIE_BUS_SHIFT) - 1; 225 resource_list_add(rl, SYS_RES_MEMORY, 0, start, end, end - start + 1); 226 if (bootverbose) 227 device_printf(dev, "ECAM for bus %d-%d at mem %jx-%jx\n", 228 sc->base.bus_start, sc->base.bus_end, start, end); 229 return (0); 230 } 231 232 int 233 pci_host_generic_acpi_attach(device_t dev) 234 { 235 struct generic_pcie_acpi_softc *sc; 236 ACPI_HANDLE handle; 237 uint64_t phys_base; 238 uint64_t pci_base; 239 uint64_t size; 240 ACPI_STATUS status; 241 int error; 242 int tuple; 243 244 sc = device_get_softc(dev); 245 handle = acpi_get_handle(dev); 246 247 /* Get Start bus number for the PCI host bus is from _BBN method */ 248 status = acpi_GetInteger(handle, "_BBN", &sc->base.bus_start); 249 if (ACPI_FAILURE(status)) { 250 device_printf(dev, "No _BBN, using start bus 0\n"); 251 sc->base.bus_start = 0; 252 } 253 254 /* Get PCI Segment (domain) needed for MCFG lookup */ 255 status = acpi_GetInteger(handle, "_SEG", &sc->base.ecam); 256 if (ACPI_FAILURE(status)) { 257 device_printf(dev, "No _SEG for PCI Bus, using segment 0\n"); 258 sc->base.ecam = 0; 259 } 260 261 /* Bus decode ranges */ 262 status = AcpiWalkResources(handle, "_CRS", 263 pci_host_generic_acpi_parse_resource, (void *)dev); 264 if (ACPI_FAILURE(status)) 265 return (ENXIO); 266 267 /* Coherency attribute */ 268 if (ACPI_FAILURE(acpi_GetInteger(handle, "_CCA", &sc->base.coherent))) 269 sc->base.coherent = 0; 270 if (bootverbose) 271 device_printf(dev, "Bus is%s cache-coherent\n", 272 sc->base.coherent ? "" : " not"); 273 274 /* add config space resource */ 275 pci_host_acpi_get_ecam_resource(dev); 276 acpi_pcib_fetch_prt(dev, &sc->ap_prt); 277 278 error = pci_host_generic_core_attach(dev); 279 if (error != 0) 280 return (error); 281 282 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { 283 phys_base = sc->base.ranges[tuple].phys_base; 284 pci_base = sc->base.ranges[tuple].pci_base; 285 size = sc->base.ranges[tuple].size; 286 if (phys_base == 0 || size == 0) 287 continue; /* empty range element */ 288 if (sc->base.ranges[tuple].flags & FLAG_MEM) { 289 error = rman_manage_region(&sc->base.mem_rman, 290 pci_base, pci_base + size - 1); 291 } else if (sc->base.ranges[tuple].flags & FLAG_IO) { 292 error = rman_manage_region(&sc->base.io_rman, 293 pci_base + PCI_IO_WINDOW_OFFSET, 294 pci_base + PCI_IO_WINDOW_OFFSET + size - 1); 295 } else 296 continue; 297 if (error) { 298 device_printf(dev, "rman_manage_region() failed." 299 "error = %d\n", error); 300 rman_fini(&sc->base.mem_rman); 301 return (error); 302 } 303 } 304 305 device_add_child(dev, "pci", -1); 306 return (bus_generic_attach(dev)); 307 } 308 309 static int 310 generic_pcie_acpi_read_ivar(device_t dev, device_t child, int index, 311 uintptr_t *result) 312 { 313 struct generic_pcie_acpi_softc *sc; 314 315 sc = device_get_softc(dev); 316 317 if (index == PCIB_IVAR_BUS) { 318 *result = sc->base.bus_start; 319 return (0); 320 } 321 322 if (index == PCIB_IVAR_DOMAIN) { 323 *result = sc->base.ecam; 324 return (0); 325 } 326 327 if (bootverbose) 328 device_printf(dev, "ERROR: Unknown index %d.\n", index); 329 return (ENOENT); 330 } 331 332 static int 333 generic_pcie_acpi_route_interrupt(device_t bus, device_t dev, int pin) 334 { 335 struct generic_pcie_acpi_softc *sc; 336 337 sc = device_get_softc(bus); 338 return (acpi_pcib_route_interrupt(bus, dev, pin, &sc->ap_prt)); 339 } 340 341 static u_int 342 generic_pcie_get_xref(device_t pci, device_t child) 343 { 344 struct generic_pcie_acpi_softc *sc; 345 uintptr_t rid; 346 u_int xref, devid; 347 int err; 348 349 sc = device_get_softc(pci); 350 err = pcib_get_id(pci, child, PCI_ID_RID, &rid); 351 if (err != 0) 352 return (ACPI_MSI_XREF); 353 err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid); 354 if (err != 0) 355 return (ACPI_MSI_XREF); 356 return (xref); 357 } 358 359 static u_int 360 generic_pcie_map_id(device_t pci, device_t child, uintptr_t *id) 361 { 362 struct generic_pcie_acpi_softc *sc; 363 uintptr_t rid; 364 u_int xref, devid; 365 int err; 366 367 sc = device_get_softc(pci); 368 err = pcib_get_id(pci, child, PCI_ID_RID, &rid); 369 if (err != 0) 370 return (err); 371 err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid); 372 if (err == 0) 373 *id = devid; 374 else 375 *id = rid; /* RID not in IORT, likely FW bug, ignore */ 376 return (0); 377 } 378 379 static int 380 generic_pcie_acpi_alloc_msi(device_t pci, device_t child, int count, 381 int maxcount, int *irqs) 382 { 383 384 #if defined(INTRNG) 385 return (intr_alloc_msi(pci, child, generic_pcie_get_xref(pci, child), 386 count, maxcount, irqs)); 387 #else 388 return (ENXIO); 389 #endif 390 } 391 392 static int 393 generic_pcie_acpi_release_msi(device_t pci, device_t child, int count, 394 int *irqs) 395 { 396 397 #if defined(INTRNG) 398 return (intr_release_msi(pci, child, generic_pcie_get_xref(pci, child), 399 count, irqs)); 400 #else 401 return (ENXIO); 402 #endif 403 } 404 405 static int 406 generic_pcie_acpi_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 407 uint32_t *data) 408 { 409 410 #if defined(INTRNG) 411 return (intr_map_msi(pci, child, generic_pcie_get_xref(pci, child), irq, 412 addr, data)); 413 #else 414 return (ENXIO); 415 #endif 416 } 417 418 static int 419 generic_pcie_acpi_alloc_msix(device_t pci, device_t child, int *irq) 420 { 421 422 #if defined(INTRNG) 423 return (intr_alloc_msix(pci, child, generic_pcie_get_xref(pci, child), 424 irq)); 425 #else 426 return (ENXIO); 427 #endif 428 } 429 430 static int 431 generic_pcie_acpi_release_msix(device_t pci, device_t child, int irq) 432 { 433 434 #if defined(INTRNG) 435 return (intr_release_msix(pci, child, generic_pcie_get_xref(pci, child), 436 irq)); 437 #else 438 return (ENXIO); 439 #endif 440 } 441 442 static int 443 generic_pcie_acpi_get_id(device_t pci, device_t child, enum pci_id_type type, 444 uintptr_t *id) 445 { 446 447 if (type == PCI_ID_MSI) 448 return (generic_pcie_map_id(pci, child, id)); 449 else 450 return (pcib_get_id(pci, child, type, id)); 451 } 452 453 static device_method_t generic_pcie_acpi_methods[] = { 454 DEVMETHOD(device_probe, generic_pcie_acpi_probe), 455 DEVMETHOD(device_attach, pci_host_generic_acpi_attach), 456 DEVMETHOD(bus_read_ivar, generic_pcie_acpi_read_ivar), 457 458 /* pcib interface */ 459 DEVMETHOD(pcib_route_interrupt, generic_pcie_acpi_route_interrupt), 460 DEVMETHOD(pcib_alloc_msi, generic_pcie_acpi_alloc_msi), 461 DEVMETHOD(pcib_release_msi, generic_pcie_acpi_release_msi), 462 DEVMETHOD(pcib_alloc_msix, generic_pcie_acpi_alloc_msix), 463 DEVMETHOD(pcib_release_msix, generic_pcie_acpi_release_msix), 464 DEVMETHOD(pcib_map_msi, generic_pcie_acpi_map_msi), 465 DEVMETHOD(pcib_get_id, generic_pcie_acpi_get_id), 466 467 DEVMETHOD_END 468 }; 469 470 DEFINE_CLASS_1(pcib, generic_pcie_acpi_driver, generic_pcie_acpi_methods, 471 sizeof(struct generic_pcie_acpi_softc), generic_pcie_core_driver); 472 473 static devclass_t generic_pcie_acpi_devclass; 474 475 DRIVER_MODULE(pcib, acpi, generic_pcie_acpi_driver, generic_pcie_acpi_devclass, 476 0, 0); 477