1 /*- 2 * Copyright (C) 2018 Cavium Inc. 3 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 4 * Copyright (c) 2014 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * This software was developed by Semihalf under 8 * the sponsorship of the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* Generic ECAM PCIe driver */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include "opt_platform.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/malloc.h> 42 #include <sys/kernel.h> 43 #include <sys/rman.h> 44 #include <sys/module.h> 45 #include <sys/bus.h> 46 #include <sys/endian.h> 47 #include <sys/cpuset.h> 48 #include <sys/rwlock.h> 49 50 #include <contrib/dev/acpica/include/acpi.h> 51 #include <contrib/dev/acpica/include/accommon.h> 52 53 #include <dev/acpica/acpivar.h> 54 #include <dev/acpica/acpi_pcibvar.h> 55 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcib_private.h> 59 #include <dev/pci/pci_host_generic.h> 60 #include <dev/pci/pci_host_generic_acpi.h> 61 62 #include <machine/cpu.h> 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include "pcib_if.h" 67 #include "acpi_bus_if.h" 68 69 /* Assembling ECAM Configuration Address */ 70 #define PCIE_BUS_SHIFT 20 71 #define PCIE_SLOT_SHIFT 15 72 #define PCIE_FUNC_SHIFT 12 73 #define PCIE_BUS_MASK 0xFF 74 #define PCIE_SLOT_MASK 0x1F 75 #define PCIE_FUNC_MASK 0x07 76 #define PCIE_REG_MASK 0xFFF 77 78 #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \ 79 ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \ 80 (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \ 81 (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \ 82 ((reg) & PCIE_REG_MASK)) 83 84 #define PCI_IO_WINDOW_OFFSET 0x1000 85 86 #define SPACE_CODE_SHIFT 24 87 #define SPACE_CODE_MASK 0x3 88 #define SPACE_CODE_IO_SPACE 0x1 89 #define PROPS_CELL_SIZE 1 90 #define PCI_ADDR_CELL_SIZE 2 91 92 static struct { 93 char oem_id[ACPI_OEM_ID_SIZE + 1]; 94 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1]; 95 uint32_t quirks; 96 } pci_acpi_quirks[] = { 97 { "MRVL ", "CN9130 ", PCIE_ECAM_DESIGNWARE_QUIRK }, 98 { "MRVL ", "CN913X ", PCIE_ECAM_DESIGNWARE_QUIRK }, 99 { "MVEBU ", "ARMADA7K", PCIE_ECAM_DESIGNWARE_QUIRK }, 100 { "MVEBU ", "ARMADA8K", PCIE_ECAM_DESIGNWARE_QUIRK }, 101 { "MVEBU ", "CN9130 ", PCIE_ECAM_DESIGNWARE_QUIRK }, 102 { "MVEBU ", "CN9131 ", PCIE_ECAM_DESIGNWARE_QUIRK }, 103 { "MVEBU ", "CN9132 ", PCIE_ECAM_DESIGNWARE_QUIRK }, 104 { 0 }, 105 }; 106 107 /* Forward prototypes */ 108 109 static int generic_pcie_acpi_probe(device_t dev); 110 static ACPI_STATUS pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *, void *); 111 static int generic_pcie_acpi_read_ivar(device_t, device_t, int, uintptr_t *); 112 113 /* 114 * generic_pcie_acpi_probe - look for root bridge flag 115 */ 116 static int 117 generic_pcie_acpi_probe(device_t dev) 118 { 119 ACPI_DEVICE_INFO *devinfo; 120 ACPI_HANDLE h; 121 int root; 122 123 if (acpi_disabled("pcib") || (h = acpi_get_handle(dev)) == NULL || 124 ACPI_FAILURE(AcpiGetObjectInfo(h, &devinfo))) 125 return (ENXIO); 126 root = (devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0; 127 AcpiOsFree(devinfo); 128 if (!root) 129 return (ENXIO); 130 131 device_set_desc(dev, "Generic PCI host controller"); 132 return (BUS_PROBE_GENERIC); 133 } 134 135 /* 136 * pci_host_generic_acpi_parse_resource - parse PCI memory, IO and bus spaces 137 * 'produced' by this bridge 138 */ 139 static ACPI_STATUS 140 pci_host_generic_acpi_parse_resource(ACPI_RESOURCE *res, void *arg) 141 { 142 device_t dev = (device_t)arg; 143 struct generic_pcie_acpi_softc *sc; 144 rman_res_t min, max, off; 145 int r; 146 147 sc = device_get_softc(dev); 148 r = sc->base.nranges; 149 switch (res->Type) { 150 case ACPI_RESOURCE_TYPE_ADDRESS16: 151 min = res->Data.Address16.Address.Minimum; 152 max = res->Data.Address16.Address.Maximum; 153 break; 154 case ACPI_RESOURCE_TYPE_ADDRESS32: 155 min = res->Data.Address32.Address.Minimum; 156 max = res->Data.Address32.Address.Maximum; 157 off = res->Data.Address32.Address.TranslationOffset; 158 break; 159 case ACPI_RESOURCE_TYPE_ADDRESS64: 160 min = res->Data.Address64.Address.Minimum; 161 max = res->Data.Address64.Address.Maximum; 162 off = res->Data.Address64.Address.TranslationOffset; 163 break; 164 default: 165 return (AE_OK); 166 } 167 168 /* Save detected ranges */ 169 if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE || 170 res->Data.Address.ResourceType == ACPI_IO_RANGE) { 171 sc->base.ranges[r].pci_base = min; 172 sc->base.ranges[r].phys_base = min + off; 173 sc->base.ranges[r].size = max - min + 1; 174 if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE) 175 sc->base.ranges[r].flags |= FLAG_TYPE_MEM; 176 else if (res->Data.Address.ResourceType == ACPI_IO_RANGE) 177 sc->base.ranges[r].flags |= FLAG_TYPE_IO; 178 sc->base.nranges++; 179 } else if (res->Data.Address.ResourceType == ACPI_BUS_NUMBER_RANGE) { 180 sc->base.bus_start = min; 181 sc->base.bus_end = max; 182 } 183 return (AE_OK); 184 } 185 186 static void 187 pci_host_acpi_get_oem_quirks(struct generic_pcie_acpi_softc *sc, 188 ACPI_TABLE_HEADER *hdr) 189 { 190 int i; 191 192 for (i = 0; pci_acpi_quirks[i].quirks; i++) { 193 if (memcmp(hdr->OemId, pci_acpi_quirks[i].oem_id, 194 ACPI_OEM_ID_SIZE) != 0) 195 continue; 196 if (memcmp(hdr->OemTableId, pci_acpi_quirks[i].oem_table_id, 197 ACPI_OEM_TABLE_ID_SIZE) != 0) 198 continue; 199 sc->base.quirks |= pci_acpi_quirks[i].quirks; 200 } 201 } 202 203 static int 204 pci_host_acpi_get_ecam_resource(device_t dev) 205 { 206 struct generic_pcie_acpi_softc *sc; 207 struct acpi_device *ad; 208 struct resource_list *rl; 209 ACPI_TABLE_HEADER *hdr; 210 ACPI_MCFG_ALLOCATION *mcfg_entry, *mcfg_end; 211 ACPI_HANDLE handle; 212 ACPI_STATUS status; 213 rman_res_t base, start, end; 214 int found, val; 215 216 sc = device_get_softc(dev); 217 handle = acpi_get_handle(dev); 218 219 /* Try MCFG first */ 220 status = AcpiGetTable(ACPI_SIG_MCFG, 1, &hdr); 221 if (ACPI_SUCCESS(status)) { 222 found = FALSE; 223 mcfg_end = (ACPI_MCFG_ALLOCATION *)((char *)hdr + hdr->Length); 224 mcfg_entry = (ACPI_MCFG_ALLOCATION *)((ACPI_TABLE_MCFG *)hdr + 1); 225 while (mcfg_entry < mcfg_end && !found) { 226 if (mcfg_entry->PciSegment == sc->base.ecam && 227 mcfg_entry->StartBusNumber <= sc->base.bus_start && 228 mcfg_entry->EndBusNumber >= sc->base.bus_start) 229 found = TRUE; 230 else 231 mcfg_entry++; 232 } 233 if (found) { 234 if (mcfg_entry->EndBusNumber < sc->base.bus_end) 235 sc->base.bus_end = mcfg_entry->EndBusNumber; 236 base = mcfg_entry->Address; 237 } else { 238 device_printf(dev, "MCFG exists, but does not have bus %d-%d\n", 239 sc->base.bus_start, sc->base.bus_end); 240 return (ENXIO); 241 } 242 pci_host_acpi_get_oem_quirks(sc, hdr); 243 if (sc->base.quirks & PCIE_ECAM_DESIGNWARE_QUIRK) 244 device_set_desc(dev, "Synopsys DesignWare PCIe Controller"); 245 } else { 246 status = acpi_GetInteger(handle, "_CBA", &val); 247 if (ACPI_SUCCESS(status)) 248 base = val; 249 else 250 return (ENXIO); 251 } 252 253 /* add as MEM rid 0 */ 254 ad = device_get_ivars(dev); 255 rl = &ad->ad_rl; 256 start = base + (sc->base.bus_start << PCIE_BUS_SHIFT); 257 end = base + ((sc->base.bus_end + 1) << PCIE_BUS_SHIFT) - 1; 258 resource_list_add(rl, SYS_RES_MEMORY, 0, start, end, end - start + 1); 259 if (bootverbose) 260 device_printf(dev, "ECAM for bus %d-%d at mem %jx-%jx\n", 261 sc->base.bus_start, sc->base.bus_end, start, end); 262 return (0); 263 } 264 265 int 266 pci_host_generic_acpi_init(device_t dev) 267 { 268 struct generic_pcie_acpi_softc *sc; 269 ACPI_HANDLE handle; 270 ACPI_STATUS status; 271 int error; 272 273 sc = device_get_softc(dev); 274 handle = acpi_get_handle(dev); 275 276 /* Get Start bus number for the PCI host bus is from _BBN method */ 277 status = acpi_GetInteger(handle, "_BBN", &sc->base.bus_start); 278 if (ACPI_FAILURE(status)) { 279 device_printf(dev, "No _BBN, using start bus 0\n"); 280 sc->base.bus_start = 0; 281 } 282 sc->base.bus_end = 255; 283 284 /* Get PCI Segment (domain) needed for MCFG lookup */ 285 status = acpi_GetInteger(handle, "_SEG", &sc->base.ecam); 286 if (ACPI_FAILURE(status)) { 287 device_printf(dev, "No _SEG for PCI Bus, using segment 0\n"); 288 sc->base.ecam = 0; 289 } 290 291 /* Bus decode ranges */ 292 status = AcpiWalkResources(handle, "_CRS", 293 pci_host_generic_acpi_parse_resource, (void *)dev); 294 if (ACPI_FAILURE(status)) 295 return (ENXIO); 296 297 /* Coherency attribute */ 298 if (ACPI_FAILURE(acpi_GetInteger(handle, "_CCA", &sc->base.coherent))) 299 sc->base.coherent = 0; 300 if (bootverbose) 301 device_printf(dev, "Bus is%s cache-coherent\n", 302 sc->base.coherent ? "" : " not"); 303 304 /* add config space resource */ 305 pci_host_acpi_get_ecam_resource(dev); 306 acpi_pcib_fetch_prt(dev, &sc->ap_prt); 307 308 error = pci_host_generic_core_attach(dev); 309 if (error != 0) 310 return (error); 311 312 return (0); 313 } 314 315 static int 316 pci_host_generic_acpi_attach(device_t dev) 317 { 318 int error; 319 320 error = pci_host_generic_acpi_init(dev); 321 if (error != 0) 322 return (error); 323 324 device_add_child(dev, "pci", -1); 325 return (bus_generic_attach(dev)); 326 } 327 328 static int 329 generic_pcie_acpi_read_ivar(device_t dev, device_t child, int index, 330 uintptr_t *result) 331 { 332 struct generic_pcie_acpi_softc *sc; 333 334 sc = device_get_softc(dev); 335 336 if (index == PCIB_IVAR_BUS) { 337 *result = sc->base.bus_start; 338 return (0); 339 } 340 341 if (index == PCIB_IVAR_DOMAIN) { 342 *result = sc->base.ecam; 343 return (0); 344 } 345 346 if (bootverbose) 347 device_printf(dev, "ERROR: Unknown index %d.\n", index); 348 return (ENOENT); 349 } 350 351 static int 352 generic_pcie_acpi_route_interrupt(device_t bus, device_t dev, int pin) 353 { 354 struct generic_pcie_acpi_softc *sc; 355 356 sc = device_get_softc(bus); 357 return (acpi_pcib_route_interrupt(bus, dev, pin, &sc->ap_prt)); 358 } 359 360 static u_int 361 generic_pcie_get_xref(device_t pci, device_t child) 362 { 363 struct generic_pcie_acpi_softc *sc; 364 uintptr_t rid; 365 u_int xref, devid; 366 int err; 367 368 sc = device_get_softc(pci); 369 err = pcib_get_id(pci, child, PCI_ID_RID, &rid); 370 if (err != 0) 371 return (ACPI_MSI_XREF); 372 err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid); 373 if (err != 0) 374 return (ACPI_MSI_XREF); 375 return (xref); 376 } 377 378 static u_int 379 generic_pcie_map_id(device_t pci, device_t child, uintptr_t *id) 380 { 381 struct generic_pcie_acpi_softc *sc; 382 uintptr_t rid; 383 u_int xref, devid; 384 int err; 385 386 sc = device_get_softc(pci); 387 err = pcib_get_id(pci, child, PCI_ID_RID, &rid); 388 if (err != 0) 389 return (err); 390 err = acpi_iort_map_pci_msi(sc->base.ecam, rid, &xref, &devid); 391 if (err == 0) 392 *id = devid; 393 else 394 *id = rid; /* RID not in IORT, likely FW bug, ignore */ 395 return (0); 396 } 397 398 static int 399 generic_pcie_acpi_alloc_msi(device_t pci, device_t child, int count, 400 int maxcount, int *irqs) 401 { 402 403 #if defined(INTRNG) 404 return (intr_alloc_msi(pci, child, generic_pcie_get_xref(pci, child), 405 count, maxcount, irqs)); 406 #else 407 return (ENXIO); 408 #endif 409 } 410 411 static int 412 generic_pcie_acpi_release_msi(device_t pci, device_t child, int count, 413 int *irqs) 414 { 415 416 #if defined(INTRNG) 417 return (intr_release_msi(pci, child, generic_pcie_get_xref(pci, child), 418 count, irqs)); 419 #else 420 return (ENXIO); 421 #endif 422 } 423 424 static int 425 generic_pcie_acpi_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 426 uint32_t *data) 427 { 428 429 #if defined(INTRNG) 430 return (intr_map_msi(pci, child, generic_pcie_get_xref(pci, child), irq, 431 addr, data)); 432 #else 433 return (ENXIO); 434 #endif 435 } 436 437 static int 438 generic_pcie_acpi_alloc_msix(device_t pci, device_t child, int *irq) 439 { 440 441 #if defined(INTRNG) 442 return (intr_alloc_msix(pci, child, generic_pcie_get_xref(pci, child), 443 irq)); 444 #else 445 return (ENXIO); 446 #endif 447 } 448 449 static int 450 generic_pcie_acpi_release_msix(device_t pci, device_t child, int irq) 451 { 452 453 #if defined(INTRNG) 454 return (intr_release_msix(pci, child, generic_pcie_get_xref(pci, child), 455 irq)); 456 #else 457 return (ENXIO); 458 #endif 459 } 460 461 static int 462 generic_pcie_acpi_get_id(device_t pci, device_t child, enum pci_id_type type, 463 uintptr_t *id) 464 { 465 466 if (type == PCI_ID_MSI) 467 return (generic_pcie_map_id(pci, child, id)); 468 else 469 return (pcib_get_id(pci, child, type, id)); 470 } 471 472 static device_method_t generic_pcie_acpi_methods[] = { 473 DEVMETHOD(device_probe, generic_pcie_acpi_probe), 474 DEVMETHOD(device_attach, pci_host_generic_acpi_attach), 475 DEVMETHOD(bus_read_ivar, generic_pcie_acpi_read_ivar), 476 477 /* pcib interface */ 478 DEVMETHOD(pcib_route_interrupt, generic_pcie_acpi_route_interrupt), 479 DEVMETHOD(pcib_alloc_msi, generic_pcie_acpi_alloc_msi), 480 DEVMETHOD(pcib_release_msi, generic_pcie_acpi_release_msi), 481 DEVMETHOD(pcib_alloc_msix, generic_pcie_acpi_alloc_msix), 482 DEVMETHOD(pcib_release_msix, generic_pcie_acpi_release_msix), 483 DEVMETHOD(pcib_map_msi, generic_pcie_acpi_map_msi), 484 DEVMETHOD(pcib_get_id, generic_pcie_acpi_get_id), 485 486 DEVMETHOD_END 487 }; 488 489 DEFINE_CLASS_1(pcib, generic_pcie_acpi_driver, generic_pcie_acpi_methods, 490 sizeof(struct generic_pcie_acpi_softc), generic_pcie_core_driver); 491 492 static devclass_t generic_pcie_acpi_devclass; 493 494 DRIVER_MODULE(pcib, acpi, generic_pcie_acpi_driver, generic_pcie_acpi_devclass, 495 0, 0); 496