1 /* 2 * Copyright (c) 2015, 2020 Ruslan Bukin <br@bsdpad.com> 3 * Copyright (c) 2015 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This software was developed by Semihalf. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * 30 * $FreeBSD$ 31 * 32 */ 33 34 #ifndef __PCI_HOST_GENERIC_H_ 35 #define __PCI_HOST_GENERIC_H_ 36 37 #include "pci_if.h" 38 39 /* Assembling ECAM Configuration Address */ 40 #define PCIE_BUS_SHIFT 20 41 #define PCIE_SLOT_SHIFT 15 42 #define PCIE_FUNC_SHIFT 12 43 #define PCIE_BUS_MASK 0xFF 44 #define PCIE_SLOT_MASK 0x1F 45 #define PCIE_FUNC_MASK 0x07 46 #define PCIE_REG_MASK 0xFFF 47 48 #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \ 49 ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \ 50 (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \ 51 (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \ 52 ((reg) & PCIE_REG_MASK)) 53 54 #define MAX_RANGES_TUPLES 16 55 #define MIN_RANGES_TUPLES 2 56 57 struct pcie_range { 58 uint64_t pci_base; 59 uint64_t phys_base; 60 uint64_t size; 61 uint64_t flags; 62 #define FLAG_TYPE(x) ((x) & FLAG_TYPE_MASK) 63 #define FLAG_TYPE_MASK 0x3 64 #define FLAG_TYPE_INVALID 0x0 65 #define FLAG_TYPE_IO 0x1 66 #define FLAG_TYPE_MEM 0x2 67 #define FLAG_TYPE_PMEM 0x3 68 }; 69 70 struct generic_pcie_core_softc { 71 struct pcie_range ranges[MAX_RANGES_TUPLES]; 72 int nranges; 73 int coherent; 74 bool has_pmem; 75 struct rman pmem_rman; 76 struct rman mem_rman; 77 struct rman io_rman; 78 struct resource *res; 79 struct resource *res1; 80 int bus_start; 81 int bus_end; 82 int ecam; 83 bus_space_tag_t bst; 84 bus_space_handle_t bsh; 85 device_t dev; 86 bus_space_handle_t ioh; 87 bus_dma_tag_t dmat; 88 }; 89 90 DECLARE_CLASS(generic_pcie_core_driver); 91 92 int pci_host_generic_core_attach(device_t); 93 struct resource *pci_host_generic_core_alloc_resource(device_t, device_t, int, 94 int *, rman_res_t, rman_res_t, rman_res_t, u_int); 95 int pci_host_generic_core_release_resource(device_t, device_t, int, int, 96 struct resource *); 97 98 #endif /* __PCI_HOST_GENERIC_H_ */ 99