1 /*- 2 * Copyright (c) 2015, 2020 Ruslan Bukin <br@bsdpad.com> 3 * Copyright (c) 2014 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This software was developed by Semihalf under 7 * the sponsorship of the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* Generic ECAM PCIe driver */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include "opt_platform.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/rman.h> 43 #include <sys/module.h> 44 #include <sys/bus.h> 45 #include <sys/endian.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcib_private.h> 50 #include <dev/pci/pci_host_generic.h> 51 52 #include <machine/bus.h> 53 #include <machine/intr.h> 54 55 #include "pcib_if.h" 56 57 /* Forward prototypes */ 58 59 static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot, 60 u_int func, u_int reg, int bytes); 61 static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot, 62 u_int func, u_int reg, uint32_t val, int bytes); 63 static int generic_pcie_maxslots(device_t dev); 64 static int generic_pcie_read_ivar(device_t dev, device_t child, int index, 65 uintptr_t *result); 66 static int generic_pcie_write_ivar(device_t dev, device_t child, int index, 67 uintptr_t value); 68 69 int 70 pci_host_generic_core_attach(device_t dev) 71 { 72 struct generic_pcie_core_softc *sc; 73 uint64_t phys_base; 74 uint64_t pci_base; 75 uint64_t size; 76 int error; 77 int rid, tuple; 78 79 sc = device_get_softc(dev); 80 sc->dev = dev; 81 82 /* Create the parent DMA tag to pass down the coherent flag */ 83 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 84 1, 0, /* alignment, bounds */ 85 BUS_SPACE_MAXADDR, /* lowaddr */ 86 BUS_SPACE_MAXADDR, /* highaddr */ 87 NULL, NULL, /* filter, filterarg */ 88 BUS_SPACE_MAXSIZE, /* maxsize */ 89 BUS_SPACE_UNRESTRICTED, /* nsegments */ 90 BUS_SPACE_MAXSIZE, /* maxsegsize */ 91 sc->coherent ? BUS_DMA_COHERENT : 0, /* flags */ 92 NULL, NULL, /* lockfunc, lockarg */ 93 &sc->dmat); 94 if (error != 0) 95 return (error); 96 97 rid = 0; 98 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 99 if (sc->res == NULL) { 100 device_printf(dev, "could not map memory.\n"); 101 return (ENXIO); 102 } 103 104 sc->bst = rman_get_bustag(sc->res); 105 sc->bsh = rman_get_bushandle(sc->res); 106 107 sc->has_pmem = false; 108 sc->pmem_rman.rm_type = RMAN_ARRAY; 109 sc->pmem_rman.rm_descr = "PCIe Prefetch Memory"; 110 111 sc->mem_rman.rm_type = RMAN_ARRAY; 112 sc->mem_rman.rm_descr = "PCIe Memory"; 113 114 sc->io_rman.rm_type = RMAN_ARRAY; 115 sc->io_rman.rm_descr = "PCIe IO window"; 116 117 /* Initialize rman and allocate memory regions */ 118 error = rman_init(&sc->pmem_rman); 119 if (error) { 120 device_printf(dev, "rman_init() failed. error = %d\n", error); 121 return (error); 122 } 123 124 error = rman_init(&sc->mem_rman); 125 if (error) { 126 device_printf(dev, "rman_init() failed. error = %d\n", error); 127 return (error); 128 } 129 130 error = rman_init(&sc->io_rman); 131 if (error) { 132 device_printf(dev, "rman_init() failed. error = %d\n", error); 133 return (error); 134 } 135 136 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { 137 phys_base = sc->ranges[tuple].phys_base; 138 pci_base = sc->ranges[tuple].pci_base; 139 size = sc->ranges[tuple].size; 140 if (phys_base == 0 || size == 0) 141 continue; /* empty range element */ 142 switch (FLAG_TYPE(sc->ranges[tuple].flags)) { 143 case FLAG_TYPE_PMEM: 144 sc->has_pmem = true; 145 error = rman_manage_region(&sc->pmem_rman, 146 pci_base, pci_base + size - 1); 147 break; 148 case FLAG_TYPE_MEM: 149 error = rman_manage_region(&sc->mem_rman, 150 pci_base, pci_base + size - 1); 151 break; 152 case FLAG_TYPE_IO: 153 error = rman_manage_region(&sc->io_rman, 154 pci_base, pci_base + size - 1); 155 break; 156 default: 157 continue; 158 } 159 if (error) { 160 device_printf(dev, "rman_manage_region() failed." 161 "error = %d\n", error); 162 rman_fini(&sc->pmem_rman); 163 rman_fini(&sc->mem_rman); 164 rman_fini(&sc->io_rman); 165 return (error); 166 } 167 } 168 169 return (0); 170 } 171 172 static uint32_t 173 generic_pcie_read_config(device_t dev, u_int bus, u_int slot, 174 u_int func, u_int reg, int bytes) 175 { 176 struct generic_pcie_core_softc *sc; 177 bus_space_handle_t h; 178 bus_space_tag_t t; 179 uint64_t offset; 180 uint32_t data; 181 182 sc = device_get_softc(dev); 183 if ((bus < sc->bus_start) || (bus > sc->bus_end)) 184 return (~0U); 185 if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || 186 (reg > PCIE_REGMAX)) 187 return (~0U); 188 189 offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg); 190 t = sc->bst; 191 h = sc->bsh; 192 193 switch (bytes) { 194 case 1: 195 data = bus_space_read_1(t, h, offset); 196 break; 197 case 2: 198 data = le16toh(bus_space_read_2(t, h, offset)); 199 break; 200 case 4: 201 data = le32toh(bus_space_read_4(t, h, offset)); 202 break; 203 default: 204 return (~0U); 205 } 206 207 return (data); 208 } 209 210 static void 211 generic_pcie_write_config(device_t dev, u_int bus, u_int slot, 212 u_int func, u_int reg, uint32_t val, int bytes) 213 { 214 struct generic_pcie_core_softc *sc; 215 bus_space_handle_t h; 216 bus_space_tag_t t; 217 uint64_t offset; 218 219 sc = device_get_softc(dev); 220 if ((bus < sc->bus_start) || (bus > sc->bus_end)) 221 return; 222 if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || 223 (reg > PCIE_REGMAX)) 224 return; 225 226 offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg); 227 228 t = sc->bst; 229 h = sc->bsh; 230 231 switch (bytes) { 232 case 1: 233 bus_space_write_1(t, h, offset, val); 234 break; 235 case 2: 236 bus_space_write_2(t, h, offset, htole16(val)); 237 break; 238 case 4: 239 bus_space_write_4(t, h, offset, htole32(val)); 240 break; 241 default: 242 return; 243 } 244 } 245 246 static int 247 generic_pcie_maxslots(device_t dev) 248 { 249 250 return (31); /* max slots per bus acc. to standard */ 251 } 252 253 static int 254 generic_pcie_read_ivar(device_t dev, device_t child, int index, 255 uintptr_t *result) 256 { 257 struct generic_pcie_core_softc *sc; 258 259 sc = device_get_softc(dev); 260 261 if (index == PCIB_IVAR_BUS) { 262 *result = sc->bus_start; 263 return (0); 264 265 } 266 267 if (index == PCIB_IVAR_DOMAIN) { 268 *result = sc->ecam; 269 return (0); 270 } 271 272 if (bootverbose) 273 device_printf(dev, "ERROR: Unknown index %d.\n", index); 274 return (ENOENT); 275 } 276 277 static int 278 generic_pcie_write_ivar(device_t dev, device_t child, int index, 279 uintptr_t value) 280 { 281 282 return (ENOENT); 283 } 284 285 static struct rman * 286 generic_pcie_rman(struct generic_pcie_core_softc *sc, int type, int flags) 287 { 288 289 switch (type) { 290 case SYS_RES_IOPORT: 291 return (&sc->io_rman); 292 case SYS_RES_MEMORY: 293 if (sc->has_pmem && (flags & RF_PREFETCHABLE) != 0) 294 return (&sc->pmem_rman); 295 return (&sc->mem_rman); 296 default: 297 break; 298 } 299 300 return (NULL); 301 } 302 303 int 304 pci_host_generic_core_release_resource(device_t dev, device_t child, int type, 305 int rid, struct resource *res) 306 { 307 struct generic_pcie_core_softc *sc; 308 struct rman *rm; 309 310 sc = device_get_softc(dev); 311 312 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 313 if (type == PCI_RES_BUS) { 314 return (pci_domain_release_bus(sc->ecam, child, rid, res)); 315 } 316 #endif 317 318 rm = generic_pcie_rman(sc, type, rman_get_flags(res)); 319 if (rm != NULL) { 320 KASSERT(rman_is_region_manager(res, rm), ("rman mismatch")); 321 rman_release_resource(res); 322 } 323 324 return (bus_generic_release_resource(dev, child, type, rid, res)); 325 } 326 327 static bool 328 generic_pcie_translate_resource(device_t dev, int type, rman_res_t start, 329 rman_res_t end, rman_res_t *new_start, rman_res_t *new_end) 330 { 331 struct generic_pcie_core_softc *sc; 332 uint64_t phys_base; 333 uint64_t pci_base; 334 uint64_t size; 335 int i, space; 336 bool found; 337 338 sc = device_get_softc(dev); 339 /* Translate the address from a PCI address to a physical address */ 340 switch (type) { 341 case SYS_RES_IOPORT: 342 case SYS_RES_MEMORY: 343 found = false; 344 for (i = 0; i < MAX_RANGES_TUPLES; i++) { 345 pci_base = sc->ranges[i].pci_base; 346 phys_base = sc->ranges[i].phys_base; 347 size = sc->ranges[i].size; 348 349 if (start < pci_base || start >= pci_base + size) 350 continue; 351 352 switch (FLAG_TYPE(sc->ranges[i].flags)) { 353 case FLAG_TYPE_MEM: 354 case FLAG_TYPE_PMEM: 355 space = SYS_RES_MEMORY; 356 break; 357 case FLAG_TYPE_IO: 358 space = SYS_RES_IOPORT; 359 break; 360 default: 361 space = -1; 362 continue; 363 } 364 365 if (type == space) { 366 *new_start = start - pci_base + phys_base; 367 *new_end = end - pci_base + phys_base; 368 found = true; 369 break; 370 } 371 } 372 break; 373 default: 374 /* No translation for non-memory types */ 375 *new_start = start; 376 *new_end = end; 377 found = true; 378 break; 379 } 380 381 return (found); 382 } 383 384 struct resource * 385 pci_host_generic_core_alloc_resource(device_t dev, device_t child, int type, 386 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 387 { 388 struct generic_pcie_core_softc *sc; 389 struct resource *res; 390 struct rman *rm; 391 rman_res_t phys_start, phys_end; 392 393 sc = device_get_softc(dev); 394 395 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 396 if (type == PCI_RES_BUS) { 397 return (pci_domain_alloc_bus(sc->ecam, child, rid, start, end, 398 count, flags)); 399 } 400 #endif 401 402 rm = generic_pcie_rman(sc, type, flags); 403 if (rm == NULL) 404 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 405 type, rid, start, end, count, flags)); 406 407 /* Translate the address from a PCI address to a physical address */ 408 if (!generic_pcie_translate_resource(dev, type, start, end, &phys_start, 409 &phys_end)) { 410 device_printf(dev, 411 "Failed to translate resource %jx-%jx type %x for %s\n", 412 (uintmax_t)start, (uintmax_t)end, type, 413 device_get_nameunit(child)); 414 return (NULL); 415 } 416 417 if (bootverbose) { 418 device_printf(dev, 419 "rman_reserve_resource: start=%#jx, end=%#jx, count=%#jx\n", 420 start, end, count); 421 } 422 423 res = rman_reserve_resource(rm, start, end, count, flags, child); 424 if (res == NULL) 425 goto fail; 426 427 rman_set_rid(res, *rid); 428 429 if (flags & RF_ACTIVE) 430 if (bus_activate_resource(child, type, *rid, res)) { 431 rman_release_resource(res); 432 goto fail; 433 } 434 435 return (res); 436 437 fail: 438 device_printf(dev, "%s FAIL: type=%d, rid=%d, " 439 "start=%016jx, end=%016jx, count=%016jx, flags=%x\n", 440 __func__, type, *rid, start, end, count, flags); 441 442 return (NULL); 443 } 444 445 static int 446 generic_pcie_activate_resource(device_t dev, device_t child, int type, 447 int rid, struct resource *r) 448 { 449 struct generic_pcie_core_softc *sc; 450 rman_res_t start, end; 451 int res; 452 453 sc = device_get_softc(dev); 454 455 if ((res = rman_activate_resource(r)) != 0) 456 return (res); 457 458 start = rman_get_start(r); 459 end = rman_get_end(r); 460 if (!generic_pcie_translate_resource(dev, type, start, end, &start, 461 &end)) 462 return (EINVAL); 463 rman_set_start(r, start); 464 rman_set_end(r, end); 465 466 return (BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child, type, 467 rid, r)); 468 } 469 470 static int 471 generic_pcie_deactivate_resource(device_t dev, device_t child, int type, 472 int rid, struct resource *r) 473 { 474 int res; 475 476 if ((res = rman_deactivate_resource(r)) != 0) 477 return (res); 478 479 switch (type) { 480 case SYS_RES_IOPORT: 481 case SYS_RES_MEMORY: 482 case SYS_RES_IRQ: 483 res = BUS_DEACTIVATE_RESOURCE(device_get_parent(dev), child, 484 type, rid, r); 485 break; 486 default: 487 break; 488 } 489 490 return (res); 491 } 492 493 static int 494 generic_pcie_adjust_resource(device_t dev, device_t child, int type, 495 struct resource *res, rman_res_t start, rman_res_t end) 496 { 497 struct generic_pcie_core_softc *sc; 498 struct rman *rm; 499 500 sc = device_get_softc(dev); 501 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 502 if (type == PCI_RES_BUS) 503 return (pci_domain_adjust_bus(sc->ecam, child, res, start, 504 end)); 505 #endif 506 507 rm = generic_pcie_rman(sc, type, rman_get_flags(res)); 508 if (rm != NULL) 509 return (rman_adjust_resource(res, start, end)); 510 return (bus_generic_adjust_resource(dev, child, type, res, start, end)); 511 } 512 513 static bus_dma_tag_t 514 generic_pcie_get_dma_tag(device_t dev, device_t child) 515 { 516 struct generic_pcie_core_softc *sc; 517 518 sc = device_get_softc(dev); 519 return (sc->dmat); 520 } 521 522 static device_method_t generic_pcie_methods[] = { 523 DEVMETHOD(device_attach, pci_host_generic_core_attach), 524 DEVMETHOD(bus_read_ivar, generic_pcie_read_ivar), 525 DEVMETHOD(bus_write_ivar, generic_pcie_write_ivar), 526 DEVMETHOD(bus_alloc_resource, pci_host_generic_core_alloc_resource), 527 DEVMETHOD(bus_adjust_resource, generic_pcie_adjust_resource), 528 DEVMETHOD(bus_activate_resource, generic_pcie_activate_resource), 529 DEVMETHOD(bus_deactivate_resource, generic_pcie_deactivate_resource), 530 DEVMETHOD(bus_release_resource, pci_host_generic_core_release_resource), 531 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 532 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 533 534 DEVMETHOD(bus_get_dma_tag, generic_pcie_get_dma_tag), 535 536 /* pcib interface */ 537 DEVMETHOD(pcib_maxslots, generic_pcie_maxslots), 538 DEVMETHOD(pcib_read_config, generic_pcie_read_config), 539 DEVMETHOD(pcib_write_config, generic_pcie_write_config), 540 541 DEVMETHOD_END 542 }; 543 544 DEFINE_CLASS_0(pcib, generic_pcie_core_driver, 545 generic_pcie_methods, sizeof(struct generic_pcie_core_softc)); 546