1 /*- 2 * Copyright (c) 2015, 2020 Ruslan Bukin <br@bsdpad.com> 3 * Copyright (c) 2014 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This software was developed by Semihalf under 7 * the sponsorship of the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* Generic ECAM PCIe driver */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include "opt_platform.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/rman.h> 43 #include <sys/module.h> 44 #include <sys/bus.h> 45 #include <sys/endian.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcib_private.h> 50 #include <dev/pci/pci_host_generic.h> 51 52 #include <machine/bus.h> 53 #include <machine/intr.h> 54 55 #include "pcib_if.h" 56 57 #if defined(VM_MEMATTR_DEVICE_NP) 58 #define PCI_UNMAPPED 59 #define PCI_RF_FLAGS RF_UNMAPPED 60 #else 61 #define PCI_RF_FLAGS 0 62 #endif 63 64 65 /* Forward prototypes */ 66 67 static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot, 68 u_int func, u_int reg, int bytes); 69 static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot, 70 u_int func, u_int reg, uint32_t val, int bytes); 71 static int generic_pcie_maxslots(device_t dev); 72 static int generic_pcie_read_ivar(device_t dev, device_t child, int index, 73 uintptr_t *result); 74 static int generic_pcie_write_ivar(device_t dev, device_t child, int index, 75 uintptr_t value); 76 77 int 78 pci_host_generic_core_attach(device_t dev) 79 { 80 #ifdef PCI_UNMAPPED 81 struct resource_map_request req; 82 struct resource_map map; 83 #endif 84 struct generic_pcie_core_softc *sc; 85 uint64_t phys_base; 86 uint64_t pci_base; 87 uint64_t size; 88 int error; 89 int rid, tuple; 90 91 sc = device_get_softc(dev); 92 sc->dev = dev; 93 94 /* Create the parent DMA tag to pass down the coherent flag */ 95 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 96 1, 0, /* alignment, bounds */ 97 BUS_SPACE_MAXADDR, /* lowaddr */ 98 BUS_SPACE_MAXADDR, /* highaddr */ 99 NULL, NULL, /* filter, filterarg */ 100 BUS_SPACE_MAXSIZE, /* maxsize */ 101 BUS_SPACE_UNRESTRICTED, /* nsegments */ 102 BUS_SPACE_MAXSIZE, /* maxsegsize */ 103 sc->coherent ? BUS_DMA_COHERENT : 0, /* flags */ 104 NULL, NULL, /* lockfunc, lockarg */ 105 &sc->dmat); 106 if (error != 0) 107 return (error); 108 109 if ((sc->quirks & PCIE_CUSTOM_CONFIG_SPACE_QUIRK) == 0) { 110 rid = 0; 111 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 112 PCI_RF_FLAGS | RF_ACTIVE); 113 if (sc->res == NULL) { 114 device_printf(dev, "could not allocate memory.\n"); 115 error = ENXIO; 116 goto err_resource; 117 } 118 #ifdef PCI_UNMAPPED 119 resource_init_map_request(&req); 120 req.memattr = VM_MEMATTR_DEVICE_NP; 121 error = bus_map_resource(dev, SYS_RES_MEMORY, sc->res, &req, 122 &map); 123 if (error != 0) { 124 device_printf(dev, "could not map memory.\n"); 125 return (error); 126 } 127 rman_set_mapping(sc->res, &map); 128 #endif 129 } 130 131 sc->has_pmem = false; 132 sc->pmem_rman.rm_type = RMAN_ARRAY; 133 sc->pmem_rman.rm_descr = "PCIe Prefetch Memory"; 134 135 sc->mem_rman.rm_type = RMAN_ARRAY; 136 sc->mem_rman.rm_descr = "PCIe Memory"; 137 138 sc->io_rman.rm_type = RMAN_ARRAY; 139 sc->io_rman.rm_descr = "PCIe IO window"; 140 141 /* Initialize rman and allocate memory regions */ 142 error = rman_init(&sc->pmem_rman); 143 if (error) { 144 device_printf(dev, "rman_init() failed. error = %d\n", error); 145 goto err_pmem_rman; 146 } 147 148 error = rman_init(&sc->mem_rman); 149 if (error) { 150 device_printf(dev, "rman_init() failed. error = %d\n", error); 151 goto err_mem_rman; 152 } 153 154 error = rman_init(&sc->io_rman); 155 if (error) { 156 device_printf(dev, "rman_init() failed. error = %d\n", error); 157 goto err_io_rman; 158 } 159 160 for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { 161 phys_base = sc->ranges[tuple].phys_base; 162 pci_base = sc->ranges[tuple].pci_base; 163 size = sc->ranges[tuple].size; 164 if (phys_base == 0 || size == 0) 165 continue; /* empty range element */ 166 switch (FLAG_TYPE(sc->ranges[tuple].flags)) { 167 case FLAG_TYPE_PMEM: 168 sc->has_pmem = true; 169 error = rman_manage_region(&sc->pmem_rman, 170 pci_base, pci_base + size - 1); 171 break; 172 case FLAG_TYPE_MEM: 173 error = rman_manage_region(&sc->mem_rman, 174 pci_base, pci_base + size - 1); 175 break; 176 case FLAG_TYPE_IO: 177 error = rman_manage_region(&sc->io_rman, 178 pci_base, pci_base + size - 1); 179 break; 180 default: 181 continue; 182 } 183 if (error) { 184 device_printf(dev, "rman_manage_region() failed." 185 "error = %d\n", error); 186 goto err_rman_manage; 187 } 188 } 189 190 return (0); 191 192 err_rman_manage: 193 rman_fini(&sc->io_rman); 194 err_io_rman: 195 rman_fini(&sc->mem_rman); 196 err_mem_rman: 197 rman_fini(&sc->pmem_rman); 198 err_pmem_rman: 199 if (sc->res != NULL) 200 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res); 201 err_resource: 202 bus_dma_tag_destroy(sc->dmat); 203 return (error); 204 } 205 206 int 207 pci_host_generic_core_detach(device_t dev) 208 { 209 struct generic_pcie_core_softc *sc; 210 int error; 211 212 sc = device_get_softc(dev); 213 214 error = bus_generic_detach(dev); 215 if (error != 0) 216 return (error); 217 218 rman_fini(&sc->io_rman); 219 rman_fini(&sc->mem_rman); 220 rman_fini(&sc->pmem_rman); 221 if (sc->res != NULL) 222 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res); 223 bus_dma_tag_destroy(sc->dmat); 224 225 return (0); 226 } 227 228 static uint32_t 229 generic_pcie_read_config(device_t dev, u_int bus, u_int slot, 230 u_int func, u_int reg, int bytes) 231 { 232 struct generic_pcie_core_softc *sc; 233 uint64_t offset; 234 uint32_t data; 235 236 sc = device_get_softc(dev); 237 if ((bus < sc->bus_start) || (bus > sc->bus_end)) 238 return (~0U); 239 if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || 240 (reg > PCIE_REGMAX)) 241 return (~0U); 242 if ((sc->quirks & PCIE_ECAM_DESIGNWARE_QUIRK) && bus == 0 && slot > 0) 243 return (~0U); 244 245 offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg); 246 247 switch (bytes) { 248 case 1: 249 data = bus_read_1(sc->res, offset); 250 break; 251 case 2: 252 data = le16toh(bus_read_2(sc->res, offset)); 253 break; 254 case 4: 255 data = le32toh(bus_read_4(sc->res, offset)); 256 break; 257 default: 258 return (~0U); 259 } 260 261 return (data); 262 } 263 264 static void 265 generic_pcie_write_config(device_t dev, u_int bus, u_int slot, 266 u_int func, u_int reg, uint32_t val, int bytes) 267 { 268 struct generic_pcie_core_softc *sc; 269 uint64_t offset; 270 271 sc = device_get_softc(dev); 272 if ((bus < sc->bus_start) || (bus > sc->bus_end)) 273 return; 274 if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || 275 (reg > PCIE_REGMAX)) 276 return; 277 278 offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg); 279 280 switch (bytes) { 281 case 1: 282 bus_write_1(sc->res, offset, val); 283 break; 284 case 2: 285 bus_write_2(sc->res, offset, htole16(val)); 286 break; 287 case 4: 288 bus_write_4(sc->res, offset, htole32(val)); 289 break; 290 default: 291 return; 292 } 293 } 294 295 static int 296 generic_pcie_maxslots(device_t dev) 297 { 298 299 return (31); /* max slots per bus acc. to standard */ 300 } 301 302 static int 303 generic_pcie_read_ivar(device_t dev, device_t child, int index, 304 uintptr_t *result) 305 { 306 struct generic_pcie_core_softc *sc; 307 308 sc = device_get_softc(dev); 309 310 if (index == PCIB_IVAR_BUS) { 311 *result = sc->bus_start; 312 return (0); 313 } 314 315 if (index == PCIB_IVAR_DOMAIN) { 316 *result = sc->ecam; 317 return (0); 318 } 319 320 if (bootverbose) 321 device_printf(dev, "ERROR: Unknown index %d.\n", index); 322 return (ENOENT); 323 } 324 325 static int 326 generic_pcie_write_ivar(device_t dev, device_t child, int index, 327 uintptr_t value) 328 { 329 330 return (ENOENT); 331 } 332 333 static struct rman * 334 generic_pcie_rman(struct generic_pcie_core_softc *sc, int type, int flags) 335 { 336 337 switch (type) { 338 case SYS_RES_IOPORT: 339 return (&sc->io_rman); 340 case SYS_RES_MEMORY: 341 if (sc->has_pmem && (flags & RF_PREFETCHABLE) != 0) 342 return (&sc->pmem_rman); 343 return (&sc->mem_rman); 344 default: 345 break; 346 } 347 348 return (NULL); 349 } 350 351 int 352 pci_host_generic_core_release_resource(device_t dev, device_t child, int type, 353 int rid, struct resource *res) 354 { 355 struct generic_pcie_core_softc *sc; 356 struct rman *rm; 357 int error; 358 359 sc = device_get_softc(dev); 360 361 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 362 if (type == PCI_RES_BUS) { 363 return (pci_domain_release_bus(sc->ecam, child, rid, res)); 364 } 365 #endif 366 367 rm = generic_pcie_rman(sc, type, rman_get_flags(res)); 368 if (rm != NULL) { 369 KASSERT(rman_is_region_manager(res, rm), ("rman mismatch")); 370 if (rman_get_flags(res) & RF_ACTIVE) { 371 error = bus_deactivate_resource(child, type, rid, res); 372 if (error) 373 return (error); 374 } 375 return (rman_release_resource(res)); 376 } 377 378 return (bus_generic_release_resource(dev, child, type, rid, res)); 379 } 380 381 static int 382 generic_pcie_translate_resource_common(device_t dev, int type, rman_res_t start, 383 rman_res_t end, rman_res_t *new_start, rman_res_t *new_end) 384 { 385 struct generic_pcie_core_softc *sc; 386 uint64_t phys_base; 387 uint64_t pci_base; 388 uint64_t size; 389 int i, space; 390 bool found; 391 392 sc = device_get_softc(dev); 393 /* Translate the address from a PCI address to a physical address */ 394 switch (type) { 395 case SYS_RES_IOPORT: 396 case SYS_RES_MEMORY: 397 found = false; 398 for (i = 0; i < MAX_RANGES_TUPLES; i++) { 399 pci_base = sc->ranges[i].pci_base; 400 phys_base = sc->ranges[i].phys_base; 401 size = sc->ranges[i].size; 402 403 if (start < pci_base || start >= pci_base + size) 404 continue; 405 406 switch (FLAG_TYPE(sc->ranges[i].flags)) { 407 case FLAG_TYPE_MEM: 408 case FLAG_TYPE_PMEM: 409 space = SYS_RES_MEMORY; 410 break; 411 case FLAG_TYPE_IO: 412 space = SYS_RES_IOPORT; 413 break; 414 default: 415 space = -1; 416 continue; 417 } 418 419 if (type == space) { 420 *new_start = start - pci_base + phys_base; 421 *new_end = end - pci_base + phys_base; 422 found = true; 423 break; 424 } 425 } 426 break; 427 default: 428 /* No translation for non-memory types */ 429 *new_start = start; 430 *new_end = end; 431 found = true; 432 break; 433 } 434 435 return (found ? 0 : ENOENT); 436 } 437 438 static int 439 generic_pcie_translate_resource(device_t bus, int type, 440 rman_res_t start, rman_res_t *newstart) 441 { 442 rman_res_t newend; /* unused */ 443 444 return (generic_pcie_translate_resource_common( 445 bus, type, start, 0, newstart, &newend)); 446 } 447 448 struct resource * 449 pci_host_generic_core_alloc_resource(device_t dev, device_t child, int type, 450 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 451 { 452 struct generic_pcie_core_softc *sc; 453 struct resource *res; 454 struct rman *rm; 455 456 sc = device_get_softc(dev); 457 458 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 459 if (type == PCI_RES_BUS) { 460 return (pci_domain_alloc_bus(sc->ecam, child, rid, start, end, 461 count, flags)); 462 } 463 #endif 464 465 rm = generic_pcie_rman(sc, type, flags); 466 if (rm == NULL) 467 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 468 type, rid, start, end, count, flags)); 469 470 if (bootverbose) { 471 device_printf(dev, 472 "rman_reserve_resource: start=%#jx, end=%#jx, count=%#jx\n", 473 start, end, count); 474 } 475 476 res = rman_reserve_resource(rm, start, end, count, flags, child); 477 if (res == NULL) 478 goto fail; 479 480 rman_set_rid(res, *rid); 481 482 if (flags & RF_ACTIVE) 483 if (bus_activate_resource(child, type, *rid, res)) { 484 rman_release_resource(res); 485 goto fail; 486 } 487 488 return (res); 489 490 fail: 491 device_printf(dev, "%s FAIL: type=%d, rid=%d, " 492 "start=%016jx, end=%016jx, count=%016jx, flags=%x\n", 493 __func__, type, *rid, start, end, count, flags); 494 495 return (NULL); 496 } 497 498 static int 499 generic_pcie_activate_resource(device_t dev, device_t child, int type, 500 int rid, struct resource *r) 501 { 502 rman_res_t start, end; 503 int res; 504 505 if ((res = rman_activate_resource(r)) != 0) 506 return (res); 507 508 start = rman_get_start(r); 509 end = rman_get_end(r); 510 res = generic_pcie_translate_resource_common(dev, type, start, end, 511 &start, &end); 512 if (res != 0) { 513 rman_deactivate_resource(r); 514 return (res); 515 } 516 rman_set_start(r, start); 517 rman_set_end(r, end); 518 519 return (BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child, type, 520 rid, r)); 521 } 522 523 static int 524 generic_pcie_deactivate_resource(device_t dev, device_t child, int type, 525 int rid, struct resource *r) 526 { 527 int res; 528 529 if ((res = rman_deactivate_resource(r)) != 0) 530 return (res); 531 532 switch (type) { 533 case SYS_RES_IOPORT: 534 case SYS_RES_MEMORY: 535 case SYS_RES_IRQ: 536 res = BUS_DEACTIVATE_RESOURCE(device_get_parent(dev), child, 537 type, rid, r); 538 break; 539 default: 540 break; 541 } 542 543 return (res); 544 } 545 546 static int 547 generic_pcie_adjust_resource(device_t dev, device_t child, int type, 548 struct resource *res, rman_res_t start, rman_res_t end) 549 { 550 struct generic_pcie_core_softc *sc; 551 struct rman *rm; 552 553 sc = device_get_softc(dev); 554 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 555 if (type == PCI_RES_BUS) 556 return (pci_domain_adjust_bus(sc->ecam, child, res, start, 557 end)); 558 #endif 559 560 rm = generic_pcie_rman(sc, type, rman_get_flags(res)); 561 if (rm != NULL) 562 return (rman_adjust_resource(res, start, end)); 563 return (bus_generic_adjust_resource(dev, child, type, res, start, end)); 564 } 565 566 static bus_dma_tag_t 567 generic_pcie_get_dma_tag(device_t dev, device_t child) 568 { 569 struct generic_pcie_core_softc *sc; 570 571 sc = device_get_softc(dev); 572 return (sc->dmat); 573 } 574 575 static device_method_t generic_pcie_methods[] = { 576 DEVMETHOD(device_attach, pci_host_generic_core_attach), 577 DEVMETHOD(device_detach, pci_host_generic_core_detach), 578 579 DEVMETHOD(bus_read_ivar, generic_pcie_read_ivar), 580 DEVMETHOD(bus_write_ivar, generic_pcie_write_ivar), 581 DEVMETHOD(bus_alloc_resource, pci_host_generic_core_alloc_resource), 582 DEVMETHOD(bus_adjust_resource, generic_pcie_adjust_resource), 583 DEVMETHOD(bus_activate_resource, generic_pcie_activate_resource), 584 DEVMETHOD(bus_deactivate_resource, generic_pcie_deactivate_resource), 585 DEVMETHOD(bus_release_resource, pci_host_generic_core_release_resource), 586 DEVMETHOD(bus_translate_resource, generic_pcie_translate_resource), 587 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 588 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 589 590 DEVMETHOD(bus_get_dma_tag, generic_pcie_get_dma_tag), 591 592 /* pcib interface */ 593 DEVMETHOD(pcib_maxslots, generic_pcie_maxslots), 594 DEVMETHOD(pcib_read_config, generic_pcie_read_config), 595 DEVMETHOD(pcib_write_config, generic_pcie_write_config), 596 597 DEVMETHOD_END 598 }; 599 600 DEFINE_CLASS_0(pcib, generic_pcie_core_driver, 601 generic_pcie_methods, sizeof(struct generic_pcie_core_softc)); 602