1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /* Armada 8k DesignWare PCIe driver */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/devmap.h> 39 #include <sys/proc.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/mutex.h> 44 #include <sys/rman.h> 45 #include <sys/sysctl.h> 46 47 #include <machine/bus.h> 48 #include <machine/intr.h> 49 #include <machine/resource.h> 50 51 #include <dev/extres/clk/clk.h> 52 #include <dev/extres/phy/phy.h> 53 #include <dev/ofw/ofw_bus.h> 54 #include <dev/ofw/ofw_bus_subr.h> 55 #include <dev/ofw/ofw_pci.h> 56 #include <dev/ofw/ofwpci.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcib_private.h> 60 #include <dev/pci/pci_dw.h> 61 62 #include "pcib_if.h" 63 #include "pci_dw_if.h" 64 65 #define MV_GLOBAL_CONTROL_REG 0x8000 66 #define PCIE_APP_LTSSM_EN (1 << 2) 67 68 #define MV_GLOBAL_STATUS_REG 0x8008 69 #define MV_STATUS_RDLH_LINK_UP (1 << 1) 70 #define MV_STATUS_PHY_LINK_UP (1 << 9) 71 72 #define MV_INT_CAUSE1 0x801C 73 #define MV_INT_MASK1 0x8020 74 #define INT_A_ASSERT_MASK (1 << 9) 75 #define INT_B_ASSERT_MASK (1 << 10) 76 #define INT_C_ASSERT_MASK (1 << 11) 77 #define INT_D_ASSERT_MASK (1 << 12) 78 79 #define MV_INT_CAUSE2 0x8024 80 #define MV_INT_MASK2 0x8028 81 #define MV_ERR_INT_CAUSE 0x802C 82 #define MV_ERR_INT_MASK 0x8030 83 84 #define MV_ARCACHE_TRC_REG 0x8050 85 #define MV_AWCACHE_TRC_REG 0x8054 86 #define MV_ARUSER_REG 0x805C 87 #define MV_AWUSER_REG 0x8060 88 89 #define MV_MAX_LANES 8 90 struct pci_mv_softc { 91 struct pci_dw_softc dw_sc; 92 device_t dev; 93 phandle_t node; 94 struct resource *irq_res; 95 void *intr_cookie; 96 phy_t phy[MV_MAX_LANES]; 97 clk_t clk_core; 98 clk_t clk_reg; 99 }; 100 101 /* Compatible devices. */ 102 static struct ofw_compat_data compat_data[] = { 103 {"marvell,armada8k-pcie", 1}, 104 {NULL, 0}, 105 }; 106 107 static int 108 pci_mv_phy_init(struct pci_mv_softc *sc) 109 { 110 int i, rv; 111 112 for (i = 0; i < MV_MAX_LANES; i++) { 113 rv = phy_get_by_ofw_idx(sc->dev, sc->node, i, &(sc->phy[i])); 114 if (rv != 0 && rv != ENOENT) { 115 device_printf(sc->dev, "Cannot get phy[%d]\n", i); 116 /* XXX revert when phy driver will be implemented */ 117 #if 0 118 goto fail; 119 #else 120 continue; 121 #endif 122 } 123 if (sc->phy[i] == NULL) 124 continue; 125 rv = phy_enable(sc->phy[i]); 126 if (rv != 0) { 127 device_printf(sc->dev, "Cannot enable phy[%d]\n", i); 128 goto fail; 129 } 130 } 131 return (0); 132 133 fail: 134 for (i = 0; i < MV_MAX_LANES; i++) { 135 if (sc->phy[i] == NULL) 136 continue; 137 phy_release(sc->phy[i]); 138 } 139 140 return (rv); 141 } 142 143 static void 144 pci_mv_init(struct pci_mv_softc *sc) 145 { 146 uint32_t reg; 147 148 149 /* Set device configuration to RC */ 150 reg = pci_dw_dbi_rd4(sc->dev, MV_GLOBAL_CONTROL_REG); 151 reg &= ~0x000000F0; 152 reg |= 0x000000040; 153 pci_dw_dbi_wr4(sc->dev, MV_GLOBAL_CONTROL_REG, reg); 154 155 /* AxCache master transaction attribures */ 156 pci_dw_dbi_wr4(sc->dev, MV_ARCACHE_TRC_REG, 0x3511); 157 pci_dw_dbi_wr4(sc->dev, MV_AWCACHE_TRC_REG, 0x5311); 158 159 /* AxDomain master transaction attribures */ 160 pci_dw_dbi_wr4(sc->dev, MV_ARUSER_REG, 0x0002); 161 pci_dw_dbi_wr4(sc->dev, MV_AWUSER_REG, 0x0002); 162 163 /* Enable all INTx interrupt (virtuual) pins */ 164 reg = pci_dw_dbi_rd4(sc->dev, MV_INT_MASK1); 165 reg |= INT_A_ASSERT_MASK | INT_B_ASSERT_MASK | 166 INT_C_ASSERT_MASK | INT_D_ASSERT_MASK; 167 pci_dw_dbi_wr4(sc->dev, MV_INT_MASK1, reg); 168 169 /* Enable local interrupts */ 170 pci_dw_dbi_wr4(sc->dev, DW_MSI_INTR0_MASK, 0xFFFFFFFF); 171 pci_dw_dbi_wr4(sc->dev, MV_INT_MASK1, 0xFFFFFFFF); 172 pci_dw_dbi_wr4(sc->dev, MV_INT_MASK2, 0xFFFFFFFD); 173 pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE1, 0xFFFFFFFF); 174 pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE2, 0xFFFFFFFF); 175 176 /* Errors have own interrupt, not yet populated in DTt */ 177 pci_dw_dbi_wr4(sc->dev, MV_ERR_INT_MASK, 0); 178 } 179 180 static int pci_mv_intr(void *arg) 181 { 182 struct pci_mv_softc *sc = arg; 183 uint32_t cause1, cause2; 184 185 /* Ack all interrups */ 186 cause1 = pci_dw_dbi_rd4(sc->dev, MV_INT_CAUSE1); 187 cause2 = pci_dw_dbi_rd4(sc->dev, MV_INT_CAUSE2); 188 189 pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE1, cause1); 190 pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE2, cause2); 191 return (FILTER_HANDLED); 192 } 193 194 static int 195 pci_mv_get_link(device_t dev, bool *status) 196 { 197 uint32_t reg; 198 199 reg = pci_dw_dbi_rd4(dev, MV_GLOBAL_STATUS_REG); 200 if ((reg & (MV_STATUS_RDLH_LINK_UP | MV_STATUS_PHY_LINK_UP)) == 201 (MV_STATUS_RDLH_LINK_UP | MV_STATUS_PHY_LINK_UP)) 202 *status = true; 203 else 204 *status = false; 205 206 return (0); 207 } 208 209 static int 210 pci_mv_probe(device_t dev) 211 { 212 213 if (!ofw_bus_status_okay(dev)) 214 return (ENXIO); 215 216 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 217 return (ENXIO); 218 219 device_set_desc(dev, "Marvell Armada8K PCI-E Controller"); 220 return (BUS_PROBE_DEFAULT); 221 } 222 223 static int 224 pci_mv_attach(device_t dev) 225 { 226 struct pci_mv_softc *sc; 227 phandle_t node; 228 int rv; 229 int rid; 230 231 sc = device_get_softc(dev); 232 node = ofw_bus_get_node(dev); 233 sc->dev = dev; 234 sc->node = node; 235 236 rid = 0; 237 sc->dw_sc.dbi_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 238 RF_ACTIVE); 239 if (sc->dw_sc.dbi_res == NULL) { 240 device_printf(dev, "Cannot allocate DBI memory\n"); 241 rv = ENXIO; 242 goto out; 243 } 244 245 /* PCI interrupt */ 246 rid = 0; 247 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 248 RF_ACTIVE | RF_SHAREABLE); 249 if (sc->irq_res == NULL) { 250 device_printf(dev, "Cannot allocate IRQ resources\n"); 251 rv = ENXIO; 252 goto out; 253 } 254 255 /* Clocks */ 256 rv = clk_get_by_ofw_name(sc->dev, 0, "core", &sc->clk_core); 257 if (rv != 0) { 258 device_printf(sc->dev, "Cannot get 'core' clock\n"); 259 rv = ENXIO; 260 goto out; 261 } 262 263 rv = clk_get_by_ofw_name(sc->dev, 0, "reg", &sc->clk_reg); 264 if (rv != 0) { 265 device_printf(sc->dev, "Cannot get 'reg' clock\n"); 266 rv = ENXIO; 267 goto out; 268 } 269 270 271 rv = clk_enable(sc->clk_core); 272 if (rv != 0) { 273 device_printf(sc->dev, "Cannot enable 'core' clock\n"); 274 rv = ENXIO; 275 goto out; 276 } 277 278 rv = clk_enable(sc->clk_reg); 279 if (rv != 0) { 280 device_printf(sc->dev, "Cannot enable 'reg' clock\n"); 281 rv = ENXIO; 282 goto out; 283 } 284 285 rv = pci_mv_phy_init(sc); 286 if (rv) 287 goto out; 288 289 rv = pci_dw_init(dev); 290 if (rv != 0) 291 goto out; 292 293 pci_mv_init(sc); 294 295 /* Setup interrupt */ 296 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 297 pci_mv_intr, NULL, sc, &sc->intr_cookie)) { 298 device_printf(dev, "cannot setup interrupt handler\n"); 299 rv = ENXIO; 300 goto out; 301 } 302 303 return (bus_generic_attach(dev)); 304 out: 305 /* XXX Cleanup */ 306 return (rv); 307 } 308 309 static device_method_t pci_mv_methods[] = { 310 /* Device interface */ 311 DEVMETHOD(device_probe, pci_mv_probe), 312 DEVMETHOD(device_attach, pci_mv_attach), 313 314 DEVMETHOD(pci_dw_get_link, pci_mv_get_link), 315 316 DEVMETHOD_END 317 }; 318 319 DEFINE_CLASS_1(pcib, pci_mv_driver, pci_mv_methods, 320 sizeof(struct pci_mv_softc), pci_dw_driver); 321 static devclass_t pci_mv_devclass; 322 DRIVER_MODULE( pci_mv, simplebus, pci_mv_driver, pci_mv_devclass, 323 NULL, NULL); 324