1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /* Armada 8k DesignWare PCIe driver */ 30 31 #include <sys/cdefs.h> 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/devmap.h> 36 #include <sys/proc.h> 37 #include <sys/kernel.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/rman.h> 42 #include <sys/sysctl.h> 43 44 #include <machine/bus.h> 45 #include <machine/intr.h> 46 #include <machine/resource.h> 47 48 #include <dev/extres/clk/clk.h> 49 #include <dev/extres/phy/phy.h> 50 #include <dev/ofw/ofw_bus.h> 51 #include <dev/ofw/ofw_bus_subr.h> 52 #include <dev/ofw/ofw_pci.h> 53 #include <dev/ofw/ofwpci.h> 54 #include <dev/pci/pcivar.h> 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcib_private.h> 57 #include <dev/pci/pci_dw.h> 58 59 #include "pcib_if.h" 60 #include "pci_dw_if.h" 61 62 #define MV_GLOBAL_CONTROL_REG 0x8000 63 #define PCIE_APP_LTSSM_EN (1 << 2) 64 65 #define MV_GLOBAL_STATUS_REG 0x8008 66 #define MV_STATUS_RDLH_LINK_UP (1 << 1) 67 #define MV_STATUS_PHY_LINK_UP (1 << 9) 68 69 #define MV_INT_CAUSE1 0x801C 70 #define MV_INT_MASK1 0x8020 71 #define INT_A_ASSERT_MASK (1 << 9) 72 #define INT_B_ASSERT_MASK (1 << 10) 73 #define INT_C_ASSERT_MASK (1 << 11) 74 #define INT_D_ASSERT_MASK (1 << 12) 75 76 #define MV_INT_CAUSE2 0x8024 77 #define MV_INT_MASK2 0x8028 78 #define MV_ERR_INT_CAUSE 0x802C 79 #define MV_ERR_INT_MASK 0x8030 80 81 #define MV_ARCACHE_TRC_REG 0x8050 82 #define MV_AWCACHE_TRC_REG 0x8054 83 #define MV_ARUSER_REG 0x805C 84 #define MV_AWUSER_REG 0x8060 85 86 #define MV_MAX_LANES 8 87 struct pci_mv_softc { 88 struct pci_dw_softc dw_sc; 89 device_t dev; 90 phandle_t node; 91 struct resource *irq_res; 92 void *intr_cookie; 93 phy_t phy[MV_MAX_LANES]; 94 clk_t clk_core; 95 clk_t clk_reg; 96 }; 97 98 /* Compatible devices. */ 99 static struct ofw_compat_data compat_data[] = { 100 {"marvell,armada8k-pcie", 1}, 101 {NULL, 0}, 102 }; 103 104 static int 105 pci_mv_phy_init(struct pci_mv_softc *sc) 106 { 107 int i, rv; 108 109 for (i = 0; i < MV_MAX_LANES; i++) { 110 rv = phy_get_by_ofw_idx(sc->dev, sc->node, i, &(sc->phy[i])); 111 if (rv != 0 && rv != ENOENT) { 112 device_printf(sc->dev, "Cannot get phy[%d]\n", i); 113 /* XXX revert when phy driver will be implemented */ 114 #if 0 115 goto fail; 116 #else 117 continue; 118 #endif 119 } 120 if (sc->phy[i] == NULL) 121 continue; 122 rv = phy_enable(sc->phy[i]); 123 if (rv != 0) { 124 device_printf(sc->dev, "Cannot enable phy[%d]\n", i); 125 goto fail; 126 } 127 } 128 return (0); 129 130 fail: 131 for (i = 0; i < MV_MAX_LANES; i++) { 132 if (sc->phy[i] == NULL) 133 continue; 134 phy_release(sc->phy[i]); 135 } 136 137 return (rv); 138 } 139 140 static void 141 pci_mv_init(struct pci_mv_softc *sc) 142 { 143 uint32_t reg; 144 145 /* Set device configuration to RC */ 146 reg = pci_dw_dbi_rd4(sc->dev, MV_GLOBAL_CONTROL_REG); 147 reg &= ~0x000000F0; 148 reg |= 0x000000040; 149 pci_dw_dbi_wr4(sc->dev, MV_GLOBAL_CONTROL_REG, reg); 150 151 /* AxCache master transaction attribures */ 152 pci_dw_dbi_wr4(sc->dev, MV_ARCACHE_TRC_REG, 0x3511); 153 pci_dw_dbi_wr4(sc->dev, MV_AWCACHE_TRC_REG, 0x5311); 154 155 /* AxDomain master transaction attribures */ 156 pci_dw_dbi_wr4(sc->dev, MV_ARUSER_REG, 0x0002); 157 pci_dw_dbi_wr4(sc->dev, MV_AWUSER_REG, 0x0002); 158 159 /* Enable all INTx interrupt (virtuual) pins */ 160 reg = pci_dw_dbi_rd4(sc->dev, MV_INT_MASK1); 161 reg |= INT_A_ASSERT_MASK | INT_B_ASSERT_MASK | 162 INT_C_ASSERT_MASK | INT_D_ASSERT_MASK; 163 pci_dw_dbi_wr4(sc->dev, MV_INT_MASK1, reg); 164 165 /* Enable local interrupts */ 166 pci_dw_dbi_wr4(sc->dev, DW_MSI_INTR0_MASK, 0xFFFFFFFF); 167 pci_dw_dbi_wr4(sc->dev, MV_INT_MASK1, 0x0001FE00); 168 pci_dw_dbi_wr4(sc->dev, MV_INT_MASK2, 0x00000000); 169 pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE1, 0xFFFFFFFF); 170 pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE2, 0xFFFFFFFF); 171 172 /* Errors have own interrupt, not yet populated in DTt */ 173 pci_dw_dbi_wr4(sc->dev, MV_ERR_INT_MASK, 0); 174 } 175 176 static int pci_mv_intr(void *arg) 177 { 178 struct pci_mv_softc *sc = arg; 179 uint32_t cause1, cause2; 180 181 /* Ack all interrups */ 182 cause1 = pci_dw_dbi_rd4(sc->dev, MV_INT_CAUSE1); 183 cause2 = pci_dw_dbi_rd4(sc->dev, MV_INT_CAUSE2); 184 185 pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE1, cause1); 186 pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE2, cause2); 187 return (FILTER_HANDLED); 188 } 189 190 static int 191 pci_mv_get_link(device_t dev, bool *status) 192 { 193 uint32_t reg; 194 195 reg = pci_dw_dbi_rd4(dev, MV_GLOBAL_STATUS_REG); 196 if ((reg & (MV_STATUS_RDLH_LINK_UP | MV_STATUS_PHY_LINK_UP)) == 197 (MV_STATUS_RDLH_LINK_UP | MV_STATUS_PHY_LINK_UP)) 198 *status = true; 199 else 200 *status = false; 201 202 return (0); 203 } 204 205 static int 206 pci_mv_probe(device_t dev) 207 { 208 209 if (!ofw_bus_status_okay(dev)) 210 return (ENXIO); 211 212 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 213 return (ENXIO); 214 215 device_set_desc(dev, "Marvell Armada8K PCI-E Controller"); 216 return (BUS_PROBE_DEFAULT); 217 } 218 219 static int 220 pci_mv_attach(device_t dev) 221 { 222 struct resource_map_request req; 223 struct resource_map map; 224 struct pci_mv_softc *sc; 225 phandle_t node; 226 int rv; 227 int rid; 228 229 sc = device_get_softc(dev); 230 node = ofw_bus_get_node(dev); 231 sc->dev = dev; 232 sc->node = node; 233 234 rid = 0; 235 sc->dw_sc.dbi_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 236 RF_ACTIVE | RF_UNMAPPED); 237 if (sc->dw_sc.dbi_res == NULL) { 238 device_printf(dev, "Cannot allocate DBI memory\n"); 239 rv = ENXIO; 240 goto out; 241 } 242 243 resource_init_map_request(&req); 244 req.memattr = VM_MEMATTR_DEVICE_NP; 245 rv = bus_map_resource(dev, SYS_RES_MEMORY, sc->dw_sc.dbi_res, &req, 246 &map); 247 if (rv != 0) { 248 device_printf(dev, "could not map memory.\n"); 249 return (rv); 250 } 251 rman_set_mapping(sc->dw_sc.dbi_res, &map); 252 253 /* PCI interrupt */ 254 rid = 0; 255 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 256 RF_ACTIVE | RF_SHAREABLE); 257 if (sc->irq_res == NULL) { 258 device_printf(dev, "Cannot allocate IRQ resources\n"); 259 rv = ENXIO; 260 goto out; 261 } 262 263 /* Clocks */ 264 rv = clk_get_by_ofw_name(sc->dev, 0, "core", &sc->clk_core); 265 if (rv != 0) { 266 device_printf(sc->dev, "Cannot get 'core' clock\n"); 267 rv = ENXIO; 268 goto out; 269 } 270 271 rv = clk_get_by_ofw_name(sc->dev, 0, "reg", &sc->clk_reg); 272 if (rv != 0) { 273 device_printf(sc->dev, "Cannot get 'reg' clock\n"); 274 rv = ENXIO; 275 goto out; 276 } 277 278 rv = clk_enable(sc->clk_core); 279 if (rv != 0) { 280 device_printf(sc->dev, "Cannot enable 'core' clock\n"); 281 rv = ENXIO; 282 goto out; 283 } 284 285 rv = clk_enable(sc->clk_reg); 286 if (rv != 0) { 287 device_printf(sc->dev, "Cannot enable 'reg' clock\n"); 288 rv = ENXIO; 289 goto out; 290 } 291 292 rv = pci_mv_phy_init(sc); 293 if (rv) 294 goto out; 295 296 rv = pci_dw_init(dev); 297 if (rv != 0) 298 goto out; 299 300 pci_mv_init(sc); 301 302 /* Setup interrupt */ 303 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 304 pci_mv_intr, NULL, sc, &sc->intr_cookie)) { 305 device_printf(dev, "cannot setup interrupt handler\n"); 306 rv = ENXIO; 307 goto out; 308 } 309 310 return (bus_generic_attach(dev)); 311 out: 312 /* XXX Cleanup */ 313 return (rv); 314 } 315 316 static device_method_t pci_mv_methods[] = { 317 /* Device interface */ 318 DEVMETHOD(device_probe, pci_mv_probe), 319 DEVMETHOD(device_attach, pci_mv_attach), 320 321 DEVMETHOD(pci_dw_get_link, pci_mv_get_link), 322 323 DEVMETHOD_END 324 }; 325 326 DEFINE_CLASS_1(pcib, pci_mv_driver, pci_mv_methods, 327 sizeof(struct pci_mv_softc), pci_dw_driver); 328 DRIVER_MODULE( pci_mv, simplebus, pci_mv_driver, NULL, NULL); 329