1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * 28 */ 29 30 #ifndef _PCI_DW_H_ 31 #define _PCI_DW_H_ 32 33 #include "pci_dw_if.h" 34 35 /* DesignWare CIe configuration registers */ 36 #define DW_PORT_LINK_CTRL 0x710 37 #define PORT_LINK_CAPABLE(n) (((n) & 0x3F) << 16) 38 #define PORT_LINK_CAPABLE_1 0x01 39 #define PORT_LINK_CAPABLE_2 0x03 40 #define PORT_LINK_CAPABLE_4 0x07 41 #define PORT_LINK_CAPABLE_8 0x0F 42 #define PORT_LINK_CAPABLE_16 0x1F 43 #define PORT_LINK_CAPABLE_32 0x3F 44 45 #define DW_GEN2_CTRL 0x80C 46 #define DIRECT_SPEED_CHANGE (1 << 17) 47 #define GEN2_CTRL_NUM_OF_LANES(n) (((n) & 0x3F) << 8) 48 #define GEN2_CTRL_NUM_OF_LANES_1 0x01 49 #define GEN2_CTRL_NUM_OF_LANES_2 0x03 50 #define GEN2_CTRL_NUM_OF_LANES_4 0x07 51 #define GEN2_CTRL_NUM_OF_LANES_8 0x0F 52 #define GEN2_CTRL_NUM_OF_LANES_16 0x1F 53 #define GEN2_CTRL_NUM_OF_LANES_32 0x3F 54 55 #define DW_MSI_ADDR_LO 0x820 56 #define DW_MSI_ADDR_HI 0x824 57 #define DW_MSI_INTR0_ENABLE 0x828 58 #define DW_MSI_INTR0_MASK 0x82C 59 #define DW_MSI_INTR0_STATUS 0x830 60 61 #define DW_MISC_CONTROL_1 0x8BC 62 #define DBI_RO_WR_EN (1 << 0) 63 64 /* Legacy (pre-4.80) iATU mode */ 65 #define DW_IATU_VIEWPORT 0x900 66 #define IATU_REGION_INBOUND (1U << 31) 67 #define IATU_REGION_INDEX(x) ((x) & 0x7) 68 #define DW_IATU_CTRL1 0x904 69 #define IATU_CTRL1_TYPE(x) ((x) & 0x1F) 70 #define IATU_CTRL1_TYPE_MEM 0x0 71 #define IATU_CTRL1_TYPE_IO 0x2 72 #define IATU_CTRL1_TYPE_CFG0 0x4 73 #define IATU_CTRL1_TYPE_CFG1 0x5 74 #define DW_IATU_CTRL2 0x908 75 #define IATU_CTRL2_REGION_EN (1U << 31) 76 #define DW_IATU_LWR_BASE_ADDR 0x90C 77 #define DW_IATU_UPPER_BASE_ADDR 0x910 78 #define DW_IATU_LIMIT_ADDR 0x914 79 #define DW_IATU_LWR_TARGET_ADDR 0x918 80 #define DW_IATU_UPPER_TARGET_ADDR 0x91C 81 82 /* Modern (4.80+) "unroll" iATU mode */ 83 #define DW_IATU_UR_STEP 0x200 84 #define DW_IATU_UR_REG(r, n) (r) * DW_IATU_UR_STEP + IATU_UR_##n 85 #define IATU_UR_CTRL1 0x00 86 #define IATU_UR_CTRL2 0x04 87 #define IATU_UR_LWR_BASE_ADDR 0x08 88 #define IATU_UR_UPPER_BASE_ADDR 0x0C 89 #define IATU_UR_LIMIT_ADDR 0x10 90 #define IATU_UR_LWR_TARGET_ADDR 0x14 91 #define IATU_UR_UPPER_TARGET_ADDR 0x18 92 93 #define DW_DEFAULT_IATU_UR_DBI_OFFSET 0x300000 94 #define DW_DEFAULT_IATU_UR_DBI_SIZE 0x1000 95 96 struct pci_dw_softc { 97 struct ofw_pci_softc ofw_pci; /* Must be first */ 98 99 /* Filled by attachement stub */ 100 struct resource *dbi_res; 101 102 /* pci_dw variables */ 103 device_t dev; 104 phandle_t node; 105 struct mtx mtx; 106 struct resource *cfg_res; 107 108 struct ofw_pci_range io_range; 109 struct ofw_pci_range *mem_ranges; 110 int num_mem_ranges; 111 112 bool coherent; 113 bus_dma_tag_t dmat; 114 115 int num_lanes; 116 int num_out_regions; 117 struct resource *iatu_ur_res; /* NB: May be dbi_res */ 118 bus_addr_t iatu_ur_offset; 119 bus_size_t iatu_ur_size; 120 bus_addr_t cfg_pa; /* PA of config memoty */ 121 bus_size_t cfg_size; /* size of config region */ 122 123 u_int bus_start; 124 u_int bus_end; 125 u_int root_bus; 126 u_int sub_bus; 127 }; 128 129 DECLARE_CLASS(pci_dw_driver); 130 131 static inline void 132 pci_dw_dbi_wr4(device_t dev, u_int reg, uint32_t val) 133 { 134 PCI_DW_DBI_WRITE(dev, reg, val, 4); 135 } 136 137 static inline void 138 pci_dw_dbi_wr2(device_t dev, u_int reg, uint16_t val) 139 { 140 PCI_DW_DBI_WRITE(dev, reg, val, 2); 141 } 142 143 static inline void 144 pci_dw_dbi_wr1(device_t dev, u_int reg, uint8_t val) 145 { 146 PCI_DW_DBI_WRITE(dev, reg, val, 1); 147 } 148 149 static inline uint32_t 150 pci_dw_dbi_rd4(device_t dev, u_int reg) 151 { 152 return (PCI_DW_DBI_READ(dev, reg, 4)); 153 } 154 155 static inline uint16_t 156 pci_dw_dbi_rd2(device_t dev, u_int reg) 157 { 158 return ((uint16_t)PCI_DW_DBI_READ(dev, reg, 2)); 159 } 160 161 static inline uint8_t 162 pci_dw_dbi_rd1(device_t dev, u_int reg) 163 { 164 return ((uint8_t)PCI_DW_DBI_READ(dev, reg, 1)); 165 } 166 167 int pci_dw_init(device_t); 168 169 #endif /* __PCI_HOST_GENERIC_H_ */ 170