1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * 28 * $FreeBSD$ 29 * 30 */ 31 32 #ifndef _PCI_DW_H_ 33 #define _PCI_DW_H_ 34 35 #include "pci_dw_if.h" 36 37 /* DesignWare CIe configuration registers */ 38 #define DW_PORT_LINK_CTRL 0x710 39 #define PORT_LINK_CAPABLE(n) (((n) & 0x3F) << 16) 40 #define PORT_LINK_CAPABLE_1 0x01 41 #define PORT_LINK_CAPABLE_2 0x03 42 #define PORT_LINK_CAPABLE_4 0x07 43 #define PORT_LINK_CAPABLE_8 0x0F 44 #define PORT_LINK_CAPABLE_16 0x1F 45 #define PORT_LINK_CAPABLE_32 0x3F 46 47 #define DW_GEN2_CTRL 0x80C 48 #define DIRECT_SPEED_CHANGE (1 << 17) 49 #define GEN2_CTRL_NUM_OF_LANES(n) (((n) & 0x3F) << 8) 50 #define GEN2_CTRL_NUM_OF_LANES_1 0x01 51 #define GEN2_CTRL_NUM_OF_LANES_2 0x03 52 #define GEN2_CTRL_NUM_OF_LANES_4 0x07 53 #define GEN2_CTRL_NUM_OF_LANES_8 0x0F 54 #define GEN2_CTRL_NUM_OF_LANES_16 0x1F 55 #define GEN2_CTRL_NUM_OF_LANES_32 0x3F 56 57 #define DW_MSI_ADDR_LO 0x820 58 #define DW_MSI_ADDR_HI 0x824 59 #define DW_MSI_INTR0_ENABLE 0x828 60 #define DW_MSI_INTR0_MASK 0x82C 61 #define DW_MSI_INTR0_STATUS 0x830 62 63 #define DW_MISC_CONTROL_1 0x8BC 64 #define DBI_RO_WR_EN (1 << 0) 65 66 /* Legacy (pre-4.80) iATU mode */ 67 #define DW_IATU_VIEWPORT 0x900 68 #define IATU_REGION_INBOUND (1U << 31) 69 #define IATU_REGION_INDEX(x) ((x) & 0x7) 70 #define DW_IATU_CTRL1 0x904 71 #define IATU_CTRL1_TYPE(x) ((x) & 0x1F) 72 #define IATU_CTRL1_TYPE_MEM 0x0 73 #define IATU_CTRL1_TYPE_IO 0x2 74 #define IATU_CTRL1_TYPE_CFG0 0x4 75 #define IATU_CTRL1_TYPE_CFG1 0x5 76 #define DW_IATU_CTRL2 0x908 77 #define IATU_CTRL2_REGION_EN (1U << 31) 78 #define DW_IATU_LWR_BASE_ADDR 0x90C 79 #define DW_IATU_UPPER_BASE_ADDR 0x910 80 #define DW_IATU_LIMIT_ADDR 0x914 81 #define DW_IATU_LWR_TARGET_ADDR 0x918 82 #define DW_IATU_UPPER_TARGET_ADDR 0x91C 83 84 /* Modern (4.80+) "unroll" iATU mode */ 85 #define DW_IATU_UR_STEP 0x200 86 #define DW_IATU_UR_REG(r, n) (r) * DW_IATU_UR_STEP + IATU_UR_##n 87 #define IATU_UR_CTRL1 0x00 88 #define IATU_UR_CTRL2 0x04 89 #define IATU_UR_LWR_BASE_ADDR 0x08 90 #define IATU_UR_UPPER_BASE_ADDR 0x0C 91 #define IATU_UR_LIMIT_ADDR 0x10 92 #define IATU_UR_LWR_TARGET_ADDR 0x14 93 #define IATU_UR_UPPER_TARGET_ADDR 0x18 94 95 #define DW_DEFAULT_IATU_UR_DBI_OFFSET 0x300000 96 #define DW_DEFAULT_IATU_UR_DBI_SIZE 0x1000 97 98 struct pci_dw_softc { 99 struct ofw_pci_softc ofw_pci; /* Must be first */ 100 101 /* Filled by attachement stub */ 102 struct resource *dbi_res; 103 104 /* pci_dw variables */ 105 device_t dev; 106 phandle_t node; 107 struct mtx mtx; 108 struct resource *cfg_res; 109 110 struct ofw_pci_range io_range; 111 struct ofw_pci_range *mem_ranges; 112 int num_mem_ranges; 113 114 bool coherent; 115 bus_dma_tag_t dmat; 116 117 int num_lanes; 118 int num_out_regions; 119 struct resource *iatu_ur_res; /* NB: May be dbi_res */ 120 bus_addr_t iatu_ur_offset; 121 bus_size_t iatu_ur_size; 122 bus_addr_t cfg_pa; /* PA of config memoty */ 123 bus_size_t cfg_size; /* size of config region */ 124 125 u_int bus_start; 126 u_int bus_end; 127 u_int root_bus; 128 u_int sub_bus; 129 }; 130 131 DECLARE_CLASS(pci_dw_driver); 132 133 static inline void 134 pci_dw_dbi_wr4(device_t dev, u_int reg, uint32_t val) 135 { 136 PCI_DW_DBI_WRITE(dev, reg, val, 4); 137 } 138 139 static inline void 140 pci_dw_dbi_wr2(device_t dev, u_int reg, uint16_t val) 141 { 142 PCI_DW_DBI_WRITE(dev, reg, val, 2); 143 } 144 145 static inline void 146 pci_dw_dbi_wr1(device_t dev, u_int reg, uint8_t val) 147 { 148 PCI_DW_DBI_WRITE(dev, reg, val, 1); 149 } 150 151 static inline uint32_t 152 pci_dw_dbi_rd4(device_t dev, u_int reg) 153 { 154 return (PCI_DW_DBI_READ(dev, reg, 4)); 155 } 156 157 static inline uint16_t 158 pci_dw_dbi_rd2(device_t dev, u_int reg) 159 { 160 return ((uint16_t)PCI_DW_DBI_READ(dev, reg, 2)); 161 } 162 163 static inline uint8_t 164 pci_dw_dbi_rd1(device_t dev, u_int reg) 165 { 166 return ((uint8_t)PCI_DW_DBI_READ(dev, reg, 1)); 167 } 168 169 int pci_dw_init(device_t); 170 171 #endif /* __PCI_HOST_GENERIC_H_ */ 172