1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /* Base class for all Synopsys DesignWare PCI/PCIe drivers */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/devmap.h> 38 #include <sys/proc.h> 39 #include <sys/kernel.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/mutex.h> 44 #include <sys/rman.h> 45 46 #include <machine/bus.h> 47 #include <machine/intr.h> 48 #include <machine/resource.h> 49 50 #include <dev/ofw/ofw_bus.h> 51 #include <dev/ofw/ofw_bus_subr.h> 52 #include <dev/ofw/ofw_pci.h> 53 #include <dev/ofw/ofwpci.h> 54 #include <dev/pci/pcivar.h> 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcib_private.h> 57 #include <dev/pci/pci_dw.h> 58 59 #include "pcib_if.h" 60 #include "pci_dw_if.h" 61 62 #define DEBUG 63 #ifdef DEBUG 64 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 65 #else 66 #define debugf(fmt, args...) 67 #endif 68 69 #define DBI_WR1(sc, reg, val) pci_dw_dbi_wr1((sc)->dev, reg, val) 70 #define DBI_WR2(sc, reg, val) pci_dw_dbi_wr2((sc)->dev, reg, val) 71 #define DBI_WR4(sc, reg, val) pci_dw_dbi_wr4((sc)->dev, reg, val) 72 #define DBI_RD1(sc, reg) pci_dw_dbi_rd1((sc)->dev, reg) 73 #define DBI_RD2(sc, reg) pci_dw_dbi_rd2((sc)->dev, reg) 74 #define DBI_RD4(sc, reg) pci_dw_dbi_rd4((sc)->dev, reg) 75 76 #define IATU_UR_WR4(sc, reg, val) \ 77 bus_write_4((sc)->iatu_ur_res, (sc)->iatu_ur_offset + (reg), (val)) 78 #define IATU_UR_RD4(sc, reg) \ 79 bus_read_4((sc)->iatu_ur_res, (sc)->iatu_ur_offset + (reg)) 80 81 #define PCI_BUS_SHIFT 20 82 #define PCI_SLOT_SHIFT 15 83 #define PCI_FUNC_SHIFT 12 84 #define PCI_BUS_MASK 0xFF 85 #define PCI_SLOT_MASK 0x1F 86 #define PCI_FUNC_MASK 0x07 87 #define PCI_REG_MASK 0xFFF 88 89 #define IATU_CFG_BUS(bus) ((uint64_t)((bus) & 0xff) << 24) 90 #define IATU_CFG_SLOT(slot) ((uint64_t)((slot) & 0x1f) << 19) 91 #define IATU_CFG_FUNC(func) ((uint64_t)((func) & 0x07) << 16) 92 93 static uint32_t 94 pci_dw_dbi_read(device_t dev, u_int reg, int width) 95 { 96 struct pci_dw_softc *sc; 97 98 sc = device_get_softc(dev); 99 MPASS(sc->dbi_res != NULL); 100 101 switch (width) { 102 case 4: 103 return (bus_read_4(sc->dbi_res, reg)); 104 case 2: 105 return (bus_read_2(sc->dbi_res, reg)); 106 case 1: 107 return (bus_read_1(sc->dbi_res, reg)); 108 default: 109 device_printf(sc->dev, "Unsupported width: %d\n", width); 110 return (0xFFFFFFFF); 111 } 112 } 113 114 static void 115 pci_dw_dbi_write(device_t dev, u_int reg, uint32_t val, int width) 116 { 117 struct pci_dw_softc *sc; 118 119 sc = device_get_softc(dev); 120 MPASS(sc->dbi_res != NULL); 121 122 switch (width) { 123 case 4: 124 bus_write_4(sc->dbi_res, reg, val); 125 break; 126 case 2: 127 bus_write_2(sc->dbi_res, reg, val); 128 break; 129 case 1: 130 bus_write_1(sc->dbi_res, reg, val); 131 break; 132 default: 133 device_printf(sc->dev, "Unsupported width: %d\n", width); 134 break; 135 } 136 } 137 138 static void 139 pci_dw_dbi_protect(struct pci_dw_softc *sc, bool protect) 140 { 141 uint32_t reg; 142 143 reg = DBI_RD4(sc, DW_MISC_CONTROL_1); 144 if (protect) 145 reg &= ~DBI_RO_WR_EN; 146 else 147 reg |= DBI_RO_WR_EN; 148 DBI_WR4(sc, DW_MISC_CONTROL_1, reg); 149 } 150 151 static bool 152 pci_dw_check_dev(struct pci_dw_softc *sc, u_int bus, u_int slot, u_int func, 153 u_int reg) 154 { 155 bool status; 156 int rv; 157 158 if (bus < sc->bus_start || bus > sc->bus_end || slot > PCI_SLOTMAX || 159 func > PCI_FUNCMAX || reg > PCIE_REGMAX) 160 return (false); 161 162 /* link is needed for access to all non-root busses */ 163 if (bus != sc->root_bus) { 164 rv = PCI_DW_GET_LINK(sc->dev, &status); 165 if (rv != 0 || !status) 166 return (false); 167 return (true); 168 } 169 170 /* we have only 1 device with 1 function root port */ 171 if (slot > 0 || func > 0) 172 return (false); 173 return (true); 174 } 175 176 static bool 177 pci_dw_detect_atu_unroll(struct pci_dw_softc *sc) 178 { 179 return (DBI_RD4(sc, DW_IATU_VIEWPORT) == 0xFFFFFFFFU); 180 } 181 182 static int 183 pci_dw_detect_out_atu_regions_unroll(struct pci_dw_softc *sc) 184 { 185 int num_regions, i; 186 uint32_t reg; 187 188 num_regions = sc->iatu_ur_size / DW_IATU_UR_STEP; 189 190 for (i = 0; i < num_regions; ++i) { 191 IATU_UR_WR4(sc, DW_IATU_UR_REG(i, LWR_TARGET_ADDR), 192 0x12340000); 193 reg = IATU_UR_RD4(sc, DW_IATU_UR_REG(i, LWR_TARGET_ADDR)); 194 if (reg != 0x12340000) 195 break; 196 } 197 198 sc->num_out_regions = i; 199 200 return (0); 201 } 202 203 static int 204 pci_dw_detect_out_atu_regions_legacy(struct pci_dw_softc *sc) 205 { 206 int num_viewports, i; 207 uint32_t reg; 208 209 /* Find out how many viewports there are in total */ 210 DBI_WR4(sc, DW_IATU_VIEWPORT, IATU_REGION_INDEX(~0U)); 211 reg = DBI_RD4(sc, DW_IATU_VIEWPORT); 212 if (reg > IATU_REGION_INDEX(~0U)) { 213 device_printf(sc->dev, 214 "Cannot detect number of output iATU regions; read %#x\n", 215 reg); 216 return (ENXIO); 217 } 218 219 num_viewports = reg + 1; 220 221 /* 222 * Find out how many of them are outbound by seeing whether a dummy 223 * page-aligned address sticks. 224 */ 225 for (i = 0; i < num_viewports; ++i) { 226 DBI_WR4(sc, DW_IATU_VIEWPORT, IATU_REGION_INDEX(i)); 227 DBI_WR4(sc, DW_IATU_LWR_TARGET_ADDR, 0x12340000); 228 reg = DBI_RD4(sc, DW_IATU_LWR_TARGET_ADDR); 229 if (reg != 0x12340000) 230 break; 231 } 232 233 sc->num_out_regions = i; 234 235 return (0); 236 } 237 238 static int 239 pci_dw_detect_out_atu_regions(struct pci_dw_softc *sc) 240 { 241 if (sc->iatu_ur_res) 242 return (pci_dw_detect_out_atu_regions_unroll(sc)); 243 else 244 return (pci_dw_detect_out_atu_regions_legacy(sc)); 245 } 246 247 static int 248 pci_dw_map_out_atu_unroll(struct pci_dw_softc *sc, int idx, int type, 249 uint64_t pa, uint64_t pci_addr, uint32_t size) 250 { 251 uint32_t reg; 252 int i; 253 254 if (size == 0) 255 return (0); 256 257 IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, LWR_BASE_ADDR), 258 pa & 0xFFFFFFFF); 259 IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, UPPER_BASE_ADDR), 260 (pa >> 32) & 0xFFFFFFFF); 261 IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, LIMIT_ADDR), 262 (pa + size - 1) & 0xFFFFFFFF); 263 IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, LWR_TARGET_ADDR), 264 pci_addr & 0xFFFFFFFF); 265 IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, UPPER_TARGET_ADDR), 266 (pci_addr >> 32) & 0xFFFFFFFF); 267 IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, CTRL1), 268 IATU_CTRL1_TYPE(type)); 269 IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, CTRL2), 270 IATU_CTRL2_REGION_EN); 271 272 /* Wait until setup becomes valid */ 273 for (i = 10; i > 0; i--) { 274 reg = IATU_UR_RD4(sc, DW_IATU_UR_REG(idx, CTRL2)); 275 if (reg & IATU_CTRL2_REGION_EN) 276 return (0); 277 DELAY(5); 278 } 279 280 device_printf(sc->dev, 281 "Cannot map outbound region %d in unroll mode iATU\n", idx); 282 return (ETIMEDOUT); 283 } 284 285 static int 286 pci_dw_map_out_atu_legacy(struct pci_dw_softc *sc, int idx, int type, 287 uint64_t pa, uint64_t pci_addr, uint32_t size) 288 { 289 uint32_t reg; 290 int i; 291 292 if (size == 0) 293 return (0); 294 295 DBI_WR4(sc, DW_IATU_VIEWPORT, IATU_REGION_INDEX(idx)); 296 DBI_WR4(sc, DW_IATU_LWR_BASE_ADDR, pa & 0xFFFFFFFF); 297 DBI_WR4(sc, DW_IATU_UPPER_BASE_ADDR, (pa >> 32) & 0xFFFFFFFF); 298 DBI_WR4(sc, DW_IATU_LIMIT_ADDR, (pa + size - 1) & 0xFFFFFFFF); 299 DBI_WR4(sc, DW_IATU_LWR_TARGET_ADDR, pci_addr & 0xFFFFFFFF); 300 DBI_WR4(sc, DW_IATU_UPPER_TARGET_ADDR, (pci_addr >> 32) & 0xFFFFFFFF); 301 DBI_WR4(sc, DW_IATU_CTRL1, IATU_CTRL1_TYPE(type)); 302 DBI_WR4(sc, DW_IATU_CTRL2, IATU_CTRL2_REGION_EN); 303 304 /* Wait until setup becomes valid */ 305 for (i = 10; i > 0; i--) { 306 reg = DBI_RD4(sc, DW_IATU_CTRL2); 307 if (reg & IATU_CTRL2_REGION_EN) 308 return (0); 309 DELAY(5); 310 } 311 312 device_printf(sc->dev, 313 "Cannot map outbound region %d in legacy mode iATU\n", idx); 314 return (ETIMEDOUT); 315 } 316 317 /* Map one outbound ATU region */ 318 static int 319 pci_dw_map_out_atu(struct pci_dw_softc *sc, int idx, int type, 320 uint64_t pa, uint64_t pci_addr, uint32_t size) 321 { 322 if (sc->iatu_ur_res) 323 return (pci_dw_map_out_atu_unroll(sc, idx, type, pa, 324 pci_addr, size)); 325 else 326 return (pci_dw_map_out_atu_legacy(sc, idx, type, pa, 327 pci_addr, size)); 328 } 329 330 static int 331 pci_dw_setup_hw(struct pci_dw_softc *sc) 332 { 333 uint32_t reg; 334 int rv, i; 335 336 pci_dw_dbi_protect(sc, false); 337 338 /* Setup config registers */ 339 DBI_WR1(sc, PCIR_CLASS, PCIC_BRIDGE); 340 DBI_WR1(sc, PCIR_SUBCLASS, PCIS_BRIDGE_PCI); 341 DBI_WR4(sc, PCIR_BAR(0), 4); 342 DBI_WR4(sc, PCIR_BAR(1), 0); 343 DBI_WR1(sc, PCIR_INTPIN, 1); 344 DBI_WR1(sc, PCIR_PRIBUS_1, sc->root_bus); 345 DBI_WR1(sc, PCIR_SECBUS_1, sc->sub_bus); 346 DBI_WR1(sc, PCIR_SUBBUS_1, sc->bus_end); 347 DBI_WR2(sc, PCIR_COMMAND, 348 PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | 349 PCIM_CMD_BUSMASTEREN | PCIM_CMD_SERRESPEN); 350 pci_dw_dbi_protect(sc, true); 351 352 /* Setup outbound memory windows */ 353 for (i = 0; i < min(sc->num_mem_ranges, sc->num_out_regions - 1); ++i) { 354 rv = pci_dw_map_out_atu(sc, i + 1, IATU_CTRL1_TYPE_MEM, 355 sc->mem_ranges[i].host, sc->mem_ranges[i].pci, 356 sc->mem_ranges[i].size); 357 if (rv != 0) 358 return (rv); 359 } 360 361 /* If we have enough regions ... */ 362 if (sc->num_mem_ranges + 1 < sc->num_out_regions && 363 sc->io_range.size != 0) { 364 /* Setup outbound I/O window */ 365 rv = pci_dw_map_out_atu(sc, sc->num_mem_ranges + 1, 366 IATU_CTRL1_TYPE_IO, sc->io_range.host, sc->io_range.pci, 367 sc->io_range.size); 368 if (rv != 0) 369 return (rv); 370 } 371 372 /* Adjust number of lanes */ 373 reg = DBI_RD4(sc, DW_PORT_LINK_CTRL); 374 reg &= ~PORT_LINK_CAPABLE(~0); 375 switch (sc->num_lanes) { 376 case 1: 377 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_1); 378 break; 379 case 2: 380 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_2); 381 break; 382 case 4: 383 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_4); 384 break; 385 case 8: 386 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_8); 387 break; 388 case 16: 389 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_16); 390 break; 391 case 32: 392 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_32); 393 break; 394 default: 395 device_printf(sc->dev, 396 "'num-lanes' property have invalid value: %d\n", 397 sc->num_lanes); 398 return (EINVAL); 399 } 400 DBI_WR4(sc, DW_PORT_LINK_CTRL, reg); 401 402 /* And link width */ 403 reg = DBI_RD4(sc, DW_GEN2_CTRL); 404 reg &= ~GEN2_CTRL_NUM_OF_LANES(~0); 405 switch (sc->num_lanes) { 406 case 1: 407 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_1); 408 break; 409 case 2: 410 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_2); 411 break; 412 case 4: 413 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_4); 414 break; 415 case 8: 416 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_8); 417 break; 418 case 16: 419 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_16); 420 break; 421 case 32: 422 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_32); 423 break; 424 } 425 DBI_WR4(sc, DW_GEN2_CTRL, reg); 426 427 reg = DBI_RD4(sc, DW_GEN2_CTRL); 428 reg |= DIRECT_SPEED_CHANGE; 429 DBI_WR4(sc, DW_GEN2_CTRL, reg); 430 431 return (0); 432 } 433 434 static int 435 pci_dw_decode_ranges(struct pci_dw_softc *sc, struct ofw_pci_range *ranges, 436 int nranges) 437 { 438 int i, nmem, rv; 439 440 nmem = 0; 441 for (i = 0; i < nranges; i++) { 442 if ((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 443 OFW_PCI_PHYS_HI_SPACE_MEM32) 444 ++nmem; 445 } 446 447 sc->mem_ranges = malloc(nmem * sizeof(*sc->mem_ranges), M_DEVBUF, 448 M_WAITOK); 449 sc->num_mem_ranges = nmem; 450 451 nmem = 0; 452 for (i = 0; i < nranges; i++) { 453 if ((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 454 OFW_PCI_PHYS_HI_SPACE_IO) { 455 if (sc->io_range.size != 0) { 456 device_printf(sc->dev, 457 "Duplicated IO range found in DT\n"); 458 rv = ENXIO; 459 goto out; 460 } 461 462 sc->io_range = ranges[i]; 463 if (sc->io_range.size > UINT32_MAX) { 464 device_printf(sc->dev, 465 "ATU IO window size is too large. " 466 "Up to 4GB windows are supported, " 467 "trimming window size to 4GB\n"); 468 sc->io_range.size = UINT32_MAX; 469 } 470 } 471 if ((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 472 OFW_PCI_PHYS_HI_SPACE_MEM32) { 473 MPASS(nmem < sc->num_mem_ranges); 474 sc->mem_ranges[nmem] = ranges[i]; 475 if (sc->mem_ranges[nmem].size > UINT32_MAX) { 476 device_printf(sc->dev, 477 "ATU MEM window size is too large. " 478 "Up to 4GB windows are supported, " 479 "trimming window size to 4GB\n"); 480 sc->mem_ranges[nmem].size = UINT32_MAX; 481 } 482 ++nmem; 483 } 484 } 485 486 MPASS(nmem == sc->num_mem_ranges); 487 488 if (nmem == 0) { 489 device_printf(sc->dev, 490 "Missing required memory range in DT\n"); 491 return (ENXIO); 492 } 493 494 return (0); 495 496 out: 497 free(sc->mem_ranges, M_DEVBUF); 498 return (rv); 499 } 500 501 /*----------------------------------------------------------------------------- 502 * 503 * P C I B I N T E R F A C E 504 */ 505 506 static uint32_t 507 pci_dw_read_config(device_t dev, u_int bus, u_int slot, 508 u_int func, u_int reg, int bytes) 509 { 510 struct pci_dw_softc *sc; 511 struct resource *res; 512 uint32_t data; 513 uint64_t addr; 514 int type, rv; 515 516 sc = device_get_softc(dev); 517 518 if (!pci_dw_check_dev(sc, bus, slot, func, reg)) 519 return (0xFFFFFFFFU); 520 521 if (bus == sc->root_bus) { 522 res = (sc->dbi_res); 523 } else { 524 addr = IATU_CFG_BUS(bus) | IATU_CFG_SLOT(slot) | 525 IATU_CFG_FUNC(func); 526 if (bus == sc->sub_bus) 527 type = IATU_CTRL1_TYPE_CFG0; 528 else 529 type = IATU_CTRL1_TYPE_CFG1; 530 rv = pci_dw_map_out_atu(sc, 0, type, 531 sc->cfg_pa, addr, sc->cfg_size); 532 if (rv != 0) 533 return (0xFFFFFFFFU); 534 res = sc->cfg_res; 535 } 536 537 switch (bytes) { 538 case 1: 539 data = bus_read_1(res, reg); 540 break; 541 case 2: 542 data = bus_read_2(res, reg); 543 break; 544 case 4: 545 data = bus_read_4(res, reg); 546 break; 547 default: 548 data = 0xFFFFFFFFU; 549 } 550 551 return (data); 552 553 } 554 555 static void 556 pci_dw_write_config(device_t dev, u_int bus, u_int slot, 557 u_int func, u_int reg, uint32_t val, int bytes) 558 { 559 struct pci_dw_softc *sc; 560 struct resource *res; 561 uint64_t addr; 562 int type, rv; 563 564 sc = device_get_softc(dev); 565 if (!pci_dw_check_dev(sc, bus, slot, func, reg)) 566 return; 567 568 if (bus == sc->root_bus) { 569 res = (sc->dbi_res); 570 } else { 571 addr = IATU_CFG_BUS(bus) | IATU_CFG_SLOT(slot) | 572 IATU_CFG_FUNC(func); 573 if (bus == sc->sub_bus) 574 type = IATU_CTRL1_TYPE_CFG0; 575 else 576 type = IATU_CTRL1_TYPE_CFG1; 577 rv = pci_dw_map_out_atu(sc, 0, type, 578 sc->cfg_pa, addr, sc->cfg_size); 579 if (rv != 0) 580 return ; 581 res = sc->cfg_res; 582 } 583 584 switch (bytes) { 585 case 1: 586 bus_write_1(res, reg, val); 587 break; 588 case 2: 589 bus_write_2(res, reg, val); 590 break; 591 case 4: 592 bus_write_4(res, reg, val); 593 break; 594 default: 595 break; 596 } 597 } 598 599 static int 600 pci_dw_alloc_msi(device_t pci, device_t child, int count, 601 int maxcount, int *irqs) 602 { 603 phandle_t msi_parent; 604 int rv; 605 606 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 607 &msi_parent, NULL); 608 if (rv != 0) 609 return (rv); 610 611 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount, 612 irqs)); 613 } 614 615 static int 616 pci_dw_release_msi(device_t pci, device_t child, int count, int *irqs) 617 { 618 phandle_t msi_parent; 619 int rv; 620 621 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 622 &msi_parent, NULL); 623 if (rv != 0) 624 return (rv); 625 return (intr_release_msi(pci, child, msi_parent, count, irqs)); 626 } 627 628 static int 629 pci_dw_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 630 uint32_t *data) 631 { 632 phandle_t msi_parent; 633 int rv; 634 635 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 636 &msi_parent, NULL); 637 if (rv != 0) 638 return (rv); 639 640 return (intr_map_msi(pci, child, msi_parent, irq, addr, data)); 641 } 642 643 static int 644 pci_dw_alloc_msix(device_t pci, device_t child, int *irq) 645 { 646 phandle_t msi_parent; 647 int rv; 648 649 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 650 &msi_parent, NULL); 651 if (rv != 0) 652 return (rv); 653 return (intr_alloc_msix(pci, child, msi_parent, irq)); 654 } 655 656 static int 657 pci_dw_release_msix(device_t pci, device_t child, int irq) 658 { 659 phandle_t msi_parent; 660 int rv; 661 662 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 663 &msi_parent, NULL); 664 if (rv != 0) 665 return (rv); 666 return (intr_release_msix(pci, child, msi_parent, irq)); 667 } 668 669 static int 670 pci_dw_get_id(device_t pci, device_t child, enum pci_id_type type, 671 uintptr_t *id) 672 { 673 phandle_t node; 674 int rv; 675 uint32_t rid; 676 uint16_t pci_rid; 677 678 if (type != PCI_ID_MSI) 679 return (pcib_get_id(pci, child, type, id)); 680 681 node = ofw_bus_get_node(pci); 682 pci_rid = pci_get_rid(child); 683 684 rv = ofw_bus_msimap(node, pci_rid, NULL, &rid); 685 if (rv != 0) 686 return (rv); 687 *id = rid; 688 689 return (0); 690 } 691 692 /*----------------------------------------------------------------------------- 693 * 694 * B U S / D E V I C E I N T E R F A C E 695 */ 696 static bus_dma_tag_t 697 pci_dw_get_dma_tag(device_t dev, device_t child) 698 { 699 struct pci_dw_softc *sc; 700 701 sc = device_get_softc(dev); 702 return (sc->dmat); 703 } 704 705 int 706 pci_dw_init(device_t dev) 707 { 708 struct pci_dw_softc *sc; 709 int rv, rid; 710 bool unroll_mode; 711 712 sc = device_get_softc(dev); 713 sc->dev = dev; 714 sc->node = ofw_bus_get_node(dev); 715 716 mtx_init(&sc->mtx, "pci_dw_mtx", NULL, MTX_DEF); 717 718 /* XXXn Should not be this configurable ? */ 719 sc->bus_start = 0; 720 sc->bus_end = 255; 721 sc->root_bus = 0; 722 sc->sub_bus = 1; 723 724 /* Read FDT properties */ 725 if (!sc->coherent) 726 sc->coherent = OF_hasprop(sc->node, "dma-coherent"); 727 728 rv = OF_getencprop(sc->node, "num-lanes", &sc->num_lanes, 729 sizeof(sc->num_lanes)); 730 if (rv != sizeof(sc->num_lanes)) 731 sc->num_lanes = 1; 732 if (sc->num_lanes != 1 && sc->num_lanes != 2 && 733 sc->num_lanes != 4 && sc->num_lanes != 8) { 734 device_printf(dev, 735 "invalid number of lanes: %d\n",sc->num_lanes); 736 sc->num_lanes = 0; 737 rv = ENXIO; 738 goto out; 739 } 740 741 rid = 0; 742 rv = ofw_bus_find_string_index(sc->node, "reg-names", "config", &rid); 743 if (rv != 0) { 744 device_printf(dev, "Cannot get config space memory\n"); 745 rv = ENXIO; 746 goto out; 747 } 748 sc->cfg_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 749 RF_ACTIVE); 750 if (sc->cfg_res == NULL) { 751 device_printf(dev, "Cannot allocate config space(rid: %d)\n", 752 rid); 753 rv = ENXIO; 754 goto out; 755 } 756 757 /* Fill up config region related variables */ 758 sc->cfg_size = rman_get_size(sc->cfg_res); 759 sc->cfg_pa = rman_get_start(sc->cfg_res) ; 760 761 if (bootverbose) 762 device_printf(dev, "Bus is%s cache-coherent\n", 763 sc->coherent ? "" : " not"); 764 rv = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 765 1, 0, /* alignment, bounds */ 766 BUS_SPACE_MAXADDR, /* lowaddr */ 767 BUS_SPACE_MAXADDR, /* highaddr */ 768 NULL, NULL, /* filter, filterarg */ 769 BUS_SPACE_MAXSIZE, /* maxsize */ 770 BUS_SPACE_UNRESTRICTED, /* nsegments */ 771 BUS_SPACE_MAXSIZE, /* maxsegsize */ 772 sc->coherent ? BUS_DMA_COHERENT : 0, /* flags */ 773 NULL, NULL, /* lockfunc, lockarg */ 774 &sc->dmat); 775 if (rv != 0) 776 goto out; 777 778 rv = ofw_pcib_init(dev); 779 if (rv != 0) 780 goto out; 781 rv = pci_dw_decode_ranges(sc, sc->ofw_pci.sc_range, 782 sc->ofw_pci.sc_nrange); 783 if (rv != 0) 784 goto out; 785 786 unroll_mode = pci_dw_detect_atu_unroll(sc); 787 if (bootverbose) 788 device_printf(dev, "Using iATU %s mode\n", 789 unroll_mode ? "unroll" : "legacy"); 790 if (unroll_mode) { 791 rid = 0; 792 rv = ofw_bus_find_string_index(sc->node, "reg-names", "atu", &rid); 793 if (rv == 0) { 794 sc->iatu_ur_res = bus_alloc_resource_any(dev, 795 SYS_RES_MEMORY, &rid, RF_ACTIVE); 796 if (sc->iatu_ur_res == NULL) { 797 device_printf(dev, 798 "Cannot allocate iATU space (rid: %d)\n", 799 rid); 800 rv = ENXIO; 801 goto out; 802 } 803 sc->iatu_ur_offset = 0; 804 sc->iatu_ur_size = rman_get_size(sc->iatu_ur_res); 805 } else if (rv == ENOENT) { 806 sc->iatu_ur_res = sc->dbi_res; 807 sc->iatu_ur_offset = DW_DEFAULT_IATU_UR_DBI_OFFSET; 808 sc->iatu_ur_size = DW_DEFAULT_IATU_UR_DBI_SIZE; 809 } else { 810 device_printf(dev, "Cannot get iATU space memory\n"); 811 rv = ENXIO; 812 goto out; 813 } 814 } 815 816 rv = pci_dw_detect_out_atu_regions(sc); 817 if (rv != 0) 818 goto out; 819 820 if (bootverbose) 821 device_printf(sc->dev, "Detected outbound iATU regions: %d\n", 822 sc->num_out_regions); 823 824 rv = pci_dw_setup_hw(sc); 825 if (rv != 0) 826 goto out; 827 828 device_add_child(dev, "pci", -1); 829 830 return (0); 831 out: 832 /* XXX Cleanup */ 833 return (rv); 834 } 835 836 static device_method_t pci_dw_methods[] = { 837 /* Bus interface */ 838 DEVMETHOD(bus_get_dma_tag, pci_dw_get_dma_tag), 839 840 /* pcib interface */ 841 DEVMETHOD(pcib_read_config, pci_dw_read_config), 842 DEVMETHOD(pcib_write_config, pci_dw_write_config), 843 DEVMETHOD(pcib_alloc_msi, pci_dw_alloc_msi), 844 DEVMETHOD(pcib_release_msi, pci_dw_release_msi), 845 DEVMETHOD(pcib_alloc_msix, pci_dw_alloc_msix), 846 DEVMETHOD(pcib_release_msix, pci_dw_release_msix), 847 DEVMETHOD(pcib_map_msi, pci_dw_map_msi), 848 DEVMETHOD(pcib_get_id, pci_dw_get_id), 849 850 /* OFW bus interface */ 851 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 852 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 853 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 854 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 855 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 856 857 /* PCI DW interface */ 858 DEVMETHOD(pci_dw_dbi_read, pci_dw_dbi_read), 859 DEVMETHOD(pci_dw_dbi_write, pci_dw_dbi_write), 860 DEVMETHOD_END 861 }; 862 863 DEFINE_CLASS_1(pcib, pci_dw_driver, pci_dw_methods, 864 sizeof(struct pci_dw_softc), ofw_pcib_driver); 865