1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /* Base class for all Synopsys DesignWare PCI/PCIe drivers */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/devmap.h> 38 #include <sys/proc.h> 39 #include <sys/kernel.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/module.h> 43 #include <sys/mutex.h> 44 #include <sys/rman.h> 45 46 #include <machine/bus.h> 47 #include <machine/intr.h> 48 #include <machine/resource.h> 49 50 #include <dev/ofw/ofw_bus.h> 51 #include <dev/ofw/ofw_bus_subr.h> 52 #include <dev/ofw/ofw_pci.h> 53 #include <dev/ofw/ofwpci.h> 54 #include <dev/pci/pcivar.h> 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcib_private.h> 57 #include <dev/pci/pci_dw.h> 58 59 #include "pcib_if.h" 60 #include "pci_dw_if.h" 61 62 #define DEBUG 63 #ifdef DEBUG 64 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 65 #else 66 #define debugf(fmt, args...) 67 #endif 68 69 #define DBI_WR1(sc, reg, val) pci_dw_dbi_wr1((sc)->dev, reg, val) 70 #define DBI_WR2(sc, reg, val) pci_dw_dbi_wr2((sc)->dev, reg, val) 71 #define DBI_WR4(sc, reg, val) pci_dw_dbi_wr4((sc)->dev, reg, val) 72 #define DBI_RD1(sc, reg) pci_dw_dbi_rd1((sc)->dev, reg) 73 #define DBI_RD2(sc, reg) pci_dw_dbi_rd2((sc)->dev, reg) 74 #define DBI_RD4(sc, reg) pci_dw_dbi_rd4((sc)->dev, reg) 75 76 #define PCI_BUS_SHIFT 20 77 #define PCI_SLOT_SHIFT 15 78 #define PCI_FUNC_SHIFT 12 79 #define PCI_BUS_MASK 0xFF 80 #define PCI_SLOT_MASK 0x1F 81 #define PCI_FUNC_MASK 0x07 82 #define PCI_REG_MASK 0xFFF 83 84 #define IATU_CFG_BUS(bus) ((uint64_t)((bus) & 0xff) << 24) 85 #define IATU_CFG_SLOT(slot) ((uint64_t)((slot) & 0x1f) << 19) 86 #define IATU_CFG_FUNC(func) ((uint64_t)((func) & 0x07) << 16) 87 88 static uint32_t 89 pci_dw_dbi_read(device_t dev, u_int reg, int width) 90 { 91 struct pci_dw_softc *sc; 92 93 sc = device_get_softc(dev); 94 MPASS(sc->dbi_res != NULL); 95 96 switch (width) { 97 case 4: 98 return (bus_read_4(sc->dbi_res, reg)); 99 case 2: 100 return (bus_read_2(sc->dbi_res, reg)); 101 case 1: 102 return (bus_read_1(sc->dbi_res, reg)); 103 default: 104 device_printf(sc->dev, "Unsupported width: %d\n", width); 105 return (0xFFFFFFFF); 106 } 107 } 108 109 static void 110 pci_dw_dbi_write(device_t dev, u_int reg, uint32_t val, int width) 111 { 112 struct pci_dw_softc *sc; 113 114 sc = device_get_softc(dev); 115 MPASS(sc->dbi_res != NULL); 116 117 switch (width) { 118 case 4: 119 bus_write_4(sc->dbi_res, reg, val); 120 break; 121 case 2: 122 bus_write_2(sc->dbi_res, reg, val); 123 break; 124 case 1: 125 bus_write_1(sc->dbi_res, reg, val); 126 break; 127 default: 128 device_printf(sc->dev, "Unsupported width: %d\n", width); 129 break; 130 } 131 } 132 133 static void 134 pci_dw_dbi_protect(struct pci_dw_softc *sc, bool protect) 135 { 136 uint32_t reg; 137 138 reg = DBI_RD4(sc, DW_MISC_CONTROL_1); 139 if (protect) 140 reg &= ~DBI_RO_WR_EN; 141 else 142 reg |= DBI_RO_WR_EN; 143 DBI_WR4(sc, DW_MISC_CONTROL_1, reg); 144 } 145 146 static bool 147 pci_dw_check_dev(struct pci_dw_softc *sc, u_int bus, u_int slot, u_int func, 148 u_int reg) 149 { 150 bool status; 151 int rv; 152 153 if (bus < sc->bus_start || bus > sc->bus_end || slot > PCI_SLOTMAX || 154 func > PCI_FUNCMAX || reg > PCIE_REGMAX) 155 return (false); 156 157 /* link is needed for access to all non-root busses */ 158 if (bus != sc->root_bus) { 159 rv = PCI_DW_GET_LINK(sc->dev, &status); 160 if (rv != 0 || !status) 161 return (false); 162 return (true); 163 } 164 165 /* we have only 1 device with 1 function root port */ 166 if (slot > 0 || func > 0) 167 return (false); 168 return (true); 169 } 170 171 /* Map one uoutbound ATU region */ 172 static int 173 pci_dw_map_out_atu(struct pci_dw_softc *sc, int idx, int type, 174 uint64_t pa, uint64_t pci_addr, uint32_t size) 175 { 176 uint32_t reg; 177 int i; 178 179 if (size == 0) 180 return (0); 181 182 DBI_WR4(sc, DW_IATU_VIEWPORT, IATU_REGION_INDEX(idx)); 183 DBI_WR4(sc, DW_IATU_LWR_BASE_ADDR, pa & 0xFFFFFFFF); 184 DBI_WR4(sc, DW_IATU_UPPER_BASE_ADDR, (pa >> 32) & 0xFFFFFFFF); 185 DBI_WR4(sc, DW_IATU_LIMIT_ADDR, (pa + size - 1) & 0xFFFFFFFF); 186 DBI_WR4(sc, DW_IATU_LWR_TARGET_ADDR, pci_addr & 0xFFFFFFFF); 187 DBI_WR4(sc, DW_IATU_UPPER_TARGET_ADDR, (pci_addr >> 32) & 0xFFFFFFFF); 188 DBI_WR4(sc, DW_IATU_CTRL1, IATU_CTRL1_TYPE(type)); 189 DBI_WR4(sc, DW_IATU_CTRL2, IATU_CTRL2_REGION_EN); 190 191 /* Wait until setup becomes valid */ 192 for (i = 10; i > 0; i--) { 193 reg = DBI_RD4(sc, DW_IATU_CTRL2); 194 if (reg & IATU_CTRL2_REGION_EN) 195 return (0); 196 DELAY(5); 197 } 198 device_printf(sc->dev, 199 "Cannot map outbound region(%d) in iATU\n", idx); 200 return (ETIMEDOUT); 201 } 202 203 static int 204 pci_dw_setup_hw(struct pci_dw_softc *sc) 205 { 206 uint32_t reg; 207 int rv; 208 209 pci_dw_dbi_protect(sc, false); 210 211 /* Setup config registers */ 212 DBI_WR1(sc, PCIR_CLASS, PCIC_BRIDGE); 213 DBI_WR1(sc, PCIR_SUBCLASS, PCIS_BRIDGE_PCI); 214 DBI_WR4(sc, PCIR_BAR(0), 4); 215 DBI_WR4(sc, PCIR_BAR(1), 0); 216 DBI_WR1(sc, PCIR_INTPIN, 1); 217 DBI_WR1(sc, PCIR_PRIBUS_1, sc->root_bus); 218 DBI_WR1(sc, PCIR_SECBUS_1, sc->sub_bus); 219 DBI_WR1(sc, PCIR_SUBBUS_1, sc->bus_end); 220 DBI_WR2(sc, PCIR_COMMAND, 221 PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | 222 PCIM_CMD_BUSMASTEREN | PCIM_CMD_SERRESPEN); 223 pci_dw_dbi_protect(sc, true); 224 225 /* Setup outbound memory window */ 226 rv = pci_dw_map_out_atu(sc, 0, IATU_CTRL1_TYPE_MEM, 227 sc->mem_range.host, sc->mem_range.pci, sc->mem_range.size); 228 if (rv != 0) 229 return (rv); 230 231 /* If we have enouht viewports ..*/ 232 if (sc->num_viewport >= 3 && sc->io_range.size != 0) { 233 /* Setup outbound I/O window */ 234 rv = pci_dw_map_out_atu(sc, 2, IATU_CTRL1_TYPE_IO, 235 sc->io_range.host, sc->io_range.pci, sc->io_range.size); 236 if (rv != 0) 237 return (rv); 238 } 239 /* XXX Should we handle also prefetch memory? */ 240 241 /* Adjust number of lanes */ 242 reg = DBI_RD4(sc, DW_PORT_LINK_CTRL); 243 reg &= ~PORT_LINK_CAPABLE(~0); 244 switch (sc->num_lanes) { 245 case 1: 246 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_1); 247 break; 248 case 2: 249 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_2); 250 break; 251 case 4: 252 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_4); 253 break; 254 case 8: 255 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_8); 256 break; 257 case 16: 258 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_16); 259 break; 260 case 32: 261 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_32); 262 break; 263 default: 264 device_printf(sc->dev, 265 "'num-lanes' property have invalid value: %d\n", 266 sc->num_lanes); 267 return (EINVAL); 268 } 269 DBI_WR4(sc, DW_PORT_LINK_CTRL, reg); 270 271 /* And link width */ 272 reg = DBI_RD4(sc, DW_GEN2_CTRL); 273 reg &= ~GEN2_CTRL_NUM_OF_LANES(~0); 274 switch (sc->num_lanes) { 275 case 1: 276 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_1); 277 break; 278 case 2: 279 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_2); 280 break; 281 case 4: 282 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_4); 283 break; 284 case 8: 285 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_8); 286 break; 287 case 16: 288 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_16); 289 break; 290 case 32: 291 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_32); 292 break; 293 } 294 DBI_WR4(sc, DW_GEN2_CTRL, reg); 295 296 reg = DBI_RD4(sc, DW_GEN2_CTRL); 297 reg |= DIRECT_SPEED_CHANGE; 298 DBI_WR4(sc, DW_GEN2_CTRL, reg); 299 300 return (0); 301 } 302 303 static int 304 pci_dw_decode_ranges(struct pci_dw_softc *sc, struct ofw_pci_range *ranges, 305 int nranges) 306 { 307 int i; 308 309 for (i = 0; i < nranges; i++) { 310 if ((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 311 OFW_PCI_PHYS_HI_SPACE_IO) { 312 if (sc->io_range.size != 0) { 313 device_printf(sc->dev, 314 "Duplicated IO range found in DT\n"); 315 return (ENXIO); 316 } 317 sc->io_range = ranges[i]; 318 } 319 if (((ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 320 OFW_PCI_PHYS_HI_SPACE_MEM32)) { 321 if (ranges[i].pci_hi & OFW_PCI_PHYS_HI_PREFETCHABLE) { 322 if (sc->pref_mem_range.size != 0) { 323 device_printf(sc->dev, 324 "Duplicated memory range found " 325 "in DT\n"); 326 return (ENXIO); 327 } 328 sc->pref_mem_range = ranges[i]; 329 } else { 330 if (sc->mem_range.size != 0) { 331 device_printf(sc->dev, 332 "Duplicated memory range found " 333 "in DT\n"); 334 return (ENXIO); 335 } 336 sc->mem_range = ranges[i]; 337 } 338 } 339 } 340 if (sc->mem_range.size == 0) { 341 device_printf(sc->dev, 342 " Not all required ranges are found in DT\n"); 343 return (ENXIO); 344 } 345 if (sc->io_range.size > UINT32_MAX) { 346 device_printf(sc->dev, 347 "ATU IO window size is too large. Up to 4GB windows " 348 "are supported, trimming window size to 4GB\n"); 349 sc->io_range.size = UINT32_MAX; 350 } 351 if (sc->mem_range.size > UINT32_MAX) { 352 device_printf(sc->dev, 353 "ATU MEM window size is too large. Up to 4GB windows " 354 "are supported, trimming window size to 4GB\n"); 355 sc->mem_range.size = UINT32_MAX; 356 } 357 return (0); 358 } 359 360 /*----------------------------------------------------------------------------- 361 * 362 * P C I B I N T E R F A C E 363 */ 364 365 static uint32_t 366 pci_dw_read_config(device_t dev, u_int bus, u_int slot, 367 u_int func, u_int reg, int bytes) 368 { 369 struct pci_dw_softc *sc; 370 struct resource *res; 371 uint32_t data; 372 uint64_t addr; 373 int type, rv; 374 375 sc = device_get_softc(dev); 376 377 if (!pci_dw_check_dev(sc, bus, slot, func, reg)) 378 return (0xFFFFFFFFU); 379 380 if (bus == sc->root_bus) { 381 res = (sc->dbi_res); 382 } else { 383 addr = IATU_CFG_BUS(bus) | IATU_CFG_SLOT(slot) | 384 IATU_CFG_FUNC(func); 385 if (bus == sc->sub_bus) 386 type = IATU_CTRL1_TYPE_CFG0; 387 else 388 type = IATU_CTRL1_TYPE_CFG1; 389 rv = pci_dw_map_out_atu(sc, 1, type, 390 sc->cfg_pa, addr, sc->cfg_size); 391 if (rv != 0) 392 return (0xFFFFFFFFU); 393 res = sc->cfg_res; 394 } 395 396 switch (bytes) { 397 case 1: 398 data = bus_read_1(res, reg); 399 break; 400 case 2: 401 data = bus_read_2(res, reg); 402 break; 403 case 4: 404 data = bus_read_4(res, reg); 405 break; 406 default: 407 data = 0xFFFFFFFFU; 408 } 409 410 return (data); 411 412 } 413 414 static void 415 pci_dw_write_config(device_t dev, u_int bus, u_int slot, 416 u_int func, u_int reg, uint32_t val, int bytes) 417 { 418 struct pci_dw_softc *sc; 419 struct resource *res; 420 uint64_t addr; 421 int type, rv; 422 423 sc = device_get_softc(dev); 424 if (!pci_dw_check_dev(sc, bus, slot, func, reg)) 425 return; 426 427 if (bus == sc->root_bus) { 428 res = (sc->dbi_res); 429 } else { 430 addr = IATU_CFG_BUS(bus) | IATU_CFG_SLOT(slot) | 431 IATU_CFG_FUNC(func); 432 if (bus == sc->sub_bus) 433 type = IATU_CTRL1_TYPE_CFG0; 434 else 435 type = IATU_CTRL1_TYPE_CFG1; 436 rv = pci_dw_map_out_atu(sc, 1, type, 437 sc->cfg_pa, addr, sc->cfg_size); 438 if (rv != 0) 439 return ; 440 res = sc->cfg_res; 441 } 442 443 switch (bytes) { 444 case 1: 445 bus_write_1(res, reg, val); 446 break; 447 case 2: 448 bus_write_2(res, reg, val); 449 break; 450 case 4: 451 bus_write_4(res, reg, val); 452 break; 453 default: 454 break; 455 } 456 } 457 458 static int 459 pci_dw_alloc_msi(device_t pci, device_t child, int count, 460 int maxcount, int *irqs) 461 { 462 phandle_t msi_parent; 463 int rv; 464 465 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 466 &msi_parent, NULL); 467 if (rv != 0) 468 return (rv); 469 470 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount, 471 irqs)); 472 } 473 474 static int 475 pci_dw_release_msi(device_t pci, device_t child, int count, int *irqs) 476 { 477 phandle_t msi_parent; 478 int rv; 479 480 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 481 &msi_parent, NULL); 482 if (rv != 0) 483 return (rv); 484 return (intr_release_msi(pci, child, msi_parent, count, irqs)); 485 } 486 487 static int 488 pci_dw_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 489 uint32_t *data) 490 { 491 phandle_t msi_parent; 492 int rv; 493 494 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 495 &msi_parent, NULL); 496 if (rv != 0) 497 return (rv); 498 499 return (intr_map_msi(pci, child, msi_parent, irq, addr, data)); 500 } 501 502 static int 503 pci_dw_alloc_msix(device_t pci, device_t child, int *irq) 504 { 505 phandle_t msi_parent; 506 int rv; 507 508 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 509 &msi_parent, NULL); 510 if (rv != 0) 511 return (rv); 512 return (intr_alloc_msix(pci, child, msi_parent, irq)); 513 } 514 515 static int 516 pci_dw_release_msix(device_t pci, device_t child, int irq) 517 { 518 phandle_t msi_parent; 519 int rv; 520 521 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 522 &msi_parent, NULL); 523 if (rv != 0) 524 return (rv); 525 return (intr_release_msix(pci, child, msi_parent, irq)); 526 } 527 528 static int 529 pci_dw_get_id(device_t pci, device_t child, enum pci_id_type type, 530 uintptr_t *id) 531 { 532 phandle_t node; 533 int rv; 534 uint32_t rid; 535 uint16_t pci_rid; 536 537 if (type != PCI_ID_MSI) 538 return (pcib_get_id(pci, child, type, id)); 539 540 node = ofw_bus_get_node(pci); 541 pci_rid = pci_get_rid(child); 542 543 rv = ofw_bus_msimap(node, pci_rid, NULL, &rid); 544 if (rv != 0) 545 return (rv); 546 *id = rid; 547 548 return (0); 549 } 550 551 /*----------------------------------------------------------------------------- 552 * 553 * B U S / D E V I C E I N T E R F A C E 554 */ 555 static bus_dma_tag_t 556 pci_dw_get_dma_tag(device_t dev, device_t child) 557 { 558 struct pci_dw_softc *sc; 559 560 sc = device_get_softc(dev); 561 return (sc->dmat); 562 } 563 564 int 565 pci_dw_init(device_t dev) 566 { 567 struct pci_dw_softc *sc; 568 int rv, rid; 569 570 sc = device_get_softc(dev); 571 sc->dev = dev; 572 sc->node = ofw_bus_get_node(dev); 573 574 mtx_init(&sc->mtx, "pci_dw_mtx", NULL, MTX_DEF); 575 576 /* XXXn Should not be this configurable ? */ 577 sc->bus_start = 0; 578 sc->bus_end = 255; 579 sc->root_bus = 0; 580 sc->sub_bus = 1; 581 582 /* Read FDT properties */ 583 if (!sc->coherent) 584 sc->coherent = OF_hasprop(sc->node, "dma-coherent"); 585 586 rv = OF_getencprop(sc->node, "num-viewport", &sc->num_viewport, 587 sizeof(sc->num_viewport)); 588 if (rv != sizeof(sc->num_viewport)) 589 sc->num_viewport = 2; 590 591 rv = OF_getencprop(sc->node, "num-lanes", &sc->num_lanes, 592 sizeof(sc->num_viewport)); 593 if (rv != sizeof(sc->num_lanes)) 594 sc->num_lanes = 1; 595 if (sc->num_lanes != 1 && sc->num_lanes != 2 && 596 sc->num_lanes != 4 && sc->num_lanes != 8) { 597 device_printf(dev, 598 "invalid number of lanes: %d\n",sc->num_lanes); 599 sc->num_lanes = 0; 600 rv = ENXIO; 601 goto out; 602 } 603 604 rid = 0; 605 rv = ofw_bus_find_string_index(sc->node, "reg-names", "config", &rid); 606 if (rv != 0) { 607 device_printf(dev, "Cannot get config space memory\n"); 608 rv = ENXIO; 609 goto out; 610 } 611 sc->cfg_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 612 RF_ACTIVE); 613 if (sc->cfg_res == NULL) { 614 device_printf(dev, "Cannot allocate config space(rid: %d)\n", 615 rid); 616 rv = ENXIO; 617 goto out; 618 } 619 620 /* Fill up config region related variables */ 621 sc->cfg_size = rman_get_size(sc->cfg_res); 622 sc->cfg_pa = rman_get_start(sc->cfg_res) ; 623 624 if (bootverbose) 625 device_printf(dev, "Bus is%s cache-coherent\n", 626 sc->coherent ? "" : " not"); 627 rv = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 628 1, 0, /* alignment, bounds */ 629 BUS_SPACE_MAXADDR, /* lowaddr */ 630 BUS_SPACE_MAXADDR, /* highaddr */ 631 NULL, NULL, /* filter, filterarg */ 632 BUS_SPACE_MAXSIZE, /* maxsize */ 633 BUS_SPACE_UNRESTRICTED, /* nsegments */ 634 BUS_SPACE_MAXSIZE, /* maxsegsize */ 635 sc->coherent ? BUS_DMA_COHERENT : 0, /* flags */ 636 NULL, NULL, /* lockfunc, lockarg */ 637 &sc->dmat); 638 if (rv != 0) 639 goto out; 640 641 rv = ofw_pcib_init(dev); 642 if (rv != 0) 643 goto out; 644 rv = pci_dw_decode_ranges(sc, sc->ofw_pci.sc_range, 645 sc->ofw_pci.sc_nrange); 646 if (rv != 0) 647 goto out; 648 649 rv = pci_dw_setup_hw(sc); 650 if (rv != 0) 651 goto out; 652 653 device_add_child(dev, "pci", -1); 654 655 return (0); 656 out: 657 /* XXX Cleanup */ 658 return (rv); 659 } 660 661 static device_method_t pci_dw_methods[] = { 662 /* Bus interface */ 663 DEVMETHOD(bus_get_dma_tag, pci_dw_get_dma_tag), 664 665 /* pcib interface */ 666 DEVMETHOD(pcib_read_config, pci_dw_read_config), 667 DEVMETHOD(pcib_write_config, pci_dw_write_config), 668 DEVMETHOD(pcib_alloc_msi, pci_dw_alloc_msi), 669 DEVMETHOD(pcib_release_msi, pci_dw_release_msi), 670 DEVMETHOD(pcib_alloc_msix, pci_dw_alloc_msix), 671 DEVMETHOD(pcib_release_msix, pci_dw_release_msix), 672 DEVMETHOD(pcib_map_msi, pci_dw_map_msi), 673 DEVMETHOD(pcib_get_id, pci_dw_get_id), 674 675 /* OFW bus interface */ 676 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 677 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 678 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 679 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 680 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 681 682 /* PCI DW interface */ 683 DEVMETHOD(pci_dw_dbi_read, pci_dw_dbi_read), 684 DEVMETHOD(pci_dw_dbi_write, pci_dw_dbi_write), 685 DEVMETHOD_END 686 }; 687 688 DEFINE_CLASS_1(pcib, pci_dw_driver, pci_dw_methods, 689 sizeof(struct pci_dw_softc), ofw_pcib_driver); 690