1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /* Base class for all Synopsys DesignWare PCI/PCIe drivers */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/proc.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 #include <sys/rman.h> 41 42 #include <machine/bus.h> 43 #include <machine/intr.h> 44 #include <machine/resource.h> 45 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 #include <dev/ofw/ofw_pci.h> 49 #include <dev/ofw/ofwpci.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcib_private.h> 53 #include <dev/pci/pci_dw.h> 54 55 #include "pcib_if.h" 56 #include "pci_dw_if.h" 57 58 #if 0 59 #define dprintf(fmt, args...) do { printf(fmt,##args); } while (0) 60 #else 61 #define dprintf(fmt, args...) 62 #endif 63 64 #define DBI_WR1(sc, reg, val) pci_dw_dbi_wr1((sc)->dev, reg, val) 65 #define DBI_WR2(sc, reg, val) pci_dw_dbi_wr2((sc)->dev, reg, val) 66 #define DBI_WR4(sc, reg, val) pci_dw_dbi_wr4((sc)->dev, reg, val) 67 #define DBI_RD1(sc, reg) pci_dw_dbi_rd1((sc)->dev, reg) 68 #define DBI_RD2(sc, reg) pci_dw_dbi_rd2((sc)->dev, reg) 69 #define DBI_RD4(sc, reg) pci_dw_dbi_rd4((sc)->dev, reg) 70 71 #define IATU_UR_WR4(sc, reg, val) \ 72 bus_write_4((sc)->iatu_ur_res, (sc)->iatu_ur_offset + (reg), (val)) 73 #define IATU_UR_RD4(sc, reg) \ 74 bus_read_4((sc)->iatu_ur_res, (sc)->iatu_ur_offset + (reg)) 75 76 #define PCI_BUS_SHIFT 20 77 #define PCI_SLOT_SHIFT 15 78 #define PCI_FUNC_SHIFT 12 79 #define PCI_BUS_MASK 0xFF 80 #define PCI_SLOT_MASK 0x1F 81 #define PCI_FUNC_MASK 0x07 82 #define PCI_REG_MASK 0xFFF 83 84 #define IATU_CFG_BUS(bus) ((uint64_t)((bus) & 0xff) << 24) 85 #define IATU_CFG_SLOT(slot) ((uint64_t)((slot) & 0x1f) << 19) 86 #define IATU_CFG_FUNC(func) ((uint64_t)((func) & 0x07) << 16) 87 88 static uint32_t 89 pci_dw_dbi_read(device_t dev, u_int reg, int width) 90 { 91 struct pci_dw_softc *sc; 92 93 sc = device_get_softc(dev); 94 MPASS(sc->dbi_res != NULL); 95 dprintf("%s: reg: 0x%04X, width: %d\n", __func__, reg, width); 96 switch (width) { 97 case 4: 98 return (bus_read_4(sc->dbi_res, reg)); 99 case 2: 100 return (bus_read_2(sc->dbi_res, reg)); 101 case 1: 102 return (bus_read_1(sc->dbi_res, reg)); 103 default: 104 device_printf(sc->dev, "Unsupported width: %d\n", width); 105 return (0xFFFFFFFF); 106 } 107 } 108 109 static void 110 pci_dw_dbi_write(device_t dev, u_int reg, uint32_t val, int width) 111 { 112 struct pci_dw_softc *sc; 113 114 sc = device_get_softc(dev); 115 MPASS(sc->dbi_res != NULL); 116 dprintf("%s: reg: 0x%04X, val: 0x%08X, width: %d\n", __func__, 117 reg, val, width); 118 119 switch (width) { 120 case 4: 121 bus_write_4(sc->dbi_res, reg, val); 122 break; 123 case 2: 124 bus_write_2(sc->dbi_res, reg, val); 125 break; 126 case 1: 127 bus_write_1(sc->dbi_res, reg, val); 128 break; 129 default: 130 device_printf(sc->dev, "Unsupported width: %d\n", width); 131 break; 132 } 133 } 134 135 static void 136 pci_dw_dbi_protect(struct pci_dw_softc *sc, bool protect) 137 { 138 uint32_t reg; 139 140 reg = DBI_RD4(sc, DW_MISC_CONTROL_1); 141 if (protect) 142 reg &= ~DBI_RO_WR_EN; 143 else 144 reg |= DBI_RO_WR_EN; 145 DBI_WR4(sc, DW_MISC_CONTROL_1, reg); 146 } 147 148 static bool 149 pci_dw_check_dev(struct pci_dw_softc *sc, u_int bus, u_int slot, u_int func, 150 u_int reg) 151 { 152 bool status; 153 int rv; 154 155 if (bus < sc->bus_start || bus > sc->bus_end || slot > PCI_SLOTMAX || 156 func > PCI_FUNCMAX || reg > PCIE_REGMAX) 157 return (false); 158 159 /* link is needed for access to all non-root busses */ 160 if (bus != sc->root_bus) { 161 rv = PCI_DW_GET_LINK(sc->dev, &status); 162 if (rv != 0 || !status) 163 return (false); 164 return (true); 165 } 166 167 /* we have only 1 device with 1 function on root port */ 168 if (slot > 0 || func > 0) 169 return (false); 170 return (true); 171 } 172 173 static bool 174 pci_dw_detect_atu_unroll(struct pci_dw_softc *sc) 175 { 176 return (DBI_RD4(sc, DW_IATU_VIEWPORT) == 0xFFFFFFFFU); 177 } 178 179 static int 180 pci_dw_detect_out_atu_regions_unroll(struct pci_dw_softc *sc) 181 { 182 int num_regions, i; 183 uint32_t reg; 184 185 num_regions = sc->iatu_ur_size / DW_IATU_UR_STEP; 186 187 for (i = 0; i < num_regions; ++i) { 188 IATU_UR_WR4(sc, DW_IATU_UR_REG(i, LWR_TARGET_ADDR), 189 0x12340000); 190 reg = IATU_UR_RD4(sc, DW_IATU_UR_REG(i, LWR_TARGET_ADDR)); 191 if (reg != 0x12340000) 192 break; 193 } 194 195 sc->num_out_regions = i; 196 197 return (0); 198 } 199 200 static int 201 pci_dw_detect_out_atu_regions_legacy(struct pci_dw_softc *sc) 202 { 203 int num_viewports, i; 204 uint32_t reg; 205 206 /* Find out how many viewports there are in total */ 207 DBI_WR4(sc, DW_IATU_VIEWPORT, IATU_REGION_INDEX(~0U)); 208 reg = DBI_RD4(sc, DW_IATU_VIEWPORT); 209 if (reg > IATU_REGION_INDEX(~0U)) { 210 device_printf(sc->dev, 211 "Cannot detect number of output iATU regions; read %#x\n", 212 reg); 213 return (ENXIO); 214 } 215 216 num_viewports = reg + 1; 217 218 /* 219 * Find out how many of them are outbound by seeing whether a dummy 220 * page-aligned address sticks. 221 */ 222 for (i = 0; i < num_viewports; ++i) { 223 DBI_WR4(sc, DW_IATU_VIEWPORT, IATU_REGION_INDEX(i)); 224 DBI_WR4(sc, DW_IATU_LWR_TARGET_ADDR, 0x12340000); 225 reg = DBI_RD4(sc, DW_IATU_LWR_TARGET_ADDR); 226 if (reg != 0x12340000) 227 break; 228 } 229 230 sc->num_out_regions = i; 231 232 return (0); 233 } 234 235 static int 236 pci_dw_detect_out_atu_regions(struct pci_dw_softc *sc) 237 { 238 if (sc->iatu_ur_res) 239 return (pci_dw_detect_out_atu_regions_unroll(sc)); 240 else 241 return (pci_dw_detect_out_atu_regions_legacy(sc)); 242 } 243 244 static int 245 pci_dw_map_out_atu_unroll(struct pci_dw_softc *sc, int idx, int type, 246 uint64_t pa, uint64_t pci_addr, uint32_t size) 247 { 248 uint32_t reg; 249 int i; 250 251 if (size == 0) 252 return (0); 253 254 IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, LWR_BASE_ADDR), 255 pa & 0xFFFFFFFF); 256 IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, UPPER_BASE_ADDR), 257 (pa >> 32) & 0xFFFFFFFF); 258 IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, LIMIT_ADDR), 259 (pa + size - 1) & 0xFFFFFFFF); 260 IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, LWR_TARGET_ADDR), 261 pci_addr & 0xFFFFFFFF); 262 IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, UPPER_TARGET_ADDR), 263 (pci_addr >> 32) & 0xFFFFFFFF); 264 IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, CTRL1), 265 IATU_CTRL1_TYPE(type)); 266 IATU_UR_WR4(sc, DW_IATU_UR_REG(idx, CTRL2), 267 IATU_CTRL2_REGION_EN); 268 269 /* Wait until setup becomes valid */ 270 for (i = 10; i > 0; i--) { 271 reg = IATU_UR_RD4(sc, DW_IATU_UR_REG(idx, CTRL2)); 272 if (reg & IATU_CTRL2_REGION_EN) 273 return (0); 274 DELAY(5); 275 } 276 277 device_printf(sc->dev, 278 "Cannot map outbound region %d in unroll mode iATU\n", idx); 279 return (ETIMEDOUT); 280 } 281 282 static int 283 pci_dw_map_out_atu_legacy(struct pci_dw_softc *sc, int idx, int type, 284 uint64_t pa, uint64_t pci_addr, uint32_t size) 285 { 286 uint32_t reg; 287 int i; 288 289 if (size == 0) 290 return (0); 291 292 DBI_WR4(sc, DW_IATU_VIEWPORT, IATU_REGION_INDEX(idx)); 293 DBI_WR4(sc, DW_IATU_LWR_BASE_ADDR, pa & 0xFFFFFFFF); 294 DBI_WR4(sc, DW_IATU_UPPER_BASE_ADDR, (pa >> 32) & 0xFFFFFFFF); 295 DBI_WR4(sc, DW_IATU_LIMIT_ADDR, (pa + size - 1) & 0xFFFFFFFF); 296 DBI_WR4(sc, DW_IATU_LWR_TARGET_ADDR, pci_addr & 0xFFFFFFFF); 297 DBI_WR4(sc, DW_IATU_UPPER_TARGET_ADDR, (pci_addr >> 32) & 0xFFFFFFFF); 298 DBI_WR4(sc, DW_IATU_CTRL1, IATU_CTRL1_TYPE(type)); 299 DBI_WR4(sc, DW_IATU_CTRL2, IATU_CTRL2_REGION_EN); 300 301 /* Wait until setup becomes valid */ 302 for (i = 10; i > 0; i--) { 303 reg = DBI_RD4(sc, DW_IATU_CTRL2); 304 if (reg & IATU_CTRL2_REGION_EN) 305 return (0); 306 DELAY(5); 307 } 308 309 device_printf(sc->dev, 310 "Cannot map outbound region %d in legacy mode iATU\n", idx); 311 return (ETIMEDOUT); 312 } 313 314 /* Map one outbound ATU region */ 315 static int 316 pci_dw_map_out_atu(struct pci_dw_softc *sc, int idx, int type, 317 uint64_t pa, uint64_t pci_addr, uint32_t size) 318 { 319 if (sc->iatu_ur_res) 320 return (pci_dw_map_out_atu_unroll(sc, idx, type, pa, 321 pci_addr, size)); 322 else 323 return (pci_dw_map_out_atu_legacy(sc, idx, type, pa, 324 pci_addr, size)); 325 } 326 327 static int 328 pci_dw_setup_hw(struct pci_dw_softc *sc) 329 { 330 uint32_t reg; 331 int rv, i; 332 333 pci_dw_dbi_protect(sc, false); 334 335 /* Setup config registers */ 336 DBI_WR1(sc, PCIR_CLASS, PCIC_BRIDGE); 337 DBI_WR1(sc, PCIR_SUBCLASS, PCIS_BRIDGE_PCI); 338 DBI_WR4(sc, PCIR_BAR(0), 4); 339 DBI_WR4(sc, PCIR_BAR(1), 0); 340 DBI_WR1(sc, PCIR_INTPIN, 1); 341 DBI_WR1(sc, PCIR_PRIBUS_1, sc->root_bus); 342 DBI_WR1(sc, PCIR_SECBUS_1, sc->sub_bus); 343 DBI_WR1(sc, PCIR_SUBBUS_1, sc->bus_end); 344 DBI_WR2(sc, PCIR_COMMAND, 345 PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | 346 PCIM_CMD_BUSMASTEREN | PCIM_CMD_SERRESPEN); 347 pci_dw_dbi_protect(sc, true); 348 349 /* Setup outbound memory windows */ 350 for (i = 0; i < min(sc->num_mem_ranges, sc->num_out_regions - 1); ++i) { 351 rv = pci_dw_map_out_atu(sc, i + 1, IATU_CTRL1_TYPE_MEM, 352 sc->mem_ranges[i].host, sc->mem_ranges[i].pci, 353 sc->mem_ranges[i].size); 354 if (rv != 0) 355 return (rv); 356 } 357 358 /* If we have enough regions ... */ 359 if (sc->num_mem_ranges + 1 < sc->num_out_regions && 360 sc->io_range.size != 0) { 361 /* Setup outbound I/O window */ 362 rv = pci_dw_map_out_atu(sc, sc->num_mem_ranges + 1, 363 IATU_CTRL1_TYPE_IO, sc->io_range.host, sc->io_range.pci, 364 sc->io_range.size); 365 if (rv != 0) 366 return (rv); 367 } 368 369 /* Adjust number of lanes */ 370 reg = DBI_RD4(sc, DW_PORT_LINK_CTRL); 371 reg &= ~PORT_LINK_CAPABLE(~0); 372 switch (sc->num_lanes) { 373 case 1: 374 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_1); 375 break; 376 case 2: 377 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_2); 378 break; 379 case 4: 380 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_4); 381 break; 382 case 8: 383 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_8); 384 break; 385 case 16: 386 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_16); 387 break; 388 case 32: 389 reg |= PORT_LINK_CAPABLE(PORT_LINK_CAPABLE_32); 390 break; 391 default: 392 device_printf(sc->dev, 393 "'num-lanes' property have invalid value: %d\n", 394 sc->num_lanes); 395 return (EINVAL); 396 } 397 DBI_WR4(sc, DW_PORT_LINK_CTRL, reg); 398 399 /* And link width */ 400 reg = DBI_RD4(sc, DW_GEN2_CTRL); 401 reg &= ~GEN2_CTRL_NUM_OF_LANES(~0); 402 switch (sc->num_lanes) { 403 case 1: 404 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_1); 405 break; 406 case 2: 407 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_2); 408 break; 409 case 4: 410 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_4); 411 break; 412 case 8: 413 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_8); 414 break; 415 case 16: 416 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_16); 417 break; 418 case 32: 419 reg |= GEN2_CTRL_NUM_OF_LANES(GEN2_CTRL_NUM_OF_LANES_32); 420 break; 421 } 422 DBI_WR4(sc, DW_GEN2_CTRL, reg); 423 424 reg = DBI_RD4(sc, DW_GEN2_CTRL); 425 reg |= DIRECT_SPEED_CHANGE; 426 DBI_WR4(sc, DW_GEN2_CTRL, reg); 427 428 return (0); 429 } 430 431 static int 432 pci_dw_decode_ranges(struct pci_dw_softc *sc, struct ofw_pci_range *ranges, 433 int nranges) 434 { 435 int i, nmem, rv; 436 437 nmem = 0; 438 for (i = 0; i < nranges; i++) { 439 switch (ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) { 440 case OFW_PCI_PHYS_HI_SPACE_MEM32: 441 case OFW_PCI_PHYS_HI_SPACE_MEM64: 442 ++nmem; 443 break; 444 default: 445 break; 446 } 447 } 448 449 sc->mem_ranges = malloc(nmem * sizeof(*sc->mem_ranges), M_DEVBUF, 450 M_WAITOK); 451 sc->num_mem_ranges = nmem; 452 453 nmem = 0; 454 for (i = 0; i < nranges; i++) { 455 switch (ranges[i].pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) { 456 457 case OFW_PCI_PHYS_HI_SPACE_IO: 458 if (sc->io_range.size != 0) { 459 device_printf(sc->dev, 460 "Duplicated IO range found in DT\n"); 461 rv = ENXIO; 462 goto out; 463 } 464 465 sc->io_range = ranges[i]; 466 if (sc->io_range.size > UINT32_MAX) { 467 device_printf(sc->dev, 468 "ATU IO window size is too large. " 469 "Up to 4GB windows are supported, " 470 "trimming window size to 4GB\n"); 471 sc->io_range.size = UINT32_MAX; 472 } 473 break; 474 475 case OFW_PCI_PHYS_HI_SPACE_MEM32: 476 case OFW_PCI_PHYS_HI_SPACE_MEM64: 477 MPASS(nmem < sc->num_mem_ranges); 478 sc->mem_ranges[nmem] = ranges[i]; 479 if (sc->mem_ranges[nmem].size > UINT32_MAX) { 480 device_printf(sc->dev, 481 "ATU MEM window size is too large. " 482 "Up to 4GB windows are supported, " 483 "trimming window size to 4GB\n"); 484 sc->mem_ranges[nmem].size = UINT32_MAX; 485 } 486 ++nmem; 487 break; 488 489 default: 490 device_printf(sc->dev, 491 "%s: Unsupported range type (0x%X)\n", 492 __func__, ranges[i].pci_hi & 493 OFW_PCI_PHYS_HI_SPACEMASK); 494 } 495 } 496 497 MPASS(nmem == sc->num_mem_ranges); 498 499 if (nmem == 0) { 500 device_printf(sc->dev, 501 "Missing required memory range in DT\n"); 502 return (ENXIO); 503 } 504 505 return (0); 506 507 out: 508 free(sc->mem_ranges, M_DEVBUF); 509 return (rv); 510 } 511 512 /*----------------------------------------------------------------------------- 513 * 514 * P C I B I N T E R F A C E 515 */ 516 517 static uint32_t 518 pci_dw_read_config(device_t dev, u_int bus, u_int slot, 519 u_int func, u_int reg, int bytes) 520 { 521 struct pci_dw_softc *sc; 522 struct resource *res; 523 uint32_t data; 524 uint64_t addr; 525 int type, rv; 526 527 sc = device_get_softc(dev); 528 529 if (!pci_dw_check_dev(sc, bus, slot, func, reg)) 530 return (0xFFFFFFFFU); 531 532 if (bus == sc->root_bus) { 533 res = (sc->dbi_res); 534 } else { 535 addr = IATU_CFG_BUS(bus) | IATU_CFG_SLOT(slot) | 536 IATU_CFG_FUNC(func); 537 if (bus == sc->sub_bus) 538 type = IATU_CTRL1_TYPE_CFG0; 539 else 540 type = IATU_CTRL1_TYPE_CFG1; 541 rv = pci_dw_map_out_atu(sc, 0, type, 542 sc->cfg_pa, addr, sc->cfg_size); 543 if (rv != 0) 544 return (0xFFFFFFFFU); 545 res = sc->cfg_res; 546 } 547 548 switch (bytes) { 549 case 1: 550 data = bus_read_1(res, reg); 551 break; 552 case 2: 553 data = bus_read_2(res, reg); 554 break; 555 case 4: 556 data = bus_read_4(res, reg); 557 break; 558 default: 559 data = 0xFFFFFFFFU; 560 } 561 562 return (data); 563 564 } 565 566 static void 567 pci_dw_write_config(device_t dev, u_int bus, u_int slot, 568 u_int func, u_int reg, uint32_t val, int bytes) 569 { 570 struct pci_dw_softc *sc; 571 struct resource *res; 572 uint64_t addr; 573 int type, rv; 574 575 sc = device_get_softc(dev); 576 if (!pci_dw_check_dev(sc, bus, slot, func, reg)) 577 return; 578 579 if (bus == sc->root_bus) { 580 res = (sc->dbi_res); 581 } else { 582 addr = IATU_CFG_BUS(bus) | IATU_CFG_SLOT(slot) | 583 IATU_CFG_FUNC(func); 584 if (bus == sc->sub_bus) 585 type = IATU_CTRL1_TYPE_CFG0; 586 else 587 type = IATU_CTRL1_TYPE_CFG1; 588 rv = pci_dw_map_out_atu(sc, 0, type, 589 sc->cfg_pa, addr, sc->cfg_size); 590 if (rv != 0) 591 return ; 592 res = sc->cfg_res; 593 } 594 595 switch (bytes) { 596 case 1: 597 bus_write_1(res, reg, val); 598 break; 599 case 2: 600 bus_write_2(res, reg, val); 601 break; 602 case 4: 603 bus_write_4(res, reg, val); 604 break; 605 default: 606 break; 607 } 608 } 609 610 static int 611 pci_dw_alloc_msi(device_t pci, device_t child, int count, 612 int maxcount, int *irqs) 613 { 614 phandle_t msi_parent; 615 int rv; 616 617 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 618 &msi_parent, NULL); 619 if (rv != 0) 620 return (rv); 621 622 return (intr_alloc_msi(pci, child, msi_parent, count, maxcount, 623 irqs)); 624 } 625 626 static int 627 pci_dw_release_msi(device_t pci, device_t child, int count, int *irqs) 628 { 629 phandle_t msi_parent; 630 int rv; 631 632 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 633 &msi_parent, NULL); 634 if (rv != 0) 635 return (rv); 636 return (intr_release_msi(pci, child, msi_parent, count, irqs)); 637 } 638 639 static int 640 pci_dw_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, 641 uint32_t *data) 642 { 643 phandle_t msi_parent; 644 int rv; 645 646 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 647 &msi_parent, NULL); 648 if (rv != 0) 649 return (rv); 650 651 return (intr_map_msi(pci, child, msi_parent, irq, addr, data)); 652 } 653 654 static int 655 pci_dw_alloc_msix(device_t pci, device_t child, int *irq) 656 { 657 phandle_t msi_parent; 658 int rv; 659 660 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 661 &msi_parent, NULL); 662 if (rv != 0) 663 return (rv); 664 return (intr_alloc_msix(pci, child, msi_parent, irq)); 665 } 666 667 static int 668 pci_dw_release_msix(device_t pci, device_t child, int irq) 669 { 670 phandle_t msi_parent; 671 int rv; 672 673 rv = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), 674 &msi_parent, NULL); 675 if (rv != 0) 676 return (rv); 677 return (intr_release_msix(pci, child, msi_parent, irq)); 678 } 679 680 static int 681 pci_dw_get_id(device_t pci, device_t child, enum pci_id_type type, 682 uintptr_t *id) 683 { 684 phandle_t node; 685 int rv; 686 uint32_t rid; 687 uint16_t pci_rid; 688 689 if (type != PCI_ID_MSI) 690 return (pcib_get_id(pci, child, type, id)); 691 692 node = ofw_bus_get_node(pci); 693 pci_rid = pci_get_rid(child); 694 695 rv = ofw_bus_msimap(node, pci_rid, NULL, &rid); 696 if (rv != 0) 697 return (rv); 698 *id = rid; 699 700 return (0); 701 } 702 703 /*----------------------------------------------------------------------------- 704 * 705 * B U S / D E V I C E I N T E R F A C E 706 */ 707 static bus_dma_tag_t 708 pci_dw_get_dma_tag(device_t dev, device_t child) 709 { 710 struct pci_dw_softc *sc; 711 712 sc = device_get_softc(dev); 713 return (sc->dmat); 714 } 715 716 int 717 pci_dw_init(device_t dev) 718 { 719 struct pci_dw_softc *sc; 720 int rv, rid; 721 bool unroll_mode; 722 u_int32_t br[2]; 723 724 sc = device_get_softc(dev); 725 sc->dev = dev; 726 sc->node = ofw_bus_get_node(dev); 727 728 mtx_init(&sc->mtx, "pci_dw_mtx", NULL, MTX_DEF); 729 730 if (OF_hasprop(sc->node, "bus-range")) { 731 rv = OF_getencprop(sc->node, "bus-range", br, sizeof(br)); 732 if (rv < 0) { 733 device_printf(dev, 734 "Cannot read 'bus-range' property: %d\n", rv); 735 rv = ENXIO; 736 goto out; 737 } 738 if (rv != 8) { 739 device_printf(dev, 740 "Malformed 'bus-range' property: %d\n", rv); 741 rv = ENXIO; 742 goto out; 743 } 744 sc->bus_start = br[0]; 745 sc->bus_end = br[1]; 746 } else { 747 sc->bus_start = 0; 748 sc->bus_end = 255; 749 } 750 sc->root_bus = sc->bus_start; 751 sc->sub_bus = sc->bus_start + 1; 752 dprintf("%s: bus range[%d..%d], root bus %d, sub bus: %d\n", __func__, 753 sc->bus_end, sc->bus_start, sc->root_bus, sc->sub_bus); 754 755 /* Read FDT properties */ 756 if (!sc->coherent) 757 sc->coherent = OF_hasprop(sc->node, "dma-coherent"); 758 759 rv = OF_getencprop(sc->node, "num-lanes", &sc->num_lanes, 760 sizeof(sc->num_lanes)); 761 if (rv != sizeof(sc->num_lanes)) 762 sc->num_lanes = 1; 763 dprintf("%s: num lanes: %d\n", __func__, sc->num_lanes); 764 765 if (sc->num_lanes != 1 && sc->num_lanes != 2 && 766 sc->num_lanes != 4 && sc->num_lanes != 8) { 767 device_printf(dev, 768 "invalid number of lanes: %d\n",sc->num_lanes); 769 sc->num_lanes = 0; 770 rv = ENXIO; 771 goto out; 772 } 773 774 rid = 0; 775 rv = ofw_bus_find_string_index(sc->node, "reg-names", "config", &rid); 776 if (rv != 0) { 777 device_printf(dev, "Cannot get config space memory\n"); 778 rv = ENXIO; 779 goto out; 780 } 781 sc->cfg_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 782 RF_ACTIVE); 783 if (sc->cfg_res == NULL) { 784 device_printf(dev, "Cannot allocate config space(rid: %d)\n", 785 rid); 786 rv = ENXIO; 787 goto out; 788 } 789 790 /* Fill up config region related variables */ 791 sc->cfg_size = rman_get_size(sc->cfg_res); 792 sc->cfg_pa = rman_get_start(sc->cfg_res) ; 793 794 if (bootverbose) 795 device_printf(dev, "Bus is%s cache-coherent\n", 796 sc->coherent ? "" : " not"); 797 rv = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 798 1, 0, /* alignment, bounds */ 799 BUS_SPACE_MAXADDR, /* lowaddr */ 800 BUS_SPACE_MAXADDR, /* highaddr */ 801 NULL, NULL, /* filter, filterarg */ 802 BUS_SPACE_MAXSIZE, /* maxsize */ 803 BUS_SPACE_UNRESTRICTED, /* nsegments */ 804 BUS_SPACE_MAXSIZE, /* maxsegsize */ 805 sc->coherent ? BUS_DMA_COHERENT : 0, /* flags */ 806 NULL, NULL, /* lockfunc, lockarg */ 807 &sc->dmat); 808 if (rv != 0) 809 goto out; 810 rv = ofw_pcib_init(dev); 811 if (rv != 0) 812 goto out; 813 rv = pci_dw_decode_ranges(sc, sc->ofw_pci.sc_range, 814 sc->ofw_pci.sc_nrange); 815 if (rv != 0) 816 goto out; 817 818 dprintf("%s: version: 0x%08X, version type:0x%08X\n", __func__, 819 DBI_RD4(sc, DW_MISC_VERSION), DBI_RD4(sc, DW_MISC_VERSION_TYPE)); 820 821 unroll_mode = pci_dw_detect_atu_unroll(sc); 822 if (bootverbose) 823 device_printf(dev, "Using iATU %s mode\n", 824 unroll_mode ? "unroll" : "legacy"); 825 if (unroll_mode) { 826 rid = 0; 827 rv = ofw_bus_find_string_index(sc->node, "reg-names", "atu", &rid); 828 if (rv == 0) { 829 dprintf("%s: Have 'atu' regs\n", __func__); 830 sc->iatu_ur_res = bus_alloc_resource_any(dev, 831 SYS_RES_MEMORY, &rid, RF_ACTIVE); 832 if (sc->iatu_ur_res == NULL) { 833 device_printf(dev, 834 "Cannot allocate iATU space (rid: %d)\n", 835 rid); 836 rv = ENXIO; 837 goto out; 838 } 839 sc->iatu_ur_offset = 0; 840 sc->iatu_ur_size = rman_get_size(sc->iatu_ur_res); 841 } else if (rv == ENOENT) { 842 dprintf("%s: Using 'dbi' regs for atu\n", __func__); 843 sc->iatu_ur_res = sc->dbi_res; 844 sc->iatu_ur_offset = DW_DEFAULT_IATU_UR_DBI_OFFSET; 845 sc->iatu_ur_size = DW_DEFAULT_IATU_UR_DBI_SIZE; 846 } else { 847 device_printf(dev, "Cannot get iATU space memory\n"); 848 rv = ENXIO; 849 goto out; 850 } 851 } 852 853 rv = pci_dw_detect_out_atu_regions(sc); 854 if (rv != 0) 855 goto out; 856 857 if (bootverbose) 858 device_printf(sc->dev, "Detected outbound iATU regions: %d\n", 859 sc->num_out_regions); 860 861 rv = pci_dw_setup_hw(sc); 862 if (rv != 0) 863 goto out; 864 865 device_add_child(dev, "pci", DEVICE_UNIT_ANY); 866 867 return (0); 868 out: 869 /* XXX Cleanup */ 870 return (rv); 871 } 872 873 static device_method_t pci_dw_methods[] = { 874 /* Bus interface */ 875 DEVMETHOD(bus_get_dma_tag, pci_dw_get_dma_tag), 876 877 /* pcib interface */ 878 DEVMETHOD(pcib_read_config, pci_dw_read_config), 879 DEVMETHOD(pcib_write_config, pci_dw_write_config), 880 DEVMETHOD(pcib_alloc_msi, pci_dw_alloc_msi), 881 DEVMETHOD(pcib_release_msi, pci_dw_release_msi), 882 DEVMETHOD(pcib_alloc_msix, pci_dw_alloc_msix), 883 DEVMETHOD(pcib_release_msix, pci_dw_release_msix), 884 DEVMETHOD(pcib_map_msi, pci_dw_map_msi), 885 DEVMETHOD(pcib_get_id, pci_dw_get_id), 886 887 /* OFW bus interface */ 888 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 889 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 890 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 891 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 892 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 893 894 /* PCI DW interface */ 895 DEVMETHOD(pci_dw_dbi_read, pci_dw_dbi_read), 896 DEVMETHOD(pci_dw_dbi_write, pci_dw_dbi_write), 897 DEVMETHOD_END 898 }; 899 900 DEFINE_CLASS_1(pcib, pci_dw_driver, pci_dw_methods, 901 sizeof(struct pci_dw_softc), ofw_pcib_driver); 902