1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 5 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000, BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice unmodified, this list of conditions, and the following 14 * disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "opt_acpi.h" 35 #include "opt_iommu.h" 36 #include "opt_bus.h" 37 38 #include <sys/param.h> 39 #include <sys/conf.h> 40 #include <sys/endian.h> 41 #include <sys/eventhandler.h> 42 #include <sys/fcntl.h> 43 #include <sys/kernel.h> 44 #include <sys/limits.h> 45 #include <sys/linker.h> 46 #include <sys/malloc.h> 47 #include <sys/module.h> 48 #include <sys/queue.h> 49 #include <sys/sbuf.h> 50 #include <sys/sysctl.h> 51 #include <sys/systm.h> 52 #include <sys/taskqueue.h> 53 #include <sys/tree.h> 54 55 #include <vm/vm.h> 56 #include <vm/pmap.h> 57 #include <vm/vm_extern.h> 58 59 #include <sys/bus.h> 60 #include <machine/bus.h> 61 #include <sys/rman.h> 62 #include <machine/resource.h> 63 #include <machine/stdarg.h> 64 65 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 66 #include <machine/intr_machdep.h> 67 #endif 68 69 #include <sys/pciio.h> 70 #include <dev/pci/pcireg.h> 71 #include <dev/pci/pcivar.h> 72 #include <dev/pci/pci_private.h> 73 74 #ifdef PCI_IOV 75 #include <sys/nv.h> 76 #include <dev/pci/pci_iov_private.h> 77 #endif 78 79 #include <dev/usb/controller/xhcireg.h> 80 #include <dev/usb/controller/ehcireg.h> 81 #include <dev/usb/controller/ohcireg.h> 82 #include <dev/usb/controller/uhcireg.h> 83 84 #include <dev/iommu/iommu.h> 85 86 #include "pcib_if.h" 87 #include "pci_if.h" 88 89 #define PCIR_IS_BIOS(cfg, reg) \ 90 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ 91 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) 92 93 static int pci_has_quirk(uint32_t devid, int quirk); 94 static pci_addr_t pci_mapbase(uint64_t mapreg); 95 static const char *pci_maptype(uint64_t mapreg); 96 static int pci_maprange(uint64_t mapreg); 97 static pci_addr_t pci_rombase(uint64_t mapreg); 98 static int pci_romsize(uint64_t testval); 99 static void pci_fixancient(pcicfgregs *cfg); 100 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...); 101 102 static int pci_porten(device_t dev); 103 static int pci_memen(device_t dev); 104 static void pci_assign_interrupt(device_t bus, device_t dev, 105 int force_route); 106 static int pci_add_map(device_t bus, device_t dev, int reg, 107 struct resource_list *rl, int force, int prefetch); 108 static int pci_probe(device_t dev); 109 static void pci_load_vendor_data(void); 110 static int pci_describe_parse_line(char **ptr, int *vendor, 111 int *device, char **desc); 112 static char *pci_describe_device(device_t dev); 113 static int pci_modevent(module_t mod, int what, void *arg); 114 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 115 pcicfgregs *cfg); 116 static void pci_read_cap(device_t pcib, pcicfgregs *cfg); 117 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 118 int reg, uint32_t *data); 119 #if 0 120 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 121 int reg, uint32_t data); 122 #endif 123 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 124 static void pci_mask_msix(device_t dev, u_int index); 125 static void pci_unmask_msix(device_t dev, u_int index); 126 static int pci_msi_blacklisted(void); 127 static int pci_msix_blacklisted(void); 128 static void pci_resume_msi(device_t dev); 129 static void pci_resume_msix(device_t dev); 130 static int pci_remap_intr_method(device_t bus, device_t dev, 131 u_int irq); 132 static void pci_hint_device_unit(device_t acdev, device_t child, 133 const char *name, int *unitp); 134 static int pci_reset_post(device_t dev, device_t child); 135 static int pci_reset_prepare(device_t dev, device_t child); 136 static int pci_reset_child(device_t dev, device_t child, 137 int flags); 138 139 static int pci_get_id_method(device_t dev, device_t child, 140 enum pci_id_type type, uintptr_t *rid); 141 142 static struct pci_devinfo * pci_fill_devinfo(device_t pcib, device_t bus, int d, 143 int b, int s, int f, uint16_t vid, uint16_t did); 144 145 static device_method_t pci_methods[] = { 146 /* Device interface */ 147 DEVMETHOD(device_probe, pci_probe), 148 DEVMETHOD(device_attach, pci_attach), 149 DEVMETHOD(device_detach, pci_detach), 150 DEVMETHOD(device_shutdown, bus_generic_shutdown), 151 DEVMETHOD(device_suspend, bus_generic_suspend), 152 DEVMETHOD(device_resume, pci_resume), 153 154 /* Bus interface */ 155 DEVMETHOD(bus_print_child, pci_print_child), 156 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 157 DEVMETHOD(bus_read_ivar, pci_read_ivar), 158 DEVMETHOD(bus_write_ivar, pci_write_ivar), 159 DEVMETHOD(bus_driver_added, pci_driver_added), 160 DEVMETHOD(bus_setup_intr, pci_setup_intr), 161 DEVMETHOD(bus_teardown_intr, pci_teardown_intr), 162 DEVMETHOD(bus_reset_prepare, pci_reset_prepare), 163 DEVMETHOD(bus_reset_post, pci_reset_post), 164 DEVMETHOD(bus_reset_child, pci_reset_child), 165 166 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag), 167 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 168 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 169 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 170 DEVMETHOD(bus_delete_resource, pci_delete_resource), 171 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 172 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 173 DEVMETHOD(bus_release_resource, pci_release_resource), 174 DEVMETHOD(bus_activate_resource, pci_activate_resource), 175 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource), 176 DEVMETHOD(bus_child_deleted, pci_child_deleted), 177 DEVMETHOD(bus_child_detached, pci_child_detached), 178 DEVMETHOD(bus_child_pnpinfo, pci_child_pnpinfo_method), 179 DEVMETHOD(bus_child_location, pci_child_location_method), 180 DEVMETHOD(bus_hint_device_unit, pci_hint_device_unit), 181 DEVMETHOD(bus_remap_intr, pci_remap_intr_method), 182 DEVMETHOD(bus_suspend_child, pci_suspend_child), 183 DEVMETHOD(bus_resume_child, pci_resume_child), 184 DEVMETHOD(bus_rescan, pci_rescan_method), 185 186 /* PCI interface */ 187 DEVMETHOD(pci_read_config, pci_read_config_method), 188 DEVMETHOD(pci_write_config, pci_write_config_method), 189 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 190 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 191 DEVMETHOD(pci_enable_io, pci_enable_io_method), 192 DEVMETHOD(pci_disable_io, pci_disable_io_method), 193 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 194 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 195 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 196 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 197 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 198 DEVMETHOD(pci_find_cap, pci_find_cap_method), 199 DEVMETHOD(pci_find_next_cap, pci_find_next_cap_method), 200 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 201 DEVMETHOD(pci_find_next_extcap, pci_find_next_extcap_method), 202 DEVMETHOD(pci_find_htcap, pci_find_htcap_method), 203 DEVMETHOD(pci_find_next_htcap, pci_find_next_htcap_method), 204 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 205 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), 206 DEVMETHOD(pci_enable_msi, pci_enable_msi_method), 207 DEVMETHOD(pci_enable_msix, pci_enable_msix_method), 208 DEVMETHOD(pci_disable_msi, pci_disable_msi_method), 209 DEVMETHOD(pci_remap_msix, pci_remap_msix_method), 210 DEVMETHOD(pci_release_msi, pci_release_msi_method), 211 DEVMETHOD(pci_msi_count, pci_msi_count_method), 212 DEVMETHOD(pci_msix_count, pci_msix_count_method), 213 DEVMETHOD(pci_msix_pba_bar, pci_msix_pba_bar_method), 214 DEVMETHOD(pci_msix_table_bar, pci_msix_table_bar_method), 215 DEVMETHOD(pci_get_id, pci_get_id_method), 216 DEVMETHOD(pci_alloc_devinfo, pci_alloc_devinfo_method), 217 DEVMETHOD(pci_child_added, pci_child_added_method), 218 #ifdef PCI_IOV 219 DEVMETHOD(pci_iov_attach, pci_iov_attach_method), 220 DEVMETHOD(pci_iov_detach, pci_iov_detach_method), 221 DEVMETHOD(pci_create_iov_child, pci_create_iov_child_method), 222 #endif 223 224 DEVMETHOD_END 225 }; 226 227 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc)); 228 229 static devclass_t pci_devclass; 230 EARLY_DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL, 231 BUS_PASS_BUS); 232 MODULE_VERSION(pci, 1); 233 234 static char *pci_vendordata; 235 static size_t pci_vendordata_size; 236 237 struct pci_quirk { 238 uint32_t devid; /* Vendor/device of the card */ 239 int type; 240 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 241 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */ 242 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */ 243 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */ 244 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */ 245 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */ 246 #define PCI_QUIRK_REALLOC_BAR 7 /* Can't allocate memory at the default address */ 247 int arg1; 248 int arg2; 249 }; 250 251 static const struct pci_quirk pci_quirks[] = { 252 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */ 253 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 254 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 255 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 256 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 257 258 /* 259 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge 260 * or the CMIC-SL (AKA ServerWorks GC_LE). 261 */ 262 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 263 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 264 265 /* 266 * MSI doesn't work on earlier Intel chipsets including 267 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855. 268 */ 269 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 270 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 271 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 272 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 273 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 274 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 275 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 276 277 /* 278 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX 279 * bridge. 280 */ 281 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 282 283 /* 284 * Some virtualization environments emulate an older chipset 285 * but support MSI just fine. QEMU uses the Intel 82440. 286 */ 287 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 }, 288 289 /* 290 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus 291 * controller depending on SoftPciRst register (PM_IO 0x55 [7]). 292 * It prevents us from attaching hpet(4) when the bit is unset. 293 * Note this quirk only affects SB600 revision A13 and earlier. 294 * For SB600 A21 and later, firmware must set the bit to hide it. 295 * For SB700 and later, it is unused and hardcoded to zero. 296 */ 297 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 }, 298 299 /* 300 * Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have 301 * a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit 302 * of the command register is set. 303 */ 304 { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 305 { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 306 { 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 307 { 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 308 { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 309 310 /* 311 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't 312 * issue MSI interrupts with PCIM_CMD_INTxDIS set either. 313 */ 314 { 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */ 315 { 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */ 316 { 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */ 317 { 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */ 318 { 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */ 319 { 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */ 320 321 /* 322 * HPE Gen 10 VGA has a memory range that can't be allocated in the 323 * expected place. 324 */ 325 { 0x98741002, PCI_QUIRK_REALLOC_BAR, 0, 0 }, 326 { 0 } 327 }; 328 329 /* map register information */ 330 #define PCI_MAPMEM 0x01 /* memory map */ 331 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 332 #define PCI_MAPPORT 0x04 /* port map */ 333 334 struct devlist pci_devq; 335 uint32_t pci_generation; 336 uint32_t pci_numdevs = 0; 337 static int pcie_chipset, pcix_chipset; 338 339 /* sysctl vars */ 340 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 341 "PCI bus tuning parameters"); 342 343 static int pci_enable_io_modes = 1; 344 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RWTUN, 345 &pci_enable_io_modes, 1, 346 "Enable I/O and memory bits in the config register. Some BIOSes do not" 347 " enable these bits correctly. We'd like to do this all the time, but" 348 " there are some peripherals that this causes problems with."); 349 350 static int pci_do_realloc_bars = 1; 351 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RWTUN, 352 &pci_do_realloc_bars, 0, 353 "Attempt to allocate a new range for any BARs whose original " 354 "firmware-assigned ranges fail to allocate during the initial device scan."); 355 356 static int pci_do_power_nodriver = 0; 357 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RWTUN, 358 &pci_do_power_nodriver, 0, 359 "Place a function into D3 state when no driver attaches to it. 0 means" 360 " disable. 1 means conservatively place devices into D3 state. 2 means" 361 " aggressively place devices into D3 state. 3 means put absolutely" 362 " everything in D3 state."); 363 364 int pci_do_power_resume = 1; 365 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RWTUN, 366 &pci_do_power_resume, 1, 367 "Transition from D3 -> D0 on resume."); 368 369 int pci_do_power_suspend = 1; 370 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RWTUN, 371 &pci_do_power_suspend, 1, 372 "Transition from D0 -> D3 on suspend."); 373 374 static int pci_do_msi = 1; 375 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RWTUN, &pci_do_msi, 1, 376 "Enable support for MSI interrupts"); 377 378 static int pci_do_msix = 1; 379 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RWTUN, &pci_do_msix, 1, 380 "Enable support for MSI-X interrupts"); 381 382 static int pci_msix_rewrite_table = 0; 383 SYSCTL_INT(_hw_pci, OID_AUTO, msix_rewrite_table, CTLFLAG_RWTUN, 384 &pci_msix_rewrite_table, 0, 385 "Rewrite entire MSI-X table when updating MSI-X entries"); 386 387 static int pci_honor_msi_blacklist = 1; 388 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RDTUN, 389 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X"); 390 391 #if defined(__i386__) || defined(__amd64__) 392 static int pci_usb_takeover = 1; 393 #else 394 static int pci_usb_takeover = 0; 395 #endif 396 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN, 397 &pci_usb_takeover, 1, 398 "Enable early takeover of USB controllers. Disable this if you depend on" 399 " BIOS emulation of USB devices, that is you use USB devices (like" 400 " keyboard or mouse) but do not load USB drivers"); 401 402 static int pci_clear_bars; 403 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0, 404 "Ignore firmware-assigned resources for BARs."); 405 406 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 407 static int pci_clear_buses; 408 SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0, 409 "Ignore firmware-assigned bus numbers."); 410 #endif 411 412 static int pci_enable_ari = 1; 413 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari, 414 0, "Enable support for PCIe Alternative RID Interpretation"); 415 416 int pci_enable_aspm = 1; 417 SYSCTL_INT(_hw_pci, OID_AUTO, enable_aspm, CTLFLAG_RDTUN, &pci_enable_aspm, 418 0, "Enable support for PCIe Active State Power Management"); 419 420 static int pci_clear_aer_on_attach = 0; 421 SYSCTL_INT(_hw_pci, OID_AUTO, clear_aer_on_attach, CTLFLAG_RWTUN, 422 &pci_clear_aer_on_attach, 0, 423 "Clear port and device AER state on driver attach"); 424 425 static int 426 pci_has_quirk(uint32_t devid, int quirk) 427 { 428 const struct pci_quirk *q; 429 430 for (q = &pci_quirks[0]; q->devid; q++) { 431 if (q->devid == devid && q->type == quirk) 432 return (1); 433 } 434 return (0); 435 } 436 437 /* Find a device_t by bus/slot/function in domain 0 */ 438 439 device_t 440 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 441 { 442 443 return (pci_find_dbsf(0, bus, slot, func)); 444 } 445 446 /* Find a device_t by domain/bus/slot/function */ 447 448 device_t 449 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func) 450 { 451 struct pci_devinfo *dinfo = NULL; 452 453 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 454 if ((dinfo->cfg.domain == domain) && 455 (dinfo->cfg.bus == bus) && 456 (dinfo->cfg.slot == slot) && 457 (dinfo->cfg.func == func)) { 458 break; 459 } 460 } 461 462 return (dinfo != NULL ? dinfo->cfg.dev : NULL); 463 } 464 465 /* Find a device_t by vendor/device ID */ 466 467 device_t 468 pci_find_device(uint16_t vendor, uint16_t device) 469 { 470 struct pci_devinfo *dinfo; 471 472 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 473 if ((dinfo->cfg.vendor == vendor) && 474 (dinfo->cfg.device == device)) { 475 return (dinfo->cfg.dev); 476 } 477 } 478 479 return (NULL); 480 } 481 482 device_t 483 pci_find_class(uint8_t class, uint8_t subclass) 484 { 485 struct pci_devinfo *dinfo; 486 487 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 488 if (dinfo->cfg.baseclass == class && 489 dinfo->cfg.subclass == subclass) { 490 return (dinfo->cfg.dev); 491 } 492 } 493 494 return (NULL); 495 } 496 497 device_t 498 pci_find_class_from(uint8_t class, uint8_t subclass, device_t from) 499 { 500 struct pci_devinfo *dinfo; 501 bool found = false; 502 503 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 504 if (from != NULL && found == false) { 505 if (from != dinfo->cfg.dev) 506 continue; 507 found = true; 508 continue; 509 } 510 if (dinfo->cfg.baseclass == class && 511 dinfo->cfg.subclass == subclass) { 512 return (dinfo->cfg.dev); 513 } 514 } 515 516 return (NULL); 517 } 518 519 static int 520 pci_printf(pcicfgregs *cfg, const char *fmt, ...) 521 { 522 va_list ap; 523 int retval; 524 525 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, 526 cfg->func); 527 va_start(ap, fmt); 528 retval += vprintf(fmt, ap); 529 va_end(ap); 530 return (retval); 531 } 532 533 /* return base address of memory or port map */ 534 535 static pci_addr_t 536 pci_mapbase(uint64_t mapreg) 537 { 538 539 if (PCI_BAR_MEM(mapreg)) 540 return (mapreg & PCIM_BAR_MEM_BASE); 541 else 542 return (mapreg & PCIM_BAR_IO_BASE); 543 } 544 545 /* return map type of memory or port map */ 546 547 static const char * 548 pci_maptype(uint64_t mapreg) 549 { 550 551 if (PCI_BAR_IO(mapreg)) 552 return ("I/O Port"); 553 if (mapreg & PCIM_BAR_MEM_PREFETCH) 554 return ("Prefetchable Memory"); 555 return ("Memory"); 556 } 557 558 /* return log2 of map size decoded for memory or port map */ 559 560 int 561 pci_mapsize(uint64_t testval) 562 { 563 int ln2size; 564 565 testval = pci_mapbase(testval); 566 ln2size = 0; 567 if (testval != 0) { 568 while ((testval & 1) == 0) 569 { 570 ln2size++; 571 testval >>= 1; 572 } 573 } 574 return (ln2size); 575 } 576 577 /* return base address of device ROM */ 578 579 static pci_addr_t 580 pci_rombase(uint64_t mapreg) 581 { 582 583 return (mapreg & PCIM_BIOS_ADDR_MASK); 584 } 585 586 /* return log2 of map size decided for device ROM */ 587 588 static int 589 pci_romsize(uint64_t testval) 590 { 591 int ln2size; 592 593 testval = pci_rombase(testval); 594 ln2size = 0; 595 if (testval != 0) { 596 while ((testval & 1) == 0) 597 { 598 ln2size++; 599 testval >>= 1; 600 } 601 } 602 return (ln2size); 603 } 604 605 /* return log2 of address range supported by map register */ 606 607 static int 608 pci_maprange(uint64_t mapreg) 609 { 610 int ln2range = 0; 611 612 if (PCI_BAR_IO(mapreg)) 613 ln2range = 32; 614 else 615 switch (mapreg & PCIM_BAR_MEM_TYPE) { 616 case PCIM_BAR_MEM_32: 617 ln2range = 32; 618 break; 619 case PCIM_BAR_MEM_1MB: 620 ln2range = 20; 621 break; 622 case PCIM_BAR_MEM_64: 623 ln2range = 64; 624 break; 625 } 626 return (ln2range); 627 } 628 629 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 630 631 static void 632 pci_fixancient(pcicfgregs *cfg) 633 { 634 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 635 return; 636 637 /* PCI to PCI bridges use header type 1 */ 638 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 639 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; 640 } 641 642 /* extract header type specific config data */ 643 644 static void 645 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 646 { 647 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 648 switch (cfg->hdrtype & PCIM_HDRTYPE) { 649 case PCIM_HDRTYPE_NORMAL: 650 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 651 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 652 cfg->mingnt = REG(PCIR_MINGNT, 1); 653 cfg->maxlat = REG(PCIR_MAXLAT, 1); 654 cfg->nummaps = PCI_MAXMAPS_0; 655 break; 656 case PCIM_HDRTYPE_BRIDGE: 657 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1); 658 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1); 659 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1); 660 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1); 661 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2); 662 cfg->nummaps = PCI_MAXMAPS_1; 663 break; 664 case PCIM_HDRTYPE_CARDBUS: 665 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1); 666 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1); 667 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1); 668 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1); 669 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2); 670 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 671 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 672 cfg->nummaps = PCI_MAXMAPS_2; 673 break; 674 } 675 #undef REG 676 } 677 678 /* read configuration header into pcicfgregs structure */ 679 struct pci_devinfo * 680 pci_read_device(device_t pcib, device_t bus, int d, int b, int s, int f) 681 { 682 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 683 uint16_t vid, did; 684 685 vid = REG(PCIR_VENDOR, 2); 686 did = REG(PCIR_DEVICE, 2); 687 if (vid != 0xffff) 688 return (pci_fill_devinfo(pcib, bus, d, b, s, f, vid, did)); 689 690 return (NULL); 691 } 692 693 struct pci_devinfo * 694 pci_alloc_devinfo_method(device_t dev) 695 { 696 697 return (malloc(sizeof(struct pci_devinfo), M_DEVBUF, 698 M_WAITOK | M_ZERO)); 699 } 700 701 static struct pci_devinfo * 702 pci_fill_devinfo(device_t pcib, device_t bus, int d, int b, int s, int f, 703 uint16_t vid, uint16_t did) 704 { 705 struct pci_devinfo *devlist_entry; 706 pcicfgregs *cfg; 707 708 devlist_entry = PCI_ALLOC_DEVINFO(bus); 709 710 cfg = &devlist_entry->cfg; 711 712 cfg->domain = d; 713 cfg->bus = b; 714 cfg->slot = s; 715 cfg->func = f; 716 cfg->vendor = vid; 717 cfg->device = did; 718 cfg->cmdreg = REG(PCIR_COMMAND, 2); 719 cfg->statreg = REG(PCIR_STATUS, 2); 720 cfg->baseclass = REG(PCIR_CLASS, 1); 721 cfg->subclass = REG(PCIR_SUBCLASS, 1); 722 cfg->progif = REG(PCIR_PROGIF, 1); 723 cfg->revid = REG(PCIR_REVID, 1); 724 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 725 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 726 cfg->lattimer = REG(PCIR_LATTIMER, 1); 727 cfg->intpin = REG(PCIR_INTPIN, 1); 728 cfg->intline = REG(PCIR_INTLINE, 1); 729 730 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 731 cfg->hdrtype &= ~PCIM_MFDEV; 732 STAILQ_INIT(&cfg->maps); 733 734 cfg->iov = NULL; 735 736 pci_fixancient(cfg); 737 pci_hdrtypedata(pcib, b, s, f, cfg); 738 739 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 740 pci_read_cap(pcib, cfg); 741 742 STAILQ_INSERT_TAIL(&pci_devq, devlist_entry, pci_links); 743 744 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; 745 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 746 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 747 devlist_entry->conf.pc_sel.pc_func = cfg->func; 748 devlist_entry->conf.pc_hdr = cfg->hdrtype; 749 750 devlist_entry->conf.pc_subvendor = cfg->subvendor; 751 devlist_entry->conf.pc_subdevice = cfg->subdevice; 752 devlist_entry->conf.pc_vendor = cfg->vendor; 753 devlist_entry->conf.pc_device = cfg->device; 754 755 devlist_entry->conf.pc_class = cfg->baseclass; 756 devlist_entry->conf.pc_subclass = cfg->subclass; 757 devlist_entry->conf.pc_progif = cfg->progif; 758 devlist_entry->conf.pc_revid = cfg->revid; 759 760 pci_numdevs++; 761 pci_generation++; 762 763 return (devlist_entry); 764 } 765 #undef REG 766 767 static void 768 pci_ea_fill_info(device_t pcib, pcicfgregs *cfg) 769 { 770 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \ 771 cfg->ea.ea_location + (n), w) 772 int num_ent; 773 int ptr; 774 int a, b; 775 uint32_t val; 776 int ent_size; 777 uint32_t dw[4]; 778 uint64_t base, max_offset; 779 struct pci_ea_entry *eae; 780 781 if (cfg->ea.ea_location == 0) 782 return; 783 784 STAILQ_INIT(&cfg->ea.ea_entries); 785 786 /* Determine the number of entries */ 787 num_ent = REG(PCIR_EA_NUM_ENT, 2); 788 num_ent &= PCIM_EA_NUM_ENT_MASK; 789 790 /* Find the first entry to care of */ 791 ptr = PCIR_EA_FIRST_ENT; 792 793 /* Skip DWORD 2 for type 1 functions */ 794 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) 795 ptr += 4; 796 797 for (a = 0; a < num_ent; a++) { 798 eae = malloc(sizeof(*eae), M_DEVBUF, M_WAITOK | M_ZERO); 799 eae->eae_cfg_offset = cfg->ea.ea_location + ptr; 800 801 /* Read a number of dwords in the entry */ 802 val = REG(ptr, 4); 803 ptr += 4; 804 ent_size = (val & PCIM_EA_ES); 805 806 for (b = 0; b < ent_size; b++) { 807 dw[b] = REG(ptr, 4); 808 ptr += 4; 809 } 810 811 eae->eae_flags = val; 812 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 813 814 base = dw[0] & PCIM_EA_FIELD_MASK; 815 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 816 b = 2; 817 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 818 base |= (uint64_t)dw[b] << 32UL; 819 b++; 820 } 821 if (((dw[1] & PCIM_EA_IS_64) != 0) 822 && (b < ent_size)) { 823 max_offset |= (uint64_t)dw[b] << 32UL; 824 b++; 825 } 826 827 eae->eae_base = base; 828 eae->eae_max_offset = max_offset; 829 830 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link); 831 832 if (bootverbose) { 833 printf("PCI(EA) dev %04x:%04x, bei %d, flags #%x, base #%jx, max_offset #%jx\n", 834 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags, 835 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset); 836 } 837 } 838 } 839 #undef REG 840 841 static void 842 pci_read_cap(device_t pcib, pcicfgregs *cfg) 843 { 844 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 845 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 846 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 847 uint64_t addr; 848 #endif 849 uint32_t val; 850 int ptr, nextptr, ptrptr; 851 852 switch (cfg->hdrtype & PCIM_HDRTYPE) { 853 case PCIM_HDRTYPE_NORMAL: 854 case PCIM_HDRTYPE_BRIDGE: 855 ptrptr = PCIR_CAP_PTR; 856 break; 857 case PCIM_HDRTYPE_CARDBUS: 858 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 859 break; 860 default: 861 return; /* no extended capabilities support */ 862 } 863 nextptr = REG(ptrptr, 1); /* sanity check? */ 864 865 /* 866 * Read capability entries. 867 */ 868 while (nextptr != 0) { 869 /* Sanity check */ 870 if (nextptr > 255) { 871 printf("illegal PCI extended capability offset %d\n", 872 nextptr); 873 return; 874 } 875 /* Find the next entry */ 876 ptr = nextptr; 877 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 878 879 /* Process this entry */ 880 switch (REG(ptr + PCICAP_ID, 1)) { 881 case PCIY_PMG: /* PCI power management */ 882 if (cfg->pp.pp_cap == 0) { 883 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 884 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 885 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE; 886 if ((nextptr - ptr) > PCIR_POWER_DATA) 887 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 888 } 889 break; 890 case PCIY_HT: /* HyperTransport */ 891 /* Determine HT-specific capability type. */ 892 val = REG(ptr + PCIR_HT_COMMAND, 2); 893 894 if ((val & 0xe000) == PCIM_HTCAP_SLAVE) 895 cfg->ht.ht_slave = ptr; 896 897 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 898 switch (val & PCIM_HTCMD_CAP_MASK) { 899 case PCIM_HTCAP_MSI_MAPPING: 900 if (!(val & PCIM_HTCMD_MSI_FIXED)) { 901 /* Sanity check the mapping window. */ 902 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 903 4); 904 addr <<= 32; 905 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 906 4); 907 if (addr != MSI_INTEL_ADDR_BASE) 908 device_printf(pcib, 909 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", 910 cfg->domain, cfg->bus, 911 cfg->slot, cfg->func, 912 (long long)addr); 913 } else 914 addr = MSI_INTEL_ADDR_BASE; 915 916 cfg->ht.ht_msimap = ptr; 917 cfg->ht.ht_msictrl = val; 918 cfg->ht.ht_msiaddr = addr; 919 break; 920 } 921 #endif 922 break; 923 case PCIY_MSI: /* PCI MSI */ 924 cfg->msi.msi_location = ptr; 925 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 926 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 927 PCIM_MSICTRL_MMC_MASK)>>1); 928 break; 929 case PCIY_MSIX: /* PCI MSI-X */ 930 cfg->msix.msix_location = ptr; 931 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 932 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl & 933 PCIM_MSIXCTRL_TABLE_SIZE) + 1; 934 val = REG(ptr + PCIR_MSIX_TABLE, 4); 935 cfg->msix.msix_table_bar = PCIR_BAR(val & 936 PCIM_MSIX_BIR_MASK); 937 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 938 val = REG(ptr + PCIR_MSIX_PBA, 4); 939 cfg->msix.msix_pba_bar = PCIR_BAR(val & 940 PCIM_MSIX_BIR_MASK); 941 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 942 break; 943 case PCIY_VPD: /* PCI Vital Product Data */ 944 cfg->vpd.vpd_reg = ptr; 945 break; 946 case PCIY_SUBVENDOR: 947 /* Should always be true. */ 948 if ((cfg->hdrtype & PCIM_HDRTYPE) == 949 PCIM_HDRTYPE_BRIDGE) { 950 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4); 951 cfg->subvendor = val & 0xffff; 952 cfg->subdevice = val >> 16; 953 } 954 break; 955 case PCIY_PCIX: /* PCI-X */ 956 /* 957 * Assume we have a PCI-X chipset if we have 958 * at least one PCI-PCI bridge with a PCI-X 959 * capability. Note that some systems with 960 * PCI-express or HT chipsets might match on 961 * this check as well. 962 */ 963 if ((cfg->hdrtype & PCIM_HDRTYPE) == 964 PCIM_HDRTYPE_BRIDGE) 965 pcix_chipset = 1; 966 cfg->pcix.pcix_location = ptr; 967 break; 968 case PCIY_EXPRESS: /* PCI-express */ 969 /* 970 * Assume we have a PCI-express chipset if we have 971 * at least one PCI-express device. 972 */ 973 pcie_chipset = 1; 974 cfg->pcie.pcie_location = ptr; 975 val = REG(ptr + PCIER_FLAGS, 2); 976 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; 977 break; 978 case PCIY_EA: /* Enhanced Allocation */ 979 cfg->ea.ea_location = ptr; 980 pci_ea_fill_info(pcib, cfg); 981 break; 982 default: 983 break; 984 } 985 } 986 987 #if defined(__powerpc__) 988 /* 989 * Enable the MSI mapping window for all HyperTransport 990 * slaves. PCI-PCI bridges have their windows enabled via 991 * PCIB_MAP_MSI(). 992 */ 993 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && 994 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { 995 device_printf(pcib, 996 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n", 997 cfg->domain, cfg->bus, cfg->slot, cfg->func); 998 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 999 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, 1000 2); 1001 } 1002 #endif 1003 /* REG and WREG use carry through to next functions */ 1004 } 1005 1006 /* 1007 * PCI Vital Product Data 1008 */ 1009 1010 #define PCI_VPD_TIMEOUT 1000000 1011 1012 static int 1013 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data) 1014 { 1015 int count = PCI_VPD_TIMEOUT; 1016 1017 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1018 1019 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); 1020 1021 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { 1022 if (--count < 0) 1023 return (ENXIO); 1024 DELAY(1); /* limit looping */ 1025 } 1026 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); 1027 1028 return (0); 1029 } 1030 1031 #if 0 1032 static int 1033 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 1034 { 1035 int count = PCI_VPD_TIMEOUT; 1036 1037 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1038 1039 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4); 1040 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2); 1041 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) { 1042 if (--count < 0) 1043 return (ENXIO); 1044 DELAY(1); /* limit looping */ 1045 } 1046 1047 return (0); 1048 } 1049 #endif 1050 1051 #undef PCI_VPD_TIMEOUT 1052 1053 struct vpd_readstate { 1054 device_t pcib; 1055 pcicfgregs *cfg; 1056 uint32_t val; 1057 int bytesinval; 1058 int off; 1059 uint8_t cksum; 1060 }; 1061 1062 static int 1063 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data) 1064 { 1065 uint32_t reg; 1066 uint8_t byte; 1067 1068 if (vrs->bytesinval == 0) { 1069 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) 1070 return (ENXIO); 1071 vrs->val = le32toh(reg); 1072 vrs->off += 4; 1073 byte = vrs->val & 0xff; 1074 vrs->bytesinval = 3; 1075 } else { 1076 vrs->val = vrs->val >> 8; 1077 byte = vrs->val & 0xff; 1078 vrs->bytesinval--; 1079 } 1080 1081 vrs->cksum += byte; 1082 *data = byte; 1083 return (0); 1084 } 1085 1086 static void 1087 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 1088 { 1089 struct vpd_readstate vrs; 1090 int state; 1091 int name; 1092 int remain; 1093 int i; 1094 int alloc, off; /* alloc/off for RO/W arrays */ 1095 int cksumvalid; 1096 int dflen; 1097 uint8_t byte; 1098 uint8_t byte2; 1099 1100 /* init vpd reader */ 1101 vrs.bytesinval = 0; 1102 vrs.off = 0; 1103 vrs.pcib = pcib; 1104 vrs.cfg = cfg; 1105 vrs.cksum = 0; 1106 1107 state = 0; 1108 name = remain = i = 0; /* shut up stupid gcc */ 1109 alloc = off = 0; /* shut up stupid gcc */ 1110 dflen = 0; /* shut up stupid gcc */ 1111 cksumvalid = -1; 1112 while (state >= 0) { 1113 if (vpd_nextbyte(&vrs, &byte)) { 1114 state = -2; 1115 break; 1116 } 1117 #if 0 1118 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \ 1119 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val, 1120 vrs.off, vrs.bytesinval, byte, state, remain, name, i); 1121 #endif 1122 switch (state) { 1123 case 0: /* item name */ 1124 if (byte & 0x80) { 1125 if (vpd_nextbyte(&vrs, &byte2)) { 1126 state = -2; 1127 break; 1128 } 1129 remain = byte2; 1130 if (vpd_nextbyte(&vrs, &byte2)) { 1131 state = -2; 1132 break; 1133 } 1134 remain |= byte2 << 8; 1135 name = byte & 0x7f; 1136 } else { 1137 remain = byte & 0x7; 1138 name = (byte >> 3) & 0xf; 1139 } 1140 if (vrs.off + remain - vrs.bytesinval > 0x8000) { 1141 pci_printf(cfg, 1142 "VPD data overflow, remain %#x\n", remain); 1143 state = -1; 1144 break; 1145 } 1146 switch (name) { 1147 case 0x2: /* String */ 1148 cfg->vpd.vpd_ident = malloc(remain + 1, 1149 M_DEVBUF, M_WAITOK); 1150 i = 0; 1151 state = 1; 1152 break; 1153 case 0xf: /* End */ 1154 state = -1; 1155 break; 1156 case 0x10: /* VPD-R */ 1157 alloc = 8; 1158 off = 0; 1159 cfg->vpd.vpd_ros = malloc(alloc * 1160 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF, 1161 M_WAITOK | M_ZERO); 1162 state = 2; 1163 break; 1164 case 0x11: /* VPD-W */ 1165 alloc = 8; 1166 off = 0; 1167 cfg->vpd.vpd_w = malloc(alloc * 1168 sizeof(*cfg->vpd.vpd_w), M_DEVBUF, 1169 M_WAITOK | M_ZERO); 1170 state = 5; 1171 break; 1172 default: /* Invalid data, abort */ 1173 state = -1; 1174 break; 1175 } 1176 break; 1177 1178 case 1: /* Identifier String */ 1179 cfg->vpd.vpd_ident[i++] = byte; 1180 remain--; 1181 if (remain == 0) { 1182 cfg->vpd.vpd_ident[i] = '\0'; 1183 state = 0; 1184 } 1185 break; 1186 1187 case 2: /* VPD-R Keyword Header */ 1188 if (off == alloc) { 1189 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1190 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros), 1191 M_DEVBUF, M_WAITOK | M_ZERO); 1192 } 1193 cfg->vpd.vpd_ros[off].keyword[0] = byte; 1194 if (vpd_nextbyte(&vrs, &byte2)) { 1195 state = -2; 1196 break; 1197 } 1198 cfg->vpd.vpd_ros[off].keyword[1] = byte2; 1199 if (vpd_nextbyte(&vrs, &byte2)) { 1200 state = -2; 1201 break; 1202 } 1203 cfg->vpd.vpd_ros[off].len = dflen = byte2; 1204 if (dflen == 0 && 1205 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV", 1206 2) == 0) { 1207 /* 1208 * if this happens, we can't trust the rest 1209 * of the VPD. 1210 */ 1211 pci_printf(cfg, "bad keyword length: %d\n", 1212 dflen); 1213 cksumvalid = 0; 1214 state = -1; 1215 break; 1216 } else if (dflen == 0) { 1217 cfg->vpd.vpd_ros[off].value = malloc(1 * 1218 sizeof(*cfg->vpd.vpd_ros[off].value), 1219 M_DEVBUF, M_WAITOK); 1220 cfg->vpd.vpd_ros[off].value[0] = '\x00'; 1221 } else 1222 cfg->vpd.vpd_ros[off].value = malloc( 1223 (dflen + 1) * 1224 sizeof(*cfg->vpd.vpd_ros[off].value), 1225 M_DEVBUF, M_WAITOK); 1226 remain -= 3; 1227 i = 0; 1228 /* keep in sync w/ state 3's transistions */ 1229 if (dflen == 0 && remain == 0) 1230 state = 0; 1231 else if (dflen == 0) 1232 state = 2; 1233 else 1234 state = 3; 1235 break; 1236 1237 case 3: /* VPD-R Keyword Value */ 1238 cfg->vpd.vpd_ros[off].value[i++] = byte; 1239 if (strncmp(cfg->vpd.vpd_ros[off].keyword, 1240 "RV", 2) == 0 && cksumvalid == -1) { 1241 if (vrs.cksum == 0) 1242 cksumvalid = 1; 1243 else { 1244 if (bootverbose) 1245 pci_printf(cfg, 1246 "bad VPD cksum, remain %hhu\n", 1247 vrs.cksum); 1248 cksumvalid = 0; 1249 state = -1; 1250 break; 1251 } 1252 } 1253 dflen--; 1254 remain--; 1255 /* keep in sync w/ state 2's transistions */ 1256 if (dflen == 0) 1257 cfg->vpd.vpd_ros[off++].value[i++] = '\0'; 1258 if (dflen == 0 && remain == 0) { 1259 cfg->vpd.vpd_rocnt = off; 1260 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1261 off * sizeof(*cfg->vpd.vpd_ros), 1262 M_DEVBUF, M_WAITOK | M_ZERO); 1263 state = 0; 1264 } else if (dflen == 0) 1265 state = 2; 1266 break; 1267 1268 case 4: 1269 remain--; 1270 if (remain == 0) 1271 state = 0; 1272 break; 1273 1274 case 5: /* VPD-W Keyword Header */ 1275 if (off == alloc) { 1276 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1277 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w), 1278 M_DEVBUF, M_WAITOK | M_ZERO); 1279 } 1280 cfg->vpd.vpd_w[off].keyword[0] = byte; 1281 if (vpd_nextbyte(&vrs, &byte2)) { 1282 state = -2; 1283 break; 1284 } 1285 cfg->vpd.vpd_w[off].keyword[1] = byte2; 1286 if (vpd_nextbyte(&vrs, &byte2)) { 1287 state = -2; 1288 break; 1289 } 1290 cfg->vpd.vpd_w[off].len = dflen = byte2; 1291 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval; 1292 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) * 1293 sizeof(*cfg->vpd.vpd_w[off].value), 1294 M_DEVBUF, M_WAITOK); 1295 remain -= 3; 1296 i = 0; 1297 /* keep in sync w/ state 6's transistions */ 1298 if (dflen == 0 && remain == 0) 1299 state = 0; 1300 else if (dflen == 0) 1301 state = 5; 1302 else 1303 state = 6; 1304 break; 1305 1306 case 6: /* VPD-W Keyword Value */ 1307 cfg->vpd.vpd_w[off].value[i++] = byte; 1308 dflen--; 1309 remain--; 1310 /* keep in sync w/ state 5's transistions */ 1311 if (dflen == 0) 1312 cfg->vpd.vpd_w[off++].value[i++] = '\0'; 1313 if (dflen == 0 && remain == 0) { 1314 cfg->vpd.vpd_wcnt = off; 1315 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1316 off * sizeof(*cfg->vpd.vpd_w), 1317 M_DEVBUF, M_WAITOK | M_ZERO); 1318 state = 0; 1319 } else if (dflen == 0) 1320 state = 5; 1321 break; 1322 1323 default: 1324 pci_printf(cfg, "invalid state: %d\n", state); 1325 state = -1; 1326 break; 1327 } 1328 } 1329 1330 if (cksumvalid == 0 || state < -1) { 1331 /* read-only data bad, clean up */ 1332 if (cfg->vpd.vpd_ros != NULL) { 1333 for (off = 0; cfg->vpd.vpd_ros[off].value; off++) 1334 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF); 1335 free(cfg->vpd.vpd_ros, M_DEVBUF); 1336 cfg->vpd.vpd_ros = NULL; 1337 } 1338 } 1339 if (state < -1) { 1340 /* I/O error, clean up */ 1341 pci_printf(cfg, "failed to read VPD data.\n"); 1342 if (cfg->vpd.vpd_ident != NULL) { 1343 free(cfg->vpd.vpd_ident, M_DEVBUF); 1344 cfg->vpd.vpd_ident = NULL; 1345 } 1346 if (cfg->vpd.vpd_w != NULL) { 1347 for (off = 0; cfg->vpd.vpd_w[off].value; off++) 1348 free(cfg->vpd.vpd_w[off].value, M_DEVBUF); 1349 free(cfg->vpd.vpd_w, M_DEVBUF); 1350 cfg->vpd.vpd_w = NULL; 1351 } 1352 } 1353 cfg->vpd.vpd_cached = 1; 1354 #undef REG 1355 #undef WREG 1356 } 1357 1358 int 1359 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 1360 { 1361 struct pci_devinfo *dinfo = device_get_ivars(child); 1362 pcicfgregs *cfg = &dinfo->cfg; 1363 1364 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1365 pci_read_vpd(device_get_parent(dev), cfg); 1366 1367 *identptr = cfg->vpd.vpd_ident; 1368 1369 if (*identptr == NULL) 1370 return (ENXIO); 1371 1372 return (0); 1373 } 1374 1375 int 1376 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 1377 const char **vptr) 1378 { 1379 struct pci_devinfo *dinfo = device_get_ivars(child); 1380 pcicfgregs *cfg = &dinfo->cfg; 1381 int i; 1382 1383 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1384 pci_read_vpd(device_get_parent(dev), cfg); 1385 1386 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 1387 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 1388 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { 1389 *vptr = cfg->vpd.vpd_ros[i].value; 1390 return (0); 1391 } 1392 1393 *vptr = NULL; 1394 return (ENXIO); 1395 } 1396 1397 struct pcicfg_vpd * 1398 pci_fetch_vpd_list(device_t dev) 1399 { 1400 struct pci_devinfo *dinfo = device_get_ivars(dev); 1401 pcicfgregs *cfg = &dinfo->cfg; 1402 1403 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1404 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg); 1405 return (&cfg->vpd); 1406 } 1407 1408 /* 1409 * Find the requested HyperTransport capability and return the offset 1410 * in configuration space via the pointer provided. The function 1411 * returns 0 on success and an error code otherwise. 1412 */ 1413 int 1414 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg) 1415 { 1416 int ptr, error; 1417 uint16_t val; 1418 1419 error = pci_find_cap(child, PCIY_HT, &ptr); 1420 if (error) 1421 return (error); 1422 1423 /* 1424 * Traverse the capabilities list checking each HT capability 1425 * to see if it matches the requested HT capability. 1426 */ 1427 for (;;) { 1428 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1429 if (capability == PCIM_HTCAP_SLAVE || 1430 capability == PCIM_HTCAP_HOST) 1431 val &= 0xe000; 1432 else 1433 val &= PCIM_HTCMD_CAP_MASK; 1434 if (val == capability) { 1435 if (capreg != NULL) 1436 *capreg = ptr; 1437 return (0); 1438 } 1439 1440 /* Skip to the next HT capability. */ 1441 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1442 break; 1443 } 1444 1445 return (ENOENT); 1446 } 1447 1448 /* 1449 * Find the next requested HyperTransport capability after start and return 1450 * the offset in configuration space via the pointer provided. The function 1451 * returns 0 on success and an error code otherwise. 1452 */ 1453 int 1454 pci_find_next_htcap_method(device_t dev, device_t child, int capability, 1455 int start, int *capreg) 1456 { 1457 int ptr; 1458 uint16_t val; 1459 1460 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == PCIY_HT, 1461 ("start capability is not HyperTransport capability")); 1462 ptr = start; 1463 1464 /* 1465 * Traverse the capabilities list checking each HT capability 1466 * to see if it matches the requested HT capability. 1467 */ 1468 for (;;) { 1469 /* Skip to the next HT capability. */ 1470 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1471 break; 1472 1473 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1474 if (capability == PCIM_HTCAP_SLAVE || 1475 capability == PCIM_HTCAP_HOST) 1476 val &= 0xe000; 1477 else 1478 val &= PCIM_HTCMD_CAP_MASK; 1479 if (val == capability) { 1480 if (capreg != NULL) 1481 *capreg = ptr; 1482 return (0); 1483 } 1484 } 1485 1486 return (ENOENT); 1487 } 1488 1489 /* 1490 * Find the requested capability and return the offset in 1491 * configuration space via the pointer provided. The function returns 1492 * 0 on success and an error code otherwise. 1493 */ 1494 int 1495 pci_find_cap_method(device_t dev, device_t child, int capability, 1496 int *capreg) 1497 { 1498 struct pci_devinfo *dinfo = device_get_ivars(child); 1499 pcicfgregs *cfg = &dinfo->cfg; 1500 uint32_t status; 1501 uint8_t ptr; 1502 1503 /* 1504 * Check the CAP_LIST bit of the PCI status register first. 1505 */ 1506 status = pci_read_config(child, PCIR_STATUS, 2); 1507 if (!(status & PCIM_STATUS_CAPPRESENT)) 1508 return (ENXIO); 1509 1510 /* 1511 * Determine the start pointer of the capabilities list. 1512 */ 1513 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1514 case PCIM_HDRTYPE_NORMAL: 1515 case PCIM_HDRTYPE_BRIDGE: 1516 ptr = PCIR_CAP_PTR; 1517 break; 1518 case PCIM_HDRTYPE_CARDBUS: 1519 ptr = PCIR_CAP_PTR_2; 1520 break; 1521 default: 1522 /* XXX: panic? */ 1523 return (ENXIO); /* no extended capabilities support */ 1524 } 1525 ptr = pci_read_config(child, ptr, 1); 1526 1527 /* 1528 * Traverse the capabilities list. 1529 */ 1530 while (ptr != 0) { 1531 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1532 if (capreg != NULL) 1533 *capreg = ptr; 1534 return (0); 1535 } 1536 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1537 } 1538 1539 return (ENOENT); 1540 } 1541 1542 /* 1543 * Find the next requested capability after start and return the offset in 1544 * configuration space via the pointer provided. The function returns 1545 * 0 on success and an error code otherwise. 1546 */ 1547 int 1548 pci_find_next_cap_method(device_t dev, device_t child, int capability, 1549 int start, int *capreg) 1550 { 1551 uint8_t ptr; 1552 1553 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == capability, 1554 ("start capability is not expected capability")); 1555 1556 ptr = pci_read_config(child, start + PCICAP_NEXTPTR, 1); 1557 while (ptr != 0) { 1558 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1559 if (capreg != NULL) 1560 *capreg = ptr; 1561 return (0); 1562 } 1563 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1564 } 1565 1566 return (ENOENT); 1567 } 1568 1569 /* 1570 * Find the requested extended capability and return the offset in 1571 * configuration space via the pointer provided. The function returns 1572 * 0 on success and an error code otherwise. 1573 */ 1574 int 1575 pci_find_extcap_method(device_t dev, device_t child, int capability, 1576 int *capreg) 1577 { 1578 struct pci_devinfo *dinfo = device_get_ivars(child); 1579 pcicfgregs *cfg = &dinfo->cfg; 1580 uint32_t ecap; 1581 uint16_t ptr; 1582 1583 /* Only supported for PCI-express devices. */ 1584 if (cfg->pcie.pcie_location == 0) 1585 return (ENXIO); 1586 1587 ptr = PCIR_EXTCAP; 1588 ecap = pci_read_config(child, ptr, 4); 1589 if (ecap == 0xffffffff || ecap == 0) 1590 return (ENOENT); 1591 for (;;) { 1592 if (PCI_EXTCAP_ID(ecap) == capability) { 1593 if (capreg != NULL) 1594 *capreg = ptr; 1595 return (0); 1596 } 1597 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1598 if (ptr == 0) 1599 break; 1600 ecap = pci_read_config(child, ptr, 4); 1601 } 1602 1603 return (ENOENT); 1604 } 1605 1606 /* 1607 * Find the next requested extended capability after start and return the 1608 * offset in configuration space via the pointer provided. The function 1609 * returns 0 on success and an error code otherwise. 1610 */ 1611 int 1612 pci_find_next_extcap_method(device_t dev, device_t child, int capability, 1613 int start, int *capreg) 1614 { 1615 struct pci_devinfo *dinfo = device_get_ivars(child); 1616 pcicfgregs *cfg = &dinfo->cfg; 1617 uint32_t ecap; 1618 uint16_t ptr; 1619 1620 /* Only supported for PCI-express devices. */ 1621 if (cfg->pcie.pcie_location == 0) 1622 return (ENXIO); 1623 1624 ecap = pci_read_config(child, start, 4); 1625 KASSERT(PCI_EXTCAP_ID(ecap) == capability, 1626 ("start extended capability is not expected capability")); 1627 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1628 while (ptr != 0) { 1629 ecap = pci_read_config(child, ptr, 4); 1630 if (PCI_EXTCAP_ID(ecap) == capability) { 1631 if (capreg != NULL) 1632 *capreg = ptr; 1633 return (0); 1634 } 1635 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1636 } 1637 1638 return (ENOENT); 1639 } 1640 1641 /* 1642 * Support for MSI-X message interrupts. 1643 */ 1644 static void 1645 pci_write_msix_entry(device_t dev, u_int index, uint64_t address, uint32_t data) 1646 { 1647 struct pci_devinfo *dinfo = device_get_ivars(dev); 1648 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1649 uint32_t offset; 1650 1651 KASSERT(msix->msix_table_len > index, ("bogus index")); 1652 offset = msix->msix_table_offset + index * 16; 1653 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); 1654 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); 1655 bus_write_4(msix->msix_table_res, offset + 8, data); 1656 } 1657 1658 void 1659 pci_enable_msix_method(device_t dev, device_t child, u_int index, 1660 uint64_t address, uint32_t data) 1661 { 1662 1663 if (pci_msix_rewrite_table) { 1664 struct pci_devinfo *dinfo = device_get_ivars(child); 1665 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1666 1667 /* 1668 * Some VM hosts require MSIX to be disabled in the 1669 * control register before updating the MSIX table 1670 * entries are allowed. It is not enough to only 1671 * disable MSIX while updating a single entry. MSIX 1672 * must be disabled while updating all entries in the 1673 * table. 1674 */ 1675 pci_write_config(child, 1676 msix->msix_location + PCIR_MSIX_CTRL, 1677 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2); 1678 pci_resume_msix(child); 1679 } else 1680 pci_write_msix_entry(child, index, address, data); 1681 1682 /* Enable MSI -> HT mapping. */ 1683 pci_ht_map_msi(child, address); 1684 } 1685 1686 void 1687 pci_mask_msix(device_t dev, u_int index) 1688 { 1689 struct pci_devinfo *dinfo = device_get_ivars(dev); 1690 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1691 uint32_t offset, val; 1692 1693 KASSERT(msix->msix_msgnum > index, ("bogus index")); 1694 offset = msix->msix_table_offset + index * 16 + 12; 1695 val = bus_read_4(msix->msix_table_res, offset); 1696 val |= PCIM_MSIX_VCTRL_MASK; 1697 1698 /* 1699 * Some devices (e.g. Samsung PM961) do not support reads of this 1700 * register, so always write the new value. 1701 */ 1702 bus_write_4(msix->msix_table_res, offset, val); 1703 } 1704 1705 void 1706 pci_unmask_msix(device_t dev, u_int index) 1707 { 1708 struct pci_devinfo *dinfo = device_get_ivars(dev); 1709 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1710 uint32_t offset, val; 1711 1712 KASSERT(msix->msix_table_len > index, ("bogus index")); 1713 offset = msix->msix_table_offset + index * 16 + 12; 1714 val = bus_read_4(msix->msix_table_res, offset); 1715 val &= ~PCIM_MSIX_VCTRL_MASK; 1716 1717 /* 1718 * Some devices (e.g. Samsung PM961) do not support reads of this 1719 * register, so always write the new value. 1720 */ 1721 bus_write_4(msix->msix_table_res, offset, val); 1722 } 1723 1724 int 1725 pci_pending_msix(device_t dev, u_int index) 1726 { 1727 struct pci_devinfo *dinfo = device_get_ivars(dev); 1728 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1729 uint32_t offset, bit; 1730 1731 KASSERT(msix->msix_table_len > index, ("bogus index")); 1732 offset = msix->msix_pba_offset + (index / 32) * 4; 1733 bit = 1 << index % 32; 1734 return (bus_read_4(msix->msix_pba_res, offset) & bit); 1735 } 1736 1737 /* 1738 * Restore MSI-X registers and table during resume. If MSI-X is 1739 * enabled then walk the virtual table to restore the actual MSI-X 1740 * table. 1741 */ 1742 static void 1743 pci_resume_msix(device_t dev) 1744 { 1745 struct pci_devinfo *dinfo = device_get_ivars(dev); 1746 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1747 struct msix_table_entry *mte; 1748 struct msix_vector *mv; 1749 int i; 1750 1751 if (msix->msix_alloc > 0) { 1752 /* First, mask all vectors. */ 1753 for (i = 0; i < msix->msix_msgnum; i++) 1754 pci_mask_msix(dev, i); 1755 1756 /* Second, program any messages with at least one handler. */ 1757 for (i = 0; i < msix->msix_table_len; i++) { 1758 mte = &msix->msix_table[i]; 1759 if (mte->mte_vector == 0 || mte->mte_handlers == 0) 1760 continue; 1761 mv = &msix->msix_vectors[mte->mte_vector - 1]; 1762 pci_write_msix_entry(dev, i, mv->mv_address, 1763 mv->mv_data); 1764 pci_unmask_msix(dev, i); 1765 } 1766 } 1767 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, 1768 msix->msix_ctrl, 2); 1769 } 1770 1771 /* 1772 * Attempt to allocate *count MSI-X messages. The actual number allocated is 1773 * returned in *count. After this function returns, each message will be 1774 * available to the driver as SYS_RES_IRQ resources starting at rid 1. 1775 */ 1776 int 1777 pci_alloc_msix_method(device_t dev, device_t child, int *count) 1778 { 1779 struct pci_devinfo *dinfo = device_get_ivars(child); 1780 pcicfgregs *cfg = &dinfo->cfg; 1781 struct resource_list_entry *rle; 1782 int actual, error, i, irq, max; 1783 1784 /* Don't let count == 0 get us into trouble. */ 1785 if (*count == 0) 1786 return (EINVAL); 1787 1788 /* If rid 0 is allocated, then fail. */ 1789 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1790 if (rle != NULL && rle->res != NULL) 1791 return (ENXIO); 1792 1793 /* Already have allocated messages? */ 1794 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1795 return (ENXIO); 1796 1797 /* If MSI-X is blacklisted for this system, fail. */ 1798 if (pci_msix_blacklisted()) 1799 return (ENXIO); 1800 1801 /* MSI-X capability present? */ 1802 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1803 return (ENODEV); 1804 1805 /* Make sure the appropriate BARs are mapped. */ 1806 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1807 cfg->msix.msix_table_bar); 1808 if (rle == NULL || rle->res == NULL || 1809 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1810 return (ENXIO); 1811 cfg->msix.msix_table_res = rle->res; 1812 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1813 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1814 cfg->msix.msix_pba_bar); 1815 if (rle == NULL || rle->res == NULL || 1816 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1817 return (ENXIO); 1818 } 1819 cfg->msix.msix_pba_res = rle->res; 1820 1821 if (bootverbose) 1822 device_printf(child, 1823 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1824 *count, cfg->msix.msix_msgnum); 1825 max = min(*count, cfg->msix.msix_msgnum); 1826 for (i = 0; i < max; i++) { 1827 /* Allocate a message. */ 1828 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq); 1829 if (error) { 1830 if (i == 0) 1831 return (error); 1832 break; 1833 } 1834 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1835 irq, 1); 1836 } 1837 actual = i; 1838 1839 if (bootverbose) { 1840 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1841 if (actual == 1) 1842 device_printf(child, "using IRQ %ju for MSI-X\n", 1843 rle->start); 1844 else { 1845 int run; 1846 1847 /* 1848 * Be fancy and try to print contiguous runs of 1849 * IRQ values as ranges. 'irq' is the previous IRQ. 1850 * 'run' is true if we are in a range. 1851 */ 1852 device_printf(child, "using IRQs %ju", rle->start); 1853 irq = rle->start; 1854 run = 0; 1855 for (i = 1; i < actual; i++) { 1856 rle = resource_list_find(&dinfo->resources, 1857 SYS_RES_IRQ, i + 1); 1858 1859 /* Still in a run? */ 1860 if (rle->start == irq + 1) { 1861 run = 1; 1862 irq++; 1863 continue; 1864 } 1865 1866 /* Finish previous range. */ 1867 if (run) { 1868 printf("-%d", irq); 1869 run = 0; 1870 } 1871 1872 /* Start new range. */ 1873 printf(",%ju", rle->start); 1874 irq = rle->start; 1875 } 1876 1877 /* Unfinished range? */ 1878 if (run) 1879 printf("-%d", irq); 1880 printf(" for MSI-X\n"); 1881 } 1882 } 1883 1884 /* Mask all vectors. */ 1885 for (i = 0; i < cfg->msix.msix_msgnum; i++) 1886 pci_mask_msix(child, i); 1887 1888 /* Allocate and initialize vector data and virtual table. */ 1889 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual, 1890 M_DEVBUF, M_WAITOK | M_ZERO); 1891 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual, 1892 M_DEVBUF, M_WAITOK | M_ZERO); 1893 for (i = 0; i < actual; i++) { 1894 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1895 cfg->msix.msix_vectors[i].mv_irq = rle->start; 1896 cfg->msix.msix_table[i].mte_vector = i + 1; 1897 } 1898 1899 /* Update control register to enable MSI-X. */ 1900 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1901 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1902 cfg->msix.msix_ctrl, 2); 1903 1904 /* Update counts of alloc'd messages. */ 1905 cfg->msix.msix_alloc = actual; 1906 cfg->msix.msix_table_len = actual; 1907 *count = actual; 1908 return (0); 1909 } 1910 1911 /* 1912 * By default, pci_alloc_msix() will assign the allocated IRQ 1913 * resources consecutively to the first N messages in the MSI-X table. 1914 * However, device drivers may want to use different layouts if they 1915 * either receive fewer messages than they asked for, or they wish to 1916 * populate the MSI-X table sparsely. This method allows the driver 1917 * to specify what layout it wants. It must be called after a 1918 * successful pci_alloc_msix() but before any of the associated 1919 * SYS_RES_IRQ resources are allocated via bus_alloc_resource(). 1920 * 1921 * The 'vectors' array contains 'count' message vectors. The array 1922 * maps directly to the MSI-X table in that index 0 in the array 1923 * specifies the vector for the first message in the MSI-X table, etc. 1924 * The vector value in each array index can either be 0 to indicate 1925 * that no vector should be assigned to a message slot, or it can be a 1926 * number from 1 to N (where N is the count returned from a 1927 * succcessful call to pci_alloc_msix()) to indicate which message 1928 * vector (IRQ) to be used for the corresponding message. 1929 * 1930 * On successful return, each message with a non-zero vector will have 1931 * an associated SYS_RES_IRQ whose rid is equal to the array index + 1932 * 1. Additionally, if any of the IRQs allocated via the previous 1933 * call to pci_alloc_msix() are not used in the mapping, those IRQs 1934 * will be freed back to the system automatically. 1935 * 1936 * For example, suppose a driver has a MSI-X table with 6 messages and 1937 * asks for 6 messages, but pci_alloc_msix() only returns a count of 1938 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and 1939 * C. After the call to pci_alloc_msix(), the device will be setup to 1940 * have an MSI-X table of ABC--- (where - means no vector assigned). 1941 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 }, 1942 * then the MSI-X table will look like A-AB-B, and the 'C' vector will 1943 * be freed back to the system. This device will also have valid 1944 * SYS_RES_IRQ rids of 1, 3, 4, and 6. 1945 * 1946 * In any case, the SYS_RES_IRQ rid X will always map to the message 1947 * at MSI-X table index X - 1 and will only be valid if a vector is 1948 * assigned to that table entry. 1949 */ 1950 int 1951 pci_remap_msix_method(device_t dev, device_t child, int count, 1952 const u_int *vectors) 1953 { 1954 struct pci_devinfo *dinfo = device_get_ivars(child); 1955 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1956 struct resource_list_entry *rle; 1957 int i, irq, j, *used; 1958 1959 /* 1960 * Have to have at least one message in the table but the 1961 * table can't be bigger than the actual MSI-X table in the 1962 * device. 1963 */ 1964 if (count == 0 || count > msix->msix_msgnum) 1965 return (EINVAL); 1966 1967 /* Sanity check the vectors. */ 1968 for (i = 0; i < count; i++) 1969 if (vectors[i] > msix->msix_alloc) 1970 return (EINVAL); 1971 1972 /* 1973 * Make sure there aren't any holes in the vectors to be used. 1974 * It's a big pain to support it, and it doesn't really make 1975 * sense anyway. Also, at least one vector must be used. 1976 */ 1977 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK | 1978 M_ZERO); 1979 for (i = 0; i < count; i++) 1980 if (vectors[i] != 0) 1981 used[vectors[i] - 1] = 1; 1982 for (i = 0; i < msix->msix_alloc - 1; i++) 1983 if (used[i] == 0 && used[i + 1] == 1) { 1984 free(used, M_DEVBUF); 1985 return (EINVAL); 1986 } 1987 if (used[0] != 1) { 1988 free(used, M_DEVBUF); 1989 return (EINVAL); 1990 } 1991 1992 /* Make sure none of the resources are allocated. */ 1993 for (i = 0; i < msix->msix_table_len; i++) { 1994 if (msix->msix_table[i].mte_vector == 0) 1995 continue; 1996 if (msix->msix_table[i].mte_handlers > 0) { 1997 free(used, M_DEVBUF); 1998 return (EBUSY); 1999 } 2000 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2001 KASSERT(rle != NULL, ("missing resource")); 2002 if (rle->res != NULL) { 2003 free(used, M_DEVBUF); 2004 return (EBUSY); 2005 } 2006 } 2007 2008 /* Free the existing resource list entries. */ 2009 for (i = 0; i < msix->msix_table_len; i++) { 2010 if (msix->msix_table[i].mte_vector == 0) 2011 continue; 2012 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2013 } 2014 2015 /* 2016 * Build the new virtual table keeping track of which vectors are 2017 * used. 2018 */ 2019 free(msix->msix_table, M_DEVBUF); 2020 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count, 2021 M_DEVBUF, M_WAITOK | M_ZERO); 2022 for (i = 0; i < count; i++) 2023 msix->msix_table[i].mte_vector = vectors[i]; 2024 msix->msix_table_len = count; 2025 2026 /* Free any unused IRQs and resize the vectors array if necessary. */ 2027 j = msix->msix_alloc - 1; 2028 if (used[j] == 0) { 2029 struct msix_vector *vec; 2030 2031 while (used[j] == 0) { 2032 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2033 msix->msix_vectors[j].mv_irq); 2034 j--; 2035 } 2036 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF, 2037 M_WAITOK); 2038 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * 2039 (j + 1)); 2040 free(msix->msix_vectors, M_DEVBUF); 2041 msix->msix_vectors = vec; 2042 msix->msix_alloc = j + 1; 2043 } 2044 free(used, M_DEVBUF); 2045 2046 /* Map the IRQs onto the rids. */ 2047 for (i = 0; i < count; i++) { 2048 if (vectors[i] == 0) 2049 continue; 2050 irq = msix->msix_vectors[vectors[i] - 1].mv_irq; 2051 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 2052 irq, 1); 2053 } 2054 2055 if (bootverbose) { 2056 device_printf(child, "Remapped MSI-X IRQs as: "); 2057 for (i = 0; i < count; i++) { 2058 if (i != 0) 2059 printf(", "); 2060 if (vectors[i] == 0) 2061 printf("---"); 2062 else 2063 printf("%d", 2064 msix->msix_vectors[vectors[i] - 1].mv_irq); 2065 } 2066 printf("\n"); 2067 } 2068 2069 return (0); 2070 } 2071 2072 static int 2073 pci_release_msix(device_t dev, device_t child) 2074 { 2075 struct pci_devinfo *dinfo = device_get_ivars(child); 2076 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2077 struct resource_list_entry *rle; 2078 int i; 2079 2080 /* Do we have any messages to release? */ 2081 if (msix->msix_alloc == 0) 2082 return (ENODEV); 2083 2084 /* Make sure none of the resources are allocated. */ 2085 for (i = 0; i < msix->msix_table_len; i++) { 2086 if (msix->msix_table[i].mte_vector == 0) 2087 continue; 2088 if (msix->msix_table[i].mte_handlers > 0) 2089 return (EBUSY); 2090 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2091 KASSERT(rle != NULL, ("missing resource")); 2092 if (rle->res != NULL) 2093 return (EBUSY); 2094 } 2095 2096 /* Update control register to disable MSI-X. */ 2097 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 2098 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, 2099 msix->msix_ctrl, 2); 2100 2101 /* Free the resource list entries. */ 2102 for (i = 0; i < msix->msix_table_len; i++) { 2103 if (msix->msix_table[i].mte_vector == 0) 2104 continue; 2105 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2106 } 2107 free(msix->msix_table, M_DEVBUF); 2108 msix->msix_table_len = 0; 2109 2110 /* Release the IRQs. */ 2111 for (i = 0; i < msix->msix_alloc; i++) 2112 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2113 msix->msix_vectors[i].mv_irq); 2114 free(msix->msix_vectors, M_DEVBUF); 2115 msix->msix_alloc = 0; 2116 return (0); 2117 } 2118 2119 /* 2120 * Return the max supported MSI-X messages this device supports. 2121 * Basically, assuming the MD code can alloc messages, this function 2122 * should return the maximum value that pci_alloc_msix() can return. 2123 * Thus, it is subject to the tunables, etc. 2124 */ 2125 int 2126 pci_msix_count_method(device_t dev, device_t child) 2127 { 2128 struct pci_devinfo *dinfo = device_get_ivars(child); 2129 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2130 2131 if (pci_do_msix && msix->msix_location != 0) 2132 return (msix->msix_msgnum); 2133 return (0); 2134 } 2135 2136 int 2137 pci_msix_pba_bar_method(device_t dev, device_t child) 2138 { 2139 struct pci_devinfo *dinfo = device_get_ivars(child); 2140 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2141 2142 if (pci_do_msix && msix->msix_location != 0) 2143 return (msix->msix_pba_bar); 2144 return (-1); 2145 } 2146 2147 int 2148 pci_msix_table_bar_method(device_t dev, device_t child) 2149 { 2150 struct pci_devinfo *dinfo = device_get_ivars(child); 2151 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2152 2153 if (pci_do_msix && msix->msix_location != 0) 2154 return (msix->msix_table_bar); 2155 return (-1); 2156 } 2157 2158 /* 2159 * HyperTransport MSI mapping control 2160 */ 2161 void 2162 pci_ht_map_msi(device_t dev, uint64_t addr) 2163 { 2164 struct pci_devinfo *dinfo = device_get_ivars(dev); 2165 struct pcicfg_ht *ht = &dinfo->cfg.ht; 2166 2167 if (!ht->ht_msimap) 2168 return; 2169 2170 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && 2171 ht->ht_msiaddr >> 20 == addr >> 20) { 2172 /* Enable MSI -> HT mapping. */ 2173 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 2174 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2175 ht->ht_msictrl, 2); 2176 } 2177 2178 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { 2179 /* Disable MSI -> HT mapping. */ 2180 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; 2181 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2182 ht->ht_msictrl, 2); 2183 } 2184 } 2185 2186 int 2187 pci_get_relaxed_ordering_enabled(device_t dev) 2188 { 2189 struct pci_devinfo *dinfo = device_get_ivars(dev); 2190 int cap; 2191 uint16_t val; 2192 2193 cap = dinfo->cfg.pcie.pcie_location; 2194 if (cap == 0) 2195 return (0); 2196 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2197 val &= PCIEM_CTL_RELAXED_ORD_ENABLE; 2198 return (val != 0); 2199 } 2200 2201 int 2202 pci_get_max_payload(device_t dev) 2203 { 2204 struct pci_devinfo *dinfo = device_get_ivars(dev); 2205 int cap; 2206 uint16_t val; 2207 2208 cap = dinfo->cfg.pcie.pcie_location; 2209 if (cap == 0) 2210 return (0); 2211 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2212 val &= PCIEM_CTL_MAX_PAYLOAD; 2213 val >>= 5; 2214 return (1 << (val + 7)); 2215 } 2216 2217 int 2218 pci_get_max_read_req(device_t dev) 2219 { 2220 struct pci_devinfo *dinfo = device_get_ivars(dev); 2221 int cap; 2222 uint16_t val; 2223 2224 cap = dinfo->cfg.pcie.pcie_location; 2225 if (cap == 0) 2226 return (0); 2227 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2228 val &= PCIEM_CTL_MAX_READ_REQUEST; 2229 val >>= 12; 2230 return (1 << (val + 7)); 2231 } 2232 2233 int 2234 pci_set_max_read_req(device_t dev, int size) 2235 { 2236 struct pci_devinfo *dinfo = device_get_ivars(dev); 2237 int cap; 2238 uint16_t val; 2239 2240 cap = dinfo->cfg.pcie.pcie_location; 2241 if (cap == 0) 2242 return (0); 2243 if (size < 128) 2244 size = 128; 2245 if (size > 4096) 2246 size = 4096; 2247 size = (1 << (fls(size) - 1)); 2248 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2249 val &= ~PCIEM_CTL_MAX_READ_REQUEST; 2250 val |= (fls(size) - 8) << 12; 2251 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2); 2252 return (size); 2253 } 2254 2255 uint32_t 2256 pcie_read_config(device_t dev, int reg, int width) 2257 { 2258 struct pci_devinfo *dinfo = device_get_ivars(dev); 2259 int cap; 2260 2261 cap = dinfo->cfg.pcie.pcie_location; 2262 if (cap == 0) { 2263 if (width == 2) 2264 return (0xffff); 2265 return (0xffffffff); 2266 } 2267 2268 return (pci_read_config(dev, cap + reg, width)); 2269 } 2270 2271 void 2272 pcie_write_config(device_t dev, int reg, uint32_t value, int width) 2273 { 2274 struct pci_devinfo *dinfo = device_get_ivars(dev); 2275 int cap; 2276 2277 cap = dinfo->cfg.pcie.pcie_location; 2278 if (cap == 0) 2279 return; 2280 pci_write_config(dev, cap + reg, value, width); 2281 } 2282 2283 /* 2284 * Adjusts a PCI-e capability register by clearing the bits in mask 2285 * and setting the bits in (value & mask). Bits not set in mask are 2286 * not adjusted. 2287 * 2288 * Returns the old value on success or all ones on failure. 2289 */ 2290 uint32_t 2291 pcie_adjust_config(device_t dev, int reg, uint32_t mask, uint32_t value, 2292 int width) 2293 { 2294 struct pci_devinfo *dinfo = device_get_ivars(dev); 2295 uint32_t old, new; 2296 int cap; 2297 2298 cap = dinfo->cfg.pcie.pcie_location; 2299 if (cap == 0) { 2300 if (width == 2) 2301 return (0xffff); 2302 return (0xffffffff); 2303 } 2304 2305 old = pci_read_config(dev, cap + reg, width); 2306 new = old & ~mask; 2307 new |= (value & mask); 2308 pci_write_config(dev, cap + reg, new, width); 2309 return (old); 2310 } 2311 2312 /* 2313 * Support for MSI message signalled interrupts. 2314 */ 2315 void 2316 pci_enable_msi_method(device_t dev, device_t child, uint64_t address, 2317 uint16_t data) 2318 { 2319 struct pci_devinfo *dinfo = device_get_ivars(child); 2320 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2321 2322 /* Write data and address values. */ 2323 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, 2324 address & 0xffffffff, 4); 2325 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2326 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, 2327 address >> 32, 4); 2328 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, 2329 data, 2); 2330 } else 2331 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, 2332 2); 2333 2334 /* Enable MSI in the control register. */ 2335 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 2336 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2337 msi->msi_ctrl, 2); 2338 2339 /* Enable MSI -> HT mapping. */ 2340 pci_ht_map_msi(child, address); 2341 } 2342 2343 void 2344 pci_disable_msi_method(device_t dev, device_t child) 2345 { 2346 struct pci_devinfo *dinfo = device_get_ivars(child); 2347 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2348 2349 /* Disable MSI -> HT mapping. */ 2350 pci_ht_map_msi(child, 0); 2351 2352 /* Disable MSI in the control register. */ 2353 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; 2354 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2355 msi->msi_ctrl, 2); 2356 } 2357 2358 /* 2359 * Restore MSI registers during resume. If MSI is enabled then 2360 * restore the data and address registers in addition to the control 2361 * register. 2362 */ 2363 static void 2364 pci_resume_msi(device_t dev) 2365 { 2366 struct pci_devinfo *dinfo = device_get_ivars(dev); 2367 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2368 uint64_t address; 2369 uint16_t data; 2370 2371 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 2372 address = msi->msi_addr; 2373 data = msi->msi_data; 2374 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 2375 address & 0xffffffff, 4); 2376 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2377 pci_write_config(dev, msi->msi_location + 2378 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 2379 pci_write_config(dev, msi->msi_location + 2380 PCIR_MSI_DATA_64BIT, data, 2); 2381 } else 2382 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, 2383 data, 2); 2384 } 2385 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 2386 2); 2387 } 2388 2389 static int 2390 pci_remap_intr_method(device_t bus, device_t dev, u_int irq) 2391 { 2392 struct pci_devinfo *dinfo = device_get_ivars(dev); 2393 pcicfgregs *cfg = &dinfo->cfg; 2394 struct resource_list_entry *rle; 2395 struct msix_table_entry *mte; 2396 struct msix_vector *mv; 2397 uint64_t addr; 2398 uint32_t data; 2399 int error, i, j; 2400 2401 /* 2402 * Handle MSI first. We try to find this IRQ among our list 2403 * of MSI IRQs. If we find it, we request updated address and 2404 * data registers and apply the results. 2405 */ 2406 if (cfg->msi.msi_alloc > 0) { 2407 /* If we don't have any active handlers, nothing to do. */ 2408 if (cfg->msi.msi_handlers == 0) 2409 return (0); 2410 for (i = 0; i < cfg->msi.msi_alloc; i++) { 2411 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 2412 i + 1); 2413 if (rle->start == irq) { 2414 error = PCIB_MAP_MSI(device_get_parent(bus), 2415 dev, irq, &addr, &data); 2416 if (error) 2417 return (error); 2418 pci_disable_msi(dev); 2419 dinfo->cfg.msi.msi_addr = addr; 2420 dinfo->cfg.msi.msi_data = data; 2421 pci_enable_msi(dev, addr, data); 2422 return (0); 2423 } 2424 } 2425 return (ENOENT); 2426 } 2427 2428 /* 2429 * For MSI-X, we check to see if we have this IRQ. If we do, 2430 * we request the updated mapping info. If that works, we go 2431 * through all the slots that use this IRQ and update them. 2432 */ 2433 if (cfg->msix.msix_alloc > 0) { 2434 for (i = 0; i < cfg->msix.msix_alloc; i++) { 2435 mv = &cfg->msix.msix_vectors[i]; 2436 if (mv->mv_irq == irq) { 2437 error = PCIB_MAP_MSI(device_get_parent(bus), 2438 dev, irq, &addr, &data); 2439 if (error) 2440 return (error); 2441 mv->mv_address = addr; 2442 mv->mv_data = data; 2443 for (j = 0; j < cfg->msix.msix_table_len; j++) { 2444 mte = &cfg->msix.msix_table[j]; 2445 if (mte->mte_vector != i + 1) 2446 continue; 2447 if (mte->mte_handlers == 0) 2448 continue; 2449 pci_mask_msix(dev, j); 2450 pci_enable_msix(dev, j, addr, data); 2451 pci_unmask_msix(dev, j); 2452 } 2453 } 2454 } 2455 return (ENOENT); 2456 } 2457 2458 return (ENOENT); 2459 } 2460 2461 /* 2462 * Returns true if the specified device is blacklisted because MSI 2463 * doesn't work. 2464 */ 2465 int 2466 pci_msi_device_blacklisted(device_t dev) 2467 { 2468 2469 if (!pci_honor_msi_blacklist) 2470 return (0); 2471 2472 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI)); 2473 } 2474 2475 /* 2476 * Determine if MSI is blacklisted globally on this system. Currently, 2477 * we just check for blacklisted chipsets as represented by the 2478 * host-PCI bridge at device 0:0:0. In the future, it may become 2479 * necessary to check other system attributes, such as the kenv values 2480 * that give the motherboard manufacturer and model number. 2481 */ 2482 static int 2483 pci_msi_blacklisted(void) 2484 { 2485 device_t dev; 2486 2487 if (!pci_honor_msi_blacklist) 2488 return (0); 2489 2490 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ 2491 if (!(pcie_chipset || pcix_chipset)) { 2492 if (vm_guest != VM_GUEST_NO) { 2493 /* 2494 * Whitelist older chipsets in virtual 2495 * machines known to support MSI. 2496 */ 2497 dev = pci_find_bsf(0, 0, 0); 2498 if (dev != NULL) 2499 return (!pci_has_quirk(pci_get_devid(dev), 2500 PCI_QUIRK_ENABLE_MSI_VM)); 2501 } 2502 return (1); 2503 } 2504 2505 dev = pci_find_bsf(0, 0, 0); 2506 if (dev != NULL) 2507 return (pci_msi_device_blacklisted(dev)); 2508 return (0); 2509 } 2510 2511 /* 2512 * Returns true if the specified device is blacklisted because MSI-X 2513 * doesn't work. Note that this assumes that if MSI doesn't work, 2514 * MSI-X doesn't either. 2515 */ 2516 int 2517 pci_msix_device_blacklisted(device_t dev) 2518 { 2519 2520 if (!pci_honor_msi_blacklist) 2521 return (0); 2522 2523 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX)) 2524 return (1); 2525 2526 return (pci_msi_device_blacklisted(dev)); 2527 } 2528 2529 /* 2530 * Determine if MSI-X is blacklisted globally on this system. If MSI 2531 * is blacklisted, assume that MSI-X is as well. Check for additional 2532 * chipsets where MSI works but MSI-X does not. 2533 */ 2534 static int 2535 pci_msix_blacklisted(void) 2536 { 2537 device_t dev; 2538 2539 if (!pci_honor_msi_blacklist) 2540 return (0); 2541 2542 dev = pci_find_bsf(0, 0, 0); 2543 if (dev != NULL && pci_has_quirk(pci_get_devid(dev), 2544 PCI_QUIRK_DISABLE_MSIX)) 2545 return (1); 2546 2547 return (pci_msi_blacklisted()); 2548 } 2549 2550 /* 2551 * Attempt to allocate *count MSI messages. The actual number allocated is 2552 * returned in *count. After this function returns, each message will be 2553 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 2554 */ 2555 int 2556 pci_alloc_msi_method(device_t dev, device_t child, int *count) 2557 { 2558 struct pci_devinfo *dinfo = device_get_ivars(child); 2559 pcicfgregs *cfg = &dinfo->cfg; 2560 struct resource_list_entry *rle; 2561 int actual, error, i, irqs[32]; 2562 uint16_t ctrl; 2563 2564 /* Don't let count == 0 get us into trouble. */ 2565 if (*count == 0) 2566 return (EINVAL); 2567 2568 /* If rid 0 is allocated, then fail. */ 2569 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 2570 if (rle != NULL && rle->res != NULL) 2571 return (ENXIO); 2572 2573 /* Already have allocated messages? */ 2574 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 2575 return (ENXIO); 2576 2577 /* If MSI is blacklisted for this system, fail. */ 2578 if (pci_msi_blacklisted()) 2579 return (ENXIO); 2580 2581 /* MSI capability present? */ 2582 if (cfg->msi.msi_location == 0 || !pci_do_msi) 2583 return (ENODEV); 2584 2585 if (bootverbose) 2586 device_printf(child, 2587 "attempting to allocate %d MSI vectors (%d supported)\n", 2588 *count, cfg->msi.msi_msgnum); 2589 2590 /* Don't ask for more than the device supports. */ 2591 actual = min(*count, cfg->msi.msi_msgnum); 2592 2593 /* Don't ask for more than 32 messages. */ 2594 actual = min(actual, 32); 2595 2596 /* MSI requires power of 2 number of messages. */ 2597 if (!powerof2(actual)) 2598 return (EINVAL); 2599 2600 for (;;) { 2601 /* Try to allocate N messages. */ 2602 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 2603 actual, irqs); 2604 if (error == 0) 2605 break; 2606 if (actual == 1) 2607 return (error); 2608 2609 /* Try N / 2. */ 2610 actual >>= 1; 2611 } 2612 2613 /* 2614 * We now have N actual messages mapped onto SYS_RES_IRQ 2615 * resources in the irqs[] array, so add new resources 2616 * starting at rid 1. 2617 */ 2618 for (i = 0; i < actual; i++) 2619 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 2620 irqs[i], irqs[i], 1); 2621 2622 if (bootverbose) { 2623 if (actual == 1) 2624 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 2625 else { 2626 int run; 2627 2628 /* 2629 * Be fancy and try to print contiguous runs 2630 * of IRQ values as ranges. 'run' is true if 2631 * we are in a range. 2632 */ 2633 device_printf(child, "using IRQs %d", irqs[0]); 2634 run = 0; 2635 for (i = 1; i < actual; i++) { 2636 /* Still in a run? */ 2637 if (irqs[i] == irqs[i - 1] + 1) { 2638 run = 1; 2639 continue; 2640 } 2641 2642 /* Finish previous range. */ 2643 if (run) { 2644 printf("-%d", irqs[i - 1]); 2645 run = 0; 2646 } 2647 2648 /* Start new range. */ 2649 printf(",%d", irqs[i]); 2650 } 2651 2652 /* Unfinished range? */ 2653 if (run) 2654 printf("-%d", irqs[actual - 1]); 2655 printf(" for MSI\n"); 2656 } 2657 } 2658 2659 /* Update control register with actual count. */ 2660 ctrl = cfg->msi.msi_ctrl; 2661 ctrl &= ~PCIM_MSICTRL_MME_MASK; 2662 ctrl |= (ffs(actual) - 1) << 4; 2663 cfg->msi.msi_ctrl = ctrl; 2664 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 2665 2666 /* Update counts of alloc'd messages. */ 2667 cfg->msi.msi_alloc = actual; 2668 cfg->msi.msi_handlers = 0; 2669 *count = actual; 2670 return (0); 2671 } 2672 2673 /* Release the MSI messages associated with this device. */ 2674 int 2675 pci_release_msi_method(device_t dev, device_t child) 2676 { 2677 struct pci_devinfo *dinfo = device_get_ivars(child); 2678 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2679 struct resource_list_entry *rle; 2680 int error, i, irqs[32]; 2681 2682 /* Try MSI-X first. */ 2683 error = pci_release_msix(dev, child); 2684 if (error != ENODEV) 2685 return (error); 2686 2687 /* Do we have any messages to release? */ 2688 if (msi->msi_alloc == 0) 2689 return (ENODEV); 2690 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); 2691 2692 /* Make sure none of the resources are allocated. */ 2693 if (msi->msi_handlers > 0) 2694 return (EBUSY); 2695 for (i = 0; i < msi->msi_alloc; i++) { 2696 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2697 KASSERT(rle != NULL, ("missing MSI resource")); 2698 if (rle->res != NULL) 2699 return (EBUSY); 2700 irqs[i] = rle->start; 2701 } 2702 2703 /* Update control register with 0 count. */ 2704 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), 2705 ("%s: MSI still enabled", __func__)); 2706 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; 2707 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2708 msi->msi_ctrl, 2); 2709 2710 /* Release the messages. */ 2711 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); 2712 for (i = 0; i < msi->msi_alloc; i++) 2713 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2714 2715 /* Update alloc count. */ 2716 msi->msi_alloc = 0; 2717 msi->msi_addr = 0; 2718 msi->msi_data = 0; 2719 return (0); 2720 } 2721 2722 /* 2723 * Return the max supported MSI messages this device supports. 2724 * Basically, assuming the MD code can alloc messages, this function 2725 * should return the maximum value that pci_alloc_msi() can return. 2726 * Thus, it is subject to the tunables, etc. 2727 */ 2728 int 2729 pci_msi_count_method(device_t dev, device_t child) 2730 { 2731 struct pci_devinfo *dinfo = device_get_ivars(child); 2732 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2733 2734 if (pci_do_msi && msi->msi_location != 0) 2735 return (msi->msi_msgnum); 2736 return (0); 2737 } 2738 2739 /* free pcicfgregs structure and all depending data structures */ 2740 2741 int 2742 pci_freecfg(struct pci_devinfo *dinfo) 2743 { 2744 struct devlist *devlist_head; 2745 struct pci_map *pm, *next; 2746 int i; 2747 2748 devlist_head = &pci_devq; 2749 2750 if (dinfo->cfg.vpd.vpd_reg) { 2751 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF); 2752 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++) 2753 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF); 2754 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF); 2755 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++) 2756 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF); 2757 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF); 2758 } 2759 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { 2760 free(pm, M_DEVBUF); 2761 } 2762 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 2763 free(dinfo, M_DEVBUF); 2764 2765 /* increment the generation count */ 2766 pci_generation++; 2767 2768 /* we're losing one device */ 2769 pci_numdevs--; 2770 return (0); 2771 } 2772 2773 /* 2774 * PCI power manangement 2775 */ 2776 int 2777 pci_set_powerstate_method(device_t dev, device_t child, int state) 2778 { 2779 struct pci_devinfo *dinfo = device_get_ivars(child); 2780 pcicfgregs *cfg = &dinfo->cfg; 2781 uint16_t status; 2782 int oldstate, highest, delay; 2783 2784 if (cfg->pp.pp_cap == 0) 2785 return (EOPNOTSUPP); 2786 2787 /* 2788 * Optimize a no state change request away. While it would be OK to 2789 * write to the hardware in theory, some devices have shown odd 2790 * behavior when going from D3 -> D3. 2791 */ 2792 oldstate = pci_get_powerstate(child); 2793 if (oldstate == state) 2794 return (0); 2795 2796 /* 2797 * The PCI power management specification states that after a state 2798 * transition between PCI power states, system software must 2799 * guarantee a minimal delay before the function accesses the device. 2800 * Compute the worst case delay that we need to guarantee before we 2801 * access the device. Many devices will be responsive much more 2802 * quickly than this delay, but there are some that don't respond 2803 * instantly to state changes. Transitions to/from D3 state require 2804 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 2805 * is done below with DELAY rather than a sleeper function because 2806 * this function can be called from contexts where we cannot sleep. 2807 */ 2808 highest = (oldstate > state) ? oldstate : state; 2809 if (highest == PCI_POWERSTATE_D3) 2810 delay = 10000; 2811 else if (highest == PCI_POWERSTATE_D2) 2812 delay = 200; 2813 else 2814 delay = 0; 2815 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 2816 & ~PCIM_PSTAT_DMASK; 2817 switch (state) { 2818 case PCI_POWERSTATE_D0: 2819 status |= PCIM_PSTAT_D0; 2820 break; 2821 case PCI_POWERSTATE_D1: 2822 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 2823 return (EOPNOTSUPP); 2824 status |= PCIM_PSTAT_D1; 2825 break; 2826 case PCI_POWERSTATE_D2: 2827 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 2828 return (EOPNOTSUPP); 2829 status |= PCIM_PSTAT_D2; 2830 break; 2831 case PCI_POWERSTATE_D3: 2832 status |= PCIM_PSTAT_D3; 2833 break; 2834 default: 2835 return (EINVAL); 2836 } 2837 2838 if (bootverbose) 2839 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate, 2840 state); 2841 2842 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 2843 if (delay) 2844 DELAY(delay); 2845 return (0); 2846 } 2847 2848 int 2849 pci_get_powerstate_method(device_t dev, device_t child) 2850 { 2851 struct pci_devinfo *dinfo = device_get_ivars(child); 2852 pcicfgregs *cfg = &dinfo->cfg; 2853 uint16_t status; 2854 int result; 2855 2856 if (cfg->pp.pp_cap != 0) { 2857 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 2858 switch (status & PCIM_PSTAT_DMASK) { 2859 case PCIM_PSTAT_D0: 2860 result = PCI_POWERSTATE_D0; 2861 break; 2862 case PCIM_PSTAT_D1: 2863 result = PCI_POWERSTATE_D1; 2864 break; 2865 case PCIM_PSTAT_D2: 2866 result = PCI_POWERSTATE_D2; 2867 break; 2868 case PCIM_PSTAT_D3: 2869 result = PCI_POWERSTATE_D3; 2870 break; 2871 default: 2872 result = PCI_POWERSTATE_UNKNOWN; 2873 break; 2874 } 2875 } else { 2876 /* No support, device is always at D0 */ 2877 result = PCI_POWERSTATE_D0; 2878 } 2879 return (result); 2880 } 2881 2882 /* 2883 * Some convenience functions for PCI device drivers. 2884 */ 2885 2886 static __inline void 2887 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 2888 { 2889 uint16_t command; 2890 2891 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2892 command |= bit; 2893 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2894 } 2895 2896 static __inline void 2897 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 2898 { 2899 uint16_t command; 2900 2901 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2902 command &= ~bit; 2903 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2904 } 2905 2906 int 2907 pci_enable_busmaster_method(device_t dev, device_t child) 2908 { 2909 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2910 return (0); 2911 } 2912 2913 int 2914 pci_disable_busmaster_method(device_t dev, device_t child) 2915 { 2916 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2917 return (0); 2918 } 2919 2920 int 2921 pci_enable_io_method(device_t dev, device_t child, int space) 2922 { 2923 uint16_t bit; 2924 2925 switch(space) { 2926 case SYS_RES_IOPORT: 2927 bit = PCIM_CMD_PORTEN; 2928 break; 2929 case SYS_RES_MEMORY: 2930 bit = PCIM_CMD_MEMEN; 2931 break; 2932 default: 2933 return (EINVAL); 2934 } 2935 pci_set_command_bit(dev, child, bit); 2936 return (0); 2937 } 2938 2939 int 2940 pci_disable_io_method(device_t dev, device_t child, int space) 2941 { 2942 uint16_t bit; 2943 2944 switch(space) { 2945 case SYS_RES_IOPORT: 2946 bit = PCIM_CMD_PORTEN; 2947 break; 2948 case SYS_RES_MEMORY: 2949 bit = PCIM_CMD_MEMEN; 2950 break; 2951 default: 2952 return (EINVAL); 2953 } 2954 pci_clear_command_bit(dev, child, bit); 2955 return (0); 2956 } 2957 2958 /* 2959 * New style pci driver. Parent device is either a pci-host-bridge or a 2960 * pci-pci-bridge. Both kinds are represented by instances of pcib. 2961 */ 2962 2963 void 2964 pci_print_verbose(struct pci_devinfo *dinfo) 2965 { 2966 2967 if (bootverbose) { 2968 pcicfgregs *cfg = &dinfo->cfg; 2969 2970 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 2971 cfg->vendor, cfg->device, cfg->revid); 2972 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n", 2973 cfg->domain, cfg->bus, cfg->slot, cfg->func); 2974 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 2975 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 2976 cfg->mfdev); 2977 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 2978 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 2979 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 2980 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 2981 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 2982 if (cfg->intpin > 0) 2983 printf("\tintpin=%c, irq=%d\n", 2984 cfg->intpin +'a' -1, cfg->intline); 2985 if (cfg->pp.pp_cap) { 2986 uint16_t status; 2987 2988 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 2989 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 2990 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 2991 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 2992 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 2993 status & PCIM_PSTAT_DMASK); 2994 } 2995 if (cfg->msi.msi_location) { 2996 int ctrl; 2997 2998 ctrl = cfg->msi.msi_ctrl; 2999 printf("\tMSI supports %d message%s%s%s\n", 3000 cfg->msi.msi_msgnum, 3001 (cfg->msi.msi_msgnum == 1) ? "" : "s", 3002 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 3003 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 3004 } 3005 if (cfg->msix.msix_location) { 3006 printf("\tMSI-X supports %d message%s ", 3007 cfg->msix.msix_msgnum, 3008 (cfg->msix.msix_msgnum == 1) ? "" : "s"); 3009 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 3010 printf("in map 0x%x\n", 3011 cfg->msix.msix_table_bar); 3012 else 3013 printf("in maps 0x%x and 0x%x\n", 3014 cfg->msix.msix_table_bar, 3015 cfg->msix.msix_pba_bar); 3016 } 3017 } 3018 } 3019 3020 static int 3021 pci_porten(device_t dev) 3022 { 3023 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0; 3024 } 3025 3026 static int 3027 pci_memen(device_t dev) 3028 { 3029 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0; 3030 } 3031 3032 void 3033 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, 3034 int *bar64) 3035 { 3036 struct pci_devinfo *dinfo; 3037 pci_addr_t map, testval; 3038 int ln2range; 3039 uint16_t cmd; 3040 3041 /* 3042 * The device ROM BAR is special. It is always a 32-bit 3043 * memory BAR. Bit 0 is special and should not be set when 3044 * sizing the BAR. 3045 */ 3046 dinfo = device_get_ivars(dev); 3047 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { 3048 map = pci_read_config(dev, reg, 4); 3049 pci_write_config(dev, reg, 0xfffffffe, 4); 3050 testval = pci_read_config(dev, reg, 4); 3051 pci_write_config(dev, reg, map, 4); 3052 *mapp = map; 3053 *testvalp = testval; 3054 if (bar64 != NULL) 3055 *bar64 = 0; 3056 return; 3057 } 3058 3059 map = pci_read_config(dev, reg, 4); 3060 ln2range = pci_maprange(map); 3061 if (ln2range == 64) 3062 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3063 3064 /* 3065 * Disable decoding via the command register before 3066 * determining the BAR's length since we will be placing it in 3067 * a weird state. 3068 */ 3069 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3070 pci_write_config(dev, PCIR_COMMAND, 3071 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 3072 3073 /* 3074 * Determine the BAR's length by writing all 1's. The bottom 3075 * log_2(size) bits of the BAR will stick as 0 when we read 3076 * the value back. 3077 * 3078 * NB: according to the PCI Local Bus Specification, rev. 3.0: 3079 * "Software writes 0FFFFFFFFh to both registers, reads them back, 3080 * and combines the result into a 64-bit value." (section 6.2.5.1) 3081 * 3082 * Writes to both registers must be performed before attempting to 3083 * read back the size value. 3084 */ 3085 testval = 0; 3086 pci_write_config(dev, reg, 0xffffffff, 4); 3087 if (ln2range == 64) { 3088 pci_write_config(dev, reg + 4, 0xffffffff, 4); 3089 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3090 } 3091 testval |= pci_read_config(dev, reg, 4); 3092 3093 /* 3094 * Restore the original value of the BAR. We may have reprogrammed 3095 * the BAR of the low-level console device and when booting verbose, 3096 * we need the console device addressable. 3097 */ 3098 pci_write_config(dev, reg, map, 4); 3099 if (ln2range == 64) 3100 pci_write_config(dev, reg + 4, map >> 32, 4); 3101 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3102 3103 *mapp = map; 3104 *testvalp = testval; 3105 if (bar64 != NULL) 3106 *bar64 = (ln2range == 64); 3107 } 3108 3109 static void 3110 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base) 3111 { 3112 struct pci_devinfo *dinfo; 3113 int ln2range; 3114 3115 /* The device ROM BAR is always a 32-bit memory BAR. */ 3116 dinfo = device_get_ivars(dev); 3117 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3118 ln2range = 32; 3119 else 3120 ln2range = pci_maprange(pm->pm_value); 3121 pci_write_config(dev, pm->pm_reg, base, 4); 3122 if (ln2range == 64) 3123 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); 3124 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); 3125 if (ln2range == 64) 3126 pm->pm_value |= (pci_addr_t)pci_read_config(dev, 3127 pm->pm_reg + 4, 4) << 32; 3128 } 3129 3130 struct pci_map * 3131 pci_find_bar(device_t dev, int reg) 3132 { 3133 struct pci_devinfo *dinfo; 3134 struct pci_map *pm; 3135 3136 dinfo = device_get_ivars(dev); 3137 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3138 if (pm->pm_reg == reg) 3139 return (pm); 3140 } 3141 return (NULL); 3142 } 3143 3144 int 3145 pci_bar_enabled(device_t dev, struct pci_map *pm) 3146 { 3147 struct pci_devinfo *dinfo; 3148 uint16_t cmd; 3149 3150 dinfo = device_get_ivars(dev); 3151 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && 3152 !(pm->pm_value & PCIM_BIOS_ENABLE)) 3153 return (0); 3154 #ifdef PCI_IOV 3155 if ((dinfo->cfg.flags & PCICFG_VF) != 0) { 3156 struct pcicfg_iov *iov; 3157 3158 iov = dinfo->cfg.iov; 3159 cmd = pci_read_config(iov->iov_pf, 3160 iov->iov_pos + PCIR_SRIOV_CTL, 2); 3161 return ((cmd & PCIM_SRIOV_VF_MSE) != 0); 3162 } 3163 #endif 3164 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3165 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) 3166 return ((cmd & PCIM_CMD_MEMEN) != 0); 3167 else 3168 return ((cmd & PCIM_CMD_PORTEN) != 0); 3169 } 3170 3171 struct pci_map * 3172 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size) 3173 { 3174 struct pci_devinfo *dinfo; 3175 struct pci_map *pm, *prev; 3176 3177 dinfo = device_get_ivars(dev); 3178 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO); 3179 pm->pm_reg = reg; 3180 pm->pm_value = value; 3181 pm->pm_size = size; 3182 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { 3183 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", 3184 reg)); 3185 if (STAILQ_NEXT(prev, pm_link) == NULL || 3186 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) 3187 break; 3188 } 3189 if (prev != NULL) 3190 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); 3191 else 3192 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); 3193 return (pm); 3194 } 3195 3196 static void 3197 pci_restore_bars(device_t dev) 3198 { 3199 struct pci_devinfo *dinfo; 3200 struct pci_map *pm; 3201 int ln2range; 3202 3203 dinfo = device_get_ivars(dev); 3204 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3205 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3206 ln2range = 32; 3207 else 3208 ln2range = pci_maprange(pm->pm_value); 3209 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); 3210 if (ln2range == 64) 3211 pci_write_config(dev, pm->pm_reg + 4, 3212 pm->pm_value >> 32, 4); 3213 } 3214 } 3215 3216 /* 3217 * Add a resource based on a pci map register. Return 1 if the map 3218 * register is a 32bit map register or 2 if it is a 64bit register. 3219 */ 3220 static int 3221 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, 3222 int force, int prefetch) 3223 { 3224 struct pci_map *pm; 3225 pci_addr_t base, map, testval; 3226 pci_addr_t start, end, count; 3227 int barlen, basezero, flags, maprange, mapsize, type; 3228 uint16_t cmd; 3229 struct resource *res; 3230 3231 /* 3232 * The BAR may already exist if the device is a CardBus card 3233 * whose CIS is stored in this BAR. 3234 */ 3235 pm = pci_find_bar(dev, reg); 3236 if (pm != NULL) { 3237 maprange = pci_maprange(pm->pm_value); 3238 barlen = maprange == 64 ? 2 : 1; 3239 return (barlen); 3240 } 3241 3242 pci_read_bar(dev, reg, &map, &testval, NULL); 3243 if (PCI_BAR_MEM(map)) { 3244 type = SYS_RES_MEMORY; 3245 if (map & PCIM_BAR_MEM_PREFETCH) 3246 prefetch = 1; 3247 } else 3248 type = SYS_RES_IOPORT; 3249 mapsize = pci_mapsize(testval); 3250 base = pci_mapbase(map); 3251 #ifdef __PCI_BAR_ZERO_VALID 3252 basezero = 0; 3253 #else 3254 basezero = base == 0; 3255 #endif 3256 maprange = pci_maprange(map); 3257 barlen = maprange == 64 ? 2 : 1; 3258 3259 /* 3260 * For I/O registers, if bottom bit is set, and the next bit up 3261 * isn't clear, we know we have a BAR that doesn't conform to the 3262 * spec, so ignore it. Also, sanity check the size of the data 3263 * areas to the type of memory involved. Memory must be at least 3264 * 16 bytes in size, while I/O ranges must be at least 4. 3265 */ 3266 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0) 3267 return (barlen); 3268 if ((type == SYS_RES_MEMORY && mapsize < 4) || 3269 (type == SYS_RES_IOPORT && mapsize < 2)) 3270 return (barlen); 3271 3272 /* Save a record of this BAR. */ 3273 pm = pci_add_bar(dev, reg, map, mapsize); 3274 if (bootverbose) { 3275 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d", 3276 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize); 3277 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3278 printf(", port disabled\n"); 3279 else if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3280 printf(", memory disabled\n"); 3281 else 3282 printf(", enabled\n"); 3283 } 3284 3285 /* 3286 * If base is 0, then we have problems if this architecture does 3287 * not allow that. It is best to ignore such entries for the 3288 * moment. These will be allocated later if the driver specifically 3289 * requests them. However, some removable buses look better when 3290 * all resources are allocated, so allow '0' to be overriden. 3291 * 3292 * Similarly treat maps whose values is the same as the test value 3293 * read back. These maps have had all f's written to them by the 3294 * BIOS in an attempt to disable the resources. 3295 */ 3296 if (!force && (basezero || map == testval)) 3297 return (barlen); 3298 if ((u_long)base != base) { 3299 device_printf(bus, 3300 "pci%d:%d:%d:%d bar %#x too many address bits", 3301 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev), 3302 pci_get_function(dev), reg); 3303 return (barlen); 3304 } 3305 3306 /* 3307 * This code theoretically does the right thing, but has 3308 * undesirable side effects in some cases where peripherals 3309 * respond oddly to having these bits enabled. Let the user 3310 * be able to turn them off (since pci_enable_io_modes is 1 by 3311 * default). 3312 */ 3313 if (pci_enable_io_modes) { 3314 /* Turn on resources that have been left off by a lazy BIOS */ 3315 if (type == SYS_RES_IOPORT && !pci_porten(dev)) { 3316 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3317 cmd |= PCIM_CMD_PORTEN; 3318 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3319 } 3320 if (type == SYS_RES_MEMORY && !pci_memen(dev)) { 3321 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3322 cmd |= PCIM_CMD_MEMEN; 3323 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3324 } 3325 } else { 3326 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3327 return (barlen); 3328 if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3329 return (barlen); 3330 } 3331 3332 count = (pci_addr_t)1 << mapsize; 3333 flags = RF_ALIGNMENT_LOG2(mapsize); 3334 if (prefetch) 3335 flags |= RF_PREFETCHABLE; 3336 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) { 3337 start = 0; /* Let the parent decide. */ 3338 end = ~0; 3339 } else { 3340 start = base; 3341 end = base + count - 1; 3342 } 3343 resource_list_add(rl, type, reg, start, end, count); 3344 3345 /* 3346 * Try to allocate the resource for this BAR from our parent 3347 * so that this resource range is already reserved. The 3348 * driver for this device will later inherit this resource in 3349 * pci_alloc_resource(). 3350 */ 3351 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count, 3352 flags); 3353 if ((pci_do_realloc_bars 3354 || pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_REALLOC_BAR)) 3355 && res == NULL && (start != 0 || end != ~0)) { 3356 /* 3357 * If the allocation fails, try to allocate a resource for 3358 * this BAR using any available range. The firmware felt 3359 * it was important enough to assign a resource, so don't 3360 * disable decoding if we can help it. 3361 */ 3362 resource_list_delete(rl, type, reg); 3363 resource_list_add(rl, type, reg, 0, ~0, count); 3364 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0, 3365 count, flags); 3366 } 3367 if (res == NULL) { 3368 /* 3369 * If the allocation fails, delete the resource list entry 3370 * and disable decoding for this device. 3371 * 3372 * If the driver requests this resource in the future, 3373 * pci_reserve_map() will try to allocate a fresh 3374 * resource range. 3375 */ 3376 resource_list_delete(rl, type, reg); 3377 pci_disable_io(dev, type); 3378 if (bootverbose) 3379 device_printf(bus, 3380 "pci%d:%d:%d:%d bar %#x failed to allocate\n", 3381 pci_get_domain(dev), pci_get_bus(dev), 3382 pci_get_slot(dev), pci_get_function(dev), reg); 3383 } else { 3384 start = rman_get_start(res); 3385 pci_write_bar(dev, pm, start); 3386 } 3387 return (barlen); 3388 } 3389 3390 /* 3391 * For ATA devices we need to decide early what addressing mode to use. 3392 * Legacy demands that the primary and secondary ATA ports sits on the 3393 * same addresses that old ISA hardware did. This dictates that we use 3394 * those addresses and ignore the BAR's if we cannot set PCI native 3395 * addressing mode. 3396 */ 3397 static void 3398 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, 3399 uint32_t prefetchmask) 3400 { 3401 int rid, type, progif; 3402 #if 0 3403 /* if this device supports PCI native addressing use it */ 3404 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3405 if ((progif & 0x8a) == 0x8a) { 3406 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 3407 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 3408 printf("Trying ATA native PCI addressing mode\n"); 3409 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 3410 } 3411 } 3412 #endif 3413 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3414 type = SYS_RES_IOPORT; 3415 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 3416 pci_add_map(bus, dev, PCIR_BAR(0), rl, force, 3417 prefetchmask & (1 << 0)); 3418 pci_add_map(bus, dev, PCIR_BAR(1), rl, force, 3419 prefetchmask & (1 << 1)); 3420 } else { 3421 rid = PCIR_BAR(0); 3422 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 3423 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0, 3424 0x1f7, 8, 0); 3425 rid = PCIR_BAR(1); 3426 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 3427 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6, 3428 0x3f6, 1, 0); 3429 } 3430 if (progif & PCIP_STORAGE_IDE_MODESEC) { 3431 pci_add_map(bus, dev, PCIR_BAR(2), rl, force, 3432 prefetchmask & (1 << 2)); 3433 pci_add_map(bus, dev, PCIR_BAR(3), rl, force, 3434 prefetchmask & (1 << 3)); 3435 } else { 3436 rid = PCIR_BAR(2); 3437 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 3438 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170, 3439 0x177, 8, 0); 3440 rid = PCIR_BAR(3); 3441 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 3442 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376, 3443 0x376, 1, 0); 3444 } 3445 pci_add_map(bus, dev, PCIR_BAR(4), rl, force, 3446 prefetchmask & (1 << 4)); 3447 pci_add_map(bus, dev, PCIR_BAR(5), rl, force, 3448 prefetchmask & (1 << 5)); 3449 } 3450 3451 static void 3452 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 3453 { 3454 struct pci_devinfo *dinfo = device_get_ivars(dev); 3455 pcicfgregs *cfg = &dinfo->cfg; 3456 char tunable_name[64]; 3457 int irq; 3458 3459 /* Has to have an intpin to have an interrupt. */ 3460 if (cfg->intpin == 0) 3461 return; 3462 3463 /* Let the user override the IRQ with a tunable. */ 3464 irq = PCI_INVALID_IRQ; 3465 snprintf(tunable_name, sizeof(tunable_name), 3466 "hw.pci%d.%d.%d.INT%c.irq", 3467 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 3468 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 3469 irq = PCI_INVALID_IRQ; 3470 3471 /* 3472 * If we didn't get an IRQ via the tunable, then we either use the 3473 * IRQ value in the intline register or we ask the bus to route an 3474 * interrupt for us. If force_route is true, then we only use the 3475 * value in the intline register if the bus was unable to assign an 3476 * IRQ. 3477 */ 3478 if (!PCI_INTERRUPT_VALID(irq)) { 3479 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 3480 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 3481 if (!PCI_INTERRUPT_VALID(irq)) 3482 irq = cfg->intline; 3483 } 3484 3485 /* If after all that we don't have an IRQ, just bail. */ 3486 if (!PCI_INTERRUPT_VALID(irq)) 3487 return; 3488 3489 /* Update the config register if it changed. */ 3490 if (irq != cfg->intline) { 3491 cfg->intline = irq; 3492 pci_write_config(dev, PCIR_INTLINE, irq, 1); 3493 } 3494 3495 /* Add this IRQ as rid 0 interrupt resource. */ 3496 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 3497 } 3498 3499 /* Perform early OHCI takeover from SMM. */ 3500 static void 3501 ohci_early_takeover(device_t self) 3502 { 3503 struct resource *res; 3504 uint32_t ctl; 3505 int rid; 3506 int i; 3507 3508 rid = PCIR_BAR(0); 3509 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3510 if (res == NULL) 3511 return; 3512 3513 ctl = bus_read_4(res, OHCI_CONTROL); 3514 if (ctl & OHCI_IR) { 3515 if (bootverbose) 3516 printf("ohci early: " 3517 "SMM active, request owner change\n"); 3518 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR); 3519 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 3520 DELAY(1000); 3521 ctl = bus_read_4(res, OHCI_CONTROL); 3522 } 3523 if (ctl & OHCI_IR) { 3524 if (bootverbose) 3525 printf("ohci early: " 3526 "SMM does not respond, resetting\n"); 3527 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET); 3528 } 3529 /* Disable interrupts */ 3530 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 3531 } 3532 3533 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3534 } 3535 3536 /* Perform early UHCI takeover from SMM. */ 3537 static void 3538 uhci_early_takeover(device_t self) 3539 { 3540 struct resource *res; 3541 int rid; 3542 3543 /* 3544 * Set the PIRQD enable bit and switch off all the others. We don't 3545 * want legacy support to interfere with us XXX Does this also mean 3546 * that the BIOS won't touch the keyboard anymore if it is connected 3547 * to the ports of the root hub? 3548 */ 3549 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2); 3550 3551 /* Disable interrupts */ 3552 rid = PCI_UHCI_BASE_REG; 3553 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE); 3554 if (res != NULL) { 3555 bus_write_2(res, UHCI_INTR, 0); 3556 bus_release_resource(self, SYS_RES_IOPORT, rid, res); 3557 } 3558 } 3559 3560 /* Perform early EHCI takeover from SMM. */ 3561 static void 3562 ehci_early_takeover(device_t self) 3563 { 3564 struct resource *res; 3565 uint32_t cparams; 3566 uint32_t eec; 3567 uint8_t eecp; 3568 uint8_t bios_sem; 3569 uint8_t offs; 3570 int rid; 3571 int i; 3572 3573 rid = PCIR_BAR(0); 3574 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3575 if (res == NULL) 3576 return; 3577 3578 cparams = bus_read_4(res, EHCI_HCCPARAMS); 3579 3580 /* Synchronise with the BIOS if it owns the controller. */ 3581 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0; 3582 eecp = EHCI_EECP_NEXT(eec)) { 3583 eec = pci_read_config(self, eecp, 4); 3584 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) { 3585 continue; 3586 } 3587 bios_sem = pci_read_config(self, eecp + 3588 EHCI_LEGSUP_BIOS_SEM, 1); 3589 if (bios_sem == 0) { 3590 continue; 3591 } 3592 if (bootverbose) 3593 printf("ehci early: " 3594 "SMM active, request owner change\n"); 3595 3596 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1); 3597 3598 for (i = 0; (i < 100) && (bios_sem != 0); i++) { 3599 DELAY(1000); 3600 bios_sem = pci_read_config(self, eecp + 3601 EHCI_LEGSUP_BIOS_SEM, 1); 3602 } 3603 3604 if (bios_sem != 0) { 3605 if (bootverbose) 3606 printf("ehci early: " 3607 "SMM does not respond\n"); 3608 } 3609 /* Disable interrupts */ 3610 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION)); 3611 bus_write_4(res, offs + EHCI_USBINTR, 0); 3612 } 3613 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3614 } 3615 3616 /* Perform early XHCI takeover from SMM. */ 3617 static void 3618 xhci_early_takeover(device_t self) 3619 { 3620 struct resource *res; 3621 uint32_t cparams; 3622 uint32_t eec; 3623 uint8_t eecp; 3624 uint8_t bios_sem; 3625 uint8_t offs; 3626 int rid; 3627 int i; 3628 3629 rid = PCIR_BAR(0); 3630 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3631 if (res == NULL) 3632 return; 3633 3634 cparams = bus_read_4(res, XHCI_HCSPARAMS0); 3635 3636 eec = -1; 3637 3638 /* Synchronise with the BIOS if it owns the controller. */ 3639 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 3640 eecp += XHCI_XECP_NEXT(eec) << 2) { 3641 eec = bus_read_4(res, eecp); 3642 3643 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 3644 continue; 3645 3646 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM); 3647 if (bios_sem == 0) 3648 continue; 3649 3650 if (bootverbose) 3651 printf("xhci early: " 3652 "SMM active, request owner change\n"); 3653 3654 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1); 3655 3656 /* wait a maximum of 5 second */ 3657 3658 for (i = 0; (i < 5000) && (bios_sem != 0); i++) { 3659 DELAY(1000); 3660 bios_sem = bus_read_1(res, eecp + 3661 XHCI_XECP_BIOS_SEM); 3662 } 3663 3664 if (bios_sem != 0) { 3665 if (bootverbose) 3666 printf("xhci early: " 3667 "SMM does not respond\n"); 3668 } 3669 3670 /* Disable interrupts */ 3671 offs = bus_read_1(res, XHCI_CAPLENGTH); 3672 bus_write_4(res, offs + XHCI_USBCMD, 0); 3673 bus_read_4(res, offs + XHCI_USBSTS); 3674 } 3675 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3676 } 3677 3678 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 3679 static void 3680 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg, 3681 struct resource_list *rl) 3682 { 3683 struct resource *res; 3684 char *cp; 3685 rman_res_t start, end, count; 3686 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus; 3687 3688 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3689 case PCIM_HDRTYPE_BRIDGE: 3690 sec_reg = PCIR_SECBUS_1; 3691 sub_reg = PCIR_SUBBUS_1; 3692 break; 3693 case PCIM_HDRTYPE_CARDBUS: 3694 sec_reg = PCIR_SECBUS_2; 3695 sub_reg = PCIR_SUBBUS_2; 3696 break; 3697 default: 3698 return; 3699 } 3700 3701 /* 3702 * If the existing bus range is valid, attempt to reserve it 3703 * from our parent. If this fails for any reason, clear the 3704 * secbus and subbus registers. 3705 * 3706 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus? 3707 * This would at least preserve the existing sec_bus if it is 3708 * valid. 3709 */ 3710 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1); 3711 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1); 3712 3713 /* Quirk handling. */ 3714 switch (pci_get_devid(dev)) { 3715 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 3716 sup_bus = pci_read_config(dev, 0x41, 1); 3717 if (sup_bus != 0xff) { 3718 sec_bus = sup_bus + 1; 3719 sub_bus = sup_bus + 1; 3720 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1); 3721 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3722 } 3723 break; 3724 3725 case 0x00dd10de: 3726 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 3727 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 3728 break; 3729 if (strncmp(cp, "Compal", 6) != 0) { 3730 freeenv(cp); 3731 break; 3732 } 3733 freeenv(cp); 3734 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 3735 break; 3736 if (strncmp(cp, "08A0", 4) != 0) { 3737 freeenv(cp); 3738 break; 3739 } 3740 freeenv(cp); 3741 if (sub_bus < 0xa) { 3742 sub_bus = 0xa; 3743 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3744 } 3745 break; 3746 } 3747 3748 if (bootverbose) 3749 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus); 3750 if (sec_bus > 0 && sub_bus >= sec_bus) { 3751 start = sec_bus; 3752 end = sub_bus; 3753 count = end - start + 1; 3754 3755 resource_list_add(rl, PCI_RES_BUS, 0, 0, ~0, count); 3756 3757 /* 3758 * If requested, clear secondary bus registers in 3759 * bridge devices to force a complete renumbering 3760 * rather than reserving the existing range. However, 3761 * preserve the existing size. 3762 */ 3763 if (pci_clear_buses) 3764 goto clear; 3765 3766 rid = 0; 3767 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid, 3768 start, end, count, 0); 3769 if (res != NULL) 3770 return; 3771 3772 if (bootverbose) 3773 device_printf(bus, 3774 "pci%d:%d:%d:%d secbus failed to allocate\n", 3775 pci_get_domain(dev), pci_get_bus(dev), 3776 pci_get_slot(dev), pci_get_function(dev)); 3777 } 3778 3779 clear: 3780 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1); 3781 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1); 3782 } 3783 3784 static struct resource * 3785 pci_alloc_secbus(device_t dev, device_t child, int *rid, rman_res_t start, 3786 rman_res_t end, rman_res_t count, u_int flags) 3787 { 3788 struct pci_devinfo *dinfo; 3789 pcicfgregs *cfg; 3790 struct resource_list *rl; 3791 struct resource *res; 3792 int sec_reg, sub_reg; 3793 3794 dinfo = device_get_ivars(child); 3795 cfg = &dinfo->cfg; 3796 rl = &dinfo->resources; 3797 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3798 case PCIM_HDRTYPE_BRIDGE: 3799 sec_reg = PCIR_SECBUS_1; 3800 sub_reg = PCIR_SUBBUS_1; 3801 break; 3802 case PCIM_HDRTYPE_CARDBUS: 3803 sec_reg = PCIR_SECBUS_2; 3804 sub_reg = PCIR_SUBBUS_2; 3805 break; 3806 default: 3807 return (NULL); 3808 } 3809 3810 if (*rid != 0) 3811 return (NULL); 3812 3813 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL) 3814 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count); 3815 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) { 3816 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid, 3817 start, end, count, flags & ~RF_ACTIVE); 3818 if (res == NULL) { 3819 resource_list_delete(rl, PCI_RES_BUS, *rid); 3820 device_printf(child, "allocating %ju bus%s failed\n", 3821 count, count == 1 ? "" : "es"); 3822 return (NULL); 3823 } 3824 if (bootverbose) 3825 device_printf(child, 3826 "Lazy allocation of %ju bus%s at %ju\n", count, 3827 count == 1 ? "" : "es", rman_get_start(res)); 3828 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1); 3829 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1); 3830 } 3831 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start, 3832 end, count, flags)); 3833 } 3834 #endif 3835 3836 static int 3837 pci_ea_bei_to_rid(device_t dev, int bei) 3838 { 3839 #ifdef PCI_IOV 3840 struct pci_devinfo *dinfo; 3841 int iov_pos; 3842 struct pcicfg_iov *iov; 3843 3844 dinfo = device_get_ivars(dev); 3845 iov = dinfo->cfg.iov; 3846 if (iov != NULL) 3847 iov_pos = iov->iov_pos; 3848 else 3849 iov_pos = 0; 3850 #endif 3851 3852 /* Check if matches BAR */ 3853 if ((bei >= PCIM_EA_BEI_BAR_0) && 3854 (bei <= PCIM_EA_BEI_BAR_5)) 3855 return (PCIR_BAR(bei)); 3856 3857 /* Check ROM */ 3858 if (bei == PCIM_EA_BEI_ROM) 3859 return (PCIR_BIOS); 3860 3861 #ifdef PCI_IOV 3862 /* Check if matches VF_BAR */ 3863 if ((iov != NULL) && (bei >= PCIM_EA_BEI_VF_BAR_0) && 3864 (bei <= PCIM_EA_BEI_VF_BAR_5)) 3865 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) + 3866 iov_pos); 3867 #endif 3868 3869 return (-1); 3870 } 3871 3872 int 3873 pci_ea_is_enabled(device_t dev, int rid) 3874 { 3875 struct pci_ea_entry *ea; 3876 struct pci_devinfo *dinfo; 3877 3878 dinfo = device_get_ivars(dev); 3879 3880 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3881 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid) 3882 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0); 3883 } 3884 3885 return (0); 3886 } 3887 3888 void 3889 pci_add_resources_ea(device_t bus, device_t dev, int alloc_iov) 3890 { 3891 struct pci_ea_entry *ea; 3892 struct pci_devinfo *dinfo; 3893 pci_addr_t start, end, count; 3894 struct resource_list *rl; 3895 int type, flags, rid; 3896 struct resource *res; 3897 uint32_t tmp; 3898 #ifdef PCI_IOV 3899 struct pcicfg_iov *iov; 3900 #endif 3901 3902 dinfo = device_get_ivars(dev); 3903 rl = &dinfo->resources; 3904 flags = 0; 3905 3906 #ifdef PCI_IOV 3907 iov = dinfo->cfg.iov; 3908 #endif 3909 3910 if (dinfo->cfg.ea.ea_location == 0) 3911 return; 3912 3913 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3914 /* 3915 * TODO: Ignore EA-BAR if is not enabled. 3916 * Currently the EA implementation supports 3917 * only situation, where EA structure contains 3918 * predefined entries. In case they are not enabled 3919 * leave them unallocated and proceed with 3920 * a legacy-BAR mechanism. 3921 */ 3922 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0) 3923 continue; 3924 3925 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) { 3926 case PCIM_EA_P_MEM_PREFETCH: 3927 case PCIM_EA_P_VF_MEM_PREFETCH: 3928 flags = RF_PREFETCHABLE; 3929 /* FALLTHROUGH */ 3930 case PCIM_EA_P_VF_MEM: 3931 case PCIM_EA_P_MEM: 3932 type = SYS_RES_MEMORY; 3933 break; 3934 case PCIM_EA_P_IO: 3935 type = SYS_RES_IOPORT; 3936 break; 3937 default: 3938 continue; 3939 } 3940 3941 if (alloc_iov != 0) { 3942 #ifdef PCI_IOV 3943 /* Allocating IOV, confirm BEI matches */ 3944 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) || 3945 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5)) 3946 continue; 3947 #else 3948 continue; 3949 #endif 3950 } else { 3951 /* Allocating BAR, confirm BEI matches */ 3952 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) || 3953 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) && 3954 (ea->eae_bei != PCIM_EA_BEI_ROM)) 3955 continue; 3956 } 3957 3958 rid = pci_ea_bei_to_rid(dev, ea->eae_bei); 3959 if (rid < 0) 3960 continue; 3961 3962 /* Skip resources already allocated by EA */ 3963 if ((resource_list_find(rl, SYS_RES_MEMORY, rid) != NULL) || 3964 (resource_list_find(rl, SYS_RES_IOPORT, rid) != NULL)) 3965 continue; 3966 3967 start = ea->eae_base; 3968 count = ea->eae_max_offset + 1; 3969 #ifdef PCI_IOV 3970 if (iov != NULL) 3971 count = count * iov->iov_num_vfs; 3972 #endif 3973 end = start + count - 1; 3974 if (count == 0) 3975 continue; 3976 3977 resource_list_add(rl, type, rid, start, end, count); 3978 res = resource_list_reserve(rl, bus, dev, type, &rid, start, end, count, 3979 flags); 3980 if (res == NULL) { 3981 resource_list_delete(rl, type, rid); 3982 3983 /* 3984 * Failed to allocate using EA, disable entry. 3985 * Another attempt to allocation will be performed 3986 * further, but this time using legacy BAR registers 3987 */ 3988 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4); 3989 tmp &= ~PCIM_EA_ENABLE; 3990 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4); 3991 3992 /* 3993 * Disabling entry might fail in case it is hardwired. 3994 * Read flags again to match current status. 3995 */ 3996 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4); 3997 3998 continue; 3999 } 4000 4001 /* As per specification, fill BAR with zeros */ 4002 pci_write_config(dev, rid, 0, 4); 4003 } 4004 } 4005 4006 void 4007 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 4008 { 4009 struct pci_devinfo *dinfo; 4010 pcicfgregs *cfg; 4011 struct resource_list *rl; 4012 const struct pci_quirk *q; 4013 uint32_t devid; 4014 int i; 4015 4016 dinfo = device_get_ivars(dev); 4017 cfg = &dinfo->cfg; 4018 rl = &dinfo->resources; 4019 devid = (cfg->device << 16) | cfg->vendor; 4020 4021 /* Allocate resources using Enhanced Allocation */ 4022 pci_add_resources_ea(bus, dev, 0); 4023 4024 /* ATA devices needs special map treatment */ 4025 if ((pci_get_class(dev) == PCIC_STORAGE) && 4026 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 4027 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 4028 (!pci_read_config(dev, PCIR_BAR(0), 4) && 4029 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 4030 pci_ata_maps(bus, dev, rl, force, prefetchmask); 4031 else 4032 for (i = 0; i < cfg->nummaps;) { 4033 /* Skip resources already managed by EA */ 4034 if ((resource_list_find(rl, SYS_RES_MEMORY, PCIR_BAR(i)) != NULL) || 4035 (resource_list_find(rl, SYS_RES_IOPORT, PCIR_BAR(i)) != NULL) || 4036 pci_ea_is_enabled(dev, PCIR_BAR(i))) { 4037 i++; 4038 continue; 4039 } 4040 4041 /* 4042 * Skip quirked resources. 4043 */ 4044 for (q = &pci_quirks[0]; q->devid != 0; q++) 4045 if (q->devid == devid && 4046 q->type == PCI_QUIRK_UNMAP_REG && 4047 q->arg1 == PCIR_BAR(i)) 4048 break; 4049 if (q->devid != 0) { 4050 i++; 4051 continue; 4052 } 4053 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force, 4054 prefetchmask & (1 << i)); 4055 } 4056 4057 /* 4058 * Add additional, quirked resources. 4059 */ 4060 for (q = &pci_quirks[0]; q->devid != 0; q++) 4061 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) 4062 pci_add_map(bus, dev, q->arg1, rl, force, 0); 4063 4064 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 4065 #ifdef __PCI_REROUTE_INTERRUPT 4066 /* 4067 * Try to re-route interrupts. Sometimes the BIOS or 4068 * firmware may leave bogus values in these registers. 4069 * If the re-route fails, then just stick with what we 4070 * have. 4071 */ 4072 pci_assign_interrupt(bus, dev, 1); 4073 #else 4074 pci_assign_interrupt(bus, dev, 0); 4075 #endif 4076 } 4077 4078 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS && 4079 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) { 4080 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI) 4081 xhci_early_takeover(dev); 4082 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI) 4083 ehci_early_takeover(dev); 4084 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI) 4085 ohci_early_takeover(dev); 4086 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI) 4087 uhci_early_takeover(dev); 4088 } 4089 4090 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 4091 /* 4092 * Reserve resources for secondary bus ranges behind bridge 4093 * devices. 4094 */ 4095 pci_reserve_secbus(bus, dev, cfg, rl); 4096 #endif 4097 } 4098 4099 static struct pci_devinfo * 4100 pci_identify_function(device_t pcib, device_t dev, int domain, int busno, 4101 int slot, int func) 4102 { 4103 struct pci_devinfo *dinfo; 4104 4105 dinfo = pci_read_device(pcib, dev, domain, busno, slot, func); 4106 if (dinfo != NULL) 4107 pci_add_child(dev, dinfo); 4108 4109 return (dinfo); 4110 } 4111 4112 void 4113 pci_add_children(device_t dev, int domain, int busno) 4114 { 4115 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4116 device_t pcib = device_get_parent(dev); 4117 struct pci_devinfo *dinfo; 4118 int maxslots; 4119 int s, f, pcifunchigh; 4120 uint8_t hdrtype; 4121 int first_func; 4122 4123 /* 4124 * Try to detect a device at slot 0, function 0. If it exists, try to 4125 * enable ARI. We must enable ARI before detecting the rest of the 4126 * functions on this bus as ARI changes the set of slots and functions 4127 * that are legal on this bus. 4128 */ 4129 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0); 4130 if (dinfo != NULL && pci_enable_ari) 4131 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); 4132 4133 /* 4134 * Start looking for new devices on slot 0 at function 1 because we 4135 * just identified the device at slot 0, function 0. 4136 */ 4137 first_func = 1; 4138 4139 maxslots = PCIB_MAXSLOTS(pcib); 4140 for (s = 0; s <= maxslots; s++, first_func = 0) { 4141 pcifunchigh = 0; 4142 f = 0; 4143 DELAY(1); 4144 hdrtype = REG(PCIR_HDRTYPE, 1); 4145 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4146 continue; 4147 if (hdrtype & PCIM_MFDEV) 4148 pcifunchigh = PCIB_MAXFUNCS(pcib); 4149 for (f = first_func; f <= pcifunchigh; f++) 4150 pci_identify_function(pcib, dev, domain, busno, s, f); 4151 } 4152 #undef REG 4153 } 4154 4155 int 4156 pci_rescan_method(device_t dev) 4157 { 4158 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4159 device_t pcib = device_get_parent(dev); 4160 device_t child, *devlist, *unchanged; 4161 int devcount, error, i, j, maxslots, oldcount; 4162 int busno, domain, s, f, pcifunchigh; 4163 uint8_t hdrtype; 4164 4165 /* No need to check for ARI on a rescan. */ 4166 error = device_get_children(dev, &devlist, &devcount); 4167 if (error) 4168 return (error); 4169 if (devcount != 0) { 4170 unchanged = malloc(devcount * sizeof(device_t), M_TEMP, 4171 M_NOWAIT | M_ZERO); 4172 if (unchanged == NULL) { 4173 free(devlist, M_TEMP); 4174 return (ENOMEM); 4175 } 4176 } else 4177 unchanged = NULL; 4178 4179 domain = pcib_get_domain(dev); 4180 busno = pcib_get_bus(dev); 4181 maxslots = PCIB_MAXSLOTS(pcib); 4182 for (s = 0; s <= maxslots; s++) { 4183 /* If function 0 is not present, skip to the next slot. */ 4184 f = 0; 4185 if (REG(PCIR_VENDOR, 2) == 0xffff) 4186 continue; 4187 pcifunchigh = 0; 4188 hdrtype = REG(PCIR_HDRTYPE, 1); 4189 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4190 continue; 4191 if (hdrtype & PCIM_MFDEV) 4192 pcifunchigh = PCIB_MAXFUNCS(pcib); 4193 for (f = 0; f <= pcifunchigh; f++) { 4194 if (REG(PCIR_VENDOR, 2) == 0xffff) 4195 continue; 4196 4197 /* 4198 * Found a valid function. Check if a 4199 * device_t for this device already exists. 4200 */ 4201 for (i = 0; i < devcount; i++) { 4202 child = devlist[i]; 4203 if (child == NULL) 4204 continue; 4205 if (pci_get_slot(child) == s && 4206 pci_get_function(child) == f) { 4207 unchanged[i] = child; 4208 goto next_func; 4209 } 4210 } 4211 4212 pci_identify_function(pcib, dev, domain, busno, s, f); 4213 next_func:; 4214 } 4215 } 4216 4217 /* Remove devices that are no longer present. */ 4218 for (i = 0; i < devcount; i++) { 4219 if (unchanged[i] != NULL) 4220 continue; 4221 device_delete_child(dev, devlist[i]); 4222 } 4223 4224 free(devlist, M_TEMP); 4225 oldcount = devcount; 4226 4227 /* Try to attach the devices just added. */ 4228 error = device_get_children(dev, &devlist, &devcount); 4229 if (error) { 4230 free(unchanged, M_TEMP); 4231 return (error); 4232 } 4233 4234 for (i = 0; i < devcount; i++) { 4235 for (j = 0; j < oldcount; j++) { 4236 if (devlist[i] == unchanged[j]) 4237 goto next_device; 4238 } 4239 4240 device_probe_and_attach(devlist[i]); 4241 next_device:; 4242 } 4243 4244 free(unchanged, M_TEMP); 4245 free(devlist, M_TEMP); 4246 return (0); 4247 #undef REG 4248 } 4249 4250 #ifdef PCI_IOV 4251 device_t 4252 pci_add_iov_child(device_t bus, device_t pf, uint16_t rid, uint16_t vid, 4253 uint16_t did) 4254 { 4255 struct pci_devinfo *vf_dinfo; 4256 device_t pcib; 4257 int busno, slot, func; 4258 4259 pcib = device_get_parent(bus); 4260 4261 PCIB_DECODE_RID(pcib, rid, &busno, &slot, &func); 4262 4263 vf_dinfo = pci_fill_devinfo(pcib, bus, pci_get_domain(pcib), busno, 4264 slot, func, vid, did); 4265 4266 vf_dinfo->cfg.flags |= PCICFG_VF; 4267 pci_add_child(bus, vf_dinfo); 4268 4269 return (vf_dinfo->cfg.dev); 4270 } 4271 4272 device_t 4273 pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid, 4274 uint16_t vid, uint16_t did) 4275 { 4276 4277 return (pci_add_iov_child(bus, pf, rid, vid, did)); 4278 } 4279 #endif 4280 4281 /* 4282 * For PCIe device set Max_Payload_Size to match PCIe root's. 4283 */ 4284 static void 4285 pcie_setup_mps(device_t dev) 4286 { 4287 struct pci_devinfo *dinfo = device_get_ivars(dev); 4288 device_t root; 4289 uint16_t rmps, mmps, mps; 4290 4291 if (dinfo->cfg.pcie.pcie_location == 0) 4292 return; 4293 root = pci_find_pcie_root_port(dev); 4294 if (root == NULL) 4295 return; 4296 /* Check whether the MPS is already configured. */ 4297 rmps = pcie_read_config(root, PCIER_DEVICE_CTL, 2) & 4298 PCIEM_CTL_MAX_PAYLOAD; 4299 mps = pcie_read_config(dev, PCIER_DEVICE_CTL, 2) & 4300 PCIEM_CTL_MAX_PAYLOAD; 4301 if (mps == rmps) 4302 return; 4303 /* Check whether the device is capable of the root's MPS. */ 4304 mmps = (pcie_read_config(dev, PCIER_DEVICE_CAP, 2) & 4305 PCIEM_CAP_MAX_PAYLOAD) << 5; 4306 if (rmps > mmps) { 4307 /* 4308 * The device is unable to handle root's MPS. Limit root. 4309 * XXX: We should traverse through all the tree, applying 4310 * it to all the devices. 4311 */ 4312 pcie_adjust_config(root, PCIER_DEVICE_CTL, 4313 PCIEM_CTL_MAX_PAYLOAD, mmps, 2); 4314 } else { 4315 pcie_adjust_config(dev, PCIER_DEVICE_CTL, 4316 PCIEM_CTL_MAX_PAYLOAD, rmps, 2); 4317 } 4318 } 4319 4320 static void 4321 pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo) 4322 { 4323 int aer; 4324 uint32_t r; 4325 uint16_t r2; 4326 4327 if (dinfo->cfg.pcie.pcie_location != 0 && 4328 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) { 4329 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4330 PCIER_ROOT_CTL, 2); 4331 r2 &= ~(PCIEM_ROOT_CTL_SERR_CORR | 4332 PCIEM_ROOT_CTL_SERR_NONFATAL | PCIEM_ROOT_CTL_SERR_FATAL); 4333 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4334 PCIER_ROOT_CTL, r2, 2); 4335 } 4336 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 4337 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 4338 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 4339 if (r != 0 && bootverbose) { 4340 pci_printf(&dinfo->cfg, 4341 "clearing AER UC 0x%08x -> 0x%08x\n", 4342 r, pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4343 4)); 4344 } 4345 4346 r = pci_read_config(dev, aer + PCIR_AER_UC_MASK, 4); 4347 r &= ~(PCIM_AER_UC_TRAINING_ERROR | 4348 PCIM_AER_UC_DL_PROTOCOL_ERROR | 4349 PCIM_AER_UC_SURPRISE_LINK_DOWN | 4350 PCIM_AER_UC_POISONED_TLP | 4351 PCIM_AER_UC_FC_PROTOCOL_ERROR | 4352 PCIM_AER_UC_COMPLETION_TIMEOUT | 4353 PCIM_AER_UC_COMPLETER_ABORT | 4354 PCIM_AER_UC_UNEXPECTED_COMPLETION | 4355 PCIM_AER_UC_RECEIVER_OVERFLOW | 4356 PCIM_AER_UC_MALFORMED_TLP | 4357 PCIM_AER_UC_ECRC_ERROR | 4358 PCIM_AER_UC_UNSUPPORTED_REQUEST | 4359 PCIM_AER_UC_ACS_VIOLATION | 4360 PCIM_AER_UC_INTERNAL_ERROR | 4361 PCIM_AER_UC_MC_BLOCKED_TLP | 4362 PCIM_AER_UC_ATOMIC_EGRESS_BLK | 4363 PCIM_AER_UC_TLP_PREFIX_BLOCKED); 4364 pci_write_config(dev, aer + PCIR_AER_UC_MASK, r, 4); 4365 4366 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 4367 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 4368 if (r != 0 && bootverbose) { 4369 pci_printf(&dinfo->cfg, 4370 "clearing AER COR 0x%08x -> 0x%08x\n", 4371 r, pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4372 4)); 4373 } 4374 4375 r = pci_read_config(dev, aer + PCIR_AER_COR_MASK, 4); 4376 r &= ~(PCIM_AER_COR_RECEIVER_ERROR | 4377 PCIM_AER_COR_BAD_TLP | 4378 PCIM_AER_COR_BAD_DLLP | 4379 PCIM_AER_COR_REPLAY_ROLLOVER | 4380 PCIM_AER_COR_REPLAY_TIMEOUT | 4381 PCIM_AER_COR_ADVISORY_NF_ERROR | 4382 PCIM_AER_COR_INTERNAL_ERROR | 4383 PCIM_AER_COR_HEADER_LOG_OVFLOW); 4384 pci_write_config(dev, aer + PCIR_AER_COR_MASK, r, 4); 4385 4386 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4387 PCIER_DEVICE_CTL, 2); 4388 r |= PCIEM_CTL_COR_ENABLE | PCIEM_CTL_NFER_ENABLE | 4389 PCIEM_CTL_FER_ENABLE | PCIEM_CTL_URR_ENABLE; 4390 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4391 PCIER_DEVICE_CTL, r, 2); 4392 } 4393 } 4394 4395 void 4396 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 4397 { 4398 device_t dev; 4399 4400 dinfo->cfg.dev = dev = device_add_child(bus, NULL, -1); 4401 device_set_ivars(dev, dinfo); 4402 resource_list_init(&dinfo->resources); 4403 pci_cfg_save(dev, dinfo, 0); 4404 pci_cfg_restore(dev, dinfo); 4405 pci_print_verbose(dinfo); 4406 pci_add_resources(bus, dev, 0, 0); 4407 pcie_setup_mps(dev); 4408 pci_child_added(dinfo->cfg.dev); 4409 4410 if (pci_clear_aer_on_attach) 4411 pci_add_child_clear_aer(dev, dinfo); 4412 4413 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev); 4414 } 4415 4416 void 4417 pci_child_added_method(device_t dev, device_t child) 4418 { 4419 4420 } 4421 4422 static int 4423 pci_probe(device_t dev) 4424 { 4425 4426 device_set_desc(dev, "PCI bus"); 4427 4428 /* Allow other subclasses to override this driver. */ 4429 return (BUS_PROBE_GENERIC); 4430 } 4431 4432 int 4433 pci_attach_common(device_t dev) 4434 { 4435 struct pci_softc *sc; 4436 int busno, domain; 4437 #ifdef PCI_RES_BUS 4438 int rid; 4439 #endif 4440 4441 sc = device_get_softc(dev); 4442 domain = pcib_get_domain(dev); 4443 busno = pcib_get_bus(dev); 4444 #ifdef PCI_RES_BUS 4445 rid = 0; 4446 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, 4447 1, 0); 4448 if (sc->sc_bus == NULL) { 4449 device_printf(dev, "failed to allocate bus number\n"); 4450 return (ENXIO); 4451 } 4452 #endif 4453 if (bootverbose) 4454 device_printf(dev, "domain=%d, physical bus=%d\n", 4455 domain, busno); 4456 sc->sc_dma_tag = bus_get_dma_tag(dev); 4457 return (0); 4458 } 4459 4460 int 4461 pci_attach(device_t dev) 4462 { 4463 int busno, domain, error; 4464 4465 error = pci_attach_common(dev); 4466 if (error) 4467 return (error); 4468 4469 /* 4470 * Since there can be multiple independently numbered PCI 4471 * buses on systems with multiple PCI domains, we can't use 4472 * the unit number to decide which bus we are probing. We ask 4473 * the parent pcib what our domain and bus numbers are. 4474 */ 4475 domain = pcib_get_domain(dev); 4476 busno = pcib_get_bus(dev); 4477 pci_add_children(dev, domain, busno); 4478 return (bus_generic_attach(dev)); 4479 } 4480 4481 int 4482 pci_detach(device_t dev) 4483 { 4484 #ifdef PCI_RES_BUS 4485 struct pci_softc *sc; 4486 #endif 4487 int error; 4488 4489 error = bus_generic_detach(dev); 4490 if (error) 4491 return (error); 4492 #ifdef PCI_RES_BUS 4493 sc = device_get_softc(dev); 4494 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus); 4495 if (error) 4496 return (error); 4497 #endif 4498 return (device_delete_children(dev)); 4499 } 4500 4501 static void 4502 pci_hint_device_unit(device_t dev, device_t child, const char *name, int *unitp) 4503 { 4504 int line, unit; 4505 const char *at; 4506 char me1[24], me2[32]; 4507 uint8_t b, s, f; 4508 uint32_t d; 4509 4510 d = pci_get_domain(child); 4511 b = pci_get_bus(child); 4512 s = pci_get_slot(child); 4513 f = pci_get_function(child); 4514 snprintf(me1, sizeof(me1), "pci%u:%u:%u", b, s, f); 4515 snprintf(me2, sizeof(me2), "pci%u:%u:%u:%u", d, b, s, f); 4516 line = 0; 4517 while (resource_find_dev(&line, name, &unit, "at", NULL) == 0) { 4518 resource_string_value(name, unit, "at", &at); 4519 if (strcmp(at, me1) != 0 && strcmp(at, me2) != 0) 4520 continue; /* No match, try next candidate */ 4521 *unitp = unit; 4522 return; 4523 } 4524 } 4525 4526 static void 4527 pci_set_power_child(device_t dev, device_t child, int state) 4528 { 4529 device_t pcib; 4530 int dstate; 4531 4532 /* 4533 * Set the device to the given state. If the firmware suggests 4534 * a different power state, use it instead. If power management 4535 * is not present, the firmware is responsible for managing 4536 * device power. Skip children who aren't attached since they 4537 * are handled separately. 4538 */ 4539 pcib = device_get_parent(dev); 4540 dstate = state; 4541 if (device_is_attached(child) && 4542 PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0) 4543 pci_set_powerstate(child, dstate); 4544 } 4545 4546 int 4547 pci_suspend_child(device_t dev, device_t child) 4548 { 4549 struct pci_devinfo *dinfo; 4550 struct resource_list_entry *rle; 4551 int error; 4552 4553 dinfo = device_get_ivars(child); 4554 4555 /* 4556 * Save the PCI configuration space for the child and set the 4557 * device in the appropriate power state for this sleep state. 4558 */ 4559 pci_cfg_save(child, dinfo, 0); 4560 4561 /* Suspend devices before potentially powering them down. */ 4562 error = bus_generic_suspend_child(dev, child); 4563 4564 if (error) 4565 return (error); 4566 4567 if (pci_do_power_suspend) { 4568 /* 4569 * Make sure this device's interrupt handler is not invoked 4570 * in the case the device uses a shared interrupt that can 4571 * be raised by some other device. 4572 * This is applicable only to regular (legacy) PCI interrupts 4573 * as MSI/MSI-X interrupts are never shared. 4574 */ 4575 rle = resource_list_find(&dinfo->resources, 4576 SYS_RES_IRQ, 0); 4577 if (rle != NULL && rle->res != NULL) 4578 (void)bus_suspend_intr(child, rle->res); 4579 pci_set_power_child(dev, child, PCI_POWERSTATE_D3); 4580 } 4581 4582 return (0); 4583 } 4584 4585 int 4586 pci_resume_child(device_t dev, device_t child) 4587 { 4588 struct pci_devinfo *dinfo; 4589 struct resource_list_entry *rle; 4590 4591 if (pci_do_power_resume) 4592 pci_set_power_child(dev, child, PCI_POWERSTATE_D0); 4593 4594 dinfo = device_get_ivars(child); 4595 pci_cfg_restore(child, dinfo); 4596 if (!device_is_attached(child)) 4597 pci_cfg_save(child, dinfo, 1); 4598 4599 bus_generic_resume_child(dev, child); 4600 4601 /* 4602 * Allow interrupts only after fully resuming the driver and hardware. 4603 */ 4604 if (pci_do_power_suspend) { 4605 /* See pci_suspend_child for details. */ 4606 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 4607 if (rle != NULL && rle->res != NULL) 4608 (void)bus_resume_intr(child, rle->res); 4609 } 4610 4611 return (0); 4612 } 4613 4614 int 4615 pci_resume(device_t dev) 4616 { 4617 device_t child, *devlist; 4618 int error, i, numdevs; 4619 4620 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 4621 return (error); 4622 4623 /* 4624 * Resume critical devices first, then everything else later. 4625 */ 4626 for (i = 0; i < numdevs; i++) { 4627 child = devlist[i]; 4628 switch (pci_get_class(child)) { 4629 case PCIC_DISPLAY: 4630 case PCIC_MEMORY: 4631 case PCIC_BRIDGE: 4632 case PCIC_BASEPERIPH: 4633 BUS_RESUME_CHILD(dev, child); 4634 break; 4635 } 4636 } 4637 for (i = 0; i < numdevs; i++) { 4638 child = devlist[i]; 4639 switch (pci_get_class(child)) { 4640 case PCIC_DISPLAY: 4641 case PCIC_MEMORY: 4642 case PCIC_BRIDGE: 4643 case PCIC_BASEPERIPH: 4644 break; 4645 default: 4646 BUS_RESUME_CHILD(dev, child); 4647 } 4648 } 4649 free(devlist, M_TEMP); 4650 return (0); 4651 } 4652 4653 static void 4654 pci_load_vendor_data(void) 4655 { 4656 caddr_t data; 4657 void *ptr; 4658 size_t sz; 4659 4660 data = preload_search_by_type("pci_vendor_data"); 4661 if (data != NULL) { 4662 ptr = preload_fetch_addr(data); 4663 sz = preload_fetch_size(data); 4664 if (ptr != NULL && sz != 0) { 4665 pci_vendordata = ptr; 4666 pci_vendordata_size = sz; 4667 /* terminate the database */ 4668 pci_vendordata[pci_vendordata_size] = '\n'; 4669 } 4670 } 4671 } 4672 4673 void 4674 pci_driver_added(device_t dev, driver_t *driver) 4675 { 4676 int numdevs; 4677 device_t *devlist; 4678 device_t child; 4679 struct pci_devinfo *dinfo; 4680 int i; 4681 4682 if (bootverbose) 4683 device_printf(dev, "driver added\n"); 4684 DEVICE_IDENTIFY(driver, dev); 4685 if (device_get_children(dev, &devlist, &numdevs) != 0) 4686 return; 4687 for (i = 0; i < numdevs; i++) { 4688 child = devlist[i]; 4689 if (device_get_state(child) != DS_NOTPRESENT) 4690 continue; 4691 dinfo = device_get_ivars(child); 4692 pci_print_verbose(dinfo); 4693 if (bootverbose) 4694 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); 4695 pci_cfg_restore(child, dinfo); 4696 if (device_probe_and_attach(child) != 0) 4697 pci_child_detached(dev, child); 4698 } 4699 free(devlist, M_TEMP); 4700 } 4701 4702 int 4703 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, 4704 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep) 4705 { 4706 struct pci_devinfo *dinfo; 4707 struct msix_table_entry *mte; 4708 struct msix_vector *mv; 4709 uint64_t addr; 4710 uint32_t data; 4711 void *cookie; 4712 int error, rid; 4713 4714 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr, 4715 arg, &cookie); 4716 if (error) 4717 return (error); 4718 4719 /* If this is not a direct child, just bail out. */ 4720 if (device_get_parent(child) != dev) { 4721 *cookiep = cookie; 4722 return(0); 4723 } 4724 4725 rid = rman_get_rid(irq); 4726 if (rid == 0) { 4727 /* Make sure that INTx is enabled */ 4728 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4729 } else { 4730 /* 4731 * Check to see if the interrupt is MSI or MSI-X. 4732 * Ask our parent to map the MSI and give 4733 * us the address and data register values. 4734 * If we fail for some reason, teardown the 4735 * interrupt handler. 4736 */ 4737 dinfo = device_get_ivars(child); 4738 if (dinfo->cfg.msi.msi_alloc > 0) { 4739 if (dinfo->cfg.msi.msi_addr == 0) { 4740 KASSERT(dinfo->cfg.msi.msi_handlers == 0, 4741 ("MSI has handlers, but vectors not mapped")); 4742 error = PCIB_MAP_MSI(device_get_parent(dev), 4743 child, rman_get_start(irq), &addr, &data); 4744 if (error) 4745 goto bad; 4746 dinfo->cfg.msi.msi_addr = addr; 4747 dinfo->cfg.msi.msi_data = data; 4748 } 4749 if (dinfo->cfg.msi.msi_handlers == 0) 4750 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, 4751 dinfo->cfg.msi.msi_data); 4752 dinfo->cfg.msi.msi_handlers++; 4753 } else { 4754 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4755 ("No MSI or MSI-X interrupts allocated")); 4756 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4757 ("MSI-X index too high")); 4758 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4759 KASSERT(mte->mte_vector != 0, ("no message vector")); 4760 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; 4761 KASSERT(mv->mv_irq == rman_get_start(irq), 4762 ("IRQ mismatch")); 4763 if (mv->mv_address == 0) { 4764 KASSERT(mte->mte_handlers == 0, 4765 ("MSI-X table entry has handlers, but vector not mapped")); 4766 error = PCIB_MAP_MSI(device_get_parent(dev), 4767 child, rman_get_start(irq), &addr, &data); 4768 if (error) 4769 goto bad; 4770 mv->mv_address = addr; 4771 mv->mv_data = data; 4772 } 4773 4774 /* 4775 * The MSIX table entry must be made valid by 4776 * incrementing the mte_handlers before 4777 * calling pci_enable_msix() and 4778 * pci_resume_msix(). Else the MSIX rewrite 4779 * table quirk will not work as expected. 4780 */ 4781 mte->mte_handlers++; 4782 if (mte->mte_handlers == 1) { 4783 pci_enable_msix(child, rid - 1, mv->mv_address, 4784 mv->mv_data); 4785 pci_unmask_msix(child, rid - 1); 4786 } 4787 } 4788 4789 /* 4790 * Make sure that INTx is disabled if we are using MSI/MSI-X, 4791 * unless the device is affected by PCI_QUIRK_MSI_INTX_BUG, 4792 * in which case we "enable" INTx so MSI/MSI-X actually works. 4793 */ 4794 if (!pci_has_quirk(pci_get_devid(child), 4795 PCI_QUIRK_MSI_INTX_BUG)) 4796 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4797 else 4798 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4799 bad: 4800 if (error) { 4801 (void)bus_generic_teardown_intr(dev, child, irq, 4802 cookie); 4803 return (error); 4804 } 4805 } 4806 *cookiep = cookie; 4807 return (0); 4808 } 4809 4810 int 4811 pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 4812 void *cookie) 4813 { 4814 struct msix_table_entry *mte; 4815 struct resource_list_entry *rle; 4816 struct pci_devinfo *dinfo; 4817 int error, rid; 4818 4819 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE)) 4820 return (EINVAL); 4821 4822 /* If this isn't a direct child, just bail out */ 4823 if (device_get_parent(child) != dev) 4824 return(bus_generic_teardown_intr(dev, child, irq, cookie)); 4825 4826 rid = rman_get_rid(irq); 4827 if (rid == 0) { 4828 /* Mask INTx */ 4829 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4830 } else { 4831 /* 4832 * Check to see if the interrupt is MSI or MSI-X. If so, 4833 * decrement the appropriate handlers count and mask the 4834 * MSI-X message, or disable MSI messages if the count 4835 * drops to 0. 4836 */ 4837 dinfo = device_get_ivars(child); 4838 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); 4839 if (rle->res != irq) 4840 return (EINVAL); 4841 if (dinfo->cfg.msi.msi_alloc > 0) { 4842 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, 4843 ("MSI-X index too high")); 4844 if (dinfo->cfg.msi.msi_handlers == 0) 4845 return (EINVAL); 4846 dinfo->cfg.msi.msi_handlers--; 4847 if (dinfo->cfg.msi.msi_handlers == 0) 4848 pci_disable_msi(child); 4849 } else { 4850 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4851 ("No MSI or MSI-X interrupts allocated")); 4852 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4853 ("MSI-X index too high")); 4854 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4855 if (mte->mte_handlers == 0) 4856 return (EINVAL); 4857 mte->mte_handlers--; 4858 if (mte->mte_handlers == 0) 4859 pci_mask_msix(child, rid - 1); 4860 } 4861 } 4862 error = bus_generic_teardown_intr(dev, child, irq, cookie); 4863 if (rid > 0) 4864 KASSERT(error == 0, 4865 ("%s: generic teardown failed for MSI/MSI-X", __func__)); 4866 return (error); 4867 } 4868 4869 int 4870 pci_print_child(device_t dev, device_t child) 4871 { 4872 struct pci_devinfo *dinfo; 4873 struct resource_list *rl; 4874 int retval = 0; 4875 4876 dinfo = device_get_ivars(child); 4877 rl = &dinfo->resources; 4878 4879 retval += bus_print_child_header(dev, child); 4880 4881 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#jx"); 4882 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 4883 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 4884 if (device_get_flags(dev)) 4885 retval += printf(" flags %#x", device_get_flags(dev)); 4886 4887 retval += printf(" at device %d.%d", pci_get_slot(child), 4888 pci_get_function(child)); 4889 4890 retval += bus_print_child_domain(dev, child); 4891 retval += bus_print_child_footer(dev, child); 4892 4893 return (retval); 4894 } 4895 4896 static const struct 4897 { 4898 int class; 4899 int subclass; 4900 int report; /* 0 = bootverbose, 1 = always */ 4901 const char *desc; 4902 } pci_nomatch_tab[] = { 4903 {PCIC_OLD, -1, 1, "old"}, 4904 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"}, 4905 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"}, 4906 {PCIC_STORAGE, -1, 1, "mass storage"}, 4907 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"}, 4908 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"}, 4909 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"}, 4910 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"}, 4911 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"}, 4912 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"}, 4913 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"}, 4914 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"}, 4915 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"}, 4916 {PCIC_NETWORK, -1, 1, "network"}, 4917 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"}, 4918 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"}, 4919 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"}, 4920 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"}, 4921 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"}, 4922 {PCIC_DISPLAY, -1, 1, "display"}, 4923 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"}, 4924 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"}, 4925 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"}, 4926 {PCIC_MULTIMEDIA, -1, 1, "multimedia"}, 4927 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"}, 4928 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"}, 4929 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"}, 4930 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"}, 4931 {PCIC_MEMORY, -1, 1, "memory"}, 4932 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"}, 4933 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"}, 4934 {PCIC_BRIDGE, -1, 1, "bridge"}, 4935 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"}, 4936 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"}, 4937 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"}, 4938 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"}, 4939 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"}, 4940 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"}, 4941 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"}, 4942 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"}, 4943 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"}, 4944 {PCIC_SIMPLECOMM, -1, 1, "simple comms"}, 4945 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */ 4946 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"}, 4947 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"}, 4948 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"}, 4949 {PCIC_BASEPERIPH, -1, 0, "base peripheral"}, 4950 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"}, 4951 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"}, 4952 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"}, 4953 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"}, 4954 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"}, 4955 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"}, 4956 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"}, 4957 {PCIC_INPUTDEV, -1, 1, "input device"}, 4958 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"}, 4959 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"}, 4960 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"}, 4961 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"}, 4962 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"}, 4963 {PCIC_DOCKING, -1, 1, "docking station"}, 4964 {PCIC_PROCESSOR, -1, 1, "processor"}, 4965 {PCIC_SERIALBUS, -1, 1, "serial bus"}, 4966 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"}, 4967 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"}, 4968 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"}, 4969 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"}, 4970 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"}, 4971 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"}, 4972 {PCIC_WIRELESS, -1, 1, "wireless controller"}, 4973 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"}, 4974 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"}, 4975 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"}, 4976 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"}, 4977 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"}, 4978 {PCIC_SATCOM, -1, 1, "satellite communication"}, 4979 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"}, 4980 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"}, 4981 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"}, 4982 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"}, 4983 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"}, 4984 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"}, 4985 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"}, 4986 {PCIC_DASP, -1, 0, "dasp"}, 4987 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"}, 4988 {PCIC_DASP, PCIS_DASP_PERFCNTRS, 1, "performance counters"}, 4989 {PCIC_DASP, PCIS_DASP_COMM_SYNC, 1, "communication synchronizer"}, 4990 {PCIC_DASP, PCIS_DASP_MGMT_CARD, 1, "signal processing management"}, 4991 {0, 0, 0, NULL} 4992 }; 4993 4994 void 4995 pci_probe_nomatch(device_t dev, device_t child) 4996 { 4997 int i, report; 4998 const char *cp, *scp; 4999 char *device; 5000 5001 /* 5002 * Look for a listing for this device in a loaded device database. 5003 */ 5004 report = 1; 5005 if ((device = pci_describe_device(child)) != NULL) { 5006 device_printf(dev, "<%s>", device); 5007 free(device, M_DEVBUF); 5008 } else { 5009 /* 5010 * Scan the class/subclass descriptions for a general 5011 * description. 5012 */ 5013 cp = "unknown"; 5014 scp = NULL; 5015 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 5016 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 5017 if (pci_nomatch_tab[i].subclass == -1) { 5018 cp = pci_nomatch_tab[i].desc; 5019 report = pci_nomatch_tab[i].report; 5020 } else if (pci_nomatch_tab[i].subclass == 5021 pci_get_subclass(child)) { 5022 scp = pci_nomatch_tab[i].desc; 5023 report = pci_nomatch_tab[i].report; 5024 } 5025 } 5026 } 5027 if (report || bootverbose) { 5028 device_printf(dev, "<%s%s%s>", 5029 cp ? cp : "", 5030 ((cp != NULL) && (scp != NULL)) ? ", " : "", 5031 scp ? scp : ""); 5032 } 5033 } 5034 if (report || bootverbose) { 5035 printf(" at device %d.%d (no driver attached)\n", 5036 pci_get_slot(child), pci_get_function(child)); 5037 } 5038 pci_cfg_save(child, device_get_ivars(child), 1); 5039 } 5040 5041 void 5042 pci_child_detached(device_t dev, device_t child) 5043 { 5044 struct pci_devinfo *dinfo; 5045 struct resource_list *rl; 5046 5047 dinfo = device_get_ivars(child); 5048 rl = &dinfo->resources; 5049 5050 /* 5051 * Have to deallocate IRQs before releasing any MSI messages and 5052 * have to release MSI messages before deallocating any memory 5053 * BARs. 5054 */ 5055 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0) 5056 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); 5057 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { 5058 if (dinfo->cfg.msi.msi_alloc != 0) 5059 pci_printf(&dinfo->cfg, "Device leaked %d MSI " 5060 "vectors\n", dinfo->cfg.msi.msi_alloc); 5061 else 5062 pci_printf(&dinfo->cfg, "Device leaked %d MSI-X " 5063 "vectors\n", dinfo->cfg.msix.msix_alloc); 5064 (void)pci_release_msi(child); 5065 } 5066 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0) 5067 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); 5068 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0) 5069 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); 5070 #ifdef PCI_RES_BUS 5071 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0) 5072 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); 5073 #endif 5074 5075 pci_cfg_save(child, dinfo, 1); 5076 } 5077 5078 /* 5079 * Parse the PCI device database, if loaded, and return a pointer to a 5080 * description of the device. 5081 * 5082 * The database is flat text formatted as follows: 5083 * 5084 * Any line not in a valid format is ignored. 5085 * Lines are terminated with newline '\n' characters. 5086 * 5087 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 5088 * the vendor name. 5089 * 5090 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 5091 * - devices cannot be listed without a corresponding VENDOR line. 5092 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 5093 * another TAB, then the device name. 5094 */ 5095 5096 /* 5097 * Assuming (ptr) points to the beginning of a line in the database, 5098 * return the vendor or device and description of the next entry. 5099 * The value of (vendor) or (device) inappropriate for the entry type 5100 * is set to -1. Returns nonzero at the end of the database. 5101 * 5102 * Note that this is slightly unrobust in the face of corrupt data; 5103 * we attempt to safeguard against this by spamming the end of the 5104 * database with a newline when we initialise. 5105 */ 5106 static int 5107 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 5108 { 5109 char *cp = *ptr; 5110 int left; 5111 5112 *device = -1; 5113 *vendor = -1; 5114 **desc = '\0'; 5115 for (;;) { 5116 left = pci_vendordata_size - (cp - pci_vendordata); 5117 if (left <= 0) { 5118 *ptr = cp; 5119 return(1); 5120 } 5121 5122 /* vendor entry? */ 5123 if (*cp != '\t' && 5124 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 5125 break; 5126 /* device entry? */ 5127 if (*cp == '\t' && 5128 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 5129 break; 5130 5131 /* skip to next line */ 5132 while (*cp != '\n' && left > 0) { 5133 cp++; 5134 left--; 5135 } 5136 if (*cp == '\n') { 5137 cp++; 5138 left--; 5139 } 5140 } 5141 /* skip to next line */ 5142 while (*cp != '\n' && left > 0) { 5143 cp++; 5144 left--; 5145 } 5146 if (*cp == '\n' && left > 0) 5147 cp++; 5148 *ptr = cp; 5149 return(0); 5150 } 5151 5152 static char * 5153 pci_describe_device(device_t dev) 5154 { 5155 int vendor, device; 5156 char *desc, *vp, *dp, *line; 5157 5158 desc = vp = dp = NULL; 5159 5160 /* 5161 * If we have no vendor data, we can't do anything. 5162 */ 5163 if (pci_vendordata == NULL) 5164 goto out; 5165 5166 /* 5167 * Scan the vendor data looking for this device 5168 */ 5169 line = pci_vendordata; 5170 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5171 goto out; 5172 for (;;) { 5173 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 5174 goto out; 5175 if (vendor == pci_get_vendor(dev)) 5176 break; 5177 } 5178 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5179 goto out; 5180 for (;;) { 5181 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 5182 *dp = 0; 5183 break; 5184 } 5185 if (vendor != -1) { 5186 *dp = 0; 5187 break; 5188 } 5189 if (device == pci_get_device(dev)) 5190 break; 5191 } 5192 if (dp[0] == '\0') 5193 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 5194 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 5195 NULL) 5196 sprintf(desc, "%s, %s", vp, dp); 5197 out: 5198 if (vp != NULL) 5199 free(vp, M_DEVBUF); 5200 if (dp != NULL) 5201 free(dp, M_DEVBUF); 5202 return(desc); 5203 } 5204 5205 int 5206 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 5207 { 5208 struct pci_devinfo *dinfo; 5209 pcicfgregs *cfg; 5210 5211 dinfo = device_get_ivars(child); 5212 cfg = &dinfo->cfg; 5213 5214 switch (which) { 5215 case PCI_IVAR_ETHADDR: 5216 /* 5217 * The generic accessor doesn't deal with failure, so 5218 * we set the return value, then return an error. 5219 */ 5220 *((uint8_t **) result) = NULL; 5221 return (EINVAL); 5222 case PCI_IVAR_SUBVENDOR: 5223 *result = cfg->subvendor; 5224 break; 5225 case PCI_IVAR_SUBDEVICE: 5226 *result = cfg->subdevice; 5227 break; 5228 case PCI_IVAR_VENDOR: 5229 *result = cfg->vendor; 5230 break; 5231 case PCI_IVAR_DEVICE: 5232 *result = cfg->device; 5233 break; 5234 case PCI_IVAR_DEVID: 5235 *result = (cfg->device << 16) | cfg->vendor; 5236 break; 5237 case PCI_IVAR_CLASS: 5238 *result = cfg->baseclass; 5239 break; 5240 case PCI_IVAR_SUBCLASS: 5241 *result = cfg->subclass; 5242 break; 5243 case PCI_IVAR_PROGIF: 5244 *result = cfg->progif; 5245 break; 5246 case PCI_IVAR_REVID: 5247 *result = cfg->revid; 5248 break; 5249 case PCI_IVAR_INTPIN: 5250 *result = cfg->intpin; 5251 break; 5252 case PCI_IVAR_IRQ: 5253 *result = cfg->intline; 5254 break; 5255 case PCI_IVAR_DOMAIN: 5256 *result = cfg->domain; 5257 break; 5258 case PCI_IVAR_BUS: 5259 *result = cfg->bus; 5260 break; 5261 case PCI_IVAR_SLOT: 5262 *result = cfg->slot; 5263 break; 5264 case PCI_IVAR_FUNCTION: 5265 *result = cfg->func; 5266 break; 5267 case PCI_IVAR_CMDREG: 5268 *result = cfg->cmdreg; 5269 break; 5270 case PCI_IVAR_CACHELNSZ: 5271 *result = cfg->cachelnsz; 5272 break; 5273 case PCI_IVAR_MINGNT: 5274 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5275 *result = -1; 5276 return (EINVAL); 5277 } 5278 *result = cfg->mingnt; 5279 break; 5280 case PCI_IVAR_MAXLAT: 5281 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5282 *result = -1; 5283 return (EINVAL); 5284 } 5285 *result = cfg->maxlat; 5286 break; 5287 case PCI_IVAR_LATTIMER: 5288 *result = cfg->lattimer; 5289 break; 5290 default: 5291 return (ENOENT); 5292 } 5293 return (0); 5294 } 5295 5296 int 5297 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 5298 { 5299 struct pci_devinfo *dinfo; 5300 5301 dinfo = device_get_ivars(child); 5302 5303 switch (which) { 5304 case PCI_IVAR_INTPIN: 5305 dinfo->cfg.intpin = value; 5306 return (0); 5307 case PCI_IVAR_ETHADDR: 5308 case PCI_IVAR_SUBVENDOR: 5309 case PCI_IVAR_SUBDEVICE: 5310 case PCI_IVAR_VENDOR: 5311 case PCI_IVAR_DEVICE: 5312 case PCI_IVAR_DEVID: 5313 case PCI_IVAR_CLASS: 5314 case PCI_IVAR_SUBCLASS: 5315 case PCI_IVAR_PROGIF: 5316 case PCI_IVAR_REVID: 5317 case PCI_IVAR_IRQ: 5318 case PCI_IVAR_DOMAIN: 5319 case PCI_IVAR_BUS: 5320 case PCI_IVAR_SLOT: 5321 case PCI_IVAR_FUNCTION: 5322 return (EINVAL); /* disallow for now */ 5323 5324 default: 5325 return (ENOENT); 5326 } 5327 } 5328 5329 #include "opt_ddb.h" 5330 #ifdef DDB 5331 #include <ddb/ddb.h> 5332 #include <sys/cons.h> 5333 5334 /* 5335 * List resources based on pci map registers, used for within ddb 5336 */ 5337 5338 DB_SHOW_COMMAND(pciregs, db_pci_dump) 5339 { 5340 struct pci_devinfo *dinfo; 5341 struct devlist *devlist_head; 5342 struct pci_conf *p; 5343 const char *name; 5344 int i, error, none_count; 5345 5346 none_count = 0; 5347 /* get the head of the device queue */ 5348 devlist_head = &pci_devq; 5349 5350 /* 5351 * Go through the list of devices and print out devices 5352 */ 5353 for (error = 0, i = 0, 5354 dinfo = STAILQ_FIRST(devlist_head); 5355 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 5356 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 5357 /* Populate pd_name and pd_unit */ 5358 name = NULL; 5359 if (dinfo->cfg.dev) 5360 name = device_get_name(dinfo->cfg.dev); 5361 5362 p = &dinfo->conf; 5363 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x " 5364 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 5365 (name && *name) ? name : "none", 5366 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 5367 none_count++, 5368 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, 5369 p->pc_sel.pc_func, (p->pc_class << 16) | 5370 (p->pc_subclass << 8) | p->pc_progif, 5371 (p->pc_subdevice << 16) | p->pc_subvendor, 5372 (p->pc_device << 16) | p->pc_vendor, 5373 p->pc_revid, p->pc_hdr); 5374 } 5375 } 5376 #endif /* DDB */ 5377 5378 struct resource * 5379 pci_reserve_map(device_t dev, device_t child, int type, int *rid, 5380 rman_res_t start, rman_res_t end, rman_res_t count, u_int num, 5381 u_int flags) 5382 { 5383 struct pci_devinfo *dinfo = device_get_ivars(child); 5384 struct resource_list *rl = &dinfo->resources; 5385 struct resource *res; 5386 struct pci_map *pm; 5387 uint16_t cmd; 5388 pci_addr_t map, testval; 5389 int mapsize; 5390 5391 res = NULL; 5392 5393 /* If rid is managed by EA, ignore it */ 5394 if (pci_ea_is_enabled(child, *rid)) 5395 goto out; 5396 5397 pm = pci_find_bar(child, *rid); 5398 if (pm != NULL) { 5399 /* This is a BAR that we failed to allocate earlier. */ 5400 mapsize = pm->pm_size; 5401 map = pm->pm_value; 5402 } else { 5403 /* 5404 * Weed out the bogons, and figure out how large the 5405 * BAR/map is. BARs that read back 0 here are bogus 5406 * and unimplemented. Note: atapci in legacy mode are 5407 * special and handled elsewhere in the code. If you 5408 * have a atapci device in legacy mode and it fails 5409 * here, that other code is broken. 5410 */ 5411 pci_read_bar(child, *rid, &map, &testval, NULL); 5412 5413 /* 5414 * Determine the size of the BAR and ignore BARs with a size 5415 * of 0. Device ROM BARs use a different mask value. 5416 */ 5417 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) 5418 mapsize = pci_romsize(testval); 5419 else 5420 mapsize = pci_mapsize(testval); 5421 if (mapsize == 0) 5422 goto out; 5423 pm = pci_add_bar(child, *rid, map, mapsize); 5424 } 5425 5426 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { 5427 if (type != SYS_RES_MEMORY) { 5428 if (bootverbose) 5429 device_printf(dev, 5430 "child %s requested type %d for rid %#x," 5431 " but the BAR says it is an memio\n", 5432 device_get_nameunit(child), type, *rid); 5433 goto out; 5434 } 5435 } else { 5436 if (type != SYS_RES_IOPORT) { 5437 if (bootverbose) 5438 device_printf(dev, 5439 "child %s requested type %d for rid %#x," 5440 " but the BAR says it is an ioport\n", 5441 device_get_nameunit(child), type, *rid); 5442 goto out; 5443 } 5444 } 5445 5446 /* 5447 * For real BARs, we need to override the size that 5448 * the driver requests, because that's what the BAR 5449 * actually uses and we would otherwise have a 5450 * situation where we might allocate the excess to 5451 * another driver, which won't work. 5452 */ 5453 count = ((pci_addr_t)1 << mapsize) * num; 5454 if (RF_ALIGNMENT(flags) < mapsize) 5455 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 5456 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH)) 5457 flags |= RF_PREFETCHABLE; 5458 5459 /* 5460 * Allocate enough resource, and then write back the 5461 * appropriate BAR for that resource. 5462 */ 5463 resource_list_add(rl, type, *rid, start, end, count); 5464 res = resource_list_reserve(rl, dev, child, type, rid, start, end, 5465 count, flags & ~RF_ACTIVE); 5466 if (res == NULL) { 5467 resource_list_delete(rl, type, *rid); 5468 device_printf(child, 5469 "%#jx bytes of rid %#x res %d failed (%#jx, %#jx).\n", 5470 count, *rid, type, start, end); 5471 goto out; 5472 } 5473 if (bootverbose) 5474 device_printf(child, 5475 "Lazy allocation of %#jx bytes rid %#x type %d at %#jx\n", 5476 count, *rid, type, rman_get_start(res)); 5477 5478 /* Disable decoding via the CMD register before updating the BAR */ 5479 cmd = pci_read_config(child, PCIR_COMMAND, 2); 5480 pci_write_config(child, PCIR_COMMAND, 5481 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 5482 5483 map = rman_get_start(res); 5484 pci_write_bar(child, pm, map); 5485 5486 /* Restore the original value of the CMD register */ 5487 pci_write_config(child, PCIR_COMMAND, cmd, 2); 5488 out: 5489 return (res); 5490 } 5491 5492 struct resource * 5493 pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid, 5494 rman_res_t start, rman_res_t end, rman_res_t count, u_long num, 5495 u_int flags) 5496 { 5497 struct pci_devinfo *dinfo; 5498 struct resource_list *rl; 5499 struct resource_list_entry *rle; 5500 struct resource *res; 5501 pcicfgregs *cfg; 5502 5503 /* 5504 * Perform lazy resource allocation 5505 */ 5506 dinfo = device_get_ivars(child); 5507 rl = &dinfo->resources; 5508 cfg = &dinfo->cfg; 5509 switch (type) { 5510 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 5511 case PCI_RES_BUS: 5512 return (pci_alloc_secbus(dev, child, rid, start, end, count, 5513 flags)); 5514 #endif 5515 case SYS_RES_IRQ: 5516 /* 5517 * Can't alloc legacy interrupt once MSI messages have 5518 * been allocated. 5519 */ 5520 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 5521 cfg->msix.msix_alloc > 0)) 5522 return (NULL); 5523 5524 /* 5525 * If the child device doesn't have an interrupt 5526 * routed and is deserving of an interrupt, try to 5527 * assign it one. 5528 */ 5529 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 5530 (cfg->intpin != 0)) 5531 pci_assign_interrupt(dev, child, 0); 5532 break; 5533 case SYS_RES_IOPORT: 5534 case SYS_RES_MEMORY: 5535 #ifdef NEW_PCIB 5536 /* 5537 * PCI-PCI bridge I/O window resources are not BARs. 5538 * For those allocations just pass the request up the 5539 * tree. 5540 */ 5541 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { 5542 switch (*rid) { 5543 case PCIR_IOBASEL_1: 5544 case PCIR_MEMBASE_1: 5545 case PCIR_PMBASEL_1: 5546 /* 5547 * XXX: Should we bother creating a resource 5548 * list entry? 5549 */ 5550 return (bus_generic_alloc_resource(dev, child, 5551 type, rid, start, end, count, flags)); 5552 } 5553 } 5554 #endif 5555 /* Reserve resources for this BAR if needed. */ 5556 rle = resource_list_find(rl, type, *rid); 5557 if (rle == NULL) { 5558 res = pci_reserve_map(dev, child, type, rid, start, end, 5559 count, num, flags); 5560 if (res == NULL) 5561 return (NULL); 5562 } 5563 } 5564 return (resource_list_alloc(rl, dev, child, type, rid, 5565 start, end, count, flags)); 5566 } 5567 5568 struct resource * 5569 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 5570 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 5571 { 5572 #ifdef PCI_IOV 5573 struct pci_devinfo *dinfo; 5574 #endif 5575 5576 if (device_get_parent(child) != dev) 5577 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 5578 type, rid, start, end, count, flags)); 5579 5580 #ifdef PCI_IOV 5581 dinfo = device_get_ivars(child); 5582 if (dinfo->cfg.flags & PCICFG_VF) { 5583 switch (type) { 5584 /* VFs can't have I/O BARs. */ 5585 case SYS_RES_IOPORT: 5586 return (NULL); 5587 case SYS_RES_MEMORY: 5588 return (pci_vf_alloc_mem_resource(dev, child, rid, 5589 start, end, count, flags)); 5590 } 5591 5592 /* Fall through for other types of resource allocations. */ 5593 } 5594 #endif 5595 5596 return (pci_alloc_multi_resource(dev, child, type, rid, start, end, 5597 count, 1, flags)); 5598 } 5599 5600 int 5601 pci_release_resource(device_t dev, device_t child, int type, int rid, 5602 struct resource *r) 5603 { 5604 struct pci_devinfo *dinfo; 5605 struct resource_list *rl; 5606 pcicfgregs *cfg; 5607 5608 if (device_get_parent(child) != dev) 5609 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 5610 type, rid, r)); 5611 5612 dinfo = device_get_ivars(child); 5613 cfg = &dinfo->cfg; 5614 5615 #ifdef PCI_IOV 5616 if (dinfo->cfg.flags & PCICFG_VF) { 5617 switch (type) { 5618 /* VFs can't have I/O BARs. */ 5619 case SYS_RES_IOPORT: 5620 return (EDOOFUS); 5621 case SYS_RES_MEMORY: 5622 return (pci_vf_release_mem_resource(dev, child, rid, 5623 r)); 5624 } 5625 5626 /* Fall through for other types of resource allocations. */ 5627 } 5628 #endif 5629 5630 #ifdef NEW_PCIB 5631 /* 5632 * PCI-PCI bridge I/O window resources are not BARs. For 5633 * those allocations just pass the request up the tree. 5634 */ 5635 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && 5636 (type == SYS_RES_IOPORT || type == SYS_RES_MEMORY)) { 5637 switch (rid) { 5638 case PCIR_IOBASEL_1: 5639 case PCIR_MEMBASE_1: 5640 case PCIR_PMBASEL_1: 5641 return (bus_generic_release_resource(dev, child, type, 5642 rid, r)); 5643 } 5644 } 5645 #endif 5646 5647 rl = &dinfo->resources; 5648 return (resource_list_release(rl, dev, child, type, rid, r)); 5649 } 5650 5651 int 5652 pci_activate_resource(device_t dev, device_t child, int type, int rid, 5653 struct resource *r) 5654 { 5655 struct pci_devinfo *dinfo; 5656 int error; 5657 5658 error = bus_generic_activate_resource(dev, child, type, rid, r); 5659 if (error) 5660 return (error); 5661 5662 /* Enable decoding in the command register when activating BARs. */ 5663 if (device_get_parent(child) == dev) { 5664 /* Device ROMs need their decoding explicitly enabled. */ 5665 dinfo = device_get_ivars(child); 5666 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5667 pci_write_bar(child, pci_find_bar(child, rid), 5668 rman_get_start(r) | PCIM_BIOS_ENABLE); 5669 switch (type) { 5670 case SYS_RES_IOPORT: 5671 case SYS_RES_MEMORY: 5672 error = PCI_ENABLE_IO(dev, child, type); 5673 break; 5674 } 5675 } 5676 return (error); 5677 } 5678 5679 int 5680 pci_deactivate_resource(device_t dev, device_t child, int type, 5681 int rid, struct resource *r) 5682 { 5683 struct pci_devinfo *dinfo; 5684 int error; 5685 5686 error = bus_generic_deactivate_resource(dev, child, type, rid, r); 5687 if (error) 5688 return (error); 5689 5690 /* Disable decoding for device ROMs. */ 5691 if (device_get_parent(child) == dev) { 5692 dinfo = device_get_ivars(child); 5693 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5694 pci_write_bar(child, pci_find_bar(child, rid), 5695 rman_get_start(r)); 5696 } 5697 return (0); 5698 } 5699 5700 void 5701 pci_child_deleted(device_t dev, device_t child) 5702 { 5703 struct resource_list_entry *rle; 5704 struct resource_list *rl; 5705 struct pci_devinfo *dinfo; 5706 5707 dinfo = device_get_ivars(child); 5708 rl = &dinfo->resources; 5709 5710 EVENTHANDLER_INVOKE(pci_delete_device, child); 5711 5712 /* Turn off access to resources we're about to free */ 5713 if (bus_child_present(child) != 0) { 5714 pci_write_config(child, PCIR_COMMAND, pci_read_config(child, 5715 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2); 5716 5717 pci_disable_busmaster(child); 5718 } 5719 5720 /* Free all allocated resources */ 5721 STAILQ_FOREACH(rle, rl, link) { 5722 if (rle->res) { 5723 if (rman_get_flags(rle->res) & RF_ACTIVE || 5724 resource_list_busy(rl, rle->type, rle->rid)) { 5725 pci_printf(&dinfo->cfg, 5726 "Resource still owned, oops. " 5727 "(type=%d, rid=%d, addr=%lx)\n", 5728 rle->type, rle->rid, 5729 rman_get_start(rle->res)); 5730 bus_release_resource(child, rle->type, rle->rid, 5731 rle->res); 5732 } 5733 resource_list_unreserve(rl, dev, child, rle->type, 5734 rle->rid); 5735 } 5736 } 5737 resource_list_free(rl); 5738 5739 pci_freecfg(dinfo); 5740 } 5741 5742 void 5743 pci_delete_resource(device_t dev, device_t child, int type, int rid) 5744 { 5745 struct pci_devinfo *dinfo; 5746 struct resource_list *rl; 5747 struct resource_list_entry *rle; 5748 5749 if (device_get_parent(child) != dev) 5750 return; 5751 5752 dinfo = device_get_ivars(child); 5753 rl = &dinfo->resources; 5754 rle = resource_list_find(rl, type, rid); 5755 if (rle == NULL) 5756 return; 5757 5758 if (rle->res) { 5759 if (rman_get_flags(rle->res) & RF_ACTIVE || 5760 resource_list_busy(rl, type, rid)) { 5761 device_printf(dev, "delete_resource: " 5762 "Resource still owned by child, oops. " 5763 "(type=%d, rid=%d, addr=%jx)\n", 5764 type, rid, rman_get_start(rle->res)); 5765 return; 5766 } 5767 resource_list_unreserve(rl, dev, child, type, rid); 5768 } 5769 resource_list_delete(rl, type, rid); 5770 } 5771 5772 struct resource_list * 5773 pci_get_resource_list (device_t dev, device_t child) 5774 { 5775 struct pci_devinfo *dinfo = device_get_ivars(child); 5776 5777 return (&dinfo->resources); 5778 } 5779 5780 #ifdef IOMMU 5781 bus_dma_tag_t 5782 pci_get_dma_tag(device_t bus, device_t dev) 5783 { 5784 bus_dma_tag_t tag; 5785 struct pci_softc *sc; 5786 5787 if (device_get_parent(dev) == bus) { 5788 /* try iommu and return if it works */ 5789 tag = iommu_get_dma_tag(bus, dev); 5790 } else 5791 tag = NULL; 5792 if (tag == NULL) { 5793 sc = device_get_softc(bus); 5794 tag = sc->sc_dma_tag; 5795 } 5796 return (tag); 5797 } 5798 #else 5799 bus_dma_tag_t 5800 pci_get_dma_tag(device_t bus, device_t dev) 5801 { 5802 struct pci_softc *sc = device_get_softc(bus); 5803 5804 return (sc->sc_dma_tag); 5805 } 5806 #endif 5807 5808 uint32_t 5809 pci_read_config_method(device_t dev, device_t child, int reg, int width) 5810 { 5811 struct pci_devinfo *dinfo = device_get_ivars(child); 5812 pcicfgregs *cfg = &dinfo->cfg; 5813 5814 #ifdef PCI_IOV 5815 /* 5816 * SR-IOV VFs don't implement the VID or DID registers, so we have to 5817 * emulate them here. 5818 */ 5819 if (cfg->flags & PCICFG_VF) { 5820 if (reg == PCIR_VENDOR) { 5821 switch (width) { 5822 case 4: 5823 return (cfg->device << 16 | cfg->vendor); 5824 case 2: 5825 return (cfg->vendor); 5826 case 1: 5827 return (cfg->vendor & 0xff); 5828 default: 5829 return (0xffffffff); 5830 } 5831 } else if (reg == PCIR_DEVICE) { 5832 switch (width) { 5833 /* Note that an unaligned 4-byte read is an error. */ 5834 case 2: 5835 return (cfg->device); 5836 case 1: 5837 return (cfg->device & 0xff); 5838 default: 5839 return (0xffffffff); 5840 } 5841 } 5842 } 5843 #endif 5844 5845 return (PCIB_READ_CONFIG(device_get_parent(dev), 5846 cfg->bus, cfg->slot, cfg->func, reg, width)); 5847 } 5848 5849 void 5850 pci_write_config_method(device_t dev, device_t child, int reg, 5851 uint32_t val, int width) 5852 { 5853 struct pci_devinfo *dinfo = device_get_ivars(child); 5854 pcicfgregs *cfg = &dinfo->cfg; 5855 5856 PCIB_WRITE_CONFIG(device_get_parent(dev), 5857 cfg->bus, cfg->slot, cfg->func, reg, val, width); 5858 } 5859 5860 int 5861 pci_child_location_method(device_t dev, device_t child, struct sbuf *sb) 5862 { 5863 5864 sbuf_printf(sb, "slot=%d function=%d dbsf=pci%d:%d:%d:%d", 5865 pci_get_slot(child), pci_get_function(child), pci_get_domain(child), 5866 pci_get_bus(child), pci_get_slot(child), pci_get_function(child)); 5867 return (0); 5868 } 5869 5870 int 5871 pci_child_pnpinfo_method(device_t dev, device_t child, struct sbuf *sb) 5872 { 5873 struct pci_devinfo *dinfo; 5874 pcicfgregs *cfg; 5875 5876 dinfo = device_get_ivars(child); 5877 cfg = &dinfo->cfg; 5878 sbuf_printf(sb, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 5879 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 5880 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 5881 cfg->progif); 5882 return (0); 5883 } 5884 5885 int 5886 pci_assign_interrupt_method(device_t dev, device_t child) 5887 { 5888 struct pci_devinfo *dinfo = device_get_ivars(child); 5889 pcicfgregs *cfg = &dinfo->cfg; 5890 5891 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 5892 cfg->intpin)); 5893 } 5894 5895 static void 5896 pci_lookup(void *arg, const char *name, device_t *dev) 5897 { 5898 long val; 5899 char *end; 5900 int domain, bus, slot, func; 5901 5902 if (*dev != NULL) 5903 return; 5904 5905 /* 5906 * Accept pciconf-style selectors of either pciD:B:S:F or 5907 * pciB:S:F. In the latter case, the domain is assumed to 5908 * be zero. 5909 */ 5910 if (strncmp(name, "pci", 3) != 0) 5911 return; 5912 val = strtol(name + 3, &end, 10); 5913 if (val < 0 || val > INT_MAX || *end != ':') 5914 return; 5915 domain = val; 5916 val = strtol(end + 1, &end, 10); 5917 if (val < 0 || val > INT_MAX || *end != ':') 5918 return; 5919 bus = val; 5920 val = strtol(end + 1, &end, 10); 5921 if (val < 0 || val > INT_MAX) 5922 return; 5923 slot = val; 5924 if (*end == ':') { 5925 val = strtol(end + 1, &end, 10); 5926 if (val < 0 || val > INT_MAX || *end != '\0') 5927 return; 5928 func = val; 5929 } else if (*end == '\0') { 5930 func = slot; 5931 slot = bus; 5932 bus = domain; 5933 domain = 0; 5934 } else 5935 return; 5936 5937 if (domain > PCI_DOMAINMAX || bus > PCI_BUSMAX || slot > PCI_SLOTMAX || 5938 func > PCIE_ARI_FUNCMAX || (slot != 0 && func > PCI_FUNCMAX)) 5939 return; 5940 5941 *dev = pci_find_dbsf(domain, bus, slot, func); 5942 } 5943 5944 static int 5945 pci_modevent(module_t mod, int what, void *arg) 5946 { 5947 static struct cdev *pci_cdev; 5948 static eventhandler_tag tag; 5949 5950 switch (what) { 5951 case MOD_LOAD: 5952 STAILQ_INIT(&pci_devq); 5953 pci_generation = 0; 5954 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 5955 "pci"); 5956 pci_load_vendor_data(); 5957 tag = EVENTHANDLER_REGISTER(dev_lookup, pci_lookup, NULL, 5958 1000); 5959 break; 5960 5961 case MOD_UNLOAD: 5962 if (tag != NULL) 5963 EVENTHANDLER_DEREGISTER(dev_lookup, tag); 5964 destroy_dev(pci_cdev); 5965 break; 5966 } 5967 5968 return (0); 5969 } 5970 5971 static void 5972 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo) 5973 { 5974 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2) 5975 struct pcicfg_pcie *cfg; 5976 int version, pos; 5977 5978 cfg = &dinfo->cfg.pcie; 5979 pos = cfg->pcie_location; 5980 5981 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 5982 5983 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); 5984 5985 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5986 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 5987 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 5988 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); 5989 5990 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5991 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 5992 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 5993 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); 5994 5995 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5996 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 5997 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); 5998 5999 if (version > 1) { 6000 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); 6001 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); 6002 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); 6003 } 6004 #undef WREG 6005 } 6006 6007 static void 6008 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo) 6009 { 6010 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 6011 dinfo->cfg.pcix.pcix_command, 2); 6012 } 6013 6014 void 6015 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 6016 { 6017 6018 /* 6019 * Restore the device to full power mode. We must do this 6020 * before we restore the registers because moving from D3 to 6021 * D0 will cause the chip's BARs and some other registers to 6022 * be reset to some unknown power on reset values. Cut down 6023 * the noise on boot by doing nothing if we are already in 6024 * state D0. 6025 */ 6026 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) 6027 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6028 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 6029 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 6030 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 6031 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 6032 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 6033 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 6034 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6035 case PCIM_HDRTYPE_NORMAL: 6036 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 6037 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 6038 break; 6039 case PCIM_HDRTYPE_BRIDGE: 6040 pci_write_config(dev, PCIR_SECLAT_1, 6041 dinfo->cfg.bridge.br_seclat, 1); 6042 pci_write_config(dev, PCIR_SUBBUS_1, 6043 dinfo->cfg.bridge.br_subbus, 1); 6044 pci_write_config(dev, PCIR_SECBUS_1, 6045 dinfo->cfg.bridge.br_secbus, 1); 6046 pci_write_config(dev, PCIR_PRIBUS_1, 6047 dinfo->cfg.bridge.br_pribus, 1); 6048 pci_write_config(dev, PCIR_BRIDGECTL_1, 6049 dinfo->cfg.bridge.br_control, 2); 6050 break; 6051 case PCIM_HDRTYPE_CARDBUS: 6052 pci_write_config(dev, PCIR_SECLAT_2, 6053 dinfo->cfg.bridge.br_seclat, 1); 6054 pci_write_config(dev, PCIR_SUBBUS_2, 6055 dinfo->cfg.bridge.br_subbus, 1); 6056 pci_write_config(dev, PCIR_SECBUS_2, 6057 dinfo->cfg.bridge.br_secbus, 1); 6058 pci_write_config(dev, PCIR_PRIBUS_2, 6059 dinfo->cfg.bridge.br_pribus, 1); 6060 pci_write_config(dev, PCIR_BRIDGECTL_2, 6061 dinfo->cfg.bridge.br_control, 2); 6062 break; 6063 } 6064 pci_restore_bars(dev); 6065 6066 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE) 6067 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 6068 6069 /* 6070 * Restore extended capabilities for PCI-Express and PCI-X 6071 */ 6072 if (dinfo->cfg.pcie.pcie_location != 0) 6073 pci_cfg_restore_pcie(dev, dinfo); 6074 if (dinfo->cfg.pcix.pcix_location != 0) 6075 pci_cfg_restore_pcix(dev, dinfo); 6076 6077 /* Restore MSI and MSI-X configurations if they are present. */ 6078 if (dinfo->cfg.msi.msi_location != 0) 6079 pci_resume_msi(dev); 6080 if (dinfo->cfg.msix.msix_location != 0) 6081 pci_resume_msix(dev); 6082 6083 #ifdef PCI_IOV 6084 if (dinfo->cfg.iov != NULL) 6085 pci_iov_cfg_restore(dev, dinfo); 6086 #endif 6087 } 6088 6089 static void 6090 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo) 6091 { 6092 #define RREG(n) pci_read_config(dev, pos + (n), 2) 6093 struct pcicfg_pcie *cfg; 6094 int version, pos; 6095 6096 cfg = &dinfo->cfg.pcie; 6097 pos = cfg->pcie_location; 6098 6099 cfg->pcie_flags = RREG(PCIER_FLAGS); 6100 6101 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6102 6103 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); 6104 6105 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6106 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6107 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6108 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); 6109 6110 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6111 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6112 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6113 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); 6114 6115 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6116 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6117 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); 6118 6119 if (version > 1) { 6120 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); 6121 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); 6122 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); 6123 } 6124 #undef RREG 6125 } 6126 6127 static void 6128 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo) 6129 { 6130 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, 6131 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); 6132 } 6133 6134 void 6135 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 6136 { 6137 uint32_t cls; 6138 int ps; 6139 6140 /* 6141 * Some drivers apparently write to these registers w/o updating our 6142 * cached copy. No harm happens if we update the copy, so do so here 6143 * so we can restore them. The COMMAND register is modified by the 6144 * bus w/o updating the cache. This should represent the normally 6145 * writable portion of the 'defined' part of type 0/1/2 headers. 6146 */ 6147 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 6148 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 6149 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 6150 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 6151 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 6152 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 6153 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 6154 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 6155 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 6156 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 6157 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 6158 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6159 case PCIM_HDRTYPE_NORMAL: 6160 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 6161 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 6162 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 6163 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 6164 break; 6165 case PCIM_HDRTYPE_BRIDGE: 6166 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6167 PCIR_SECLAT_1, 1); 6168 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6169 PCIR_SUBBUS_1, 1); 6170 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6171 PCIR_SECBUS_1, 1); 6172 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6173 PCIR_PRIBUS_1, 1); 6174 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6175 PCIR_BRIDGECTL_1, 2); 6176 break; 6177 case PCIM_HDRTYPE_CARDBUS: 6178 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6179 PCIR_SECLAT_2, 1); 6180 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6181 PCIR_SUBBUS_2, 1); 6182 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6183 PCIR_SECBUS_2, 1); 6184 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6185 PCIR_PRIBUS_2, 1); 6186 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6187 PCIR_BRIDGECTL_2, 2); 6188 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2); 6189 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2); 6190 break; 6191 } 6192 6193 if (dinfo->cfg.pcie.pcie_location != 0) 6194 pci_cfg_save_pcie(dev, dinfo); 6195 6196 if (dinfo->cfg.pcix.pcix_location != 0) 6197 pci_cfg_save_pcix(dev, dinfo); 6198 6199 #ifdef PCI_IOV 6200 if (dinfo->cfg.iov != NULL) 6201 pci_iov_cfg_save(dev, dinfo); 6202 #endif 6203 6204 /* 6205 * don't set the state for display devices, base peripherals and 6206 * memory devices since bad things happen when they are powered down. 6207 * We should (a) have drivers that can easily detach and (b) use 6208 * generic drivers for these devices so that some device actually 6209 * attaches. We need to make sure that when we implement (a) we don't 6210 * power the device down on a reattach. 6211 */ 6212 cls = pci_get_class(dev); 6213 if (!setstate) 6214 return; 6215 switch (pci_do_power_nodriver) 6216 { 6217 case 0: /* NO powerdown at all */ 6218 return; 6219 case 1: /* Conservative about what to power down */ 6220 if (cls == PCIC_STORAGE) 6221 return; 6222 /*FALLTHROUGH*/ 6223 case 2: /* Aggressive about what to power down */ 6224 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 6225 cls == PCIC_BASEPERIPH) 6226 return; 6227 /*FALLTHROUGH*/ 6228 case 3: /* Power down everything */ 6229 break; 6230 } 6231 /* 6232 * PCI spec says we can only go into D3 state from D0 state. 6233 * Transition from D[12] into D0 before going to D3 state. 6234 */ 6235 ps = pci_get_powerstate(dev); 6236 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6237 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6238 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 6239 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6240 } 6241 6242 /* Wrapper APIs suitable for device driver use. */ 6243 void 6244 pci_save_state(device_t dev) 6245 { 6246 struct pci_devinfo *dinfo; 6247 6248 dinfo = device_get_ivars(dev); 6249 pci_cfg_save(dev, dinfo, 0); 6250 } 6251 6252 void 6253 pci_restore_state(device_t dev) 6254 { 6255 struct pci_devinfo *dinfo; 6256 6257 dinfo = device_get_ivars(dev); 6258 pci_cfg_restore(dev, dinfo); 6259 } 6260 6261 static int 6262 pci_get_id_method(device_t dev, device_t child, enum pci_id_type type, 6263 uintptr_t *id) 6264 { 6265 6266 return (PCIB_GET_ID(device_get_parent(dev), child, type, id)); 6267 } 6268 6269 /* Find the upstream port of a given PCI device in a root complex. */ 6270 device_t 6271 pci_find_pcie_root_port(device_t dev) 6272 { 6273 struct pci_devinfo *dinfo; 6274 devclass_t pci_class; 6275 device_t pcib, bus; 6276 6277 pci_class = devclass_find("pci"); 6278 KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class, 6279 ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); 6280 6281 /* 6282 * Walk the bridge hierarchy until we find a PCI-e root 6283 * port or a non-PCI device. 6284 */ 6285 for (;;) { 6286 bus = device_get_parent(dev); 6287 KASSERT(bus != NULL, ("%s: null parent of %s", __func__, 6288 device_get_nameunit(dev))); 6289 6290 pcib = device_get_parent(bus); 6291 KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__, 6292 device_get_nameunit(bus))); 6293 6294 /* 6295 * pcib's parent must be a PCI bus for this to be a 6296 * PCI-PCI bridge. 6297 */ 6298 if (device_get_devclass(device_get_parent(pcib)) != pci_class) 6299 return (NULL); 6300 6301 dinfo = device_get_ivars(pcib); 6302 if (dinfo->cfg.pcie.pcie_location != 0 && 6303 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) 6304 return (pcib); 6305 6306 dev = pcib; 6307 } 6308 } 6309 6310 /* 6311 * Wait for pending transactions to complete on a PCI-express function. 6312 * 6313 * The maximum delay is specified in milliseconds in max_delay. Note 6314 * that this function may sleep. 6315 * 6316 * Returns true if the function is idle and false if the timeout is 6317 * exceeded. If dev is not a PCI-express function, this returns true. 6318 */ 6319 bool 6320 pcie_wait_for_pending_transactions(device_t dev, u_int max_delay) 6321 { 6322 struct pci_devinfo *dinfo = device_get_ivars(dev); 6323 uint16_t sta; 6324 int cap; 6325 6326 cap = dinfo->cfg.pcie.pcie_location; 6327 if (cap == 0) 6328 return (true); 6329 6330 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6331 while (sta & PCIEM_STA_TRANSACTION_PND) { 6332 if (max_delay == 0) 6333 return (false); 6334 6335 /* Poll once every 100 milliseconds up to the timeout. */ 6336 if (max_delay > 100) { 6337 pause_sbt("pcietp", 100 * SBT_1MS, 0, C_HARDCLOCK); 6338 max_delay -= 100; 6339 } else { 6340 pause_sbt("pcietp", max_delay * SBT_1MS, 0, 6341 C_HARDCLOCK); 6342 max_delay = 0; 6343 } 6344 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6345 } 6346 6347 return (true); 6348 } 6349 6350 /* 6351 * Determine the maximum Completion Timeout in microseconds. 6352 * 6353 * For non-PCI-express functions this returns 0. 6354 */ 6355 int 6356 pcie_get_max_completion_timeout(device_t dev) 6357 { 6358 struct pci_devinfo *dinfo = device_get_ivars(dev); 6359 int cap; 6360 6361 cap = dinfo->cfg.pcie.pcie_location; 6362 if (cap == 0) 6363 return (0); 6364 6365 /* 6366 * Functions using the 1.x spec use the default timeout range of 6367 * 50 microseconds to 50 milliseconds. Functions that do not 6368 * support programmable timeouts also use this range. 6369 */ 6370 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 || 6371 (pci_read_config(dev, cap + PCIER_DEVICE_CAP2, 4) & 6372 PCIEM_CAP2_COMP_TIMO_RANGES) == 0) 6373 return (50 * 1000); 6374 6375 switch (pci_read_config(dev, cap + PCIER_DEVICE_CTL2, 2) & 6376 PCIEM_CTL2_COMP_TIMO_VAL) { 6377 case PCIEM_CTL2_COMP_TIMO_100US: 6378 return (100); 6379 case PCIEM_CTL2_COMP_TIMO_10MS: 6380 return (10 * 1000); 6381 case PCIEM_CTL2_COMP_TIMO_55MS: 6382 return (55 * 1000); 6383 case PCIEM_CTL2_COMP_TIMO_210MS: 6384 return (210 * 1000); 6385 case PCIEM_CTL2_COMP_TIMO_900MS: 6386 return (900 * 1000); 6387 case PCIEM_CTL2_COMP_TIMO_3500MS: 6388 return (3500 * 1000); 6389 case PCIEM_CTL2_COMP_TIMO_13S: 6390 return (13 * 1000 * 1000); 6391 case PCIEM_CTL2_COMP_TIMO_64S: 6392 return (64 * 1000 * 1000); 6393 default: 6394 return (50 * 1000); 6395 } 6396 } 6397 6398 void 6399 pcie_apei_error(device_t dev, int sev, uint8_t *aerp) 6400 { 6401 struct pci_devinfo *dinfo = device_get_ivars(dev); 6402 const char *s; 6403 int aer; 6404 uint32_t r, r1; 6405 uint16_t rs; 6406 6407 if (sev == PCIEM_STA_CORRECTABLE_ERROR) 6408 s = "Correctable"; 6409 else if (sev == PCIEM_STA_NON_FATAL_ERROR) 6410 s = "Uncorrectable (Non-Fatal)"; 6411 else 6412 s = "Uncorrectable (Fatal)"; 6413 device_printf(dev, "%s PCIe error reported by APEI\n", s); 6414 if (aerp) { 6415 if (sev == PCIEM_STA_CORRECTABLE_ERROR) { 6416 r = le32dec(aerp + PCIR_AER_COR_STATUS); 6417 r1 = le32dec(aerp + PCIR_AER_COR_MASK); 6418 } else { 6419 r = le32dec(aerp + PCIR_AER_UC_STATUS); 6420 r1 = le32dec(aerp + PCIR_AER_UC_MASK); 6421 } 6422 device_printf(dev, "status 0x%08x mask 0x%08x", r, r1); 6423 if (sev != PCIEM_STA_CORRECTABLE_ERROR) { 6424 r = le32dec(aerp + PCIR_AER_UC_SEVERITY); 6425 rs = le16dec(aerp + PCIR_AER_CAP_CONTROL); 6426 printf(" severity 0x%08x first %d\n", 6427 r, rs & 0x1f); 6428 } else 6429 printf("\n"); 6430 } 6431 6432 /* As kind of recovery just report and clear the error statuses. */ 6433 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6434 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6435 if (r != 0) { 6436 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6437 device_printf(dev, "Clearing UC AER errors 0x%08x\n", r); 6438 } 6439 6440 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6441 if (r != 0) { 6442 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6443 device_printf(dev, "Clearing COR AER errors 0x%08x\n", r); 6444 } 6445 } 6446 if (dinfo->cfg.pcie.pcie_location != 0) { 6447 rs = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6448 PCIER_DEVICE_STA, 2); 6449 if ((rs & (PCIEM_STA_CORRECTABLE_ERROR | 6450 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6451 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6452 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6453 PCIER_DEVICE_STA, rs, 2); 6454 device_printf(dev, "Clearing PCIe errors 0x%04x\n", rs); 6455 } 6456 } 6457 } 6458 6459 /* 6460 * Perform a Function Level Reset (FLR) on a device. 6461 * 6462 * This function first waits for any pending transactions to complete 6463 * within the timeout specified by max_delay. If transactions are 6464 * still pending, the function will return false without attempting a 6465 * reset. 6466 * 6467 * If dev is not a PCI-express function or does not support FLR, this 6468 * function returns false. 6469 * 6470 * Note that no registers are saved or restored. The caller is 6471 * responsible for saving and restoring any registers including 6472 * PCI-standard registers via pci_save_state() and 6473 * pci_restore_state(). 6474 */ 6475 bool 6476 pcie_flr(device_t dev, u_int max_delay, bool force) 6477 { 6478 struct pci_devinfo *dinfo = device_get_ivars(dev); 6479 uint16_t cmd, ctl; 6480 int compl_delay; 6481 int cap; 6482 6483 cap = dinfo->cfg.pcie.pcie_location; 6484 if (cap == 0) 6485 return (false); 6486 6487 if (!(pci_read_config(dev, cap + PCIER_DEVICE_CAP, 4) & PCIEM_CAP_FLR)) 6488 return (false); 6489 6490 /* 6491 * Disable busmastering to prevent generation of new 6492 * transactions while waiting for the device to go idle. If 6493 * the idle timeout fails, the command register is restored 6494 * which will re-enable busmastering. 6495 */ 6496 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 6497 pci_write_config(dev, PCIR_COMMAND, cmd & ~(PCIM_CMD_BUSMASTEREN), 2); 6498 if (!pcie_wait_for_pending_transactions(dev, max_delay)) { 6499 if (!force) { 6500 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 6501 return (false); 6502 } 6503 pci_printf(&dinfo->cfg, 6504 "Resetting with transactions pending after %d ms\n", 6505 max_delay); 6506 6507 /* 6508 * Extend the post-FLR delay to cover the maximum 6509 * Completion Timeout delay of anything in flight 6510 * during the FLR delay. Enforce a minimum delay of 6511 * at least 10ms. 6512 */ 6513 compl_delay = pcie_get_max_completion_timeout(dev) / 1000; 6514 if (compl_delay < 10) 6515 compl_delay = 10; 6516 } else 6517 compl_delay = 0; 6518 6519 /* Initiate the reset. */ 6520 ctl = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 6521 pci_write_config(dev, cap + PCIER_DEVICE_CTL, ctl | 6522 PCIEM_CTL_INITIATE_FLR, 2); 6523 6524 /* Wait for 100ms. */ 6525 pause_sbt("pcieflr", (100 + compl_delay) * SBT_1MS, 0, C_HARDCLOCK); 6526 6527 if (pci_read_config(dev, cap + PCIER_DEVICE_STA, 2) & 6528 PCIEM_STA_TRANSACTION_PND) 6529 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n"); 6530 return (true); 6531 } 6532 6533 /* 6534 * Attempt a power-management reset by cycling the device in/out of D3 6535 * state. PCI spec says we can only go into D3 state from D0 state. 6536 * Transition from D[12] into D0 before going to D3 state. 6537 */ 6538 int 6539 pci_power_reset(device_t dev) 6540 { 6541 int ps; 6542 6543 ps = pci_get_powerstate(dev); 6544 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6545 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6546 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6547 pci_set_powerstate(dev, ps); 6548 return (0); 6549 } 6550 6551 /* 6552 * Try link drop and retrain of the downstream port of upstream 6553 * switch, for PCIe. According to the PCIe 3.0 spec 6.6.1, this must 6554 * cause Conventional Hot reset of the device in the slot. 6555 * Alternative, for PCIe, could be the secondary bus reset initiatied 6556 * on the upstream switch PCIR_BRIDGECTL_1, bit 6. 6557 */ 6558 int 6559 pcie_link_reset(device_t port, int pcie_location) 6560 { 6561 uint16_t v; 6562 6563 v = pci_read_config(port, pcie_location + PCIER_LINK_CTL, 2); 6564 v |= PCIEM_LINK_CTL_LINK_DIS; 6565 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6566 pause_sbt("pcier1", mstosbt(20), 0, 0); 6567 v &= ~PCIEM_LINK_CTL_LINK_DIS; 6568 v |= PCIEM_LINK_CTL_RETRAIN_LINK; 6569 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6570 pause_sbt("pcier2", mstosbt(100), 0, 0); /* 100 ms */ 6571 v = pci_read_config(port, pcie_location + PCIER_LINK_STA, 2); 6572 return ((v & PCIEM_LINK_STA_TRAINING) != 0 ? ETIMEDOUT : 0); 6573 } 6574 6575 static int 6576 pci_reset_post(device_t dev, device_t child) 6577 { 6578 6579 if (dev == device_get_parent(child)) 6580 pci_restore_state(child); 6581 return (0); 6582 } 6583 6584 static int 6585 pci_reset_prepare(device_t dev, device_t child) 6586 { 6587 6588 if (dev == device_get_parent(child)) 6589 pci_save_state(child); 6590 return (0); 6591 } 6592 6593 static int 6594 pci_reset_child(device_t dev, device_t child, int flags) 6595 { 6596 int error; 6597 6598 if (dev == NULL || device_get_parent(child) != dev) 6599 return (0); 6600 if ((flags & DEVF_RESET_DETACH) != 0) { 6601 error = device_get_state(child) == DS_ATTACHED ? 6602 device_detach(child) : 0; 6603 } else { 6604 error = BUS_SUSPEND_CHILD(dev, child); 6605 } 6606 if (error == 0) { 6607 if (!pcie_flr(child, 1000, false)) { 6608 error = BUS_RESET_PREPARE(dev, child); 6609 if (error == 0) 6610 pci_power_reset(child); 6611 BUS_RESET_POST(dev, child); 6612 } 6613 if ((flags & DEVF_RESET_DETACH) != 0) 6614 device_probe_and_attach(child); 6615 else 6616 BUS_RESUME_CHILD(dev, child); 6617 } 6618 return (error); 6619 } 6620 6621 const struct pci_device_table * 6622 pci_match_device(device_t child, const struct pci_device_table *id, size_t nelt) 6623 { 6624 bool match; 6625 uint16_t vendor, device, subvendor, subdevice, class, subclass, revid; 6626 6627 vendor = pci_get_vendor(child); 6628 device = pci_get_device(child); 6629 subvendor = pci_get_subvendor(child); 6630 subdevice = pci_get_subdevice(child); 6631 class = pci_get_class(child); 6632 subclass = pci_get_subclass(child); 6633 revid = pci_get_revid(child); 6634 while (nelt-- > 0) { 6635 match = true; 6636 if (id->match_flag_vendor) 6637 match &= vendor == id->vendor; 6638 if (id->match_flag_device) 6639 match &= device == id->device; 6640 if (id->match_flag_subvendor) 6641 match &= subvendor == id->subvendor; 6642 if (id->match_flag_subdevice) 6643 match &= subdevice == id->subdevice; 6644 if (id->match_flag_class) 6645 match &= class == id->class_id; 6646 if (id->match_flag_subclass) 6647 match &= subclass == id->subclass; 6648 if (id->match_flag_revid) 6649 match &= revid == id->revid; 6650 if (match) 6651 return (id); 6652 id++; 6653 } 6654 return (NULL); 6655 } 6656 6657 static void 6658 pci_print_faulted_dev_name(const struct pci_devinfo *dinfo) 6659 { 6660 const char *dev_name; 6661 device_t dev; 6662 6663 dev = dinfo->cfg.dev; 6664 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus, 6665 dinfo->cfg.slot, dinfo->cfg.func); 6666 dev_name = device_get_name(dev); 6667 if (dev_name != NULL) 6668 printf(" (%s%d)", dev_name, device_get_unit(dev)); 6669 } 6670 6671 void 6672 pci_print_faulted_dev(void) 6673 { 6674 struct pci_devinfo *dinfo; 6675 device_t dev; 6676 int aer, i; 6677 uint32_t r1, r2; 6678 uint16_t status; 6679 6680 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6681 dev = dinfo->cfg.dev; 6682 status = pci_read_config(dev, PCIR_STATUS, 2); 6683 status &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6684 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6685 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6686 if (status != 0) { 6687 pci_print_faulted_dev_name(dinfo); 6688 printf(" error 0x%04x\n", status); 6689 } 6690 if (dinfo->cfg.pcie.pcie_location != 0) { 6691 status = pci_read_config(dev, 6692 dinfo->cfg.pcie.pcie_location + 6693 PCIER_DEVICE_STA, 2); 6694 if ((status & (PCIEM_STA_CORRECTABLE_ERROR | 6695 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6696 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6697 pci_print_faulted_dev_name(dinfo); 6698 printf(" PCIe DEVCTL 0x%04x DEVSTA 0x%04x\n", 6699 pci_read_config(dev, 6700 dinfo->cfg.pcie.pcie_location + 6701 PCIER_DEVICE_CTL, 2), 6702 status); 6703 } 6704 } 6705 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6706 r1 = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6707 r2 = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6708 if (r1 != 0 || r2 != 0) { 6709 pci_print_faulted_dev_name(dinfo); 6710 printf(" AER UC 0x%08x Mask 0x%08x Svr 0x%08x\n" 6711 " COR 0x%08x Mask 0x%08x Ctl 0x%08x\n", 6712 r1, pci_read_config(dev, aer + 6713 PCIR_AER_UC_MASK, 4), 6714 pci_read_config(dev, aer + 6715 PCIR_AER_UC_SEVERITY, 4), 6716 r2, pci_read_config(dev, aer + 6717 PCIR_AER_COR_MASK, 4), 6718 pci_read_config(dev, aer + 6719 PCIR_AER_CAP_CONTROL, 4)); 6720 for (i = 0; i < 4; i++) { 6721 r1 = pci_read_config(dev, aer + 6722 PCIR_AER_HEADER_LOG + i * 4, 4); 6723 printf(" HL%d: 0x%08x\n", i, r1); 6724 } 6725 } 6726 } 6727 } 6728 } 6729 6730 #ifdef DDB 6731 DB_SHOW_COMMAND(pcierr, pci_print_faulted_dev_db) 6732 { 6733 6734 pci_print_faulted_dev(); 6735 } 6736 6737 static void 6738 db_clear_pcie_errors(const struct pci_devinfo *dinfo) 6739 { 6740 device_t dev; 6741 int aer; 6742 uint32_t r; 6743 6744 dev = dinfo->cfg.dev; 6745 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6746 PCIER_DEVICE_STA, 2); 6747 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6748 PCIER_DEVICE_STA, r, 2); 6749 6750 if (pci_find_extcap(dev, PCIZ_AER, &aer) != 0) 6751 return; 6752 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6753 if (r != 0) 6754 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6755 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6756 if (r != 0) 6757 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6758 } 6759 6760 DB_COMMAND(pci_clearerr, db_pci_clearerr) 6761 { 6762 struct pci_devinfo *dinfo; 6763 device_t dev; 6764 uint16_t status, status1; 6765 6766 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6767 dev = dinfo->cfg.dev; 6768 status1 = status = pci_read_config(dev, PCIR_STATUS, 2); 6769 status1 &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6770 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6771 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6772 if (status1 != 0) { 6773 status &= ~status1; 6774 pci_write_config(dev, PCIR_STATUS, status, 2); 6775 } 6776 if (dinfo->cfg.pcie.pcie_location != 0) 6777 db_clear_pcie_errors(dinfo); 6778 } 6779 } 6780 #endif 6781