1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 5 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000, BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice unmodified, this list of conditions, and the following 14 * disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "opt_acpi.h" 35 #include "opt_iommu.h" 36 #include "opt_bus.h" 37 38 #include <sys/param.h> 39 #include <sys/conf.h> 40 #include <sys/endian.h> 41 #include <sys/eventhandler.h> 42 #include <sys/fcntl.h> 43 #include <sys/kernel.h> 44 #include <sys/limits.h> 45 #include <sys/linker.h> 46 #include <sys/malloc.h> 47 #include <sys/module.h> 48 #include <sys/queue.h> 49 #include <sys/sbuf.h> 50 #include <sys/sysctl.h> 51 #include <sys/systm.h> 52 #include <sys/taskqueue.h> 53 #include <sys/tree.h> 54 55 #include <vm/vm.h> 56 #include <vm/pmap.h> 57 #include <vm/vm_extern.h> 58 59 #include <sys/bus.h> 60 #include <machine/bus.h> 61 #include <sys/rman.h> 62 #include <machine/resource.h> 63 #include <machine/stdarg.h> 64 65 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 66 #include <machine/intr_machdep.h> 67 #endif 68 69 #include <sys/pciio.h> 70 #include <dev/pci/pcireg.h> 71 #include <dev/pci/pcivar.h> 72 #include <dev/pci/pci_private.h> 73 74 #ifdef PCI_IOV 75 #include <sys/nv.h> 76 #include <dev/pci/pci_iov_private.h> 77 #endif 78 79 #include <dev/usb/controller/xhcireg.h> 80 #include <dev/usb/controller/ehcireg.h> 81 #include <dev/usb/controller/ohcireg.h> 82 #include <dev/usb/controller/uhcireg.h> 83 84 #include <dev/iommu/iommu.h> 85 86 #include "pcib_if.h" 87 #include "pci_if.h" 88 89 #define PCIR_IS_BIOS(cfg, reg) \ 90 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ 91 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) 92 93 static int pci_has_quirk(uint32_t devid, int quirk); 94 static pci_addr_t pci_mapbase(uint64_t mapreg); 95 static const char *pci_maptype(uint64_t mapreg); 96 static int pci_maprange(uint64_t mapreg); 97 static pci_addr_t pci_rombase(uint64_t mapreg); 98 static int pci_romsize(uint64_t testval); 99 static void pci_fixancient(pcicfgregs *cfg); 100 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...); 101 102 static int pci_porten(device_t dev); 103 static int pci_memen(device_t dev); 104 static void pci_assign_interrupt(device_t bus, device_t dev, 105 int force_route); 106 static int pci_add_map(device_t bus, device_t dev, int reg, 107 struct resource_list *rl, int force, int prefetch); 108 static int pci_probe(device_t dev); 109 static void pci_load_vendor_data(void); 110 static int pci_describe_parse_line(char **ptr, int *vendor, 111 int *device, char **desc); 112 static char *pci_describe_device(device_t dev); 113 static int pci_modevent(module_t mod, int what, void *arg); 114 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 115 pcicfgregs *cfg); 116 static void pci_read_cap(device_t pcib, pcicfgregs *cfg); 117 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 118 int reg, uint32_t *data); 119 #if 0 120 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 121 int reg, uint32_t data); 122 #endif 123 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 124 static void pci_mask_msix(device_t dev, u_int index); 125 static void pci_unmask_msix(device_t dev, u_int index); 126 static int pci_msi_blacklisted(void); 127 static int pci_msix_blacklisted(void); 128 static void pci_resume_msi(device_t dev); 129 static void pci_resume_msix(device_t dev); 130 static int pci_remap_intr_method(device_t bus, device_t dev, 131 u_int irq); 132 static void pci_hint_device_unit(device_t acdev, device_t child, 133 const char *name, int *unitp); 134 static int pci_reset_post(device_t dev, device_t child); 135 static int pci_reset_prepare(device_t dev, device_t child); 136 static int pci_reset_child(device_t dev, device_t child, 137 int flags); 138 139 static int pci_get_id_method(device_t dev, device_t child, 140 enum pci_id_type type, uintptr_t *rid); 141 142 static struct pci_devinfo * pci_fill_devinfo(device_t pcib, device_t bus, int d, 143 int b, int s, int f, uint16_t vid, uint16_t did); 144 145 static device_method_t pci_methods[] = { 146 /* Device interface */ 147 DEVMETHOD(device_probe, pci_probe), 148 DEVMETHOD(device_attach, pci_attach), 149 DEVMETHOD(device_detach, pci_detach), 150 DEVMETHOD(device_shutdown, bus_generic_shutdown), 151 DEVMETHOD(device_suspend, bus_generic_suspend), 152 DEVMETHOD(device_resume, pci_resume), 153 154 /* Bus interface */ 155 DEVMETHOD(bus_print_child, pci_print_child), 156 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 157 DEVMETHOD(bus_read_ivar, pci_read_ivar), 158 DEVMETHOD(bus_write_ivar, pci_write_ivar), 159 DEVMETHOD(bus_driver_added, pci_driver_added), 160 DEVMETHOD(bus_setup_intr, pci_setup_intr), 161 DEVMETHOD(bus_teardown_intr, pci_teardown_intr), 162 DEVMETHOD(bus_reset_prepare, pci_reset_prepare), 163 DEVMETHOD(bus_reset_post, pci_reset_post), 164 DEVMETHOD(bus_reset_child, pci_reset_child), 165 166 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag), 167 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 168 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 169 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 170 DEVMETHOD(bus_delete_resource, pci_delete_resource), 171 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 172 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 173 DEVMETHOD(bus_release_resource, pci_release_resource), 174 DEVMETHOD(bus_activate_resource, pci_activate_resource), 175 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource), 176 DEVMETHOD(bus_child_deleted, pci_child_deleted), 177 DEVMETHOD(bus_child_detached, pci_child_detached), 178 DEVMETHOD(bus_child_pnpinfo, pci_child_pnpinfo_method), 179 DEVMETHOD(bus_child_location, pci_child_location_method), 180 DEVMETHOD(bus_hint_device_unit, pci_hint_device_unit), 181 DEVMETHOD(bus_remap_intr, pci_remap_intr_method), 182 DEVMETHOD(bus_suspend_child, pci_suspend_child), 183 DEVMETHOD(bus_resume_child, pci_resume_child), 184 DEVMETHOD(bus_rescan, pci_rescan_method), 185 186 /* PCI interface */ 187 DEVMETHOD(pci_read_config, pci_read_config_method), 188 DEVMETHOD(pci_write_config, pci_write_config_method), 189 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 190 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 191 DEVMETHOD(pci_enable_io, pci_enable_io_method), 192 DEVMETHOD(pci_disable_io, pci_disable_io_method), 193 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 194 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 195 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 196 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 197 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 198 DEVMETHOD(pci_find_cap, pci_find_cap_method), 199 DEVMETHOD(pci_find_next_cap, pci_find_next_cap_method), 200 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 201 DEVMETHOD(pci_find_next_extcap, pci_find_next_extcap_method), 202 DEVMETHOD(pci_find_htcap, pci_find_htcap_method), 203 DEVMETHOD(pci_find_next_htcap, pci_find_next_htcap_method), 204 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 205 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), 206 DEVMETHOD(pci_enable_msi, pci_enable_msi_method), 207 DEVMETHOD(pci_enable_msix, pci_enable_msix_method), 208 DEVMETHOD(pci_disable_msi, pci_disable_msi_method), 209 DEVMETHOD(pci_remap_msix, pci_remap_msix_method), 210 DEVMETHOD(pci_release_msi, pci_release_msi_method), 211 DEVMETHOD(pci_msi_count, pci_msi_count_method), 212 DEVMETHOD(pci_msix_count, pci_msix_count_method), 213 DEVMETHOD(pci_msix_pba_bar, pci_msix_pba_bar_method), 214 DEVMETHOD(pci_msix_table_bar, pci_msix_table_bar_method), 215 DEVMETHOD(pci_get_id, pci_get_id_method), 216 DEVMETHOD(pci_alloc_devinfo, pci_alloc_devinfo_method), 217 DEVMETHOD(pci_child_added, pci_child_added_method), 218 #ifdef PCI_IOV 219 DEVMETHOD(pci_iov_attach, pci_iov_attach_method), 220 DEVMETHOD(pci_iov_detach, pci_iov_detach_method), 221 DEVMETHOD(pci_create_iov_child, pci_create_iov_child_method), 222 #endif 223 224 DEVMETHOD_END 225 }; 226 227 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc)); 228 229 static devclass_t pci_devclass; 230 EARLY_DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL, 231 BUS_PASS_BUS); 232 MODULE_VERSION(pci, 1); 233 234 static char *pci_vendordata; 235 static size_t pci_vendordata_size; 236 237 struct pci_quirk { 238 uint32_t devid; /* Vendor/device of the card */ 239 int type; 240 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 241 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */ 242 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */ 243 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */ 244 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */ 245 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */ 246 #define PCI_QUIRK_REALLOC_BAR 7 /* Can't allocate memory at the default address */ 247 int arg1; 248 int arg2; 249 }; 250 251 static const struct pci_quirk pci_quirks[] = { 252 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */ 253 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 254 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 255 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 256 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 257 258 /* 259 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge 260 * or the CMIC-SL (AKA ServerWorks GC_LE). 261 */ 262 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 263 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 264 265 /* 266 * MSI doesn't work on earlier Intel chipsets including 267 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855. 268 */ 269 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 270 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 271 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 272 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 273 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 274 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 275 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 276 277 /* 278 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX 279 * bridge. 280 */ 281 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 282 283 /* 284 * Some virtualization environments emulate an older chipset 285 * but support MSI just fine. QEMU uses the Intel 82440. 286 */ 287 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 }, 288 289 /* 290 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus 291 * controller depending on SoftPciRst register (PM_IO 0x55 [7]). 292 * It prevents us from attaching hpet(4) when the bit is unset. 293 * Note this quirk only affects SB600 revision A13 and earlier. 294 * For SB600 A21 and later, firmware must set the bit to hide it. 295 * For SB700 and later, it is unused and hardcoded to zero. 296 */ 297 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 }, 298 299 /* 300 * Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have 301 * a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit 302 * of the command register is set. 303 */ 304 { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 305 { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 306 { 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 307 { 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 308 { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 309 310 /* 311 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't 312 * issue MSI interrupts with PCIM_CMD_INTxDIS set either. 313 */ 314 { 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */ 315 { 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */ 316 { 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */ 317 { 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */ 318 { 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */ 319 { 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */ 320 321 /* 322 * HPE Gen 10 VGA has a memory range that can't be allocated in the 323 * expected place. 324 */ 325 { 0x98741002, PCI_QUIRK_REALLOC_BAR, 0, 0 }, 326 { 0 } 327 }; 328 329 /* map register information */ 330 #define PCI_MAPMEM 0x01 /* memory map */ 331 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 332 #define PCI_MAPPORT 0x04 /* port map */ 333 334 struct devlist pci_devq; 335 uint32_t pci_generation; 336 uint32_t pci_numdevs = 0; 337 static int pcie_chipset, pcix_chipset; 338 339 /* sysctl vars */ 340 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 341 "PCI bus tuning parameters"); 342 343 static int pci_enable_io_modes = 1; 344 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RWTUN, 345 &pci_enable_io_modes, 1, 346 "Enable I/O and memory bits in the config register. Some BIOSes do not" 347 " enable these bits correctly. We'd like to do this all the time, but" 348 " there are some peripherals that this causes problems with."); 349 350 static int pci_do_realloc_bars = 1; 351 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RWTUN, 352 &pci_do_realloc_bars, 0, 353 "Attempt to allocate a new range for any BARs whose original " 354 "firmware-assigned ranges fail to allocate during the initial device scan."); 355 356 static int pci_do_power_nodriver = 0; 357 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RWTUN, 358 &pci_do_power_nodriver, 0, 359 "Place a function into D3 state when no driver attaches to it. 0 means" 360 " disable. 1 means conservatively place devices into D3 state. 2 means" 361 " aggressively place devices into D3 state. 3 means put absolutely" 362 " everything in D3 state."); 363 364 int pci_do_power_resume = 1; 365 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RWTUN, 366 &pci_do_power_resume, 1, 367 "Transition from D3 -> D0 on resume."); 368 369 int pci_do_power_suspend = 1; 370 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RWTUN, 371 &pci_do_power_suspend, 1, 372 "Transition from D0 -> D3 on suspend."); 373 374 static int pci_do_msi = 1; 375 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RWTUN, &pci_do_msi, 1, 376 "Enable support for MSI interrupts"); 377 378 static int pci_do_msix = 1; 379 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RWTUN, &pci_do_msix, 1, 380 "Enable support for MSI-X interrupts"); 381 382 static int pci_msix_rewrite_table = 0; 383 SYSCTL_INT(_hw_pci, OID_AUTO, msix_rewrite_table, CTLFLAG_RWTUN, 384 &pci_msix_rewrite_table, 0, 385 "Rewrite entire MSI-X table when updating MSI-X entries"); 386 387 static int pci_honor_msi_blacklist = 1; 388 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RDTUN, 389 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X"); 390 391 #if defined(__i386__) || defined(__amd64__) 392 static int pci_usb_takeover = 1; 393 #else 394 static int pci_usb_takeover = 0; 395 #endif 396 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN, 397 &pci_usb_takeover, 1, 398 "Enable early takeover of USB controllers. Disable this if you depend on" 399 " BIOS emulation of USB devices, that is you use USB devices (like" 400 " keyboard or mouse) but do not load USB drivers"); 401 402 static int pci_clear_bars; 403 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0, 404 "Ignore firmware-assigned resources for BARs."); 405 406 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 407 static int pci_clear_buses; 408 SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0, 409 "Ignore firmware-assigned bus numbers."); 410 #endif 411 412 static int pci_enable_ari = 1; 413 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari, 414 0, "Enable support for PCIe Alternative RID Interpretation"); 415 416 int pci_enable_aspm = 1; 417 SYSCTL_INT(_hw_pci, OID_AUTO, enable_aspm, CTLFLAG_RDTUN, &pci_enable_aspm, 418 0, "Enable support for PCIe Active State Power Management"); 419 420 static int pci_clear_aer_on_attach = 0; 421 SYSCTL_INT(_hw_pci, OID_AUTO, clear_aer_on_attach, CTLFLAG_RWTUN, 422 &pci_clear_aer_on_attach, 0, 423 "Clear port and device AER state on driver attach"); 424 425 static int 426 pci_has_quirk(uint32_t devid, int quirk) 427 { 428 const struct pci_quirk *q; 429 430 for (q = &pci_quirks[0]; q->devid; q++) { 431 if (q->devid == devid && q->type == quirk) 432 return (1); 433 } 434 return (0); 435 } 436 437 /* Find a device_t by bus/slot/function in domain 0 */ 438 439 device_t 440 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 441 { 442 443 return (pci_find_dbsf(0, bus, slot, func)); 444 } 445 446 /* Find a device_t by domain/bus/slot/function */ 447 448 device_t 449 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func) 450 { 451 struct pci_devinfo *dinfo = NULL; 452 453 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 454 if ((dinfo->cfg.domain == domain) && 455 (dinfo->cfg.bus == bus) && 456 (dinfo->cfg.slot == slot) && 457 (dinfo->cfg.func == func)) { 458 break; 459 } 460 } 461 462 return (dinfo != NULL ? dinfo->cfg.dev : NULL); 463 } 464 465 /* Find a device_t by vendor/device ID */ 466 467 device_t 468 pci_find_device(uint16_t vendor, uint16_t device) 469 { 470 struct pci_devinfo *dinfo; 471 472 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 473 if ((dinfo->cfg.vendor == vendor) && 474 (dinfo->cfg.device == device)) { 475 return (dinfo->cfg.dev); 476 } 477 } 478 479 return (NULL); 480 } 481 482 device_t 483 pci_find_class(uint8_t class, uint8_t subclass) 484 { 485 struct pci_devinfo *dinfo; 486 487 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 488 if (dinfo->cfg.baseclass == class && 489 dinfo->cfg.subclass == subclass) { 490 return (dinfo->cfg.dev); 491 } 492 } 493 494 return (NULL); 495 } 496 497 device_t 498 pci_find_class_from(uint8_t class, uint8_t subclass, device_t from) 499 { 500 struct pci_devinfo *dinfo; 501 bool found = false; 502 503 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 504 if (from != NULL && found == false) { 505 if (from != dinfo->cfg.dev) 506 continue; 507 found = true; 508 continue; 509 } 510 if (dinfo->cfg.baseclass == class && 511 dinfo->cfg.subclass == subclass) { 512 return (dinfo->cfg.dev); 513 } 514 } 515 516 return (NULL); 517 } 518 519 static int 520 pci_printf(pcicfgregs *cfg, const char *fmt, ...) 521 { 522 va_list ap; 523 int retval; 524 525 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, 526 cfg->func); 527 va_start(ap, fmt); 528 retval += vprintf(fmt, ap); 529 va_end(ap); 530 return (retval); 531 } 532 533 /* return base address of memory or port map */ 534 535 static pci_addr_t 536 pci_mapbase(uint64_t mapreg) 537 { 538 539 if (PCI_BAR_MEM(mapreg)) 540 return (mapreg & PCIM_BAR_MEM_BASE); 541 else 542 return (mapreg & PCIM_BAR_IO_BASE); 543 } 544 545 /* return map type of memory or port map */ 546 547 static const char * 548 pci_maptype(uint64_t mapreg) 549 { 550 551 if (PCI_BAR_IO(mapreg)) 552 return ("I/O Port"); 553 if (mapreg & PCIM_BAR_MEM_PREFETCH) 554 return ("Prefetchable Memory"); 555 return ("Memory"); 556 } 557 558 /* return log2 of map size decoded for memory or port map */ 559 560 int 561 pci_mapsize(uint64_t testval) 562 { 563 int ln2size; 564 565 testval = pci_mapbase(testval); 566 ln2size = 0; 567 if (testval != 0) { 568 while ((testval & 1) == 0) 569 { 570 ln2size++; 571 testval >>= 1; 572 } 573 } 574 return (ln2size); 575 } 576 577 /* return base address of device ROM */ 578 579 static pci_addr_t 580 pci_rombase(uint64_t mapreg) 581 { 582 583 return (mapreg & PCIM_BIOS_ADDR_MASK); 584 } 585 586 /* return log2 of map size decided for device ROM */ 587 588 static int 589 pci_romsize(uint64_t testval) 590 { 591 int ln2size; 592 593 testval = pci_rombase(testval); 594 ln2size = 0; 595 if (testval != 0) { 596 while ((testval & 1) == 0) 597 { 598 ln2size++; 599 testval >>= 1; 600 } 601 } 602 return (ln2size); 603 } 604 605 /* return log2 of address range supported by map register */ 606 607 static int 608 pci_maprange(uint64_t mapreg) 609 { 610 int ln2range = 0; 611 612 if (PCI_BAR_IO(mapreg)) 613 ln2range = 32; 614 else 615 switch (mapreg & PCIM_BAR_MEM_TYPE) { 616 case PCIM_BAR_MEM_32: 617 ln2range = 32; 618 break; 619 case PCIM_BAR_MEM_1MB: 620 ln2range = 20; 621 break; 622 case PCIM_BAR_MEM_64: 623 ln2range = 64; 624 break; 625 } 626 return (ln2range); 627 } 628 629 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 630 631 static void 632 pci_fixancient(pcicfgregs *cfg) 633 { 634 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 635 return; 636 637 /* PCI to PCI bridges use header type 1 */ 638 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 639 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; 640 } 641 642 /* extract header type specific config data */ 643 644 static void 645 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 646 { 647 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 648 switch (cfg->hdrtype & PCIM_HDRTYPE) { 649 case PCIM_HDRTYPE_NORMAL: 650 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 651 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 652 cfg->mingnt = REG(PCIR_MINGNT, 1); 653 cfg->maxlat = REG(PCIR_MAXLAT, 1); 654 cfg->nummaps = PCI_MAXMAPS_0; 655 break; 656 case PCIM_HDRTYPE_BRIDGE: 657 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1); 658 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1); 659 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1); 660 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1); 661 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2); 662 cfg->nummaps = PCI_MAXMAPS_1; 663 break; 664 case PCIM_HDRTYPE_CARDBUS: 665 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1); 666 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1); 667 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1); 668 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1); 669 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2); 670 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 671 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 672 cfg->nummaps = PCI_MAXMAPS_2; 673 break; 674 } 675 #undef REG 676 } 677 678 /* read configuration header into pcicfgregs structure */ 679 struct pci_devinfo * 680 pci_read_device(device_t pcib, device_t bus, int d, int b, int s, int f) 681 { 682 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 683 uint16_t vid, did; 684 685 vid = REG(PCIR_VENDOR, 2); 686 did = REG(PCIR_DEVICE, 2); 687 if (vid != 0xffff) 688 return (pci_fill_devinfo(pcib, bus, d, b, s, f, vid, did)); 689 690 return (NULL); 691 } 692 693 struct pci_devinfo * 694 pci_alloc_devinfo_method(device_t dev) 695 { 696 697 return (malloc(sizeof(struct pci_devinfo), M_DEVBUF, 698 M_WAITOK | M_ZERO)); 699 } 700 701 static struct pci_devinfo * 702 pci_fill_devinfo(device_t pcib, device_t bus, int d, int b, int s, int f, 703 uint16_t vid, uint16_t did) 704 { 705 struct pci_devinfo *devlist_entry; 706 pcicfgregs *cfg; 707 708 devlist_entry = PCI_ALLOC_DEVINFO(bus); 709 710 cfg = &devlist_entry->cfg; 711 712 cfg->domain = d; 713 cfg->bus = b; 714 cfg->slot = s; 715 cfg->func = f; 716 cfg->vendor = vid; 717 cfg->device = did; 718 cfg->cmdreg = REG(PCIR_COMMAND, 2); 719 cfg->statreg = REG(PCIR_STATUS, 2); 720 cfg->baseclass = REG(PCIR_CLASS, 1); 721 cfg->subclass = REG(PCIR_SUBCLASS, 1); 722 cfg->progif = REG(PCIR_PROGIF, 1); 723 cfg->revid = REG(PCIR_REVID, 1); 724 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 725 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 726 cfg->lattimer = REG(PCIR_LATTIMER, 1); 727 cfg->intpin = REG(PCIR_INTPIN, 1); 728 cfg->intline = REG(PCIR_INTLINE, 1); 729 730 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 731 cfg->hdrtype &= ~PCIM_MFDEV; 732 STAILQ_INIT(&cfg->maps); 733 734 cfg->iov = NULL; 735 736 pci_fixancient(cfg); 737 pci_hdrtypedata(pcib, b, s, f, cfg); 738 739 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 740 pci_read_cap(pcib, cfg); 741 742 STAILQ_INSERT_TAIL(&pci_devq, devlist_entry, pci_links); 743 744 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; 745 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 746 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 747 devlist_entry->conf.pc_sel.pc_func = cfg->func; 748 devlist_entry->conf.pc_hdr = cfg->hdrtype; 749 750 devlist_entry->conf.pc_subvendor = cfg->subvendor; 751 devlist_entry->conf.pc_subdevice = cfg->subdevice; 752 devlist_entry->conf.pc_vendor = cfg->vendor; 753 devlist_entry->conf.pc_device = cfg->device; 754 755 devlist_entry->conf.pc_class = cfg->baseclass; 756 devlist_entry->conf.pc_subclass = cfg->subclass; 757 devlist_entry->conf.pc_progif = cfg->progif; 758 devlist_entry->conf.pc_revid = cfg->revid; 759 760 pci_numdevs++; 761 pci_generation++; 762 763 return (devlist_entry); 764 } 765 #undef REG 766 767 static void 768 pci_ea_fill_info(device_t pcib, pcicfgregs *cfg) 769 { 770 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \ 771 cfg->ea.ea_location + (n), w) 772 int num_ent; 773 int ptr; 774 int a, b; 775 uint32_t val; 776 int ent_size; 777 uint32_t dw[4]; 778 uint64_t base, max_offset; 779 struct pci_ea_entry *eae; 780 781 if (cfg->ea.ea_location == 0) 782 return; 783 784 STAILQ_INIT(&cfg->ea.ea_entries); 785 786 /* Determine the number of entries */ 787 num_ent = REG(PCIR_EA_NUM_ENT, 2); 788 num_ent &= PCIM_EA_NUM_ENT_MASK; 789 790 /* Find the first entry to care of */ 791 ptr = PCIR_EA_FIRST_ENT; 792 793 /* Skip DWORD 2 for type 1 functions */ 794 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) 795 ptr += 4; 796 797 for (a = 0; a < num_ent; a++) { 798 eae = malloc(sizeof(*eae), M_DEVBUF, M_WAITOK | M_ZERO); 799 eae->eae_cfg_offset = cfg->ea.ea_location + ptr; 800 801 /* Read a number of dwords in the entry */ 802 val = REG(ptr, 4); 803 ptr += 4; 804 ent_size = (val & PCIM_EA_ES); 805 806 for (b = 0; b < ent_size; b++) { 807 dw[b] = REG(ptr, 4); 808 ptr += 4; 809 } 810 811 eae->eae_flags = val; 812 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 813 814 base = dw[0] & PCIM_EA_FIELD_MASK; 815 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 816 b = 2; 817 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 818 base |= (uint64_t)dw[b] << 32UL; 819 b++; 820 } 821 if (((dw[1] & PCIM_EA_IS_64) != 0) 822 && (b < ent_size)) { 823 max_offset |= (uint64_t)dw[b] << 32UL; 824 b++; 825 } 826 827 eae->eae_base = base; 828 eae->eae_max_offset = max_offset; 829 830 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link); 831 832 if (bootverbose) { 833 printf("PCI(EA) dev %04x:%04x, bei %d, flags #%x, base #%jx, max_offset #%jx\n", 834 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags, 835 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset); 836 } 837 } 838 } 839 #undef REG 840 841 static void 842 pci_read_cap(device_t pcib, pcicfgregs *cfg) 843 { 844 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 845 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 846 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 847 uint64_t addr; 848 #endif 849 uint32_t val; 850 int ptr, nextptr, ptrptr; 851 852 switch (cfg->hdrtype & PCIM_HDRTYPE) { 853 case PCIM_HDRTYPE_NORMAL: 854 case PCIM_HDRTYPE_BRIDGE: 855 ptrptr = PCIR_CAP_PTR; 856 break; 857 case PCIM_HDRTYPE_CARDBUS: 858 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 859 break; 860 default: 861 return; /* no extended capabilities support */ 862 } 863 nextptr = REG(ptrptr, 1); /* sanity check? */ 864 865 /* 866 * Read capability entries. 867 */ 868 while (nextptr != 0) { 869 /* Sanity check */ 870 if (nextptr > 255) { 871 printf("illegal PCI extended capability offset %d\n", 872 nextptr); 873 return; 874 } 875 /* Find the next entry */ 876 ptr = nextptr; 877 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 878 879 /* Process this entry */ 880 switch (REG(ptr + PCICAP_ID, 1)) { 881 case PCIY_PMG: /* PCI power management */ 882 if (cfg->pp.pp_cap == 0) { 883 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 884 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 885 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE; 886 if ((nextptr - ptr) > PCIR_POWER_DATA) 887 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 888 } 889 break; 890 case PCIY_HT: /* HyperTransport */ 891 /* Determine HT-specific capability type. */ 892 val = REG(ptr + PCIR_HT_COMMAND, 2); 893 894 if ((val & 0xe000) == PCIM_HTCAP_SLAVE) 895 cfg->ht.ht_slave = ptr; 896 897 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 898 switch (val & PCIM_HTCMD_CAP_MASK) { 899 case PCIM_HTCAP_MSI_MAPPING: 900 if (!(val & PCIM_HTCMD_MSI_FIXED)) { 901 /* Sanity check the mapping window. */ 902 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 903 4); 904 addr <<= 32; 905 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 906 4); 907 if (addr != MSI_INTEL_ADDR_BASE) 908 device_printf(pcib, 909 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", 910 cfg->domain, cfg->bus, 911 cfg->slot, cfg->func, 912 (long long)addr); 913 } else 914 addr = MSI_INTEL_ADDR_BASE; 915 916 cfg->ht.ht_msimap = ptr; 917 cfg->ht.ht_msictrl = val; 918 cfg->ht.ht_msiaddr = addr; 919 break; 920 } 921 #endif 922 break; 923 case PCIY_MSI: /* PCI MSI */ 924 cfg->msi.msi_location = ptr; 925 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 926 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 927 PCIM_MSICTRL_MMC_MASK)>>1); 928 break; 929 case PCIY_MSIX: /* PCI MSI-X */ 930 cfg->msix.msix_location = ptr; 931 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 932 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl & 933 PCIM_MSIXCTRL_TABLE_SIZE) + 1; 934 val = REG(ptr + PCIR_MSIX_TABLE, 4); 935 cfg->msix.msix_table_bar = PCIR_BAR(val & 936 PCIM_MSIX_BIR_MASK); 937 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 938 val = REG(ptr + PCIR_MSIX_PBA, 4); 939 cfg->msix.msix_pba_bar = PCIR_BAR(val & 940 PCIM_MSIX_BIR_MASK); 941 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 942 break; 943 case PCIY_VPD: /* PCI Vital Product Data */ 944 cfg->vpd.vpd_reg = ptr; 945 break; 946 case PCIY_SUBVENDOR: 947 /* Should always be true. */ 948 if ((cfg->hdrtype & PCIM_HDRTYPE) == 949 PCIM_HDRTYPE_BRIDGE) { 950 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4); 951 cfg->subvendor = val & 0xffff; 952 cfg->subdevice = val >> 16; 953 } 954 break; 955 case PCIY_PCIX: /* PCI-X */ 956 /* 957 * Assume we have a PCI-X chipset if we have 958 * at least one PCI-PCI bridge with a PCI-X 959 * capability. Note that some systems with 960 * PCI-express or HT chipsets might match on 961 * this check as well. 962 */ 963 if ((cfg->hdrtype & PCIM_HDRTYPE) == 964 PCIM_HDRTYPE_BRIDGE) 965 pcix_chipset = 1; 966 cfg->pcix.pcix_location = ptr; 967 break; 968 case PCIY_EXPRESS: /* PCI-express */ 969 /* 970 * Assume we have a PCI-express chipset if we have 971 * at least one PCI-express device. 972 */ 973 pcie_chipset = 1; 974 cfg->pcie.pcie_location = ptr; 975 val = REG(ptr + PCIER_FLAGS, 2); 976 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; 977 break; 978 case PCIY_EA: /* Enhanced Allocation */ 979 cfg->ea.ea_location = ptr; 980 pci_ea_fill_info(pcib, cfg); 981 break; 982 default: 983 break; 984 } 985 } 986 987 #if defined(__powerpc__) 988 /* 989 * Enable the MSI mapping window for all HyperTransport 990 * slaves. PCI-PCI bridges have their windows enabled via 991 * PCIB_MAP_MSI(). 992 */ 993 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && 994 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { 995 device_printf(pcib, 996 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n", 997 cfg->domain, cfg->bus, cfg->slot, cfg->func); 998 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 999 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, 1000 2); 1001 } 1002 #endif 1003 /* REG and WREG use carry through to next functions */ 1004 } 1005 1006 /* 1007 * PCI Vital Product Data 1008 */ 1009 1010 #define PCI_VPD_TIMEOUT 1000000 1011 1012 static int 1013 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data) 1014 { 1015 int count = PCI_VPD_TIMEOUT; 1016 1017 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1018 1019 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); 1020 1021 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { 1022 if (--count < 0) 1023 return (ENXIO); 1024 DELAY(1); /* limit looping */ 1025 } 1026 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); 1027 1028 return (0); 1029 } 1030 1031 #if 0 1032 static int 1033 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 1034 { 1035 int count = PCI_VPD_TIMEOUT; 1036 1037 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1038 1039 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4); 1040 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2); 1041 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) { 1042 if (--count < 0) 1043 return (ENXIO); 1044 DELAY(1); /* limit looping */ 1045 } 1046 1047 return (0); 1048 } 1049 #endif 1050 1051 #undef PCI_VPD_TIMEOUT 1052 1053 struct vpd_readstate { 1054 device_t pcib; 1055 pcicfgregs *cfg; 1056 uint32_t val; 1057 int bytesinval; 1058 int off; 1059 uint8_t cksum; 1060 }; 1061 1062 static int 1063 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data) 1064 { 1065 uint32_t reg; 1066 uint8_t byte; 1067 1068 if (vrs->bytesinval == 0) { 1069 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) 1070 return (ENXIO); 1071 vrs->val = le32toh(reg); 1072 vrs->off += 4; 1073 byte = vrs->val & 0xff; 1074 vrs->bytesinval = 3; 1075 } else { 1076 vrs->val = vrs->val >> 8; 1077 byte = vrs->val & 0xff; 1078 vrs->bytesinval--; 1079 } 1080 1081 vrs->cksum += byte; 1082 *data = byte; 1083 return (0); 1084 } 1085 1086 static void 1087 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 1088 { 1089 struct vpd_readstate vrs; 1090 int state; 1091 int name; 1092 int remain; 1093 int i; 1094 int alloc, off; /* alloc/off for RO/W arrays */ 1095 int cksumvalid; 1096 int dflen; 1097 uint8_t byte; 1098 uint8_t byte2; 1099 1100 /* init vpd reader */ 1101 vrs.bytesinval = 0; 1102 vrs.off = 0; 1103 vrs.pcib = pcib; 1104 vrs.cfg = cfg; 1105 vrs.cksum = 0; 1106 1107 state = 0; 1108 name = remain = i = 0; /* shut up stupid gcc */ 1109 alloc = off = 0; /* shut up stupid gcc */ 1110 dflen = 0; /* shut up stupid gcc */ 1111 cksumvalid = -1; 1112 while (state >= 0) { 1113 if (vpd_nextbyte(&vrs, &byte)) { 1114 state = -2; 1115 break; 1116 } 1117 #if 0 1118 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \ 1119 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val, 1120 vrs.off, vrs.bytesinval, byte, state, remain, name, i); 1121 #endif 1122 switch (state) { 1123 case 0: /* item name */ 1124 if (byte & 0x80) { 1125 if (vpd_nextbyte(&vrs, &byte2)) { 1126 state = -2; 1127 break; 1128 } 1129 remain = byte2; 1130 if (vpd_nextbyte(&vrs, &byte2)) { 1131 state = -2; 1132 break; 1133 } 1134 remain |= byte2 << 8; 1135 name = byte & 0x7f; 1136 } else { 1137 remain = byte & 0x7; 1138 name = (byte >> 3) & 0xf; 1139 } 1140 if (vrs.off + remain - vrs.bytesinval > 0x8000) { 1141 pci_printf(cfg, 1142 "VPD data overflow, remain %#x\n", remain); 1143 state = -1; 1144 break; 1145 } 1146 switch (name) { 1147 case 0x2: /* String */ 1148 cfg->vpd.vpd_ident = malloc(remain + 1, 1149 M_DEVBUF, M_WAITOK); 1150 i = 0; 1151 state = 1; 1152 break; 1153 case 0xf: /* End */ 1154 state = -1; 1155 break; 1156 case 0x10: /* VPD-R */ 1157 alloc = 8; 1158 off = 0; 1159 cfg->vpd.vpd_ros = malloc(alloc * 1160 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF, 1161 M_WAITOK | M_ZERO); 1162 state = 2; 1163 break; 1164 case 0x11: /* VPD-W */ 1165 alloc = 8; 1166 off = 0; 1167 cfg->vpd.vpd_w = malloc(alloc * 1168 sizeof(*cfg->vpd.vpd_w), M_DEVBUF, 1169 M_WAITOK | M_ZERO); 1170 state = 5; 1171 break; 1172 default: /* Invalid data, abort */ 1173 state = -1; 1174 break; 1175 } 1176 break; 1177 1178 case 1: /* Identifier String */ 1179 cfg->vpd.vpd_ident[i++] = byte; 1180 remain--; 1181 if (remain == 0) { 1182 cfg->vpd.vpd_ident[i] = '\0'; 1183 state = 0; 1184 } 1185 break; 1186 1187 case 2: /* VPD-R Keyword Header */ 1188 if (off == alloc) { 1189 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1190 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros), 1191 M_DEVBUF, M_WAITOK | M_ZERO); 1192 } 1193 cfg->vpd.vpd_ros[off].keyword[0] = byte; 1194 if (vpd_nextbyte(&vrs, &byte2)) { 1195 state = -2; 1196 break; 1197 } 1198 cfg->vpd.vpd_ros[off].keyword[1] = byte2; 1199 if (vpd_nextbyte(&vrs, &byte2)) { 1200 state = -2; 1201 break; 1202 } 1203 cfg->vpd.vpd_ros[off].len = dflen = byte2; 1204 if (dflen == 0 && 1205 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV", 1206 2) == 0) { 1207 /* 1208 * if this happens, we can't trust the rest 1209 * of the VPD. 1210 */ 1211 pci_printf(cfg, "bad keyword length: %d\n", 1212 dflen); 1213 cksumvalid = 0; 1214 state = -1; 1215 break; 1216 } else if (dflen == 0) { 1217 cfg->vpd.vpd_ros[off].value = malloc(1 * 1218 sizeof(*cfg->vpd.vpd_ros[off].value), 1219 M_DEVBUF, M_WAITOK); 1220 cfg->vpd.vpd_ros[off].value[0] = '\x00'; 1221 } else 1222 cfg->vpd.vpd_ros[off].value = malloc( 1223 (dflen + 1) * 1224 sizeof(*cfg->vpd.vpd_ros[off].value), 1225 M_DEVBUF, M_WAITOK); 1226 remain -= 3; 1227 i = 0; 1228 /* keep in sync w/ state 3's transistions */ 1229 if (dflen == 0 && remain == 0) 1230 state = 0; 1231 else if (dflen == 0) 1232 state = 2; 1233 else 1234 state = 3; 1235 break; 1236 1237 case 3: /* VPD-R Keyword Value */ 1238 cfg->vpd.vpd_ros[off].value[i++] = byte; 1239 if (strncmp(cfg->vpd.vpd_ros[off].keyword, 1240 "RV", 2) == 0 && cksumvalid == -1) { 1241 if (vrs.cksum == 0) 1242 cksumvalid = 1; 1243 else { 1244 if (bootverbose) 1245 pci_printf(cfg, 1246 "bad VPD cksum, remain %hhu\n", 1247 vrs.cksum); 1248 cksumvalid = 0; 1249 state = -1; 1250 break; 1251 } 1252 } 1253 dflen--; 1254 remain--; 1255 /* keep in sync w/ state 2's transistions */ 1256 if (dflen == 0) 1257 cfg->vpd.vpd_ros[off++].value[i++] = '\0'; 1258 if (dflen == 0 && remain == 0) { 1259 cfg->vpd.vpd_rocnt = off; 1260 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1261 off * sizeof(*cfg->vpd.vpd_ros), 1262 M_DEVBUF, M_WAITOK | M_ZERO); 1263 state = 0; 1264 } else if (dflen == 0) 1265 state = 2; 1266 break; 1267 1268 case 4: 1269 remain--; 1270 if (remain == 0) 1271 state = 0; 1272 break; 1273 1274 case 5: /* VPD-W Keyword Header */ 1275 if (off == alloc) { 1276 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1277 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w), 1278 M_DEVBUF, M_WAITOK | M_ZERO); 1279 } 1280 cfg->vpd.vpd_w[off].keyword[0] = byte; 1281 if (vpd_nextbyte(&vrs, &byte2)) { 1282 state = -2; 1283 break; 1284 } 1285 cfg->vpd.vpd_w[off].keyword[1] = byte2; 1286 if (vpd_nextbyte(&vrs, &byte2)) { 1287 state = -2; 1288 break; 1289 } 1290 cfg->vpd.vpd_w[off].len = dflen = byte2; 1291 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval; 1292 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) * 1293 sizeof(*cfg->vpd.vpd_w[off].value), 1294 M_DEVBUF, M_WAITOK); 1295 remain -= 3; 1296 i = 0; 1297 /* keep in sync w/ state 6's transistions */ 1298 if (dflen == 0 && remain == 0) 1299 state = 0; 1300 else if (dflen == 0) 1301 state = 5; 1302 else 1303 state = 6; 1304 break; 1305 1306 case 6: /* VPD-W Keyword Value */ 1307 cfg->vpd.vpd_w[off].value[i++] = byte; 1308 dflen--; 1309 remain--; 1310 /* keep in sync w/ state 5's transistions */ 1311 if (dflen == 0) 1312 cfg->vpd.vpd_w[off++].value[i++] = '\0'; 1313 if (dflen == 0 && remain == 0) { 1314 cfg->vpd.vpd_wcnt = off; 1315 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1316 off * sizeof(*cfg->vpd.vpd_w), 1317 M_DEVBUF, M_WAITOK | M_ZERO); 1318 state = 0; 1319 } else if (dflen == 0) 1320 state = 5; 1321 break; 1322 1323 default: 1324 pci_printf(cfg, "invalid state: %d\n", state); 1325 state = -1; 1326 break; 1327 } 1328 } 1329 1330 if (cksumvalid == 0 || state < -1) { 1331 /* read-only data bad, clean up */ 1332 if (cfg->vpd.vpd_ros != NULL) { 1333 for (off = 0; cfg->vpd.vpd_ros[off].value; off++) 1334 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF); 1335 free(cfg->vpd.vpd_ros, M_DEVBUF); 1336 cfg->vpd.vpd_ros = NULL; 1337 } 1338 } 1339 if (state < -1) { 1340 /* I/O error, clean up */ 1341 pci_printf(cfg, "failed to read VPD data.\n"); 1342 if (cfg->vpd.vpd_ident != NULL) { 1343 free(cfg->vpd.vpd_ident, M_DEVBUF); 1344 cfg->vpd.vpd_ident = NULL; 1345 } 1346 if (cfg->vpd.vpd_w != NULL) { 1347 for (off = 0; cfg->vpd.vpd_w[off].value; off++) 1348 free(cfg->vpd.vpd_w[off].value, M_DEVBUF); 1349 free(cfg->vpd.vpd_w, M_DEVBUF); 1350 cfg->vpd.vpd_w = NULL; 1351 } 1352 } 1353 cfg->vpd.vpd_cached = 1; 1354 #undef REG 1355 #undef WREG 1356 } 1357 1358 int 1359 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 1360 { 1361 struct pci_devinfo *dinfo = device_get_ivars(child); 1362 pcicfgregs *cfg = &dinfo->cfg; 1363 1364 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1365 pci_read_vpd(device_get_parent(dev), cfg); 1366 1367 *identptr = cfg->vpd.vpd_ident; 1368 1369 if (*identptr == NULL) 1370 return (ENXIO); 1371 1372 return (0); 1373 } 1374 1375 int 1376 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 1377 const char **vptr) 1378 { 1379 struct pci_devinfo *dinfo = device_get_ivars(child); 1380 pcicfgregs *cfg = &dinfo->cfg; 1381 int i; 1382 1383 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1384 pci_read_vpd(device_get_parent(dev), cfg); 1385 1386 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 1387 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 1388 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { 1389 *vptr = cfg->vpd.vpd_ros[i].value; 1390 return (0); 1391 } 1392 1393 *vptr = NULL; 1394 return (ENXIO); 1395 } 1396 1397 struct pcicfg_vpd * 1398 pci_fetch_vpd_list(device_t dev) 1399 { 1400 struct pci_devinfo *dinfo = device_get_ivars(dev); 1401 pcicfgregs *cfg = &dinfo->cfg; 1402 1403 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1404 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg); 1405 return (&cfg->vpd); 1406 } 1407 1408 /* 1409 * Find the requested HyperTransport capability and return the offset 1410 * in configuration space via the pointer provided. The function 1411 * returns 0 on success and an error code otherwise. 1412 */ 1413 int 1414 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg) 1415 { 1416 int ptr, error; 1417 uint16_t val; 1418 1419 error = pci_find_cap(child, PCIY_HT, &ptr); 1420 if (error) 1421 return (error); 1422 1423 /* 1424 * Traverse the capabilities list checking each HT capability 1425 * to see if it matches the requested HT capability. 1426 */ 1427 for (;;) { 1428 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1429 if (capability == PCIM_HTCAP_SLAVE || 1430 capability == PCIM_HTCAP_HOST) 1431 val &= 0xe000; 1432 else 1433 val &= PCIM_HTCMD_CAP_MASK; 1434 if (val == capability) { 1435 if (capreg != NULL) 1436 *capreg = ptr; 1437 return (0); 1438 } 1439 1440 /* Skip to the next HT capability. */ 1441 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1442 break; 1443 } 1444 1445 return (ENOENT); 1446 } 1447 1448 /* 1449 * Find the next requested HyperTransport capability after start and return 1450 * the offset in configuration space via the pointer provided. The function 1451 * returns 0 on success and an error code otherwise. 1452 */ 1453 int 1454 pci_find_next_htcap_method(device_t dev, device_t child, int capability, 1455 int start, int *capreg) 1456 { 1457 int ptr; 1458 uint16_t val; 1459 1460 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == PCIY_HT, 1461 ("start capability is not HyperTransport capability")); 1462 ptr = start; 1463 1464 /* 1465 * Traverse the capabilities list checking each HT capability 1466 * to see if it matches the requested HT capability. 1467 */ 1468 for (;;) { 1469 /* Skip to the next HT capability. */ 1470 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1471 break; 1472 1473 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1474 if (capability == PCIM_HTCAP_SLAVE || 1475 capability == PCIM_HTCAP_HOST) 1476 val &= 0xe000; 1477 else 1478 val &= PCIM_HTCMD_CAP_MASK; 1479 if (val == capability) { 1480 if (capreg != NULL) 1481 *capreg = ptr; 1482 return (0); 1483 } 1484 } 1485 1486 return (ENOENT); 1487 } 1488 1489 /* 1490 * Find the requested capability and return the offset in 1491 * configuration space via the pointer provided. The function returns 1492 * 0 on success and an error code otherwise. 1493 */ 1494 int 1495 pci_find_cap_method(device_t dev, device_t child, int capability, 1496 int *capreg) 1497 { 1498 struct pci_devinfo *dinfo = device_get_ivars(child); 1499 pcicfgregs *cfg = &dinfo->cfg; 1500 uint32_t status; 1501 uint8_t ptr; 1502 1503 /* 1504 * Check the CAP_LIST bit of the PCI status register first. 1505 */ 1506 status = pci_read_config(child, PCIR_STATUS, 2); 1507 if (!(status & PCIM_STATUS_CAPPRESENT)) 1508 return (ENXIO); 1509 1510 /* 1511 * Determine the start pointer of the capabilities list. 1512 */ 1513 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1514 case PCIM_HDRTYPE_NORMAL: 1515 case PCIM_HDRTYPE_BRIDGE: 1516 ptr = PCIR_CAP_PTR; 1517 break; 1518 case PCIM_HDRTYPE_CARDBUS: 1519 ptr = PCIR_CAP_PTR_2; 1520 break; 1521 default: 1522 /* XXX: panic? */ 1523 return (ENXIO); /* no extended capabilities support */ 1524 } 1525 ptr = pci_read_config(child, ptr, 1); 1526 1527 /* 1528 * Traverse the capabilities list. 1529 */ 1530 while (ptr != 0) { 1531 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1532 if (capreg != NULL) 1533 *capreg = ptr; 1534 return (0); 1535 } 1536 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1537 } 1538 1539 return (ENOENT); 1540 } 1541 1542 /* 1543 * Find the next requested capability after start and return the offset in 1544 * configuration space via the pointer provided. The function returns 1545 * 0 on success and an error code otherwise. 1546 */ 1547 int 1548 pci_find_next_cap_method(device_t dev, device_t child, int capability, 1549 int start, int *capreg) 1550 { 1551 uint8_t ptr; 1552 1553 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == capability, 1554 ("start capability is not expected capability")); 1555 1556 ptr = pci_read_config(child, start + PCICAP_NEXTPTR, 1); 1557 while (ptr != 0) { 1558 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1559 if (capreg != NULL) 1560 *capreg = ptr; 1561 return (0); 1562 } 1563 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1564 } 1565 1566 return (ENOENT); 1567 } 1568 1569 /* 1570 * Find the requested extended capability and return the offset in 1571 * configuration space via the pointer provided. The function returns 1572 * 0 on success and an error code otherwise. 1573 */ 1574 int 1575 pci_find_extcap_method(device_t dev, device_t child, int capability, 1576 int *capreg) 1577 { 1578 struct pci_devinfo *dinfo = device_get_ivars(child); 1579 pcicfgregs *cfg = &dinfo->cfg; 1580 uint32_t ecap; 1581 uint16_t ptr; 1582 1583 /* Only supported for PCI-express devices. */ 1584 if (cfg->pcie.pcie_location == 0) 1585 return (ENXIO); 1586 1587 ptr = PCIR_EXTCAP; 1588 ecap = pci_read_config(child, ptr, 4); 1589 if (ecap == 0xffffffff || ecap == 0) 1590 return (ENOENT); 1591 for (;;) { 1592 if (PCI_EXTCAP_ID(ecap) == capability) { 1593 if (capreg != NULL) 1594 *capreg = ptr; 1595 return (0); 1596 } 1597 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1598 if (ptr == 0) 1599 break; 1600 ecap = pci_read_config(child, ptr, 4); 1601 } 1602 1603 return (ENOENT); 1604 } 1605 1606 /* 1607 * Find the next requested extended capability after start and return the 1608 * offset in configuration space via the pointer provided. The function 1609 * returns 0 on success and an error code otherwise. 1610 */ 1611 int 1612 pci_find_next_extcap_method(device_t dev, device_t child, int capability, 1613 int start, int *capreg) 1614 { 1615 struct pci_devinfo *dinfo = device_get_ivars(child); 1616 pcicfgregs *cfg = &dinfo->cfg; 1617 uint32_t ecap; 1618 uint16_t ptr; 1619 1620 /* Only supported for PCI-express devices. */ 1621 if (cfg->pcie.pcie_location == 0) 1622 return (ENXIO); 1623 1624 ecap = pci_read_config(child, start, 4); 1625 KASSERT(PCI_EXTCAP_ID(ecap) == capability, 1626 ("start extended capability is not expected capability")); 1627 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1628 while (ptr != 0) { 1629 ecap = pci_read_config(child, ptr, 4); 1630 if (PCI_EXTCAP_ID(ecap) == capability) { 1631 if (capreg != NULL) 1632 *capreg = ptr; 1633 return (0); 1634 } 1635 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1636 } 1637 1638 return (ENOENT); 1639 } 1640 1641 /* 1642 * Support for MSI-X message interrupts. 1643 */ 1644 static void 1645 pci_write_msix_entry(device_t dev, u_int index, uint64_t address, uint32_t data) 1646 { 1647 struct pci_devinfo *dinfo = device_get_ivars(dev); 1648 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1649 uint32_t offset; 1650 1651 KASSERT(msix->msix_table_len > index, ("bogus index")); 1652 offset = msix->msix_table_offset + index * 16; 1653 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); 1654 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); 1655 bus_write_4(msix->msix_table_res, offset + 8, data); 1656 } 1657 1658 void 1659 pci_enable_msix_method(device_t dev, device_t child, u_int index, 1660 uint64_t address, uint32_t data) 1661 { 1662 1663 if (pci_msix_rewrite_table) { 1664 struct pci_devinfo *dinfo = device_get_ivars(child); 1665 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1666 1667 /* 1668 * Some VM hosts require MSIX to be disabled in the 1669 * control register before updating the MSIX table 1670 * entries are allowed. It is not enough to only 1671 * disable MSIX while updating a single entry. MSIX 1672 * must be disabled while updating all entries in the 1673 * table. 1674 */ 1675 pci_write_config(child, 1676 msix->msix_location + PCIR_MSIX_CTRL, 1677 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2); 1678 pci_resume_msix(child); 1679 } else 1680 pci_write_msix_entry(child, index, address, data); 1681 1682 /* Enable MSI -> HT mapping. */ 1683 pci_ht_map_msi(child, address); 1684 } 1685 1686 void 1687 pci_mask_msix(device_t dev, u_int index) 1688 { 1689 struct pci_devinfo *dinfo = device_get_ivars(dev); 1690 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1691 uint32_t offset, val; 1692 1693 KASSERT(msix->msix_msgnum > index, ("bogus index")); 1694 offset = msix->msix_table_offset + index * 16 + 12; 1695 val = bus_read_4(msix->msix_table_res, offset); 1696 val |= PCIM_MSIX_VCTRL_MASK; 1697 1698 /* 1699 * Some devices (e.g. Samsung PM961) do not support reads of this 1700 * register, so always write the new value. 1701 */ 1702 bus_write_4(msix->msix_table_res, offset, val); 1703 } 1704 1705 void 1706 pci_unmask_msix(device_t dev, u_int index) 1707 { 1708 struct pci_devinfo *dinfo = device_get_ivars(dev); 1709 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1710 uint32_t offset, val; 1711 1712 KASSERT(msix->msix_table_len > index, ("bogus index")); 1713 offset = msix->msix_table_offset + index * 16 + 12; 1714 val = bus_read_4(msix->msix_table_res, offset); 1715 val &= ~PCIM_MSIX_VCTRL_MASK; 1716 1717 /* 1718 * Some devices (e.g. Samsung PM961) do not support reads of this 1719 * register, so always write the new value. 1720 */ 1721 bus_write_4(msix->msix_table_res, offset, val); 1722 } 1723 1724 int 1725 pci_pending_msix(device_t dev, u_int index) 1726 { 1727 struct pci_devinfo *dinfo = device_get_ivars(dev); 1728 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1729 uint32_t offset, bit; 1730 1731 KASSERT(msix->msix_table_len > index, ("bogus index")); 1732 offset = msix->msix_pba_offset + (index / 32) * 4; 1733 bit = 1 << index % 32; 1734 return (bus_read_4(msix->msix_pba_res, offset) & bit); 1735 } 1736 1737 /* 1738 * Restore MSI-X registers and table during resume. If MSI-X is 1739 * enabled then walk the virtual table to restore the actual MSI-X 1740 * table. 1741 */ 1742 static void 1743 pci_resume_msix(device_t dev) 1744 { 1745 struct pci_devinfo *dinfo = device_get_ivars(dev); 1746 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1747 struct msix_table_entry *mte; 1748 struct msix_vector *mv; 1749 int i; 1750 1751 if (msix->msix_alloc > 0) { 1752 /* First, mask all vectors. */ 1753 for (i = 0; i < msix->msix_msgnum; i++) 1754 pci_mask_msix(dev, i); 1755 1756 /* Second, program any messages with at least one handler. */ 1757 for (i = 0; i < msix->msix_table_len; i++) { 1758 mte = &msix->msix_table[i]; 1759 if (mte->mte_vector == 0 || mte->mte_handlers == 0) 1760 continue; 1761 mv = &msix->msix_vectors[mte->mte_vector - 1]; 1762 pci_write_msix_entry(dev, i, mv->mv_address, 1763 mv->mv_data); 1764 pci_unmask_msix(dev, i); 1765 } 1766 } 1767 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, 1768 msix->msix_ctrl, 2); 1769 } 1770 1771 /* 1772 * Attempt to allocate *count MSI-X messages. The actual number allocated is 1773 * returned in *count. After this function returns, each message will be 1774 * available to the driver as SYS_RES_IRQ resources starting at rid 1. 1775 */ 1776 int 1777 pci_alloc_msix_method(device_t dev, device_t child, int *count) 1778 { 1779 struct pci_devinfo *dinfo = device_get_ivars(child); 1780 pcicfgregs *cfg = &dinfo->cfg; 1781 struct resource_list_entry *rle; 1782 int actual, error, i, irq, max; 1783 1784 /* Don't let count == 0 get us into trouble. */ 1785 if (*count == 0) 1786 return (EINVAL); 1787 1788 /* If rid 0 is allocated, then fail. */ 1789 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1790 if (rle != NULL && rle->res != NULL) 1791 return (ENXIO); 1792 1793 /* Already have allocated messages? */ 1794 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1795 return (ENXIO); 1796 1797 /* If MSI-X is blacklisted for this system, fail. */ 1798 if (pci_msix_blacklisted()) 1799 return (ENXIO); 1800 1801 /* MSI-X capability present? */ 1802 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1803 return (ENODEV); 1804 1805 /* Make sure the appropriate BARs are mapped. */ 1806 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1807 cfg->msix.msix_table_bar); 1808 if (rle == NULL || rle->res == NULL || 1809 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1810 return (ENXIO); 1811 cfg->msix.msix_table_res = rle->res; 1812 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1813 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1814 cfg->msix.msix_pba_bar); 1815 if (rle == NULL || rle->res == NULL || 1816 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1817 return (ENXIO); 1818 } 1819 cfg->msix.msix_pba_res = rle->res; 1820 1821 if (bootverbose) 1822 device_printf(child, 1823 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1824 *count, cfg->msix.msix_msgnum); 1825 max = min(*count, cfg->msix.msix_msgnum); 1826 for (i = 0; i < max; i++) { 1827 /* Allocate a message. */ 1828 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq); 1829 if (error) { 1830 if (i == 0) 1831 return (error); 1832 break; 1833 } 1834 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1835 irq, 1); 1836 } 1837 actual = i; 1838 1839 if (bootverbose) { 1840 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1841 if (actual == 1) 1842 device_printf(child, "using IRQ %ju for MSI-X\n", 1843 rle->start); 1844 else { 1845 int run; 1846 1847 /* 1848 * Be fancy and try to print contiguous runs of 1849 * IRQ values as ranges. 'irq' is the previous IRQ. 1850 * 'run' is true if we are in a range. 1851 */ 1852 device_printf(child, "using IRQs %ju", rle->start); 1853 irq = rle->start; 1854 run = 0; 1855 for (i = 1; i < actual; i++) { 1856 rle = resource_list_find(&dinfo->resources, 1857 SYS_RES_IRQ, i + 1); 1858 1859 /* Still in a run? */ 1860 if (rle->start == irq + 1) { 1861 run = 1; 1862 irq++; 1863 continue; 1864 } 1865 1866 /* Finish previous range. */ 1867 if (run) { 1868 printf("-%d", irq); 1869 run = 0; 1870 } 1871 1872 /* Start new range. */ 1873 printf(",%ju", rle->start); 1874 irq = rle->start; 1875 } 1876 1877 /* Unfinished range? */ 1878 if (run) 1879 printf("-%d", irq); 1880 printf(" for MSI-X\n"); 1881 } 1882 } 1883 1884 /* Mask all vectors. */ 1885 for (i = 0; i < cfg->msix.msix_msgnum; i++) 1886 pci_mask_msix(child, i); 1887 1888 /* Allocate and initialize vector data and virtual table. */ 1889 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual, 1890 M_DEVBUF, M_WAITOK | M_ZERO); 1891 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual, 1892 M_DEVBUF, M_WAITOK | M_ZERO); 1893 for (i = 0; i < actual; i++) { 1894 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1895 cfg->msix.msix_vectors[i].mv_irq = rle->start; 1896 cfg->msix.msix_table[i].mte_vector = i + 1; 1897 } 1898 1899 /* Update control register to enable MSI-X. */ 1900 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1901 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1902 cfg->msix.msix_ctrl, 2); 1903 1904 /* Update counts of alloc'd messages. */ 1905 cfg->msix.msix_alloc = actual; 1906 cfg->msix.msix_table_len = actual; 1907 *count = actual; 1908 return (0); 1909 } 1910 1911 /* 1912 * By default, pci_alloc_msix() will assign the allocated IRQ 1913 * resources consecutively to the first N messages in the MSI-X table. 1914 * However, device drivers may want to use different layouts if they 1915 * either receive fewer messages than they asked for, or they wish to 1916 * populate the MSI-X table sparsely. This method allows the driver 1917 * to specify what layout it wants. It must be called after a 1918 * successful pci_alloc_msix() but before any of the associated 1919 * SYS_RES_IRQ resources are allocated via bus_alloc_resource(). 1920 * 1921 * The 'vectors' array contains 'count' message vectors. The array 1922 * maps directly to the MSI-X table in that index 0 in the array 1923 * specifies the vector for the first message in the MSI-X table, etc. 1924 * The vector value in each array index can either be 0 to indicate 1925 * that no vector should be assigned to a message slot, or it can be a 1926 * number from 1 to N (where N is the count returned from a 1927 * succcessful call to pci_alloc_msix()) to indicate which message 1928 * vector (IRQ) to be used for the corresponding message. 1929 * 1930 * On successful return, each message with a non-zero vector will have 1931 * an associated SYS_RES_IRQ whose rid is equal to the array index + 1932 * 1. Additionally, if any of the IRQs allocated via the previous 1933 * call to pci_alloc_msix() are not used in the mapping, those IRQs 1934 * will be freed back to the system automatically. 1935 * 1936 * For example, suppose a driver has a MSI-X table with 6 messages and 1937 * asks for 6 messages, but pci_alloc_msix() only returns a count of 1938 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and 1939 * C. After the call to pci_alloc_msix(), the device will be setup to 1940 * have an MSI-X table of ABC--- (where - means no vector assigned). 1941 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 }, 1942 * then the MSI-X table will look like A-AB-B, and the 'C' vector will 1943 * be freed back to the system. This device will also have valid 1944 * SYS_RES_IRQ rids of 1, 3, 4, and 6. 1945 * 1946 * In any case, the SYS_RES_IRQ rid X will always map to the message 1947 * at MSI-X table index X - 1 and will only be valid if a vector is 1948 * assigned to that table entry. 1949 */ 1950 int 1951 pci_remap_msix_method(device_t dev, device_t child, int count, 1952 const u_int *vectors) 1953 { 1954 struct pci_devinfo *dinfo = device_get_ivars(child); 1955 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1956 struct resource_list_entry *rle; 1957 int i, irq, j, *used; 1958 1959 /* 1960 * Have to have at least one message in the table but the 1961 * table can't be bigger than the actual MSI-X table in the 1962 * device. 1963 */ 1964 if (count == 0 || count > msix->msix_msgnum) 1965 return (EINVAL); 1966 1967 /* Sanity check the vectors. */ 1968 for (i = 0; i < count; i++) 1969 if (vectors[i] > msix->msix_alloc) 1970 return (EINVAL); 1971 1972 /* 1973 * Make sure there aren't any holes in the vectors to be used. 1974 * It's a big pain to support it, and it doesn't really make 1975 * sense anyway. Also, at least one vector must be used. 1976 */ 1977 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK | 1978 M_ZERO); 1979 for (i = 0; i < count; i++) 1980 if (vectors[i] != 0) 1981 used[vectors[i] - 1] = 1; 1982 for (i = 0; i < msix->msix_alloc - 1; i++) 1983 if (used[i] == 0 && used[i + 1] == 1) { 1984 free(used, M_DEVBUF); 1985 return (EINVAL); 1986 } 1987 if (used[0] != 1) { 1988 free(used, M_DEVBUF); 1989 return (EINVAL); 1990 } 1991 1992 /* Make sure none of the resources are allocated. */ 1993 for (i = 0; i < msix->msix_table_len; i++) { 1994 if (msix->msix_table[i].mte_vector == 0) 1995 continue; 1996 if (msix->msix_table[i].mte_handlers > 0) { 1997 free(used, M_DEVBUF); 1998 return (EBUSY); 1999 } 2000 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2001 KASSERT(rle != NULL, ("missing resource")); 2002 if (rle->res != NULL) { 2003 free(used, M_DEVBUF); 2004 return (EBUSY); 2005 } 2006 } 2007 2008 /* Free the existing resource list entries. */ 2009 for (i = 0; i < msix->msix_table_len; i++) { 2010 if (msix->msix_table[i].mte_vector == 0) 2011 continue; 2012 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2013 } 2014 2015 /* 2016 * Build the new virtual table keeping track of which vectors are 2017 * used. 2018 */ 2019 free(msix->msix_table, M_DEVBUF); 2020 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count, 2021 M_DEVBUF, M_WAITOK | M_ZERO); 2022 for (i = 0; i < count; i++) 2023 msix->msix_table[i].mte_vector = vectors[i]; 2024 msix->msix_table_len = count; 2025 2026 /* Free any unused IRQs and resize the vectors array if necessary. */ 2027 j = msix->msix_alloc - 1; 2028 if (used[j] == 0) { 2029 struct msix_vector *vec; 2030 2031 while (used[j] == 0) { 2032 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2033 msix->msix_vectors[j].mv_irq); 2034 j--; 2035 } 2036 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF, 2037 M_WAITOK); 2038 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * 2039 (j + 1)); 2040 free(msix->msix_vectors, M_DEVBUF); 2041 msix->msix_vectors = vec; 2042 msix->msix_alloc = j + 1; 2043 } 2044 free(used, M_DEVBUF); 2045 2046 /* Map the IRQs onto the rids. */ 2047 for (i = 0; i < count; i++) { 2048 if (vectors[i] == 0) 2049 continue; 2050 irq = msix->msix_vectors[vectors[i] - 1].mv_irq; 2051 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 2052 irq, 1); 2053 } 2054 2055 if (bootverbose) { 2056 device_printf(child, "Remapped MSI-X IRQs as: "); 2057 for (i = 0; i < count; i++) { 2058 if (i != 0) 2059 printf(", "); 2060 if (vectors[i] == 0) 2061 printf("---"); 2062 else 2063 printf("%d", 2064 msix->msix_vectors[vectors[i] - 1].mv_irq); 2065 } 2066 printf("\n"); 2067 } 2068 2069 return (0); 2070 } 2071 2072 static int 2073 pci_release_msix(device_t dev, device_t child) 2074 { 2075 struct pci_devinfo *dinfo = device_get_ivars(child); 2076 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2077 struct resource_list_entry *rle; 2078 int i; 2079 2080 /* Do we have any messages to release? */ 2081 if (msix->msix_alloc == 0) 2082 return (ENODEV); 2083 2084 /* Make sure none of the resources are allocated. */ 2085 for (i = 0; i < msix->msix_table_len; i++) { 2086 if (msix->msix_table[i].mte_vector == 0) 2087 continue; 2088 if (msix->msix_table[i].mte_handlers > 0) 2089 return (EBUSY); 2090 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2091 KASSERT(rle != NULL, ("missing resource")); 2092 if (rle->res != NULL) 2093 return (EBUSY); 2094 } 2095 2096 /* Update control register to disable MSI-X. */ 2097 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 2098 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, 2099 msix->msix_ctrl, 2); 2100 2101 /* Free the resource list entries. */ 2102 for (i = 0; i < msix->msix_table_len; i++) { 2103 if (msix->msix_table[i].mte_vector == 0) 2104 continue; 2105 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2106 } 2107 free(msix->msix_table, M_DEVBUF); 2108 msix->msix_table_len = 0; 2109 2110 /* Release the IRQs. */ 2111 for (i = 0; i < msix->msix_alloc; i++) 2112 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2113 msix->msix_vectors[i].mv_irq); 2114 free(msix->msix_vectors, M_DEVBUF); 2115 msix->msix_alloc = 0; 2116 return (0); 2117 } 2118 2119 /* 2120 * Return the max supported MSI-X messages this device supports. 2121 * Basically, assuming the MD code can alloc messages, this function 2122 * should return the maximum value that pci_alloc_msix() can return. 2123 * Thus, it is subject to the tunables, etc. 2124 */ 2125 int 2126 pci_msix_count_method(device_t dev, device_t child) 2127 { 2128 struct pci_devinfo *dinfo = device_get_ivars(child); 2129 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2130 2131 if (pci_do_msix && msix->msix_location != 0) 2132 return (msix->msix_msgnum); 2133 return (0); 2134 } 2135 2136 int 2137 pci_msix_pba_bar_method(device_t dev, device_t child) 2138 { 2139 struct pci_devinfo *dinfo = device_get_ivars(child); 2140 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2141 2142 if (pci_do_msix && msix->msix_location != 0) 2143 return (msix->msix_pba_bar); 2144 return (-1); 2145 } 2146 2147 int 2148 pci_msix_table_bar_method(device_t dev, device_t child) 2149 { 2150 struct pci_devinfo *dinfo = device_get_ivars(child); 2151 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2152 2153 if (pci_do_msix && msix->msix_location != 0) 2154 return (msix->msix_table_bar); 2155 return (-1); 2156 } 2157 2158 /* 2159 * HyperTransport MSI mapping control 2160 */ 2161 void 2162 pci_ht_map_msi(device_t dev, uint64_t addr) 2163 { 2164 struct pci_devinfo *dinfo = device_get_ivars(dev); 2165 struct pcicfg_ht *ht = &dinfo->cfg.ht; 2166 2167 if (!ht->ht_msimap) 2168 return; 2169 2170 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && 2171 ht->ht_msiaddr >> 20 == addr >> 20) { 2172 /* Enable MSI -> HT mapping. */ 2173 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 2174 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2175 ht->ht_msictrl, 2); 2176 } 2177 2178 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { 2179 /* Disable MSI -> HT mapping. */ 2180 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; 2181 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2182 ht->ht_msictrl, 2); 2183 } 2184 } 2185 2186 int 2187 pci_get_relaxed_ordering_enabled(device_t dev) 2188 { 2189 struct pci_devinfo *dinfo = device_get_ivars(dev); 2190 int cap; 2191 uint16_t val; 2192 2193 cap = dinfo->cfg.pcie.pcie_location; 2194 if (cap == 0) 2195 return (0); 2196 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2197 val &= PCIEM_CTL_RELAXED_ORD_ENABLE; 2198 return (val != 0); 2199 } 2200 2201 int 2202 pci_get_max_payload(device_t dev) 2203 { 2204 struct pci_devinfo *dinfo = device_get_ivars(dev); 2205 int cap; 2206 uint16_t val; 2207 2208 cap = dinfo->cfg.pcie.pcie_location; 2209 if (cap == 0) 2210 return (0); 2211 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2212 val &= PCIEM_CTL_MAX_PAYLOAD; 2213 val >>= 5; 2214 return (1 << (val + 7)); 2215 } 2216 2217 int 2218 pci_get_max_read_req(device_t dev) 2219 { 2220 struct pci_devinfo *dinfo = device_get_ivars(dev); 2221 int cap; 2222 uint16_t val; 2223 2224 cap = dinfo->cfg.pcie.pcie_location; 2225 if (cap == 0) 2226 return (0); 2227 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2228 val &= PCIEM_CTL_MAX_READ_REQUEST; 2229 val >>= 12; 2230 return (1 << (val + 7)); 2231 } 2232 2233 int 2234 pci_set_max_read_req(device_t dev, int size) 2235 { 2236 struct pci_devinfo *dinfo = device_get_ivars(dev); 2237 int cap; 2238 uint16_t val; 2239 2240 cap = dinfo->cfg.pcie.pcie_location; 2241 if (cap == 0) 2242 return (0); 2243 if (size < 128) 2244 size = 128; 2245 if (size > 4096) 2246 size = 4096; 2247 size = (1 << (fls(size) - 1)); 2248 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2249 val &= ~PCIEM_CTL_MAX_READ_REQUEST; 2250 val |= (fls(size) - 8) << 12; 2251 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2); 2252 return (size); 2253 } 2254 2255 uint32_t 2256 pcie_read_config(device_t dev, int reg, int width) 2257 { 2258 struct pci_devinfo *dinfo = device_get_ivars(dev); 2259 int cap; 2260 2261 cap = dinfo->cfg.pcie.pcie_location; 2262 if (cap == 0) { 2263 if (width == 2) 2264 return (0xffff); 2265 return (0xffffffff); 2266 } 2267 2268 return (pci_read_config(dev, cap + reg, width)); 2269 } 2270 2271 void 2272 pcie_write_config(device_t dev, int reg, uint32_t value, int width) 2273 { 2274 struct pci_devinfo *dinfo = device_get_ivars(dev); 2275 int cap; 2276 2277 cap = dinfo->cfg.pcie.pcie_location; 2278 if (cap == 0) 2279 return; 2280 pci_write_config(dev, cap + reg, value, width); 2281 } 2282 2283 /* 2284 * Adjusts a PCI-e capability register by clearing the bits in mask 2285 * and setting the bits in (value & mask). Bits not set in mask are 2286 * not adjusted. 2287 * 2288 * Returns the old value on success or all ones on failure. 2289 */ 2290 uint32_t 2291 pcie_adjust_config(device_t dev, int reg, uint32_t mask, uint32_t value, 2292 int width) 2293 { 2294 struct pci_devinfo *dinfo = device_get_ivars(dev); 2295 uint32_t old, new; 2296 int cap; 2297 2298 cap = dinfo->cfg.pcie.pcie_location; 2299 if (cap == 0) { 2300 if (width == 2) 2301 return (0xffff); 2302 return (0xffffffff); 2303 } 2304 2305 old = pci_read_config(dev, cap + reg, width); 2306 new = old & ~mask; 2307 new |= (value & mask); 2308 pci_write_config(dev, cap + reg, new, width); 2309 return (old); 2310 } 2311 2312 /* 2313 * Support for MSI message signalled interrupts. 2314 */ 2315 void 2316 pci_enable_msi_method(device_t dev, device_t child, uint64_t address, 2317 uint16_t data) 2318 { 2319 struct pci_devinfo *dinfo = device_get_ivars(child); 2320 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2321 2322 /* Write data and address values. */ 2323 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, 2324 address & 0xffffffff, 4); 2325 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2326 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, 2327 address >> 32, 4); 2328 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, 2329 data, 2); 2330 } else 2331 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, 2332 2); 2333 2334 /* Enable MSI in the control register. */ 2335 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 2336 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2337 msi->msi_ctrl, 2); 2338 2339 /* Enable MSI -> HT mapping. */ 2340 pci_ht_map_msi(child, address); 2341 } 2342 2343 void 2344 pci_disable_msi_method(device_t dev, device_t child) 2345 { 2346 struct pci_devinfo *dinfo = device_get_ivars(child); 2347 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2348 2349 /* Disable MSI -> HT mapping. */ 2350 pci_ht_map_msi(child, 0); 2351 2352 /* Disable MSI in the control register. */ 2353 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; 2354 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2355 msi->msi_ctrl, 2); 2356 } 2357 2358 /* 2359 * Restore MSI registers during resume. If MSI is enabled then 2360 * restore the data and address registers in addition to the control 2361 * register. 2362 */ 2363 static void 2364 pci_resume_msi(device_t dev) 2365 { 2366 struct pci_devinfo *dinfo = device_get_ivars(dev); 2367 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2368 uint64_t address; 2369 uint16_t data; 2370 2371 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 2372 address = msi->msi_addr; 2373 data = msi->msi_data; 2374 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 2375 address & 0xffffffff, 4); 2376 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2377 pci_write_config(dev, msi->msi_location + 2378 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 2379 pci_write_config(dev, msi->msi_location + 2380 PCIR_MSI_DATA_64BIT, data, 2); 2381 } else 2382 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, 2383 data, 2); 2384 } 2385 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 2386 2); 2387 } 2388 2389 static int 2390 pci_remap_intr_method(device_t bus, device_t dev, u_int irq) 2391 { 2392 struct pci_devinfo *dinfo = device_get_ivars(dev); 2393 pcicfgregs *cfg = &dinfo->cfg; 2394 struct resource_list_entry *rle; 2395 struct msix_table_entry *mte; 2396 struct msix_vector *mv; 2397 uint64_t addr; 2398 uint32_t data; 2399 int error, i, j; 2400 2401 /* 2402 * Handle MSI first. We try to find this IRQ among our list 2403 * of MSI IRQs. If we find it, we request updated address and 2404 * data registers and apply the results. 2405 */ 2406 if (cfg->msi.msi_alloc > 0) { 2407 /* If we don't have any active handlers, nothing to do. */ 2408 if (cfg->msi.msi_handlers == 0) 2409 return (0); 2410 for (i = 0; i < cfg->msi.msi_alloc; i++) { 2411 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 2412 i + 1); 2413 if (rle->start == irq) { 2414 error = PCIB_MAP_MSI(device_get_parent(bus), 2415 dev, irq, &addr, &data); 2416 if (error) 2417 return (error); 2418 pci_disable_msi(dev); 2419 dinfo->cfg.msi.msi_addr = addr; 2420 dinfo->cfg.msi.msi_data = data; 2421 pci_enable_msi(dev, addr, data); 2422 return (0); 2423 } 2424 } 2425 return (ENOENT); 2426 } 2427 2428 /* 2429 * For MSI-X, we check to see if we have this IRQ. If we do, 2430 * we request the updated mapping info. If that works, we go 2431 * through all the slots that use this IRQ and update them. 2432 */ 2433 if (cfg->msix.msix_alloc > 0) { 2434 for (i = 0; i < cfg->msix.msix_alloc; i++) { 2435 mv = &cfg->msix.msix_vectors[i]; 2436 if (mv->mv_irq == irq) { 2437 error = PCIB_MAP_MSI(device_get_parent(bus), 2438 dev, irq, &addr, &data); 2439 if (error) 2440 return (error); 2441 mv->mv_address = addr; 2442 mv->mv_data = data; 2443 for (j = 0; j < cfg->msix.msix_table_len; j++) { 2444 mte = &cfg->msix.msix_table[j]; 2445 if (mte->mte_vector != i + 1) 2446 continue; 2447 if (mte->mte_handlers == 0) 2448 continue; 2449 pci_mask_msix(dev, j); 2450 pci_enable_msix(dev, j, addr, data); 2451 pci_unmask_msix(dev, j); 2452 } 2453 } 2454 } 2455 return (ENOENT); 2456 } 2457 2458 return (ENOENT); 2459 } 2460 2461 /* 2462 * Returns true if the specified device is blacklisted because MSI 2463 * doesn't work. 2464 */ 2465 int 2466 pci_msi_device_blacklisted(device_t dev) 2467 { 2468 2469 if (!pci_honor_msi_blacklist) 2470 return (0); 2471 2472 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI)); 2473 } 2474 2475 /* 2476 * Determine if MSI is blacklisted globally on this system. Currently, 2477 * we just check for blacklisted chipsets as represented by the 2478 * host-PCI bridge at device 0:0:0. In the future, it may become 2479 * necessary to check other system attributes, such as the kenv values 2480 * that give the motherboard manufacturer and model number. 2481 */ 2482 static int 2483 pci_msi_blacklisted(void) 2484 { 2485 device_t dev; 2486 2487 if (!pci_honor_msi_blacklist) 2488 return (0); 2489 2490 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ 2491 if (!(pcie_chipset || pcix_chipset)) { 2492 if (vm_guest != VM_GUEST_NO) { 2493 /* 2494 * Whitelist older chipsets in virtual 2495 * machines known to support MSI. 2496 */ 2497 dev = pci_find_bsf(0, 0, 0); 2498 if (dev != NULL) 2499 return (!pci_has_quirk(pci_get_devid(dev), 2500 PCI_QUIRK_ENABLE_MSI_VM)); 2501 } 2502 return (1); 2503 } 2504 2505 dev = pci_find_bsf(0, 0, 0); 2506 if (dev != NULL) 2507 return (pci_msi_device_blacklisted(dev)); 2508 return (0); 2509 } 2510 2511 /* 2512 * Returns true if the specified device is blacklisted because MSI-X 2513 * doesn't work. Note that this assumes that if MSI doesn't work, 2514 * MSI-X doesn't either. 2515 */ 2516 int 2517 pci_msix_device_blacklisted(device_t dev) 2518 { 2519 2520 if (!pci_honor_msi_blacklist) 2521 return (0); 2522 2523 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX)) 2524 return (1); 2525 2526 return (pci_msi_device_blacklisted(dev)); 2527 } 2528 2529 /* 2530 * Determine if MSI-X is blacklisted globally on this system. If MSI 2531 * is blacklisted, assume that MSI-X is as well. Check for additional 2532 * chipsets where MSI works but MSI-X does not. 2533 */ 2534 static int 2535 pci_msix_blacklisted(void) 2536 { 2537 device_t dev; 2538 2539 if (!pci_honor_msi_blacklist) 2540 return (0); 2541 2542 dev = pci_find_bsf(0, 0, 0); 2543 if (dev != NULL && pci_has_quirk(pci_get_devid(dev), 2544 PCI_QUIRK_DISABLE_MSIX)) 2545 return (1); 2546 2547 return (pci_msi_blacklisted()); 2548 } 2549 2550 /* 2551 * Attempt to allocate *count MSI messages. The actual number allocated is 2552 * returned in *count. After this function returns, each message will be 2553 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 2554 */ 2555 int 2556 pci_alloc_msi_method(device_t dev, device_t child, int *count) 2557 { 2558 struct pci_devinfo *dinfo = device_get_ivars(child); 2559 pcicfgregs *cfg = &dinfo->cfg; 2560 struct resource_list_entry *rle; 2561 int actual, error, i, irqs[32]; 2562 uint16_t ctrl; 2563 2564 /* Don't let count == 0 get us into trouble. */ 2565 if (*count == 0) 2566 return (EINVAL); 2567 2568 /* If rid 0 is allocated, then fail. */ 2569 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 2570 if (rle != NULL && rle->res != NULL) 2571 return (ENXIO); 2572 2573 /* Already have allocated messages? */ 2574 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 2575 return (ENXIO); 2576 2577 /* If MSI is blacklisted for this system, fail. */ 2578 if (pci_msi_blacklisted()) 2579 return (ENXIO); 2580 2581 /* MSI capability present? */ 2582 if (cfg->msi.msi_location == 0 || !pci_do_msi) 2583 return (ENODEV); 2584 2585 if (bootverbose) 2586 device_printf(child, 2587 "attempting to allocate %d MSI vectors (%d supported)\n", 2588 *count, cfg->msi.msi_msgnum); 2589 2590 /* Don't ask for more than the device supports. */ 2591 actual = min(*count, cfg->msi.msi_msgnum); 2592 2593 /* Don't ask for more than 32 messages. */ 2594 actual = min(actual, 32); 2595 2596 /* MSI requires power of 2 number of messages. */ 2597 if (!powerof2(actual)) 2598 return (EINVAL); 2599 2600 for (;;) { 2601 /* Try to allocate N messages. */ 2602 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 2603 actual, irqs); 2604 if (error == 0) 2605 break; 2606 if (actual == 1) 2607 return (error); 2608 2609 /* Try N / 2. */ 2610 actual >>= 1; 2611 } 2612 2613 /* 2614 * We now have N actual messages mapped onto SYS_RES_IRQ 2615 * resources in the irqs[] array, so add new resources 2616 * starting at rid 1. 2617 */ 2618 for (i = 0; i < actual; i++) 2619 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 2620 irqs[i], irqs[i], 1); 2621 2622 if (bootverbose) { 2623 if (actual == 1) 2624 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 2625 else { 2626 int run; 2627 2628 /* 2629 * Be fancy and try to print contiguous runs 2630 * of IRQ values as ranges. 'run' is true if 2631 * we are in a range. 2632 */ 2633 device_printf(child, "using IRQs %d", irqs[0]); 2634 run = 0; 2635 for (i = 1; i < actual; i++) { 2636 /* Still in a run? */ 2637 if (irqs[i] == irqs[i - 1] + 1) { 2638 run = 1; 2639 continue; 2640 } 2641 2642 /* Finish previous range. */ 2643 if (run) { 2644 printf("-%d", irqs[i - 1]); 2645 run = 0; 2646 } 2647 2648 /* Start new range. */ 2649 printf(",%d", irqs[i]); 2650 } 2651 2652 /* Unfinished range? */ 2653 if (run) 2654 printf("-%d", irqs[actual - 1]); 2655 printf(" for MSI\n"); 2656 } 2657 } 2658 2659 /* Update control register with actual count. */ 2660 ctrl = cfg->msi.msi_ctrl; 2661 ctrl &= ~PCIM_MSICTRL_MME_MASK; 2662 ctrl |= (ffs(actual) - 1) << 4; 2663 cfg->msi.msi_ctrl = ctrl; 2664 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 2665 2666 /* Update counts of alloc'd messages. */ 2667 cfg->msi.msi_alloc = actual; 2668 cfg->msi.msi_handlers = 0; 2669 *count = actual; 2670 return (0); 2671 } 2672 2673 /* Release the MSI messages associated with this device. */ 2674 int 2675 pci_release_msi_method(device_t dev, device_t child) 2676 { 2677 struct pci_devinfo *dinfo = device_get_ivars(child); 2678 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2679 struct resource_list_entry *rle; 2680 int error, i, irqs[32]; 2681 2682 /* Try MSI-X first. */ 2683 error = pci_release_msix(dev, child); 2684 if (error != ENODEV) 2685 return (error); 2686 2687 /* Do we have any messages to release? */ 2688 if (msi->msi_alloc == 0) 2689 return (ENODEV); 2690 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); 2691 2692 /* Make sure none of the resources are allocated. */ 2693 if (msi->msi_handlers > 0) 2694 return (EBUSY); 2695 for (i = 0; i < msi->msi_alloc; i++) { 2696 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2697 KASSERT(rle != NULL, ("missing MSI resource")); 2698 if (rle->res != NULL) 2699 return (EBUSY); 2700 irqs[i] = rle->start; 2701 } 2702 2703 /* Update control register with 0 count. */ 2704 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), 2705 ("%s: MSI still enabled", __func__)); 2706 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; 2707 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2708 msi->msi_ctrl, 2); 2709 2710 /* Release the messages. */ 2711 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); 2712 for (i = 0; i < msi->msi_alloc; i++) 2713 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2714 2715 /* Update alloc count. */ 2716 msi->msi_alloc = 0; 2717 msi->msi_addr = 0; 2718 msi->msi_data = 0; 2719 return (0); 2720 } 2721 2722 /* 2723 * Return the max supported MSI messages this device supports. 2724 * Basically, assuming the MD code can alloc messages, this function 2725 * should return the maximum value that pci_alloc_msi() can return. 2726 * Thus, it is subject to the tunables, etc. 2727 */ 2728 int 2729 pci_msi_count_method(device_t dev, device_t child) 2730 { 2731 struct pci_devinfo *dinfo = device_get_ivars(child); 2732 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2733 2734 if (pci_do_msi && msi->msi_location != 0) 2735 return (msi->msi_msgnum); 2736 return (0); 2737 } 2738 2739 /* free pcicfgregs structure and all depending data structures */ 2740 2741 int 2742 pci_freecfg(struct pci_devinfo *dinfo) 2743 { 2744 struct devlist *devlist_head; 2745 struct pci_map *pm, *next; 2746 int i; 2747 2748 devlist_head = &pci_devq; 2749 2750 if (dinfo->cfg.vpd.vpd_reg) { 2751 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF); 2752 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++) 2753 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF); 2754 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF); 2755 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++) 2756 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF); 2757 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF); 2758 } 2759 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { 2760 free(pm, M_DEVBUF); 2761 } 2762 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 2763 free(dinfo, M_DEVBUF); 2764 2765 /* increment the generation count */ 2766 pci_generation++; 2767 2768 /* we're losing one device */ 2769 pci_numdevs--; 2770 return (0); 2771 } 2772 2773 /* 2774 * PCI power manangement 2775 */ 2776 int 2777 pci_set_powerstate_method(device_t dev, device_t child, int state) 2778 { 2779 struct pci_devinfo *dinfo = device_get_ivars(child); 2780 pcicfgregs *cfg = &dinfo->cfg; 2781 uint16_t status; 2782 int oldstate, highest, delay; 2783 2784 if (cfg->pp.pp_cap == 0) 2785 return (EOPNOTSUPP); 2786 2787 /* 2788 * Optimize a no state change request away. While it would be OK to 2789 * write to the hardware in theory, some devices have shown odd 2790 * behavior when going from D3 -> D3. 2791 */ 2792 oldstate = pci_get_powerstate(child); 2793 if (oldstate == state) 2794 return (0); 2795 2796 /* 2797 * The PCI power management specification states that after a state 2798 * transition between PCI power states, system software must 2799 * guarantee a minimal delay before the function accesses the device. 2800 * Compute the worst case delay that we need to guarantee before we 2801 * access the device. Many devices will be responsive much more 2802 * quickly than this delay, but there are some that don't respond 2803 * instantly to state changes. Transitions to/from D3 state require 2804 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 2805 * is done below with DELAY rather than a sleeper function because 2806 * this function can be called from contexts where we cannot sleep. 2807 */ 2808 highest = (oldstate > state) ? oldstate : state; 2809 if (highest == PCI_POWERSTATE_D3) 2810 delay = 10000; 2811 else if (highest == PCI_POWERSTATE_D2) 2812 delay = 200; 2813 else 2814 delay = 0; 2815 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 2816 & ~PCIM_PSTAT_DMASK; 2817 switch (state) { 2818 case PCI_POWERSTATE_D0: 2819 status |= PCIM_PSTAT_D0; 2820 break; 2821 case PCI_POWERSTATE_D1: 2822 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 2823 return (EOPNOTSUPP); 2824 status |= PCIM_PSTAT_D1; 2825 break; 2826 case PCI_POWERSTATE_D2: 2827 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 2828 return (EOPNOTSUPP); 2829 status |= PCIM_PSTAT_D2; 2830 break; 2831 case PCI_POWERSTATE_D3: 2832 status |= PCIM_PSTAT_D3; 2833 break; 2834 default: 2835 return (EINVAL); 2836 } 2837 2838 if (bootverbose) 2839 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate, 2840 state); 2841 2842 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 2843 if (delay) 2844 DELAY(delay); 2845 return (0); 2846 } 2847 2848 int 2849 pci_get_powerstate_method(device_t dev, device_t child) 2850 { 2851 struct pci_devinfo *dinfo = device_get_ivars(child); 2852 pcicfgregs *cfg = &dinfo->cfg; 2853 uint16_t status; 2854 int result; 2855 2856 if (cfg->pp.pp_cap != 0) { 2857 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 2858 switch (status & PCIM_PSTAT_DMASK) { 2859 case PCIM_PSTAT_D0: 2860 result = PCI_POWERSTATE_D0; 2861 break; 2862 case PCIM_PSTAT_D1: 2863 result = PCI_POWERSTATE_D1; 2864 break; 2865 case PCIM_PSTAT_D2: 2866 result = PCI_POWERSTATE_D2; 2867 break; 2868 case PCIM_PSTAT_D3: 2869 result = PCI_POWERSTATE_D3; 2870 break; 2871 default: 2872 result = PCI_POWERSTATE_UNKNOWN; 2873 break; 2874 } 2875 } else { 2876 /* No support, device is always at D0 */ 2877 result = PCI_POWERSTATE_D0; 2878 } 2879 return (result); 2880 } 2881 2882 /* 2883 * Some convenience functions for PCI device drivers. 2884 */ 2885 2886 static __inline void 2887 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 2888 { 2889 uint16_t command; 2890 2891 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2892 command |= bit; 2893 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2894 } 2895 2896 static __inline void 2897 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 2898 { 2899 uint16_t command; 2900 2901 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2902 command &= ~bit; 2903 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2904 } 2905 2906 int 2907 pci_enable_busmaster_method(device_t dev, device_t child) 2908 { 2909 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2910 return (0); 2911 } 2912 2913 int 2914 pci_disable_busmaster_method(device_t dev, device_t child) 2915 { 2916 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2917 return (0); 2918 } 2919 2920 int 2921 pci_enable_io_method(device_t dev, device_t child, int space) 2922 { 2923 uint16_t bit; 2924 2925 switch(space) { 2926 case SYS_RES_IOPORT: 2927 bit = PCIM_CMD_PORTEN; 2928 break; 2929 case SYS_RES_MEMORY: 2930 bit = PCIM_CMD_MEMEN; 2931 break; 2932 default: 2933 return (EINVAL); 2934 } 2935 pci_set_command_bit(dev, child, bit); 2936 return (0); 2937 } 2938 2939 int 2940 pci_disable_io_method(device_t dev, device_t child, int space) 2941 { 2942 uint16_t bit; 2943 2944 switch(space) { 2945 case SYS_RES_IOPORT: 2946 bit = PCIM_CMD_PORTEN; 2947 break; 2948 case SYS_RES_MEMORY: 2949 bit = PCIM_CMD_MEMEN; 2950 break; 2951 default: 2952 return (EINVAL); 2953 } 2954 pci_clear_command_bit(dev, child, bit); 2955 return (0); 2956 } 2957 2958 /* 2959 * New style pci driver. Parent device is either a pci-host-bridge or a 2960 * pci-pci-bridge. Both kinds are represented by instances of pcib. 2961 */ 2962 2963 void 2964 pci_print_verbose(struct pci_devinfo *dinfo) 2965 { 2966 2967 if (bootverbose) { 2968 pcicfgregs *cfg = &dinfo->cfg; 2969 2970 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 2971 cfg->vendor, cfg->device, cfg->revid); 2972 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n", 2973 cfg->domain, cfg->bus, cfg->slot, cfg->func); 2974 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 2975 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 2976 cfg->mfdev); 2977 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 2978 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 2979 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 2980 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 2981 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 2982 if (cfg->intpin > 0) 2983 printf("\tintpin=%c, irq=%d\n", 2984 cfg->intpin +'a' -1, cfg->intline); 2985 if (cfg->pp.pp_cap) { 2986 uint16_t status; 2987 2988 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 2989 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 2990 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 2991 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 2992 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 2993 status & PCIM_PSTAT_DMASK); 2994 } 2995 if (cfg->msi.msi_location) { 2996 int ctrl; 2997 2998 ctrl = cfg->msi.msi_ctrl; 2999 printf("\tMSI supports %d message%s%s%s\n", 3000 cfg->msi.msi_msgnum, 3001 (cfg->msi.msi_msgnum == 1) ? "" : "s", 3002 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 3003 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 3004 } 3005 if (cfg->msix.msix_location) { 3006 printf("\tMSI-X supports %d message%s ", 3007 cfg->msix.msix_msgnum, 3008 (cfg->msix.msix_msgnum == 1) ? "" : "s"); 3009 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 3010 printf("in map 0x%x\n", 3011 cfg->msix.msix_table_bar); 3012 else 3013 printf("in maps 0x%x and 0x%x\n", 3014 cfg->msix.msix_table_bar, 3015 cfg->msix.msix_pba_bar); 3016 } 3017 } 3018 } 3019 3020 static int 3021 pci_porten(device_t dev) 3022 { 3023 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0; 3024 } 3025 3026 static int 3027 pci_memen(device_t dev) 3028 { 3029 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0; 3030 } 3031 3032 void 3033 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, 3034 int *bar64) 3035 { 3036 struct pci_devinfo *dinfo; 3037 pci_addr_t map, testval; 3038 int ln2range; 3039 uint16_t cmd; 3040 3041 /* 3042 * The device ROM BAR is special. It is always a 32-bit 3043 * memory BAR. Bit 0 is special and should not be set when 3044 * sizing the BAR. 3045 */ 3046 dinfo = device_get_ivars(dev); 3047 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { 3048 map = pci_read_config(dev, reg, 4); 3049 pci_write_config(dev, reg, 0xfffffffe, 4); 3050 testval = pci_read_config(dev, reg, 4); 3051 pci_write_config(dev, reg, map, 4); 3052 *mapp = map; 3053 *testvalp = testval; 3054 if (bar64 != NULL) 3055 *bar64 = 0; 3056 return; 3057 } 3058 3059 map = pci_read_config(dev, reg, 4); 3060 ln2range = pci_maprange(map); 3061 if (ln2range == 64) 3062 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3063 3064 /* 3065 * Disable decoding via the command register before 3066 * determining the BAR's length since we will be placing it in 3067 * a weird state. 3068 */ 3069 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3070 pci_write_config(dev, PCIR_COMMAND, 3071 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 3072 3073 /* 3074 * Determine the BAR's length by writing all 1's. The bottom 3075 * log_2(size) bits of the BAR will stick as 0 when we read 3076 * the value back. 3077 * 3078 * NB: according to the PCI Local Bus Specification, rev. 3.0: 3079 * "Software writes 0FFFFFFFFh to both registers, reads them back, 3080 * and combines the result into a 64-bit value." (section 6.2.5.1) 3081 * 3082 * Writes to both registers must be performed before attempting to 3083 * read back the size value. 3084 */ 3085 testval = 0; 3086 pci_write_config(dev, reg, 0xffffffff, 4); 3087 if (ln2range == 64) { 3088 pci_write_config(dev, reg + 4, 0xffffffff, 4); 3089 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3090 } 3091 testval |= pci_read_config(dev, reg, 4); 3092 3093 /* 3094 * Restore the original value of the BAR. We may have reprogrammed 3095 * the BAR of the low-level console device and when booting verbose, 3096 * we need the console device addressable. 3097 */ 3098 pci_write_config(dev, reg, map, 4); 3099 if (ln2range == 64) 3100 pci_write_config(dev, reg + 4, map >> 32, 4); 3101 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3102 3103 *mapp = map; 3104 *testvalp = testval; 3105 if (bar64 != NULL) 3106 *bar64 = (ln2range == 64); 3107 } 3108 3109 static void 3110 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base) 3111 { 3112 struct pci_devinfo *dinfo; 3113 int ln2range; 3114 3115 /* The device ROM BAR is always a 32-bit memory BAR. */ 3116 dinfo = device_get_ivars(dev); 3117 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3118 ln2range = 32; 3119 else 3120 ln2range = pci_maprange(pm->pm_value); 3121 pci_write_config(dev, pm->pm_reg, base, 4); 3122 if (ln2range == 64) 3123 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); 3124 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); 3125 if (ln2range == 64) 3126 pm->pm_value |= (pci_addr_t)pci_read_config(dev, 3127 pm->pm_reg + 4, 4) << 32; 3128 } 3129 3130 struct pci_map * 3131 pci_find_bar(device_t dev, int reg) 3132 { 3133 struct pci_devinfo *dinfo; 3134 struct pci_map *pm; 3135 3136 dinfo = device_get_ivars(dev); 3137 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3138 if (pm->pm_reg == reg) 3139 return (pm); 3140 } 3141 return (NULL); 3142 } 3143 3144 int 3145 pci_bar_enabled(device_t dev, struct pci_map *pm) 3146 { 3147 struct pci_devinfo *dinfo; 3148 uint16_t cmd; 3149 3150 dinfo = device_get_ivars(dev); 3151 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && 3152 !(pm->pm_value & PCIM_BIOS_ENABLE)) 3153 return (0); 3154 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3155 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) 3156 return ((cmd & PCIM_CMD_MEMEN) != 0); 3157 else 3158 return ((cmd & PCIM_CMD_PORTEN) != 0); 3159 } 3160 3161 struct pci_map * 3162 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size) 3163 { 3164 struct pci_devinfo *dinfo; 3165 struct pci_map *pm, *prev; 3166 3167 dinfo = device_get_ivars(dev); 3168 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO); 3169 pm->pm_reg = reg; 3170 pm->pm_value = value; 3171 pm->pm_size = size; 3172 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { 3173 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", 3174 reg)); 3175 if (STAILQ_NEXT(prev, pm_link) == NULL || 3176 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) 3177 break; 3178 } 3179 if (prev != NULL) 3180 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); 3181 else 3182 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); 3183 return (pm); 3184 } 3185 3186 static void 3187 pci_restore_bars(device_t dev) 3188 { 3189 struct pci_devinfo *dinfo; 3190 struct pci_map *pm; 3191 int ln2range; 3192 3193 dinfo = device_get_ivars(dev); 3194 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3195 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3196 ln2range = 32; 3197 else 3198 ln2range = pci_maprange(pm->pm_value); 3199 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); 3200 if (ln2range == 64) 3201 pci_write_config(dev, pm->pm_reg + 4, 3202 pm->pm_value >> 32, 4); 3203 } 3204 } 3205 3206 /* 3207 * Add a resource based on a pci map register. Return 1 if the map 3208 * register is a 32bit map register or 2 if it is a 64bit register. 3209 */ 3210 static int 3211 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, 3212 int force, int prefetch) 3213 { 3214 struct pci_map *pm; 3215 pci_addr_t base, map, testval; 3216 pci_addr_t start, end, count; 3217 int barlen, basezero, flags, maprange, mapsize, type; 3218 uint16_t cmd; 3219 struct resource *res; 3220 3221 /* 3222 * The BAR may already exist if the device is a CardBus card 3223 * whose CIS is stored in this BAR. 3224 */ 3225 pm = pci_find_bar(dev, reg); 3226 if (pm != NULL) { 3227 maprange = pci_maprange(pm->pm_value); 3228 barlen = maprange == 64 ? 2 : 1; 3229 return (barlen); 3230 } 3231 3232 pci_read_bar(dev, reg, &map, &testval, NULL); 3233 if (PCI_BAR_MEM(map)) { 3234 type = SYS_RES_MEMORY; 3235 if (map & PCIM_BAR_MEM_PREFETCH) 3236 prefetch = 1; 3237 } else 3238 type = SYS_RES_IOPORT; 3239 mapsize = pci_mapsize(testval); 3240 base = pci_mapbase(map); 3241 #ifdef __PCI_BAR_ZERO_VALID 3242 basezero = 0; 3243 #else 3244 basezero = base == 0; 3245 #endif 3246 maprange = pci_maprange(map); 3247 barlen = maprange == 64 ? 2 : 1; 3248 3249 /* 3250 * For I/O registers, if bottom bit is set, and the next bit up 3251 * isn't clear, we know we have a BAR that doesn't conform to the 3252 * spec, so ignore it. Also, sanity check the size of the data 3253 * areas to the type of memory involved. Memory must be at least 3254 * 16 bytes in size, while I/O ranges must be at least 4. 3255 */ 3256 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0) 3257 return (barlen); 3258 if ((type == SYS_RES_MEMORY && mapsize < 4) || 3259 (type == SYS_RES_IOPORT && mapsize < 2)) 3260 return (barlen); 3261 3262 /* Save a record of this BAR. */ 3263 pm = pci_add_bar(dev, reg, map, mapsize); 3264 if (bootverbose) { 3265 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d", 3266 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize); 3267 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3268 printf(", port disabled\n"); 3269 else if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3270 printf(", memory disabled\n"); 3271 else 3272 printf(", enabled\n"); 3273 } 3274 3275 /* 3276 * If base is 0, then we have problems if this architecture does 3277 * not allow that. It is best to ignore such entries for the 3278 * moment. These will be allocated later if the driver specifically 3279 * requests them. However, some removable buses look better when 3280 * all resources are allocated, so allow '0' to be overriden. 3281 * 3282 * Similarly treat maps whose values is the same as the test value 3283 * read back. These maps have had all f's written to them by the 3284 * BIOS in an attempt to disable the resources. 3285 */ 3286 if (!force && (basezero || map == testval)) 3287 return (barlen); 3288 if ((u_long)base != base) { 3289 device_printf(bus, 3290 "pci%d:%d:%d:%d bar %#x too many address bits", 3291 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev), 3292 pci_get_function(dev), reg); 3293 return (barlen); 3294 } 3295 3296 /* 3297 * This code theoretically does the right thing, but has 3298 * undesirable side effects in some cases where peripherals 3299 * respond oddly to having these bits enabled. Let the user 3300 * be able to turn them off (since pci_enable_io_modes is 1 by 3301 * default). 3302 */ 3303 if (pci_enable_io_modes) { 3304 /* Turn on resources that have been left off by a lazy BIOS */ 3305 if (type == SYS_RES_IOPORT && !pci_porten(dev)) { 3306 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3307 cmd |= PCIM_CMD_PORTEN; 3308 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3309 } 3310 if (type == SYS_RES_MEMORY && !pci_memen(dev)) { 3311 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3312 cmd |= PCIM_CMD_MEMEN; 3313 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3314 } 3315 } else { 3316 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3317 return (barlen); 3318 if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3319 return (barlen); 3320 } 3321 3322 count = (pci_addr_t)1 << mapsize; 3323 flags = RF_ALIGNMENT_LOG2(mapsize); 3324 if (prefetch) 3325 flags |= RF_PREFETCHABLE; 3326 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) { 3327 start = 0; /* Let the parent decide. */ 3328 end = ~0; 3329 } else { 3330 start = base; 3331 end = base + count - 1; 3332 } 3333 resource_list_add(rl, type, reg, start, end, count); 3334 3335 /* 3336 * Try to allocate the resource for this BAR from our parent 3337 * so that this resource range is already reserved. The 3338 * driver for this device will later inherit this resource in 3339 * pci_alloc_resource(). 3340 */ 3341 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count, 3342 flags); 3343 if ((pci_do_realloc_bars 3344 || pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_REALLOC_BAR)) 3345 && res == NULL && (start != 0 || end != ~0)) { 3346 /* 3347 * If the allocation fails, try to allocate a resource for 3348 * this BAR using any available range. The firmware felt 3349 * it was important enough to assign a resource, so don't 3350 * disable decoding if we can help it. 3351 */ 3352 resource_list_delete(rl, type, reg); 3353 resource_list_add(rl, type, reg, 0, ~0, count); 3354 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0, 3355 count, flags); 3356 } 3357 if (res == NULL) { 3358 /* 3359 * If the allocation fails, delete the resource list entry 3360 * and disable decoding for this device. 3361 * 3362 * If the driver requests this resource in the future, 3363 * pci_reserve_map() will try to allocate a fresh 3364 * resource range. 3365 */ 3366 resource_list_delete(rl, type, reg); 3367 pci_disable_io(dev, type); 3368 if (bootverbose) 3369 device_printf(bus, 3370 "pci%d:%d:%d:%d bar %#x failed to allocate\n", 3371 pci_get_domain(dev), pci_get_bus(dev), 3372 pci_get_slot(dev), pci_get_function(dev), reg); 3373 } else { 3374 start = rman_get_start(res); 3375 pci_write_bar(dev, pm, start); 3376 } 3377 return (barlen); 3378 } 3379 3380 /* 3381 * For ATA devices we need to decide early what addressing mode to use. 3382 * Legacy demands that the primary and secondary ATA ports sits on the 3383 * same addresses that old ISA hardware did. This dictates that we use 3384 * those addresses and ignore the BAR's if we cannot set PCI native 3385 * addressing mode. 3386 */ 3387 static void 3388 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, 3389 uint32_t prefetchmask) 3390 { 3391 int rid, type, progif; 3392 #if 0 3393 /* if this device supports PCI native addressing use it */ 3394 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3395 if ((progif & 0x8a) == 0x8a) { 3396 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 3397 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 3398 printf("Trying ATA native PCI addressing mode\n"); 3399 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 3400 } 3401 } 3402 #endif 3403 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3404 type = SYS_RES_IOPORT; 3405 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 3406 pci_add_map(bus, dev, PCIR_BAR(0), rl, force, 3407 prefetchmask & (1 << 0)); 3408 pci_add_map(bus, dev, PCIR_BAR(1), rl, force, 3409 prefetchmask & (1 << 1)); 3410 } else { 3411 rid = PCIR_BAR(0); 3412 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 3413 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0, 3414 0x1f7, 8, 0); 3415 rid = PCIR_BAR(1); 3416 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 3417 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6, 3418 0x3f6, 1, 0); 3419 } 3420 if (progif & PCIP_STORAGE_IDE_MODESEC) { 3421 pci_add_map(bus, dev, PCIR_BAR(2), rl, force, 3422 prefetchmask & (1 << 2)); 3423 pci_add_map(bus, dev, PCIR_BAR(3), rl, force, 3424 prefetchmask & (1 << 3)); 3425 } else { 3426 rid = PCIR_BAR(2); 3427 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 3428 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170, 3429 0x177, 8, 0); 3430 rid = PCIR_BAR(3); 3431 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 3432 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376, 3433 0x376, 1, 0); 3434 } 3435 pci_add_map(bus, dev, PCIR_BAR(4), rl, force, 3436 prefetchmask & (1 << 4)); 3437 pci_add_map(bus, dev, PCIR_BAR(5), rl, force, 3438 prefetchmask & (1 << 5)); 3439 } 3440 3441 static void 3442 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 3443 { 3444 struct pci_devinfo *dinfo = device_get_ivars(dev); 3445 pcicfgregs *cfg = &dinfo->cfg; 3446 char tunable_name[64]; 3447 int irq; 3448 3449 /* Has to have an intpin to have an interrupt. */ 3450 if (cfg->intpin == 0) 3451 return; 3452 3453 /* Let the user override the IRQ with a tunable. */ 3454 irq = PCI_INVALID_IRQ; 3455 snprintf(tunable_name, sizeof(tunable_name), 3456 "hw.pci%d.%d.%d.INT%c.irq", 3457 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 3458 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 3459 irq = PCI_INVALID_IRQ; 3460 3461 /* 3462 * If we didn't get an IRQ via the tunable, then we either use the 3463 * IRQ value in the intline register or we ask the bus to route an 3464 * interrupt for us. If force_route is true, then we only use the 3465 * value in the intline register if the bus was unable to assign an 3466 * IRQ. 3467 */ 3468 if (!PCI_INTERRUPT_VALID(irq)) { 3469 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 3470 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 3471 if (!PCI_INTERRUPT_VALID(irq)) 3472 irq = cfg->intline; 3473 } 3474 3475 /* If after all that we don't have an IRQ, just bail. */ 3476 if (!PCI_INTERRUPT_VALID(irq)) 3477 return; 3478 3479 /* Update the config register if it changed. */ 3480 if (irq != cfg->intline) { 3481 cfg->intline = irq; 3482 pci_write_config(dev, PCIR_INTLINE, irq, 1); 3483 } 3484 3485 /* Add this IRQ as rid 0 interrupt resource. */ 3486 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 3487 } 3488 3489 /* Perform early OHCI takeover from SMM. */ 3490 static void 3491 ohci_early_takeover(device_t self) 3492 { 3493 struct resource *res; 3494 uint32_t ctl; 3495 int rid; 3496 int i; 3497 3498 rid = PCIR_BAR(0); 3499 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3500 if (res == NULL) 3501 return; 3502 3503 ctl = bus_read_4(res, OHCI_CONTROL); 3504 if (ctl & OHCI_IR) { 3505 if (bootverbose) 3506 printf("ohci early: " 3507 "SMM active, request owner change\n"); 3508 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR); 3509 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 3510 DELAY(1000); 3511 ctl = bus_read_4(res, OHCI_CONTROL); 3512 } 3513 if (ctl & OHCI_IR) { 3514 if (bootverbose) 3515 printf("ohci early: " 3516 "SMM does not respond, resetting\n"); 3517 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET); 3518 } 3519 /* Disable interrupts */ 3520 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 3521 } 3522 3523 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3524 } 3525 3526 /* Perform early UHCI takeover from SMM. */ 3527 static void 3528 uhci_early_takeover(device_t self) 3529 { 3530 struct resource *res; 3531 int rid; 3532 3533 /* 3534 * Set the PIRQD enable bit and switch off all the others. We don't 3535 * want legacy support to interfere with us XXX Does this also mean 3536 * that the BIOS won't touch the keyboard anymore if it is connected 3537 * to the ports of the root hub? 3538 */ 3539 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2); 3540 3541 /* Disable interrupts */ 3542 rid = PCI_UHCI_BASE_REG; 3543 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE); 3544 if (res != NULL) { 3545 bus_write_2(res, UHCI_INTR, 0); 3546 bus_release_resource(self, SYS_RES_IOPORT, rid, res); 3547 } 3548 } 3549 3550 /* Perform early EHCI takeover from SMM. */ 3551 static void 3552 ehci_early_takeover(device_t self) 3553 { 3554 struct resource *res; 3555 uint32_t cparams; 3556 uint32_t eec; 3557 uint8_t eecp; 3558 uint8_t bios_sem; 3559 uint8_t offs; 3560 int rid; 3561 int i; 3562 3563 rid = PCIR_BAR(0); 3564 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3565 if (res == NULL) 3566 return; 3567 3568 cparams = bus_read_4(res, EHCI_HCCPARAMS); 3569 3570 /* Synchronise with the BIOS if it owns the controller. */ 3571 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0; 3572 eecp = EHCI_EECP_NEXT(eec)) { 3573 eec = pci_read_config(self, eecp, 4); 3574 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) { 3575 continue; 3576 } 3577 bios_sem = pci_read_config(self, eecp + 3578 EHCI_LEGSUP_BIOS_SEM, 1); 3579 if (bios_sem == 0) { 3580 continue; 3581 } 3582 if (bootverbose) 3583 printf("ehci early: " 3584 "SMM active, request owner change\n"); 3585 3586 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1); 3587 3588 for (i = 0; (i < 100) && (bios_sem != 0); i++) { 3589 DELAY(1000); 3590 bios_sem = pci_read_config(self, eecp + 3591 EHCI_LEGSUP_BIOS_SEM, 1); 3592 } 3593 3594 if (bios_sem != 0) { 3595 if (bootverbose) 3596 printf("ehci early: " 3597 "SMM does not respond\n"); 3598 } 3599 /* Disable interrupts */ 3600 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION)); 3601 bus_write_4(res, offs + EHCI_USBINTR, 0); 3602 } 3603 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3604 } 3605 3606 /* Perform early XHCI takeover from SMM. */ 3607 static void 3608 xhci_early_takeover(device_t self) 3609 { 3610 struct resource *res; 3611 uint32_t cparams; 3612 uint32_t eec; 3613 uint8_t eecp; 3614 uint8_t bios_sem; 3615 uint8_t offs; 3616 int rid; 3617 int i; 3618 3619 rid = PCIR_BAR(0); 3620 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3621 if (res == NULL) 3622 return; 3623 3624 cparams = bus_read_4(res, XHCI_HCSPARAMS0); 3625 3626 eec = -1; 3627 3628 /* Synchronise with the BIOS if it owns the controller. */ 3629 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 3630 eecp += XHCI_XECP_NEXT(eec) << 2) { 3631 eec = bus_read_4(res, eecp); 3632 3633 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 3634 continue; 3635 3636 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM); 3637 if (bios_sem == 0) 3638 continue; 3639 3640 if (bootverbose) 3641 printf("xhci early: " 3642 "SMM active, request owner change\n"); 3643 3644 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1); 3645 3646 /* wait a maximum of 5 second */ 3647 3648 for (i = 0; (i < 5000) && (bios_sem != 0); i++) { 3649 DELAY(1000); 3650 bios_sem = bus_read_1(res, eecp + 3651 XHCI_XECP_BIOS_SEM); 3652 } 3653 3654 if (bios_sem != 0) { 3655 if (bootverbose) 3656 printf("xhci early: " 3657 "SMM does not respond\n"); 3658 } 3659 3660 /* Disable interrupts */ 3661 offs = bus_read_1(res, XHCI_CAPLENGTH); 3662 bus_write_4(res, offs + XHCI_USBCMD, 0); 3663 bus_read_4(res, offs + XHCI_USBSTS); 3664 } 3665 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3666 } 3667 3668 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 3669 static void 3670 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg, 3671 struct resource_list *rl) 3672 { 3673 struct resource *res; 3674 char *cp; 3675 rman_res_t start, end, count; 3676 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus; 3677 3678 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3679 case PCIM_HDRTYPE_BRIDGE: 3680 sec_reg = PCIR_SECBUS_1; 3681 sub_reg = PCIR_SUBBUS_1; 3682 break; 3683 case PCIM_HDRTYPE_CARDBUS: 3684 sec_reg = PCIR_SECBUS_2; 3685 sub_reg = PCIR_SUBBUS_2; 3686 break; 3687 default: 3688 return; 3689 } 3690 3691 /* 3692 * If the existing bus range is valid, attempt to reserve it 3693 * from our parent. If this fails for any reason, clear the 3694 * secbus and subbus registers. 3695 * 3696 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus? 3697 * This would at least preserve the existing sec_bus if it is 3698 * valid. 3699 */ 3700 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1); 3701 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1); 3702 3703 /* Quirk handling. */ 3704 switch (pci_get_devid(dev)) { 3705 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 3706 sup_bus = pci_read_config(dev, 0x41, 1); 3707 if (sup_bus != 0xff) { 3708 sec_bus = sup_bus + 1; 3709 sub_bus = sup_bus + 1; 3710 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1); 3711 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3712 } 3713 break; 3714 3715 case 0x00dd10de: 3716 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 3717 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 3718 break; 3719 if (strncmp(cp, "Compal", 6) != 0) { 3720 freeenv(cp); 3721 break; 3722 } 3723 freeenv(cp); 3724 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 3725 break; 3726 if (strncmp(cp, "08A0", 4) != 0) { 3727 freeenv(cp); 3728 break; 3729 } 3730 freeenv(cp); 3731 if (sub_bus < 0xa) { 3732 sub_bus = 0xa; 3733 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3734 } 3735 break; 3736 } 3737 3738 if (bootverbose) 3739 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus); 3740 if (sec_bus > 0 && sub_bus >= sec_bus) { 3741 start = sec_bus; 3742 end = sub_bus; 3743 count = end - start + 1; 3744 3745 resource_list_add(rl, PCI_RES_BUS, 0, 0, ~0, count); 3746 3747 /* 3748 * If requested, clear secondary bus registers in 3749 * bridge devices to force a complete renumbering 3750 * rather than reserving the existing range. However, 3751 * preserve the existing size. 3752 */ 3753 if (pci_clear_buses) 3754 goto clear; 3755 3756 rid = 0; 3757 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid, 3758 start, end, count, 0); 3759 if (res != NULL) 3760 return; 3761 3762 if (bootverbose) 3763 device_printf(bus, 3764 "pci%d:%d:%d:%d secbus failed to allocate\n", 3765 pci_get_domain(dev), pci_get_bus(dev), 3766 pci_get_slot(dev), pci_get_function(dev)); 3767 } 3768 3769 clear: 3770 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1); 3771 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1); 3772 } 3773 3774 static struct resource * 3775 pci_alloc_secbus(device_t dev, device_t child, int *rid, rman_res_t start, 3776 rman_res_t end, rman_res_t count, u_int flags) 3777 { 3778 struct pci_devinfo *dinfo; 3779 pcicfgregs *cfg; 3780 struct resource_list *rl; 3781 struct resource *res; 3782 int sec_reg, sub_reg; 3783 3784 dinfo = device_get_ivars(child); 3785 cfg = &dinfo->cfg; 3786 rl = &dinfo->resources; 3787 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3788 case PCIM_HDRTYPE_BRIDGE: 3789 sec_reg = PCIR_SECBUS_1; 3790 sub_reg = PCIR_SUBBUS_1; 3791 break; 3792 case PCIM_HDRTYPE_CARDBUS: 3793 sec_reg = PCIR_SECBUS_2; 3794 sub_reg = PCIR_SUBBUS_2; 3795 break; 3796 default: 3797 return (NULL); 3798 } 3799 3800 if (*rid != 0) 3801 return (NULL); 3802 3803 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL) 3804 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count); 3805 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) { 3806 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid, 3807 start, end, count, flags & ~RF_ACTIVE); 3808 if (res == NULL) { 3809 resource_list_delete(rl, PCI_RES_BUS, *rid); 3810 device_printf(child, "allocating %ju bus%s failed\n", 3811 count, count == 1 ? "" : "es"); 3812 return (NULL); 3813 } 3814 if (bootverbose) 3815 device_printf(child, 3816 "Lazy allocation of %ju bus%s at %ju\n", count, 3817 count == 1 ? "" : "es", rman_get_start(res)); 3818 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1); 3819 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1); 3820 } 3821 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start, 3822 end, count, flags)); 3823 } 3824 #endif 3825 3826 static int 3827 pci_ea_bei_to_rid(device_t dev, int bei) 3828 { 3829 #ifdef PCI_IOV 3830 struct pci_devinfo *dinfo; 3831 int iov_pos; 3832 struct pcicfg_iov *iov; 3833 3834 dinfo = device_get_ivars(dev); 3835 iov = dinfo->cfg.iov; 3836 if (iov != NULL) 3837 iov_pos = iov->iov_pos; 3838 else 3839 iov_pos = 0; 3840 #endif 3841 3842 /* Check if matches BAR */ 3843 if ((bei >= PCIM_EA_BEI_BAR_0) && 3844 (bei <= PCIM_EA_BEI_BAR_5)) 3845 return (PCIR_BAR(bei)); 3846 3847 /* Check ROM */ 3848 if (bei == PCIM_EA_BEI_ROM) 3849 return (PCIR_BIOS); 3850 3851 #ifdef PCI_IOV 3852 /* Check if matches VF_BAR */ 3853 if ((iov != NULL) && (bei >= PCIM_EA_BEI_VF_BAR_0) && 3854 (bei <= PCIM_EA_BEI_VF_BAR_5)) 3855 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) + 3856 iov_pos); 3857 #endif 3858 3859 return (-1); 3860 } 3861 3862 int 3863 pci_ea_is_enabled(device_t dev, int rid) 3864 { 3865 struct pci_ea_entry *ea; 3866 struct pci_devinfo *dinfo; 3867 3868 dinfo = device_get_ivars(dev); 3869 3870 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3871 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid) 3872 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0); 3873 } 3874 3875 return (0); 3876 } 3877 3878 void 3879 pci_add_resources_ea(device_t bus, device_t dev, int alloc_iov) 3880 { 3881 struct pci_ea_entry *ea; 3882 struct pci_devinfo *dinfo; 3883 pci_addr_t start, end, count; 3884 struct resource_list *rl; 3885 int type, flags, rid; 3886 struct resource *res; 3887 uint32_t tmp; 3888 #ifdef PCI_IOV 3889 struct pcicfg_iov *iov; 3890 #endif 3891 3892 dinfo = device_get_ivars(dev); 3893 rl = &dinfo->resources; 3894 flags = 0; 3895 3896 #ifdef PCI_IOV 3897 iov = dinfo->cfg.iov; 3898 #endif 3899 3900 if (dinfo->cfg.ea.ea_location == 0) 3901 return; 3902 3903 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3904 /* 3905 * TODO: Ignore EA-BAR if is not enabled. 3906 * Currently the EA implementation supports 3907 * only situation, where EA structure contains 3908 * predefined entries. In case they are not enabled 3909 * leave them unallocated and proceed with 3910 * a legacy-BAR mechanism. 3911 */ 3912 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0) 3913 continue; 3914 3915 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) { 3916 case PCIM_EA_P_MEM_PREFETCH: 3917 case PCIM_EA_P_VF_MEM_PREFETCH: 3918 flags = RF_PREFETCHABLE; 3919 /* FALLTHROUGH */ 3920 case PCIM_EA_P_VF_MEM: 3921 case PCIM_EA_P_MEM: 3922 type = SYS_RES_MEMORY; 3923 break; 3924 case PCIM_EA_P_IO: 3925 type = SYS_RES_IOPORT; 3926 break; 3927 default: 3928 continue; 3929 } 3930 3931 if (alloc_iov != 0) { 3932 #ifdef PCI_IOV 3933 /* Allocating IOV, confirm BEI matches */ 3934 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) || 3935 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5)) 3936 continue; 3937 #else 3938 continue; 3939 #endif 3940 } else { 3941 /* Allocating BAR, confirm BEI matches */ 3942 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) || 3943 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) && 3944 (ea->eae_bei != PCIM_EA_BEI_ROM)) 3945 continue; 3946 } 3947 3948 rid = pci_ea_bei_to_rid(dev, ea->eae_bei); 3949 if (rid < 0) 3950 continue; 3951 3952 /* Skip resources already allocated by EA */ 3953 if ((resource_list_find(rl, SYS_RES_MEMORY, rid) != NULL) || 3954 (resource_list_find(rl, SYS_RES_IOPORT, rid) != NULL)) 3955 continue; 3956 3957 start = ea->eae_base; 3958 count = ea->eae_max_offset + 1; 3959 #ifdef PCI_IOV 3960 if (iov != NULL) 3961 count = count * iov->iov_num_vfs; 3962 #endif 3963 end = start + count - 1; 3964 if (count == 0) 3965 continue; 3966 3967 resource_list_add(rl, type, rid, start, end, count); 3968 res = resource_list_reserve(rl, bus, dev, type, &rid, start, end, count, 3969 flags); 3970 if (res == NULL) { 3971 resource_list_delete(rl, type, rid); 3972 3973 /* 3974 * Failed to allocate using EA, disable entry. 3975 * Another attempt to allocation will be performed 3976 * further, but this time using legacy BAR registers 3977 */ 3978 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4); 3979 tmp &= ~PCIM_EA_ENABLE; 3980 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4); 3981 3982 /* 3983 * Disabling entry might fail in case it is hardwired. 3984 * Read flags again to match current status. 3985 */ 3986 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4); 3987 3988 continue; 3989 } 3990 3991 /* As per specification, fill BAR with zeros */ 3992 pci_write_config(dev, rid, 0, 4); 3993 } 3994 } 3995 3996 void 3997 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 3998 { 3999 struct pci_devinfo *dinfo; 4000 pcicfgregs *cfg; 4001 struct resource_list *rl; 4002 const struct pci_quirk *q; 4003 uint32_t devid; 4004 int i; 4005 4006 dinfo = device_get_ivars(dev); 4007 cfg = &dinfo->cfg; 4008 rl = &dinfo->resources; 4009 devid = (cfg->device << 16) | cfg->vendor; 4010 4011 /* Allocate resources using Enhanced Allocation */ 4012 pci_add_resources_ea(bus, dev, 0); 4013 4014 /* ATA devices needs special map treatment */ 4015 if ((pci_get_class(dev) == PCIC_STORAGE) && 4016 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 4017 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 4018 (!pci_read_config(dev, PCIR_BAR(0), 4) && 4019 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 4020 pci_ata_maps(bus, dev, rl, force, prefetchmask); 4021 else 4022 for (i = 0; i < cfg->nummaps;) { 4023 /* Skip resources already managed by EA */ 4024 if ((resource_list_find(rl, SYS_RES_MEMORY, PCIR_BAR(i)) != NULL) || 4025 (resource_list_find(rl, SYS_RES_IOPORT, PCIR_BAR(i)) != NULL) || 4026 pci_ea_is_enabled(dev, PCIR_BAR(i))) { 4027 i++; 4028 continue; 4029 } 4030 4031 /* 4032 * Skip quirked resources. 4033 */ 4034 for (q = &pci_quirks[0]; q->devid != 0; q++) 4035 if (q->devid == devid && 4036 q->type == PCI_QUIRK_UNMAP_REG && 4037 q->arg1 == PCIR_BAR(i)) 4038 break; 4039 if (q->devid != 0) { 4040 i++; 4041 continue; 4042 } 4043 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force, 4044 prefetchmask & (1 << i)); 4045 } 4046 4047 /* 4048 * Add additional, quirked resources. 4049 */ 4050 for (q = &pci_quirks[0]; q->devid != 0; q++) 4051 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) 4052 pci_add_map(bus, dev, q->arg1, rl, force, 0); 4053 4054 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 4055 #ifdef __PCI_REROUTE_INTERRUPT 4056 /* 4057 * Try to re-route interrupts. Sometimes the BIOS or 4058 * firmware may leave bogus values in these registers. 4059 * If the re-route fails, then just stick with what we 4060 * have. 4061 */ 4062 pci_assign_interrupt(bus, dev, 1); 4063 #else 4064 pci_assign_interrupt(bus, dev, 0); 4065 #endif 4066 } 4067 4068 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS && 4069 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) { 4070 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI) 4071 xhci_early_takeover(dev); 4072 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI) 4073 ehci_early_takeover(dev); 4074 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI) 4075 ohci_early_takeover(dev); 4076 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI) 4077 uhci_early_takeover(dev); 4078 } 4079 4080 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 4081 /* 4082 * Reserve resources for secondary bus ranges behind bridge 4083 * devices. 4084 */ 4085 pci_reserve_secbus(bus, dev, cfg, rl); 4086 #endif 4087 } 4088 4089 static struct pci_devinfo * 4090 pci_identify_function(device_t pcib, device_t dev, int domain, int busno, 4091 int slot, int func) 4092 { 4093 struct pci_devinfo *dinfo; 4094 4095 dinfo = pci_read_device(pcib, dev, domain, busno, slot, func); 4096 if (dinfo != NULL) 4097 pci_add_child(dev, dinfo); 4098 4099 return (dinfo); 4100 } 4101 4102 void 4103 pci_add_children(device_t dev, int domain, int busno) 4104 { 4105 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4106 device_t pcib = device_get_parent(dev); 4107 struct pci_devinfo *dinfo; 4108 int maxslots; 4109 int s, f, pcifunchigh; 4110 uint8_t hdrtype; 4111 int first_func; 4112 4113 /* 4114 * Try to detect a device at slot 0, function 0. If it exists, try to 4115 * enable ARI. We must enable ARI before detecting the rest of the 4116 * functions on this bus as ARI changes the set of slots and functions 4117 * that are legal on this bus. 4118 */ 4119 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0); 4120 if (dinfo != NULL && pci_enable_ari) 4121 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); 4122 4123 /* 4124 * Start looking for new devices on slot 0 at function 1 because we 4125 * just identified the device at slot 0, function 0. 4126 */ 4127 first_func = 1; 4128 4129 maxslots = PCIB_MAXSLOTS(pcib); 4130 for (s = 0; s <= maxslots; s++, first_func = 0) { 4131 pcifunchigh = 0; 4132 f = 0; 4133 DELAY(1); 4134 hdrtype = REG(PCIR_HDRTYPE, 1); 4135 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4136 continue; 4137 if (hdrtype & PCIM_MFDEV) 4138 pcifunchigh = PCIB_MAXFUNCS(pcib); 4139 for (f = first_func; f <= pcifunchigh; f++) 4140 pci_identify_function(pcib, dev, domain, busno, s, f); 4141 } 4142 #undef REG 4143 } 4144 4145 int 4146 pci_rescan_method(device_t dev) 4147 { 4148 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4149 device_t pcib = device_get_parent(dev); 4150 device_t child, *devlist, *unchanged; 4151 int devcount, error, i, j, maxslots, oldcount; 4152 int busno, domain, s, f, pcifunchigh; 4153 uint8_t hdrtype; 4154 4155 /* No need to check for ARI on a rescan. */ 4156 error = device_get_children(dev, &devlist, &devcount); 4157 if (error) 4158 return (error); 4159 if (devcount != 0) { 4160 unchanged = malloc(devcount * sizeof(device_t), M_TEMP, 4161 M_NOWAIT | M_ZERO); 4162 if (unchanged == NULL) { 4163 free(devlist, M_TEMP); 4164 return (ENOMEM); 4165 } 4166 } else 4167 unchanged = NULL; 4168 4169 domain = pcib_get_domain(dev); 4170 busno = pcib_get_bus(dev); 4171 maxslots = PCIB_MAXSLOTS(pcib); 4172 for (s = 0; s <= maxslots; s++) { 4173 /* If function 0 is not present, skip to the next slot. */ 4174 f = 0; 4175 if (REG(PCIR_VENDOR, 2) == 0xffff) 4176 continue; 4177 pcifunchigh = 0; 4178 hdrtype = REG(PCIR_HDRTYPE, 1); 4179 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4180 continue; 4181 if (hdrtype & PCIM_MFDEV) 4182 pcifunchigh = PCIB_MAXFUNCS(pcib); 4183 for (f = 0; f <= pcifunchigh; f++) { 4184 if (REG(PCIR_VENDOR, 2) == 0xffff) 4185 continue; 4186 4187 /* 4188 * Found a valid function. Check if a 4189 * device_t for this device already exists. 4190 */ 4191 for (i = 0; i < devcount; i++) { 4192 child = devlist[i]; 4193 if (child == NULL) 4194 continue; 4195 if (pci_get_slot(child) == s && 4196 pci_get_function(child) == f) { 4197 unchanged[i] = child; 4198 goto next_func; 4199 } 4200 } 4201 4202 pci_identify_function(pcib, dev, domain, busno, s, f); 4203 next_func:; 4204 } 4205 } 4206 4207 /* Remove devices that are no longer present. */ 4208 for (i = 0; i < devcount; i++) { 4209 if (unchanged[i] != NULL) 4210 continue; 4211 device_delete_child(dev, devlist[i]); 4212 } 4213 4214 free(devlist, M_TEMP); 4215 oldcount = devcount; 4216 4217 /* Try to attach the devices just added. */ 4218 error = device_get_children(dev, &devlist, &devcount); 4219 if (error) { 4220 free(unchanged, M_TEMP); 4221 return (error); 4222 } 4223 4224 for (i = 0; i < devcount; i++) { 4225 for (j = 0; j < oldcount; j++) { 4226 if (devlist[i] == unchanged[j]) 4227 goto next_device; 4228 } 4229 4230 device_probe_and_attach(devlist[i]); 4231 next_device:; 4232 } 4233 4234 free(unchanged, M_TEMP); 4235 free(devlist, M_TEMP); 4236 return (0); 4237 #undef REG 4238 } 4239 4240 #ifdef PCI_IOV 4241 device_t 4242 pci_add_iov_child(device_t bus, device_t pf, uint16_t rid, uint16_t vid, 4243 uint16_t did) 4244 { 4245 struct pci_devinfo *vf_dinfo; 4246 device_t pcib; 4247 int busno, slot, func; 4248 4249 pcib = device_get_parent(bus); 4250 4251 PCIB_DECODE_RID(pcib, rid, &busno, &slot, &func); 4252 4253 vf_dinfo = pci_fill_devinfo(pcib, bus, pci_get_domain(pcib), busno, 4254 slot, func, vid, did); 4255 4256 vf_dinfo->cfg.flags |= PCICFG_VF; 4257 pci_add_child(bus, vf_dinfo); 4258 4259 return (vf_dinfo->cfg.dev); 4260 } 4261 4262 device_t 4263 pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid, 4264 uint16_t vid, uint16_t did) 4265 { 4266 4267 return (pci_add_iov_child(bus, pf, rid, vid, did)); 4268 } 4269 #endif 4270 4271 /* 4272 * For PCIe device set Max_Payload_Size to match PCIe root's. 4273 */ 4274 static void 4275 pcie_setup_mps(device_t dev) 4276 { 4277 struct pci_devinfo *dinfo = device_get_ivars(dev); 4278 device_t root; 4279 uint16_t rmps, mmps, mps; 4280 4281 if (dinfo->cfg.pcie.pcie_location == 0) 4282 return; 4283 root = pci_find_pcie_root_port(dev); 4284 if (root == NULL) 4285 return; 4286 /* Check whether the MPS is already configured. */ 4287 rmps = pcie_read_config(root, PCIER_DEVICE_CTL, 2) & 4288 PCIEM_CTL_MAX_PAYLOAD; 4289 mps = pcie_read_config(dev, PCIER_DEVICE_CTL, 2) & 4290 PCIEM_CTL_MAX_PAYLOAD; 4291 if (mps == rmps) 4292 return; 4293 /* Check whether the device is capable of the root's MPS. */ 4294 mmps = (pcie_read_config(dev, PCIER_DEVICE_CAP, 2) & 4295 PCIEM_CAP_MAX_PAYLOAD) << 5; 4296 if (rmps > mmps) { 4297 /* 4298 * The device is unable to handle root's MPS. Limit root. 4299 * XXX: We should traverse through all the tree, applying 4300 * it to all the devices. 4301 */ 4302 pcie_adjust_config(root, PCIER_DEVICE_CTL, 4303 PCIEM_CTL_MAX_PAYLOAD, mmps, 2); 4304 } else { 4305 pcie_adjust_config(dev, PCIER_DEVICE_CTL, 4306 PCIEM_CTL_MAX_PAYLOAD, rmps, 2); 4307 } 4308 } 4309 4310 static void 4311 pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo) 4312 { 4313 int aer; 4314 uint32_t r; 4315 uint16_t r2; 4316 4317 if (dinfo->cfg.pcie.pcie_location != 0 && 4318 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) { 4319 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4320 PCIER_ROOT_CTL, 2); 4321 r2 &= ~(PCIEM_ROOT_CTL_SERR_CORR | 4322 PCIEM_ROOT_CTL_SERR_NONFATAL | PCIEM_ROOT_CTL_SERR_FATAL); 4323 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4324 PCIER_ROOT_CTL, r2, 2); 4325 } 4326 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 4327 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 4328 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 4329 if (r != 0 && bootverbose) { 4330 pci_printf(&dinfo->cfg, 4331 "clearing AER UC 0x%08x -> 0x%08x\n", 4332 r, pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4333 4)); 4334 } 4335 4336 r = pci_read_config(dev, aer + PCIR_AER_UC_MASK, 4); 4337 r &= ~(PCIM_AER_UC_TRAINING_ERROR | 4338 PCIM_AER_UC_DL_PROTOCOL_ERROR | 4339 PCIM_AER_UC_SURPRISE_LINK_DOWN | 4340 PCIM_AER_UC_POISONED_TLP | 4341 PCIM_AER_UC_FC_PROTOCOL_ERROR | 4342 PCIM_AER_UC_COMPLETION_TIMEOUT | 4343 PCIM_AER_UC_COMPLETER_ABORT | 4344 PCIM_AER_UC_UNEXPECTED_COMPLETION | 4345 PCIM_AER_UC_RECEIVER_OVERFLOW | 4346 PCIM_AER_UC_MALFORMED_TLP | 4347 PCIM_AER_UC_ECRC_ERROR | 4348 PCIM_AER_UC_UNSUPPORTED_REQUEST | 4349 PCIM_AER_UC_ACS_VIOLATION | 4350 PCIM_AER_UC_INTERNAL_ERROR | 4351 PCIM_AER_UC_MC_BLOCKED_TLP | 4352 PCIM_AER_UC_ATOMIC_EGRESS_BLK | 4353 PCIM_AER_UC_TLP_PREFIX_BLOCKED); 4354 pci_write_config(dev, aer + PCIR_AER_UC_MASK, r, 4); 4355 4356 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 4357 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 4358 if (r != 0 && bootverbose) { 4359 pci_printf(&dinfo->cfg, 4360 "clearing AER COR 0x%08x -> 0x%08x\n", 4361 r, pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4362 4)); 4363 } 4364 4365 r = pci_read_config(dev, aer + PCIR_AER_COR_MASK, 4); 4366 r &= ~(PCIM_AER_COR_RECEIVER_ERROR | 4367 PCIM_AER_COR_BAD_TLP | 4368 PCIM_AER_COR_BAD_DLLP | 4369 PCIM_AER_COR_REPLAY_ROLLOVER | 4370 PCIM_AER_COR_REPLAY_TIMEOUT | 4371 PCIM_AER_COR_ADVISORY_NF_ERROR | 4372 PCIM_AER_COR_INTERNAL_ERROR | 4373 PCIM_AER_COR_HEADER_LOG_OVFLOW); 4374 pci_write_config(dev, aer + PCIR_AER_COR_MASK, r, 4); 4375 4376 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4377 PCIER_DEVICE_CTL, 2); 4378 r |= PCIEM_CTL_COR_ENABLE | PCIEM_CTL_NFER_ENABLE | 4379 PCIEM_CTL_FER_ENABLE | PCIEM_CTL_URR_ENABLE; 4380 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4381 PCIER_DEVICE_CTL, r, 2); 4382 } 4383 } 4384 4385 void 4386 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 4387 { 4388 device_t dev; 4389 4390 dinfo->cfg.dev = dev = device_add_child(bus, NULL, -1); 4391 device_set_ivars(dev, dinfo); 4392 resource_list_init(&dinfo->resources); 4393 pci_cfg_save(dev, dinfo, 0); 4394 pci_cfg_restore(dev, dinfo); 4395 pci_print_verbose(dinfo); 4396 pci_add_resources(bus, dev, 0, 0); 4397 pcie_setup_mps(dev); 4398 pci_child_added(dinfo->cfg.dev); 4399 4400 if (pci_clear_aer_on_attach) 4401 pci_add_child_clear_aer(dev, dinfo); 4402 4403 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev); 4404 } 4405 4406 void 4407 pci_child_added_method(device_t dev, device_t child) 4408 { 4409 4410 } 4411 4412 static int 4413 pci_probe(device_t dev) 4414 { 4415 4416 device_set_desc(dev, "PCI bus"); 4417 4418 /* Allow other subclasses to override this driver. */ 4419 return (BUS_PROBE_GENERIC); 4420 } 4421 4422 int 4423 pci_attach_common(device_t dev) 4424 { 4425 struct pci_softc *sc; 4426 int busno, domain; 4427 #ifdef PCI_RES_BUS 4428 int rid; 4429 #endif 4430 4431 sc = device_get_softc(dev); 4432 domain = pcib_get_domain(dev); 4433 busno = pcib_get_bus(dev); 4434 #ifdef PCI_RES_BUS 4435 rid = 0; 4436 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, 4437 1, 0); 4438 if (sc->sc_bus == NULL) { 4439 device_printf(dev, "failed to allocate bus number\n"); 4440 return (ENXIO); 4441 } 4442 #endif 4443 if (bootverbose) 4444 device_printf(dev, "domain=%d, physical bus=%d\n", 4445 domain, busno); 4446 sc->sc_dma_tag = bus_get_dma_tag(dev); 4447 return (0); 4448 } 4449 4450 int 4451 pci_attach(device_t dev) 4452 { 4453 int busno, domain, error; 4454 4455 error = pci_attach_common(dev); 4456 if (error) 4457 return (error); 4458 4459 /* 4460 * Since there can be multiple independently numbered PCI 4461 * buses on systems with multiple PCI domains, we can't use 4462 * the unit number to decide which bus we are probing. We ask 4463 * the parent pcib what our domain and bus numbers are. 4464 */ 4465 domain = pcib_get_domain(dev); 4466 busno = pcib_get_bus(dev); 4467 pci_add_children(dev, domain, busno); 4468 return (bus_generic_attach(dev)); 4469 } 4470 4471 int 4472 pci_detach(device_t dev) 4473 { 4474 #ifdef PCI_RES_BUS 4475 struct pci_softc *sc; 4476 #endif 4477 int error; 4478 4479 error = bus_generic_detach(dev); 4480 if (error) 4481 return (error); 4482 #ifdef PCI_RES_BUS 4483 sc = device_get_softc(dev); 4484 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus); 4485 if (error) 4486 return (error); 4487 #endif 4488 return (device_delete_children(dev)); 4489 } 4490 4491 static void 4492 pci_hint_device_unit(device_t dev, device_t child, const char *name, int *unitp) 4493 { 4494 int line, unit; 4495 const char *at; 4496 char me1[24], me2[32]; 4497 uint8_t b, s, f; 4498 uint32_t d; 4499 4500 d = pci_get_domain(child); 4501 b = pci_get_bus(child); 4502 s = pci_get_slot(child); 4503 f = pci_get_function(child); 4504 snprintf(me1, sizeof(me1), "pci%u:%u:%u", b, s, f); 4505 snprintf(me2, sizeof(me2), "pci%u:%u:%u:%u", d, b, s, f); 4506 line = 0; 4507 while (resource_find_dev(&line, name, &unit, "at", NULL) == 0) { 4508 resource_string_value(name, unit, "at", &at); 4509 if (strcmp(at, me1) != 0 && strcmp(at, me2) != 0) 4510 continue; /* No match, try next candidate */ 4511 *unitp = unit; 4512 return; 4513 } 4514 } 4515 4516 static void 4517 pci_set_power_child(device_t dev, device_t child, int state) 4518 { 4519 device_t pcib; 4520 int dstate; 4521 4522 /* 4523 * Set the device to the given state. If the firmware suggests 4524 * a different power state, use it instead. If power management 4525 * is not present, the firmware is responsible for managing 4526 * device power. Skip children who aren't attached since they 4527 * are handled separately. 4528 */ 4529 pcib = device_get_parent(dev); 4530 dstate = state; 4531 if (device_is_attached(child) && 4532 PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0) 4533 pci_set_powerstate(child, dstate); 4534 } 4535 4536 int 4537 pci_suspend_child(device_t dev, device_t child) 4538 { 4539 struct pci_devinfo *dinfo; 4540 struct resource_list_entry *rle; 4541 int error; 4542 4543 dinfo = device_get_ivars(child); 4544 4545 /* 4546 * Save the PCI configuration space for the child and set the 4547 * device in the appropriate power state for this sleep state. 4548 */ 4549 pci_cfg_save(child, dinfo, 0); 4550 4551 /* Suspend devices before potentially powering them down. */ 4552 error = bus_generic_suspend_child(dev, child); 4553 4554 if (error) 4555 return (error); 4556 4557 if (pci_do_power_suspend) { 4558 /* 4559 * Make sure this device's interrupt handler is not invoked 4560 * in the case the device uses a shared interrupt that can 4561 * be raised by some other device. 4562 * This is applicable only to regular (legacy) PCI interrupts 4563 * as MSI/MSI-X interrupts are never shared. 4564 */ 4565 rle = resource_list_find(&dinfo->resources, 4566 SYS_RES_IRQ, 0); 4567 if (rle != NULL && rle->res != NULL) 4568 (void)bus_suspend_intr(child, rle->res); 4569 pci_set_power_child(dev, child, PCI_POWERSTATE_D3); 4570 } 4571 4572 return (0); 4573 } 4574 4575 int 4576 pci_resume_child(device_t dev, device_t child) 4577 { 4578 struct pci_devinfo *dinfo; 4579 struct resource_list_entry *rle; 4580 4581 if (pci_do_power_resume) 4582 pci_set_power_child(dev, child, PCI_POWERSTATE_D0); 4583 4584 dinfo = device_get_ivars(child); 4585 pci_cfg_restore(child, dinfo); 4586 if (!device_is_attached(child)) 4587 pci_cfg_save(child, dinfo, 1); 4588 4589 bus_generic_resume_child(dev, child); 4590 4591 /* 4592 * Allow interrupts only after fully resuming the driver and hardware. 4593 */ 4594 if (pci_do_power_suspend) { 4595 /* See pci_suspend_child for details. */ 4596 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 4597 if (rle != NULL && rle->res != NULL) 4598 (void)bus_resume_intr(child, rle->res); 4599 } 4600 4601 return (0); 4602 } 4603 4604 int 4605 pci_resume(device_t dev) 4606 { 4607 device_t child, *devlist; 4608 int error, i, numdevs; 4609 4610 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 4611 return (error); 4612 4613 /* 4614 * Resume critical devices first, then everything else later. 4615 */ 4616 for (i = 0; i < numdevs; i++) { 4617 child = devlist[i]; 4618 switch (pci_get_class(child)) { 4619 case PCIC_DISPLAY: 4620 case PCIC_MEMORY: 4621 case PCIC_BRIDGE: 4622 case PCIC_BASEPERIPH: 4623 BUS_RESUME_CHILD(dev, child); 4624 break; 4625 } 4626 } 4627 for (i = 0; i < numdevs; i++) { 4628 child = devlist[i]; 4629 switch (pci_get_class(child)) { 4630 case PCIC_DISPLAY: 4631 case PCIC_MEMORY: 4632 case PCIC_BRIDGE: 4633 case PCIC_BASEPERIPH: 4634 break; 4635 default: 4636 BUS_RESUME_CHILD(dev, child); 4637 } 4638 } 4639 free(devlist, M_TEMP); 4640 return (0); 4641 } 4642 4643 static void 4644 pci_load_vendor_data(void) 4645 { 4646 caddr_t data; 4647 void *ptr; 4648 size_t sz; 4649 4650 data = preload_search_by_type("pci_vendor_data"); 4651 if (data != NULL) { 4652 ptr = preload_fetch_addr(data); 4653 sz = preload_fetch_size(data); 4654 if (ptr != NULL && sz != 0) { 4655 pci_vendordata = ptr; 4656 pci_vendordata_size = sz; 4657 /* terminate the database */ 4658 pci_vendordata[pci_vendordata_size] = '\n'; 4659 } 4660 } 4661 } 4662 4663 void 4664 pci_driver_added(device_t dev, driver_t *driver) 4665 { 4666 int numdevs; 4667 device_t *devlist; 4668 device_t child; 4669 struct pci_devinfo *dinfo; 4670 int i; 4671 4672 if (bootverbose) 4673 device_printf(dev, "driver added\n"); 4674 DEVICE_IDENTIFY(driver, dev); 4675 if (device_get_children(dev, &devlist, &numdevs) != 0) 4676 return; 4677 for (i = 0; i < numdevs; i++) { 4678 child = devlist[i]; 4679 if (device_get_state(child) != DS_NOTPRESENT) 4680 continue; 4681 dinfo = device_get_ivars(child); 4682 pci_print_verbose(dinfo); 4683 if (bootverbose) 4684 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); 4685 pci_cfg_restore(child, dinfo); 4686 if (device_probe_and_attach(child) != 0) 4687 pci_child_detached(dev, child); 4688 } 4689 free(devlist, M_TEMP); 4690 } 4691 4692 int 4693 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, 4694 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep) 4695 { 4696 struct pci_devinfo *dinfo; 4697 struct msix_table_entry *mte; 4698 struct msix_vector *mv; 4699 uint64_t addr; 4700 uint32_t data; 4701 void *cookie; 4702 int error, rid; 4703 4704 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr, 4705 arg, &cookie); 4706 if (error) 4707 return (error); 4708 4709 /* If this is not a direct child, just bail out. */ 4710 if (device_get_parent(child) != dev) { 4711 *cookiep = cookie; 4712 return(0); 4713 } 4714 4715 rid = rman_get_rid(irq); 4716 if (rid == 0) { 4717 /* Make sure that INTx is enabled */ 4718 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4719 } else { 4720 /* 4721 * Check to see if the interrupt is MSI or MSI-X. 4722 * Ask our parent to map the MSI and give 4723 * us the address and data register values. 4724 * If we fail for some reason, teardown the 4725 * interrupt handler. 4726 */ 4727 dinfo = device_get_ivars(child); 4728 if (dinfo->cfg.msi.msi_alloc > 0) { 4729 if (dinfo->cfg.msi.msi_addr == 0) { 4730 KASSERT(dinfo->cfg.msi.msi_handlers == 0, 4731 ("MSI has handlers, but vectors not mapped")); 4732 error = PCIB_MAP_MSI(device_get_parent(dev), 4733 child, rman_get_start(irq), &addr, &data); 4734 if (error) 4735 goto bad; 4736 dinfo->cfg.msi.msi_addr = addr; 4737 dinfo->cfg.msi.msi_data = data; 4738 } 4739 if (dinfo->cfg.msi.msi_handlers == 0) 4740 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, 4741 dinfo->cfg.msi.msi_data); 4742 dinfo->cfg.msi.msi_handlers++; 4743 } else { 4744 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4745 ("No MSI or MSI-X interrupts allocated")); 4746 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4747 ("MSI-X index too high")); 4748 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4749 KASSERT(mte->mte_vector != 0, ("no message vector")); 4750 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; 4751 KASSERT(mv->mv_irq == rman_get_start(irq), 4752 ("IRQ mismatch")); 4753 if (mv->mv_address == 0) { 4754 KASSERT(mte->mte_handlers == 0, 4755 ("MSI-X table entry has handlers, but vector not mapped")); 4756 error = PCIB_MAP_MSI(device_get_parent(dev), 4757 child, rman_get_start(irq), &addr, &data); 4758 if (error) 4759 goto bad; 4760 mv->mv_address = addr; 4761 mv->mv_data = data; 4762 } 4763 4764 /* 4765 * The MSIX table entry must be made valid by 4766 * incrementing the mte_handlers before 4767 * calling pci_enable_msix() and 4768 * pci_resume_msix(). Else the MSIX rewrite 4769 * table quirk will not work as expected. 4770 */ 4771 mte->mte_handlers++; 4772 if (mte->mte_handlers == 1) { 4773 pci_enable_msix(child, rid - 1, mv->mv_address, 4774 mv->mv_data); 4775 pci_unmask_msix(child, rid - 1); 4776 } 4777 } 4778 4779 /* 4780 * Make sure that INTx is disabled if we are using MSI/MSI-X, 4781 * unless the device is affected by PCI_QUIRK_MSI_INTX_BUG, 4782 * in which case we "enable" INTx so MSI/MSI-X actually works. 4783 */ 4784 if (!pci_has_quirk(pci_get_devid(child), 4785 PCI_QUIRK_MSI_INTX_BUG)) 4786 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4787 else 4788 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4789 bad: 4790 if (error) { 4791 (void)bus_generic_teardown_intr(dev, child, irq, 4792 cookie); 4793 return (error); 4794 } 4795 } 4796 *cookiep = cookie; 4797 return (0); 4798 } 4799 4800 int 4801 pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 4802 void *cookie) 4803 { 4804 struct msix_table_entry *mte; 4805 struct resource_list_entry *rle; 4806 struct pci_devinfo *dinfo; 4807 int error, rid; 4808 4809 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE)) 4810 return (EINVAL); 4811 4812 /* If this isn't a direct child, just bail out */ 4813 if (device_get_parent(child) != dev) 4814 return(bus_generic_teardown_intr(dev, child, irq, cookie)); 4815 4816 rid = rman_get_rid(irq); 4817 if (rid == 0) { 4818 /* Mask INTx */ 4819 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4820 } else { 4821 /* 4822 * Check to see if the interrupt is MSI or MSI-X. If so, 4823 * decrement the appropriate handlers count and mask the 4824 * MSI-X message, or disable MSI messages if the count 4825 * drops to 0. 4826 */ 4827 dinfo = device_get_ivars(child); 4828 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); 4829 if (rle->res != irq) 4830 return (EINVAL); 4831 if (dinfo->cfg.msi.msi_alloc > 0) { 4832 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, 4833 ("MSI-X index too high")); 4834 if (dinfo->cfg.msi.msi_handlers == 0) 4835 return (EINVAL); 4836 dinfo->cfg.msi.msi_handlers--; 4837 if (dinfo->cfg.msi.msi_handlers == 0) 4838 pci_disable_msi(child); 4839 } else { 4840 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4841 ("No MSI or MSI-X interrupts allocated")); 4842 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4843 ("MSI-X index too high")); 4844 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4845 if (mte->mte_handlers == 0) 4846 return (EINVAL); 4847 mte->mte_handlers--; 4848 if (mte->mte_handlers == 0) 4849 pci_mask_msix(child, rid - 1); 4850 } 4851 } 4852 error = bus_generic_teardown_intr(dev, child, irq, cookie); 4853 if (rid > 0) 4854 KASSERT(error == 0, 4855 ("%s: generic teardown failed for MSI/MSI-X", __func__)); 4856 return (error); 4857 } 4858 4859 int 4860 pci_print_child(device_t dev, device_t child) 4861 { 4862 struct pci_devinfo *dinfo; 4863 struct resource_list *rl; 4864 int retval = 0; 4865 4866 dinfo = device_get_ivars(child); 4867 rl = &dinfo->resources; 4868 4869 retval += bus_print_child_header(dev, child); 4870 4871 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#jx"); 4872 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 4873 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 4874 if (device_get_flags(dev)) 4875 retval += printf(" flags %#x", device_get_flags(dev)); 4876 4877 retval += printf(" at device %d.%d", pci_get_slot(child), 4878 pci_get_function(child)); 4879 4880 retval += bus_print_child_domain(dev, child); 4881 retval += bus_print_child_footer(dev, child); 4882 4883 return (retval); 4884 } 4885 4886 static const struct 4887 { 4888 int class; 4889 int subclass; 4890 int report; /* 0 = bootverbose, 1 = always */ 4891 const char *desc; 4892 } pci_nomatch_tab[] = { 4893 {PCIC_OLD, -1, 1, "old"}, 4894 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"}, 4895 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"}, 4896 {PCIC_STORAGE, -1, 1, "mass storage"}, 4897 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"}, 4898 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"}, 4899 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"}, 4900 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"}, 4901 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"}, 4902 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"}, 4903 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"}, 4904 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"}, 4905 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"}, 4906 {PCIC_NETWORK, -1, 1, "network"}, 4907 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"}, 4908 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"}, 4909 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"}, 4910 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"}, 4911 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"}, 4912 {PCIC_DISPLAY, -1, 1, "display"}, 4913 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"}, 4914 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"}, 4915 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"}, 4916 {PCIC_MULTIMEDIA, -1, 1, "multimedia"}, 4917 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"}, 4918 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"}, 4919 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"}, 4920 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"}, 4921 {PCIC_MEMORY, -1, 1, "memory"}, 4922 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"}, 4923 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"}, 4924 {PCIC_BRIDGE, -1, 1, "bridge"}, 4925 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"}, 4926 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"}, 4927 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"}, 4928 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"}, 4929 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"}, 4930 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"}, 4931 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"}, 4932 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"}, 4933 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"}, 4934 {PCIC_SIMPLECOMM, -1, 1, "simple comms"}, 4935 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */ 4936 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"}, 4937 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"}, 4938 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"}, 4939 {PCIC_BASEPERIPH, -1, 0, "base peripheral"}, 4940 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"}, 4941 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"}, 4942 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"}, 4943 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"}, 4944 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"}, 4945 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"}, 4946 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"}, 4947 {PCIC_INPUTDEV, -1, 1, "input device"}, 4948 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"}, 4949 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"}, 4950 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"}, 4951 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"}, 4952 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"}, 4953 {PCIC_DOCKING, -1, 1, "docking station"}, 4954 {PCIC_PROCESSOR, -1, 1, "processor"}, 4955 {PCIC_SERIALBUS, -1, 1, "serial bus"}, 4956 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"}, 4957 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"}, 4958 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"}, 4959 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"}, 4960 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"}, 4961 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"}, 4962 {PCIC_WIRELESS, -1, 1, "wireless controller"}, 4963 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"}, 4964 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"}, 4965 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"}, 4966 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"}, 4967 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"}, 4968 {PCIC_SATCOM, -1, 1, "satellite communication"}, 4969 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"}, 4970 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"}, 4971 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"}, 4972 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"}, 4973 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"}, 4974 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"}, 4975 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"}, 4976 {PCIC_DASP, -1, 0, "dasp"}, 4977 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"}, 4978 {PCIC_DASP, PCIS_DASP_PERFCNTRS, 1, "performance counters"}, 4979 {PCIC_DASP, PCIS_DASP_COMM_SYNC, 1, "communication synchronizer"}, 4980 {PCIC_DASP, PCIS_DASP_MGMT_CARD, 1, "signal processing management"}, 4981 {0, 0, 0, NULL} 4982 }; 4983 4984 void 4985 pci_probe_nomatch(device_t dev, device_t child) 4986 { 4987 int i, report; 4988 const char *cp, *scp; 4989 char *device; 4990 4991 /* 4992 * Look for a listing for this device in a loaded device database. 4993 */ 4994 report = 1; 4995 if ((device = pci_describe_device(child)) != NULL) { 4996 device_printf(dev, "<%s>", device); 4997 free(device, M_DEVBUF); 4998 } else { 4999 /* 5000 * Scan the class/subclass descriptions for a general 5001 * description. 5002 */ 5003 cp = "unknown"; 5004 scp = NULL; 5005 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 5006 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 5007 if (pci_nomatch_tab[i].subclass == -1) { 5008 cp = pci_nomatch_tab[i].desc; 5009 report = pci_nomatch_tab[i].report; 5010 } else if (pci_nomatch_tab[i].subclass == 5011 pci_get_subclass(child)) { 5012 scp = pci_nomatch_tab[i].desc; 5013 report = pci_nomatch_tab[i].report; 5014 } 5015 } 5016 } 5017 if (report || bootverbose) { 5018 device_printf(dev, "<%s%s%s>", 5019 cp ? cp : "", 5020 ((cp != NULL) && (scp != NULL)) ? ", " : "", 5021 scp ? scp : ""); 5022 } 5023 } 5024 if (report || bootverbose) { 5025 printf(" at device %d.%d (no driver attached)\n", 5026 pci_get_slot(child), pci_get_function(child)); 5027 } 5028 pci_cfg_save(child, device_get_ivars(child), 1); 5029 } 5030 5031 void 5032 pci_child_detached(device_t dev, device_t child) 5033 { 5034 struct pci_devinfo *dinfo; 5035 struct resource_list *rl; 5036 5037 dinfo = device_get_ivars(child); 5038 rl = &dinfo->resources; 5039 5040 /* 5041 * Have to deallocate IRQs before releasing any MSI messages and 5042 * have to release MSI messages before deallocating any memory 5043 * BARs. 5044 */ 5045 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0) 5046 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); 5047 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { 5048 if (dinfo->cfg.msi.msi_alloc != 0) 5049 pci_printf(&dinfo->cfg, "Device leaked %d MSI " 5050 "vectors\n", dinfo->cfg.msi.msi_alloc); 5051 else 5052 pci_printf(&dinfo->cfg, "Device leaked %d MSI-X " 5053 "vectors\n", dinfo->cfg.msix.msix_alloc); 5054 (void)pci_release_msi(child); 5055 } 5056 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0) 5057 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); 5058 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0) 5059 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); 5060 #ifdef PCI_RES_BUS 5061 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0) 5062 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); 5063 #endif 5064 5065 pci_cfg_save(child, dinfo, 1); 5066 } 5067 5068 /* 5069 * Parse the PCI device database, if loaded, and return a pointer to a 5070 * description of the device. 5071 * 5072 * The database is flat text formatted as follows: 5073 * 5074 * Any line not in a valid format is ignored. 5075 * Lines are terminated with newline '\n' characters. 5076 * 5077 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 5078 * the vendor name. 5079 * 5080 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 5081 * - devices cannot be listed without a corresponding VENDOR line. 5082 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 5083 * another TAB, then the device name. 5084 */ 5085 5086 /* 5087 * Assuming (ptr) points to the beginning of a line in the database, 5088 * return the vendor or device and description of the next entry. 5089 * The value of (vendor) or (device) inappropriate for the entry type 5090 * is set to -1. Returns nonzero at the end of the database. 5091 * 5092 * Note that this is slightly unrobust in the face of corrupt data; 5093 * we attempt to safeguard against this by spamming the end of the 5094 * database with a newline when we initialise. 5095 */ 5096 static int 5097 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 5098 { 5099 char *cp = *ptr; 5100 int left; 5101 5102 *device = -1; 5103 *vendor = -1; 5104 **desc = '\0'; 5105 for (;;) { 5106 left = pci_vendordata_size - (cp - pci_vendordata); 5107 if (left <= 0) { 5108 *ptr = cp; 5109 return(1); 5110 } 5111 5112 /* vendor entry? */ 5113 if (*cp != '\t' && 5114 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 5115 break; 5116 /* device entry? */ 5117 if (*cp == '\t' && 5118 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 5119 break; 5120 5121 /* skip to next line */ 5122 while (*cp != '\n' && left > 0) { 5123 cp++; 5124 left--; 5125 } 5126 if (*cp == '\n') { 5127 cp++; 5128 left--; 5129 } 5130 } 5131 /* skip to next line */ 5132 while (*cp != '\n' && left > 0) { 5133 cp++; 5134 left--; 5135 } 5136 if (*cp == '\n' && left > 0) 5137 cp++; 5138 *ptr = cp; 5139 return(0); 5140 } 5141 5142 static char * 5143 pci_describe_device(device_t dev) 5144 { 5145 int vendor, device; 5146 char *desc, *vp, *dp, *line; 5147 5148 desc = vp = dp = NULL; 5149 5150 /* 5151 * If we have no vendor data, we can't do anything. 5152 */ 5153 if (pci_vendordata == NULL) 5154 goto out; 5155 5156 /* 5157 * Scan the vendor data looking for this device 5158 */ 5159 line = pci_vendordata; 5160 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5161 goto out; 5162 for (;;) { 5163 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 5164 goto out; 5165 if (vendor == pci_get_vendor(dev)) 5166 break; 5167 } 5168 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5169 goto out; 5170 for (;;) { 5171 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 5172 *dp = 0; 5173 break; 5174 } 5175 if (vendor != -1) { 5176 *dp = 0; 5177 break; 5178 } 5179 if (device == pci_get_device(dev)) 5180 break; 5181 } 5182 if (dp[0] == '\0') 5183 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 5184 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 5185 NULL) 5186 sprintf(desc, "%s, %s", vp, dp); 5187 out: 5188 if (vp != NULL) 5189 free(vp, M_DEVBUF); 5190 if (dp != NULL) 5191 free(dp, M_DEVBUF); 5192 return(desc); 5193 } 5194 5195 int 5196 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 5197 { 5198 struct pci_devinfo *dinfo; 5199 pcicfgregs *cfg; 5200 5201 dinfo = device_get_ivars(child); 5202 cfg = &dinfo->cfg; 5203 5204 switch (which) { 5205 case PCI_IVAR_ETHADDR: 5206 /* 5207 * The generic accessor doesn't deal with failure, so 5208 * we set the return value, then return an error. 5209 */ 5210 *((uint8_t **) result) = NULL; 5211 return (EINVAL); 5212 case PCI_IVAR_SUBVENDOR: 5213 *result = cfg->subvendor; 5214 break; 5215 case PCI_IVAR_SUBDEVICE: 5216 *result = cfg->subdevice; 5217 break; 5218 case PCI_IVAR_VENDOR: 5219 *result = cfg->vendor; 5220 break; 5221 case PCI_IVAR_DEVICE: 5222 *result = cfg->device; 5223 break; 5224 case PCI_IVAR_DEVID: 5225 *result = (cfg->device << 16) | cfg->vendor; 5226 break; 5227 case PCI_IVAR_CLASS: 5228 *result = cfg->baseclass; 5229 break; 5230 case PCI_IVAR_SUBCLASS: 5231 *result = cfg->subclass; 5232 break; 5233 case PCI_IVAR_PROGIF: 5234 *result = cfg->progif; 5235 break; 5236 case PCI_IVAR_REVID: 5237 *result = cfg->revid; 5238 break; 5239 case PCI_IVAR_INTPIN: 5240 *result = cfg->intpin; 5241 break; 5242 case PCI_IVAR_IRQ: 5243 *result = cfg->intline; 5244 break; 5245 case PCI_IVAR_DOMAIN: 5246 *result = cfg->domain; 5247 break; 5248 case PCI_IVAR_BUS: 5249 *result = cfg->bus; 5250 break; 5251 case PCI_IVAR_SLOT: 5252 *result = cfg->slot; 5253 break; 5254 case PCI_IVAR_FUNCTION: 5255 *result = cfg->func; 5256 break; 5257 case PCI_IVAR_CMDREG: 5258 *result = cfg->cmdreg; 5259 break; 5260 case PCI_IVAR_CACHELNSZ: 5261 *result = cfg->cachelnsz; 5262 break; 5263 case PCI_IVAR_MINGNT: 5264 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5265 *result = -1; 5266 return (EINVAL); 5267 } 5268 *result = cfg->mingnt; 5269 break; 5270 case PCI_IVAR_MAXLAT: 5271 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5272 *result = -1; 5273 return (EINVAL); 5274 } 5275 *result = cfg->maxlat; 5276 break; 5277 case PCI_IVAR_LATTIMER: 5278 *result = cfg->lattimer; 5279 break; 5280 default: 5281 return (ENOENT); 5282 } 5283 return (0); 5284 } 5285 5286 int 5287 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 5288 { 5289 struct pci_devinfo *dinfo; 5290 5291 dinfo = device_get_ivars(child); 5292 5293 switch (which) { 5294 case PCI_IVAR_INTPIN: 5295 dinfo->cfg.intpin = value; 5296 return (0); 5297 case PCI_IVAR_ETHADDR: 5298 case PCI_IVAR_SUBVENDOR: 5299 case PCI_IVAR_SUBDEVICE: 5300 case PCI_IVAR_VENDOR: 5301 case PCI_IVAR_DEVICE: 5302 case PCI_IVAR_DEVID: 5303 case PCI_IVAR_CLASS: 5304 case PCI_IVAR_SUBCLASS: 5305 case PCI_IVAR_PROGIF: 5306 case PCI_IVAR_REVID: 5307 case PCI_IVAR_IRQ: 5308 case PCI_IVAR_DOMAIN: 5309 case PCI_IVAR_BUS: 5310 case PCI_IVAR_SLOT: 5311 case PCI_IVAR_FUNCTION: 5312 return (EINVAL); /* disallow for now */ 5313 5314 default: 5315 return (ENOENT); 5316 } 5317 } 5318 5319 #include "opt_ddb.h" 5320 #ifdef DDB 5321 #include <ddb/ddb.h> 5322 #include <sys/cons.h> 5323 5324 /* 5325 * List resources based on pci map registers, used for within ddb 5326 */ 5327 5328 DB_SHOW_COMMAND(pciregs, db_pci_dump) 5329 { 5330 struct pci_devinfo *dinfo; 5331 struct devlist *devlist_head; 5332 struct pci_conf *p; 5333 const char *name; 5334 int i, error, none_count; 5335 5336 none_count = 0; 5337 /* get the head of the device queue */ 5338 devlist_head = &pci_devq; 5339 5340 /* 5341 * Go through the list of devices and print out devices 5342 */ 5343 for (error = 0, i = 0, 5344 dinfo = STAILQ_FIRST(devlist_head); 5345 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 5346 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 5347 /* Populate pd_name and pd_unit */ 5348 name = NULL; 5349 if (dinfo->cfg.dev) 5350 name = device_get_name(dinfo->cfg.dev); 5351 5352 p = &dinfo->conf; 5353 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x " 5354 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 5355 (name && *name) ? name : "none", 5356 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 5357 none_count++, 5358 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, 5359 p->pc_sel.pc_func, (p->pc_class << 16) | 5360 (p->pc_subclass << 8) | p->pc_progif, 5361 (p->pc_subdevice << 16) | p->pc_subvendor, 5362 (p->pc_device << 16) | p->pc_vendor, 5363 p->pc_revid, p->pc_hdr); 5364 } 5365 } 5366 #endif /* DDB */ 5367 5368 static struct resource * 5369 pci_reserve_map(device_t dev, device_t child, int type, int *rid, 5370 rman_res_t start, rman_res_t end, rman_res_t count, u_int num, 5371 u_int flags) 5372 { 5373 struct pci_devinfo *dinfo = device_get_ivars(child); 5374 struct resource_list *rl = &dinfo->resources; 5375 struct resource *res; 5376 struct pci_map *pm; 5377 uint16_t cmd; 5378 pci_addr_t map, testval; 5379 int mapsize; 5380 5381 res = NULL; 5382 5383 /* If rid is managed by EA, ignore it */ 5384 if (pci_ea_is_enabled(child, *rid)) 5385 goto out; 5386 5387 pm = pci_find_bar(child, *rid); 5388 if (pm != NULL) { 5389 /* This is a BAR that we failed to allocate earlier. */ 5390 mapsize = pm->pm_size; 5391 map = pm->pm_value; 5392 } else { 5393 /* 5394 * Weed out the bogons, and figure out how large the 5395 * BAR/map is. BARs that read back 0 here are bogus 5396 * and unimplemented. Note: atapci in legacy mode are 5397 * special and handled elsewhere in the code. If you 5398 * have a atapci device in legacy mode and it fails 5399 * here, that other code is broken. 5400 */ 5401 pci_read_bar(child, *rid, &map, &testval, NULL); 5402 5403 /* 5404 * Determine the size of the BAR and ignore BARs with a size 5405 * of 0. Device ROM BARs use a different mask value. 5406 */ 5407 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) 5408 mapsize = pci_romsize(testval); 5409 else 5410 mapsize = pci_mapsize(testval); 5411 if (mapsize == 0) 5412 goto out; 5413 pm = pci_add_bar(child, *rid, map, mapsize); 5414 } 5415 5416 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { 5417 if (type != SYS_RES_MEMORY) { 5418 if (bootverbose) 5419 device_printf(dev, 5420 "child %s requested type %d for rid %#x," 5421 " but the BAR says it is an memio\n", 5422 device_get_nameunit(child), type, *rid); 5423 goto out; 5424 } 5425 } else { 5426 if (type != SYS_RES_IOPORT) { 5427 if (bootverbose) 5428 device_printf(dev, 5429 "child %s requested type %d for rid %#x," 5430 " but the BAR says it is an ioport\n", 5431 device_get_nameunit(child), type, *rid); 5432 goto out; 5433 } 5434 } 5435 5436 /* 5437 * For real BARs, we need to override the size that 5438 * the driver requests, because that's what the BAR 5439 * actually uses and we would otherwise have a 5440 * situation where we might allocate the excess to 5441 * another driver, which won't work. 5442 */ 5443 count = ((pci_addr_t)1 << mapsize) * num; 5444 if (RF_ALIGNMENT(flags) < mapsize) 5445 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 5446 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH)) 5447 flags |= RF_PREFETCHABLE; 5448 5449 /* 5450 * Allocate enough resource, and then write back the 5451 * appropriate BAR for that resource. 5452 */ 5453 resource_list_add(rl, type, *rid, start, end, count); 5454 res = resource_list_reserve(rl, dev, child, type, rid, start, end, 5455 count, flags & ~RF_ACTIVE); 5456 if (res == NULL) { 5457 resource_list_delete(rl, type, *rid); 5458 device_printf(child, 5459 "%#jx bytes of rid %#x res %d failed (%#jx, %#jx).\n", 5460 count, *rid, type, start, end); 5461 goto out; 5462 } 5463 if (bootverbose) 5464 device_printf(child, 5465 "Lazy allocation of %#jx bytes rid %#x type %d at %#jx\n", 5466 count, *rid, type, rman_get_start(res)); 5467 5468 /* Disable decoding via the CMD register before updating the BAR */ 5469 cmd = pci_read_config(child, PCIR_COMMAND, 2); 5470 pci_write_config(child, PCIR_COMMAND, 5471 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 5472 5473 map = rman_get_start(res); 5474 pci_write_bar(child, pm, map); 5475 5476 /* Restore the original value of the CMD register */ 5477 pci_write_config(child, PCIR_COMMAND, cmd, 2); 5478 out: 5479 return (res); 5480 } 5481 5482 struct resource * 5483 pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid, 5484 rman_res_t start, rman_res_t end, rman_res_t count, u_long num, 5485 u_int flags) 5486 { 5487 struct pci_devinfo *dinfo; 5488 struct resource_list *rl; 5489 struct resource_list_entry *rle; 5490 struct resource *res; 5491 pcicfgregs *cfg; 5492 5493 /* 5494 * Perform lazy resource allocation 5495 */ 5496 dinfo = device_get_ivars(child); 5497 rl = &dinfo->resources; 5498 cfg = &dinfo->cfg; 5499 switch (type) { 5500 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 5501 case PCI_RES_BUS: 5502 return (pci_alloc_secbus(dev, child, rid, start, end, count, 5503 flags)); 5504 #endif 5505 case SYS_RES_IRQ: 5506 /* 5507 * Can't alloc legacy interrupt once MSI messages have 5508 * been allocated. 5509 */ 5510 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 5511 cfg->msix.msix_alloc > 0)) 5512 return (NULL); 5513 5514 /* 5515 * If the child device doesn't have an interrupt 5516 * routed and is deserving of an interrupt, try to 5517 * assign it one. 5518 */ 5519 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 5520 (cfg->intpin != 0)) 5521 pci_assign_interrupt(dev, child, 0); 5522 break; 5523 case SYS_RES_IOPORT: 5524 case SYS_RES_MEMORY: 5525 #ifdef NEW_PCIB 5526 /* 5527 * PCI-PCI bridge I/O window resources are not BARs. 5528 * For those allocations just pass the request up the 5529 * tree. 5530 */ 5531 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { 5532 switch (*rid) { 5533 case PCIR_IOBASEL_1: 5534 case PCIR_MEMBASE_1: 5535 case PCIR_PMBASEL_1: 5536 /* 5537 * XXX: Should we bother creating a resource 5538 * list entry? 5539 */ 5540 return (bus_generic_alloc_resource(dev, child, 5541 type, rid, start, end, count, flags)); 5542 } 5543 } 5544 #endif 5545 /* Reserve resources for this BAR if needed. */ 5546 rle = resource_list_find(rl, type, *rid); 5547 if (rle == NULL) { 5548 res = pci_reserve_map(dev, child, type, rid, start, end, 5549 count, num, flags); 5550 if (res == NULL) 5551 return (NULL); 5552 } 5553 } 5554 return (resource_list_alloc(rl, dev, child, type, rid, 5555 start, end, count, flags)); 5556 } 5557 5558 struct resource * 5559 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 5560 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 5561 { 5562 #ifdef PCI_IOV 5563 struct pci_devinfo *dinfo; 5564 #endif 5565 5566 if (device_get_parent(child) != dev) 5567 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 5568 type, rid, start, end, count, flags)); 5569 5570 #ifdef PCI_IOV 5571 dinfo = device_get_ivars(child); 5572 if (dinfo->cfg.flags & PCICFG_VF) { 5573 switch (type) { 5574 /* VFs can't have I/O BARs. */ 5575 case SYS_RES_IOPORT: 5576 return (NULL); 5577 case SYS_RES_MEMORY: 5578 return (pci_vf_alloc_mem_resource(dev, child, rid, 5579 start, end, count, flags)); 5580 } 5581 5582 /* Fall through for other types of resource allocations. */ 5583 } 5584 #endif 5585 5586 return (pci_alloc_multi_resource(dev, child, type, rid, start, end, 5587 count, 1, flags)); 5588 } 5589 5590 int 5591 pci_release_resource(device_t dev, device_t child, int type, int rid, 5592 struct resource *r) 5593 { 5594 struct pci_devinfo *dinfo; 5595 struct resource_list *rl; 5596 pcicfgregs *cfg; 5597 5598 if (device_get_parent(child) != dev) 5599 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 5600 type, rid, r)); 5601 5602 dinfo = device_get_ivars(child); 5603 cfg = &dinfo->cfg; 5604 5605 #ifdef PCI_IOV 5606 if (dinfo->cfg.flags & PCICFG_VF) { 5607 switch (type) { 5608 /* VFs can't have I/O BARs. */ 5609 case SYS_RES_IOPORT: 5610 return (EDOOFUS); 5611 case SYS_RES_MEMORY: 5612 return (pci_vf_release_mem_resource(dev, child, rid, 5613 r)); 5614 } 5615 5616 /* Fall through for other types of resource allocations. */ 5617 } 5618 #endif 5619 5620 #ifdef NEW_PCIB 5621 /* 5622 * PCI-PCI bridge I/O window resources are not BARs. For 5623 * those allocations just pass the request up the tree. 5624 */ 5625 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && 5626 (type == SYS_RES_IOPORT || type == SYS_RES_MEMORY)) { 5627 switch (rid) { 5628 case PCIR_IOBASEL_1: 5629 case PCIR_MEMBASE_1: 5630 case PCIR_PMBASEL_1: 5631 return (bus_generic_release_resource(dev, child, type, 5632 rid, r)); 5633 } 5634 } 5635 #endif 5636 5637 rl = &dinfo->resources; 5638 return (resource_list_release(rl, dev, child, type, rid, r)); 5639 } 5640 5641 int 5642 pci_activate_resource(device_t dev, device_t child, int type, int rid, 5643 struct resource *r) 5644 { 5645 struct pci_devinfo *dinfo; 5646 int error; 5647 5648 error = bus_generic_activate_resource(dev, child, type, rid, r); 5649 if (error) 5650 return (error); 5651 5652 /* Enable decoding in the command register when activating BARs. */ 5653 if (device_get_parent(child) == dev) { 5654 /* Device ROMs need their decoding explicitly enabled. */ 5655 dinfo = device_get_ivars(child); 5656 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5657 pci_write_bar(child, pci_find_bar(child, rid), 5658 rman_get_start(r) | PCIM_BIOS_ENABLE); 5659 switch (type) { 5660 case SYS_RES_IOPORT: 5661 case SYS_RES_MEMORY: 5662 error = PCI_ENABLE_IO(dev, child, type); 5663 break; 5664 } 5665 } 5666 return (error); 5667 } 5668 5669 int 5670 pci_deactivate_resource(device_t dev, device_t child, int type, 5671 int rid, struct resource *r) 5672 { 5673 struct pci_devinfo *dinfo; 5674 int error; 5675 5676 error = bus_generic_deactivate_resource(dev, child, type, rid, r); 5677 if (error) 5678 return (error); 5679 5680 /* Disable decoding for device ROMs. */ 5681 if (device_get_parent(child) == dev) { 5682 dinfo = device_get_ivars(child); 5683 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5684 pci_write_bar(child, pci_find_bar(child, rid), 5685 rman_get_start(r)); 5686 } 5687 return (0); 5688 } 5689 5690 void 5691 pci_child_deleted(device_t dev, device_t child) 5692 { 5693 struct resource_list_entry *rle; 5694 struct resource_list *rl; 5695 struct pci_devinfo *dinfo; 5696 5697 dinfo = device_get_ivars(child); 5698 rl = &dinfo->resources; 5699 5700 EVENTHANDLER_INVOKE(pci_delete_device, child); 5701 5702 /* Turn off access to resources we're about to free */ 5703 if (bus_child_present(child) != 0) { 5704 pci_write_config(child, PCIR_COMMAND, pci_read_config(child, 5705 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2); 5706 5707 pci_disable_busmaster(child); 5708 } 5709 5710 /* Free all allocated resources */ 5711 STAILQ_FOREACH(rle, rl, link) { 5712 if (rle->res) { 5713 if (rman_get_flags(rle->res) & RF_ACTIVE || 5714 resource_list_busy(rl, rle->type, rle->rid)) { 5715 pci_printf(&dinfo->cfg, 5716 "Resource still owned, oops. " 5717 "(type=%d, rid=%d, addr=%lx)\n", 5718 rle->type, rle->rid, 5719 rman_get_start(rle->res)); 5720 bus_release_resource(child, rle->type, rle->rid, 5721 rle->res); 5722 } 5723 resource_list_unreserve(rl, dev, child, rle->type, 5724 rle->rid); 5725 } 5726 } 5727 resource_list_free(rl); 5728 5729 pci_freecfg(dinfo); 5730 } 5731 5732 void 5733 pci_delete_resource(device_t dev, device_t child, int type, int rid) 5734 { 5735 struct pci_devinfo *dinfo; 5736 struct resource_list *rl; 5737 struct resource_list_entry *rle; 5738 5739 if (device_get_parent(child) != dev) 5740 return; 5741 5742 dinfo = device_get_ivars(child); 5743 rl = &dinfo->resources; 5744 rle = resource_list_find(rl, type, rid); 5745 if (rle == NULL) 5746 return; 5747 5748 if (rle->res) { 5749 if (rman_get_flags(rle->res) & RF_ACTIVE || 5750 resource_list_busy(rl, type, rid)) { 5751 device_printf(dev, "delete_resource: " 5752 "Resource still owned by child, oops. " 5753 "(type=%d, rid=%d, addr=%jx)\n", 5754 type, rid, rman_get_start(rle->res)); 5755 return; 5756 } 5757 resource_list_unreserve(rl, dev, child, type, rid); 5758 } 5759 resource_list_delete(rl, type, rid); 5760 } 5761 5762 struct resource_list * 5763 pci_get_resource_list (device_t dev, device_t child) 5764 { 5765 struct pci_devinfo *dinfo = device_get_ivars(child); 5766 5767 return (&dinfo->resources); 5768 } 5769 5770 #ifdef IOMMU 5771 bus_dma_tag_t 5772 pci_get_dma_tag(device_t bus, device_t dev) 5773 { 5774 bus_dma_tag_t tag; 5775 struct pci_softc *sc; 5776 5777 if (device_get_parent(dev) == bus) { 5778 /* try iommu and return if it works */ 5779 tag = iommu_get_dma_tag(bus, dev); 5780 } else 5781 tag = NULL; 5782 if (tag == NULL) { 5783 sc = device_get_softc(bus); 5784 tag = sc->sc_dma_tag; 5785 } 5786 return (tag); 5787 } 5788 #else 5789 bus_dma_tag_t 5790 pci_get_dma_tag(device_t bus, device_t dev) 5791 { 5792 struct pci_softc *sc = device_get_softc(bus); 5793 5794 return (sc->sc_dma_tag); 5795 } 5796 #endif 5797 5798 uint32_t 5799 pci_read_config_method(device_t dev, device_t child, int reg, int width) 5800 { 5801 struct pci_devinfo *dinfo = device_get_ivars(child); 5802 pcicfgregs *cfg = &dinfo->cfg; 5803 5804 #ifdef PCI_IOV 5805 /* 5806 * SR-IOV VFs don't implement the VID or DID registers, so we have to 5807 * emulate them here. 5808 */ 5809 if (cfg->flags & PCICFG_VF) { 5810 if (reg == PCIR_VENDOR) { 5811 switch (width) { 5812 case 4: 5813 return (cfg->device << 16 | cfg->vendor); 5814 case 2: 5815 return (cfg->vendor); 5816 case 1: 5817 return (cfg->vendor & 0xff); 5818 default: 5819 return (0xffffffff); 5820 } 5821 } else if (reg == PCIR_DEVICE) { 5822 switch (width) { 5823 /* Note that an unaligned 4-byte read is an error. */ 5824 case 2: 5825 return (cfg->device); 5826 case 1: 5827 return (cfg->device & 0xff); 5828 default: 5829 return (0xffffffff); 5830 } 5831 } 5832 } 5833 #endif 5834 5835 return (PCIB_READ_CONFIG(device_get_parent(dev), 5836 cfg->bus, cfg->slot, cfg->func, reg, width)); 5837 } 5838 5839 void 5840 pci_write_config_method(device_t dev, device_t child, int reg, 5841 uint32_t val, int width) 5842 { 5843 struct pci_devinfo *dinfo = device_get_ivars(child); 5844 pcicfgregs *cfg = &dinfo->cfg; 5845 5846 PCIB_WRITE_CONFIG(device_get_parent(dev), 5847 cfg->bus, cfg->slot, cfg->func, reg, val, width); 5848 } 5849 5850 int 5851 pci_child_location_method(device_t dev, device_t child, struct sbuf *sb) 5852 { 5853 5854 sbuf_printf(sb, "slot=%d function=%d dbsf=pci%d:%d:%d:%d", 5855 pci_get_slot(child), pci_get_function(child), pci_get_domain(child), 5856 pci_get_bus(child), pci_get_slot(child), pci_get_function(child)); 5857 return (0); 5858 } 5859 5860 int 5861 pci_child_pnpinfo_method(device_t dev, device_t child, struct sbuf *sb) 5862 { 5863 struct pci_devinfo *dinfo; 5864 pcicfgregs *cfg; 5865 5866 dinfo = device_get_ivars(child); 5867 cfg = &dinfo->cfg; 5868 sbuf_printf(sb, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 5869 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 5870 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 5871 cfg->progif); 5872 return (0); 5873 } 5874 5875 int 5876 pci_assign_interrupt_method(device_t dev, device_t child) 5877 { 5878 struct pci_devinfo *dinfo = device_get_ivars(child); 5879 pcicfgregs *cfg = &dinfo->cfg; 5880 5881 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 5882 cfg->intpin)); 5883 } 5884 5885 static void 5886 pci_lookup(void *arg, const char *name, device_t *dev) 5887 { 5888 long val; 5889 char *end; 5890 int domain, bus, slot, func; 5891 5892 if (*dev != NULL) 5893 return; 5894 5895 /* 5896 * Accept pciconf-style selectors of either pciD:B:S:F or 5897 * pciB:S:F. In the latter case, the domain is assumed to 5898 * be zero. 5899 */ 5900 if (strncmp(name, "pci", 3) != 0) 5901 return; 5902 val = strtol(name + 3, &end, 10); 5903 if (val < 0 || val > INT_MAX || *end != ':') 5904 return; 5905 domain = val; 5906 val = strtol(end + 1, &end, 10); 5907 if (val < 0 || val > INT_MAX || *end != ':') 5908 return; 5909 bus = val; 5910 val = strtol(end + 1, &end, 10); 5911 if (val < 0 || val > INT_MAX) 5912 return; 5913 slot = val; 5914 if (*end == ':') { 5915 val = strtol(end + 1, &end, 10); 5916 if (val < 0 || val > INT_MAX || *end != '\0') 5917 return; 5918 func = val; 5919 } else if (*end == '\0') { 5920 func = slot; 5921 slot = bus; 5922 bus = domain; 5923 domain = 0; 5924 } else 5925 return; 5926 5927 if (domain > PCI_DOMAINMAX || bus > PCI_BUSMAX || slot > PCI_SLOTMAX || 5928 func > PCIE_ARI_FUNCMAX || (slot != 0 && func > PCI_FUNCMAX)) 5929 return; 5930 5931 *dev = pci_find_dbsf(domain, bus, slot, func); 5932 } 5933 5934 static int 5935 pci_modevent(module_t mod, int what, void *arg) 5936 { 5937 static struct cdev *pci_cdev; 5938 static eventhandler_tag tag; 5939 5940 switch (what) { 5941 case MOD_LOAD: 5942 STAILQ_INIT(&pci_devq); 5943 pci_generation = 0; 5944 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 5945 "pci"); 5946 pci_load_vendor_data(); 5947 tag = EVENTHANDLER_REGISTER(dev_lookup, pci_lookup, NULL, 5948 1000); 5949 break; 5950 5951 case MOD_UNLOAD: 5952 if (tag != NULL) 5953 EVENTHANDLER_DEREGISTER(dev_lookup, tag); 5954 destroy_dev(pci_cdev); 5955 break; 5956 } 5957 5958 return (0); 5959 } 5960 5961 static void 5962 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo) 5963 { 5964 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2) 5965 struct pcicfg_pcie *cfg; 5966 int version, pos; 5967 5968 cfg = &dinfo->cfg.pcie; 5969 pos = cfg->pcie_location; 5970 5971 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 5972 5973 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); 5974 5975 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5976 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 5977 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 5978 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); 5979 5980 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5981 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 5982 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 5983 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); 5984 5985 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5986 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 5987 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); 5988 5989 if (version > 1) { 5990 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); 5991 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); 5992 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); 5993 } 5994 #undef WREG 5995 } 5996 5997 static void 5998 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo) 5999 { 6000 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 6001 dinfo->cfg.pcix.pcix_command, 2); 6002 } 6003 6004 void 6005 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 6006 { 6007 6008 /* 6009 * Restore the device to full power mode. We must do this 6010 * before we restore the registers because moving from D3 to 6011 * D0 will cause the chip's BARs and some other registers to 6012 * be reset to some unknown power on reset values. Cut down 6013 * the noise on boot by doing nothing if we are already in 6014 * state D0. 6015 */ 6016 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) 6017 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6018 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 6019 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 6020 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 6021 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 6022 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 6023 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 6024 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6025 case PCIM_HDRTYPE_NORMAL: 6026 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 6027 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 6028 break; 6029 case PCIM_HDRTYPE_BRIDGE: 6030 pci_write_config(dev, PCIR_SECLAT_1, 6031 dinfo->cfg.bridge.br_seclat, 1); 6032 pci_write_config(dev, PCIR_SUBBUS_1, 6033 dinfo->cfg.bridge.br_subbus, 1); 6034 pci_write_config(dev, PCIR_SECBUS_1, 6035 dinfo->cfg.bridge.br_secbus, 1); 6036 pci_write_config(dev, PCIR_PRIBUS_1, 6037 dinfo->cfg.bridge.br_pribus, 1); 6038 pci_write_config(dev, PCIR_BRIDGECTL_1, 6039 dinfo->cfg.bridge.br_control, 2); 6040 break; 6041 case PCIM_HDRTYPE_CARDBUS: 6042 pci_write_config(dev, PCIR_SECLAT_2, 6043 dinfo->cfg.bridge.br_seclat, 1); 6044 pci_write_config(dev, PCIR_SUBBUS_2, 6045 dinfo->cfg.bridge.br_subbus, 1); 6046 pci_write_config(dev, PCIR_SECBUS_2, 6047 dinfo->cfg.bridge.br_secbus, 1); 6048 pci_write_config(dev, PCIR_PRIBUS_2, 6049 dinfo->cfg.bridge.br_pribus, 1); 6050 pci_write_config(dev, PCIR_BRIDGECTL_2, 6051 dinfo->cfg.bridge.br_control, 2); 6052 break; 6053 } 6054 pci_restore_bars(dev); 6055 6056 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE) 6057 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 6058 6059 /* 6060 * Restore extended capabilities for PCI-Express and PCI-X 6061 */ 6062 if (dinfo->cfg.pcie.pcie_location != 0) 6063 pci_cfg_restore_pcie(dev, dinfo); 6064 if (dinfo->cfg.pcix.pcix_location != 0) 6065 pci_cfg_restore_pcix(dev, dinfo); 6066 6067 /* Restore MSI and MSI-X configurations if they are present. */ 6068 if (dinfo->cfg.msi.msi_location != 0) 6069 pci_resume_msi(dev); 6070 if (dinfo->cfg.msix.msix_location != 0) 6071 pci_resume_msix(dev); 6072 6073 #ifdef PCI_IOV 6074 if (dinfo->cfg.iov != NULL) 6075 pci_iov_cfg_restore(dev, dinfo); 6076 #endif 6077 } 6078 6079 static void 6080 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo) 6081 { 6082 #define RREG(n) pci_read_config(dev, pos + (n), 2) 6083 struct pcicfg_pcie *cfg; 6084 int version, pos; 6085 6086 cfg = &dinfo->cfg.pcie; 6087 pos = cfg->pcie_location; 6088 6089 cfg->pcie_flags = RREG(PCIER_FLAGS); 6090 6091 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6092 6093 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); 6094 6095 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6096 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6097 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6098 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); 6099 6100 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6101 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6102 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6103 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); 6104 6105 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6106 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6107 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); 6108 6109 if (version > 1) { 6110 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); 6111 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); 6112 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); 6113 } 6114 #undef RREG 6115 } 6116 6117 static void 6118 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo) 6119 { 6120 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, 6121 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); 6122 } 6123 6124 void 6125 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 6126 { 6127 uint32_t cls; 6128 int ps; 6129 6130 /* 6131 * Some drivers apparently write to these registers w/o updating our 6132 * cached copy. No harm happens if we update the copy, so do so here 6133 * so we can restore them. The COMMAND register is modified by the 6134 * bus w/o updating the cache. This should represent the normally 6135 * writable portion of the 'defined' part of type 0/1/2 headers. 6136 */ 6137 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 6138 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 6139 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 6140 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 6141 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 6142 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 6143 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 6144 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 6145 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 6146 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 6147 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 6148 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6149 case PCIM_HDRTYPE_NORMAL: 6150 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 6151 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 6152 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 6153 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 6154 break; 6155 case PCIM_HDRTYPE_BRIDGE: 6156 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6157 PCIR_SECLAT_1, 1); 6158 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6159 PCIR_SUBBUS_1, 1); 6160 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6161 PCIR_SECBUS_1, 1); 6162 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6163 PCIR_PRIBUS_1, 1); 6164 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6165 PCIR_BRIDGECTL_1, 2); 6166 break; 6167 case PCIM_HDRTYPE_CARDBUS: 6168 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6169 PCIR_SECLAT_2, 1); 6170 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6171 PCIR_SUBBUS_2, 1); 6172 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6173 PCIR_SECBUS_2, 1); 6174 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6175 PCIR_PRIBUS_2, 1); 6176 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6177 PCIR_BRIDGECTL_2, 2); 6178 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2); 6179 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2); 6180 break; 6181 } 6182 6183 if (dinfo->cfg.pcie.pcie_location != 0) 6184 pci_cfg_save_pcie(dev, dinfo); 6185 6186 if (dinfo->cfg.pcix.pcix_location != 0) 6187 pci_cfg_save_pcix(dev, dinfo); 6188 6189 #ifdef PCI_IOV 6190 if (dinfo->cfg.iov != NULL) 6191 pci_iov_cfg_save(dev, dinfo); 6192 #endif 6193 6194 /* 6195 * don't set the state for display devices, base peripherals and 6196 * memory devices since bad things happen when they are powered down. 6197 * We should (a) have drivers that can easily detach and (b) use 6198 * generic drivers for these devices so that some device actually 6199 * attaches. We need to make sure that when we implement (a) we don't 6200 * power the device down on a reattach. 6201 */ 6202 cls = pci_get_class(dev); 6203 if (!setstate) 6204 return; 6205 switch (pci_do_power_nodriver) 6206 { 6207 case 0: /* NO powerdown at all */ 6208 return; 6209 case 1: /* Conservative about what to power down */ 6210 if (cls == PCIC_STORAGE) 6211 return; 6212 /*FALLTHROUGH*/ 6213 case 2: /* Aggressive about what to power down */ 6214 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 6215 cls == PCIC_BASEPERIPH) 6216 return; 6217 /*FALLTHROUGH*/ 6218 case 3: /* Power down everything */ 6219 break; 6220 } 6221 /* 6222 * PCI spec says we can only go into D3 state from D0 state. 6223 * Transition from D[12] into D0 before going to D3 state. 6224 */ 6225 ps = pci_get_powerstate(dev); 6226 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6227 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6228 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 6229 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6230 } 6231 6232 /* Wrapper APIs suitable for device driver use. */ 6233 void 6234 pci_save_state(device_t dev) 6235 { 6236 struct pci_devinfo *dinfo; 6237 6238 dinfo = device_get_ivars(dev); 6239 pci_cfg_save(dev, dinfo, 0); 6240 } 6241 6242 void 6243 pci_restore_state(device_t dev) 6244 { 6245 struct pci_devinfo *dinfo; 6246 6247 dinfo = device_get_ivars(dev); 6248 pci_cfg_restore(dev, dinfo); 6249 } 6250 6251 static int 6252 pci_get_id_method(device_t dev, device_t child, enum pci_id_type type, 6253 uintptr_t *id) 6254 { 6255 6256 return (PCIB_GET_ID(device_get_parent(dev), child, type, id)); 6257 } 6258 6259 /* Find the upstream port of a given PCI device in a root complex. */ 6260 device_t 6261 pci_find_pcie_root_port(device_t dev) 6262 { 6263 struct pci_devinfo *dinfo; 6264 devclass_t pci_class; 6265 device_t pcib, bus; 6266 6267 pci_class = devclass_find("pci"); 6268 KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class, 6269 ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); 6270 6271 /* 6272 * Walk the bridge hierarchy until we find a PCI-e root 6273 * port or a non-PCI device. 6274 */ 6275 for (;;) { 6276 bus = device_get_parent(dev); 6277 KASSERT(bus != NULL, ("%s: null parent of %s", __func__, 6278 device_get_nameunit(dev))); 6279 6280 pcib = device_get_parent(bus); 6281 KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__, 6282 device_get_nameunit(bus))); 6283 6284 /* 6285 * pcib's parent must be a PCI bus for this to be a 6286 * PCI-PCI bridge. 6287 */ 6288 if (device_get_devclass(device_get_parent(pcib)) != pci_class) 6289 return (NULL); 6290 6291 dinfo = device_get_ivars(pcib); 6292 if (dinfo->cfg.pcie.pcie_location != 0 && 6293 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) 6294 return (pcib); 6295 6296 dev = pcib; 6297 } 6298 } 6299 6300 /* 6301 * Wait for pending transactions to complete on a PCI-express function. 6302 * 6303 * The maximum delay is specified in milliseconds in max_delay. Note 6304 * that this function may sleep. 6305 * 6306 * Returns true if the function is idle and false if the timeout is 6307 * exceeded. If dev is not a PCI-express function, this returns true. 6308 */ 6309 bool 6310 pcie_wait_for_pending_transactions(device_t dev, u_int max_delay) 6311 { 6312 struct pci_devinfo *dinfo = device_get_ivars(dev); 6313 uint16_t sta; 6314 int cap; 6315 6316 cap = dinfo->cfg.pcie.pcie_location; 6317 if (cap == 0) 6318 return (true); 6319 6320 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6321 while (sta & PCIEM_STA_TRANSACTION_PND) { 6322 if (max_delay == 0) 6323 return (false); 6324 6325 /* Poll once every 100 milliseconds up to the timeout. */ 6326 if (max_delay > 100) { 6327 pause_sbt("pcietp", 100 * SBT_1MS, 0, C_HARDCLOCK); 6328 max_delay -= 100; 6329 } else { 6330 pause_sbt("pcietp", max_delay * SBT_1MS, 0, 6331 C_HARDCLOCK); 6332 max_delay = 0; 6333 } 6334 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6335 } 6336 6337 return (true); 6338 } 6339 6340 /* 6341 * Determine the maximum Completion Timeout in microseconds. 6342 * 6343 * For non-PCI-express functions this returns 0. 6344 */ 6345 int 6346 pcie_get_max_completion_timeout(device_t dev) 6347 { 6348 struct pci_devinfo *dinfo = device_get_ivars(dev); 6349 int cap; 6350 6351 cap = dinfo->cfg.pcie.pcie_location; 6352 if (cap == 0) 6353 return (0); 6354 6355 /* 6356 * Functions using the 1.x spec use the default timeout range of 6357 * 50 microseconds to 50 milliseconds. Functions that do not 6358 * support programmable timeouts also use this range. 6359 */ 6360 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 || 6361 (pci_read_config(dev, cap + PCIER_DEVICE_CAP2, 4) & 6362 PCIEM_CAP2_COMP_TIMO_RANGES) == 0) 6363 return (50 * 1000); 6364 6365 switch (pci_read_config(dev, cap + PCIER_DEVICE_CTL2, 2) & 6366 PCIEM_CTL2_COMP_TIMO_VAL) { 6367 case PCIEM_CTL2_COMP_TIMO_100US: 6368 return (100); 6369 case PCIEM_CTL2_COMP_TIMO_10MS: 6370 return (10 * 1000); 6371 case PCIEM_CTL2_COMP_TIMO_55MS: 6372 return (55 * 1000); 6373 case PCIEM_CTL2_COMP_TIMO_210MS: 6374 return (210 * 1000); 6375 case PCIEM_CTL2_COMP_TIMO_900MS: 6376 return (900 * 1000); 6377 case PCIEM_CTL2_COMP_TIMO_3500MS: 6378 return (3500 * 1000); 6379 case PCIEM_CTL2_COMP_TIMO_13S: 6380 return (13 * 1000 * 1000); 6381 case PCIEM_CTL2_COMP_TIMO_64S: 6382 return (64 * 1000 * 1000); 6383 default: 6384 return (50 * 1000); 6385 } 6386 } 6387 6388 void 6389 pcie_apei_error(device_t dev, int sev, uint8_t *aerp) 6390 { 6391 struct pci_devinfo *dinfo = device_get_ivars(dev); 6392 const char *s; 6393 int aer; 6394 uint32_t r, r1; 6395 uint16_t rs; 6396 6397 if (sev == PCIEM_STA_CORRECTABLE_ERROR) 6398 s = "Correctable"; 6399 else if (sev == PCIEM_STA_NON_FATAL_ERROR) 6400 s = "Uncorrectable (Non-Fatal)"; 6401 else 6402 s = "Uncorrectable (Fatal)"; 6403 device_printf(dev, "%s PCIe error reported by APEI\n", s); 6404 if (aerp) { 6405 if (sev == PCIEM_STA_CORRECTABLE_ERROR) { 6406 r = le32dec(aerp + PCIR_AER_COR_STATUS); 6407 r1 = le32dec(aerp + PCIR_AER_COR_MASK); 6408 } else { 6409 r = le32dec(aerp + PCIR_AER_UC_STATUS); 6410 r1 = le32dec(aerp + PCIR_AER_UC_MASK); 6411 } 6412 device_printf(dev, "status 0x%08x mask 0x%08x", r, r1); 6413 if (sev != PCIEM_STA_CORRECTABLE_ERROR) { 6414 r = le32dec(aerp + PCIR_AER_UC_SEVERITY); 6415 rs = le16dec(aerp + PCIR_AER_CAP_CONTROL); 6416 printf(" severity 0x%08x first %d\n", 6417 r, rs & 0x1f); 6418 } else 6419 printf("\n"); 6420 } 6421 6422 /* As kind of recovery just report and clear the error statuses. */ 6423 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6424 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6425 if (r != 0) { 6426 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6427 device_printf(dev, "Clearing UC AER errors 0x%08x\n", r); 6428 } 6429 6430 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6431 if (r != 0) { 6432 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6433 device_printf(dev, "Clearing COR AER errors 0x%08x\n", r); 6434 } 6435 } 6436 if (dinfo->cfg.pcie.pcie_location != 0) { 6437 rs = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6438 PCIER_DEVICE_STA, 2); 6439 if ((rs & (PCIEM_STA_CORRECTABLE_ERROR | 6440 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6441 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6442 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6443 PCIER_DEVICE_STA, rs, 2); 6444 device_printf(dev, "Clearing PCIe errors 0x%04x\n", rs); 6445 } 6446 } 6447 } 6448 6449 /* 6450 * Perform a Function Level Reset (FLR) on a device. 6451 * 6452 * This function first waits for any pending transactions to complete 6453 * within the timeout specified by max_delay. If transactions are 6454 * still pending, the function will return false without attempting a 6455 * reset. 6456 * 6457 * If dev is not a PCI-express function or does not support FLR, this 6458 * function returns false. 6459 * 6460 * Note that no registers are saved or restored. The caller is 6461 * responsible for saving and restoring any registers including 6462 * PCI-standard registers via pci_save_state() and 6463 * pci_restore_state(). 6464 */ 6465 bool 6466 pcie_flr(device_t dev, u_int max_delay, bool force) 6467 { 6468 struct pci_devinfo *dinfo = device_get_ivars(dev); 6469 uint16_t cmd, ctl; 6470 int compl_delay; 6471 int cap; 6472 6473 cap = dinfo->cfg.pcie.pcie_location; 6474 if (cap == 0) 6475 return (false); 6476 6477 if (!(pci_read_config(dev, cap + PCIER_DEVICE_CAP, 4) & PCIEM_CAP_FLR)) 6478 return (false); 6479 6480 /* 6481 * Disable busmastering to prevent generation of new 6482 * transactions while waiting for the device to go idle. If 6483 * the idle timeout fails, the command register is restored 6484 * which will re-enable busmastering. 6485 */ 6486 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 6487 pci_write_config(dev, PCIR_COMMAND, cmd & ~(PCIM_CMD_BUSMASTEREN), 2); 6488 if (!pcie_wait_for_pending_transactions(dev, max_delay)) { 6489 if (!force) { 6490 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 6491 return (false); 6492 } 6493 pci_printf(&dinfo->cfg, 6494 "Resetting with transactions pending after %d ms\n", 6495 max_delay); 6496 6497 /* 6498 * Extend the post-FLR delay to cover the maximum 6499 * Completion Timeout delay of anything in flight 6500 * during the FLR delay. Enforce a minimum delay of 6501 * at least 10ms. 6502 */ 6503 compl_delay = pcie_get_max_completion_timeout(dev) / 1000; 6504 if (compl_delay < 10) 6505 compl_delay = 10; 6506 } else 6507 compl_delay = 0; 6508 6509 /* Initiate the reset. */ 6510 ctl = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 6511 pci_write_config(dev, cap + PCIER_DEVICE_CTL, ctl | 6512 PCIEM_CTL_INITIATE_FLR, 2); 6513 6514 /* Wait for 100ms. */ 6515 pause_sbt("pcieflr", (100 + compl_delay) * SBT_1MS, 0, C_HARDCLOCK); 6516 6517 if (pci_read_config(dev, cap + PCIER_DEVICE_STA, 2) & 6518 PCIEM_STA_TRANSACTION_PND) 6519 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n"); 6520 return (true); 6521 } 6522 6523 /* 6524 * Attempt a power-management reset by cycling the device in/out of D3 6525 * state. PCI spec says we can only go into D3 state from D0 state. 6526 * Transition from D[12] into D0 before going to D3 state. 6527 */ 6528 int 6529 pci_power_reset(device_t dev) 6530 { 6531 int ps; 6532 6533 ps = pci_get_powerstate(dev); 6534 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6535 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6536 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6537 pci_set_powerstate(dev, ps); 6538 return (0); 6539 } 6540 6541 /* 6542 * Try link drop and retrain of the downstream port of upstream 6543 * switch, for PCIe. According to the PCIe 3.0 spec 6.6.1, this must 6544 * cause Conventional Hot reset of the device in the slot. 6545 * Alternative, for PCIe, could be the secondary bus reset initiatied 6546 * on the upstream switch PCIR_BRIDGECTL_1, bit 6. 6547 */ 6548 int 6549 pcie_link_reset(device_t port, int pcie_location) 6550 { 6551 uint16_t v; 6552 6553 v = pci_read_config(port, pcie_location + PCIER_LINK_CTL, 2); 6554 v |= PCIEM_LINK_CTL_LINK_DIS; 6555 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6556 pause_sbt("pcier1", mstosbt(20), 0, 0); 6557 v &= ~PCIEM_LINK_CTL_LINK_DIS; 6558 v |= PCIEM_LINK_CTL_RETRAIN_LINK; 6559 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6560 pause_sbt("pcier2", mstosbt(100), 0, 0); /* 100 ms */ 6561 v = pci_read_config(port, pcie_location + PCIER_LINK_STA, 2); 6562 return ((v & PCIEM_LINK_STA_TRAINING) != 0 ? ETIMEDOUT : 0); 6563 } 6564 6565 static int 6566 pci_reset_post(device_t dev, device_t child) 6567 { 6568 6569 if (dev == device_get_parent(child)) 6570 pci_restore_state(child); 6571 return (0); 6572 } 6573 6574 static int 6575 pci_reset_prepare(device_t dev, device_t child) 6576 { 6577 6578 if (dev == device_get_parent(child)) 6579 pci_save_state(child); 6580 return (0); 6581 } 6582 6583 static int 6584 pci_reset_child(device_t dev, device_t child, int flags) 6585 { 6586 int error; 6587 6588 if (dev == NULL || device_get_parent(child) != dev) 6589 return (0); 6590 if ((flags & DEVF_RESET_DETACH) != 0) { 6591 error = device_get_state(child) == DS_ATTACHED ? 6592 device_detach(child) : 0; 6593 } else { 6594 error = BUS_SUSPEND_CHILD(dev, child); 6595 } 6596 if (error == 0) { 6597 if (!pcie_flr(child, 1000, false)) { 6598 error = BUS_RESET_PREPARE(dev, child); 6599 if (error == 0) 6600 pci_power_reset(child); 6601 BUS_RESET_POST(dev, child); 6602 } 6603 if ((flags & DEVF_RESET_DETACH) != 0) 6604 device_probe_and_attach(child); 6605 else 6606 BUS_RESUME_CHILD(dev, child); 6607 } 6608 return (error); 6609 } 6610 6611 const struct pci_device_table * 6612 pci_match_device(device_t child, const struct pci_device_table *id, size_t nelt) 6613 { 6614 bool match; 6615 uint16_t vendor, device, subvendor, subdevice, class, subclass, revid; 6616 6617 vendor = pci_get_vendor(child); 6618 device = pci_get_device(child); 6619 subvendor = pci_get_subvendor(child); 6620 subdevice = pci_get_subdevice(child); 6621 class = pci_get_class(child); 6622 subclass = pci_get_subclass(child); 6623 revid = pci_get_revid(child); 6624 while (nelt-- > 0) { 6625 match = true; 6626 if (id->match_flag_vendor) 6627 match &= vendor == id->vendor; 6628 if (id->match_flag_device) 6629 match &= device == id->device; 6630 if (id->match_flag_subvendor) 6631 match &= subvendor == id->subvendor; 6632 if (id->match_flag_subdevice) 6633 match &= subdevice == id->subdevice; 6634 if (id->match_flag_class) 6635 match &= class == id->class_id; 6636 if (id->match_flag_subclass) 6637 match &= subclass == id->subclass; 6638 if (id->match_flag_revid) 6639 match &= revid == id->revid; 6640 if (match) 6641 return (id); 6642 id++; 6643 } 6644 return (NULL); 6645 } 6646 6647 static void 6648 pci_print_faulted_dev_name(const struct pci_devinfo *dinfo) 6649 { 6650 const char *dev_name; 6651 device_t dev; 6652 6653 dev = dinfo->cfg.dev; 6654 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus, 6655 dinfo->cfg.slot, dinfo->cfg.func); 6656 dev_name = device_get_name(dev); 6657 if (dev_name != NULL) 6658 printf(" (%s%d)", dev_name, device_get_unit(dev)); 6659 } 6660 6661 void 6662 pci_print_faulted_dev(void) 6663 { 6664 struct pci_devinfo *dinfo; 6665 device_t dev; 6666 int aer, i; 6667 uint32_t r1, r2; 6668 uint16_t status; 6669 6670 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6671 dev = dinfo->cfg.dev; 6672 status = pci_read_config(dev, PCIR_STATUS, 2); 6673 status &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6674 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6675 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6676 if (status != 0) { 6677 pci_print_faulted_dev_name(dinfo); 6678 printf(" error 0x%04x\n", status); 6679 } 6680 if (dinfo->cfg.pcie.pcie_location != 0) { 6681 status = pci_read_config(dev, 6682 dinfo->cfg.pcie.pcie_location + 6683 PCIER_DEVICE_STA, 2); 6684 if ((status & (PCIEM_STA_CORRECTABLE_ERROR | 6685 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6686 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6687 pci_print_faulted_dev_name(dinfo); 6688 printf(" PCIe DEVCTL 0x%04x DEVSTA 0x%04x\n", 6689 pci_read_config(dev, 6690 dinfo->cfg.pcie.pcie_location + 6691 PCIER_DEVICE_CTL, 2), 6692 status); 6693 } 6694 } 6695 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6696 r1 = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6697 r2 = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6698 if (r1 != 0 || r2 != 0) { 6699 pci_print_faulted_dev_name(dinfo); 6700 printf(" AER UC 0x%08x Mask 0x%08x Svr 0x%08x\n" 6701 " COR 0x%08x Mask 0x%08x Ctl 0x%08x\n", 6702 r1, pci_read_config(dev, aer + 6703 PCIR_AER_UC_MASK, 4), 6704 pci_read_config(dev, aer + 6705 PCIR_AER_UC_SEVERITY, 4), 6706 r2, pci_read_config(dev, aer + 6707 PCIR_AER_COR_MASK, 4), 6708 pci_read_config(dev, aer + 6709 PCIR_AER_CAP_CONTROL, 4)); 6710 for (i = 0; i < 4; i++) { 6711 r1 = pci_read_config(dev, aer + 6712 PCIR_AER_HEADER_LOG + i * 4, 4); 6713 printf(" HL%d: 0x%08x\n", i, r1); 6714 } 6715 } 6716 } 6717 } 6718 } 6719 6720 #ifdef DDB 6721 DB_SHOW_COMMAND(pcierr, pci_print_faulted_dev_db) 6722 { 6723 6724 pci_print_faulted_dev(); 6725 } 6726 6727 static void 6728 db_clear_pcie_errors(const struct pci_devinfo *dinfo) 6729 { 6730 device_t dev; 6731 int aer; 6732 uint32_t r; 6733 6734 dev = dinfo->cfg.dev; 6735 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6736 PCIER_DEVICE_STA, 2); 6737 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6738 PCIER_DEVICE_STA, r, 2); 6739 6740 if (pci_find_extcap(dev, PCIZ_AER, &aer) != 0) 6741 return; 6742 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6743 if (r != 0) 6744 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6745 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6746 if (r != 0) 6747 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6748 } 6749 6750 DB_COMMAND(pci_clearerr, db_pci_clearerr) 6751 { 6752 struct pci_devinfo *dinfo; 6753 device_t dev; 6754 uint16_t status, status1; 6755 6756 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6757 dev = dinfo->cfg.dev; 6758 status1 = status = pci_read_config(dev, PCIR_STATUS, 2); 6759 status1 &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6760 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6761 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6762 if (status1 != 0) { 6763 status &= ~status1; 6764 pci_write_config(dev, PCIR_STATUS, status, 2); 6765 } 6766 if (dinfo->cfg.pcie.pcie_location != 0) 6767 db_clear_pcie_errors(dinfo); 6768 } 6769 } 6770 #endif 6771