1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 * 30 */ 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/linker.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/types.h> 44 45 #include <vm/vm.h> 46 #include <vm/pmap.h> 47 #include <vm/vm_extern.h> 48 49 #include <sys/bus.h> 50 #include <machine/bus.h> 51 #include <sys/rman.h> 52 #include <machine/resource.h> 53 54 #include <sys/pciio.h> 55 #include <pci/pcireg.h> 56 #include <pci/pcivar.h> 57 58 #include "pcib_if.h" 59 #include "pci_if.h" 60 61 static u_int32_t pci_mapbase(unsigned mapreg); 62 static int pci_maptype(unsigned mapreg); 63 static int pci_mapsize(unsigned testval); 64 static int pci_maprange(unsigned mapreg); 65 static void pci_fixancient(pcicfgregs *cfg); 66 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 67 pcicfgregs *cfg); 68 static struct pci_devinfo *pci_read_device(device_t pcib, int b, int s, int f); 69 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 70 71 static void pci_print_verbose(struct pci_devinfo *dinfo); 72 static int pci_porten(device_t pcib, int b, int s, int f); 73 static int pci_memen(device_t pcib, int b, int s, int f); 74 static int pci_add_map(device_t pcib, int b, int s, int f, int reg, 75 struct resource_list *rl); 76 static void pci_add_resources(device_t pcib, int b, int s, int f, 77 device_t dev); 78 static void pci_add_children(device_t dev, int busno); 79 static int pci_probe(device_t dev); 80 static int pci_print_resources(struct resource_list *rl, 81 const char *name, int type, 82 const char *format); 83 static int pci_print_child(device_t dev, device_t child); 84 static void pci_probe_nomatch(device_t dev, device_t child); 85 static int pci_describe_parse_line(char **ptr, int *vendor, 86 int *device, char **desc); 87 static char *pci_describe_device(device_t dev); 88 static int pci_read_ivar(device_t dev, device_t child, int which, 89 uintptr_t *result); 90 static int pci_write_ivar(device_t dev, device_t child, int which, 91 uintptr_t value); 92 static struct resource *pci_alloc_resource(device_t dev, device_t child, 93 int type, int *rid, u_long start, 94 u_long end, u_long count, u_int flags); 95 static void pci_delete_resource(device_t dev, device_t child, 96 int type, int rid); 97 static struct resource_list *pci_get_resource_list (device_t dev, device_t child); 98 static u_int32_t pci_read_config_method(device_t dev, device_t child, 99 int reg, int width); 100 static void pci_write_config_method(device_t dev, device_t child, 101 int reg, u_int32_t val, int width); 102 static int pci_modevent(module_t mod, int what, void *arg); 103 104 static device_method_t pci_methods[] = { 105 /* Device interface */ 106 DEVMETHOD(device_probe, pci_probe), 107 DEVMETHOD(device_attach, bus_generic_attach), 108 DEVMETHOD(device_shutdown, bus_generic_shutdown), 109 DEVMETHOD(device_suspend, bus_generic_suspend), 110 DEVMETHOD(device_resume, bus_generic_resume), 111 112 /* Bus interface */ 113 DEVMETHOD(bus_print_child, pci_print_child), 114 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 115 DEVMETHOD(bus_read_ivar, pci_read_ivar), 116 DEVMETHOD(bus_write_ivar, pci_write_ivar), 117 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 118 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 119 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 120 121 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 122 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 123 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 124 DEVMETHOD(bus_delete_resource, pci_delete_resource), 125 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 126 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 127 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 128 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 129 130 /* PCI interface */ 131 DEVMETHOD(pci_read_config, pci_read_config_method), 132 DEVMETHOD(pci_write_config, pci_write_config_method), 133 134 { 0, 0 } 135 }; 136 137 static driver_t pci_driver = { 138 "pci", 139 pci_methods, 140 0, /* no softc */ 141 }; 142 143 static devclass_t pci_devclass; 144 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 145 DRIVER_MODULE(pci, acpi_pcib, pci_driver, pci_devclass, pci_modevent, 0); 146 147 static char *pci_vendordata; 148 static size_t pci_vendordata_size; 149 150 151 struct pci_quirk { 152 u_int32_t devid; /* Vendor/device of the card */ 153 int type; 154 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 155 int arg1; 156 int arg2; 157 }; 158 159 struct pci_quirk pci_quirks[] = { 160 /* 161 * The Intel 82371AB has a map register at offset 0x90. 162 */ 163 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 164 165 { 0 } 166 }; 167 168 /* map register information */ 169 #define PCI_MAPMEM 0x01 /* memory map */ 170 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 171 #define PCI_MAPPORT 0x04 /* port map */ 172 173 u_int32_t pci_numdevs = 0; 174 175 /* return base address of memory or port map */ 176 177 static u_int32_t 178 pci_mapbase(unsigned mapreg) 179 { 180 int mask = 0x03; 181 if ((mapreg & 0x01) == 0) 182 mask = 0x0f; 183 return (mapreg & ~mask); 184 } 185 186 /* return map type of memory or port map */ 187 188 static int 189 pci_maptype(unsigned mapreg) 190 { 191 static u_int8_t maptype[0x10] = { 192 PCI_MAPMEM, PCI_MAPPORT, 193 PCI_MAPMEM, 0, 194 PCI_MAPMEM, PCI_MAPPORT, 195 0, 0, 196 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 197 PCI_MAPMEM|PCI_MAPMEMP, 0, 198 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 199 0, 0, 200 }; 201 202 return maptype[mapreg & 0x0f]; 203 } 204 205 /* return log2 of map size decoded for memory or port map */ 206 207 static int 208 pci_mapsize(unsigned testval) 209 { 210 int ln2size; 211 212 testval = pci_mapbase(testval); 213 ln2size = 0; 214 if (testval != 0) { 215 while ((testval & 1) == 0) 216 { 217 ln2size++; 218 testval >>= 1; 219 } 220 } 221 return (ln2size); 222 } 223 224 /* return log2 of address range supported by map register */ 225 226 static int 227 pci_maprange(unsigned mapreg) 228 { 229 int ln2range = 0; 230 switch (mapreg & 0x07) { 231 case 0x00: 232 case 0x01: 233 case 0x05: 234 ln2range = 32; 235 break; 236 case 0x02: 237 ln2range = 20; 238 break; 239 case 0x04: 240 ln2range = 64; 241 break; 242 } 243 return (ln2range); 244 } 245 246 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 247 248 static void 249 pci_fixancient(pcicfgregs *cfg) 250 { 251 if (cfg->hdrtype != 0) 252 return; 253 254 /* PCI to PCI bridges use header type 1 */ 255 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 256 cfg->hdrtype = 1; 257 } 258 259 /* extract header type specific config data */ 260 261 static void 262 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 263 { 264 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 265 switch (cfg->hdrtype) { 266 case 0: 267 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 268 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 269 cfg->nummaps = PCI_MAXMAPS_0; 270 break; 271 case 1: 272 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 273 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 274 cfg->nummaps = PCI_MAXMAPS_1; 275 break; 276 case 2: 277 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 278 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 279 cfg->nummaps = PCI_MAXMAPS_2; 280 break; 281 } 282 #undef REG 283 } 284 285 /* read configuration header into pcicfgregs structure */ 286 287 static struct pci_devinfo * 288 pci_read_device(device_t pcib, int b, int s, int f) 289 { 290 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 291 pcicfgregs *cfg = NULL; 292 struct pci_devinfo *devlist_entry; 293 struct devlist *devlist_head; 294 295 devlist_head = &pci_devq; 296 297 devlist_entry = NULL; 298 299 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 300 devlist_entry = malloc(sizeof(struct pci_devinfo), 301 M_DEVBUF, M_WAITOK | M_ZERO); 302 if (devlist_entry == NULL) 303 return (NULL); 304 305 cfg = &devlist_entry->cfg; 306 307 cfg->bus = b; 308 cfg->slot = s; 309 cfg->func = f; 310 cfg->vendor = REG(PCIR_VENDOR, 2); 311 cfg->device = REG(PCIR_DEVICE, 2); 312 cfg->cmdreg = REG(PCIR_COMMAND, 2); 313 cfg->statreg = REG(PCIR_STATUS, 2); 314 cfg->baseclass = REG(PCIR_CLASS, 1); 315 cfg->subclass = REG(PCIR_SUBCLASS, 1); 316 cfg->progif = REG(PCIR_PROGIF, 1); 317 cfg->revid = REG(PCIR_REVID, 1); 318 cfg->hdrtype = REG(PCIR_HEADERTYPE, 1); 319 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 320 cfg->lattimer = REG(PCIR_LATTIMER, 1); 321 cfg->intpin = REG(PCIR_INTPIN, 1); 322 cfg->intline = REG(PCIR_INTLINE, 1); 323 324 cfg->mingnt = REG(PCIR_MINGNT, 1); 325 cfg->maxlat = REG(PCIR_MAXLAT, 1); 326 327 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 328 cfg->hdrtype &= ~PCIM_MFDEV; 329 330 pci_fixancient(cfg); 331 pci_hdrtypedata(pcib, b, s, f, cfg); 332 333 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 334 pci_read_extcap(pcib, cfg); 335 336 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 337 338 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 339 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 340 devlist_entry->conf.pc_sel.pc_func = cfg->func; 341 devlist_entry->conf.pc_hdr = cfg->hdrtype; 342 343 devlist_entry->conf.pc_subvendor = cfg->subvendor; 344 devlist_entry->conf.pc_subdevice = cfg->subdevice; 345 devlist_entry->conf.pc_vendor = cfg->vendor; 346 devlist_entry->conf.pc_device = cfg->device; 347 348 devlist_entry->conf.pc_class = cfg->baseclass; 349 devlist_entry->conf.pc_subclass = cfg->subclass; 350 devlist_entry->conf.pc_progif = cfg->progif; 351 devlist_entry->conf.pc_revid = cfg->revid; 352 353 pci_numdevs++; 354 pci_generation++; 355 } 356 return (devlist_entry); 357 #undef REG 358 } 359 360 static void 361 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 362 { 363 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 364 int ptr, nextptr, ptrptr; 365 366 switch (cfg->hdrtype) { 367 case 0: 368 ptrptr = 0x34; 369 break; 370 case 2: 371 ptrptr = 0x14; 372 break; 373 default: 374 return; /* no extended capabilities support */ 375 } 376 nextptr = REG(ptrptr, 1); /* sanity check? */ 377 378 /* 379 * Read capability entries. 380 */ 381 while (nextptr != 0) { 382 /* Sanity check */ 383 if (nextptr > 255) { 384 printf("illegal PCI extended capability offset %d\n", 385 nextptr); 386 return; 387 } 388 /* Find the next entry */ 389 ptr = nextptr; 390 nextptr = REG(ptr + 1, 1); 391 392 /* Process this entry */ 393 switch (REG(ptr, 1)) { 394 case 0x01: /* PCI power management */ 395 if (cfg->pp_cap == 0) { 396 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 397 cfg->pp_status = ptr + PCIR_POWER_STATUS; 398 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 399 if ((nextptr - ptr) > PCIR_POWER_DATA) 400 cfg->pp_data = ptr + PCIR_POWER_DATA; 401 } 402 break; 403 default: 404 break; 405 } 406 } 407 #undef REG 408 } 409 410 #if 0 411 /* free pcicfgregs structure and all depending data structures */ 412 413 static int 414 pci_freecfg(struct pci_devinfo *dinfo) 415 { 416 struct devlist *devlist_head; 417 418 devlist_head = &pci_devq; 419 420 if (dinfo->cfg.map != NULL) 421 free(dinfo->cfg.map, M_DEVBUF); 422 /* XXX this hasn't been tested */ 423 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 424 free(dinfo, M_DEVBUF); 425 426 /* increment the generation count */ 427 pci_generation++; 428 429 /* we're losing one device */ 430 pci_numdevs--; 431 return (0); 432 } 433 #endif 434 435 /* 436 * PCI power manangement 437 */ 438 int 439 pci_set_powerstate(device_t dev, int state) 440 { 441 struct pci_devinfo *dinfo = device_get_ivars(dev); 442 pcicfgregs *cfg = &dinfo->cfg; 443 u_int16_t status; 444 int result; 445 446 if (cfg->pp_cap != 0) { 447 status = pci_read_config(dev, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK; 448 result = 0; 449 switch (state) { 450 case PCI_POWERSTATE_D0: 451 status |= PCIM_PSTAT_D0; 452 break; 453 case PCI_POWERSTATE_D1: 454 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) { 455 status |= PCIM_PSTAT_D1; 456 } else { 457 result = EOPNOTSUPP; 458 } 459 break; 460 case PCI_POWERSTATE_D2: 461 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) { 462 status |= PCIM_PSTAT_D2; 463 } else { 464 result = EOPNOTSUPP; 465 } 466 break; 467 case PCI_POWERSTATE_D3: 468 status |= PCIM_PSTAT_D3; 469 break; 470 default: 471 result = EINVAL; 472 } 473 if (result == 0) 474 pci_write_config(dev, cfg->pp_status, status, 2); 475 } else { 476 result = ENXIO; 477 } 478 return(result); 479 } 480 481 int 482 pci_get_powerstate(device_t dev) 483 { 484 struct pci_devinfo *dinfo = device_get_ivars(dev); 485 pcicfgregs *cfg = &dinfo->cfg; 486 u_int16_t status; 487 int result; 488 489 if (cfg->pp_cap != 0) { 490 status = pci_read_config(dev, cfg->pp_status, 2); 491 switch (status & PCIM_PSTAT_DMASK) { 492 case PCIM_PSTAT_D0: 493 result = PCI_POWERSTATE_D0; 494 break; 495 case PCIM_PSTAT_D1: 496 result = PCI_POWERSTATE_D1; 497 break; 498 case PCIM_PSTAT_D2: 499 result = PCI_POWERSTATE_D2; 500 break; 501 case PCIM_PSTAT_D3: 502 result = PCI_POWERSTATE_D3; 503 break; 504 default: 505 result = PCI_POWERSTATE_UNKNOWN; 506 break; 507 } 508 } else { 509 /* No support, device is always at D0 */ 510 result = PCI_POWERSTATE_D0; 511 } 512 return(result); 513 } 514 515 /* 516 * Some convenience functions for PCI device drivers. 517 */ 518 519 static __inline void 520 pci_set_command_bit(device_t dev, u_int16_t bit) 521 { 522 u_int16_t command; 523 524 command = pci_read_config(dev, PCIR_COMMAND, 2); 525 command |= bit; 526 pci_write_config(dev, PCIR_COMMAND, command, 2); 527 } 528 529 static __inline void 530 pci_clear_command_bit(device_t dev, u_int16_t bit) 531 { 532 u_int16_t command; 533 534 command = pci_read_config(dev, PCIR_COMMAND, 2); 535 command &= ~bit; 536 pci_write_config(dev, PCIR_COMMAND, command, 2); 537 } 538 539 void 540 pci_enable_busmaster(device_t dev) 541 { 542 pci_set_command_bit(dev, PCIM_CMD_BUSMASTEREN); 543 } 544 545 void 546 pci_disable_busmaster(device_t dev) 547 { 548 pci_clear_command_bit(dev, PCIM_CMD_BUSMASTEREN); 549 } 550 551 void 552 pci_enable_io(device_t dev, int space) 553 { 554 switch(space) { 555 case SYS_RES_IOPORT: 556 pci_set_command_bit(dev, PCIM_CMD_PORTEN); 557 break; 558 case SYS_RES_MEMORY: 559 pci_set_command_bit(dev, PCIM_CMD_MEMEN); 560 break; 561 } 562 } 563 564 void 565 pci_disable_io(device_t dev, int space) 566 { 567 switch(space) { 568 case SYS_RES_IOPORT: 569 pci_clear_command_bit(dev, PCIM_CMD_PORTEN); 570 break; 571 case SYS_RES_MEMORY: 572 pci_clear_command_bit(dev, PCIM_CMD_MEMEN); 573 break; 574 } 575 } 576 577 /* 578 * New style pci driver. Parent device is either a pci-host-bridge or a 579 * pci-pci-bridge. Both kinds are represented by instances of pcib. 580 */ 581 582 static void 583 pci_print_verbose(struct pci_devinfo *dinfo) 584 { 585 if (bootverbose) { 586 pcicfgregs *cfg = &dinfo->cfg; 587 588 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 589 cfg->vendor, cfg->device, cfg->revid); 590 printf("\tbus=%d, slot=%d, func=%d\n", 591 cfg->bus, cfg->slot, cfg->func); 592 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 593 cfg->baseclass, cfg->subclass, cfg->progif, 594 cfg->hdrtype, cfg->mfdev); 595 #ifdef PCI_DEBUG 596 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 597 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 598 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 599 cfg->lattimer, cfg->lattimer * 30, 600 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 601 #endif /* PCI_DEBUG */ 602 if (cfg->intpin > 0) 603 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 604 if (cfg->pp_cap) { 605 u_int16_t status; 606 607 status = pci_read_config(cfg->dev, cfg->pp_status, 2); 608 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 609 cfg->pp_cap & PCIM_PCAP_SPEC, 610 cfg->pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 611 cfg->pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 612 status & PCIM_PSTAT_DMASK); 613 } 614 } 615 } 616 617 static int 618 pci_porten(device_t pcib, int b, int s, int f) 619 { 620 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 621 & PCIM_CMD_PORTEN) != 0; 622 } 623 624 static int 625 pci_memen(device_t pcib, int b, int s, int f) 626 { 627 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 628 & PCIM_CMD_MEMEN) != 0; 629 } 630 631 /* 632 * Add a resource based on a pci map register. Return 1 if the map 633 * register is a 32bit map register or 2 if it is a 64bit register. 634 */ 635 static int 636 pci_add_map(device_t pcib, int b, int s, int f, int reg, 637 struct resource_list *rl) 638 { 639 u_int32_t map; 640 u_int64_t base; 641 u_int8_t ln2size; 642 u_int8_t ln2range; 643 u_int32_t testval; 644 #ifdef PCI_ENABLE_IO_MODES 645 u_int16_t cmd; 646 #endif 647 int type; 648 649 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 650 651 if (map == 0 || map == 0xffffffff) 652 return 1; /* skip invalid entry */ 653 654 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 655 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 656 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 657 658 base = pci_mapbase(map); 659 if (pci_maptype(map) & PCI_MAPMEM) 660 type = SYS_RES_MEMORY; 661 else 662 type = SYS_RES_IOPORT; 663 ln2size = pci_mapsize(testval); 664 ln2range = pci_maprange(testval); 665 if (ln2range == 64) { 666 /* Read the other half of a 64bit map register */ 667 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 668 } 669 670 if (bootverbose) { 671 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 672 reg, pci_maptype(map), ln2range, 673 (unsigned int) base, ln2size); 674 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 675 printf(", port disabled\n"); 676 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 677 printf(", memory disabled\n"); 678 else 679 printf(", enabled\n"); 680 } 681 682 /* 683 * This code theoretically does the right thing, but has 684 * undesirable side effects in some cases where 685 * peripherals respond oddly to having these bits 686 * enabled. Leave them alone by default. 687 */ 688 #ifdef PCI_ENABLE_IO_MODES 689 /* Turn on resources that have been left off by a lazy BIOS */ 690 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 691 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 692 cmd |= PCIM_CMD_PORTEN; 693 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 694 } 695 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 696 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 697 cmd |= PCIM_CMD_MEMEN; 698 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 699 } 700 #else 701 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 702 return 1; 703 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 704 return 1; 705 #endif 706 707 resource_list_add(rl, type, reg, 708 base, base + (1 << ln2size) - 1, 709 (1 << ln2size)); 710 711 return (ln2range == 64) ? 2 : 1; 712 } 713 714 static void 715 pci_add_resources(device_t pcib, int b, int s, int f, device_t dev) 716 { 717 struct pci_devinfo *dinfo = device_get_ivars(dev); 718 pcicfgregs *cfg = &dinfo->cfg; 719 struct resource_list *rl = &dinfo->resources; 720 struct pci_quirk *q; 721 int i; 722 723 for (i = 0; i < cfg->nummaps;) { 724 i += pci_add_map(pcib, b, s, f, PCIR_MAPS + i*4, rl); 725 } 726 727 for (q = &pci_quirks[0]; q->devid; q++) { 728 if (q->devid == ((cfg->device << 16) | cfg->vendor) 729 && q->type == PCI_QUIRK_MAP_REG) 730 pci_add_map(pcib, b, s, f, q->arg1, rl); 731 } 732 733 if (cfg->intpin > 0 && cfg->intline != 255) 734 resource_list_add(rl, SYS_RES_IRQ, 0, 735 cfg->intline, cfg->intline, 1); 736 } 737 738 static void 739 pci_add_children(device_t dev, int busno) 740 { 741 device_t pcib = device_get_parent(dev); 742 int maxslots; 743 int s, f; 744 745 maxslots = PCIB_MAXSLOTS(pcib); 746 747 for (s = 0; s <= maxslots; s++) { 748 int pcifunchigh = 0; 749 for (f = 0; f <= pcifunchigh; f++) { 750 struct pci_devinfo *dinfo = 751 pci_read_device(pcib, busno, s, f); 752 if (dinfo != NULL) { 753 if (dinfo->cfg.mfdev) 754 pcifunchigh = PCI_FUNCMAX; 755 756 dinfo->cfg.dev = device_add_child(dev, NULL, -1); 757 device_set_ivars(dinfo->cfg.dev, dinfo); 758 pci_add_resources(pcib, busno, s, f, 759 dinfo->cfg.dev); 760 pci_print_verbose(dinfo); 761 } 762 } 763 } 764 } 765 766 static int 767 pci_probe(device_t dev) 768 { 769 static int once, busno; 770 caddr_t vendordata, info; 771 772 device_set_desc(dev, "PCI bus"); 773 774 if (bootverbose) 775 device_printf(dev, "physical bus=%d\n", pcib_get_bus(dev)); 776 777 /* 778 * Since there can be multiple independantly numbered PCI 779 * busses on some large alpha systems, we can't use the unit 780 * number to decide what bus we are probing. We ask the parent 781 * pcib what our bus number is. 782 */ 783 busno = pcib_get_bus(dev); 784 if (busno < 0) 785 return ENXIO; 786 pci_add_children(dev, busno); 787 788 if (!once) { 789 make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, "pci"); 790 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 791 info = preload_search_info(vendordata, MODINFO_ADDR); 792 pci_vendordata = *(char **)info; 793 info = preload_search_info(vendordata, MODINFO_SIZE); 794 pci_vendordata_size = *(size_t *)info; 795 /* terminate the database */ 796 pci_vendordata[pci_vendordata_size] = '\n'; 797 } 798 once++; 799 } 800 801 return 0; 802 } 803 804 static int 805 pci_print_resources(struct resource_list *rl, const char *name, int type, 806 const char *format) 807 { 808 struct resource_list_entry *rle; 809 int printed, retval; 810 811 printed = 0; 812 retval = 0; 813 /* Yes, this is kinda cheating */ 814 SLIST_FOREACH(rle, rl, link) { 815 if (rle->type == type) { 816 if (printed == 0) 817 retval += printf(" %s ", name); 818 else if (printed > 0) 819 retval += printf(","); 820 printed++; 821 retval += printf(format, rle->start); 822 if (rle->count > 1) { 823 retval += printf("-"); 824 retval += printf(format, rle->start + 825 rle->count - 1); 826 } 827 } 828 } 829 return retval; 830 } 831 832 static int 833 pci_print_child(device_t dev, device_t child) 834 { 835 struct pci_devinfo *dinfo; 836 struct resource_list *rl; 837 pcicfgregs *cfg; 838 int retval = 0; 839 840 dinfo = device_get_ivars(child); 841 cfg = &dinfo->cfg; 842 rl = &dinfo->resources; 843 844 retval += bus_print_child_header(dev, child); 845 846 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx"); 847 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx"); 848 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld"); 849 if (device_get_flags(dev)) 850 retval += printf(" flags %#x", device_get_flags(dev)); 851 852 retval += printf(" at device %d.%d", pci_get_slot(child), 853 pci_get_function(child)); 854 855 retval += bus_print_child_footer(dev, child); 856 857 return (retval); 858 } 859 860 static struct 861 { 862 int class; 863 int subclass; 864 char *desc; 865 } pci_nomatch_tab[] = { 866 {PCIC_OLD, -1, "old"}, 867 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 868 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 869 {PCIC_STORAGE, -1, "mass storage"}, 870 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 871 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 872 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 873 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 874 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 875 {PCIC_NETWORK, -1, "network"}, 876 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 877 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 878 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 879 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 880 {PCIC_DISPLAY, -1, "display"}, 881 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 882 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 883 {PCIC_MULTIMEDIA, -1, "multimedia"}, 884 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 885 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 886 {PCIC_MEMORY, -1, "memory"}, 887 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 888 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 889 {PCIC_BRIDGE, -1, "bridge"}, 890 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 891 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 892 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 893 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 894 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 895 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 896 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 897 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 898 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 899 {PCIC_SIMPLECOMM, -1, "simple comms"}, 900 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 901 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 902 {PCIC_BASEPERIPH, -1, "base peripheral"}, 903 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 904 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 905 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 906 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 907 {PCIC_INPUTDEV, -1, "input device"}, 908 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 909 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 910 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 911 {PCIC_DOCKING, -1, "docking station"}, 912 {PCIC_PROCESSOR, -1, "processor"}, 913 {PCIC_SERIALBUS, -1, "serial bus"}, 914 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 915 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 916 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 917 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 918 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 919 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 920 {0, 0, NULL} 921 }; 922 923 static void 924 pci_probe_nomatch(device_t dev, device_t child) 925 { 926 int i; 927 char *cp, *scp, *device; 928 929 /* 930 * Look for a listing for this device in a loaded device database. 931 */ 932 if ((device = pci_describe_device(child)) != NULL) { 933 device_printf(dev, "<%s>", device); 934 free(device, M_DEVBUF); 935 } else { 936 /* 937 * Scan the class/subclass descriptions for a general description. 938 */ 939 cp = "unknown"; 940 scp = NULL; 941 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 942 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 943 if (pci_nomatch_tab[i].subclass == -1) { 944 cp = pci_nomatch_tab[i].desc; 945 } else if (pci_nomatch_tab[i].subclass == pci_get_subclass(child)) { 946 scp = pci_nomatch_tab[i].desc; 947 } 948 } 949 } 950 device_printf(dev, "<%s%s%s>", 951 cp ? : "", 952 ((cp != NULL) && (scp != NULL)) ? ", " : "", 953 scp ? : ""); 954 } 955 printf(" at %d.%d (no driver attached)\n", 956 pci_get_slot(child), 957 pci_get_function(child)); 958 return; 959 } 960 961 /* 962 * Parse the PCI device database, if loaded, and return a pointer to a 963 * description of the device. 964 * 965 * The database is flat text formatted as follows: 966 * 967 * Any line not in a valid format is ignored. 968 * Lines are terminated with newline '\n' characters. 969 * 970 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 971 * the vendor name. 972 * 973 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 974 * - devices cannot be listed without a corresponding VENDOR line. 975 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 976 * another TAB, then the device name. 977 */ 978 979 /* 980 * Assuming (ptr) points to the beginning of a line in the database, 981 * return the vendor or device and description of the next entry. 982 * The value of (vendor) or (device) inappropriate for the entry type 983 * is set to -1. Returns nonzero at the end of the database. 984 * 985 * Note that this is slightly unrobust in the face of corrupt data; 986 * we attempt to safeguard against this by spamming the end of the 987 * database with a newline when we initialise. 988 */ 989 static int 990 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 991 { 992 char *cp = *ptr; 993 int left; 994 995 *device = -1; 996 *vendor = -1; 997 **desc = '\0'; 998 for (;;) { 999 left = pci_vendordata_size - (cp - pci_vendordata); 1000 if (left <= 0) { 1001 *ptr = cp; 1002 return(1); 1003 } 1004 1005 /* vendor entry? */ 1006 if (*cp != '\t' && sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1007 break; 1008 /* device entry? */ 1009 if (*cp == '\t' && sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1010 break; 1011 1012 /* skip to next line */ 1013 while (*cp != '\n' && left > 0) { 1014 cp++; 1015 left--; 1016 } 1017 if (*cp == '\n') { 1018 cp++; 1019 left--; 1020 } 1021 } 1022 /* skip to next line */ 1023 while (*cp != '\n' && left > 0) { 1024 cp++; 1025 left--; 1026 } 1027 if (*cp == '\n' && left > 0) 1028 cp++; 1029 *ptr = cp; 1030 return(0); 1031 } 1032 1033 static char * 1034 pci_describe_device(device_t dev) 1035 { 1036 int vendor, device; 1037 char *desc, *vp, *dp, *line; 1038 1039 desc = vp = dp = NULL; 1040 1041 /* 1042 * If we have no vendor data, we can't do anything. 1043 */ 1044 if (pci_vendordata == NULL) 1045 goto out; 1046 1047 /* 1048 * Scan the vendor data looking for this device 1049 */ 1050 line = pci_vendordata; 1051 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1052 goto out; 1053 for (;;) { 1054 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1055 goto out; 1056 if (vendor == pci_get_vendor(dev)) 1057 break; 1058 } 1059 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1060 goto out; 1061 for (;;) { 1062 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1063 *dp = 0; 1064 break; 1065 } 1066 if (vendor != -1) { 1067 *dp = 0; 1068 break; 1069 } 1070 if (device == pci_get_device(dev)) 1071 break; 1072 } 1073 if (dp[0] == '\0') 1074 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1075 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != NULL) 1076 sprintf(desc, "%s, %s", vp, dp); 1077 out: 1078 if (vp != NULL) 1079 free(vp, M_DEVBUF); 1080 if (dp != NULL) 1081 free(dp, M_DEVBUF); 1082 return(desc); 1083 } 1084 1085 static int 1086 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1087 { 1088 struct pci_devinfo *dinfo; 1089 pcicfgregs *cfg; 1090 1091 dinfo = device_get_ivars(child); 1092 cfg = &dinfo->cfg; 1093 1094 switch (which) { 1095 case PCI_IVAR_SUBVENDOR: 1096 *result = cfg->subvendor; 1097 break; 1098 case PCI_IVAR_SUBDEVICE: 1099 *result = cfg->subdevice; 1100 break; 1101 case PCI_IVAR_VENDOR: 1102 *result = cfg->vendor; 1103 break; 1104 case PCI_IVAR_DEVICE: 1105 *result = cfg->device; 1106 break; 1107 case PCI_IVAR_DEVID: 1108 *result = (cfg->device << 16) | cfg->vendor; 1109 break; 1110 case PCI_IVAR_CLASS: 1111 *result = cfg->baseclass; 1112 break; 1113 case PCI_IVAR_SUBCLASS: 1114 *result = cfg->subclass; 1115 break; 1116 case PCI_IVAR_PROGIF: 1117 *result = cfg->progif; 1118 break; 1119 case PCI_IVAR_REVID: 1120 *result = cfg->revid; 1121 break; 1122 case PCI_IVAR_INTPIN: 1123 *result = cfg->intpin; 1124 break; 1125 case PCI_IVAR_IRQ: 1126 *result = cfg->intline; 1127 break; 1128 case PCI_IVAR_BUS: 1129 *result = cfg->bus; 1130 break; 1131 case PCI_IVAR_SLOT: 1132 *result = cfg->slot; 1133 break; 1134 case PCI_IVAR_FUNCTION: 1135 *result = cfg->func; 1136 break; 1137 default: 1138 return ENOENT; 1139 } 1140 return 0; 1141 } 1142 1143 static int 1144 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1145 { 1146 struct pci_devinfo *dinfo; 1147 pcicfgregs *cfg; 1148 1149 dinfo = device_get_ivars(child); 1150 cfg = &dinfo->cfg; 1151 1152 switch (which) { 1153 case PCI_IVAR_SUBVENDOR: 1154 case PCI_IVAR_SUBDEVICE: 1155 case PCI_IVAR_VENDOR: 1156 case PCI_IVAR_DEVICE: 1157 case PCI_IVAR_DEVID: 1158 case PCI_IVAR_CLASS: 1159 case PCI_IVAR_SUBCLASS: 1160 case PCI_IVAR_PROGIF: 1161 case PCI_IVAR_REVID: 1162 case PCI_IVAR_INTPIN: 1163 case PCI_IVAR_IRQ: 1164 case PCI_IVAR_BUS: 1165 case PCI_IVAR_SLOT: 1166 case PCI_IVAR_FUNCTION: 1167 return EINVAL; /* disallow for now */ 1168 1169 default: 1170 return ENOENT; 1171 } 1172 return 0; 1173 } 1174 1175 static struct resource * 1176 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1177 u_long start, u_long end, u_long count, u_int flags) 1178 { 1179 struct pci_devinfo *dinfo = device_get_ivars(child); 1180 struct resource_list *rl = &dinfo->resources; 1181 pcicfgregs *cfg = &dinfo->cfg; 1182 1183 /* 1184 * Perform lazy resource allocation 1185 * 1186 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY 1187 */ 1188 if (device_get_parent(child) == dev) { 1189 /* 1190 * If device doesn't have an interrupt routed, and is deserving of 1191 * an interrupt, try to assign it one. 1192 */ 1193 if ((type == SYS_RES_IRQ) && (cfg->intline == 255) && (cfg->intpin != 0)) { 1194 cfg->intline = PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1195 cfg->intpin); 1196 if (cfg->intline != 255) { 1197 pci_write_config(child, PCIR_INTLINE, cfg->intline, 1); 1198 resource_list_add(rl, SYS_RES_IRQ, 0, 1199 cfg->intline, cfg->intline, 1); 1200 } 1201 } 1202 } 1203 1204 return resource_list_alloc(rl, dev, child, type, rid, 1205 start, end, count, flags); 1206 } 1207 1208 static void 1209 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1210 { 1211 printf("pci_delete_resource: PCI resources can not be deleted\n"); 1212 } 1213 1214 static struct resource_list * 1215 pci_get_resource_list (device_t dev, device_t child) 1216 { 1217 struct pci_devinfo * dinfo = device_get_ivars(child); 1218 struct resource_list * rl = &dinfo->resources; 1219 1220 if (!rl) 1221 return (NULL); 1222 1223 return (rl); 1224 } 1225 1226 static u_int32_t 1227 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1228 { 1229 struct pci_devinfo *dinfo = device_get_ivars(child); 1230 pcicfgregs *cfg = &dinfo->cfg; 1231 1232 return PCIB_READ_CONFIG(device_get_parent(dev), 1233 cfg->bus, cfg->slot, cfg->func, 1234 reg, width); 1235 } 1236 1237 static void 1238 pci_write_config_method(device_t dev, device_t child, int reg, 1239 u_int32_t val, int width) 1240 { 1241 struct pci_devinfo *dinfo = device_get_ivars(child); 1242 pcicfgregs *cfg = &dinfo->cfg; 1243 1244 PCIB_WRITE_CONFIG(device_get_parent(dev), 1245 cfg->bus, cfg->slot, cfg->func, 1246 reg, val, width); 1247 } 1248 1249 static int 1250 pci_modevent(module_t mod, int what, void *arg) 1251 { 1252 switch (what) { 1253 case MOD_LOAD: 1254 STAILQ_INIT(&pci_devq); 1255 pci_generation = 0; 1256 break; 1257 1258 case MOD_UNLOAD: 1259 break; 1260 } 1261 1262 return 0; 1263 } 1264