1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 * 30 */ 31 32 #include "opt_bus.h" 33 #include "opt_pci.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/linker.h> 40 #include <sys/fcntl.h> 41 #include <sys/conf.h> 42 #include <sys/kernel.h> 43 #include <sys/queue.h> 44 #include <sys/types.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 55 #include <sys/pciio.h> 56 #include <pci/pcireg.h> 57 #include <pci/pcivar.h> 58 59 #include "pcib_if.h" 60 #include "pci_if.h" 61 62 static u_int32_t pci_mapbase(unsigned mapreg); 63 static int pci_maptype(unsigned mapreg); 64 static int pci_mapsize(unsigned testval); 65 static int pci_maprange(unsigned mapreg); 66 static void pci_fixancient(pcicfgregs *cfg); 67 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 68 pcicfgregs *cfg); 69 static struct pci_devinfo *pci_read_device(device_t pcib, int b, int s, int f); 70 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 71 72 static void pci_print_verbose(struct pci_devinfo *dinfo); 73 static int pci_porten(device_t pcib, int b, int s, int f); 74 static int pci_memen(device_t pcib, int b, int s, int f); 75 static int pci_add_map(device_t pcib, int b, int s, int f, int reg, 76 struct resource_list *rl); 77 static void pci_add_resources(device_t pcib, int b, int s, int f, 78 device_t dev); 79 static void pci_add_children(device_t dev, int busno); 80 static int pci_probe(device_t dev); 81 static int pci_print_child(device_t dev, device_t child); 82 static void pci_probe_nomatch(device_t dev, device_t child); 83 static int pci_describe_parse_line(char **ptr, int *vendor, 84 int *device, char **desc); 85 static char *pci_describe_device(device_t dev); 86 static int pci_read_ivar(device_t dev, device_t child, int which, 87 uintptr_t *result); 88 static int pci_write_ivar(device_t dev, device_t child, int which, 89 uintptr_t value); 90 static struct resource *pci_alloc_resource(device_t dev, device_t child, 91 int type, int *rid, u_long start, 92 u_long end, u_long count, u_int flags); 93 static void pci_delete_resource(device_t dev, device_t child, 94 int type, int rid); 95 static struct resource_list *pci_get_resource_list (device_t dev, device_t child); 96 static u_int32_t pci_read_config_method(device_t dev, device_t child, 97 int reg, int width); 98 static void pci_write_config_method(device_t dev, device_t child, 99 int reg, u_int32_t val, int width); 100 static void pci_enable_busmaster_method(device_t dev, 101 device_t child); 102 static void pci_disable_busmaster_method(device_t dev, 103 device_t child); 104 static void pci_enable_io_method(device_t dev, device_t child, 105 int space); 106 static void pci_disable_io_method(device_t dev, device_t child, 107 int space); 108 static int pci_set_powerstate_method(device_t dev, device_t child, 109 int state); 110 static int pci_get_powerstate_method(device_t dev, device_t child); 111 static int pci_modevent(module_t mod, int what, void *arg); 112 113 static device_method_t pci_methods[] = { 114 /* Device interface */ 115 DEVMETHOD(device_probe, pci_probe), 116 DEVMETHOD(device_attach, bus_generic_attach), 117 DEVMETHOD(device_shutdown, bus_generic_shutdown), 118 DEVMETHOD(device_suspend, bus_generic_suspend), 119 DEVMETHOD(device_resume, bus_generic_resume), 120 121 /* Bus interface */ 122 DEVMETHOD(bus_print_child, pci_print_child), 123 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 124 DEVMETHOD(bus_read_ivar, pci_read_ivar), 125 DEVMETHOD(bus_write_ivar, pci_write_ivar), 126 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 127 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 128 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 129 130 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 131 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 132 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 133 DEVMETHOD(bus_delete_resource, pci_delete_resource), 134 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 135 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 136 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 137 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 138 139 /* PCI interface */ 140 DEVMETHOD(pci_read_config, pci_read_config_method), 141 DEVMETHOD(pci_write_config, pci_write_config_method), 142 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 143 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 144 DEVMETHOD(pci_enable_io, pci_enable_io_method), 145 DEVMETHOD(pci_disable_io, pci_disable_io_method), 146 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 147 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 148 149 { 0, 0 } 150 }; 151 152 static driver_t pci_driver = { 153 "pci", 154 pci_methods, 155 0, /* no softc */ 156 }; 157 158 static devclass_t pci_devclass; 159 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 160 DRIVER_MODULE(pci, acpi_pcib, pci_driver, pci_devclass, pci_modevent, 0); 161 162 static char *pci_vendordata; 163 static size_t pci_vendordata_size; 164 165 166 struct pci_quirk { 167 u_int32_t devid; /* Vendor/device of the card */ 168 int type; 169 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 170 int arg1; 171 int arg2; 172 }; 173 174 struct pci_quirk pci_quirks[] = { 175 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 176 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 177 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 178 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 179 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 180 181 { 0 } 182 }; 183 184 /* map register information */ 185 #define PCI_MAPMEM 0x01 /* memory map */ 186 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 187 #define PCI_MAPPORT 0x04 /* port map */ 188 189 struct devlist pci_devq; 190 u_int32_t pci_generation; 191 u_int32_t pci_numdevs = 0; 192 193 /* Find a device_t by bus/slot/function */ 194 195 device_t 196 pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func) 197 { 198 struct pci_devinfo *dinfo; 199 200 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 201 if ((dinfo->cfg.bus == bus) && 202 (dinfo->cfg.slot == slot) && 203 (dinfo->cfg.func == func)) { 204 return (dinfo->cfg.dev); 205 } 206 } 207 208 return (NULL); 209 } 210 211 /* Find a device_t by vendor/device ID */ 212 213 device_t 214 pci_find_device (u_int16_t vendor, u_int16_t device) 215 { 216 struct pci_devinfo *dinfo; 217 218 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 219 if ((dinfo->cfg.vendor == vendor) && 220 (dinfo->cfg.device == device)) { 221 return (dinfo->cfg.dev); 222 } 223 } 224 225 return (NULL); 226 } 227 228 /* return base address of memory or port map */ 229 230 static u_int32_t 231 pci_mapbase(unsigned mapreg) 232 { 233 int mask = 0x03; 234 if ((mapreg & 0x01) == 0) 235 mask = 0x0f; 236 return (mapreg & ~mask); 237 } 238 239 /* return map type of memory or port map */ 240 241 static int 242 pci_maptype(unsigned mapreg) 243 { 244 static u_int8_t maptype[0x10] = { 245 PCI_MAPMEM, PCI_MAPPORT, 246 PCI_MAPMEM, 0, 247 PCI_MAPMEM, PCI_MAPPORT, 248 0, 0, 249 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 250 PCI_MAPMEM|PCI_MAPMEMP, 0, 251 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 252 0, 0, 253 }; 254 255 return maptype[mapreg & 0x0f]; 256 } 257 258 /* return log2 of map size decoded for memory or port map */ 259 260 static int 261 pci_mapsize(unsigned testval) 262 { 263 int ln2size; 264 265 testval = pci_mapbase(testval); 266 ln2size = 0; 267 if (testval != 0) { 268 while ((testval & 1) == 0) 269 { 270 ln2size++; 271 testval >>= 1; 272 } 273 } 274 return (ln2size); 275 } 276 277 /* return log2 of address range supported by map register */ 278 279 static int 280 pci_maprange(unsigned mapreg) 281 { 282 int ln2range = 0; 283 switch (mapreg & 0x07) { 284 case 0x00: 285 case 0x01: 286 case 0x05: 287 ln2range = 32; 288 break; 289 case 0x02: 290 ln2range = 20; 291 break; 292 case 0x04: 293 ln2range = 64; 294 break; 295 } 296 return (ln2range); 297 } 298 299 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 300 301 static void 302 pci_fixancient(pcicfgregs *cfg) 303 { 304 if (cfg->hdrtype != 0) 305 return; 306 307 /* PCI to PCI bridges use header type 1 */ 308 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 309 cfg->hdrtype = 1; 310 } 311 312 /* extract header type specific config data */ 313 314 static void 315 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 316 { 317 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 318 switch (cfg->hdrtype) { 319 case 0: 320 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 321 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 322 cfg->nummaps = PCI_MAXMAPS_0; 323 break; 324 case 1: 325 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 326 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 327 cfg->nummaps = PCI_MAXMAPS_1; 328 break; 329 case 2: 330 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 331 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 332 cfg->nummaps = PCI_MAXMAPS_2; 333 break; 334 } 335 #undef REG 336 } 337 338 /* read configuration header into pcicfgregs structure */ 339 340 static struct pci_devinfo * 341 pci_read_device(device_t pcib, int b, int s, int f) 342 { 343 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 344 pcicfgregs *cfg = NULL; 345 struct pci_devinfo *devlist_entry; 346 struct devlist *devlist_head; 347 348 devlist_head = &pci_devq; 349 350 devlist_entry = NULL; 351 352 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 353 devlist_entry = malloc(sizeof(struct pci_devinfo), 354 M_DEVBUF, M_WAITOK | M_ZERO); 355 if (devlist_entry == NULL) 356 return (NULL); 357 358 cfg = &devlist_entry->cfg; 359 360 cfg->bus = b; 361 cfg->slot = s; 362 cfg->func = f; 363 cfg->vendor = REG(PCIR_VENDOR, 2); 364 cfg->device = REG(PCIR_DEVICE, 2); 365 cfg->cmdreg = REG(PCIR_COMMAND, 2); 366 cfg->statreg = REG(PCIR_STATUS, 2); 367 cfg->baseclass = REG(PCIR_CLASS, 1); 368 cfg->subclass = REG(PCIR_SUBCLASS, 1); 369 cfg->progif = REG(PCIR_PROGIF, 1); 370 cfg->revid = REG(PCIR_REVID, 1); 371 cfg->hdrtype = REG(PCIR_HEADERTYPE, 1); 372 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 373 cfg->lattimer = REG(PCIR_LATTIMER, 1); 374 cfg->intpin = REG(PCIR_INTPIN, 1); 375 cfg->intline = REG(PCIR_INTLINE, 1); 376 377 cfg->mingnt = REG(PCIR_MINGNT, 1); 378 cfg->maxlat = REG(PCIR_MAXLAT, 1); 379 380 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 381 cfg->hdrtype &= ~PCIM_MFDEV; 382 383 pci_fixancient(cfg); 384 pci_hdrtypedata(pcib, b, s, f, cfg); 385 386 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 387 pci_read_extcap(pcib, cfg); 388 389 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 390 391 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 392 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 393 devlist_entry->conf.pc_sel.pc_func = cfg->func; 394 devlist_entry->conf.pc_hdr = cfg->hdrtype; 395 396 devlist_entry->conf.pc_subvendor = cfg->subvendor; 397 devlist_entry->conf.pc_subdevice = cfg->subdevice; 398 devlist_entry->conf.pc_vendor = cfg->vendor; 399 devlist_entry->conf.pc_device = cfg->device; 400 401 devlist_entry->conf.pc_class = cfg->baseclass; 402 devlist_entry->conf.pc_subclass = cfg->subclass; 403 devlist_entry->conf.pc_progif = cfg->progif; 404 devlist_entry->conf.pc_revid = cfg->revid; 405 406 pci_numdevs++; 407 pci_generation++; 408 } 409 return (devlist_entry); 410 #undef REG 411 } 412 413 static void 414 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 415 { 416 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 417 int ptr, nextptr, ptrptr; 418 419 switch (cfg->hdrtype) { 420 case 0: 421 ptrptr = 0x34; 422 break; 423 case 2: 424 ptrptr = 0x14; 425 break; 426 default: 427 return; /* no extended capabilities support */ 428 } 429 nextptr = REG(ptrptr, 1); /* sanity check? */ 430 431 /* 432 * Read capability entries. 433 */ 434 while (nextptr != 0) { 435 /* Sanity check */ 436 if (nextptr > 255) { 437 printf("illegal PCI extended capability offset %d\n", 438 nextptr); 439 return; 440 } 441 /* Find the next entry */ 442 ptr = nextptr; 443 nextptr = REG(ptr + 1, 1); 444 445 /* Process this entry */ 446 switch (REG(ptr, 1)) { 447 case 0x01: /* PCI power management */ 448 if (cfg->pp_cap == 0) { 449 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 450 cfg->pp_status = ptr + PCIR_POWER_STATUS; 451 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 452 if ((nextptr - ptr) > PCIR_POWER_DATA) 453 cfg->pp_data = ptr + PCIR_POWER_DATA; 454 } 455 break; 456 default: 457 break; 458 } 459 } 460 #undef REG 461 } 462 463 #if 0 464 /* free pcicfgregs structure and all depending data structures */ 465 466 static int 467 pci_freecfg(struct pci_devinfo *dinfo) 468 { 469 struct devlist *devlist_head; 470 471 devlist_head = &pci_devq; 472 473 if (dinfo->cfg.map != NULL) 474 free(dinfo->cfg.map, M_DEVBUF); 475 /* XXX this hasn't been tested */ 476 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 477 free(dinfo, M_DEVBUF); 478 479 /* increment the generation count */ 480 pci_generation++; 481 482 /* we're losing one device */ 483 pci_numdevs--; 484 return (0); 485 } 486 #endif 487 488 /* 489 * PCI power manangement 490 */ 491 static int 492 pci_set_powerstate_method(device_t dev, device_t child, int state) 493 { 494 struct pci_devinfo *dinfo = device_get_ivars(child); 495 pcicfgregs *cfg = &dinfo->cfg; 496 u_int16_t status; 497 int result; 498 499 if (cfg->pp_cap != 0) { 500 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK; 501 result = 0; 502 switch (state) { 503 case PCI_POWERSTATE_D0: 504 status |= PCIM_PSTAT_D0; 505 break; 506 case PCI_POWERSTATE_D1: 507 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) { 508 status |= PCIM_PSTAT_D1; 509 } else { 510 result = EOPNOTSUPP; 511 } 512 break; 513 case PCI_POWERSTATE_D2: 514 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) { 515 status |= PCIM_PSTAT_D2; 516 } else { 517 result = EOPNOTSUPP; 518 } 519 break; 520 case PCI_POWERSTATE_D3: 521 status |= PCIM_PSTAT_D3; 522 break; 523 default: 524 result = EINVAL; 525 } 526 if (result == 0) 527 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2); 528 } else { 529 result = ENXIO; 530 } 531 return(result); 532 } 533 534 static int 535 pci_get_powerstate_method(device_t dev, device_t child) 536 { 537 struct pci_devinfo *dinfo = device_get_ivars(child); 538 pcicfgregs *cfg = &dinfo->cfg; 539 u_int16_t status; 540 int result; 541 542 if (cfg->pp_cap != 0) { 543 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2); 544 switch (status & PCIM_PSTAT_DMASK) { 545 case PCIM_PSTAT_D0: 546 result = PCI_POWERSTATE_D0; 547 break; 548 case PCIM_PSTAT_D1: 549 result = PCI_POWERSTATE_D1; 550 break; 551 case PCIM_PSTAT_D2: 552 result = PCI_POWERSTATE_D2; 553 break; 554 case PCIM_PSTAT_D3: 555 result = PCI_POWERSTATE_D3; 556 break; 557 default: 558 result = PCI_POWERSTATE_UNKNOWN; 559 break; 560 } 561 } else { 562 /* No support, device is always at D0 */ 563 result = PCI_POWERSTATE_D0; 564 } 565 return(result); 566 } 567 568 /* 569 * Some convenience functions for PCI device drivers. 570 */ 571 572 static __inline void 573 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit) 574 { 575 u_int16_t command; 576 577 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 578 command |= bit; 579 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 580 } 581 582 static __inline void 583 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit) 584 { 585 u_int16_t command; 586 587 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 588 command &= ~bit; 589 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 590 } 591 592 static void 593 pci_enable_busmaster_method(device_t dev, device_t child) 594 { 595 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 596 } 597 598 static void 599 pci_disable_busmaster_method(device_t dev, device_t child) 600 { 601 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 602 } 603 604 static void 605 pci_enable_io_method(device_t dev, device_t child, int space) 606 { 607 switch(space) { 608 case SYS_RES_IOPORT: 609 pci_set_command_bit(dev, child, PCIM_CMD_PORTEN); 610 break; 611 case SYS_RES_MEMORY: 612 pci_set_command_bit(dev, child, PCIM_CMD_MEMEN); 613 break; 614 } 615 } 616 617 static void 618 pci_disable_io_method(device_t dev, device_t child, int space) 619 { 620 switch(space) { 621 case SYS_RES_IOPORT: 622 pci_clear_command_bit(dev, child, PCIM_CMD_PORTEN); 623 break; 624 case SYS_RES_MEMORY: 625 pci_clear_command_bit(dev, child, PCIM_CMD_MEMEN); 626 break; 627 } 628 } 629 630 /* 631 * New style pci driver. Parent device is either a pci-host-bridge or a 632 * pci-pci-bridge. Both kinds are represented by instances of pcib. 633 */ 634 635 static void 636 pci_print_verbose(struct pci_devinfo *dinfo) 637 { 638 if (bootverbose) { 639 pcicfgregs *cfg = &dinfo->cfg; 640 641 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 642 cfg->vendor, cfg->device, cfg->revid); 643 printf("\tbus=%d, slot=%d, func=%d\n", 644 cfg->bus, cfg->slot, cfg->func); 645 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 646 cfg->baseclass, cfg->subclass, cfg->progif, 647 cfg->hdrtype, cfg->mfdev); 648 #ifdef PCI_DEBUG 649 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 650 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 651 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 652 cfg->lattimer, cfg->lattimer * 30, 653 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 654 #endif /* PCI_DEBUG */ 655 if (cfg->intpin > 0) 656 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 657 if (cfg->pp_cap) { 658 u_int16_t status; 659 660 status = pci_read_config(cfg->dev, cfg->pp_status, 2); 661 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 662 cfg->pp_cap & PCIM_PCAP_SPEC, 663 cfg->pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 664 cfg->pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 665 status & PCIM_PSTAT_DMASK); 666 } 667 } 668 } 669 670 static int 671 pci_porten(device_t pcib, int b, int s, int f) 672 { 673 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 674 & PCIM_CMD_PORTEN) != 0; 675 } 676 677 static int 678 pci_memen(device_t pcib, int b, int s, int f) 679 { 680 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 681 & PCIM_CMD_MEMEN) != 0; 682 } 683 684 /* 685 * Add a resource based on a pci map register. Return 1 if the map 686 * register is a 32bit map register or 2 if it is a 64bit register. 687 */ 688 static int 689 pci_add_map(device_t pcib, int b, int s, int f, int reg, 690 struct resource_list *rl) 691 { 692 u_int32_t map; 693 u_int64_t base; 694 u_int8_t ln2size; 695 u_int8_t ln2range; 696 u_int32_t testval; 697 #ifdef PCI_ENABLE_IO_MODES 698 u_int16_t cmd; 699 #endif 700 int type; 701 702 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 703 704 if (map == 0 || map == 0xffffffff) 705 return 1; /* skip invalid entry */ 706 707 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 708 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 709 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 710 711 base = pci_mapbase(map); 712 if (pci_maptype(map) & PCI_MAPMEM) 713 type = SYS_RES_MEMORY; 714 else 715 type = SYS_RES_IOPORT; 716 ln2size = pci_mapsize(testval); 717 ln2range = pci_maprange(testval); 718 if (ln2range == 64) { 719 /* Read the other half of a 64bit map register */ 720 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 721 } 722 723 if (bootverbose) { 724 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 725 reg, pci_maptype(map), ln2range, 726 (unsigned int) base, ln2size); 727 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 728 printf(", port disabled\n"); 729 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 730 printf(", memory disabled\n"); 731 else 732 printf(", enabled\n"); 733 } 734 735 /* 736 * This code theoretically does the right thing, but has 737 * undesirable side effects in some cases where 738 * peripherals respond oddly to having these bits 739 * enabled. Leave them alone by default. 740 */ 741 #ifdef PCI_ENABLE_IO_MODES 742 /* Turn on resources that have been left off by a lazy BIOS */ 743 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 744 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 745 cmd |= PCIM_CMD_PORTEN; 746 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 747 } 748 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 749 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 750 cmd |= PCIM_CMD_MEMEN; 751 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 752 } 753 #else 754 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 755 return 1; 756 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 757 return 1; 758 #endif 759 760 resource_list_add(rl, type, reg, 761 base, base + (1 << ln2size) - 1, 762 (1 << ln2size)); 763 764 return (ln2range == 64) ? 2 : 1; 765 } 766 767 static void 768 pci_add_resources(device_t pcib, int b, int s, int f, device_t dev) 769 { 770 struct pci_devinfo *dinfo = device_get_ivars(dev); 771 pcicfgregs *cfg = &dinfo->cfg; 772 struct resource_list *rl = &dinfo->resources; 773 struct pci_quirk *q; 774 int i; 775 776 for (i = 0; i < cfg->nummaps;) { 777 i += pci_add_map(pcib, b, s, f, PCIR_MAPS + i*4, rl); 778 } 779 780 for (q = &pci_quirks[0]; q->devid; q++) { 781 if (q->devid == ((cfg->device << 16) | cfg->vendor) 782 && q->type == PCI_QUIRK_MAP_REG) 783 pci_add_map(pcib, b, s, f, q->arg1, rl); 784 } 785 786 if (cfg->intpin > 0 && cfg->intline != 255) { 787 #ifdef __ia64__ 788 /* 789 * Re-route interrupts on ia64 so that we can get the 790 * I/O SAPIC interrupt numbers (the BIOS leaves legacy 791 * PIC interrupt numbers in the intline registers). 792 */ 793 cfg->intline = PCIB_ROUTE_INTERRUPT(pcib, 794 dev, 795 cfg->intpin); 796 #endif 797 resource_list_add(rl, SYS_RES_IRQ, 0, 798 cfg->intline, cfg->intline, 1); 799 } 800 } 801 802 static void 803 pci_add_children(device_t dev, int busno) 804 { 805 device_t pcib = device_get_parent(dev); 806 int maxslots; 807 int s, f; 808 809 maxslots = PCIB_MAXSLOTS(pcib); 810 811 for (s = 0; s <= maxslots; s++) { 812 int pcifunchigh = 0; 813 for (f = 0; f <= pcifunchigh; f++) { 814 struct pci_devinfo *dinfo = 815 pci_read_device(pcib, busno, s, f); 816 if (dinfo != NULL) { 817 if (dinfo->cfg.mfdev) 818 pcifunchigh = PCI_FUNCMAX; 819 820 dinfo->cfg.dev = device_add_child(dev, NULL, -1); 821 device_set_ivars(dinfo->cfg.dev, dinfo); 822 pci_add_resources(pcib, busno, s, f, 823 dinfo->cfg.dev); 824 pci_print_verbose(dinfo); 825 } 826 } 827 } 828 } 829 830 static int 831 pci_probe(device_t dev) 832 { 833 static int once, busno; 834 caddr_t vendordata, info; 835 836 device_set_desc(dev, "PCI bus"); 837 838 if (bootverbose) 839 device_printf(dev, "physical bus=%d\n", pcib_get_bus(dev)); 840 841 /* 842 * Since there can be multiple independantly numbered PCI 843 * busses on some large alpha systems, we can't use the unit 844 * number to decide what bus we are probing. We ask the parent 845 * pcib what our bus number is. 846 */ 847 busno = pcib_get_bus(dev); 848 if (busno < 0) 849 return ENXIO; 850 pci_add_children(dev, busno); 851 852 if (!once) { 853 make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, "pci"); 854 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 855 info = preload_search_info(vendordata, MODINFO_ADDR); 856 pci_vendordata = *(char **)info; 857 info = preload_search_info(vendordata, MODINFO_SIZE); 858 pci_vendordata_size = *(size_t *)info; 859 /* terminate the database */ 860 pci_vendordata[pci_vendordata_size] = '\n'; 861 } 862 once++; 863 } 864 865 return 0; 866 } 867 868 static int 869 pci_print_child(device_t dev, device_t child) 870 { 871 struct pci_devinfo *dinfo; 872 struct resource_list *rl; 873 pcicfgregs *cfg; 874 int retval = 0; 875 876 dinfo = device_get_ivars(child); 877 cfg = &dinfo->cfg; 878 rl = &dinfo->resources; 879 880 retval += bus_print_child_header(dev, child); 881 882 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 883 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 884 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 885 if (device_get_flags(dev)) 886 retval += printf(" flags %#x", device_get_flags(dev)); 887 888 retval += printf(" at device %d.%d", pci_get_slot(child), 889 pci_get_function(child)); 890 891 retval += bus_print_child_footer(dev, child); 892 893 return (retval); 894 } 895 896 static struct 897 { 898 int class; 899 int subclass; 900 char *desc; 901 } pci_nomatch_tab[] = { 902 {PCIC_OLD, -1, "old"}, 903 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 904 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 905 {PCIC_STORAGE, -1, "mass storage"}, 906 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 907 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 908 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 909 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 910 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 911 {PCIC_NETWORK, -1, "network"}, 912 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 913 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 914 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 915 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 916 {PCIC_DISPLAY, -1, "display"}, 917 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 918 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 919 {PCIC_MULTIMEDIA, -1, "multimedia"}, 920 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 921 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 922 {PCIC_MEMORY, -1, "memory"}, 923 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 924 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 925 {PCIC_BRIDGE, -1, "bridge"}, 926 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 927 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 928 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 929 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 930 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 931 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 932 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 933 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 934 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 935 {PCIC_SIMPLECOMM, -1, "simple comms"}, 936 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 937 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 938 {PCIC_BASEPERIPH, -1, "base peripheral"}, 939 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 940 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 941 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 942 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 943 {PCIC_INPUTDEV, -1, "input device"}, 944 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 945 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 946 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 947 {PCIC_DOCKING, -1, "docking station"}, 948 {PCIC_PROCESSOR, -1, "processor"}, 949 {PCIC_SERIALBUS, -1, "serial bus"}, 950 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 951 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 952 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 953 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 954 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 955 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 956 {0, 0, NULL} 957 }; 958 959 static void 960 pci_probe_nomatch(device_t dev, device_t child) 961 { 962 int i; 963 char *cp, *scp, *device; 964 965 /* 966 * Look for a listing for this device in a loaded device database. 967 */ 968 if ((device = pci_describe_device(child)) != NULL) { 969 device_printf(dev, "<%s>", device); 970 free(device, M_DEVBUF); 971 } else { 972 /* 973 * Scan the class/subclass descriptions for a general description. 974 */ 975 cp = "unknown"; 976 scp = NULL; 977 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 978 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 979 if (pci_nomatch_tab[i].subclass == -1) { 980 cp = pci_nomatch_tab[i].desc; 981 } else if (pci_nomatch_tab[i].subclass == pci_get_subclass(child)) { 982 scp = pci_nomatch_tab[i].desc; 983 } 984 } 985 } 986 device_printf(dev, "<%s%s%s>", 987 cp ? : "", 988 ((cp != NULL) && (scp != NULL)) ? ", " : "", 989 scp ? : ""); 990 } 991 printf(" at device %d.%d (no driver attached)\n", 992 pci_get_slot(child), 993 pci_get_function(child)); 994 return; 995 } 996 997 /* 998 * Parse the PCI device database, if loaded, and return a pointer to a 999 * description of the device. 1000 * 1001 * The database is flat text formatted as follows: 1002 * 1003 * Any line not in a valid format is ignored. 1004 * Lines are terminated with newline '\n' characters. 1005 * 1006 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1007 * the vendor name. 1008 * 1009 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1010 * - devices cannot be listed without a corresponding VENDOR line. 1011 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1012 * another TAB, then the device name. 1013 */ 1014 1015 /* 1016 * Assuming (ptr) points to the beginning of a line in the database, 1017 * return the vendor or device and description of the next entry. 1018 * The value of (vendor) or (device) inappropriate for the entry type 1019 * is set to -1. Returns nonzero at the end of the database. 1020 * 1021 * Note that this is slightly unrobust in the face of corrupt data; 1022 * we attempt to safeguard against this by spamming the end of the 1023 * database with a newline when we initialise. 1024 */ 1025 static int 1026 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1027 { 1028 char *cp = *ptr; 1029 int left; 1030 1031 *device = -1; 1032 *vendor = -1; 1033 **desc = '\0'; 1034 for (;;) { 1035 left = pci_vendordata_size - (cp - pci_vendordata); 1036 if (left <= 0) { 1037 *ptr = cp; 1038 return(1); 1039 } 1040 1041 /* vendor entry? */ 1042 if (*cp != '\t' && sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1043 break; 1044 /* device entry? */ 1045 if (*cp == '\t' && sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1046 break; 1047 1048 /* skip to next line */ 1049 while (*cp != '\n' && left > 0) { 1050 cp++; 1051 left--; 1052 } 1053 if (*cp == '\n') { 1054 cp++; 1055 left--; 1056 } 1057 } 1058 /* skip to next line */ 1059 while (*cp != '\n' && left > 0) { 1060 cp++; 1061 left--; 1062 } 1063 if (*cp == '\n' && left > 0) 1064 cp++; 1065 *ptr = cp; 1066 return(0); 1067 } 1068 1069 static char * 1070 pci_describe_device(device_t dev) 1071 { 1072 int vendor, device; 1073 char *desc, *vp, *dp, *line; 1074 1075 desc = vp = dp = NULL; 1076 1077 /* 1078 * If we have no vendor data, we can't do anything. 1079 */ 1080 if (pci_vendordata == NULL) 1081 goto out; 1082 1083 /* 1084 * Scan the vendor data looking for this device 1085 */ 1086 line = pci_vendordata; 1087 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1088 goto out; 1089 for (;;) { 1090 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1091 goto out; 1092 if (vendor == pci_get_vendor(dev)) 1093 break; 1094 } 1095 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1096 goto out; 1097 for (;;) { 1098 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1099 *dp = 0; 1100 break; 1101 } 1102 if (vendor != -1) { 1103 *dp = 0; 1104 break; 1105 } 1106 if (device == pci_get_device(dev)) 1107 break; 1108 } 1109 if (dp[0] == '\0') 1110 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1111 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != NULL) 1112 sprintf(desc, "%s, %s", vp, dp); 1113 out: 1114 if (vp != NULL) 1115 free(vp, M_DEVBUF); 1116 if (dp != NULL) 1117 free(dp, M_DEVBUF); 1118 return(desc); 1119 } 1120 1121 static int 1122 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1123 { 1124 struct pci_devinfo *dinfo; 1125 pcicfgregs *cfg; 1126 1127 dinfo = device_get_ivars(child); 1128 cfg = &dinfo->cfg; 1129 1130 switch (which) { 1131 case PCI_IVAR_SUBVENDOR: 1132 *result = cfg->subvendor; 1133 break; 1134 case PCI_IVAR_SUBDEVICE: 1135 *result = cfg->subdevice; 1136 break; 1137 case PCI_IVAR_VENDOR: 1138 *result = cfg->vendor; 1139 break; 1140 case PCI_IVAR_DEVICE: 1141 *result = cfg->device; 1142 break; 1143 case PCI_IVAR_DEVID: 1144 *result = (cfg->device << 16) | cfg->vendor; 1145 break; 1146 case PCI_IVAR_CLASS: 1147 *result = cfg->baseclass; 1148 break; 1149 case PCI_IVAR_SUBCLASS: 1150 *result = cfg->subclass; 1151 break; 1152 case PCI_IVAR_PROGIF: 1153 *result = cfg->progif; 1154 break; 1155 case PCI_IVAR_REVID: 1156 *result = cfg->revid; 1157 break; 1158 case PCI_IVAR_INTPIN: 1159 *result = cfg->intpin; 1160 break; 1161 case PCI_IVAR_IRQ: 1162 *result = cfg->intline; 1163 break; 1164 case PCI_IVAR_BUS: 1165 *result = cfg->bus; 1166 break; 1167 case PCI_IVAR_SLOT: 1168 *result = cfg->slot; 1169 break; 1170 case PCI_IVAR_FUNCTION: 1171 *result = cfg->func; 1172 break; 1173 default: 1174 return ENOENT; 1175 } 1176 return 0; 1177 } 1178 1179 static int 1180 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1181 { 1182 struct pci_devinfo *dinfo; 1183 pcicfgregs *cfg; 1184 1185 dinfo = device_get_ivars(child); 1186 cfg = &dinfo->cfg; 1187 1188 switch (which) { 1189 case PCI_IVAR_SUBVENDOR: 1190 case PCI_IVAR_SUBDEVICE: 1191 case PCI_IVAR_VENDOR: 1192 case PCI_IVAR_DEVICE: 1193 case PCI_IVAR_DEVID: 1194 case PCI_IVAR_CLASS: 1195 case PCI_IVAR_SUBCLASS: 1196 case PCI_IVAR_PROGIF: 1197 case PCI_IVAR_REVID: 1198 case PCI_IVAR_INTPIN: 1199 case PCI_IVAR_IRQ: 1200 case PCI_IVAR_BUS: 1201 case PCI_IVAR_SLOT: 1202 case PCI_IVAR_FUNCTION: 1203 return EINVAL; /* disallow for now */ 1204 1205 default: 1206 return ENOENT; 1207 } 1208 return 0; 1209 } 1210 1211 static struct resource * 1212 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1213 u_long start, u_long end, u_long count, u_int flags) 1214 { 1215 struct pci_devinfo *dinfo = device_get_ivars(child); 1216 struct resource_list *rl = &dinfo->resources; 1217 pcicfgregs *cfg = &dinfo->cfg; 1218 1219 /* 1220 * Perform lazy resource allocation 1221 * 1222 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY 1223 */ 1224 if (device_get_parent(child) == dev) { 1225 /* 1226 * If device doesn't have an interrupt routed, and is deserving of 1227 * an interrupt, try to assign it one. 1228 */ 1229 if ((type == SYS_RES_IRQ) && (cfg->intline == 255 || cfg->intline == 0) && (cfg->intpin != 0)) { 1230 cfg->intline = PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1231 cfg->intpin); 1232 if (cfg->intline != 255) { 1233 pci_write_config(child, PCIR_INTLINE, cfg->intline, 1); 1234 resource_list_add(rl, SYS_RES_IRQ, 0, 1235 cfg->intline, cfg->intline, 1); 1236 } 1237 } 1238 } 1239 1240 return resource_list_alloc(rl, dev, child, type, rid, 1241 start, end, count, flags); 1242 } 1243 1244 static void 1245 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1246 { 1247 printf("pci_delete_resource: PCI resources can not be deleted\n"); 1248 } 1249 1250 static struct resource_list * 1251 pci_get_resource_list (device_t dev, device_t child) 1252 { 1253 struct pci_devinfo * dinfo = device_get_ivars(child); 1254 struct resource_list * rl = &dinfo->resources; 1255 1256 if (!rl) 1257 return (NULL); 1258 1259 return (rl); 1260 } 1261 1262 static u_int32_t 1263 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1264 { 1265 struct pci_devinfo *dinfo = device_get_ivars(child); 1266 pcicfgregs *cfg = &dinfo->cfg; 1267 1268 return PCIB_READ_CONFIG(device_get_parent(dev), 1269 cfg->bus, cfg->slot, cfg->func, 1270 reg, width); 1271 } 1272 1273 static void 1274 pci_write_config_method(device_t dev, device_t child, int reg, 1275 u_int32_t val, int width) 1276 { 1277 struct pci_devinfo *dinfo = device_get_ivars(child); 1278 pcicfgregs *cfg = &dinfo->cfg; 1279 1280 PCIB_WRITE_CONFIG(device_get_parent(dev), 1281 cfg->bus, cfg->slot, cfg->func, 1282 reg, val, width); 1283 } 1284 1285 static int 1286 pci_modevent(module_t mod, int what, void *arg) 1287 { 1288 switch (what) { 1289 case MOD_LOAD: 1290 STAILQ_INIT(&pci_devq); 1291 pci_generation = 0; 1292 break; 1293 1294 case MOD_UNLOAD: 1295 break; 1296 } 1297 1298 return 0; 1299 } 1300