1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 5 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000, BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice unmodified, this list of conditions, and the following 14 * disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "opt_acpi.h" 35 #include "opt_bus.h" 36 37 #include <sys/param.h> 38 #include <sys/conf.h> 39 #include <sys/endian.h> 40 #include <sys/eventhandler.h> 41 #include <sys/fcntl.h> 42 #include <sys/kernel.h> 43 #include <sys/limits.h> 44 #include <sys/linker.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/queue.h> 48 #include <sys/sysctl.h> 49 #include <sys/systm.h> 50 51 #include <vm/vm.h> 52 #include <vm/pmap.h> 53 #include <vm/vm_extern.h> 54 55 #include <sys/bus.h> 56 #include <machine/bus.h> 57 #include <sys/rman.h> 58 #include <machine/resource.h> 59 #include <machine/stdarg.h> 60 61 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 62 #include <machine/intr_machdep.h> 63 #endif 64 65 #include <sys/pciio.h> 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pci_private.h> 69 70 #ifdef PCI_IOV 71 #include <sys/nv.h> 72 #include <dev/pci/pci_iov_private.h> 73 #endif 74 75 #include <dev/usb/controller/xhcireg.h> 76 #include <dev/usb/controller/ehcireg.h> 77 #include <dev/usb/controller/ohcireg.h> 78 #include <dev/usb/controller/uhcireg.h> 79 80 #include "pcib_if.h" 81 #include "pci_if.h" 82 83 #define PCIR_IS_BIOS(cfg, reg) \ 84 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ 85 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) 86 87 static int pci_has_quirk(uint32_t devid, int quirk); 88 static pci_addr_t pci_mapbase(uint64_t mapreg); 89 static const char *pci_maptype(uint64_t mapreg); 90 static int pci_maprange(uint64_t mapreg); 91 static pci_addr_t pci_rombase(uint64_t mapreg); 92 static int pci_romsize(uint64_t testval); 93 static void pci_fixancient(pcicfgregs *cfg); 94 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...); 95 96 static int pci_porten(device_t dev); 97 static int pci_memen(device_t dev); 98 static void pci_assign_interrupt(device_t bus, device_t dev, 99 int force_route); 100 static int pci_add_map(device_t bus, device_t dev, int reg, 101 struct resource_list *rl, int force, int prefetch); 102 static int pci_probe(device_t dev); 103 static int pci_attach(device_t dev); 104 static int pci_detach(device_t dev); 105 static void pci_load_vendor_data(void); 106 static int pci_describe_parse_line(char **ptr, int *vendor, 107 int *device, char **desc); 108 static char *pci_describe_device(device_t dev); 109 static int pci_modevent(module_t mod, int what, void *arg); 110 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 111 pcicfgregs *cfg); 112 static void pci_read_cap(device_t pcib, pcicfgregs *cfg); 113 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 114 int reg, uint32_t *data); 115 #if 0 116 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 117 int reg, uint32_t data); 118 #endif 119 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 120 static void pci_mask_msix(device_t dev, u_int index); 121 static void pci_unmask_msix(device_t dev, u_int index); 122 static int pci_msi_blacklisted(void); 123 static int pci_msix_blacklisted(void); 124 static void pci_resume_msi(device_t dev); 125 static void pci_resume_msix(device_t dev); 126 static int pci_remap_intr_method(device_t bus, device_t dev, 127 u_int irq); 128 static void pci_hint_device_unit(device_t acdev, device_t child, 129 const char *name, int *unitp); 130 static int pci_reset_post(device_t dev, device_t child); 131 static int pci_reset_prepare(device_t dev, device_t child); 132 static int pci_reset_child(device_t dev, device_t child, 133 int flags); 134 135 static int pci_get_id_method(device_t dev, device_t child, 136 enum pci_id_type type, uintptr_t *rid); 137 138 static struct pci_devinfo * pci_fill_devinfo(device_t pcib, device_t bus, int d, 139 int b, int s, int f, uint16_t vid, uint16_t did); 140 141 static device_method_t pci_methods[] = { 142 /* Device interface */ 143 DEVMETHOD(device_probe, pci_probe), 144 DEVMETHOD(device_attach, pci_attach), 145 DEVMETHOD(device_detach, pci_detach), 146 DEVMETHOD(device_shutdown, bus_generic_shutdown), 147 DEVMETHOD(device_suspend, bus_generic_suspend), 148 DEVMETHOD(device_resume, pci_resume), 149 150 /* Bus interface */ 151 DEVMETHOD(bus_print_child, pci_print_child), 152 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 153 DEVMETHOD(bus_read_ivar, pci_read_ivar), 154 DEVMETHOD(bus_write_ivar, pci_write_ivar), 155 DEVMETHOD(bus_driver_added, pci_driver_added), 156 DEVMETHOD(bus_setup_intr, pci_setup_intr), 157 DEVMETHOD(bus_teardown_intr, pci_teardown_intr), 158 DEVMETHOD(bus_reset_prepare, pci_reset_prepare), 159 DEVMETHOD(bus_reset_post, pci_reset_post), 160 DEVMETHOD(bus_reset_child, pci_reset_child), 161 162 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag), 163 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 164 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 165 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 166 DEVMETHOD(bus_delete_resource, pci_delete_resource), 167 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 168 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 169 DEVMETHOD(bus_release_resource, pci_release_resource), 170 DEVMETHOD(bus_activate_resource, pci_activate_resource), 171 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource), 172 DEVMETHOD(bus_child_deleted, pci_child_deleted), 173 DEVMETHOD(bus_child_detached, pci_child_detached), 174 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 175 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 176 DEVMETHOD(bus_hint_device_unit, pci_hint_device_unit), 177 DEVMETHOD(bus_remap_intr, pci_remap_intr_method), 178 DEVMETHOD(bus_suspend_child, pci_suspend_child), 179 DEVMETHOD(bus_resume_child, pci_resume_child), 180 DEVMETHOD(bus_rescan, pci_rescan_method), 181 182 /* PCI interface */ 183 DEVMETHOD(pci_read_config, pci_read_config_method), 184 DEVMETHOD(pci_write_config, pci_write_config_method), 185 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 186 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 187 DEVMETHOD(pci_enable_io, pci_enable_io_method), 188 DEVMETHOD(pci_disable_io, pci_disable_io_method), 189 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 190 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 191 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 192 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 193 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 194 DEVMETHOD(pci_find_cap, pci_find_cap_method), 195 DEVMETHOD(pci_find_next_cap, pci_find_next_cap_method), 196 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 197 DEVMETHOD(pci_find_next_extcap, pci_find_next_extcap_method), 198 DEVMETHOD(pci_find_htcap, pci_find_htcap_method), 199 DEVMETHOD(pci_find_next_htcap, pci_find_next_htcap_method), 200 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 201 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), 202 DEVMETHOD(pci_enable_msi, pci_enable_msi_method), 203 DEVMETHOD(pci_enable_msix, pci_enable_msix_method), 204 DEVMETHOD(pci_disable_msi, pci_disable_msi_method), 205 DEVMETHOD(pci_remap_msix, pci_remap_msix_method), 206 DEVMETHOD(pci_release_msi, pci_release_msi_method), 207 DEVMETHOD(pci_msi_count, pci_msi_count_method), 208 DEVMETHOD(pci_msix_count, pci_msix_count_method), 209 DEVMETHOD(pci_msix_pba_bar, pci_msix_pba_bar_method), 210 DEVMETHOD(pci_msix_table_bar, pci_msix_table_bar_method), 211 DEVMETHOD(pci_get_id, pci_get_id_method), 212 DEVMETHOD(pci_alloc_devinfo, pci_alloc_devinfo_method), 213 DEVMETHOD(pci_child_added, pci_child_added_method), 214 #ifdef PCI_IOV 215 DEVMETHOD(pci_iov_attach, pci_iov_attach_method), 216 DEVMETHOD(pci_iov_detach, pci_iov_detach_method), 217 DEVMETHOD(pci_create_iov_child, pci_create_iov_child_method), 218 #endif 219 220 DEVMETHOD_END 221 }; 222 223 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc)); 224 225 static devclass_t pci_devclass; 226 EARLY_DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL, 227 BUS_PASS_BUS); 228 MODULE_VERSION(pci, 1); 229 230 static char *pci_vendordata; 231 static size_t pci_vendordata_size; 232 233 struct pci_quirk { 234 uint32_t devid; /* Vendor/device of the card */ 235 int type; 236 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 237 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */ 238 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */ 239 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */ 240 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */ 241 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */ 242 #define PCI_QUIRK_REALLOC_BAR 7 /* Can't allocate memory at the default address */ 243 int arg1; 244 int arg2; 245 }; 246 247 static const struct pci_quirk pci_quirks[] = { 248 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */ 249 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 250 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 251 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 252 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 253 254 /* 255 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge 256 * or the CMIC-SL (AKA ServerWorks GC_LE). 257 */ 258 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 259 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 260 261 /* 262 * MSI doesn't work on earlier Intel chipsets including 263 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855. 264 */ 265 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 266 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 267 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 268 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 269 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 270 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 271 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 272 273 /* 274 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX 275 * bridge. 276 */ 277 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 278 279 /* 280 * MSI-X allocation doesn't work properly for devices passed through 281 * by VMware up to at least ESXi 5.1. 282 */ 283 { 0x079015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCI/PCI-X */ 284 { 0x07a015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCIe */ 285 286 /* 287 * Some virtualization environments emulate an older chipset 288 * but support MSI just fine. QEMU uses the Intel 82440. 289 */ 290 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 }, 291 292 /* 293 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus 294 * controller depending on SoftPciRst register (PM_IO 0x55 [7]). 295 * It prevents us from attaching hpet(4) when the bit is unset. 296 * Note this quirk only affects SB600 revision A13 and earlier. 297 * For SB600 A21 and later, firmware must set the bit to hide it. 298 * For SB700 and later, it is unused and hardcoded to zero. 299 */ 300 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 }, 301 302 /* 303 * Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have 304 * a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit 305 * of the command register is set. 306 */ 307 { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 308 { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 309 { 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 310 { 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 311 { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 312 313 /* 314 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't 315 * issue MSI interrupts with PCIM_CMD_INTxDIS set either. 316 */ 317 { 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */ 318 { 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */ 319 { 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */ 320 { 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */ 321 { 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */ 322 { 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */ 323 324 /* 325 * HPE Gen 10 VGA has a memory range that can't be allocated in the 326 * expected place. 327 */ 328 { 0x98741002, PCI_QUIRK_REALLOC_BAR, 0, 0 }, 329 330 { 0 } 331 }; 332 333 /* map register information */ 334 #define PCI_MAPMEM 0x01 /* memory map */ 335 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 336 #define PCI_MAPPORT 0x04 /* port map */ 337 338 struct devlist pci_devq; 339 uint32_t pci_generation; 340 uint32_t pci_numdevs = 0; 341 static int pcie_chipset, pcix_chipset; 342 343 /* sysctl vars */ 344 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 345 346 static int pci_enable_io_modes = 1; 347 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RWTUN, 348 &pci_enable_io_modes, 1, 349 "Enable I/O and memory bits in the config register. Some BIOSes do not" 350 " enable these bits correctly. We'd like to do this all the time, but" 351 " there are some peripherals that this causes problems with."); 352 353 static int pci_do_realloc_bars = 1; 354 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RWTUN, 355 &pci_do_realloc_bars, 0, 356 "Attempt to allocate a new range for any BARs whose original " 357 "firmware-assigned ranges fail to allocate during the initial device scan."); 358 359 static int pci_do_power_nodriver = 0; 360 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RWTUN, 361 &pci_do_power_nodriver, 0, 362 "Place a function into D3 state when no driver attaches to it. 0 means" 363 " disable. 1 means conservatively place devices into D3 state. 2 means" 364 " aggressively place devices into D3 state. 3 means put absolutely" 365 " everything in D3 state."); 366 367 int pci_do_power_resume = 1; 368 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RWTUN, 369 &pci_do_power_resume, 1, 370 "Transition from D3 -> D0 on resume."); 371 372 int pci_do_power_suspend = 1; 373 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RWTUN, 374 &pci_do_power_suspend, 1, 375 "Transition from D0 -> D3 on suspend."); 376 377 static int pci_do_msi = 1; 378 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RWTUN, &pci_do_msi, 1, 379 "Enable support for MSI interrupts"); 380 381 static int pci_do_msix = 1; 382 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RWTUN, &pci_do_msix, 1, 383 "Enable support for MSI-X interrupts"); 384 385 static int pci_msix_rewrite_table = 0; 386 SYSCTL_INT(_hw_pci, OID_AUTO, msix_rewrite_table, CTLFLAG_RWTUN, 387 &pci_msix_rewrite_table, 0, 388 "Rewrite entire MSI-X table when updating MSI-X entries"); 389 390 static int pci_honor_msi_blacklist = 1; 391 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RDTUN, 392 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X"); 393 394 #if defined(__i386__) || defined(__amd64__) 395 static int pci_usb_takeover = 1; 396 #else 397 static int pci_usb_takeover = 0; 398 #endif 399 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN, 400 &pci_usb_takeover, 1, 401 "Enable early takeover of USB controllers. Disable this if you depend on" 402 " BIOS emulation of USB devices, that is you use USB devices (like" 403 " keyboard or mouse) but do not load USB drivers"); 404 405 static int pci_clear_bars; 406 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0, 407 "Ignore firmware-assigned resources for BARs."); 408 409 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 410 static int pci_clear_buses; 411 SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0, 412 "Ignore firmware-assigned bus numbers."); 413 #endif 414 415 static int pci_enable_ari = 1; 416 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari, 417 0, "Enable support for PCIe Alternative RID Interpretation"); 418 419 static int pci_clear_aer_on_attach = 0; 420 SYSCTL_INT(_hw_pci, OID_AUTO, clear_aer_on_attach, CTLFLAG_RWTUN, 421 &pci_clear_aer_on_attach, 0, 422 "Clear port and device AER state on driver attach"); 423 424 static int 425 pci_has_quirk(uint32_t devid, int quirk) 426 { 427 const struct pci_quirk *q; 428 429 for (q = &pci_quirks[0]; q->devid; q++) { 430 if (q->devid == devid && q->type == quirk) 431 return (1); 432 } 433 return (0); 434 } 435 436 /* Find a device_t by bus/slot/function in domain 0 */ 437 438 device_t 439 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 440 { 441 442 return (pci_find_dbsf(0, bus, slot, func)); 443 } 444 445 /* Find a device_t by domain/bus/slot/function */ 446 447 device_t 448 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func) 449 { 450 struct pci_devinfo *dinfo; 451 452 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 453 if ((dinfo->cfg.domain == domain) && 454 (dinfo->cfg.bus == bus) && 455 (dinfo->cfg.slot == slot) && 456 (dinfo->cfg.func == func)) { 457 return (dinfo->cfg.dev); 458 } 459 } 460 461 return (NULL); 462 } 463 464 /* Find a device_t by vendor/device ID */ 465 466 device_t 467 pci_find_device(uint16_t vendor, uint16_t device) 468 { 469 struct pci_devinfo *dinfo; 470 471 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 472 if ((dinfo->cfg.vendor == vendor) && 473 (dinfo->cfg.device == device)) { 474 return (dinfo->cfg.dev); 475 } 476 } 477 478 return (NULL); 479 } 480 481 device_t 482 pci_find_class(uint8_t class, uint8_t subclass) 483 { 484 struct pci_devinfo *dinfo; 485 486 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 487 if (dinfo->cfg.baseclass == class && 488 dinfo->cfg.subclass == subclass) { 489 return (dinfo->cfg.dev); 490 } 491 } 492 493 return (NULL); 494 } 495 496 static int 497 pci_printf(pcicfgregs *cfg, const char *fmt, ...) 498 { 499 va_list ap; 500 int retval; 501 502 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, 503 cfg->func); 504 va_start(ap, fmt); 505 retval += vprintf(fmt, ap); 506 va_end(ap); 507 return (retval); 508 } 509 510 /* return base address of memory or port map */ 511 512 static pci_addr_t 513 pci_mapbase(uint64_t mapreg) 514 { 515 516 if (PCI_BAR_MEM(mapreg)) 517 return (mapreg & PCIM_BAR_MEM_BASE); 518 else 519 return (mapreg & PCIM_BAR_IO_BASE); 520 } 521 522 /* return map type of memory or port map */ 523 524 static const char * 525 pci_maptype(uint64_t mapreg) 526 { 527 528 if (PCI_BAR_IO(mapreg)) 529 return ("I/O Port"); 530 if (mapreg & PCIM_BAR_MEM_PREFETCH) 531 return ("Prefetchable Memory"); 532 return ("Memory"); 533 } 534 535 /* return log2 of map size decoded for memory or port map */ 536 537 int 538 pci_mapsize(uint64_t testval) 539 { 540 int ln2size; 541 542 testval = pci_mapbase(testval); 543 ln2size = 0; 544 if (testval != 0) { 545 while ((testval & 1) == 0) 546 { 547 ln2size++; 548 testval >>= 1; 549 } 550 } 551 return (ln2size); 552 } 553 554 /* return base address of device ROM */ 555 556 static pci_addr_t 557 pci_rombase(uint64_t mapreg) 558 { 559 560 return (mapreg & PCIM_BIOS_ADDR_MASK); 561 } 562 563 /* return log2 of map size decided for device ROM */ 564 565 static int 566 pci_romsize(uint64_t testval) 567 { 568 int ln2size; 569 570 testval = pci_rombase(testval); 571 ln2size = 0; 572 if (testval != 0) { 573 while ((testval & 1) == 0) 574 { 575 ln2size++; 576 testval >>= 1; 577 } 578 } 579 return (ln2size); 580 } 581 582 /* return log2 of address range supported by map register */ 583 584 static int 585 pci_maprange(uint64_t mapreg) 586 { 587 int ln2range = 0; 588 589 if (PCI_BAR_IO(mapreg)) 590 ln2range = 32; 591 else 592 switch (mapreg & PCIM_BAR_MEM_TYPE) { 593 case PCIM_BAR_MEM_32: 594 ln2range = 32; 595 break; 596 case PCIM_BAR_MEM_1MB: 597 ln2range = 20; 598 break; 599 case PCIM_BAR_MEM_64: 600 ln2range = 64; 601 break; 602 } 603 return (ln2range); 604 } 605 606 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 607 608 static void 609 pci_fixancient(pcicfgregs *cfg) 610 { 611 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 612 return; 613 614 /* PCI to PCI bridges use header type 1 */ 615 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 616 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; 617 } 618 619 /* extract header type specific config data */ 620 621 static void 622 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 623 { 624 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 625 switch (cfg->hdrtype & PCIM_HDRTYPE) { 626 case PCIM_HDRTYPE_NORMAL: 627 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 628 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 629 cfg->mingnt = REG(PCIR_MINGNT, 1); 630 cfg->maxlat = REG(PCIR_MAXLAT, 1); 631 cfg->nummaps = PCI_MAXMAPS_0; 632 break; 633 case PCIM_HDRTYPE_BRIDGE: 634 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1); 635 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1); 636 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1); 637 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1); 638 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2); 639 cfg->nummaps = PCI_MAXMAPS_1; 640 break; 641 case PCIM_HDRTYPE_CARDBUS: 642 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1); 643 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1); 644 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1); 645 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1); 646 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2); 647 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 648 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 649 cfg->nummaps = PCI_MAXMAPS_2; 650 break; 651 } 652 #undef REG 653 } 654 655 /* read configuration header into pcicfgregs structure */ 656 struct pci_devinfo * 657 pci_read_device(device_t pcib, device_t bus, int d, int b, int s, int f) 658 { 659 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 660 uint16_t vid, did; 661 662 vid = REG(PCIR_VENDOR, 2); 663 did = REG(PCIR_DEVICE, 2); 664 if (vid != 0xffff) 665 return (pci_fill_devinfo(pcib, bus, d, b, s, f, vid, did)); 666 667 return (NULL); 668 } 669 670 struct pci_devinfo * 671 pci_alloc_devinfo_method(device_t dev) 672 { 673 674 return (malloc(sizeof(struct pci_devinfo), M_DEVBUF, 675 M_WAITOK | M_ZERO)); 676 } 677 678 static struct pci_devinfo * 679 pci_fill_devinfo(device_t pcib, device_t bus, int d, int b, int s, int f, 680 uint16_t vid, uint16_t did) 681 { 682 struct pci_devinfo *devlist_entry; 683 pcicfgregs *cfg; 684 685 devlist_entry = PCI_ALLOC_DEVINFO(bus); 686 687 cfg = &devlist_entry->cfg; 688 689 cfg->domain = d; 690 cfg->bus = b; 691 cfg->slot = s; 692 cfg->func = f; 693 cfg->vendor = vid; 694 cfg->device = did; 695 cfg->cmdreg = REG(PCIR_COMMAND, 2); 696 cfg->statreg = REG(PCIR_STATUS, 2); 697 cfg->baseclass = REG(PCIR_CLASS, 1); 698 cfg->subclass = REG(PCIR_SUBCLASS, 1); 699 cfg->progif = REG(PCIR_PROGIF, 1); 700 cfg->revid = REG(PCIR_REVID, 1); 701 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 702 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 703 cfg->lattimer = REG(PCIR_LATTIMER, 1); 704 cfg->intpin = REG(PCIR_INTPIN, 1); 705 cfg->intline = REG(PCIR_INTLINE, 1); 706 707 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 708 cfg->hdrtype &= ~PCIM_MFDEV; 709 STAILQ_INIT(&cfg->maps); 710 711 cfg->iov = NULL; 712 713 pci_fixancient(cfg); 714 pci_hdrtypedata(pcib, b, s, f, cfg); 715 716 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 717 pci_read_cap(pcib, cfg); 718 719 STAILQ_INSERT_TAIL(&pci_devq, devlist_entry, pci_links); 720 721 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; 722 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 723 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 724 devlist_entry->conf.pc_sel.pc_func = cfg->func; 725 devlist_entry->conf.pc_hdr = cfg->hdrtype; 726 727 devlist_entry->conf.pc_subvendor = cfg->subvendor; 728 devlist_entry->conf.pc_subdevice = cfg->subdevice; 729 devlist_entry->conf.pc_vendor = cfg->vendor; 730 devlist_entry->conf.pc_device = cfg->device; 731 732 devlist_entry->conf.pc_class = cfg->baseclass; 733 devlist_entry->conf.pc_subclass = cfg->subclass; 734 devlist_entry->conf.pc_progif = cfg->progif; 735 devlist_entry->conf.pc_revid = cfg->revid; 736 737 pci_numdevs++; 738 pci_generation++; 739 740 return (devlist_entry); 741 } 742 #undef REG 743 744 static void 745 pci_ea_fill_info(device_t pcib, pcicfgregs *cfg) 746 { 747 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \ 748 cfg->ea.ea_location + (n), w) 749 int num_ent; 750 int ptr; 751 int a, b; 752 uint32_t val; 753 int ent_size; 754 uint32_t dw[4]; 755 uint64_t base, max_offset; 756 struct pci_ea_entry *eae; 757 758 if (cfg->ea.ea_location == 0) 759 return; 760 761 STAILQ_INIT(&cfg->ea.ea_entries); 762 763 /* Determine the number of entries */ 764 num_ent = REG(PCIR_EA_NUM_ENT, 2); 765 num_ent &= PCIM_EA_NUM_ENT_MASK; 766 767 /* Find the first entry to care of */ 768 ptr = PCIR_EA_FIRST_ENT; 769 770 /* Skip DWORD 2 for type 1 functions */ 771 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) 772 ptr += 4; 773 774 for (a = 0; a < num_ent; a++) { 775 776 eae = malloc(sizeof(*eae), M_DEVBUF, M_WAITOK | M_ZERO); 777 eae->eae_cfg_offset = cfg->ea.ea_location + ptr; 778 779 /* Read a number of dwords in the entry */ 780 val = REG(ptr, 4); 781 ptr += 4; 782 ent_size = (val & PCIM_EA_ES); 783 784 for (b = 0; b < ent_size; b++) { 785 dw[b] = REG(ptr, 4); 786 ptr += 4; 787 } 788 789 eae->eae_flags = val; 790 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 791 792 base = dw[0] & PCIM_EA_FIELD_MASK; 793 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 794 b = 2; 795 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 796 base |= (uint64_t)dw[b] << 32UL; 797 b++; 798 } 799 if (((dw[1] & PCIM_EA_IS_64) != 0) 800 && (b < ent_size)) { 801 max_offset |= (uint64_t)dw[b] << 32UL; 802 b++; 803 } 804 805 eae->eae_base = base; 806 eae->eae_max_offset = max_offset; 807 808 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link); 809 810 if (bootverbose) { 811 printf("PCI(EA) dev %04x:%04x, bei %d, flags #%x, base #%jx, max_offset #%jx\n", 812 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags, 813 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset); 814 } 815 } 816 } 817 #undef REG 818 819 static void 820 pci_read_cap(device_t pcib, pcicfgregs *cfg) 821 { 822 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 823 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 824 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 825 uint64_t addr; 826 #endif 827 uint32_t val; 828 int ptr, nextptr, ptrptr; 829 830 switch (cfg->hdrtype & PCIM_HDRTYPE) { 831 case PCIM_HDRTYPE_NORMAL: 832 case PCIM_HDRTYPE_BRIDGE: 833 ptrptr = PCIR_CAP_PTR; 834 break; 835 case PCIM_HDRTYPE_CARDBUS: 836 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 837 break; 838 default: 839 return; /* no extended capabilities support */ 840 } 841 nextptr = REG(ptrptr, 1); /* sanity check? */ 842 843 /* 844 * Read capability entries. 845 */ 846 while (nextptr != 0) { 847 /* Sanity check */ 848 if (nextptr > 255) { 849 printf("illegal PCI extended capability offset %d\n", 850 nextptr); 851 return; 852 } 853 /* Find the next entry */ 854 ptr = nextptr; 855 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 856 857 /* Process this entry */ 858 switch (REG(ptr + PCICAP_ID, 1)) { 859 case PCIY_PMG: /* PCI power management */ 860 if (cfg->pp.pp_cap == 0) { 861 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 862 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 863 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE; 864 if ((nextptr - ptr) > PCIR_POWER_DATA) 865 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 866 } 867 break; 868 case PCIY_HT: /* HyperTransport */ 869 /* Determine HT-specific capability type. */ 870 val = REG(ptr + PCIR_HT_COMMAND, 2); 871 872 if ((val & 0xe000) == PCIM_HTCAP_SLAVE) 873 cfg->ht.ht_slave = ptr; 874 875 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 876 switch (val & PCIM_HTCMD_CAP_MASK) { 877 case PCIM_HTCAP_MSI_MAPPING: 878 if (!(val & PCIM_HTCMD_MSI_FIXED)) { 879 /* Sanity check the mapping window. */ 880 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 881 4); 882 addr <<= 32; 883 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 884 4); 885 if (addr != MSI_INTEL_ADDR_BASE) 886 device_printf(pcib, 887 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", 888 cfg->domain, cfg->bus, 889 cfg->slot, cfg->func, 890 (long long)addr); 891 } else 892 addr = MSI_INTEL_ADDR_BASE; 893 894 cfg->ht.ht_msimap = ptr; 895 cfg->ht.ht_msictrl = val; 896 cfg->ht.ht_msiaddr = addr; 897 break; 898 } 899 #endif 900 break; 901 case PCIY_MSI: /* PCI MSI */ 902 cfg->msi.msi_location = ptr; 903 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 904 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 905 PCIM_MSICTRL_MMC_MASK)>>1); 906 break; 907 case PCIY_MSIX: /* PCI MSI-X */ 908 cfg->msix.msix_location = ptr; 909 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 910 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl & 911 PCIM_MSIXCTRL_TABLE_SIZE) + 1; 912 val = REG(ptr + PCIR_MSIX_TABLE, 4); 913 cfg->msix.msix_table_bar = PCIR_BAR(val & 914 PCIM_MSIX_BIR_MASK); 915 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 916 val = REG(ptr + PCIR_MSIX_PBA, 4); 917 cfg->msix.msix_pba_bar = PCIR_BAR(val & 918 PCIM_MSIX_BIR_MASK); 919 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 920 break; 921 case PCIY_VPD: /* PCI Vital Product Data */ 922 cfg->vpd.vpd_reg = ptr; 923 break; 924 case PCIY_SUBVENDOR: 925 /* Should always be true. */ 926 if ((cfg->hdrtype & PCIM_HDRTYPE) == 927 PCIM_HDRTYPE_BRIDGE) { 928 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4); 929 cfg->subvendor = val & 0xffff; 930 cfg->subdevice = val >> 16; 931 } 932 break; 933 case PCIY_PCIX: /* PCI-X */ 934 /* 935 * Assume we have a PCI-X chipset if we have 936 * at least one PCI-PCI bridge with a PCI-X 937 * capability. Note that some systems with 938 * PCI-express or HT chipsets might match on 939 * this check as well. 940 */ 941 if ((cfg->hdrtype & PCIM_HDRTYPE) == 942 PCIM_HDRTYPE_BRIDGE) 943 pcix_chipset = 1; 944 cfg->pcix.pcix_location = ptr; 945 break; 946 case PCIY_EXPRESS: /* PCI-express */ 947 /* 948 * Assume we have a PCI-express chipset if we have 949 * at least one PCI-express device. 950 */ 951 pcie_chipset = 1; 952 cfg->pcie.pcie_location = ptr; 953 val = REG(ptr + PCIER_FLAGS, 2); 954 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; 955 break; 956 case PCIY_EA: /* Enhanced Allocation */ 957 cfg->ea.ea_location = ptr; 958 pci_ea_fill_info(pcib, cfg); 959 break; 960 default: 961 break; 962 } 963 } 964 965 #if defined(__powerpc__) 966 /* 967 * Enable the MSI mapping window for all HyperTransport 968 * slaves. PCI-PCI bridges have their windows enabled via 969 * PCIB_MAP_MSI(). 970 */ 971 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && 972 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { 973 device_printf(pcib, 974 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n", 975 cfg->domain, cfg->bus, cfg->slot, cfg->func); 976 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 977 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, 978 2); 979 } 980 #endif 981 /* REG and WREG use carry through to next functions */ 982 } 983 984 /* 985 * PCI Vital Product Data 986 */ 987 988 #define PCI_VPD_TIMEOUT 1000000 989 990 static int 991 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data) 992 { 993 int count = PCI_VPD_TIMEOUT; 994 995 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 996 997 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); 998 999 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { 1000 if (--count < 0) 1001 return (ENXIO); 1002 DELAY(1); /* limit looping */ 1003 } 1004 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); 1005 1006 return (0); 1007 } 1008 1009 #if 0 1010 static int 1011 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 1012 { 1013 int count = PCI_VPD_TIMEOUT; 1014 1015 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1016 1017 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4); 1018 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2); 1019 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) { 1020 if (--count < 0) 1021 return (ENXIO); 1022 DELAY(1); /* limit looping */ 1023 } 1024 1025 return (0); 1026 } 1027 #endif 1028 1029 #undef PCI_VPD_TIMEOUT 1030 1031 struct vpd_readstate { 1032 device_t pcib; 1033 pcicfgregs *cfg; 1034 uint32_t val; 1035 int bytesinval; 1036 int off; 1037 uint8_t cksum; 1038 }; 1039 1040 static int 1041 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data) 1042 { 1043 uint32_t reg; 1044 uint8_t byte; 1045 1046 if (vrs->bytesinval == 0) { 1047 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) 1048 return (ENXIO); 1049 vrs->val = le32toh(reg); 1050 vrs->off += 4; 1051 byte = vrs->val & 0xff; 1052 vrs->bytesinval = 3; 1053 } else { 1054 vrs->val = vrs->val >> 8; 1055 byte = vrs->val & 0xff; 1056 vrs->bytesinval--; 1057 } 1058 1059 vrs->cksum += byte; 1060 *data = byte; 1061 return (0); 1062 } 1063 1064 static void 1065 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 1066 { 1067 struct vpd_readstate vrs; 1068 int state; 1069 int name; 1070 int remain; 1071 int i; 1072 int alloc, off; /* alloc/off for RO/W arrays */ 1073 int cksumvalid; 1074 int dflen; 1075 uint8_t byte; 1076 uint8_t byte2; 1077 1078 /* init vpd reader */ 1079 vrs.bytesinval = 0; 1080 vrs.off = 0; 1081 vrs.pcib = pcib; 1082 vrs.cfg = cfg; 1083 vrs.cksum = 0; 1084 1085 state = 0; 1086 name = remain = i = 0; /* shut up stupid gcc */ 1087 alloc = off = 0; /* shut up stupid gcc */ 1088 dflen = 0; /* shut up stupid gcc */ 1089 cksumvalid = -1; 1090 while (state >= 0) { 1091 if (vpd_nextbyte(&vrs, &byte)) { 1092 state = -2; 1093 break; 1094 } 1095 #if 0 1096 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \ 1097 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val, 1098 vrs.off, vrs.bytesinval, byte, state, remain, name, i); 1099 #endif 1100 switch (state) { 1101 case 0: /* item name */ 1102 if (byte & 0x80) { 1103 if (vpd_nextbyte(&vrs, &byte2)) { 1104 state = -2; 1105 break; 1106 } 1107 remain = byte2; 1108 if (vpd_nextbyte(&vrs, &byte2)) { 1109 state = -2; 1110 break; 1111 } 1112 remain |= byte2 << 8; 1113 if (remain > (0x7f*4 - vrs.off)) { 1114 state = -1; 1115 pci_printf(cfg, 1116 "invalid VPD data, remain %#x\n", 1117 remain); 1118 } 1119 name = byte & 0x7f; 1120 } else { 1121 remain = byte & 0x7; 1122 name = (byte >> 3) & 0xf; 1123 } 1124 switch (name) { 1125 case 0x2: /* String */ 1126 cfg->vpd.vpd_ident = malloc(remain + 1, 1127 M_DEVBUF, M_WAITOK); 1128 i = 0; 1129 state = 1; 1130 break; 1131 case 0xf: /* End */ 1132 state = -1; 1133 break; 1134 case 0x10: /* VPD-R */ 1135 alloc = 8; 1136 off = 0; 1137 cfg->vpd.vpd_ros = malloc(alloc * 1138 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF, 1139 M_WAITOK | M_ZERO); 1140 state = 2; 1141 break; 1142 case 0x11: /* VPD-W */ 1143 alloc = 8; 1144 off = 0; 1145 cfg->vpd.vpd_w = malloc(alloc * 1146 sizeof(*cfg->vpd.vpd_w), M_DEVBUF, 1147 M_WAITOK | M_ZERO); 1148 state = 5; 1149 break; 1150 default: /* Invalid data, abort */ 1151 state = -1; 1152 break; 1153 } 1154 break; 1155 1156 case 1: /* Identifier String */ 1157 cfg->vpd.vpd_ident[i++] = byte; 1158 remain--; 1159 if (remain == 0) { 1160 cfg->vpd.vpd_ident[i] = '\0'; 1161 state = 0; 1162 } 1163 break; 1164 1165 case 2: /* VPD-R Keyword Header */ 1166 if (off == alloc) { 1167 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1168 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros), 1169 M_DEVBUF, M_WAITOK | M_ZERO); 1170 } 1171 cfg->vpd.vpd_ros[off].keyword[0] = byte; 1172 if (vpd_nextbyte(&vrs, &byte2)) { 1173 state = -2; 1174 break; 1175 } 1176 cfg->vpd.vpd_ros[off].keyword[1] = byte2; 1177 if (vpd_nextbyte(&vrs, &byte2)) { 1178 state = -2; 1179 break; 1180 } 1181 cfg->vpd.vpd_ros[off].len = dflen = byte2; 1182 if (dflen == 0 && 1183 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV", 1184 2) == 0) { 1185 /* 1186 * if this happens, we can't trust the rest 1187 * of the VPD. 1188 */ 1189 pci_printf(cfg, "bad keyword length: %d\n", 1190 dflen); 1191 cksumvalid = 0; 1192 state = -1; 1193 break; 1194 } else if (dflen == 0) { 1195 cfg->vpd.vpd_ros[off].value = malloc(1 * 1196 sizeof(*cfg->vpd.vpd_ros[off].value), 1197 M_DEVBUF, M_WAITOK); 1198 cfg->vpd.vpd_ros[off].value[0] = '\x00'; 1199 } else 1200 cfg->vpd.vpd_ros[off].value = malloc( 1201 (dflen + 1) * 1202 sizeof(*cfg->vpd.vpd_ros[off].value), 1203 M_DEVBUF, M_WAITOK); 1204 remain -= 3; 1205 i = 0; 1206 /* keep in sync w/ state 3's transistions */ 1207 if (dflen == 0 && remain == 0) 1208 state = 0; 1209 else if (dflen == 0) 1210 state = 2; 1211 else 1212 state = 3; 1213 break; 1214 1215 case 3: /* VPD-R Keyword Value */ 1216 cfg->vpd.vpd_ros[off].value[i++] = byte; 1217 if (strncmp(cfg->vpd.vpd_ros[off].keyword, 1218 "RV", 2) == 0 && cksumvalid == -1) { 1219 if (vrs.cksum == 0) 1220 cksumvalid = 1; 1221 else { 1222 if (bootverbose) 1223 pci_printf(cfg, 1224 "bad VPD cksum, remain %hhu\n", 1225 vrs.cksum); 1226 cksumvalid = 0; 1227 state = -1; 1228 break; 1229 } 1230 } 1231 dflen--; 1232 remain--; 1233 /* keep in sync w/ state 2's transistions */ 1234 if (dflen == 0) 1235 cfg->vpd.vpd_ros[off++].value[i++] = '\0'; 1236 if (dflen == 0 && remain == 0) { 1237 cfg->vpd.vpd_rocnt = off; 1238 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1239 off * sizeof(*cfg->vpd.vpd_ros), 1240 M_DEVBUF, M_WAITOK | M_ZERO); 1241 state = 0; 1242 } else if (dflen == 0) 1243 state = 2; 1244 break; 1245 1246 case 4: 1247 remain--; 1248 if (remain == 0) 1249 state = 0; 1250 break; 1251 1252 case 5: /* VPD-W Keyword Header */ 1253 if (off == alloc) { 1254 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1255 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w), 1256 M_DEVBUF, M_WAITOK | M_ZERO); 1257 } 1258 cfg->vpd.vpd_w[off].keyword[0] = byte; 1259 if (vpd_nextbyte(&vrs, &byte2)) { 1260 state = -2; 1261 break; 1262 } 1263 cfg->vpd.vpd_w[off].keyword[1] = byte2; 1264 if (vpd_nextbyte(&vrs, &byte2)) { 1265 state = -2; 1266 break; 1267 } 1268 cfg->vpd.vpd_w[off].len = dflen = byte2; 1269 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval; 1270 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) * 1271 sizeof(*cfg->vpd.vpd_w[off].value), 1272 M_DEVBUF, M_WAITOK); 1273 remain -= 3; 1274 i = 0; 1275 /* keep in sync w/ state 6's transistions */ 1276 if (dflen == 0 && remain == 0) 1277 state = 0; 1278 else if (dflen == 0) 1279 state = 5; 1280 else 1281 state = 6; 1282 break; 1283 1284 case 6: /* VPD-W Keyword Value */ 1285 cfg->vpd.vpd_w[off].value[i++] = byte; 1286 dflen--; 1287 remain--; 1288 /* keep in sync w/ state 5's transistions */ 1289 if (dflen == 0) 1290 cfg->vpd.vpd_w[off++].value[i++] = '\0'; 1291 if (dflen == 0 && remain == 0) { 1292 cfg->vpd.vpd_wcnt = off; 1293 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1294 off * sizeof(*cfg->vpd.vpd_w), 1295 M_DEVBUF, M_WAITOK | M_ZERO); 1296 state = 0; 1297 } else if (dflen == 0) 1298 state = 5; 1299 break; 1300 1301 default: 1302 pci_printf(cfg, "invalid state: %d\n", state); 1303 state = -1; 1304 break; 1305 } 1306 } 1307 1308 if (cksumvalid == 0 || state < -1) { 1309 /* read-only data bad, clean up */ 1310 if (cfg->vpd.vpd_ros != NULL) { 1311 for (off = 0; cfg->vpd.vpd_ros[off].value; off++) 1312 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF); 1313 free(cfg->vpd.vpd_ros, M_DEVBUF); 1314 cfg->vpd.vpd_ros = NULL; 1315 } 1316 } 1317 if (state < -1) { 1318 /* I/O error, clean up */ 1319 pci_printf(cfg, "failed to read VPD data.\n"); 1320 if (cfg->vpd.vpd_ident != NULL) { 1321 free(cfg->vpd.vpd_ident, M_DEVBUF); 1322 cfg->vpd.vpd_ident = NULL; 1323 } 1324 if (cfg->vpd.vpd_w != NULL) { 1325 for (off = 0; cfg->vpd.vpd_w[off].value; off++) 1326 free(cfg->vpd.vpd_w[off].value, M_DEVBUF); 1327 free(cfg->vpd.vpd_w, M_DEVBUF); 1328 cfg->vpd.vpd_w = NULL; 1329 } 1330 } 1331 cfg->vpd.vpd_cached = 1; 1332 #undef REG 1333 #undef WREG 1334 } 1335 1336 int 1337 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 1338 { 1339 struct pci_devinfo *dinfo = device_get_ivars(child); 1340 pcicfgregs *cfg = &dinfo->cfg; 1341 1342 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1343 pci_read_vpd(device_get_parent(dev), cfg); 1344 1345 *identptr = cfg->vpd.vpd_ident; 1346 1347 if (*identptr == NULL) 1348 return (ENXIO); 1349 1350 return (0); 1351 } 1352 1353 int 1354 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 1355 const char **vptr) 1356 { 1357 struct pci_devinfo *dinfo = device_get_ivars(child); 1358 pcicfgregs *cfg = &dinfo->cfg; 1359 int i; 1360 1361 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1362 pci_read_vpd(device_get_parent(dev), cfg); 1363 1364 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 1365 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 1366 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { 1367 *vptr = cfg->vpd.vpd_ros[i].value; 1368 return (0); 1369 } 1370 1371 *vptr = NULL; 1372 return (ENXIO); 1373 } 1374 1375 struct pcicfg_vpd * 1376 pci_fetch_vpd_list(device_t dev) 1377 { 1378 struct pci_devinfo *dinfo = device_get_ivars(dev); 1379 pcicfgregs *cfg = &dinfo->cfg; 1380 1381 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1382 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg); 1383 return (&cfg->vpd); 1384 } 1385 1386 /* 1387 * Find the requested HyperTransport capability and return the offset 1388 * in configuration space via the pointer provided. The function 1389 * returns 0 on success and an error code otherwise. 1390 */ 1391 int 1392 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg) 1393 { 1394 int ptr, error; 1395 uint16_t val; 1396 1397 error = pci_find_cap(child, PCIY_HT, &ptr); 1398 if (error) 1399 return (error); 1400 1401 /* 1402 * Traverse the capabilities list checking each HT capability 1403 * to see if it matches the requested HT capability. 1404 */ 1405 for (;;) { 1406 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1407 if (capability == PCIM_HTCAP_SLAVE || 1408 capability == PCIM_HTCAP_HOST) 1409 val &= 0xe000; 1410 else 1411 val &= PCIM_HTCMD_CAP_MASK; 1412 if (val == capability) { 1413 if (capreg != NULL) 1414 *capreg = ptr; 1415 return (0); 1416 } 1417 1418 /* Skip to the next HT capability. */ 1419 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1420 break; 1421 } 1422 1423 return (ENOENT); 1424 } 1425 1426 /* 1427 * Find the next requested HyperTransport capability after start and return 1428 * the offset in configuration space via the pointer provided. The function 1429 * returns 0 on success and an error code otherwise. 1430 */ 1431 int 1432 pci_find_next_htcap_method(device_t dev, device_t child, int capability, 1433 int start, int *capreg) 1434 { 1435 int ptr; 1436 uint16_t val; 1437 1438 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == PCIY_HT, 1439 ("start capability is not HyperTransport capability")); 1440 ptr = start; 1441 1442 /* 1443 * Traverse the capabilities list checking each HT capability 1444 * to see if it matches the requested HT capability. 1445 */ 1446 for (;;) { 1447 /* Skip to the next HT capability. */ 1448 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1449 break; 1450 1451 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1452 if (capability == PCIM_HTCAP_SLAVE || 1453 capability == PCIM_HTCAP_HOST) 1454 val &= 0xe000; 1455 else 1456 val &= PCIM_HTCMD_CAP_MASK; 1457 if (val == capability) { 1458 if (capreg != NULL) 1459 *capreg = ptr; 1460 return (0); 1461 } 1462 } 1463 1464 return (ENOENT); 1465 } 1466 1467 /* 1468 * Find the requested capability and return the offset in 1469 * configuration space via the pointer provided. The function returns 1470 * 0 on success and an error code otherwise. 1471 */ 1472 int 1473 pci_find_cap_method(device_t dev, device_t child, int capability, 1474 int *capreg) 1475 { 1476 struct pci_devinfo *dinfo = device_get_ivars(child); 1477 pcicfgregs *cfg = &dinfo->cfg; 1478 uint32_t status; 1479 uint8_t ptr; 1480 1481 /* 1482 * Check the CAP_LIST bit of the PCI status register first. 1483 */ 1484 status = pci_read_config(child, PCIR_STATUS, 2); 1485 if (!(status & PCIM_STATUS_CAPPRESENT)) 1486 return (ENXIO); 1487 1488 /* 1489 * Determine the start pointer of the capabilities list. 1490 */ 1491 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1492 case PCIM_HDRTYPE_NORMAL: 1493 case PCIM_HDRTYPE_BRIDGE: 1494 ptr = PCIR_CAP_PTR; 1495 break; 1496 case PCIM_HDRTYPE_CARDBUS: 1497 ptr = PCIR_CAP_PTR_2; 1498 break; 1499 default: 1500 /* XXX: panic? */ 1501 return (ENXIO); /* no extended capabilities support */ 1502 } 1503 ptr = pci_read_config(child, ptr, 1); 1504 1505 /* 1506 * Traverse the capabilities list. 1507 */ 1508 while (ptr != 0) { 1509 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1510 if (capreg != NULL) 1511 *capreg = ptr; 1512 return (0); 1513 } 1514 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1515 } 1516 1517 return (ENOENT); 1518 } 1519 1520 /* 1521 * Find the next requested capability after start and return the offset in 1522 * configuration space via the pointer provided. The function returns 1523 * 0 on success and an error code otherwise. 1524 */ 1525 int 1526 pci_find_next_cap_method(device_t dev, device_t child, int capability, 1527 int start, int *capreg) 1528 { 1529 uint8_t ptr; 1530 1531 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == capability, 1532 ("start capability is not expected capability")); 1533 1534 ptr = pci_read_config(child, start + PCICAP_NEXTPTR, 1); 1535 while (ptr != 0) { 1536 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1537 if (capreg != NULL) 1538 *capreg = ptr; 1539 return (0); 1540 } 1541 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1542 } 1543 1544 return (ENOENT); 1545 } 1546 1547 /* 1548 * Find the requested extended capability and return the offset in 1549 * configuration space via the pointer provided. The function returns 1550 * 0 on success and an error code otherwise. 1551 */ 1552 int 1553 pci_find_extcap_method(device_t dev, device_t child, int capability, 1554 int *capreg) 1555 { 1556 struct pci_devinfo *dinfo = device_get_ivars(child); 1557 pcicfgregs *cfg = &dinfo->cfg; 1558 uint32_t ecap; 1559 uint16_t ptr; 1560 1561 /* Only supported for PCI-express devices. */ 1562 if (cfg->pcie.pcie_location == 0) 1563 return (ENXIO); 1564 1565 ptr = PCIR_EXTCAP; 1566 ecap = pci_read_config(child, ptr, 4); 1567 if (ecap == 0xffffffff || ecap == 0) 1568 return (ENOENT); 1569 for (;;) { 1570 if (PCI_EXTCAP_ID(ecap) == capability) { 1571 if (capreg != NULL) 1572 *capreg = ptr; 1573 return (0); 1574 } 1575 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1576 if (ptr == 0) 1577 break; 1578 ecap = pci_read_config(child, ptr, 4); 1579 } 1580 1581 return (ENOENT); 1582 } 1583 1584 /* 1585 * Find the next requested extended capability after start and return the 1586 * offset in configuration space via the pointer provided. The function 1587 * returns 0 on success and an error code otherwise. 1588 */ 1589 int 1590 pci_find_next_extcap_method(device_t dev, device_t child, int capability, 1591 int start, int *capreg) 1592 { 1593 struct pci_devinfo *dinfo = device_get_ivars(child); 1594 pcicfgregs *cfg = &dinfo->cfg; 1595 uint32_t ecap; 1596 uint16_t ptr; 1597 1598 /* Only supported for PCI-express devices. */ 1599 if (cfg->pcie.pcie_location == 0) 1600 return (ENXIO); 1601 1602 ecap = pci_read_config(child, start, 4); 1603 KASSERT(PCI_EXTCAP_ID(ecap) == capability, 1604 ("start extended capability is not expected capability")); 1605 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1606 while (ptr != 0) { 1607 ecap = pci_read_config(child, ptr, 4); 1608 if (PCI_EXTCAP_ID(ecap) == capability) { 1609 if (capreg != NULL) 1610 *capreg = ptr; 1611 return (0); 1612 } 1613 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1614 } 1615 1616 return (ENOENT); 1617 } 1618 1619 /* 1620 * Support for MSI-X message interrupts. 1621 */ 1622 static void 1623 pci_write_msix_entry(device_t dev, u_int index, uint64_t address, uint32_t data) 1624 { 1625 struct pci_devinfo *dinfo = device_get_ivars(dev); 1626 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1627 uint32_t offset; 1628 1629 KASSERT(msix->msix_table_len > index, ("bogus index")); 1630 offset = msix->msix_table_offset + index * 16; 1631 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); 1632 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); 1633 bus_write_4(msix->msix_table_res, offset + 8, data); 1634 } 1635 1636 void 1637 pci_enable_msix_method(device_t dev, device_t child, u_int index, 1638 uint64_t address, uint32_t data) 1639 { 1640 1641 if (pci_msix_rewrite_table) { 1642 struct pci_devinfo *dinfo = device_get_ivars(child); 1643 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1644 1645 /* 1646 * Some VM hosts require MSIX to be disabled in the 1647 * control register before updating the MSIX table 1648 * entries are allowed. It is not enough to only 1649 * disable MSIX while updating a single entry. MSIX 1650 * must be disabled while updating all entries in the 1651 * table. 1652 */ 1653 pci_write_config(child, 1654 msix->msix_location + PCIR_MSIX_CTRL, 1655 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2); 1656 pci_resume_msix(child); 1657 } else 1658 pci_write_msix_entry(child, index, address, data); 1659 1660 /* Enable MSI -> HT mapping. */ 1661 pci_ht_map_msi(child, address); 1662 } 1663 1664 void 1665 pci_mask_msix(device_t dev, u_int index) 1666 { 1667 struct pci_devinfo *dinfo = device_get_ivars(dev); 1668 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1669 uint32_t offset, val; 1670 1671 KASSERT(msix->msix_msgnum > index, ("bogus index")); 1672 offset = msix->msix_table_offset + index * 16 + 12; 1673 val = bus_read_4(msix->msix_table_res, offset); 1674 val |= PCIM_MSIX_VCTRL_MASK; 1675 1676 /* 1677 * Some devices (e.g. Samsung PM961) do not support reads of this 1678 * register, so always write the new value. 1679 */ 1680 bus_write_4(msix->msix_table_res, offset, val); 1681 } 1682 1683 void 1684 pci_unmask_msix(device_t dev, u_int index) 1685 { 1686 struct pci_devinfo *dinfo = device_get_ivars(dev); 1687 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1688 uint32_t offset, val; 1689 1690 KASSERT(msix->msix_table_len > index, ("bogus index")); 1691 offset = msix->msix_table_offset + index * 16 + 12; 1692 val = bus_read_4(msix->msix_table_res, offset); 1693 val &= ~PCIM_MSIX_VCTRL_MASK; 1694 1695 /* 1696 * Some devices (e.g. Samsung PM961) do not support reads of this 1697 * register, so always write the new value. 1698 */ 1699 bus_write_4(msix->msix_table_res, offset, val); 1700 } 1701 1702 int 1703 pci_pending_msix(device_t dev, u_int index) 1704 { 1705 struct pci_devinfo *dinfo = device_get_ivars(dev); 1706 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1707 uint32_t offset, bit; 1708 1709 KASSERT(msix->msix_table_len > index, ("bogus index")); 1710 offset = msix->msix_pba_offset + (index / 32) * 4; 1711 bit = 1 << index % 32; 1712 return (bus_read_4(msix->msix_pba_res, offset) & bit); 1713 } 1714 1715 /* 1716 * Restore MSI-X registers and table during resume. If MSI-X is 1717 * enabled then walk the virtual table to restore the actual MSI-X 1718 * table. 1719 */ 1720 static void 1721 pci_resume_msix(device_t dev) 1722 { 1723 struct pci_devinfo *dinfo = device_get_ivars(dev); 1724 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1725 struct msix_table_entry *mte; 1726 struct msix_vector *mv; 1727 int i; 1728 1729 if (msix->msix_alloc > 0) { 1730 /* First, mask all vectors. */ 1731 for (i = 0; i < msix->msix_msgnum; i++) 1732 pci_mask_msix(dev, i); 1733 1734 /* Second, program any messages with at least one handler. */ 1735 for (i = 0; i < msix->msix_table_len; i++) { 1736 mte = &msix->msix_table[i]; 1737 if (mte->mte_vector == 0 || mte->mte_handlers == 0) 1738 continue; 1739 mv = &msix->msix_vectors[mte->mte_vector - 1]; 1740 pci_write_msix_entry(dev, i, mv->mv_address, 1741 mv->mv_data); 1742 pci_unmask_msix(dev, i); 1743 } 1744 } 1745 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, 1746 msix->msix_ctrl, 2); 1747 } 1748 1749 /* 1750 * Attempt to allocate *count MSI-X messages. The actual number allocated is 1751 * returned in *count. After this function returns, each message will be 1752 * available to the driver as SYS_RES_IRQ resources starting at rid 1. 1753 */ 1754 int 1755 pci_alloc_msix_method(device_t dev, device_t child, int *count) 1756 { 1757 struct pci_devinfo *dinfo = device_get_ivars(child); 1758 pcicfgregs *cfg = &dinfo->cfg; 1759 struct resource_list_entry *rle; 1760 int actual, error, i, irq, max; 1761 1762 /* Don't let count == 0 get us into trouble. */ 1763 if (*count == 0) 1764 return (EINVAL); 1765 1766 /* If rid 0 is allocated, then fail. */ 1767 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1768 if (rle != NULL && rle->res != NULL) 1769 return (ENXIO); 1770 1771 /* Already have allocated messages? */ 1772 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1773 return (ENXIO); 1774 1775 /* If MSI-X is blacklisted for this system, fail. */ 1776 if (pci_msix_blacklisted()) 1777 return (ENXIO); 1778 1779 /* MSI-X capability present? */ 1780 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1781 return (ENODEV); 1782 1783 /* Make sure the appropriate BARs are mapped. */ 1784 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1785 cfg->msix.msix_table_bar); 1786 if (rle == NULL || rle->res == NULL || 1787 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1788 return (ENXIO); 1789 cfg->msix.msix_table_res = rle->res; 1790 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1791 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1792 cfg->msix.msix_pba_bar); 1793 if (rle == NULL || rle->res == NULL || 1794 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1795 return (ENXIO); 1796 } 1797 cfg->msix.msix_pba_res = rle->res; 1798 1799 if (bootverbose) 1800 device_printf(child, 1801 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1802 *count, cfg->msix.msix_msgnum); 1803 max = min(*count, cfg->msix.msix_msgnum); 1804 for (i = 0; i < max; i++) { 1805 /* Allocate a message. */ 1806 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq); 1807 if (error) { 1808 if (i == 0) 1809 return (error); 1810 break; 1811 } 1812 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1813 irq, 1); 1814 } 1815 actual = i; 1816 1817 if (bootverbose) { 1818 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1819 if (actual == 1) 1820 device_printf(child, "using IRQ %ju for MSI-X\n", 1821 rle->start); 1822 else { 1823 int run; 1824 1825 /* 1826 * Be fancy and try to print contiguous runs of 1827 * IRQ values as ranges. 'irq' is the previous IRQ. 1828 * 'run' is true if we are in a range. 1829 */ 1830 device_printf(child, "using IRQs %ju", rle->start); 1831 irq = rle->start; 1832 run = 0; 1833 for (i = 1; i < actual; i++) { 1834 rle = resource_list_find(&dinfo->resources, 1835 SYS_RES_IRQ, i + 1); 1836 1837 /* Still in a run? */ 1838 if (rle->start == irq + 1) { 1839 run = 1; 1840 irq++; 1841 continue; 1842 } 1843 1844 /* Finish previous range. */ 1845 if (run) { 1846 printf("-%d", irq); 1847 run = 0; 1848 } 1849 1850 /* Start new range. */ 1851 printf(",%ju", rle->start); 1852 irq = rle->start; 1853 } 1854 1855 /* Unfinished range? */ 1856 if (run) 1857 printf("-%d", irq); 1858 printf(" for MSI-X\n"); 1859 } 1860 } 1861 1862 /* Mask all vectors. */ 1863 for (i = 0; i < cfg->msix.msix_msgnum; i++) 1864 pci_mask_msix(child, i); 1865 1866 /* Allocate and initialize vector data and virtual table. */ 1867 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual, 1868 M_DEVBUF, M_WAITOK | M_ZERO); 1869 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual, 1870 M_DEVBUF, M_WAITOK | M_ZERO); 1871 for (i = 0; i < actual; i++) { 1872 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1873 cfg->msix.msix_vectors[i].mv_irq = rle->start; 1874 cfg->msix.msix_table[i].mte_vector = i + 1; 1875 } 1876 1877 /* Update control register to enable MSI-X. */ 1878 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1879 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1880 cfg->msix.msix_ctrl, 2); 1881 1882 /* Update counts of alloc'd messages. */ 1883 cfg->msix.msix_alloc = actual; 1884 cfg->msix.msix_table_len = actual; 1885 *count = actual; 1886 return (0); 1887 } 1888 1889 /* 1890 * By default, pci_alloc_msix() will assign the allocated IRQ 1891 * resources consecutively to the first N messages in the MSI-X table. 1892 * However, device drivers may want to use different layouts if they 1893 * either receive fewer messages than they asked for, or they wish to 1894 * populate the MSI-X table sparsely. This method allows the driver 1895 * to specify what layout it wants. It must be called after a 1896 * successful pci_alloc_msix() but before any of the associated 1897 * SYS_RES_IRQ resources are allocated via bus_alloc_resource(). 1898 * 1899 * The 'vectors' array contains 'count' message vectors. The array 1900 * maps directly to the MSI-X table in that index 0 in the array 1901 * specifies the vector for the first message in the MSI-X table, etc. 1902 * The vector value in each array index can either be 0 to indicate 1903 * that no vector should be assigned to a message slot, or it can be a 1904 * number from 1 to N (where N is the count returned from a 1905 * succcessful call to pci_alloc_msix()) to indicate which message 1906 * vector (IRQ) to be used for the corresponding message. 1907 * 1908 * On successful return, each message with a non-zero vector will have 1909 * an associated SYS_RES_IRQ whose rid is equal to the array index + 1910 * 1. Additionally, if any of the IRQs allocated via the previous 1911 * call to pci_alloc_msix() are not used in the mapping, those IRQs 1912 * will be freed back to the system automatically. 1913 * 1914 * For example, suppose a driver has a MSI-X table with 6 messages and 1915 * asks for 6 messages, but pci_alloc_msix() only returns a count of 1916 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and 1917 * C. After the call to pci_alloc_msix(), the device will be setup to 1918 * have an MSI-X table of ABC--- (where - means no vector assigned). 1919 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 }, 1920 * then the MSI-X table will look like A-AB-B, and the 'C' vector will 1921 * be freed back to the system. This device will also have valid 1922 * SYS_RES_IRQ rids of 1, 3, 4, and 6. 1923 * 1924 * In any case, the SYS_RES_IRQ rid X will always map to the message 1925 * at MSI-X table index X - 1 and will only be valid if a vector is 1926 * assigned to that table entry. 1927 */ 1928 int 1929 pci_remap_msix_method(device_t dev, device_t child, int count, 1930 const u_int *vectors) 1931 { 1932 struct pci_devinfo *dinfo = device_get_ivars(child); 1933 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1934 struct resource_list_entry *rle; 1935 int i, irq, j, *used; 1936 1937 /* 1938 * Have to have at least one message in the table but the 1939 * table can't be bigger than the actual MSI-X table in the 1940 * device. 1941 */ 1942 if (count == 0 || count > msix->msix_msgnum) 1943 return (EINVAL); 1944 1945 /* Sanity check the vectors. */ 1946 for (i = 0; i < count; i++) 1947 if (vectors[i] > msix->msix_alloc) 1948 return (EINVAL); 1949 1950 /* 1951 * Make sure there aren't any holes in the vectors to be used. 1952 * It's a big pain to support it, and it doesn't really make 1953 * sense anyway. Also, at least one vector must be used. 1954 */ 1955 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK | 1956 M_ZERO); 1957 for (i = 0; i < count; i++) 1958 if (vectors[i] != 0) 1959 used[vectors[i] - 1] = 1; 1960 for (i = 0; i < msix->msix_alloc - 1; i++) 1961 if (used[i] == 0 && used[i + 1] == 1) { 1962 free(used, M_DEVBUF); 1963 return (EINVAL); 1964 } 1965 if (used[0] != 1) { 1966 free(used, M_DEVBUF); 1967 return (EINVAL); 1968 } 1969 1970 /* Make sure none of the resources are allocated. */ 1971 for (i = 0; i < msix->msix_table_len; i++) { 1972 if (msix->msix_table[i].mte_vector == 0) 1973 continue; 1974 if (msix->msix_table[i].mte_handlers > 0) { 1975 free(used, M_DEVBUF); 1976 return (EBUSY); 1977 } 1978 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1979 KASSERT(rle != NULL, ("missing resource")); 1980 if (rle->res != NULL) { 1981 free(used, M_DEVBUF); 1982 return (EBUSY); 1983 } 1984 } 1985 1986 /* Free the existing resource list entries. */ 1987 for (i = 0; i < msix->msix_table_len; i++) { 1988 if (msix->msix_table[i].mte_vector == 0) 1989 continue; 1990 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1991 } 1992 1993 /* 1994 * Build the new virtual table keeping track of which vectors are 1995 * used. 1996 */ 1997 free(msix->msix_table, M_DEVBUF); 1998 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count, 1999 M_DEVBUF, M_WAITOK | M_ZERO); 2000 for (i = 0; i < count; i++) 2001 msix->msix_table[i].mte_vector = vectors[i]; 2002 msix->msix_table_len = count; 2003 2004 /* Free any unused IRQs and resize the vectors array if necessary. */ 2005 j = msix->msix_alloc - 1; 2006 if (used[j] == 0) { 2007 struct msix_vector *vec; 2008 2009 while (used[j] == 0) { 2010 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2011 msix->msix_vectors[j].mv_irq); 2012 j--; 2013 } 2014 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF, 2015 M_WAITOK); 2016 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * 2017 (j + 1)); 2018 free(msix->msix_vectors, M_DEVBUF); 2019 msix->msix_vectors = vec; 2020 msix->msix_alloc = j + 1; 2021 } 2022 free(used, M_DEVBUF); 2023 2024 /* Map the IRQs onto the rids. */ 2025 for (i = 0; i < count; i++) { 2026 if (vectors[i] == 0) 2027 continue; 2028 irq = msix->msix_vectors[vectors[i] - 1].mv_irq; 2029 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 2030 irq, 1); 2031 } 2032 2033 if (bootverbose) { 2034 device_printf(child, "Remapped MSI-X IRQs as: "); 2035 for (i = 0; i < count; i++) { 2036 if (i != 0) 2037 printf(", "); 2038 if (vectors[i] == 0) 2039 printf("---"); 2040 else 2041 printf("%d", 2042 msix->msix_vectors[vectors[i] - 1].mv_irq); 2043 } 2044 printf("\n"); 2045 } 2046 2047 return (0); 2048 } 2049 2050 static int 2051 pci_release_msix(device_t dev, device_t child) 2052 { 2053 struct pci_devinfo *dinfo = device_get_ivars(child); 2054 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2055 struct resource_list_entry *rle; 2056 int i; 2057 2058 /* Do we have any messages to release? */ 2059 if (msix->msix_alloc == 0) 2060 return (ENODEV); 2061 2062 /* Make sure none of the resources are allocated. */ 2063 for (i = 0; i < msix->msix_table_len; i++) { 2064 if (msix->msix_table[i].mte_vector == 0) 2065 continue; 2066 if (msix->msix_table[i].mte_handlers > 0) 2067 return (EBUSY); 2068 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2069 KASSERT(rle != NULL, ("missing resource")); 2070 if (rle->res != NULL) 2071 return (EBUSY); 2072 } 2073 2074 /* Update control register to disable MSI-X. */ 2075 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 2076 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, 2077 msix->msix_ctrl, 2); 2078 2079 /* Free the resource list entries. */ 2080 for (i = 0; i < msix->msix_table_len; i++) { 2081 if (msix->msix_table[i].mte_vector == 0) 2082 continue; 2083 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2084 } 2085 free(msix->msix_table, M_DEVBUF); 2086 msix->msix_table_len = 0; 2087 2088 /* Release the IRQs. */ 2089 for (i = 0; i < msix->msix_alloc; i++) 2090 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2091 msix->msix_vectors[i].mv_irq); 2092 free(msix->msix_vectors, M_DEVBUF); 2093 msix->msix_alloc = 0; 2094 return (0); 2095 } 2096 2097 /* 2098 * Return the max supported MSI-X messages this device supports. 2099 * Basically, assuming the MD code can alloc messages, this function 2100 * should return the maximum value that pci_alloc_msix() can return. 2101 * Thus, it is subject to the tunables, etc. 2102 */ 2103 int 2104 pci_msix_count_method(device_t dev, device_t child) 2105 { 2106 struct pci_devinfo *dinfo = device_get_ivars(child); 2107 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2108 2109 if (pci_do_msix && msix->msix_location != 0) 2110 return (msix->msix_msgnum); 2111 return (0); 2112 } 2113 2114 int 2115 pci_msix_pba_bar_method(device_t dev, device_t child) 2116 { 2117 struct pci_devinfo *dinfo = device_get_ivars(child); 2118 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2119 2120 if (pci_do_msix && msix->msix_location != 0) 2121 return (msix->msix_pba_bar); 2122 return (-1); 2123 } 2124 2125 int 2126 pci_msix_table_bar_method(device_t dev, device_t child) 2127 { 2128 struct pci_devinfo *dinfo = device_get_ivars(child); 2129 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2130 2131 if (pci_do_msix && msix->msix_location != 0) 2132 return (msix->msix_table_bar); 2133 return (-1); 2134 } 2135 2136 /* 2137 * HyperTransport MSI mapping control 2138 */ 2139 void 2140 pci_ht_map_msi(device_t dev, uint64_t addr) 2141 { 2142 struct pci_devinfo *dinfo = device_get_ivars(dev); 2143 struct pcicfg_ht *ht = &dinfo->cfg.ht; 2144 2145 if (!ht->ht_msimap) 2146 return; 2147 2148 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && 2149 ht->ht_msiaddr >> 20 == addr >> 20) { 2150 /* Enable MSI -> HT mapping. */ 2151 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 2152 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2153 ht->ht_msictrl, 2); 2154 } 2155 2156 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { 2157 /* Disable MSI -> HT mapping. */ 2158 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; 2159 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2160 ht->ht_msictrl, 2); 2161 } 2162 } 2163 2164 int 2165 pci_get_max_payload(device_t dev) 2166 { 2167 struct pci_devinfo *dinfo = device_get_ivars(dev); 2168 int cap; 2169 uint16_t val; 2170 2171 cap = dinfo->cfg.pcie.pcie_location; 2172 if (cap == 0) 2173 return (0); 2174 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2175 val &= PCIEM_CTL_MAX_PAYLOAD; 2176 val >>= 5; 2177 return (1 << (val + 7)); 2178 } 2179 2180 int 2181 pci_get_max_read_req(device_t dev) 2182 { 2183 struct pci_devinfo *dinfo = device_get_ivars(dev); 2184 int cap; 2185 uint16_t val; 2186 2187 cap = dinfo->cfg.pcie.pcie_location; 2188 if (cap == 0) 2189 return (0); 2190 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2191 val &= PCIEM_CTL_MAX_READ_REQUEST; 2192 val >>= 12; 2193 return (1 << (val + 7)); 2194 } 2195 2196 int 2197 pci_set_max_read_req(device_t dev, int size) 2198 { 2199 struct pci_devinfo *dinfo = device_get_ivars(dev); 2200 int cap; 2201 uint16_t val; 2202 2203 cap = dinfo->cfg.pcie.pcie_location; 2204 if (cap == 0) 2205 return (0); 2206 if (size < 128) 2207 size = 128; 2208 if (size > 4096) 2209 size = 4096; 2210 size = (1 << (fls(size) - 1)); 2211 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2212 val &= ~PCIEM_CTL_MAX_READ_REQUEST; 2213 val |= (fls(size) - 8) << 12; 2214 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2); 2215 return (size); 2216 } 2217 2218 uint32_t 2219 pcie_read_config(device_t dev, int reg, int width) 2220 { 2221 struct pci_devinfo *dinfo = device_get_ivars(dev); 2222 int cap; 2223 2224 cap = dinfo->cfg.pcie.pcie_location; 2225 if (cap == 0) { 2226 if (width == 2) 2227 return (0xffff); 2228 return (0xffffffff); 2229 } 2230 2231 return (pci_read_config(dev, cap + reg, width)); 2232 } 2233 2234 void 2235 pcie_write_config(device_t dev, int reg, uint32_t value, int width) 2236 { 2237 struct pci_devinfo *dinfo = device_get_ivars(dev); 2238 int cap; 2239 2240 cap = dinfo->cfg.pcie.pcie_location; 2241 if (cap == 0) 2242 return; 2243 pci_write_config(dev, cap + reg, value, width); 2244 } 2245 2246 /* 2247 * Adjusts a PCI-e capability register by clearing the bits in mask 2248 * and setting the bits in (value & mask). Bits not set in mask are 2249 * not adjusted. 2250 * 2251 * Returns the old value on success or all ones on failure. 2252 */ 2253 uint32_t 2254 pcie_adjust_config(device_t dev, int reg, uint32_t mask, uint32_t value, 2255 int width) 2256 { 2257 struct pci_devinfo *dinfo = device_get_ivars(dev); 2258 uint32_t old, new; 2259 int cap; 2260 2261 cap = dinfo->cfg.pcie.pcie_location; 2262 if (cap == 0) { 2263 if (width == 2) 2264 return (0xffff); 2265 return (0xffffffff); 2266 } 2267 2268 old = pci_read_config(dev, cap + reg, width); 2269 new = old & ~mask; 2270 new |= (value & mask); 2271 pci_write_config(dev, cap + reg, new, width); 2272 return (old); 2273 } 2274 2275 /* 2276 * Support for MSI message signalled interrupts. 2277 */ 2278 void 2279 pci_enable_msi_method(device_t dev, device_t child, uint64_t address, 2280 uint16_t data) 2281 { 2282 struct pci_devinfo *dinfo = device_get_ivars(child); 2283 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2284 2285 /* Write data and address values. */ 2286 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, 2287 address & 0xffffffff, 4); 2288 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2289 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, 2290 address >> 32, 4); 2291 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, 2292 data, 2); 2293 } else 2294 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, 2295 2); 2296 2297 /* Enable MSI in the control register. */ 2298 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 2299 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2300 msi->msi_ctrl, 2); 2301 2302 /* Enable MSI -> HT mapping. */ 2303 pci_ht_map_msi(child, address); 2304 } 2305 2306 void 2307 pci_disable_msi_method(device_t dev, device_t child) 2308 { 2309 struct pci_devinfo *dinfo = device_get_ivars(child); 2310 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2311 2312 /* Disable MSI -> HT mapping. */ 2313 pci_ht_map_msi(child, 0); 2314 2315 /* Disable MSI in the control register. */ 2316 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; 2317 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2318 msi->msi_ctrl, 2); 2319 } 2320 2321 /* 2322 * Restore MSI registers during resume. If MSI is enabled then 2323 * restore the data and address registers in addition to the control 2324 * register. 2325 */ 2326 static void 2327 pci_resume_msi(device_t dev) 2328 { 2329 struct pci_devinfo *dinfo = device_get_ivars(dev); 2330 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2331 uint64_t address; 2332 uint16_t data; 2333 2334 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 2335 address = msi->msi_addr; 2336 data = msi->msi_data; 2337 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 2338 address & 0xffffffff, 4); 2339 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2340 pci_write_config(dev, msi->msi_location + 2341 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 2342 pci_write_config(dev, msi->msi_location + 2343 PCIR_MSI_DATA_64BIT, data, 2); 2344 } else 2345 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, 2346 data, 2); 2347 } 2348 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 2349 2); 2350 } 2351 2352 static int 2353 pci_remap_intr_method(device_t bus, device_t dev, u_int irq) 2354 { 2355 struct pci_devinfo *dinfo = device_get_ivars(dev); 2356 pcicfgregs *cfg = &dinfo->cfg; 2357 struct resource_list_entry *rle; 2358 struct msix_table_entry *mte; 2359 struct msix_vector *mv; 2360 uint64_t addr; 2361 uint32_t data; 2362 int error, i, j; 2363 2364 /* 2365 * Handle MSI first. We try to find this IRQ among our list 2366 * of MSI IRQs. If we find it, we request updated address and 2367 * data registers and apply the results. 2368 */ 2369 if (cfg->msi.msi_alloc > 0) { 2370 2371 /* If we don't have any active handlers, nothing to do. */ 2372 if (cfg->msi.msi_handlers == 0) 2373 return (0); 2374 for (i = 0; i < cfg->msi.msi_alloc; i++) { 2375 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 2376 i + 1); 2377 if (rle->start == irq) { 2378 error = PCIB_MAP_MSI(device_get_parent(bus), 2379 dev, irq, &addr, &data); 2380 if (error) 2381 return (error); 2382 pci_disable_msi(dev); 2383 dinfo->cfg.msi.msi_addr = addr; 2384 dinfo->cfg.msi.msi_data = data; 2385 pci_enable_msi(dev, addr, data); 2386 return (0); 2387 } 2388 } 2389 return (ENOENT); 2390 } 2391 2392 /* 2393 * For MSI-X, we check to see if we have this IRQ. If we do, 2394 * we request the updated mapping info. If that works, we go 2395 * through all the slots that use this IRQ and update them. 2396 */ 2397 if (cfg->msix.msix_alloc > 0) { 2398 for (i = 0; i < cfg->msix.msix_alloc; i++) { 2399 mv = &cfg->msix.msix_vectors[i]; 2400 if (mv->mv_irq == irq) { 2401 error = PCIB_MAP_MSI(device_get_parent(bus), 2402 dev, irq, &addr, &data); 2403 if (error) 2404 return (error); 2405 mv->mv_address = addr; 2406 mv->mv_data = data; 2407 for (j = 0; j < cfg->msix.msix_table_len; j++) { 2408 mte = &cfg->msix.msix_table[j]; 2409 if (mte->mte_vector != i + 1) 2410 continue; 2411 if (mte->mte_handlers == 0) 2412 continue; 2413 pci_mask_msix(dev, j); 2414 pci_enable_msix(dev, j, addr, data); 2415 pci_unmask_msix(dev, j); 2416 } 2417 } 2418 } 2419 return (ENOENT); 2420 } 2421 2422 return (ENOENT); 2423 } 2424 2425 /* 2426 * Returns true if the specified device is blacklisted because MSI 2427 * doesn't work. 2428 */ 2429 int 2430 pci_msi_device_blacklisted(device_t dev) 2431 { 2432 2433 if (!pci_honor_msi_blacklist) 2434 return (0); 2435 2436 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI)); 2437 } 2438 2439 /* 2440 * Determine if MSI is blacklisted globally on this system. Currently, 2441 * we just check for blacklisted chipsets as represented by the 2442 * host-PCI bridge at device 0:0:0. In the future, it may become 2443 * necessary to check other system attributes, such as the kenv values 2444 * that give the motherboard manufacturer and model number. 2445 */ 2446 static int 2447 pci_msi_blacklisted(void) 2448 { 2449 device_t dev; 2450 2451 if (!pci_honor_msi_blacklist) 2452 return (0); 2453 2454 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ 2455 if (!(pcie_chipset || pcix_chipset)) { 2456 if (vm_guest != VM_GUEST_NO) { 2457 /* 2458 * Whitelist older chipsets in virtual 2459 * machines known to support MSI. 2460 */ 2461 dev = pci_find_bsf(0, 0, 0); 2462 if (dev != NULL) 2463 return (!pci_has_quirk(pci_get_devid(dev), 2464 PCI_QUIRK_ENABLE_MSI_VM)); 2465 } 2466 return (1); 2467 } 2468 2469 dev = pci_find_bsf(0, 0, 0); 2470 if (dev != NULL) 2471 return (pci_msi_device_blacklisted(dev)); 2472 return (0); 2473 } 2474 2475 /* 2476 * Returns true if the specified device is blacklisted because MSI-X 2477 * doesn't work. Note that this assumes that if MSI doesn't work, 2478 * MSI-X doesn't either. 2479 */ 2480 int 2481 pci_msix_device_blacklisted(device_t dev) 2482 { 2483 2484 if (!pci_honor_msi_blacklist) 2485 return (0); 2486 2487 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX)) 2488 return (1); 2489 2490 return (pci_msi_device_blacklisted(dev)); 2491 } 2492 2493 /* 2494 * Determine if MSI-X is blacklisted globally on this system. If MSI 2495 * is blacklisted, assume that MSI-X is as well. Check for additional 2496 * chipsets where MSI works but MSI-X does not. 2497 */ 2498 static int 2499 pci_msix_blacklisted(void) 2500 { 2501 device_t dev; 2502 2503 if (!pci_honor_msi_blacklist) 2504 return (0); 2505 2506 dev = pci_find_bsf(0, 0, 0); 2507 if (dev != NULL && pci_has_quirk(pci_get_devid(dev), 2508 PCI_QUIRK_DISABLE_MSIX)) 2509 return (1); 2510 2511 return (pci_msi_blacklisted()); 2512 } 2513 2514 /* 2515 * Attempt to allocate *count MSI messages. The actual number allocated is 2516 * returned in *count. After this function returns, each message will be 2517 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 2518 */ 2519 int 2520 pci_alloc_msi_method(device_t dev, device_t child, int *count) 2521 { 2522 struct pci_devinfo *dinfo = device_get_ivars(child); 2523 pcicfgregs *cfg = &dinfo->cfg; 2524 struct resource_list_entry *rle; 2525 int actual, error, i, irqs[32]; 2526 uint16_t ctrl; 2527 2528 /* Don't let count == 0 get us into trouble. */ 2529 if (*count == 0) 2530 return (EINVAL); 2531 2532 /* If rid 0 is allocated, then fail. */ 2533 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 2534 if (rle != NULL && rle->res != NULL) 2535 return (ENXIO); 2536 2537 /* Already have allocated messages? */ 2538 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 2539 return (ENXIO); 2540 2541 /* If MSI is blacklisted for this system, fail. */ 2542 if (pci_msi_blacklisted()) 2543 return (ENXIO); 2544 2545 /* MSI capability present? */ 2546 if (cfg->msi.msi_location == 0 || !pci_do_msi) 2547 return (ENODEV); 2548 2549 if (bootverbose) 2550 device_printf(child, 2551 "attempting to allocate %d MSI vectors (%d supported)\n", 2552 *count, cfg->msi.msi_msgnum); 2553 2554 /* Don't ask for more than the device supports. */ 2555 actual = min(*count, cfg->msi.msi_msgnum); 2556 2557 /* Don't ask for more than 32 messages. */ 2558 actual = min(actual, 32); 2559 2560 /* MSI requires power of 2 number of messages. */ 2561 if (!powerof2(actual)) 2562 return (EINVAL); 2563 2564 for (;;) { 2565 /* Try to allocate N messages. */ 2566 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 2567 actual, irqs); 2568 if (error == 0) 2569 break; 2570 if (actual == 1) 2571 return (error); 2572 2573 /* Try N / 2. */ 2574 actual >>= 1; 2575 } 2576 2577 /* 2578 * We now have N actual messages mapped onto SYS_RES_IRQ 2579 * resources in the irqs[] array, so add new resources 2580 * starting at rid 1. 2581 */ 2582 for (i = 0; i < actual; i++) 2583 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 2584 irqs[i], irqs[i], 1); 2585 2586 if (bootverbose) { 2587 if (actual == 1) 2588 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 2589 else { 2590 int run; 2591 2592 /* 2593 * Be fancy and try to print contiguous runs 2594 * of IRQ values as ranges. 'run' is true if 2595 * we are in a range. 2596 */ 2597 device_printf(child, "using IRQs %d", irqs[0]); 2598 run = 0; 2599 for (i = 1; i < actual; i++) { 2600 2601 /* Still in a run? */ 2602 if (irqs[i] == irqs[i - 1] + 1) { 2603 run = 1; 2604 continue; 2605 } 2606 2607 /* Finish previous range. */ 2608 if (run) { 2609 printf("-%d", irqs[i - 1]); 2610 run = 0; 2611 } 2612 2613 /* Start new range. */ 2614 printf(",%d", irqs[i]); 2615 } 2616 2617 /* Unfinished range? */ 2618 if (run) 2619 printf("-%d", irqs[actual - 1]); 2620 printf(" for MSI\n"); 2621 } 2622 } 2623 2624 /* Update control register with actual count. */ 2625 ctrl = cfg->msi.msi_ctrl; 2626 ctrl &= ~PCIM_MSICTRL_MME_MASK; 2627 ctrl |= (ffs(actual) - 1) << 4; 2628 cfg->msi.msi_ctrl = ctrl; 2629 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 2630 2631 /* Update counts of alloc'd messages. */ 2632 cfg->msi.msi_alloc = actual; 2633 cfg->msi.msi_handlers = 0; 2634 *count = actual; 2635 return (0); 2636 } 2637 2638 /* Release the MSI messages associated with this device. */ 2639 int 2640 pci_release_msi_method(device_t dev, device_t child) 2641 { 2642 struct pci_devinfo *dinfo = device_get_ivars(child); 2643 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2644 struct resource_list_entry *rle; 2645 int error, i, irqs[32]; 2646 2647 /* Try MSI-X first. */ 2648 error = pci_release_msix(dev, child); 2649 if (error != ENODEV) 2650 return (error); 2651 2652 /* Do we have any messages to release? */ 2653 if (msi->msi_alloc == 0) 2654 return (ENODEV); 2655 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); 2656 2657 /* Make sure none of the resources are allocated. */ 2658 if (msi->msi_handlers > 0) 2659 return (EBUSY); 2660 for (i = 0; i < msi->msi_alloc; i++) { 2661 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2662 KASSERT(rle != NULL, ("missing MSI resource")); 2663 if (rle->res != NULL) 2664 return (EBUSY); 2665 irqs[i] = rle->start; 2666 } 2667 2668 /* Update control register with 0 count. */ 2669 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), 2670 ("%s: MSI still enabled", __func__)); 2671 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; 2672 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2673 msi->msi_ctrl, 2); 2674 2675 /* Release the messages. */ 2676 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); 2677 for (i = 0; i < msi->msi_alloc; i++) 2678 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2679 2680 /* Update alloc count. */ 2681 msi->msi_alloc = 0; 2682 msi->msi_addr = 0; 2683 msi->msi_data = 0; 2684 return (0); 2685 } 2686 2687 /* 2688 * Return the max supported MSI messages this device supports. 2689 * Basically, assuming the MD code can alloc messages, this function 2690 * should return the maximum value that pci_alloc_msi() can return. 2691 * Thus, it is subject to the tunables, etc. 2692 */ 2693 int 2694 pci_msi_count_method(device_t dev, device_t child) 2695 { 2696 struct pci_devinfo *dinfo = device_get_ivars(child); 2697 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2698 2699 if (pci_do_msi && msi->msi_location != 0) 2700 return (msi->msi_msgnum); 2701 return (0); 2702 } 2703 2704 /* free pcicfgregs structure and all depending data structures */ 2705 2706 int 2707 pci_freecfg(struct pci_devinfo *dinfo) 2708 { 2709 struct devlist *devlist_head; 2710 struct pci_map *pm, *next; 2711 int i; 2712 2713 devlist_head = &pci_devq; 2714 2715 if (dinfo->cfg.vpd.vpd_reg) { 2716 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF); 2717 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++) 2718 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF); 2719 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF); 2720 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++) 2721 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF); 2722 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF); 2723 } 2724 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { 2725 free(pm, M_DEVBUF); 2726 } 2727 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 2728 free(dinfo, M_DEVBUF); 2729 2730 /* increment the generation count */ 2731 pci_generation++; 2732 2733 /* we're losing one device */ 2734 pci_numdevs--; 2735 return (0); 2736 } 2737 2738 /* 2739 * PCI power manangement 2740 */ 2741 int 2742 pci_set_powerstate_method(device_t dev, device_t child, int state) 2743 { 2744 struct pci_devinfo *dinfo = device_get_ivars(child); 2745 pcicfgregs *cfg = &dinfo->cfg; 2746 uint16_t status; 2747 int oldstate, highest, delay; 2748 2749 if (cfg->pp.pp_cap == 0) 2750 return (EOPNOTSUPP); 2751 2752 /* 2753 * Optimize a no state change request away. While it would be OK to 2754 * write to the hardware in theory, some devices have shown odd 2755 * behavior when going from D3 -> D3. 2756 */ 2757 oldstate = pci_get_powerstate(child); 2758 if (oldstate == state) 2759 return (0); 2760 2761 /* 2762 * The PCI power management specification states that after a state 2763 * transition between PCI power states, system software must 2764 * guarantee a minimal delay before the function accesses the device. 2765 * Compute the worst case delay that we need to guarantee before we 2766 * access the device. Many devices will be responsive much more 2767 * quickly than this delay, but there are some that don't respond 2768 * instantly to state changes. Transitions to/from D3 state require 2769 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 2770 * is done below with DELAY rather than a sleeper function because 2771 * this function can be called from contexts where we cannot sleep. 2772 */ 2773 highest = (oldstate > state) ? oldstate : state; 2774 if (highest == PCI_POWERSTATE_D3) 2775 delay = 10000; 2776 else if (highest == PCI_POWERSTATE_D2) 2777 delay = 200; 2778 else 2779 delay = 0; 2780 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 2781 & ~PCIM_PSTAT_DMASK; 2782 switch (state) { 2783 case PCI_POWERSTATE_D0: 2784 status |= PCIM_PSTAT_D0; 2785 break; 2786 case PCI_POWERSTATE_D1: 2787 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 2788 return (EOPNOTSUPP); 2789 status |= PCIM_PSTAT_D1; 2790 break; 2791 case PCI_POWERSTATE_D2: 2792 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 2793 return (EOPNOTSUPP); 2794 status |= PCIM_PSTAT_D2; 2795 break; 2796 case PCI_POWERSTATE_D3: 2797 status |= PCIM_PSTAT_D3; 2798 break; 2799 default: 2800 return (EINVAL); 2801 } 2802 2803 if (bootverbose) 2804 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate, 2805 state); 2806 2807 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 2808 if (delay) 2809 DELAY(delay); 2810 return (0); 2811 } 2812 2813 int 2814 pci_get_powerstate_method(device_t dev, device_t child) 2815 { 2816 struct pci_devinfo *dinfo = device_get_ivars(child); 2817 pcicfgregs *cfg = &dinfo->cfg; 2818 uint16_t status; 2819 int result; 2820 2821 if (cfg->pp.pp_cap != 0) { 2822 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 2823 switch (status & PCIM_PSTAT_DMASK) { 2824 case PCIM_PSTAT_D0: 2825 result = PCI_POWERSTATE_D0; 2826 break; 2827 case PCIM_PSTAT_D1: 2828 result = PCI_POWERSTATE_D1; 2829 break; 2830 case PCIM_PSTAT_D2: 2831 result = PCI_POWERSTATE_D2; 2832 break; 2833 case PCIM_PSTAT_D3: 2834 result = PCI_POWERSTATE_D3; 2835 break; 2836 default: 2837 result = PCI_POWERSTATE_UNKNOWN; 2838 break; 2839 } 2840 } else { 2841 /* No support, device is always at D0 */ 2842 result = PCI_POWERSTATE_D0; 2843 } 2844 return (result); 2845 } 2846 2847 /* 2848 * Some convenience functions for PCI device drivers. 2849 */ 2850 2851 static __inline void 2852 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 2853 { 2854 uint16_t command; 2855 2856 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2857 command |= bit; 2858 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2859 } 2860 2861 static __inline void 2862 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 2863 { 2864 uint16_t command; 2865 2866 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2867 command &= ~bit; 2868 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2869 } 2870 2871 int 2872 pci_enable_busmaster_method(device_t dev, device_t child) 2873 { 2874 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2875 return (0); 2876 } 2877 2878 int 2879 pci_disable_busmaster_method(device_t dev, device_t child) 2880 { 2881 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2882 return (0); 2883 } 2884 2885 int 2886 pci_enable_io_method(device_t dev, device_t child, int space) 2887 { 2888 uint16_t bit; 2889 2890 switch(space) { 2891 case SYS_RES_IOPORT: 2892 bit = PCIM_CMD_PORTEN; 2893 break; 2894 case SYS_RES_MEMORY: 2895 bit = PCIM_CMD_MEMEN; 2896 break; 2897 default: 2898 return (EINVAL); 2899 } 2900 pci_set_command_bit(dev, child, bit); 2901 return (0); 2902 } 2903 2904 int 2905 pci_disable_io_method(device_t dev, device_t child, int space) 2906 { 2907 uint16_t bit; 2908 2909 switch(space) { 2910 case SYS_RES_IOPORT: 2911 bit = PCIM_CMD_PORTEN; 2912 break; 2913 case SYS_RES_MEMORY: 2914 bit = PCIM_CMD_MEMEN; 2915 break; 2916 default: 2917 return (EINVAL); 2918 } 2919 pci_clear_command_bit(dev, child, bit); 2920 return (0); 2921 } 2922 2923 /* 2924 * New style pci driver. Parent device is either a pci-host-bridge or a 2925 * pci-pci-bridge. Both kinds are represented by instances of pcib. 2926 */ 2927 2928 void 2929 pci_print_verbose(struct pci_devinfo *dinfo) 2930 { 2931 2932 if (bootverbose) { 2933 pcicfgregs *cfg = &dinfo->cfg; 2934 2935 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 2936 cfg->vendor, cfg->device, cfg->revid); 2937 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n", 2938 cfg->domain, cfg->bus, cfg->slot, cfg->func); 2939 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 2940 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 2941 cfg->mfdev); 2942 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 2943 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 2944 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 2945 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 2946 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 2947 if (cfg->intpin > 0) 2948 printf("\tintpin=%c, irq=%d\n", 2949 cfg->intpin +'a' -1, cfg->intline); 2950 if (cfg->pp.pp_cap) { 2951 uint16_t status; 2952 2953 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 2954 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 2955 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 2956 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 2957 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 2958 status & PCIM_PSTAT_DMASK); 2959 } 2960 if (cfg->msi.msi_location) { 2961 int ctrl; 2962 2963 ctrl = cfg->msi.msi_ctrl; 2964 printf("\tMSI supports %d message%s%s%s\n", 2965 cfg->msi.msi_msgnum, 2966 (cfg->msi.msi_msgnum == 1) ? "" : "s", 2967 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 2968 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 2969 } 2970 if (cfg->msix.msix_location) { 2971 printf("\tMSI-X supports %d message%s ", 2972 cfg->msix.msix_msgnum, 2973 (cfg->msix.msix_msgnum == 1) ? "" : "s"); 2974 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 2975 printf("in map 0x%x\n", 2976 cfg->msix.msix_table_bar); 2977 else 2978 printf("in maps 0x%x and 0x%x\n", 2979 cfg->msix.msix_table_bar, 2980 cfg->msix.msix_pba_bar); 2981 } 2982 } 2983 } 2984 2985 static int 2986 pci_porten(device_t dev) 2987 { 2988 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0; 2989 } 2990 2991 static int 2992 pci_memen(device_t dev) 2993 { 2994 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0; 2995 } 2996 2997 void 2998 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, 2999 int *bar64) 3000 { 3001 struct pci_devinfo *dinfo; 3002 pci_addr_t map, testval; 3003 int ln2range; 3004 uint16_t cmd; 3005 3006 /* 3007 * The device ROM BAR is special. It is always a 32-bit 3008 * memory BAR. Bit 0 is special and should not be set when 3009 * sizing the BAR. 3010 */ 3011 dinfo = device_get_ivars(dev); 3012 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { 3013 map = pci_read_config(dev, reg, 4); 3014 pci_write_config(dev, reg, 0xfffffffe, 4); 3015 testval = pci_read_config(dev, reg, 4); 3016 pci_write_config(dev, reg, map, 4); 3017 *mapp = map; 3018 *testvalp = testval; 3019 if (bar64 != NULL) 3020 *bar64 = 0; 3021 return; 3022 } 3023 3024 map = pci_read_config(dev, reg, 4); 3025 ln2range = pci_maprange(map); 3026 if (ln2range == 64) 3027 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3028 3029 /* 3030 * Disable decoding via the command register before 3031 * determining the BAR's length since we will be placing it in 3032 * a weird state. 3033 */ 3034 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3035 pci_write_config(dev, PCIR_COMMAND, 3036 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 3037 3038 /* 3039 * Determine the BAR's length by writing all 1's. The bottom 3040 * log_2(size) bits of the BAR will stick as 0 when we read 3041 * the value back. 3042 * 3043 * NB: according to the PCI Local Bus Specification, rev. 3.0: 3044 * "Software writes 0FFFFFFFFh to both registers, reads them back, 3045 * and combines the result into a 64-bit value." (section 6.2.5.1) 3046 * 3047 * Writes to both registers must be performed before attempting to 3048 * read back the size value. 3049 */ 3050 testval = 0; 3051 pci_write_config(dev, reg, 0xffffffff, 4); 3052 if (ln2range == 64) { 3053 pci_write_config(dev, reg + 4, 0xffffffff, 4); 3054 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3055 } 3056 testval |= pci_read_config(dev, reg, 4); 3057 3058 /* 3059 * Restore the original value of the BAR. We may have reprogrammed 3060 * the BAR of the low-level console device and when booting verbose, 3061 * we need the console device addressable. 3062 */ 3063 pci_write_config(dev, reg, map, 4); 3064 if (ln2range == 64) 3065 pci_write_config(dev, reg + 4, map >> 32, 4); 3066 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3067 3068 *mapp = map; 3069 *testvalp = testval; 3070 if (bar64 != NULL) 3071 *bar64 = (ln2range == 64); 3072 } 3073 3074 static void 3075 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base) 3076 { 3077 struct pci_devinfo *dinfo; 3078 int ln2range; 3079 3080 /* The device ROM BAR is always a 32-bit memory BAR. */ 3081 dinfo = device_get_ivars(dev); 3082 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3083 ln2range = 32; 3084 else 3085 ln2range = pci_maprange(pm->pm_value); 3086 pci_write_config(dev, pm->pm_reg, base, 4); 3087 if (ln2range == 64) 3088 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); 3089 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); 3090 if (ln2range == 64) 3091 pm->pm_value |= (pci_addr_t)pci_read_config(dev, 3092 pm->pm_reg + 4, 4) << 32; 3093 } 3094 3095 struct pci_map * 3096 pci_find_bar(device_t dev, int reg) 3097 { 3098 struct pci_devinfo *dinfo; 3099 struct pci_map *pm; 3100 3101 dinfo = device_get_ivars(dev); 3102 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3103 if (pm->pm_reg == reg) 3104 return (pm); 3105 } 3106 return (NULL); 3107 } 3108 3109 int 3110 pci_bar_enabled(device_t dev, struct pci_map *pm) 3111 { 3112 struct pci_devinfo *dinfo; 3113 uint16_t cmd; 3114 3115 dinfo = device_get_ivars(dev); 3116 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && 3117 !(pm->pm_value & PCIM_BIOS_ENABLE)) 3118 return (0); 3119 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3120 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) 3121 return ((cmd & PCIM_CMD_MEMEN) != 0); 3122 else 3123 return ((cmd & PCIM_CMD_PORTEN) != 0); 3124 } 3125 3126 struct pci_map * 3127 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size) 3128 { 3129 struct pci_devinfo *dinfo; 3130 struct pci_map *pm, *prev; 3131 3132 dinfo = device_get_ivars(dev); 3133 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO); 3134 pm->pm_reg = reg; 3135 pm->pm_value = value; 3136 pm->pm_size = size; 3137 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { 3138 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", 3139 reg)); 3140 if (STAILQ_NEXT(prev, pm_link) == NULL || 3141 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) 3142 break; 3143 } 3144 if (prev != NULL) 3145 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); 3146 else 3147 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); 3148 return (pm); 3149 } 3150 3151 static void 3152 pci_restore_bars(device_t dev) 3153 { 3154 struct pci_devinfo *dinfo; 3155 struct pci_map *pm; 3156 int ln2range; 3157 3158 dinfo = device_get_ivars(dev); 3159 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3160 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3161 ln2range = 32; 3162 else 3163 ln2range = pci_maprange(pm->pm_value); 3164 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); 3165 if (ln2range == 64) 3166 pci_write_config(dev, pm->pm_reg + 4, 3167 pm->pm_value >> 32, 4); 3168 } 3169 } 3170 3171 /* 3172 * Add a resource based on a pci map register. Return 1 if the map 3173 * register is a 32bit map register or 2 if it is a 64bit register. 3174 */ 3175 static int 3176 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, 3177 int force, int prefetch) 3178 { 3179 struct pci_map *pm; 3180 pci_addr_t base, map, testval; 3181 pci_addr_t start, end, count; 3182 int barlen, basezero, flags, maprange, mapsize, type; 3183 uint16_t cmd; 3184 struct resource *res; 3185 3186 /* 3187 * The BAR may already exist if the device is a CardBus card 3188 * whose CIS is stored in this BAR. 3189 */ 3190 pm = pci_find_bar(dev, reg); 3191 if (pm != NULL) { 3192 maprange = pci_maprange(pm->pm_value); 3193 barlen = maprange == 64 ? 2 : 1; 3194 return (barlen); 3195 } 3196 3197 pci_read_bar(dev, reg, &map, &testval, NULL); 3198 if (PCI_BAR_MEM(map)) { 3199 type = SYS_RES_MEMORY; 3200 if (map & PCIM_BAR_MEM_PREFETCH) 3201 prefetch = 1; 3202 } else 3203 type = SYS_RES_IOPORT; 3204 mapsize = pci_mapsize(testval); 3205 base = pci_mapbase(map); 3206 #ifdef __PCI_BAR_ZERO_VALID 3207 basezero = 0; 3208 #else 3209 basezero = base == 0; 3210 #endif 3211 maprange = pci_maprange(map); 3212 barlen = maprange == 64 ? 2 : 1; 3213 3214 /* 3215 * For I/O registers, if bottom bit is set, and the next bit up 3216 * isn't clear, we know we have a BAR that doesn't conform to the 3217 * spec, so ignore it. Also, sanity check the size of the data 3218 * areas to the type of memory involved. Memory must be at least 3219 * 16 bytes in size, while I/O ranges must be at least 4. 3220 */ 3221 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0) 3222 return (barlen); 3223 if ((type == SYS_RES_MEMORY && mapsize < 4) || 3224 (type == SYS_RES_IOPORT && mapsize < 2)) 3225 return (barlen); 3226 3227 /* Save a record of this BAR. */ 3228 pm = pci_add_bar(dev, reg, map, mapsize); 3229 if (bootverbose) { 3230 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d", 3231 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize); 3232 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3233 printf(", port disabled\n"); 3234 else if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3235 printf(", memory disabled\n"); 3236 else 3237 printf(", enabled\n"); 3238 } 3239 3240 /* 3241 * If base is 0, then we have problems if this architecture does 3242 * not allow that. It is best to ignore such entries for the 3243 * moment. These will be allocated later if the driver specifically 3244 * requests them. However, some removable buses look better when 3245 * all resources are allocated, so allow '0' to be overriden. 3246 * 3247 * Similarly treat maps whose values is the same as the test value 3248 * read back. These maps have had all f's written to them by the 3249 * BIOS in an attempt to disable the resources. 3250 */ 3251 if (!force && (basezero || map == testval)) 3252 return (barlen); 3253 if ((u_long)base != base) { 3254 device_printf(bus, 3255 "pci%d:%d:%d:%d bar %#x too many address bits", 3256 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev), 3257 pci_get_function(dev), reg); 3258 return (barlen); 3259 } 3260 3261 /* 3262 * This code theoretically does the right thing, but has 3263 * undesirable side effects in some cases where peripherals 3264 * respond oddly to having these bits enabled. Let the user 3265 * be able to turn them off (since pci_enable_io_modes is 1 by 3266 * default). 3267 */ 3268 if (pci_enable_io_modes) { 3269 /* Turn on resources that have been left off by a lazy BIOS */ 3270 if (type == SYS_RES_IOPORT && !pci_porten(dev)) { 3271 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3272 cmd |= PCIM_CMD_PORTEN; 3273 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3274 } 3275 if (type == SYS_RES_MEMORY && !pci_memen(dev)) { 3276 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3277 cmd |= PCIM_CMD_MEMEN; 3278 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3279 } 3280 } else { 3281 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3282 return (barlen); 3283 if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3284 return (barlen); 3285 } 3286 3287 count = (pci_addr_t)1 << mapsize; 3288 flags = RF_ALIGNMENT_LOG2(mapsize); 3289 if (prefetch) 3290 flags |= RF_PREFETCHABLE; 3291 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) { 3292 start = 0; /* Let the parent decide. */ 3293 end = ~0; 3294 } else { 3295 start = base; 3296 end = base + count - 1; 3297 } 3298 resource_list_add(rl, type, reg, start, end, count); 3299 3300 /* 3301 * Try to allocate the resource for this BAR from our parent 3302 * so that this resource range is already reserved. The 3303 * driver for this device will later inherit this resource in 3304 * pci_alloc_resource(). 3305 */ 3306 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count, 3307 flags); 3308 if ((pci_do_realloc_bars 3309 || pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_REALLOC_BAR)) 3310 && res == NULL && (start != 0 || end != ~0)) { 3311 /* 3312 * If the allocation fails, try to allocate a resource for 3313 * this BAR using any available range. The firmware felt 3314 * it was important enough to assign a resource, so don't 3315 * disable decoding if we can help it. 3316 */ 3317 resource_list_delete(rl, type, reg); 3318 resource_list_add(rl, type, reg, 0, ~0, count); 3319 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0, 3320 count, flags); 3321 } 3322 if (res == NULL) { 3323 /* 3324 * If the allocation fails, delete the resource list entry 3325 * and disable decoding for this device. 3326 * 3327 * If the driver requests this resource in the future, 3328 * pci_reserve_map() will try to allocate a fresh 3329 * resource range. 3330 */ 3331 resource_list_delete(rl, type, reg); 3332 pci_disable_io(dev, type); 3333 if (bootverbose) 3334 device_printf(bus, 3335 "pci%d:%d:%d:%d bar %#x failed to allocate\n", 3336 pci_get_domain(dev), pci_get_bus(dev), 3337 pci_get_slot(dev), pci_get_function(dev), reg); 3338 } else { 3339 start = rman_get_start(res); 3340 pci_write_bar(dev, pm, start); 3341 } 3342 return (barlen); 3343 } 3344 3345 /* 3346 * For ATA devices we need to decide early what addressing mode to use. 3347 * Legacy demands that the primary and secondary ATA ports sits on the 3348 * same addresses that old ISA hardware did. This dictates that we use 3349 * those addresses and ignore the BAR's if we cannot set PCI native 3350 * addressing mode. 3351 */ 3352 static void 3353 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, 3354 uint32_t prefetchmask) 3355 { 3356 int rid, type, progif; 3357 #if 0 3358 /* if this device supports PCI native addressing use it */ 3359 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3360 if ((progif & 0x8a) == 0x8a) { 3361 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 3362 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 3363 printf("Trying ATA native PCI addressing mode\n"); 3364 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 3365 } 3366 } 3367 #endif 3368 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3369 type = SYS_RES_IOPORT; 3370 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 3371 pci_add_map(bus, dev, PCIR_BAR(0), rl, force, 3372 prefetchmask & (1 << 0)); 3373 pci_add_map(bus, dev, PCIR_BAR(1), rl, force, 3374 prefetchmask & (1 << 1)); 3375 } else { 3376 rid = PCIR_BAR(0); 3377 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 3378 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0, 3379 0x1f7, 8, 0); 3380 rid = PCIR_BAR(1); 3381 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 3382 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6, 3383 0x3f6, 1, 0); 3384 } 3385 if (progif & PCIP_STORAGE_IDE_MODESEC) { 3386 pci_add_map(bus, dev, PCIR_BAR(2), rl, force, 3387 prefetchmask & (1 << 2)); 3388 pci_add_map(bus, dev, PCIR_BAR(3), rl, force, 3389 prefetchmask & (1 << 3)); 3390 } else { 3391 rid = PCIR_BAR(2); 3392 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 3393 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170, 3394 0x177, 8, 0); 3395 rid = PCIR_BAR(3); 3396 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 3397 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376, 3398 0x376, 1, 0); 3399 } 3400 pci_add_map(bus, dev, PCIR_BAR(4), rl, force, 3401 prefetchmask & (1 << 4)); 3402 pci_add_map(bus, dev, PCIR_BAR(5), rl, force, 3403 prefetchmask & (1 << 5)); 3404 } 3405 3406 static void 3407 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 3408 { 3409 struct pci_devinfo *dinfo = device_get_ivars(dev); 3410 pcicfgregs *cfg = &dinfo->cfg; 3411 char tunable_name[64]; 3412 int irq; 3413 3414 /* Has to have an intpin to have an interrupt. */ 3415 if (cfg->intpin == 0) 3416 return; 3417 3418 /* Let the user override the IRQ with a tunable. */ 3419 irq = PCI_INVALID_IRQ; 3420 snprintf(tunable_name, sizeof(tunable_name), 3421 "hw.pci%d.%d.%d.INT%c.irq", 3422 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 3423 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 3424 irq = PCI_INVALID_IRQ; 3425 3426 /* 3427 * If we didn't get an IRQ via the tunable, then we either use the 3428 * IRQ value in the intline register or we ask the bus to route an 3429 * interrupt for us. If force_route is true, then we only use the 3430 * value in the intline register if the bus was unable to assign an 3431 * IRQ. 3432 */ 3433 if (!PCI_INTERRUPT_VALID(irq)) { 3434 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 3435 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 3436 if (!PCI_INTERRUPT_VALID(irq)) 3437 irq = cfg->intline; 3438 } 3439 3440 /* If after all that we don't have an IRQ, just bail. */ 3441 if (!PCI_INTERRUPT_VALID(irq)) 3442 return; 3443 3444 /* Update the config register if it changed. */ 3445 if (irq != cfg->intline) { 3446 cfg->intline = irq; 3447 pci_write_config(dev, PCIR_INTLINE, irq, 1); 3448 } 3449 3450 /* Add this IRQ as rid 0 interrupt resource. */ 3451 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 3452 } 3453 3454 /* Perform early OHCI takeover from SMM. */ 3455 static void 3456 ohci_early_takeover(device_t self) 3457 { 3458 struct resource *res; 3459 uint32_t ctl; 3460 int rid; 3461 int i; 3462 3463 rid = PCIR_BAR(0); 3464 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3465 if (res == NULL) 3466 return; 3467 3468 ctl = bus_read_4(res, OHCI_CONTROL); 3469 if (ctl & OHCI_IR) { 3470 if (bootverbose) 3471 printf("ohci early: " 3472 "SMM active, request owner change\n"); 3473 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR); 3474 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 3475 DELAY(1000); 3476 ctl = bus_read_4(res, OHCI_CONTROL); 3477 } 3478 if (ctl & OHCI_IR) { 3479 if (bootverbose) 3480 printf("ohci early: " 3481 "SMM does not respond, resetting\n"); 3482 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET); 3483 } 3484 /* Disable interrupts */ 3485 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 3486 } 3487 3488 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3489 } 3490 3491 /* Perform early UHCI takeover from SMM. */ 3492 static void 3493 uhci_early_takeover(device_t self) 3494 { 3495 struct resource *res; 3496 int rid; 3497 3498 /* 3499 * Set the PIRQD enable bit and switch off all the others. We don't 3500 * want legacy support to interfere with us XXX Does this also mean 3501 * that the BIOS won't touch the keyboard anymore if it is connected 3502 * to the ports of the root hub? 3503 */ 3504 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2); 3505 3506 /* Disable interrupts */ 3507 rid = PCI_UHCI_BASE_REG; 3508 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE); 3509 if (res != NULL) { 3510 bus_write_2(res, UHCI_INTR, 0); 3511 bus_release_resource(self, SYS_RES_IOPORT, rid, res); 3512 } 3513 } 3514 3515 /* Perform early EHCI takeover from SMM. */ 3516 static void 3517 ehci_early_takeover(device_t self) 3518 { 3519 struct resource *res; 3520 uint32_t cparams; 3521 uint32_t eec; 3522 uint8_t eecp; 3523 uint8_t bios_sem; 3524 uint8_t offs; 3525 int rid; 3526 int i; 3527 3528 rid = PCIR_BAR(0); 3529 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3530 if (res == NULL) 3531 return; 3532 3533 cparams = bus_read_4(res, EHCI_HCCPARAMS); 3534 3535 /* Synchronise with the BIOS if it owns the controller. */ 3536 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0; 3537 eecp = EHCI_EECP_NEXT(eec)) { 3538 eec = pci_read_config(self, eecp, 4); 3539 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) { 3540 continue; 3541 } 3542 bios_sem = pci_read_config(self, eecp + 3543 EHCI_LEGSUP_BIOS_SEM, 1); 3544 if (bios_sem == 0) { 3545 continue; 3546 } 3547 if (bootverbose) 3548 printf("ehci early: " 3549 "SMM active, request owner change\n"); 3550 3551 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1); 3552 3553 for (i = 0; (i < 100) && (bios_sem != 0); i++) { 3554 DELAY(1000); 3555 bios_sem = pci_read_config(self, eecp + 3556 EHCI_LEGSUP_BIOS_SEM, 1); 3557 } 3558 3559 if (bios_sem != 0) { 3560 if (bootverbose) 3561 printf("ehci early: " 3562 "SMM does not respond\n"); 3563 } 3564 /* Disable interrupts */ 3565 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION)); 3566 bus_write_4(res, offs + EHCI_USBINTR, 0); 3567 } 3568 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3569 } 3570 3571 /* Perform early XHCI takeover from SMM. */ 3572 static void 3573 xhci_early_takeover(device_t self) 3574 { 3575 struct resource *res; 3576 uint32_t cparams; 3577 uint32_t eec; 3578 uint8_t eecp; 3579 uint8_t bios_sem; 3580 uint8_t offs; 3581 int rid; 3582 int i; 3583 3584 rid = PCIR_BAR(0); 3585 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3586 if (res == NULL) 3587 return; 3588 3589 cparams = bus_read_4(res, XHCI_HCSPARAMS0); 3590 3591 eec = -1; 3592 3593 /* Synchronise with the BIOS if it owns the controller. */ 3594 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 3595 eecp += XHCI_XECP_NEXT(eec) << 2) { 3596 eec = bus_read_4(res, eecp); 3597 3598 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 3599 continue; 3600 3601 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM); 3602 if (bios_sem == 0) 3603 continue; 3604 3605 if (bootverbose) 3606 printf("xhci early: " 3607 "SMM active, request owner change\n"); 3608 3609 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1); 3610 3611 /* wait a maximum of 5 second */ 3612 3613 for (i = 0; (i < 5000) && (bios_sem != 0); i++) { 3614 DELAY(1000); 3615 bios_sem = bus_read_1(res, eecp + 3616 XHCI_XECP_BIOS_SEM); 3617 } 3618 3619 if (bios_sem != 0) { 3620 if (bootverbose) 3621 printf("xhci early: " 3622 "SMM does not respond\n"); 3623 } 3624 3625 /* Disable interrupts */ 3626 offs = bus_read_1(res, XHCI_CAPLENGTH); 3627 bus_write_4(res, offs + XHCI_USBCMD, 0); 3628 bus_read_4(res, offs + XHCI_USBSTS); 3629 } 3630 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3631 } 3632 3633 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 3634 static void 3635 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg, 3636 struct resource_list *rl) 3637 { 3638 struct resource *res; 3639 char *cp; 3640 rman_res_t start, end, count; 3641 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus; 3642 3643 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3644 case PCIM_HDRTYPE_BRIDGE: 3645 sec_reg = PCIR_SECBUS_1; 3646 sub_reg = PCIR_SUBBUS_1; 3647 break; 3648 case PCIM_HDRTYPE_CARDBUS: 3649 sec_reg = PCIR_SECBUS_2; 3650 sub_reg = PCIR_SUBBUS_2; 3651 break; 3652 default: 3653 return; 3654 } 3655 3656 /* 3657 * If the existing bus range is valid, attempt to reserve it 3658 * from our parent. If this fails for any reason, clear the 3659 * secbus and subbus registers. 3660 * 3661 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus? 3662 * This would at least preserve the existing sec_bus if it is 3663 * valid. 3664 */ 3665 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1); 3666 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1); 3667 3668 /* Quirk handling. */ 3669 switch (pci_get_devid(dev)) { 3670 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 3671 sup_bus = pci_read_config(dev, 0x41, 1); 3672 if (sup_bus != 0xff) { 3673 sec_bus = sup_bus + 1; 3674 sub_bus = sup_bus + 1; 3675 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1); 3676 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3677 } 3678 break; 3679 3680 case 0x00dd10de: 3681 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 3682 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 3683 break; 3684 if (strncmp(cp, "Compal", 6) != 0) { 3685 freeenv(cp); 3686 break; 3687 } 3688 freeenv(cp); 3689 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 3690 break; 3691 if (strncmp(cp, "08A0", 4) != 0) { 3692 freeenv(cp); 3693 break; 3694 } 3695 freeenv(cp); 3696 if (sub_bus < 0xa) { 3697 sub_bus = 0xa; 3698 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3699 } 3700 break; 3701 } 3702 3703 if (bootverbose) 3704 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus); 3705 if (sec_bus > 0 && sub_bus >= sec_bus) { 3706 start = sec_bus; 3707 end = sub_bus; 3708 count = end - start + 1; 3709 3710 resource_list_add(rl, PCI_RES_BUS, 0, 0, ~0, count); 3711 3712 /* 3713 * If requested, clear secondary bus registers in 3714 * bridge devices to force a complete renumbering 3715 * rather than reserving the existing range. However, 3716 * preserve the existing size. 3717 */ 3718 if (pci_clear_buses) 3719 goto clear; 3720 3721 rid = 0; 3722 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid, 3723 start, end, count, 0); 3724 if (res != NULL) 3725 return; 3726 3727 if (bootverbose) 3728 device_printf(bus, 3729 "pci%d:%d:%d:%d secbus failed to allocate\n", 3730 pci_get_domain(dev), pci_get_bus(dev), 3731 pci_get_slot(dev), pci_get_function(dev)); 3732 } 3733 3734 clear: 3735 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1); 3736 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1); 3737 } 3738 3739 static struct resource * 3740 pci_alloc_secbus(device_t dev, device_t child, int *rid, rman_res_t start, 3741 rman_res_t end, rman_res_t count, u_int flags) 3742 { 3743 struct pci_devinfo *dinfo; 3744 pcicfgregs *cfg; 3745 struct resource_list *rl; 3746 struct resource *res; 3747 int sec_reg, sub_reg; 3748 3749 dinfo = device_get_ivars(child); 3750 cfg = &dinfo->cfg; 3751 rl = &dinfo->resources; 3752 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3753 case PCIM_HDRTYPE_BRIDGE: 3754 sec_reg = PCIR_SECBUS_1; 3755 sub_reg = PCIR_SUBBUS_1; 3756 break; 3757 case PCIM_HDRTYPE_CARDBUS: 3758 sec_reg = PCIR_SECBUS_2; 3759 sub_reg = PCIR_SUBBUS_2; 3760 break; 3761 default: 3762 return (NULL); 3763 } 3764 3765 if (*rid != 0) 3766 return (NULL); 3767 3768 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL) 3769 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count); 3770 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) { 3771 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid, 3772 start, end, count, flags & ~RF_ACTIVE); 3773 if (res == NULL) { 3774 resource_list_delete(rl, PCI_RES_BUS, *rid); 3775 device_printf(child, "allocating %ju bus%s failed\n", 3776 count, count == 1 ? "" : "es"); 3777 return (NULL); 3778 } 3779 if (bootverbose) 3780 device_printf(child, 3781 "Lazy allocation of %ju bus%s at %ju\n", count, 3782 count == 1 ? "" : "es", rman_get_start(res)); 3783 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1); 3784 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1); 3785 } 3786 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start, 3787 end, count, flags)); 3788 } 3789 #endif 3790 3791 static int 3792 pci_ea_bei_to_rid(device_t dev, int bei) 3793 { 3794 #ifdef PCI_IOV 3795 struct pci_devinfo *dinfo; 3796 int iov_pos; 3797 struct pcicfg_iov *iov; 3798 3799 dinfo = device_get_ivars(dev); 3800 iov = dinfo->cfg.iov; 3801 if (iov != NULL) 3802 iov_pos = iov->iov_pos; 3803 else 3804 iov_pos = 0; 3805 #endif 3806 3807 /* Check if matches BAR */ 3808 if ((bei >= PCIM_EA_BEI_BAR_0) && 3809 (bei <= PCIM_EA_BEI_BAR_5)) 3810 return (PCIR_BAR(bei)); 3811 3812 /* Check ROM */ 3813 if (bei == PCIM_EA_BEI_ROM) 3814 return (PCIR_BIOS); 3815 3816 #ifdef PCI_IOV 3817 /* Check if matches VF_BAR */ 3818 if ((iov != NULL) && (bei >= PCIM_EA_BEI_VF_BAR_0) && 3819 (bei <= PCIM_EA_BEI_VF_BAR_5)) 3820 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) + 3821 iov_pos); 3822 #endif 3823 3824 return (-1); 3825 } 3826 3827 int 3828 pci_ea_is_enabled(device_t dev, int rid) 3829 { 3830 struct pci_ea_entry *ea; 3831 struct pci_devinfo *dinfo; 3832 3833 dinfo = device_get_ivars(dev); 3834 3835 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3836 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid) 3837 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0); 3838 } 3839 3840 return (0); 3841 } 3842 3843 void 3844 pci_add_resources_ea(device_t bus, device_t dev, int alloc_iov) 3845 { 3846 struct pci_ea_entry *ea; 3847 struct pci_devinfo *dinfo; 3848 pci_addr_t start, end, count; 3849 struct resource_list *rl; 3850 int type, flags, rid; 3851 struct resource *res; 3852 uint32_t tmp; 3853 #ifdef PCI_IOV 3854 struct pcicfg_iov *iov; 3855 #endif 3856 3857 dinfo = device_get_ivars(dev); 3858 rl = &dinfo->resources; 3859 flags = 0; 3860 3861 #ifdef PCI_IOV 3862 iov = dinfo->cfg.iov; 3863 #endif 3864 3865 if (dinfo->cfg.ea.ea_location == 0) 3866 return; 3867 3868 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3869 3870 /* 3871 * TODO: Ignore EA-BAR if is not enabled. 3872 * Currently the EA implementation supports 3873 * only situation, where EA structure contains 3874 * predefined entries. In case they are not enabled 3875 * leave them unallocated and proceed with 3876 * a legacy-BAR mechanism. 3877 */ 3878 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0) 3879 continue; 3880 3881 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) { 3882 case PCIM_EA_P_MEM_PREFETCH: 3883 case PCIM_EA_P_VF_MEM_PREFETCH: 3884 flags = RF_PREFETCHABLE; 3885 /* FALLTHROUGH */ 3886 case PCIM_EA_P_VF_MEM: 3887 case PCIM_EA_P_MEM: 3888 type = SYS_RES_MEMORY; 3889 break; 3890 case PCIM_EA_P_IO: 3891 type = SYS_RES_IOPORT; 3892 break; 3893 default: 3894 continue; 3895 } 3896 3897 if (alloc_iov != 0) { 3898 #ifdef PCI_IOV 3899 /* Allocating IOV, confirm BEI matches */ 3900 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) || 3901 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5)) 3902 continue; 3903 #else 3904 continue; 3905 #endif 3906 } else { 3907 /* Allocating BAR, confirm BEI matches */ 3908 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) || 3909 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) && 3910 (ea->eae_bei != PCIM_EA_BEI_ROM)) 3911 continue; 3912 } 3913 3914 rid = pci_ea_bei_to_rid(dev, ea->eae_bei); 3915 if (rid < 0) 3916 continue; 3917 3918 /* Skip resources already allocated by EA */ 3919 if ((resource_list_find(rl, SYS_RES_MEMORY, rid) != NULL) || 3920 (resource_list_find(rl, SYS_RES_IOPORT, rid) != NULL)) 3921 continue; 3922 3923 start = ea->eae_base; 3924 count = ea->eae_max_offset + 1; 3925 #ifdef PCI_IOV 3926 if (iov != NULL) 3927 count = count * iov->iov_num_vfs; 3928 #endif 3929 end = start + count - 1; 3930 if (count == 0) 3931 continue; 3932 3933 resource_list_add(rl, type, rid, start, end, count); 3934 res = resource_list_reserve(rl, bus, dev, type, &rid, start, end, count, 3935 flags); 3936 if (res == NULL) { 3937 resource_list_delete(rl, type, rid); 3938 3939 /* 3940 * Failed to allocate using EA, disable entry. 3941 * Another attempt to allocation will be performed 3942 * further, but this time using legacy BAR registers 3943 */ 3944 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4); 3945 tmp &= ~PCIM_EA_ENABLE; 3946 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4); 3947 3948 /* 3949 * Disabling entry might fail in case it is hardwired. 3950 * Read flags again to match current status. 3951 */ 3952 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4); 3953 3954 continue; 3955 } 3956 3957 /* As per specification, fill BAR with zeros */ 3958 pci_write_config(dev, rid, 0, 4); 3959 } 3960 } 3961 3962 void 3963 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 3964 { 3965 struct pci_devinfo *dinfo; 3966 pcicfgregs *cfg; 3967 struct resource_list *rl; 3968 const struct pci_quirk *q; 3969 uint32_t devid; 3970 int i; 3971 3972 dinfo = device_get_ivars(dev); 3973 cfg = &dinfo->cfg; 3974 rl = &dinfo->resources; 3975 devid = (cfg->device << 16) | cfg->vendor; 3976 3977 /* Allocate resources using Enhanced Allocation */ 3978 pci_add_resources_ea(bus, dev, 0); 3979 3980 /* ATA devices needs special map treatment */ 3981 if ((pci_get_class(dev) == PCIC_STORAGE) && 3982 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 3983 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 3984 (!pci_read_config(dev, PCIR_BAR(0), 4) && 3985 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 3986 pci_ata_maps(bus, dev, rl, force, prefetchmask); 3987 else 3988 for (i = 0; i < cfg->nummaps;) { 3989 /* Skip resources already managed by EA */ 3990 if ((resource_list_find(rl, SYS_RES_MEMORY, PCIR_BAR(i)) != NULL) || 3991 (resource_list_find(rl, SYS_RES_IOPORT, PCIR_BAR(i)) != NULL) || 3992 pci_ea_is_enabled(dev, PCIR_BAR(i))) { 3993 i++; 3994 continue; 3995 } 3996 3997 /* 3998 * Skip quirked resources. 3999 */ 4000 for (q = &pci_quirks[0]; q->devid != 0; q++) 4001 if (q->devid == devid && 4002 q->type == PCI_QUIRK_UNMAP_REG && 4003 q->arg1 == PCIR_BAR(i)) 4004 break; 4005 if (q->devid != 0) { 4006 i++; 4007 continue; 4008 } 4009 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force, 4010 prefetchmask & (1 << i)); 4011 } 4012 4013 /* 4014 * Add additional, quirked resources. 4015 */ 4016 for (q = &pci_quirks[0]; q->devid != 0; q++) 4017 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) 4018 pci_add_map(bus, dev, q->arg1, rl, force, 0); 4019 4020 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 4021 #ifdef __PCI_REROUTE_INTERRUPT 4022 /* 4023 * Try to re-route interrupts. Sometimes the BIOS or 4024 * firmware may leave bogus values in these registers. 4025 * If the re-route fails, then just stick with what we 4026 * have. 4027 */ 4028 pci_assign_interrupt(bus, dev, 1); 4029 #else 4030 pci_assign_interrupt(bus, dev, 0); 4031 #endif 4032 } 4033 4034 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS && 4035 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) { 4036 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI) 4037 xhci_early_takeover(dev); 4038 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI) 4039 ehci_early_takeover(dev); 4040 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI) 4041 ohci_early_takeover(dev); 4042 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI) 4043 uhci_early_takeover(dev); 4044 } 4045 4046 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 4047 /* 4048 * Reserve resources for secondary bus ranges behind bridge 4049 * devices. 4050 */ 4051 pci_reserve_secbus(bus, dev, cfg, rl); 4052 #endif 4053 } 4054 4055 static struct pci_devinfo * 4056 pci_identify_function(device_t pcib, device_t dev, int domain, int busno, 4057 int slot, int func) 4058 { 4059 struct pci_devinfo *dinfo; 4060 4061 dinfo = pci_read_device(pcib, dev, domain, busno, slot, func); 4062 if (dinfo != NULL) 4063 pci_add_child(dev, dinfo); 4064 4065 return (dinfo); 4066 } 4067 4068 void 4069 pci_add_children(device_t dev, int domain, int busno) 4070 { 4071 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4072 device_t pcib = device_get_parent(dev); 4073 struct pci_devinfo *dinfo; 4074 int maxslots; 4075 int s, f, pcifunchigh; 4076 uint8_t hdrtype; 4077 int first_func; 4078 4079 /* 4080 * Try to detect a device at slot 0, function 0. If it exists, try to 4081 * enable ARI. We must enable ARI before detecting the rest of the 4082 * functions on this bus as ARI changes the set of slots and functions 4083 * that are legal on this bus. 4084 */ 4085 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0); 4086 if (dinfo != NULL && pci_enable_ari) 4087 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); 4088 4089 /* 4090 * Start looking for new devices on slot 0 at function 1 because we 4091 * just identified the device at slot 0, function 0. 4092 */ 4093 first_func = 1; 4094 4095 maxslots = PCIB_MAXSLOTS(pcib); 4096 for (s = 0; s <= maxslots; s++, first_func = 0) { 4097 pcifunchigh = 0; 4098 f = 0; 4099 DELAY(1); 4100 hdrtype = REG(PCIR_HDRTYPE, 1); 4101 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4102 continue; 4103 if (hdrtype & PCIM_MFDEV) 4104 pcifunchigh = PCIB_MAXFUNCS(pcib); 4105 for (f = first_func; f <= pcifunchigh; f++) 4106 pci_identify_function(pcib, dev, domain, busno, s, f); 4107 } 4108 #undef REG 4109 } 4110 4111 int 4112 pci_rescan_method(device_t dev) 4113 { 4114 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4115 device_t pcib = device_get_parent(dev); 4116 device_t child, *devlist, *unchanged; 4117 int devcount, error, i, j, maxslots, oldcount; 4118 int busno, domain, s, f, pcifunchigh; 4119 uint8_t hdrtype; 4120 4121 /* No need to check for ARI on a rescan. */ 4122 error = device_get_children(dev, &devlist, &devcount); 4123 if (error) 4124 return (error); 4125 if (devcount != 0) { 4126 unchanged = malloc(devcount * sizeof(device_t), M_TEMP, 4127 M_NOWAIT | M_ZERO); 4128 if (unchanged == NULL) { 4129 free(devlist, M_TEMP); 4130 return (ENOMEM); 4131 } 4132 } else 4133 unchanged = NULL; 4134 4135 domain = pcib_get_domain(dev); 4136 busno = pcib_get_bus(dev); 4137 maxslots = PCIB_MAXSLOTS(pcib); 4138 for (s = 0; s <= maxslots; s++) { 4139 /* If function 0 is not present, skip to the next slot. */ 4140 f = 0; 4141 if (REG(PCIR_VENDOR, 2) == 0xffff) 4142 continue; 4143 pcifunchigh = 0; 4144 hdrtype = REG(PCIR_HDRTYPE, 1); 4145 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4146 continue; 4147 if (hdrtype & PCIM_MFDEV) 4148 pcifunchigh = PCIB_MAXFUNCS(pcib); 4149 for (f = 0; f <= pcifunchigh; f++) { 4150 if (REG(PCIR_VENDOR, 2) == 0xffff) 4151 continue; 4152 4153 /* 4154 * Found a valid function. Check if a 4155 * device_t for this device already exists. 4156 */ 4157 for (i = 0; i < devcount; i++) { 4158 child = devlist[i]; 4159 if (child == NULL) 4160 continue; 4161 if (pci_get_slot(child) == s && 4162 pci_get_function(child) == f) { 4163 unchanged[i] = child; 4164 goto next_func; 4165 } 4166 } 4167 4168 pci_identify_function(pcib, dev, domain, busno, s, f); 4169 next_func:; 4170 } 4171 } 4172 4173 /* Remove devices that are no longer present. */ 4174 for (i = 0; i < devcount; i++) { 4175 if (unchanged[i] != NULL) 4176 continue; 4177 device_delete_child(dev, devlist[i]); 4178 } 4179 4180 free(devlist, M_TEMP); 4181 oldcount = devcount; 4182 4183 /* Try to attach the devices just added. */ 4184 error = device_get_children(dev, &devlist, &devcount); 4185 if (error) { 4186 free(unchanged, M_TEMP); 4187 return (error); 4188 } 4189 4190 for (i = 0; i < devcount; i++) { 4191 for (j = 0; j < oldcount; j++) { 4192 if (devlist[i] == unchanged[j]) 4193 goto next_device; 4194 } 4195 4196 device_probe_and_attach(devlist[i]); 4197 next_device:; 4198 } 4199 4200 free(unchanged, M_TEMP); 4201 free(devlist, M_TEMP); 4202 return (0); 4203 #undef REG 4204 } 4205 4206 #ifdef PCI_IOV 4207 device_t 4208 pci_add_iov_child(device_t bus, device_t pf, uint16_t rid, uint16_t vid, 4209 uint16_t did) 4210 { 4211 struct pci_devinfo *vf_dinfo; 4212 device_t pcib; 4213 int busno, slot, func; 4214 4215 pcib = device_get_parent(bus); 4216 4217 PCIB_DECODE_RID(pcib, rid, &busno, &slot, &func); 4218 4219 vf_dinfo = pci_fill_devinfo(pcib, bus, pci_get_domain(pcib), busno, 4220 slot, func, vid, did); 4221 4222 vf_dinfo->cfg.flags |= PCICFG_VF; 4223 pci_add_child(bus, vf_dinfo); 4224 4225 return (vf_dinfo->cfg.dev); 4226 } 4227 4228 device_t 4229 pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid, 4230 uint16_t vid, uint16_t did) 4231 { 4232 4233 return (pci_add_iov_child(bus, pf, rid, vid, did)); 4234 } 4235 #endif 4236 4237 static void 4238 pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo) 4239 { 4240 int aer; 4241 uint32_t r; 4242 uint16_t r2; 4243 4244 if (dinfo->cfg.pcie.pcie_location != 0 && 4245 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) { 4246 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4247 PCIER_ROOT_CTL, 2); 4248 r2 &= ~(PCIEM_ROOT_CTL_SERR_CORR | 4249 PCIEM_ROOT_CTL_SERR_NONFATAL | PCIEM_ROOT_CTL_SERR_FATAL); 4250 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4251 PCIER_ROOT_CTL, r2, 2); 4252 } 4253 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 4254 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 4255 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 4256 if (r != 0 && bootverbose) { 4257 pci_printf(&dinfo->cfg, 4258 "clearing AER UC 0x%08x -> 0x%08x\n", 4259 r, pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4260 4)); 4261 } 4262 4263 r = pci_read_config(dev, aer + PCIR_AER_UC_MASK, 4); 4264 r &= ~(PCIM_AER_UC_TRAINING_ERROR | 4265 PCIM_AER_UC_DL_PROTOCOL_ERROR | 4266 PCIM_AER_UC_SURPRISE_LINK_DOWN | 4267 PCIM_AER_UC_POISONED_TLP | 4268 PCIM_AER_UC_FC_PROTOCOL_ERROR | 4269 PCIM_AER_UC_COMPLETION_TIMEOUT | 4270 PCIM_AER_UC_COMPLETER_ABORT | 4271 PCIM_AER_UC_UNEXPECTED_COMPLETION | 4272 PCIM_AER_UC_RECEIVER_OVERFLOW | 4273 PCIM_AER_UC_MALFORMED_TLP | 4274 PCIM_AER_UC_ECRC_ERROR | 4275 PCIM_AER_UC_UNSUPPORTED_REQUEST | 4276 PCIM_AER_UC_ACS_VIOLATION | 4277 PCIM_AER_UC_INTERNAL_ERROR | 4278 PCIM_AER_UC_MC_BLOCKED_TLP | 4279 PCIM_AER_UC_ATOMIC_EGRESS_BLK | 4280 PCIM_AER_UC_TLP_PREFIX_BLOCKED); 4281 pci_write_config(dev, aer + PCIR_AER_UC_MASK, r, 4); 4282 4283 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 4284 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 4285 if (r != 0 && bootverbose) { 4286 pci_printf(&dinfo->cfg, 4287 "clearing AER COR 0x%08x -> 0x%08x\n", 4288 r, pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4289 4)); 4290 } 4291 4292 r = pci_read_config(dev, aer + PCIR_AER_COR_MASK, 4); 4293 r &= ~(PCIM_AER_COR_RECEIVER_ERROR | 4294 PCIM_AER_COR_BAD_TLP | 4295 PCIM_AER_COR_BAD_DLLP | 4296 PCIM_AER_COR_REPLAY_ROLLOVER | 4297 PCIM_AER_COR_REPLAY_TIMEOUT | 4298 PCIM_AER_COR_ADVISORY_NF_ERROR | 4299 PCIM_AER_COR_INTERNAL_ERROR | 4300 PCIM_AER_COR_HEADER_LOG_OVFLOW); 4301 pci_write_config(dev, aer + PCIR_AER_COR_MASK, r, 4); 4302 4303 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4304 PCIER_DEVICE_CTL, 2); 4305 r |= PCIEM_CTL_COR_ENABLE | PCIEM_CTL_NFER_ENABLE | 4306 PCIEM_CTL_FER_ENABLE | PCIEM_CTL_URR_ENABLE; 4307 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4308 PCIER_DEVICE_CTL, r, 2); 4309 } 4310 } 4311 4312 void 4313 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 4314 { 4315 device_t dev; 4316 4317 dinfo->cfg.dev = dev = device_add_child(bus, NULL, -1); 4318 device_set_ivars(dev, dinfo); 4319 resource_list_init(&dinfo->resources); 4320 pci_cfg_save(dev, dinfo, 0); 4321 pci_cfg_restore(dev, dinfo); 4322 pci_print_verbose(dinfo); 4323 pci_add_resources(bus, dev, 0, 0); 4324 pci_child_added(dinfo->cfg.dev); 4325 4326 if (pci_clear_aer_on_attach) 4327 pci_add_child_clear_aer(dev, dinfo); 4328 4329 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev); 4330 } 4331 4332 void 4333 pci_child_added_method(device_t dev, device_t child) 4334 { 4335 4336 } 4337 4338 static int 4339 pci_probe(device_t dev) 4340 { 4341 4342 device_set_desc(dev, "PCI bus"); 4343 4344 /* Allow other subclasses to override this driver. */ 4345 return (BUS_PROBE_GENERIC); 4346 } 4347 4348 int 4349 pci_attach_common(device_t dev) 4350 { 4351 struct pci_softc *sc; 4352 int busno, domain; 4353 #ifdef PCI_RES_BUS 4354 int rid; 4355 #endif 4356 4357 sc = device_get_softc(dev); 4358 domain = pcib_get_domain(dev); 4359 busno = pcib_get_bus(dev); 4360 #ifdef PCI_RES_BUS 4361 rid = 0; 4362 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, 4363 1, 0); 4364 if (sc->sc_bus == NULL) { 4365 device_printf(dev, "failed to allocate bus number\n"); 4366 return (ENXIO); 4367 } 4368 #endif 4369 if (bootverbose) 4370 device_printf(dev, "domain=%d, physical bus=%d\n", 4371 domain, busno); 4372 sc->sc_dma_tag = bus_get_dma_tag(dev); 4373 return (0); 4374 } 4375 4376 static int 4377 pci_attach(device_t dev) 4378 { 4379 int busno, domain, error; 4380 4381 error = pci_attach_common(dev); 4382 if (error) 4383 return (error); 4384 4385 /* 4386 * Since there can be multiple independently numbered PCI 4387 * buses on systems with multiple PCI domains, we can't use 4388 * the unit number to decide which bus we are probing. We ask 4389 * the parent pcib what our domain and bus numbers are. 4390 */ 4391 domain = pcib_get_domain(dev); 4392 busno = pcib_get_bus(dev); 4393 pci_add_children(dev, domain, busno); 4394 return (bus_generic_attach(dev)); 4395 } 4396 4397 static int 4398 pci_detach(device_t dev) 4399 { 4400 #ifdef PCI_RES_BUS 4401 struct pci_softc *sc; 4402 #endif 4403 int error; 4404 4405 error = bus_generic_detach(dev); 4406 if (error) 4407 return (error); 4408 #ifdef PCI_RES_BUS 4409 sc = device_get_softc(dev); 4410 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus); 4411 if (error) 4412 return (error); 4413 #endif 4414 return (device_delete_children(dev)); 4415 } 4416 4417 static void 4418 pci_hint_device_unit(device_t dev, device_t child, const char *name, int *unitp) 4419 { 4420 int line, unit; 4421 const char *at; 4422 char me1[24], me2[32]; 4423 uint8_t b, s, f; 4424 uint32_t d; 4425 4426 d = pci_get_domain(child); 4427 b = pci_get_bus(child); 4428 s = pci_get_slot(child); 4429 f = pci_get_function(child); 4430 snprintf(me1, sizeof(me1), "pci%u:%u:%u", b, s, f); 4431 snprintf(me2, sizeof(me2), "pci%u:%u:%u:%u", d, b, s, f); 4432 line = 0; 4433 while (resource_find_dev(&line, name, &unit, "at", NULL) == 0) { 4434 resource_string_value(name, unit, "at", &at); 4435 if (strcmp(at, me1) != 0 && strcmp(at, me2) != 0) 4436 continue; /* No match, try next candidate */ 4437 *unitp = unit; 4438 return; 4439 } 4440 } 4441 4442 static void 4443 pci_set_power_child(device_t dev, device_t child, int state) 4444 { 4445 device_t pcib; 4446 int dstate; 4447 4448 /* 4449 * Set the device to the given state. If the firmware suggests 4450 * a different power state, use it instead. If power management 4451 * is not present, the firmware is responsible for managing 4452 * device power. Skip children who aren't attached since they 4453 * are handled separately. 4454 */ 4455 pcib = device_get_parent(dev); 4456 dstate = state; 4457 if (device_is_attached(child) && 4458 PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0) 4459 pci_set_powerstate(child, dstate); 4460 } 4461 4462 int 4463 pci_suspend_child(device_t dev, device_t child) 4464 { 4465 struct pci_devinfo *dinfo; 4466 struct resource_list_entry *rle; 4467 int error; 4468 4469 dinfo = device_get_ivars(child); 4470 4471 /* 4472 * Save the PCI configuration space for the child and set the 4473 * device in the appropriate power state for this sleep state. 4474 */ 4475 pci_cfg_save(child, dinfo, 0); 4476 4477 /* Suspend devices before potentially powering them down. */ 4478 error = bus_generic_suspend_child(dev, child); 4479 4480 if (error) 4481 return (error); 4482 4483 if (pci_do_power_suspend) { 4484 /* 4485 * Make sure this device's interrupt handler is not invoked 4486 * in the case the device uses a shared interrupt that can 4487 * be raised by some other device. 4488 * This is applicable only to regular (legacy) PCI interrupts 4489 * as MSI/MSI-X interrupts are never shared. 4490 */ 4491 rle = resource_list_find(&dinfo->resources, 4492 SYS_RES_IRQ, 0); 4493 if (rle != NULL && rle->res != NULL) 4494 (void)bus_suspend_intr(child, rle->res); 4495 pci_set_power_child(dev, child, PCI_POWERSTATE_D3); 4496 } 4497 4498 return (0); 4499 } 4500 4501 int 4502 pci_resume_child(device_t dev, device_t child) 4503 { 4504 struct pci_devinfo *dinfo; 4505 struct resource_list_entry *rle; 4506 4507 if (pci_do_power_resume) 4508 pci_set_power_child(dev, child, PCI_POWERSTATE_D0); 4509 4510 dinfo = device_get_ivars(child); 4511 pci_cfg_restore(child, dinfo); 4512 if (!device_is_attached(child)) 4513 pci_cfg_save(child, dinfo, 1); 4514 4515 bus_generic_resume_child(dev, child); 4516 4517 /* 4518 * Allow interrupts only after fully resuming the driver and hardware. 4519 */ 4520 if (pci_do_power_suspend) { 4521 /* See pci_suspend_child for details. */ 4522 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 4523 if (rle != NULL && rle->res != NULL) 4524 (void)bus_resume_intr(child, rle->res); 4525 } 4526 4527 return (0); 4528 } 4529 4530 int 4531 pci_resume(device_t dev) 4532 { 4533 device_t child, *devlist; 4534 int error, i, numdevs; 4535 4536 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 4537 return (error); 4538 4539 /* 4540 * Resume critical devices first, then everything else later. 4541 */ 4542 for (i = 0; i < numdevs; i++) { 4543 child = devlist[i]; 4544 switch (pci_get_class(child)) { 4545 case PCIC_DISPLAY: 4546 case PCIC_MEMORY: 4547 case PCIC_BRIDGE: 4548 case PCIC_BASEPERIPH: 4549 BUS_RESUME_CHILD(dev, child); 4550 break; 4551 } 4552 } 4553 for (i = 0; i < numdevs; i++) { 4554 child = devlist[i]; 4555 switch (pci_get_class(child)) { 4556 case PCIC_DISPLAY: 4557 case PCIC_MEMORY: 4558 case PCIC_BRIDGE: 4559 case PCIC_BASEPERIPH: 4560 break; 4561 default: 4562 BUS_RESUME_CHILD(dev, child); 4563 } 4564 } 4565 free(devlist, M_TEMP); 4566 return (0); 4567 } 4568 4569 static void 4570 pci_load_vendor_data(void) 4571 { 4572 caddr_t data; 4573 void *ptr; 4574 size_t sz; 4575 4576 data = preload_search_by_type("pci_vendor_data"); 4577 if (data != NULL) { 4578 ptr = preload_fetch_addr(data); 4579 sz = preload_fetch_size(data); 4580 if (ptr != NULL && sz != 0) { 4581 pci_vendordata = ptr; 4582 pci_vendordata_size = sz; 4583 /* terminate the database */ 4584 pci_vendordata[pci_vendordata_size] = '\n'; 4585 } 4586 } 4587 } 4588 4589 void 4590 pci_driver_added(device_t dev, driver_t *driver) 4591 { 4592 int numdevs; 4593 device_t *devlist; 4594 device_t child; 4595 struct pci_devinfo *dinfo; 4596 int i; 4597 4598 if (bootverbose) 4599 device_printf(dev, "driver added\n"); 4600 DEVICE_IDENTIFY(driver, dev); 4601 if (device_get_children(dev, &devlist, &numdevs) != 0) 4602 return; 4603 for (i = 0; i < numdevs; i++) { 4604 child = devlist[i]; 4605 if (device_get_state(child) != DS_NOTPRESENT) 4606 continue; 4607 dinfo = device_get_ivars(child); 4608 pci_print_verbose(dinfo); 4609 if (bootverbose) 4610 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); 4611 pci_cfg_restore(child, dinfo); 4612 if (device_probe_and_attach(child) != 0) 4613 pci_child_detached(dev, child); 4614 } 4615 free(devlist, M_TEMP); 4616 } 4617 4618 int 4619 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, 4620 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep) 4621 { 4622 struct pci_devinfo *dinfo; 4623 struct msix_table_entry *mte; 4624 struct msix_vector *mv; 4625 uint64_t addr; 4626 uint32_t data; 4627 void *cookie; 4628 int error, rid; 4629 4630 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr, 4631 arg, &cookie); 4632 if (error) 4633 return (error); 4634 4635 /* If this is not a direct child, just bail out. */ 4636 if (device_get_parent(child) != dev) { 4637 *cookiep = cookie; 4638 return(0); 4639 } 4640 4641 rid = rman_get_rid(irq); 4642 if (rid == 0) { 4643 /* Make sure that INTx is enabled */ 4644 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4645 } else { 4646 /* 4647 * Check to see if the interrupt is MSI or MSI-X. 4648 * Ask our parent to map the MSI and give 4649 * us the address and data register values. 4650 * If we fail for some reason, teardown the 4651 * interrupt handler. 4652 */ 4653 dinfo = device_get_ivars(child); 4654 if (dinfo->cfg.msi.msi_alloc > 0) { 4655 if (dinfo->cfg.msi.msi_addr == 0) { 4656 KASSERT(dinfo->cfg.msi.msi_handlers == 0, 4657 ("MSI has handlers, but vectors not mapped")); 4658 error = PCIB_MAP_MSI(device_get_parent(dev), 4659 child, rman_get_start(irq), &addr, &data); 4660 if (error) 4661 goto bad; 4662 dinfo->cfg.msi.msi_addr = addr; 4663 dinfo->cfg.msi.msi_data = data; 4664 } 4665 if (dinfo->cfg.msi.msi_handlers == 0) 4666 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, 4667 dinfo->cfg.msi.msi_data); 4668 dinfo->cfg.msi.msi_handlers++; 4669 } else { 4670 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4671 ("No MSI or MSI-X interrupts allocated")); 4672 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4673 ("MSI-X index too high")); 4674 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4675 KASSERT(mte->mte_vector != 0, ("no message vector")); 4676 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; 4677 KASSERT(mv->mv_irq == rman_get_start(irq), 4678 ("IRQ mismatch")); 4679 if (mv->mv_address == 0) { 4680 KASSERT(mte->mte_handlers == 0, 4681 ("MSI-X table entry has handlers, but vector not mapped")); 4682 error = PCIB_MAP_MSI(device_get_parent(dev), 4683 child, rman_get_start(irq), &addr, &data); 4684 if (error) 4685 goto bad; 4686 mv->mv_address = addr; 4687 mv->mv_data = data; 4688 } 4689 4690 /* 4691 * The MSIX table entry must be made valid by 4692 * incrementing the mte_handlers before 4693 * calling pci_enable_msix() and 4694 * pci_resume_msix(). Else the MSIX rewrite 4695 * table quirk will not work as expected. 4696 */ 4697 mte->mte_handlers++; 4698 if (mte->mte_handlers == 1) { 4699 pci_enable_msix(child, rid - 1, mv->mv_address, 4700 mv->mv_data); 4701 pci_unmask_msix(child, rid - 1); 4702 } 4703 } 4704 4705 /* 4706 * Make sure that INTx is disabled if we are using MSI/MSI-X, 4707 * unless the device is affected by PCI_QUIRK_MSI_INTX_BUG, 4708 * in which case we "enable" INTx so MSI/MSI-X actually works. 4709 */ 4710 if (!pci_has_quirk(pci_get_devid(child), 4711 PCI_QUIRK_MSI_INTX_BUG)) 4712 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4713 else 4714 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4715 bad: 4716 if (error) { 4717 (void)bus_generic_teardown_intr(dev, child, irq, 4718 cookie); 4719 return (error); 4720 } 4721 } 4722 *cookiep = cookie; 4723 return (0); 4724 } 4725 4726 int 4727 pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 4728 void *cookie) 4729 { 4730 struct msix_table_entry *mte; 4731 struct resource_list_entry *rle; 4732 struct pci_devinfo *dinfo; 4733 int error, rid; 4734 4735 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE)) 4736 return (EINVAL); 4737 4738 /* If this isn't a direct child, just bail out */ 4739 if (device_get_parent(child) != dev) 4740 return(bus_generic_teardown_intr(dev, child, irq, cookie)); 4741 4742 rid = rman_get_rid(irq); 4743 if (rid == 0) { 4744 /* Mask INTx */ 4745 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4746 } else { 4747 /* 4748 * Check to see if the interrupt is MSI or MSI-X. If so, 4749 * decrement the appropriate handlers count and mask the 4750 * MSI-X message, or disable MSI messages if the count 4751 * drops to 0. 4752 */ 4753 dinfo = device_get_ivars(child); 4754 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); 4755 if (rle->res != irq) 4756 return (EINVAL); 4757 if (dinfo->cfg.msi.msi_alloc > 0) { 4758 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, 4759 ("MSI-X index too high")); 4760 if (dinfo->cfg.msi.msi_handlers == 0) 4761 return (EINVAL); 4762 dinfo->cfg.msi.msi_handlers--; 4763 if (dinfo->cfg.msi.msi_handlers == 0) 4764 pci_disable_msi(child); 4765 } else { 4766 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4767 ("No MSI or MSI-X interrupts allocated")); 4768 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4769 ("MSI-X index too high")); 4770 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4771 if (mte->mte_handlers == 0) 4772 return (EINVAL); 4773 mte->mte_handlers--; 4774 if (mte->mte_handlers == 0) 4775 pci_mask_msix(child, rid - 1); 4776 } 4777 } 4778 error = bus_generic_teardown_intr(dev, child, irq, cookie); 4779 if (rid > 0) 4780 KASSERT(error == 0, 4781 ("%s: generic teardown failed for MSI/MSI-X", __func__)); 4782 return (error); 4783 } 4784 4785 int 4786 pci_print_child(device_t dev, device_t child) 4787 { 4788 struct pci_devinfo *dinfo; 4789 struct resource_list *rl; 4790 int retval = 0; 4791 4792 dinfo = device_get_ivars(child); 4793 rl = &dinfo->resources; 4794 4795 retval += bus_print_child_header(dev, child); 4796 4797 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#jx"); 4798 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 4799 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 4800 if (device_get_flags(dev)) 4801 retval += printf(" flags %#x", device_get_flags(dev)); 4802 4803 retval += printf(" at device %d.%d", pci_get_slot(child), 4804 pci_get_function(child)); 4805 4806 retval += bus_print_child_domain(dev, child); 4807 retval += bus_print_child_footer(dev, child); 4808 4809 return (retval); 4810 } 4811 4812 static const struct 4813 { 4814 int class; 4815 int subclass; 4816 int report; /* 0 = bootverbose, 1 = always */ 4817 const char *desc; 4818 } pci_nomatch_tab[] = { 4819 {PCIC_OLD, -1, 1, "old"}, 4820 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"}, 4821 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"}, 4822 {PCIC_STORAGE, -1, 1, "mass storage"}, 4823 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"}, 4824 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"}, 4825 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"}, 4826 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"}, 4827 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"}, 4828 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"}, 4829 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"}, 4830 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"}, 4831 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"}, 4832 {PCIC_NETWORK, -1, 1, "network"}, 4833 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"}, 4834 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"}, 4835 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"}, 4836 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"}, 4837 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"}, 4838 {PCIC_DISPLAY, -1, 1, "display"}, 4839 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"}, 4840 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"}, 4841 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"}, 4842 {PCIC_MULTIMEDIA, -1, 1, "multimedia"}, 4843 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"}, 4844 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"}, 4845 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"}, 4846 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"}, 4847 {PCIC_MEMORY, -1, 1, "memory"}, 4848 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"}, 4849 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"}, 4850 {PCIC_BRIDGE, -1, 1, "bridge"}, 4851 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"}, 4852 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"}, 4853 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"}, 4854 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"}, 4855 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"}, 4856 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"}, 4857 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"}, 4858 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"}, 4859 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"}, 4860 {PCIC_SIMPLECOMM, -1, 1, "simple comms"}, 4861 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */ 4862 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"}, 4863 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"}, 4864 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"}, 4865 {PCIC_BASEPERIPH, -1, 0, "base peripheral"}, 4866 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"}, 4867 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"}, 4868 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"}, 4869 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"}, 4870 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"}, 4871 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"}, 4872 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"}, 4873 {PCIC_INPUTDEV, -1, 1, "input device"}, 4874 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"}, 4875 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"}, 4876 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"}, 4877 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"}, 4878 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"}, 4879 {PCIC_DOCKING, -1, 1, "docking station"}, 4880 {PCIC_PROCESSOR, -1, 1, "processor"}, 4881 {PCIC_SERIALBUS, -1, 1, "serial bus"}, 4882 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"}, 4883 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"}, 4884 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"}, 4885 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"}, 4886 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"}, 4887 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"}, 4888 {PCIC_WIRELESS, -1, 1, "wireless controller"}, 4889 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"}, 4890 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"}, 4891 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"}, 4892 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"}, 4893 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"}, 4894 {PCIC_SATCOM, -1, 1, "satellite communication"}, 4895 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"}, 4896 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"}, 4897 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"}, 4898 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"}, 4899 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"}, 4900 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"}, 4901 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"}, 4902 {PCIC_DASP, -1, 0, "dasp"}, 4903 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"}, 4904 {PCIC_DASP, PCIS_DASP_PERFCNTRS, 1, "performance counters"}, 4905 {PCIC_DASP, PCIS_DASP_COMM_SYNC, 1, "communication synchronizer"}, 4906 {PCIC_DASP, PCIS_DASP_MGMT_CARD, 1, "signal processing management"}, 4907 {0, 0, 0, NULL} 4908 }; 4909 4910 void 4911 pci_probe_nomatch(device_t dev, device_t child) 4912 { 4913 int i, report; 4914 const char *cp, *scp; 4915 char *device; 4916 4917 /* 4918 * Look for a listing for this device in a loaded device database. 4919 */ 4920 report = 1; 4921 if ((device = pci_describe_device(child)) != NULL) { 4922 device_printf(dev, "<%s>", device); 4923 free(device, M_DEVBUF); 4924 } else { 4925 /* 4926 * Scan the class/subclass descriptions for a general 4927 * description. 4928 */ 4929 cp = "unknown"; 4930 scp = NULL; 4931 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 4932 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 4933 if (pci_nomatch_tab[i].subclass == -1) { 4934 cp = pci_nomatch_tab[i].desc; 4935 report = pci_nomatch_tab[i].report; 4936 } else if (pci_nomatch_tab[i].subclass == 4937 pci_get_subclass(child)) { 4938 scp = pci_nomatch_tab[i].desc; 4939 report = pci_nomatch_tab[i].report; 4940 } 4941 } 4942 } 4943 if (report || bootverbose) { 4944 device_printf(dev, "<%s%s%s>", 4945 cp ? cp : "", 4946 ((cp != NULL) && (scp != NULL)) ? ", " : "", 4947 scp ? scp : ""); 4948 } 4949 } 4950 if (report || bootverbose) { 4951 printf(" at device %d.%d (no driver attached)\n", 4952 pci_get_slot(child), pci_get_function(child)); 4953 } 4954 pci_cfg_save(child, device_get_ivars(child), 1); 4955 } 4956 4957 void 4958 pci_child_detached(device_t dev, device_t child) 4959 { 4960 struct pci_devinfo *dinfo; 4961 struct resource_list *rl; 4962 4963 dinfo = device_get_ivars(child); 4964 rl = &dinfo->resources; 4965 4966 /* 4967 * Have to deallocate IRQs before releasing any MSI messages and 4968 * have to release MSI messages before deallocating any memory 4969 * BARs. 4970 */ 4971 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0) 4972 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); 4973 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { 4974 pci_printf(&dinfo->cfg, "Device leaked MSI vectors\n"); 4975 (void)pci_release_msi(child); 4976 } 4977 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0) 4978 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); 4979 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0) 4980 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); 4981 #ifdef PCI_RES_BUS 4982 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0) 4983 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); 4984 #endif 4985 4986 pci_cfg_save(child, dinfo, 1); 4987 } 4988 4989 /* 4990 * Parse the PCI device database, if loaded, and return a pointer to a 4991 * description of the device. 4992 * 4993 * The database is flat text formatted as follows: 4994 * 4995 * Any line not in a valid format is ignored. 4996 * Lines are terminated with newline '\n' characters. 4997 * 4998 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 4999 * the vendor name. 5000 * 5001 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 5002 * - devices cannot be listed without a corresponding VENDOR line. 5003 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 5004 * another TAB, then the device name. 5005 */ 5006 5007 /* 5008 * Assuming (ptr) points to the beginning of a line in the database, 5009 * return the vendor or device and description of the next entry. 5010 * The value of (vendor) or (device) inappropriate for the entry type 5011 * is set to -1. Returns nonzero at the end of the database. 5012 * 5013 * Note that this is slightly unrobust in the face of corrupt data; 5014 * we attempt to safeguard against this by spamming the end of the 5015 * database with a newline when we initialise. 5016 */ 5017 static int 5018 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 5019 { 5020 char *cp = *ptr; 5021 int left; 5022 5023 *device = -1; 5024 *vendor = -1; 5025 **desc = '\0'; 5026 for (;;) { 5027 left = pci_vendordata_size - (cp - pci_vendordata); 5028 if (left <= 0) { 5029 *ptr = cp; 5030 return(1); 5031 } 5032 5033 /* vendor entry? */ 5034 if (*cp != '\t' && 5035 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 5036 break; 5037 /* device entry? */ 5038 if (*cp == '\t' && 5039 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 5040 break; 5041 5042 /* skip to next line */ 5043 while (*cp != '\n' && left > 0) { 5044 cp++; 5045 left--; 5046 } 5047 if (*cp == '\n') { 5048 cp++; 5049 left--; 5050 } 5051 } 5052 /* skip to next line */ 5053 while (*cp != '\n' && left > 0) { 5054 cp++; 5055 left--; 5056 } 5057 if (*cp == '\n' && left > 0) 5058 cp++; 5059 *ptr = cp; 5060 return(0); 5061 } 5062 5063 static char * 5064 pci_describe_device(device_t dev) 5065 { 5066 int vendor, device; 5067 char *desc, *vp, *dp, *line; 5068 5069 desc = vp = dp = NULL; 5070 5071 /* 5072 * If we have no vendor data, we can't do anything. 5073 */ 5074 if (pci_vendordata == NULL) 5075 goto out; 5076 5077 /* 5078 * Scan the vendor data looking for this device 5079 */ 5080 line = pci_vendordata; 5081 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5082 goto out; 5083 for (;;) { 5084 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 5085 goto out; 5086 if (vendor == pci_get_vendor(dev)) 5087 break; 5088 } 5089 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5090 goto out; 5091 for (;;) { 5092 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 5093 *dp = 0; 5094 break; 5095 } 5096 if (vendor != -1) { 5097 *dp = 0; 5098 break; 5099 } 5100 if (device == pci_get_device(dev)) 5101 break; 5102 } 5103 if (dp[0] == '\0') 5104 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 5105 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 5106 NULL) 5107 sprintf(desc, "%s, %s", vp, dp); 5108 out: 5109 if (vp != NULL) 5110 free(vp, M_DEVBUF); 5111 if (dp != NULL) 5112 free(dp, M_DEVBUF); 5113 return(desc); 5114 } 5115 5116 int 5117 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 5118 { 5119 struct pci_devinfo *dinfo; 5120 pcicfgregs *cfg; 5121 5122 dinfo = device_get_ivars(child); 5123 cfg = &dinfo->cfg; 5124 5125 switch (which) { 5126 case PCI_IVAR_ETHADDR: 5127 /* 5128 * The generic accessor doesn't deal with failure, so 5129 * we set the return value, then return an error. 5130 */ 5131 *((uint8_t **) result) = NULL; 5132 return (EINVAL); 5133 case PCI_IVAR_SUBVENDOR: 5134 *result = cfg->subvendor; 5135 break; 5136 case PCI_IVAR_SUBDEVICE: 5137 *result = cfg->subdevice; 5138 break; 5139 case PCI_IVAR_VENDOR: 5140 *result = cfg->vendor; 5141 break; 5142 case PCI_IVAR_DEVICE: 5143 *result = cfg->device; 5144 break; 5145 case PCI_IVAR_DEVID: 5146 *result = (cfg->device << 16) | cfg->vendor; 5147 break; 5148 case PCI_IVAR_CLASS: 5149 *result = cfg->baseclass; 5150 break; 5151 case PCI_IVAR_SUBCLASS: 5152 *result = cfg->subclass; 5153 break; 5154 case PCI_IVAR_PROGIF: 5155 *result = cfg->progif; 5156 break; 5157 case PCI_IVAR_REVID: 5158 *result = cfg->revid; 5159 break; 5160 case PCI_IVAR_INTPIN: 5161 *result = cfg->intpin; 5162 break; 5163 case PCI_IVAR_IRQ: 5164 *result = cfg->intline; 5165 break; 5166 case PCI_IVAR_DOMAIN: 5167 *result = cfg->domain; 5168 break; 5169 case PCI_IVAR_BUS: 5170 *result = cfg->bus; 5171 break; 5172 case PCI_IVAR_SLOT: 5173 *result = cfg->slot; 5174 break; 5175 case PCI_IVAR_FUNCTION: 5176 *result = cfg->func; 5177 break; 5178 case PCI_IVAR_CMDREG: 5179 *result = cfg->cmdreg; 5180 break; 5181 case PCI_IVAR_CACHELNSZ: 5182 *result = cfg->cachelnsz; 5183 break; 5184 case PCI_IVAR_MINGNT: 5185 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5186 *result = -1; 5187 return (EINVAL); 5188 } 5189 *result = cfg->mingnt; 5190 break; 5191 case PCI_IVAR_MAXLAT: 5192 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5193 *result = -1; 5194 return (EINVAL); 5195 } 5196 *result = cfg->maxlat; 5197 break; 5198 case PCI_IVAR_LATTIMER: 5199 *result = cfg->lattimer; 5200 break; 5201 default: 5202 return (ENOENT); 5203 } 5204 return (0); 5205 } 5206 5207 int 5208 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 5209 { 5210 struct pci_devinfo *dinfo; 5211 5212 dinfo = device_get_ivars(child); 5213 5214 switch (which) { 5215 case PCI_IVAR_INTPIN: 5216 dinfo->cfg.intpin = value; 5217 return (0); 5218 case PCI_IVAR_ETHADDR: 5219 case PCI_IVAR_SUBVENDOR: 5220 case PCI_IVAR_SUBDEVICE: 5221 case PCI_IVAR_VENDOR: 5222 case PCI_IVAR_DEVICE: 5223 case PCI_IVAR_DEVID: 5224 case PCI_IVAR_CLASS: 5225 case PCI_IVAR_SUBCLASS: 5226 case PCI_IVAR_PROGIF: 5227 case PCI_IVAR_REVID: 5228 case PCI_IVAR_IRQ: 5229 case PCI_IVAR_DOMAIN: 5230 case PCI_IVAR_BUS: 5231 case PCI_IVAR_SLOT: 5232 case PCI_IVAR_FUNCTION: 5233 return (EINVAL); /* disallow for now */ 5234 5235 default: 5236 return (ENOENT); 5237 } 5238 } 5239 5240 #include "opt_ddb.h" 5241 #ifdef DDB 5242 #include <ddb/ddb.h> 5243 #include <sys/cons.h> 5244 5245 /* 5246 * List resources based on pci map registers, used for within ddb 5247 */ 5248 5249 DB_SHOW_COMMAND(pciregs, db_pci_dump) 5250 { 5251 struct pci_devinfo *dinfo; 5252 struct devlist *devlist_head; 5253 struct pci_conf *p; 5254 const char *name; 5255 int i, error, none_count; 5256 5257 none_count = 0; 5258 /* get the head of the device queue */ 5259 devlist_head = &pci_devq; 5260 5261 /* 5262 * Go through the list of devices and print out devices 5263 */ 5264 for (error = 0, i = 0, 5265 dinfo = STAILQ_FIRST(devlist_head); 5266 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 5267 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 5268 5269 /* Populate pd_name and pd_unit */ 5270 name = NULL; 5271 if (dinfo->cfg.dev) 5272 name = device_get_name(dinfo->cfg.dev); 5273 5274 p = &dinfo->conf; 5275 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x " 5276 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 5277 (name && *name) ? name : "none", 5278 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 5279 none_count++, 5280 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, 5281 p->pc_sel.pc_func, (p->pc_class << 16) | 5282 (p->pc_subclass << 8) | p->pc_progif, 5283 (p->pc_subdevice << 16) | p->pc_subvendor, 5284 (p->pc_device << 16) | p->pc_vendor, 5285 p->pc_revid, p->pc_hdr); 5286 } 5287 } 5288 #endif /* DDB */ 5289 5290 static struct resource * 5291 pci_reserve_map(device_t dev, device_t child, int type, int *rid, 5292 rman_res_t start, rman_res_t end, rman_res_t count, u_int num, 5293 u_int flags) 5294 { 5295 struct pci_devinfo *dinfo = device_get_ivars(child); 5296 struct resource_list *rl = &dinfo->resources; 5297 struct resource *res; 5298 struct pci_map *pm; 5299 uint16_t cmd; 5300 pci_addr_t map, testval; 5301 int mapsize; 5302 5303 res = NULL; 5304 5305 /* If rid is managed by EA, ignore it */ 5306 if (pci_ea_is_enabled(child, *rid)) 5307 goto out; 5308 5309 pm = pci_find_bar(child, *rid); 5310 if (pm != NULL) { 5311 /* This is a BAR that we failed to allocate earlier. */ 5312 mapsize = pm->pm_size; 5313 map = pm->pm_value; 5314 } else { 5315 /* 5316 * Weed out the bogons, and figure out how large the 5317 * BAR/map is. BARs that read back 0 here are bogus 5318 * and unimplemented. Note: atapci in legacy mode are 5319 * special and handled elsewhere in the code. If you 5320 * have a atapci device in legacy mode and it fails 5321 * here, that other code is broken. 5322 */ 5323 pci_read_bar(child, *rid, &map, &testval, NULL); 5324 5325 /* 5326 * Determine the size of the BAR and ignore BARs with a size 5327 * of 0. Device ROM BARs use a different mask value. 5328 */ 5329 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) 5330 mapsize = pci_romsize(testval); 5331 else 5332 mapsize = pci_mapsize(testval); 5333 if (mapsize == 0) 5334 goto out; 5335 pm = pci_add_bar(child, *rid, map, mapsize); 5336 } 5337 5338 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { 5339 if (type != SYS_RES_MEMORY) { 5340 if (bootverbose) 5341 device_printf(dev, 5342 "child %s requested type %d for rid %#x," 5343 " but the BAR says it is an memio\n", 5344 device_get_nameunit(child), type, *rid); 5345 goto out; 5346 } 5347 } else { 5348 if (type != SYS_RES_IOPORT) { 5349 if (bootverbose) 5350 device_printf(dev, 5351 "child %s requested type %d for rid %#x," 5352 " but the BAR says it is an ioport\n", 5353 device_get_nameunit(child), type, *rid); 5354 goto out; 5355 } 5356 } 5357 5358 /* 5359 * For real BARs, we need to override the size that 5360 * the driver requests, because that's what the BAR 5361 * actually uses and we would otherwise have a 5362 * situation where we might allocate the excess to 5363 * another driver, which won't work. 5364 */ 5365 count = ((pci_addr_t)1 << mapsize) * num; 5366 if (RF_ALIGNMENT(flags) < mapsize) 5367 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 5368 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH)) 5369 flags |= RF_PREFETCHABLE; 5370 5371 /* 5372 * Allocate enough resource, and then write back the 5373 * appropriate BAR for that resource. 5374 */ 5375 resource_list_add(rl, type, *rid, start, end, count); 5376 res = resource_list_reserve(rl, dev, child, type, rid, start, end, 5377 count, flags & ~RF_ACTIVE); 5378 if (res == NULL) { 5379 resource_list_delete(rl, type, *rid); 5380 device_printf(child, 5381 "%#jx bytes of rid %#x res %d failed (%#jx, %#jx).\n", 5382 count, *rid, type, start, end); 5383 goto out; 5384 } 5385 if (bootverbose) 5386 device_printf(child, 5387 "Lazy allocation of %#jx bytes rid %#x type %d at %#jx\n", 5388 count, *rid, type, rman_get_start(res)); 5389 5390 /* Disable decoding via the CMD register before updating the BAR */ 5391 cmd = pci_read_config(child, PCIR_COMMAND, 2); 5392 pci_write_config(child, PCIR_COMMAND, 5393 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 5394 5395 map = rman_get_start(res); 5396 pci_write_bar(child, pm, map); 5397 5398 /* Restore the original value of the CMD register */ 5399 pci_write_config(child, PCIR_COMMAND, cmd, 2); 5400 out: 5401 return (res); 5402 } 5403 5404 struct resource * 5405 pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid, 5406 rman_res_t start, rman_res_t end, rman_res_t count, u_long num, 5407 u_int flags) 5408 { 5409 struct pci_devinfo *dinfo; 5410 struct resource_list *rl; 5411 struct resource_list_entry *rle; 5412 struct resource *res; 5413 pcicfgregs *cfg; 5414 5415 /* 5416 * Perform lazy resource allocation 5417 */ 5418 dinfo = device_get_ivars(child); 5419 rl = &dinfo->resources; 5420 cfg = &dinfo->cfg; 5421 switch (type) { 5422 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 5423 case PCI_RES_BUS: 5424 return (pci_alloc_secbus(dev, child, rid, start, end, count, 5425 flags)); 5426 #endif 5427 case SYS_RES_IRQ: 5428 /* 5429 * Can't alloc legacy interrupt once MSI messages have 5430 * been allocated. 5431 */ 5432 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 5433 cfg->msix.msix_alloc > 0)) 5434 return (NULL); 5435 5436 /* 5437 * If the child device doesn't have an interrupt 5438 * routed and is deserving of an interrupt, try to 5439 * assign it one. 5440 */ 5441 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 5442 (cfg->intpin != 0)) 5443 pci_assign_interrupt(dev, child, 0); 5444 break; 5445 case SYS_RES_IOPORT: 5446 case SYS_RES_MEMORY: 5447 #ifdef NEW_PCIB 5448 /* 5449 * PCI-PCI bridge I/O window resources are not BARs. 5450 * For those allocations just pass the request up the 5451 * tree. 5452 */ 5453 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { 5454 switch (*rid) { 5455 case PCIR_IOBASEL_1: 5456 case PCIR_MEMBASE_1: 5457 case PCIR_PMBASEL_1: 5458 /* 5459 * XXX: Should we bother creating a resource 5460 * list entry? 5461 */ 5462 return (bus_generic_alloc_resource(dev, child, 5463 type, rid, start, end, count, flags)); 5464 } 5465 } 5466 #endif 5467 /* Reserve resources for this BAR if needed. */ 5468 rle = resource_list_find(rl, type, *rid); 5469 if (rle == NULL) { 5470 res = pci_reserve_map(dev, child, type, rid, start, end, 5471 count, num, flags); 5472 if (res == NULL) 5473 return (NULL); 5474 } 5475 } 5476 return (resource_list_alloc(rl, dev, child, type, rid, 5477 start, end, count, flags)); 5478 } 5479 5480 struct resource * 5481 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 5482 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 5483 { 5484 #ifdef PCI_IOV 5485 struct pci_devinfo *dinfo; 5486 #endif 5487 5488 if (device_get_parent(child) != dev) 5489 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 5490 type, rid, start, end, count, flags)); 5491 5492 #ifdef PCI_IOV 5493 dinfo = device_get_ivars(child); 5494 if (dinfo->cfg.flags & PCICFG_VF) { 5495 switch (type) { 5496 /* VFs can't have I/O BARs. */ 5497 case SYS_RES_IOPORT: 5498 return (NULL); 5499 case SYS_RES_MEMORY: 5500 return (pci_vf_alloc_mem_resource(dev, child, rid, 5501 start, end, count, flags)); 5502 } 5503 5504 /* Fall through for other types of resource allocations. */ 5505 } 5506 #endif 5507 5508 return (pci_alloc_multi_resource(dev, child, type, rid, start, end, 5509 count, 1, flags)); 5510 } 5511 5512 int 5513 pci_release_resource(device_t dev, device_t child, int type, int rid, 5514 struct resource *r) 5515 { 5516 struct pci_devinfo *dinfo; 5517 struct resource_list *rl; 5518 pcicfgregs *cfg; 5519 5520 if (device_get_parent(child) != dev) 5521 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 5522 type, rid, r)); 5523 5524 dinfo = device_get_ivars(child); 5525 cfg = &dinfo->cfg; 5526 5527 #ifdef PCI_IOV 5528 if (dinfo->cfg.flags & PCICFG_VF) { 5529 switch (type) { 5530 /* VFs can't have I/O BARs. */ 5531 case SYS_RES_IOPORT: 5532 return (EDOOFUS); 5533 case SYS_RES_MEMORY: 5534 return (pci_vf_release_mem_resource(dev, child, rid, 5535 r)); 5536 } 5537 5538 /* Fall through for other types of resource allocations. */ 5539 } 5540 #endif 5541 5542 #ifdef NEW_PCIB 5543 /* 5544 * PCI-PCI bridge I/O window resources are not BARs. For 5545 * those allocations just pass the request up the tree. 5546 */ 5547 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && 5548 (type == SYS_RES_IOPORT || type == SYS_RES_MEMORY)) { 5549 switch (rid) { 5550 case PCIR_IOBASEL_1: 5551 case PCIR_MEMBASE_1: 5552 case PCIR_PMBASEL_1: 5553 return (bus_generic_release_resource(dev, child, type, 5554 rid, r)); 5555 } 5556 } 5557 #endif 5558 5559 rl = &dinfo->resources; 5560 return (resource_list_release(rl, dev, child, type, rid, r)); 5561 } 5562 5563 int 5564 pci_activate_resource(device_t dev, device_t child, int type, int rid, 5565 struct resource *r) 5566 { 5567 struct pci_devinfo *dinfo; 5568 int error; 5569 5570 error = bus_generic_activate_resource(dev, child, type, rid, r); 5571 if (error) 5572 return (error); 5573 5574 /* Enable decoding in the command register when activating BARs. */ 5575 if (device_get_parent(child) == dev) { 5576 /* Device ROMs need their decoding explicitly enabled. */ 5577 dinfo = device_get_ivars(child); 5578 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5579 pci_write_bar(child, pci_find_bar(child, rid), 5580 rman_get_start(r) | PCIM_BIOS_ENABLE); 5581 switch (type) { 5582 case SYS_RES_IOPORT: 5583 case SYS_RES_MEMORY: 5584 error = PCI_ENABLE_IO(dev, child, type); 5585 break; 5586 } 5587 } 5588 return (error); 5589 } 5590 5591 int 5592 pci_deactivate_resource(device_t dev, device_t child, int type, 5593 int rid, struct resource *r) 5594 { 5595 struct pci_devinfo *dinfo; 5596 int error; 5597 5598 error = bus_generic_deactivate_resource(dev, child, type, rid, r); 5599 if (error) 5600 return (error); 5601 5602 /* Disable decoding for device ROMs. */ 5603 if (device_get_parent(child) == dev) { 5604 dinfo = device_get_ivars(child); 5605 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5606 pci_write_bar(child, pci_find_bar(child, rid), 5607 rman_get_start(r)); 5608 } 5609 return (0); 5610 } 5611 5612 void 5613 pci_child_deleted(device_t dev, device_t child) 5614 { 5615 struct resource_list_entry *rle; 5616 struct resource_list *rl; 5617 struct pci_devinfo *dinfo; 5618 5619 dinfo = device_get_ivars(child); 5620 rl = &dinfo->resources; 5621 5622 EVENTHANDLER_INVOKE(pci_delete_device, child); 5623 5624 /* Turn off access to resources we're about to free */ 5625 if (bus_child_present(child) != 0) { 5626 pci_write_config(child, PCIR_COMMAND, pci_read_config(child, 5627 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2); 5628 5629 pci_disable_busmaster(child); 5630 } 5631 5632 /* Free all allocated resources */ 5633 STAILQ_FOREACH(rle, rl, link) { 5634 if (rle->res) { 5635 if (rman_get_flags(rle->res) & RF_ACTIVE || 5636 resource_list_busy(rl, rle->type, rle->rid)) { 5637 pci_printf(&dinfo->cfg, 5638 "Resource still owned, oops. " 5639 "(type=%d, rid=%d, addr=%lx)\n", 5640 rle->type, rle->rid, 5641 rman_get_start(rle->res)); 5642 bus_release_resource(child, rle->type, rle->rid, 5643 rle->res); 5644 } 5645 resource_list_unreserve(rl, dev, child, rle->type, 5646 rle->rid); 5647 } 5648 } 5649 resource_list_free(rl); 5650 5651 pci_freecfg(dinfo); 5652 } 5653 5654 void 5655 pci_delete_resource(device_t dev, device_t child, int type, int rid) 5656 { 5657 struct pci_devinfo *dinfo; 5658 struct resource_list *rl; 5659 struct resource_list_entry *rle; 5660 5661 if (device_get_parent(child) != dev) 5662 return; 5663 5664 dinfo = device_get_ivars(child); 5665 rl = &dinfo->resources; 5666 rle = resource_list_find(rl, type, rid); 5667 if (rle == NULL) 5668 return; 5669 5670 if (rle->res) { 5671 if (rman_get_flags(rle->res) & RF_ACTIVE || 5672 resource_list_busy(rl, type, rid)) { 5673 device_printf(dev, "delete_resource: " 5674 "Resource still owned by child, oops. " 5675 "(type=%d, rid=%d, addr=%jx)\n", 5676 type, rid, rman_get_start(rle->res)); 5677 return; 5678 } 5679 resource_list_unreserve(rl, dev, child, type, rid); 5680 } 5681 resource_list_delete(rl, type, rid); 5682 } 5683 5684 struct resource_list * 5685 pci_get_resource_list (device_t dev, device_t child) 5686 { 5687 struct pci_devinfo *dinfo = device_get_ivars(child); 5688 5689 return (&dinfo->resources); 5690 } 5691 5692 #ifdef ACPI_DMAR 5693 bus_dma_tag_t dmar_get_dma_tag(device_t dev, device_t child); 5694 bus_dma_tag_t 5695 pci_get_dma_tag(device_t bus, device_t dev) 5696 { 5697 bus_dma_tag_t tag; 5698 struct pci_softc *sc; 5699 5700 if (device_get_parent(dev) == bus) { 5701 /* try dmar and return if it works */ 5702 tag = dmar_get_dma_tag(bus, dev); 5703 } else 5704 tag = NULL; 5705 if (tag == NULL) { 5706 sc = device_get_softc(bus); 5707 tag = sc->sc_dma_tag; 5708 } 5709 return (tag); 5710 } 5711 #else 5712 bus_dma_tag_t 5713 pci_get_dma_tag(device_t bus, device_t dev) 5714 { 5715 struct pci_softc *sc = device_get_softc(bus); 5716 5717 return (sc->sc_dma_tag); 5718 } 5719 #endif 5720 5721 uint32_t 5722 pci_read_config_method(device_t dev, device_t child, int reg, int width) 5723 { 5724 struct pci_devinfo *dinfo = device_get_ivars(child); 5725 pcicfgregs *cfg = &dinfo->cfg; 5726 5727 #ifdef PCI_IOV 5728 /* 5729 * SR-IOV VFs don't implement the VID or DID registers, so we have to 5730 * emulate them here. 5731 */ 5732 if (cfg->flags & PCICFG_VF) { 5733 if (reg == PCIR_VENDOR) { 5734 switch (width) { 5735 case 4: 5736 return (cfg->device << 16 | cfg->vendor); 5737 case 2: 5738 return (cfg->vendor); 5739 case 1: 5740 return (cfg->vendor & 0xff); 5741 default: 5742 return (0xffffffff); 5743 } 5744 } else if (reg == PCIR_DEVICE) { 5745 switch (width) { 5746 /* Note that an unaligned 4-byte read is an error. */ 5747 case 2: 5748 return (cfg->device); 5749 case 1: 5750 return (cfg->device & 0xff); 5751 default: 5752 return (0xffffffff); 5753 } 5754 } 5755 } 5756 #endif 5757 5758 return (PCIB_READ_CONFIG(device_get_parent(dev), 5759 cfg->bus, cfg->slot, cfg->func, reg, width)); 5760 } 5761 5762 void 5763 pci_write_config_method(device_t dev, device_t child, int reg, 5764 uint32_t val, int width) 5765 { 5766 struct pci_devinfo *dinfo = device_get_ivars(child); 5767 pcicfgregs *cfg = &dinfo->cfg; 5768 5769 PCIB_WRITE_CONFIG(device_get_parent(dev), 5770 cfg->bus, cfg->slot, cfg->func, reg, val, width); 5771 } 5772 5773 int 5774 pci_child_location_str_method(device_t dev, device_t child, char *buf, 5775 size_t buflen) 5776 { 5777 5778 snprintf(buf, buflen, "slot=%d function=%d dbsf=pci%d:%d:%d:%d", 5779 pci_get_slot(child), pci_get_function(child), pci_get_domain(child), 5780 pci_get_bus(child), pci_get_slot(child), pci_get_function(child)); 5781 return (0); 5782 } 5783 5784 int 5785 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 5786 size_t buflen) 5787 { 5788 struct pci_devinfo *dinfo; 5789 pcicfgregs *cfg; 5790 5791 dinfo = device_get_ivars(child); 5792 cfg = &dinfo->cfg; 5793 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 5794 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 5795 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 5796 cfg->progif); 5797 return (0); 5798 } 5799 5800 int 5801 pci_assign_interrupt_method(device_t dev, device_t child) 5802 { 5803 struct pci_devinfo *dinfo = device_get_ivars(child); 5804 pcicfgregs *cfg = &dinfo->cfg; 5805 5806 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 5807 cfg->intpin)); 5808 } 5809 5810 static void 5811 pci_lookup(void *arg, const char *name, device_t *dev) 5812 { 5813 long val; 5814 char *end; 5815 int domain, bus, slot, func; 5816 5817 if (*dev != NULL) 5818 return; 5819 5820 /* 5821 * Accept pciconf-style selectors of either pciD:B:S:F or 5822 * pciB:S:F. In the latter case, the domain is assumed to 5823 * be zero. 5824 */ 5825 if (strncmp(name, "pci", 3) != 0) 5826 return; 5827 val = strtol(name + 3, &end, 10); 5828 if (val < 0 || val > INT_MAX || *end != ':') 5829 return; 5830 domain = val; 5831 val = strtol(end + 1, &end, 10); 5832 if (val < 0 || val > INT_MAX || *end != ':') 5833 return; 5834 bus = val; 5835 val = strtol(end + 1, &end, 10); 5836 if (val < 0 || val > INT_MAX) 5837 return; 5838 slot = val; 5839 if (*end == ':') { 5840 val = strtol(end + 1, &end, 10); 5841 if (val < 0 || val > INT_MAX || *end != '\0') 5842 return; 5843 func = val; 5844 } else if (*end == '\0') { 5845 func = slot; 5846 slot = bus; 5847 bus = domain; 5848 domain = 0; 5849 } else 5850 return; 5851 5852 if (domain > PCI_DOMAINMAX || bus > PCI_BUSMAX || slot > PCI_SLOTMAX || 5853 func > PCIE_ARI_FUNCMAX || (slot != 0 && func > PCI_FUNCMAX)) 5854 return; 5855 5856 *dev = pci_find_dbsf(domain, bus, slot, func); 5857 } 5858 5859 static int 5860 pci_modevent(module_t mod, int what, void *arg) 5861 { 5862 static struct cdev *pci_cdev; 5863 static eventhandler_tag tag; 5864 5865 switch (what) { 5866 case MOD_LOAD: 5867 STAILQ_INIT(&pci_devq); 5868 pci_generation = 0; 5869 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 5870 "pci"); 5871 pci_load_vendor_data(); 5872 tag = EVENTHANDLER_REGISTER(dev_lookup, pci_lookup, NULL, 5873 1000); 5874 break; 5875 5876 case MOD_UNLOAD: 5877 if (tag != NULL) 5878 EVENTHANDLER_DEREGISTER(dev_lookup, tag); 5879 destroy_dev(pci_cdev); 5880 break; 5881 } 5882 5883 return (0); 5884 } 5885 5886 static void 5887 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo) 5888 { 5889 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2) 5890 struct pcicfg_pcie *cfg; 5891 int version, pos; 5892 5893 cfg = &dinfo->cfg.pcie; 5894 pos = cfg->pcie_location; 5895 5896 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 5897 5898 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); 5899 5900 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5901 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 5902 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 5903 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); 5904 5905 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5906 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 5907 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 5908 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); 5909 5910 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5911 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 5912 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); 5913 5914 if (version > 1) { 5915 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); 5916 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); 5917 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); 5918 } 5919 #undef WREG 5920 } 5921 5922 static void 5923 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo) 5924 { 5925 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 5926 dinfo->cfg.pcix.pcix_command, 2); 5927 } 5928 5929 void 5930 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 5931 { 5932 5933 /* 5934 * Restore the device to full power mode. We must do this 5935 * before we restore the registers because moving from D3 to 5936 * D0 will cause the chip's BARs and some other registers to 5937 * be reset to some unknown power on reset values. Cut down 5938 * the noise on boot by doing nothing if we are already in 5939 * state D0. 5940 */ 5941 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) 5942 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 5943 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 5944 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 5945 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 5946 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 5947 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 5948 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 5949 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 5950 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 5951 case PCIM_HDRTYPE_NORMAL: 5952 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 5953 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 5954 break; 5955 case PCIM_HDRTYPE_BRIDGE: 5956 pci_write_config(dev, PCIR_SECLAT_1, 5957 dinfo->cfg.bridge.br_seclat, 1); 5958 pci_write_config(dev, PCIR_SUBBUS_1, 5959 dinfo->cfg.bridge.br_subbus, 1); 5960 pci_write_config(dev, PCIR_SECBUS_1, 5961 dinfo->cfg.bridge.br_secbus, 1); 5962 pci_write_config(dev, PCIR_PRIBUS_1, 5963 dinfo->cfg.bridge.br_pribus, 1); 5964 pci_write_config(dev, PCIR_BRIDGECTL_1, 5965 dinfo->cfg.bridge.br_control, 2); 5966 break; 5967 case PCIM_HDRTYPE_CARDBUS: 5968 pci_write_config(dev, PCIR_SECLAT_2, 5969 dinfo->cfg.bridge.br_seclat, 1); 5970 pci_write_config(dev, PCIR_SUBBUS_2, 5971 dinfo->cfg.bridge.br_subbus, 1); 5972 pci_write_config(dev, PCIR_SECBUS_2, 5973 dinfo->cfg.bridge.br_secbus, 1); 5974 pci_write_config(dev, PCIR_PRIBUS_2, 5975 dinfo->cfg.bridge.br_pribus, 1); 5976 pci_write_config(dev, PCIR_BRIDGECTL_2, 5977 dinfo->cfg.bridge.br_control, 2); 5978 break; 5979 } 5980 pci_restore_bars(dev); 5981 5982 /* 5983 * Restore extended capabilities for PCI-Express and PCI-X 5984 */ 5985 if (dinfo->cfg.pcie.pcie_location != 0) 5986 pci_cfg_restore_pcie(dev, dinfo); 5987 if (dinfo->cfg.pcix.pcix_location != 0) 5988 pci_cfg_restore_pcix(dev, dinfo); 5989 5990 /* Restore MSI and MSI-X configurations if they are present. */ 5991 if (dinfo->cfg.msi.msi_location != 0) 5992 pci_resume_msi(dev); 5993 if (dinfo->cfg.msix.msix_location != 0) 5994 pci_resume_msix(dev); 5995 5996 #ifdef PCI_IOV 5997 if (dinfo->cfg.iov != NULL) 5998 pci_iov_cfg_restore(dev, dinfo); 5999 #endif 6000 } 6001 6002 static void 6003 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo) 6004 { 6005 #define RREG(n) pci_read_config(dev, pos + (n), 2) 6006 struct pcicfg_pcie *cfg; 6007 int version, pos; 6008 6009 cfg = &dinfo->cfg.pcie; 6010 pos = cfg->pcie_location; 6011 6012 cfg->pcie_flags = RREG(PCIER_FLAGS); 6013 6014 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6015 6016 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); 6017 6018 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6019 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6020 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6021 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); 6022 6023 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6024 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6025 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6026 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); 6027 6028 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6029 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6030 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); 6031 6032 if (version > 1) { 6033 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); 6034 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); 6035 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); 6036 } 6037 #undef RREG 6038 } 6039 6040 static void 6041 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo) 6042 { 6043 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, 6044 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); 6045 } 6046 6047 void 6048 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 6049 { 6050 uint32_t cls; 6051 int ps; 6052 6053 /* 6054 * Some drivers apparently write to these registers w/o updating our 6055 * cached copy. No harm happens if we update the copy, so do so here 6056 * so we can restore them. The COMMAND register is modified by the 6057 * bus w/o updating the cache. This should represent the normally 6058 * writable portion of the 'defined' part of type 0/1/2 headers. 6059 */ 6060 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 6061 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 6062 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 6063 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 6064 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 6065 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 6066 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 6067 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 6068 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 6069 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 6070 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 6071 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6072 case PCIM_HDRTYPE_NORMAL: 6073 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 6074 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 6075 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 6076 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 6077 break; 6078 case PCIM_HDRTYPE_BRIDGE: 6079 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6080 PCIR_SECLAT_1, 1); 6081 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6082 PCIR_SUBBUS_1, 1); 6083 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6084 PCIR_SECBUS_1, 1); 6085 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6086 PCIR_PRIBUS_1, 1); 6087 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6088 PCIR_BRIDGECTL_1, 2); 6089 break; 6090 case PCIM_HDRTYPE_CARDBUS: 6091 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6092 PCIR_SECLAT_2, 1); 6093 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6094 PCIR_SUBBUS_2, 1); 6095 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6096 PCIR_SECBUS_2, 1); 6097 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6098 PCIR_PRIBUS_2, 1); 6099 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6100 PCIR_BRIDGECTL_2, 2); 6101 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2); 6102 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2); 6103 break; 6104 } 6105 6106 if (dinfo->cfg.pcie.pcie_location != 0) 6107 pci_cfg_save_pcie(dev, dinfo); 6108 6109 if (dinfo->cfg.pcix.pcix_location != 0) 6110 pci_cfg_save_pcix(dev, dinfo); 6111 6112 #ifdef PCI_IOV 6113 if (dinfo->cfg.iov != NULL) 6114 pci_iov_cfg_save(dev, dinfo); 6115 #endif 6116 6117 /* 6118 * don't set the state for display devices, base peripherals and 6119 * memory devices since bad things happen when they are powered down. 6120 * We should (a) have drivers that can easily detach and (b) use 6121 * generic drivers for these devices so that some device actually 6122 * attaches. We need to make sure that when we implement (a) we don't 6123 * power the device down on a reattach. 6124 */ 6125 cls = pci_get_class(dev); 6126 if (!setstate) 6127 return; 6128 switch (pci_do_power_nodriver) 6129 { 6130 case 0: /* NO powerdown at all */ 6131 return; 6132 case 1: /* Conservative about what to power down */ 6133 if (cls == PCIC_STORAGE) 6134 return; 6135 /*FALLTHROUGH*/ 6136 case 2: /* Aggressive about what to power down */ 6137 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 6138 cls == PCIC_BASEPERIPH) 6139 return; 6140 /*FALLTHROUGH*/ 6141 case 3: /* Power down everything */ 6142 break; 6143 } 6144 /* 6145 * PCI spec says we can only go into D3 state from D0 state. 6146 * Transition from D[12] into D0 before going to D3 state. 6147 */ 6148 ps = pci_get_powerstate(dev); 6149 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6150 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6151 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 6152 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6153 } 6154 6155 /* Wrapper APIs suitable for device driver use. */ 6156 void 6157 pci_save_state(device_t dev) 6158 { 6159 struct pci_devinfo *dinfo; 6160 6161 dinfo = device_get_ivars(dev); 6162 pci_cfg_save(dev, dinfo, 0); 6163 } 6164 6165 void 6166 pci_restore_state(device_t dev) 6167 { 6168 struct pci_devinfo *dinfo; 6169 6170 dinfo = device_get_ivars(dev); 6171 pci_cfg_restore(dev, dinfo); 6172 } 6173 6174 static int 6175 pci_get_id_method(device_t dev, device_t child, enum pci_id_type type, 6176 uintptr_t *id) 6177 { 6178 6179 return (PCIB_GET_ID(device_get_parent(dev), child, type, id)); 6180 } 6181 6182 /* Find the upstream port of a given PCI device in a root complex. */ 6183 device_t 6184 pci_find_pcie_root_port(device_t dev) 6185 { 6186 struct pci_devinfo *dinfo; 6187 devclass_t pci_class; 6188 device_t pcib, bus; 6189 6190 pci_class = devclass_find("pci"); 6191 KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class, 6192 ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); 6193 6194 /* 6195 * Walk the bridge hierarchy until we find a PCI-e root 6196 * port or a non-PCI device. 6197 */ 6198 for (;;) { 6199 bus = device_get_parent(dev); 6200 KASSERT(bus != NULL, ("%s: null parent of %s", __func__, 6201 device_get_nameunit(dev))); 6202 6203 pcib = device_get_parent(bus); 6204 KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__, 6205 device_get_nameunit(bus))); 6206 6207 /* 6208 * pcib's parent must be a PCI bus for this to be a 6209 * PCI-PCI bridge. 6210 */ 6211 if (device_get_devclass(device_get_parent(pcib)) != pci_class) 6212 return (NULL); 6213 6214 dinfo = device_get_ivars(pcib); 6215 if (dinfo->cfg.pcie.pcie_location != 0 && 6216 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) 6217 return (pcib); 6218 6219 dev = pcib; 6220 } 6221 } 6222 6223 /* 6224 * Wait for pending transactions to complete on a PCI-express function. 6225 * 6226 * The maximum delay is specified in milliseconds in max_delay. Note 6227 * that this function may sleep. 6228 * 6229 * Returns true if the function is idle and false if the timeout is 6230 * exceeded. If dev is not a PCI-express function, this returns true. 6231 */ 6232 bool 6233 pcie_wait_for_pending_transactions(device_t dev, u_int max_delay) 6234 { 6235 struct pci_devinfo *dinfo = device_get_ivars(dev); 6236 uint16_t sta; 6237 int cap; 6238 6239 cap = dinfo->cfg.pcie.pcie_location; 6240 if (cap == 0) 6241 return (true); 6242 6243 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6244 while (sta & PCIEM_STA_TRANSACTION_PND) { 6245 if (max_delay == 0) 6246 return (false); 6247 6248 /* Poll once every 100 milliseconds up to the timeout. */ 6249 if (max_delay > 100) { 6250 pause_sbt("pcietp", 100 * SBT_1MS, 0, C_HARDCLOCK); 6251 max_delay -= 100; 6252 } else { 6253 pause_sbt("pcietp", max_delay * SBT_1MS, 0, 6254 C_HARDCLOCK); 6255 max_delay = 0; 6256 } 6257 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6258 } 6259 6260 return (true); 6261 } 6262 6263 /* 6264 * Determine the maximum Completion Timeout in microseconds. 6265 * 6266 * For non-PCI-express functions this returns 0. 6267 */ 6268 int 6269 pcie_get_max_completion_timeout(device_t dev) 6270 { 6271 struct pci_devinfo *dinfo = device_get_ivars(dev); 6272 int cap; 6273 6274 cap = dinfo->cfg.pcie.pcie_location; 6275 if (cap == 0) 6276 return (0); 6277 6278 /* 6279 * Functions using the 1.x spec use the default timeout range of 6280 * 50 microseconds to 50 milliseconds. Functions that do not 6281 * support programmable timeouts also use this range. 6282 */ 6283 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 || 6284 (pci_read_config(dev, cap + PCIER_DEVICE_CAP2, 4) & 6285 PCIEM_CAP2_COMP_TIMO_RANGES) == 0) 6286 return (50 * 1000); 6287 6288 switch (pci_read_config(dev, cap + PCIER_DEVICE_CTL2, 2) & 6289 PCIEM_CTL2_COMP_TIMO_VAL) { 6290 case PCIEM_CTL2_COMP_TIMO_100US: 6291 return (100); 6292 case PCIEM_CTL2_COMP_TIMO_10MS: 6293 return (10 * 1000); 6294 case PCIEM_CTL2_COMP_TIMO_55MS: 6295 return (55 * 1000); 6296 case PCIEM_CTL2_COMP_TIMO_210MS: 6297 return (210 * 1000); 6298 case PCIEM_CTL2_COMP_TIMO_900MS: 6299 return (900 * 1000); 6300 case PCIEM_CTL2_COMP_TIMO_3500MS: 6301 return (3500 * 1000); 6302 case PCIEM_CTL2_COMP_TIMO_13S: 6303 return (13 * 1000 * 1000); 6304 case PCIEM_CTL2_COMP_TIMO_64S: 6305 return (64 * 1000 * 1000); 6306 default: 6307 return (50 * 1000); 6308 } 6309 } 6310 6311 /* 6312 * Perform a Function Level Reset (FLR) on a device. 6313 * 6314 * This function first waits for any pending transactions to complete 6315 * within the timeout specified by max_delay. If transactions are 6316 * still pending, the function will return false without attempting a 6317 * reset. 6318 * 6319 * If dev is not a PCI-express function or does not support FLR, this 6320 * function returns false. 6321 * 6322 * Note that no registers are saved or restored. The caller is 6323 * responsible for saving and restoring any registers including 6324 * PCI-standard registers via pci_save_state() and 6325 * pci_restore_state(). 6326 */ 6327 bool 6328 pcie_flr(device_t dev, u_int max_delay, bool force) 6329 { 6330 struct pci_devinfo *dinfo = device_get_ivars(dev); 6331 uint16_t cmd, ctl; 6332 int compl_delay; 6333 int cap; 6334 6335 cap = dinfo->cfg.pcie.pcie_location; 6336 if (cap == 0) 6337 return (false); 6338 6339 if (!(pci_read_config(dev, cap + PCIER_DEVICE_CAP, 4) & PCIEM_CAP_FLR)) 6340 return (false); 6341 6342 /* 6343 * Disable busmastering to prevent generation of new 6344 * transactions while waiting for the device to go idle. If 6345 * the idle timeout fails, the command register is restored 6346 * which will re-enable busmastering. 6347 */ 6348 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 6349 pci_write_config(dev, PCIR_COMMAND, cmd & ~(PCIM_CMD_BUSMASTEREN), 2); 6350 if (!pcie_wait_for_pending_transactions(dev, max_delay)) { 6351 if (!force) { 6352 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 6353 return (false); 6354 } 6355 pci_printf(&dinfo->cfg, 6356 "Resetting with transactions pending after %d ms\n", 6357 max_delay); 6358 6359 /* 6360 * Extend the post-FLR delay to cover the maximum 6361 * Completion Timeout delay of anything in flight 6362 * during the FLR delay. Enforce a minimum delay of 6363 * at least 10ms. 6364 */ 6365 compl_delay = pcie_get_max_completion_timeout(dev) / 1000; 6366 if (compl_delay < 10) 6367 compl_delay = 10; 6368 } else 6369 compl_delay = 0; 6370 6371 /* Initiate the reset. */ 6372 ctl = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 6373 pci_write_config(dev, cap + PCIER_DEVICE_CTL, ctl | 6374 PCIEM_CTL_INITIATE_FLR, 2); 6375 6376 /* Wait for 100ms. */ 6377 pause_sbt("pcieflr", (100 + compl_delay) * SBT_1MS, 0, C_HARDCLOCK); 6378 6379 if (pci_read_config(dev, cap + PCIER_DEVICE_STA, 2) & 6380 PCIEM_STA_TRANSACTION_PND) 6381 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n"); 6382 return (true); 6383 } 6384 6385 /* 6386 * Attempt a power-management reset by cycling the device in/out of D3 6387 * state. PCI spec says we can only go into D3 state from D0 state. 6388 * Transition from D[12] into D0 before going to D3 state. 6389 */ 6390 int 6391 pci_power_reset(device_t dev) 6392 { 6393 int ps; 6394 6395 ps = pci_get_powerstate(dev); 6396 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6397 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6398 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6399 pci_set_powerstate(dev, ps); 6400 return (0); 6401 } 6402 6403 /* 6404 * Try link drop and retrain of the downstream port of upstream 6405 * switch, for PCIe. According to the PCIe 3.0 spec 6.6.1, this must 6406 * cause Conventional Hot reset of the device in the slot. 6407 * Alternative, for PCIe, could be the secondary bus reset initiatied 6408 * on the upstream switch PCIR_BRIDGECTL_1, bit 6. 6409 */ 6410 int 6411 pcie_link_reset(device_t port, int pcie_location) 6412 { 6413 uint16_t v; 6414 6415 v = pci_read_config(port, pcie_location + PCIER_LINK_CTL, 2); 6416 v |= PCIEM_LINK_CTL_LINK_DIS; 6417 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6418 pause_sbt("pcier1", mstosbt(20), 0, 0); 6419 v &= ~PCIEM_LINK_CTL_LINK_DIS; 6420 v |= PCIEM_LINK_CTL_RETRAIN_LINK; 6421 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6422 pause_sbt("pcier2", mstosbt(100), 0, 0); /* 100 ms */ 6423 v = pci_read_config(port, pcie_location + PCIER_LINK_STA, 2); 6424 return ((v & PCIEM_LINK_STA_TRAINING) != 0 ? ETIMEDOUT : 0); 6425 } 6426 6427 static int 6428 pci_reset_post(device_t dev, device_t child) 6429 { 6430 6431 if (dev == device_get_parent(child)) 6432 pci_restore_state(child); 6433 return (0); 6434 } 6435 6436 static int 6437 pci_reset_prepare(device_t dev, device_t child) 6438 { 6439 6440 if (dev == device_get_parent(child)) 6441 pci_save_state(child); 6442 return (0); 6443 } 6444 6445 static int 6446 pci_reset_child(device_t dev, device_t child, int flags) 6447 { 6448 int error; 6449 6450 if (dev == NULL || device_get_parent(child) != dev) 6451 return (0); 6452 if ((flags & DEVF_RESET_DETACH) != 0) { 6453 error = device_get_state(child) == DS_ATTACHED ? 6454 device_detach(child) : 0; 6455 } else { 6456 error = BUS_SUSPEND_CHILD(dev, child); 6457 } 6458 if (error == 0) { 6459 if (!pcie_flr(child, 1000, false)) { 6460 error = BUS_RESET_PREPARE(dev, child); 6461 if (error == 0) 6462 pci_power_reset(child); 6463 BUS_RESET_POST(dev, child); 6464 } 6465 if ((flags & DEVF_RESET_DETACH) != 0) 6466 device_probe_and_attach(child); 6467 else 6468 BUS_RESUME_CHILD(dev, child); 6469 } 6470 return (error); 6471 } 6472 6473 const struct pci_device_table * 6474 pci_match_device(device_t child, const struct pci_device_table *id, size_t nelt) 6475 { 6476 bool match; 6477 uint16_t vendor, device, subvendor, subdevice, class, subclass, revid; 6478 6479 vendor = pci_get_vendor(child); 6480 device = pci_get_device(child); 6481 subvendor = pci_get_subvendor(child); 6482 subdevice = pci_get_subdevice(child); 6483 class = pci_get_class(child); 6484 subclass = pci_get_subclass(child); 6485 revid = pci_get_revid(child); 6486 while (nelt-- > 0) { 6487 match = true; 6488 if (id->match_flag_vendor) 6489 match &= vendor == id->vendor; 6490 if (id->match_flag_device) 6491 match &= device == id->device; 6492 if (id->match_flag_subvendor) 6493 match &= subvendor == id->subvendor; 6494 if (id->match_flag_subdevice) 6495 match &= subdevice == id->subdevice; 6496 if (id->match_flag_class) 6497 match &= class == id->class_id; 6498 if (id->match_flag_subclass) 6499 match &= subclass == id->subclass; 6500 if (id->match_flag_revid) 6501 match &= revid == id->revid; 6502 if (match) 6503 return (id); 6504 id++; 6505 } 6506 return (NULL); 6507 } 6508 6509 static void 6510 pci_print_faulted_dev_name(const struct pci_devinfo *dinfo) 6511 { 6512 const char *dev_name; 6513 device_t dev; 6514 6515 dev = dinfo->cfg.dev; 6516 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus, 6517 dinfo->cfg.slot, dinfo->cfg.func); 6518 dev_name = device_get_name(dev); 6519 if (dev_name != NULL) 6520 printf(" (%s%d)", dev_name, device_get_unit(dev)); 6521 } 6522 6523 void 6524 pci_print_faulted_dev(void) 6525 { 6526 struct pci_devinfo *dinfo; 6527 device_t dev; 6528 int aer, i; 6529 uint32_t r1, r2; 6530 uint16_t status; 6531 6532 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6533 dev = dinfo->cfg.dev; 6534 status = pci_read_config(dev, PCIR_STATUS, 2); 6535 status &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6536 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6537 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6538 if (status != 0) { 6539 pci_print_faulted_dev_name(dinfo); 6540 printf(" error 0x%04x\n", status); 6541 } 6542 if (dinfo->cfg.pcie.pcie_location != 0) { 6543 status = pci_read_config(dev, 6544 dinfo->cfg.pcie.pcie_location + 6545 PCIER_DEVICE_STA, 2); 6546 if ((status & (PCIEM_STA_CORRECTABLE_ERROR | 6547 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6548 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6549 pci_print_faulted_dev_name(dinfo); 6550 printf(" PCIe DEVCTL 0x%04x DEVSTA 0x%04x\n", 6551 pci_read_config(dev, 6552 dinfo->cfg.pcie.pcie_location + 6553 PCIER_DEVICE_CTL, 2), 6554 status); 6555 } 6556 } 6557 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6558 r1 = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6559 r2 = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6560 if (r1 != 0 || r2 != 0) { 6561 pci_print_faulted_dev_name(dinfo); 6562 printf(" AER UC 0x%08x Mask 0x%08x Svr 0x%08x\n" 6563 " COR 0x%08x Mask 0x%08x Ctl 0x%08x\n", 6564 r1, pci_read_config(dev, aer + 6565 PCIR_AER_UC_MASK, 4), 6566 pci_read_config(dev, aer + 6567 PCIR_AER_UC_SEVERITY, 4), 6568 r2, pci_read_config(dev, aer + 6569 PCIR_AER_COR_MASK, 4), 6570 pci_read_config(dev, aer + 6571 PCIR_AER_CAP_CONTROL, 4)); 6572 for (i = 0; i < 4; i++) { 6573 r1 = pci_read_config(dev, aer + 6574 PCIR_AER_HEADER_LOG + i * 4, 4); 6575 printf(" HL%d: 0x%08x\n", i, r1); 6576 } 6577 } 6578 } 6579 } 6580 } 6581 6582 #ifdef DDB 6583 DB_SHOW_COMMAND(pcierr, pci_print_faulted_dev_db) 6584 { 6585 6586 pci_print_faulted_dev(); 6587 } 6588 6589 static void 6590 db_clear_pcie_errors(const struct pci_devinfo *dinfo) 6591 { 6592 device_t dev; 6593 int aer; 6594 uint32_t r; 6595 6596 dev = dinfo->cfg.dev; 6597 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6598 PCIER_DEVICE_STA, 2); 6599 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6600 PCIER_DEVICE_STA, r, 2); 6601 6602 if (pci_find_extcap(dev, PCIZ_AER, &aer) != 0) 6603 return; 6604 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6605 if (r != 0) 6606 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6607 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6608 if (r != 0) 6609 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6610 } 6611 6612 DB_COMMAND(pci_clearerr, db_pci_clearerr) 6613 { 6614 struct pci_devinfo *dinfo; 6615 device_t dev; 6616 uint16_t status, status1; 6617 6618 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6619 dev = dinfo->cfg.dev; 6620 status1 = status = pci_read_config(dev, PCIR_STATUS, 2); 6621 status1 &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6622 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6623 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6624 if (status1 != 0) { 6625 status &= ~status1; 6626 pci_write_config(dev, PCIR_STATUS, status, 2); 6627 } 6628 if (dinfo->cfg.pcie.pcie_location != 0) 6629 db_clear_pcie_errors(dinfo); 6630 } 6631 } 6632 #endif 6633