1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/linker.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/sysctl.h> 44 #include <sys/types.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 55 #include <sys/pciio.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pci_private.h> 59 60 #include "pcib_if.h" 61 #include "pci_if.h" 62 63 #if (defined(__i386__) && !defined(PC98)) || defined(__amd64__) || \ 64 defined (__ia64__) 65 #include <contrib/dev/acpica/acpi.h> 66 #include "acpi_if.h" 67 #else 68 #define ACPI_PWR_FOR_SLEEP(x, y, z) 69 #endif 70 71 static uint32_t pci_mapbase(unsigned mapreg); 72 static int pci_maptype(unsigned mapreg); 73 static int pci_mapsize(unsigned testval); 74 static int pci_maprange(unsigned mapreg); 75 static void pci_fixancient(pcicfgregs *cfg); 76 77 static int pci_porten(device_t pcib, int b, int s, int f); 78 static int pci_memen(device_t pcib, int b, int s, int f); 79 static int pci_add_map(device_t pcib, device_t bus, device_t dev, 80 int b, int s, int f, int reg, 81 struct resource_list *rl); 82 static void pci_add_resources(device_t pcib, device_t bus, 83 device_t dev); 84 static int pci_probe(device_t dev); 85 static int pci_attach(device_t dev); 86 static void pci_load_vendor_data(void); 87 static int pci_describe_parse_line(char **ptr, int *vendor, 88 int *device, char **desc); 89 static char *pci_describe_device(device_t dev); 90 static int pci_modevent(module_t mod, int what, void *arg); 91 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 92 pcicfgregs *cfg); 93 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 94 95 static device_method_t pci_methods[] = { 96 /* Device interface */ 97 DEVMETHOD(device_probe, pci_probe), 98 DEVMETHOD(device_attach, pci_attach), 99 DEVMETHOD(device_detach, bus_generic_detach), 100 DEVMETHOD(device_shutdown, bus_generic_shutdown), 101 DEVMETHOD(device_suspend, pci_suspend), 102 DEVMETHOD(device_resume, pci_resume), 103 104 /* Bus interface */ 105 DEVMETHOD(bus_print_child, pci_print_child), 106 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 107 DEVMETHOD(bus_read_ivar, pci_read_ivar), 108 DEVMETHOD(bus_write_ivar, pci_write_ivar), 109 DEVMETHOD(bus_driver_added, pci_driver_added), 110 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 111 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 112 113 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 114 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 115 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 116 DEVMETHOD(bus_delete_resource, pci_delete_resource), 117 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 118 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 119 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 120 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 121 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 122 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 123 124 /* PCI interface */ 125 DEVMETHOD(pci_read_config, pci_read_config_method), 126 DEVMETHOD(pci_write_config, pci_write_config_method), 127 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 128 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 129 DEVMETHOD(pci_enable_io, pci_enable_io_method), 130 DEVMETHOD(pci_disable_io, pci_disable_io_method), 131 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 132 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 133 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 134 135 { 0, 0 } 136 }; 137 138 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 139 140 devclass_t pci_devclass; 141 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 142 MODULE_VERSION(pci, 1); 143 144 static char *pci_vendordata; 145 static size_t pci_vendordata_size; 146 147 148 struct pci_quirk { 149 uint32_t devid; /* Vendor/device of the card */ 150 int type; 151 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 152 int arg1; 153 int arg2; 154 }; 155 156 struct pci_quirk pci_quirks[] = { 157 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 158 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 159 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 160 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 161 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 162 163 { 0 } 164 }; 165 166 /* map register information */ 167 #define PCI_MAPMEM 0x01 /* memory map */ 168 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 169 #define PCI_MAPPORT 0x04 /* port map */ 170 171 struct devlist pci_devq; 172 uint32_t pci_generation; 173 uint32_t pci_numdevs = 0; 174 175 /* sysctl vars */ 176 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 177 178 static int pci_enable_io_modes = 1; 179 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 180 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 181 &pci_enable_io_modes, 1, 182 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 183 enable these bits correctly. We'd like to do this all the time, but there\n\ 184 are some peripherals that this causes problems with."); 185 186 static int pci_do_powerstate = 1; 187 TUNABLE_INT("hw.pci.do_powerstate", &pci_do_powerstate); 188 SYSCTL_INT(_hw_pci, OID_AUTO, do_powerstate, CTLFLAG_RW, 189 &pci_do_powerstate, 1, 190 "Power down devices into D3 state when no driver attaches to them.\n\ 191 Otherwise, leave the device in D0 state when no driver attaches."); 192 193 /* Find a device_t by bus/slot/function */ 194 195 device_t 196 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 197 { 198 struct pci_devinfo *dinfo; 199 200 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 201 if ((dinfo->cfg.bus == bus) && 202 (dinfo->cfg.slot == slot) && 203 (dinfo->cfg.func == func)) { 204 return (dinfo->cfg.dev); 205 } 206 } 207 208 return (NULL); 209 } 210 211 /* Find a device_t by vendor/device ID */ 212 213 device_t 214 pci_find_device(uint16_t vendor, uint16_t device) 215 { 216 struct pci_devinfo *dinfo; 217 218 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 219 if ((dinfo->cfg.vendor == vendor) && 220 (dinfo->cfg.device == device)) { 221 return (dinfo->cfg.dev); 222 } 223 } 224 225 return (NULL); 226 } 227 228 /* return base address of memory or port map */ 229 230 static uint32_t 231 pci_mapbase(unsigned mapreg) 232 { 233 int mask = 0x03; 234 if ((mapreg & 0x01) == 0) 235 mask = 0x0f; 236 return (mapreg & ~mask); 237 } 238 239 /* return map type of memory or port map */ 240 241 static int 242 pci_maptype(unsigned mapreg) 243 { 244 static uint8_t maptype[0x10] = { 245 PCI_MAPMEM, PCI_MAPPORT, 246 PCI_MAPMEM, 0, 247 PCI_MAPMEM, PCI_MAPPORT, 248 0, 0, 249 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 250 PCI_MAPMEM|PCI_MAPMEMP, 0, 251 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 252 0, 0, 253 }; 254 255 return maptype[mapreg & 0x0f]; 256 } 257 258 /* return log2 of map size decoded for memory or port map */ 259 260 static int 261 pci_mapsize(unsigned testval) 262 { 263 int ln2size; 264 265 testval = pci_mapbase(testval); 266 ln2size = 0; 267 if (testval != 0) { 268 while ((testval & 1) == 0) 269 { 270 ln2size++; 271 testval >>= 1; 272 } 273 } 274 return (ln2size); 275 } 276 277 /* return log2 of address range supported by map register */ 278 279 static int 280 pci_maprange(unsigned mapreg) 281 { 282 int ln2range = 0; 283 switch (mapreg & 0x07) { 284 case 0x00: 285 case 0x01: 286 case 0x05: 287 ln2range = 32; 288 break; 289 case 0x02: 290 ln2range = 20; 291 break; 292 case 0x04: 293 ln2range = 64; 294 break; 295 } 296 return (ln2range); 297 } 298 299 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 300 301 static void 302 pci_fixancient(pcicfgregs *cfg) 303 { 304 if (cfg->hdrtype != 0) 305 return; 306 307 /* PCI to PCI bridges use header type 1 */ 308 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 309 cfg->hdrtype = 1; 310 } 311 312 /* extract header type specific config data */ 313 314 static void 315 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 316 { 317 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 318 switch (cfg->hdrtype) { 319 case 0: 320 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 321 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 322 cfg->nummaps = PCI_MAXMAPS_0; 323 break; 324 case 1: 325 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 326 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 327 cfg->nummaps = PCI_MAXMAPS_1; 328 break; 329 case 2: 330 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 331 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 332 cfg->nummaps = PCI_MAXMAPS_2; 333 break; 334 } 335 #undef REG 336 } 337 338 /* read configuration header into pcicfgregs structure */ 339 340 struct pci_devinfo * 341 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 342 { 343 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 344 pcicfgregs *cfg = NULL; 345 struct pci_devinfo *devlist_entry; 346 struct devlist *devlist_head; 347 348 devlist_head = &pci_devq; 349 350 devlist_entry = NULL; 351 352 if (REG(PCIR_DEVVENDOR, 4) != -1) { 353 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 354 if (devlist_entry == NULL) 355 return (NULL); 356 357 cfg = &devlist_entry->cfg; 358 359 cfg->bus = b; 360 cfg->slot = s; 361 cfg->func = f; 362 cfg->vendor = REG(PCIR_VENDOR, 2); 363 cfg->device = REG(PCIR_DEVICE, 2); 364 cfg->cmdreg = REG(PCIR_COMMAND, 2); 365 cfg->statreg = REG(PCIR_STATUS, 2); 366 cfg->baseclass = REG(PCIR_CLASS, 1); 367 cfg->subclass = REG(PCIR_SUBCLASS, 1); 368 cfg->progif = REG(PCIR_PROGIF, 1); 369 cfg->revid = REG(PCIR_REVID, 1); 370 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 371 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 372 cfg->lattimer = REG(PCIR_LATTIMER, 1); 373 cfg->intpin = REG(PCIR_INTPIN, 1); 374 cfg->intline = REG(PCIR_INTLINE, 1); 375 376 cfg->mingnt = REG(PCIR_MINGNT, 1); 377 cfg->maxlat = REG(PCIR_MAXLAT, 1); 378 379 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 380 cfg->hdrtype &= ~PCIM_MFDEV; 381 382 pci_fixancient(cfg); 383 pci_hdrtypedata(pcib, b, s, f, cfg); 384 385 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 386 pci_read_extcap(pcib, cfg); 387 388 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 389 390 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 391 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 392 devlist_entry->conf.pc_sel.pc_func = cfg->func; 393 devlist_entry->conf.pc_hdr = cfg->hdrtype; 394 395 devlist_entry->conf.pc_subvendor = cfg->subvendor; 396 devlist_entry->conf.pc_subdevice = cfg->subdevice; 397 devlist_entry->conf.pc_vendor = cfg->vendor; 398 devlist_entry->conf.pc_device = cfg->device; 399 400 devlist_entry->conf.pc_class = cfg->baseclass; 401 devlist_entry->conf.pc_subclass = cfg->subclass; 402 devlist_entry->conf.pc_progif = cfg->progif; 403 devlist_entry->conf.pc_revid = cfg->revid; 404 405 pci_numdevs++; 406 pci_generation++; 407 } 408 return (devlist_entry); 409 #undef REG 410 } 411 412 static void 413 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 414 { 415 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 416 int ptr, nextptr, ptrptr; 417 418 switch (cfg->hdrtype & PCIM_HDRTYPE) { 419 case 0: 420 ptrptr = PCIR_CAP_PTR; 421 break; 422 case 2: 423 ptrptr = 0x14; 424 break; 425 default: 426 return; /* no extended capabilities support */ 427 } 428 nextptr = REG(ptrptr, 1); /* sanity check? */ 429 430 /* 431 * Read capability entries. 432 */ 433 while (nextptr != 0) { 434 /* Sanity check */ 435 if (nextptr > 255) { 436 printf("illegal PCI extended capability offset %d\n", 437 nextptr); 438 return; 439 } 440 /* Find the next entry */ 441 ptr = nextptr; 442 nextptr = REG(ptr + 1, 1); 443 444 /* Process this entry */ 445 switch (REG(ptr, 1)) { 446 case PCIY_PMG: /* PCI power management */ 447 if (cfg->pp.pp_cap == 0) { 448 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 449 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 450 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 451 if ((nextptr - ptr) > PCIR_POWER_DATA) 452 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 453 } 454 break; 455 case PCIY_MSI: /* PCI MSI */ 456 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 457 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 458 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 459 else 460 cfg->msi.msi_data = PCIR_MSI_DATA; 461 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 462 PCIM_MSICTRL_MMC_MASK)>>1); 463 default: 464 break; 465 } 466 } 467 #undef REG 468 } 469 470 /* free pcicfgregs structure and all depending data structures */ 471 472 int 473 pci_freecfg(struct pci_devinfo *dinfo) 474 { 475 struct devlist *devlist_head; 476 477 devlist_head = &pci_devq; 478 479 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 480 free(dinfo, M_DEVBUF); 481 482 /* increment the generation count */ 483 pci_generation++; 484 485 /* we're losing one device */ 486 pci_numdevs--; 487 return (0); 488 } 489 490 /* 491 * PCI power manangement 492 */ 493 int 494 pci_set_powerstate_method(device_t dev, device_t child, int state) 495 { 496 struct pci_devinfo *dinfo = device_get_ivars(child); 497 pcicfgregs *cfg = &dinfo->cfg; 498 uint16_t status; 499 int result, oldstate, highest, delay; 500 501 if (cfg->pp.pp_cap == 0) 502 return (EOPNOTSUPP); 503 504 /* 505 * Optimize a no state change request away. While it would be OK to 506 * write to the hardware in theory, some devices have shown odd 507 * behavior when going from D3 -> D3. 508 */ 509 oldstate = pci_get_powerstate(child); 510 if (oldstate == state) 511 return (0); 512 513 /* 514 * The PCI power management specification states that after a state 515 * transition between PCI power states, system software must 516 * guarantee a minimal delay before the function accesses the device. 517 * Compute the worst case delay that we need to guarantee before we 518 * access the device. Many devices will be responsive much more 519 * quickly than this delay, but there are some that don't respond 520 * instantly to state changes. Transitions to/from D3 state require 521 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 522 * is done below with DELAY rather than a sleeper function because 523 * this function can be called from contexts where we cannot sleep. 524 */ 525 highest = (oldstate > state) ? oldstate : state; 526 if (highest == PCI_POWERSTATE_D3) 527 delay = 10000; 528 else if (highest == PCI_POWERSTATE_D2) 529 delay = 200; 530 else 531 delay = 0; 532 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 533 & ~PCIM_PSTAT_DMASK; 534 result = 0; 535 switch (state) { 536 case PCI_POWERSTATE_D0: 537 status |= PCIM_PSTAT_D0; 538 break; 539 case PCI_POWERSTATE_D1: 540 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 541 return (EOPNOTSUPP); 542 status |= PCIM_PSTAT_D1; 543 break; 544 case PCI_POWERSTATE_D2: 545 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 546 return (EOPNOTSUPP); 547 status |= PCIM_PSTAT_D2; 548 break; 549 case PCI_POWERSTATE_D3: 550 status |= PCIM_PSTAT_D3; 551 break; 552 default: 553 return (EINVAL); 554 } 555 556 if (bootverbose) 557 printf( 558 "pci%d:%d:%d: Transition from D%d to D%d\n", 559 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 560 oldstate, state); 561 562 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 563 if (delay) 564 DELAY(delay); 565 return (0); 566 } 567 568 int 569 pci_get_powerstate_method(device_t dev, device_t child) 570 { 571 struct pci_devinfo *dinfo = device_get_ivars(child); 572 pcicfgregs *cfg = &dinfo->cfg; 573 uint16_t status; 574 int result; 575 576 if (cfg->pp.pp_cap != 0) { 577 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 578 switch (status & PCIM_PSTAT_DMASK) { 579 case PCIM_PSTAT_D0: 580 result = PCI_POWERSTATE_D0; 581 break; 582 case PCIM_PSTAT_D1: 583 result = PCI_POWERSTATE_D1; 584 break; 585 case PCIM_PSTAT_D2: 586 result = PCI_POWERSTATE_D2; 587 break; 588 case PCIM_PSTAT_D3: 589 result = PCI_POWERSTATE_D3; 590 break; 591 default: 592 result = PCI_POWERSTATE_UNKNOWN; 593 break; 594 } 595 } else { 596 /* No support, device is always at D0 */ 597 result = PCI_POWERSTATE_D0; 598 } 599 return (result); 600 } 601 602 /* 603 * Some convenience functions for PCI device drivers. 604 */ 605 606 static __inline void 607 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 608 { 609 uint16_t command; 610 611 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 612 command |= bit; 613 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 614 } 615 616 static __inline void 617 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 618 { 619 uint16_t command; 620 621 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 622 command &= ~bit; 623 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 624 } 625 626 int 627 pci_enable_busmaster_method(device_t dev, device_t child) 628 { 629 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 630 return (0); 631 } 632 633 int 634 pci_disable_busmaster_method(device_t dev, device_t child) 635 { 636 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 637 return (0); 638 } 639 640 int 641 pci_enable_io_method(device_t dev, device_t child, int space) 642 { 643 uint16_t command; 644 uint16_t bit; 645 char *error; 646 647 bit = 0; 648 error = NULL; 649 650 switch(space) { 651 case SYS_RES_IOPORT: 652 bit = PCIM_CMD_PORTEN; 653 error = "port"; 654 break; 655 case SYS_RES_MEMORY: 656 bit = PCIM_CMD_MEMEN; 657 error = "memory"; 658 break; 659 default: 660 return (EINVAL); 661 } 662 pci_set_command_bit(dev, child, bit); 663 /* Some devices seem to need a brief stall here, what do to? */ 664 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 665 if (command & bit) 666 return (0); 667 device_printf(child, "failed to enable %s mapping!\n", error); 668 return (ENXIO); 669 } 670 671 int 672 pci_disable_io_method(device_t dev, device_t child, int space) 673 { 674 uint16_t command; 675 uint16_t bit; 676 char *error; 677 678 bit = 0; 679 error = NULL; 680 681 switch(space) { 682 case SYS_RES_IOPORT: 683 bit = PCIM_CMD_PORTEN; 684 error = "port"; 685 break; 686 case SYS_RES_MEMORY: 687 bit = PCIM_CMD_MEMEN; 688 error = "memory"; 689 break; 690 default: 691 return (EINVAL); 692 } 693 pci_clear_command_bit(dev, child, bit); 694 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 695 if (command & bit) { 696 device_printf(child, "failed to disable %s mapping!\n", error); 697 return (ENXIO); 698 } 699 return (0); 700 } 701 702 /* 703 * New style pci driver. Parent device is either a pci-host-bridge or a 704 * pci-pci-bridge. Both kinds are represented by instances of pcib. 705 */ 706 707 void 708 pci_print_verbose(struct pci_devinfo *dinfo) 709 { 710 if (bootverbose) { 711 pcicfgregs *cfg = &dinfo->cfg; 712 713 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 714 cfg->vendor, cfg->device, cfg->revid); 715 printf("\tbus=%d, slot=%d, func=%d\n", 716 cfg->bus, cfg->slot, cfg->func); 717 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 718 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 719 cfg->mfdev); 720 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 721 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 722 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 723 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 724 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 725 if (cfg->intpin > 0) 726 printf("\tintpin=%c, irq=%d\n", 727 cfg->intpin +'a' -1, cfg->intline); 728 if (cfg->pp.pp_cap) { 729 uint16_t status; 730 731 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 732 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 733 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 734 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 735 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 736 status & PCIM_PSTAT_DMASK); 737 } 738 if (cfg->msi.msi_data) { 739 int ctrl; 740 741 ctrl = cfg->msi.msi_ctrl; 742 printf("\tMSI supports %d message%s%s%s\n", 743 cfg->msi.msi_msgnum, 744 (cfg->msi.msi_msgnum == 1) ? "" : "s", 745 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 746 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 747 } 748 } 749 } 750 751 static int 752 pci_porten(device_t pcib, int b, int s, int f) 753 { 754 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 755 & PCIM_CMD_PORTEN) != 0; 756 } 757 758 static int 759 pci_memen(device_t pcib, int b, int s, int f) 760 { 761 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 762 & PCIM_CMD_MEMEN) != 0; 763 } 764 765 /* 766 * Add a resource based on a pci map register. Return 1 if the map 767 * register is a 32bit map register or 2 if it is a 64bit register. 768 */ 769 static int 770 pci_add_map(device_t pcib, device_t bus, device_t dev, 771 int b, int s, int f, int reg, struct resource_list *rl) 772 { 773 uint32_t map; 774 uint64_t base; 775 uint64_t start, end, count; 776 uint8_t ln2size; 777 uint8_t ln2range; 778 uint32_t testval; 779 uint16_t cmd; 780 int type; 781 782 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 783 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 784 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 785 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 786 787 if (pci_maptype(map) & PCI_MAPMEM) 788 type = SYS_RES_MEMORY; 789 else 790 type = SYS_RES_IOPORT; 791 ln2size = pci_mapsize(testval); 792 ln2range = pci_maprange(testval); 793 base = pci_mapbase(map); 794 795 /* 796 * For I/O registers, if bottom bit is set, and the next bit up 797 * isn't clear, we know we have a BAR that doesn't conform to the 798 * spec, so ignore it. Also, sanity check the size of the data 799 * areas to the type of memory involved. Memory must be at least 800 * 32 bytes in size, while I/O ranges must be at least 4. 801 */ 802 if ((testval & 0x1) == 0x1 && 803 (testval & 0x2) != 0) 804 return (1); 805 if ((type == SYS_RES_MEMORY && ln2size < 5) || 806 (type == SYS_RES_IOPORT && ln2size < 2)) 807 return (1); 808 809 if (ln2range == 64) 810 /* Read the other half of a 64bit map register */ 811 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 812 813 if (bootverbose) { 814 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 815 reg, pci_maptype(map), ln2range, 816 (unsigned int) base, ln2size); 817 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 818 printf(", port disabled\n"); 819 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 820 printf(", memory disabled\n"); 821 else 822 printf(", enabled\n"); 823 } 824 825 /* 826 * If base is 0, then we have problems. It is best to ignore 827 * such entries for the moment. These will be allocated later if 828 * the driver specifically requests them. 829 */ 830 if (base == 0) 831 return 1; 832 /* 833 * This code theoretically does the right thing, but has 834 * undesirable side effects in some cases where peripherals 835 * respond oddly to having these bits enabled. Let the user 836 * be able to turn them off (since pci_enable_io_modes is 1 by 837 * default). 838 */ 839 if (pci_enable_io_modes) { 840 /* Turn on resources that have been left off by a lazy BIOS */ 841 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 842 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 843 cmd |= PCIM_CMD_PORTEN; 844 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 845 } 846 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 847 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 848 cmd |= PCIM_CMD_MEMEN; 849 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 850 } 851 } else { 852 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 853 return (1); 854 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 855 return (1); 856 } 857 858 start = base; 859 end = base + (1 << ln2size) - 1; 860 count = 1 << ln2size; 861 resource_list_add(rl, type, reg, start, end, count); 862 863 /* 864 * Not quite sure what to do on failure of allocating the resource 865 * since I can postulate several right answers. 866 */ 867 resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 0); 868 return ((ln2range == 64) ? 2 : 1); 869 } 870 871 /* 872 * For ATA devices we need to decide early what addressing mode to use. 873 * Legacy demands that the primary and secondary ATA ports sits on the 874 * same addresses that old ISA hardware did. This dictates that we use 875 * those addresses and ignore the BAR's if we cannot set PCI native 876 * addressing mode. 877 */ 878 static void 879 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 880 int s, int f, struct resource_list *rl) 881 { 882 int rid, type, progif; 883 #if 0 884 /* if this device supports PCI native addressing use it */ 885 progif = pci_read_config(dev, PCIR_PROGIF, 1); 886 if ((progif & 0x8a) == 0x8a) { 887 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 888 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 889 printf("Trying ATA native PCI addressing mode\n"); 890 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 891 } 892 } 893 #endif 894 progif = pci_read_config(dev, PCIR_PROGIF, 1); 895 type = SYS_RES_IOPORT; 896 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 897 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl); 898 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl); 899 } 900 else { 901 rid = PCIR_BAR(0); 902 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 903 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,8,0); 904 rid = PCIR_BAR(1); 905 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 906 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,1,0); 907 } 908 if (progif & PCIP_STORAGE_IDE_MODESEC) { 909 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl); 910 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl); 911 } 912 else { 913 rid = PCIR_BAR(2); 914 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 915 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,8,0); 916 rid = PCIR_BAR(3); 917 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 918 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,1,0); 919 } 920 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl); 921 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl); 922 } 923 924 static void 925 pci_add_resources(device_t pcib, device_t bus, device_t dev) 926 { 927 struct pci_devinfo *dinfo = device_get_ivars(dev); 928 pcicfgregs *cfg = &dinfo->cfg; 929 struct resource_list *rl = &dinfo->resources; 930 struct pci_quirk *q; 931 int b, i, irq, f, s; 932 933 b = cfg->bus; 934 s = cfg->slot; 935 f = cfg->func; 936 937 /* ATA devices needs special map treatment */ 938 if ((pci_get_class(dev) == PCIC_STORAGE) && 939 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 940 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 941 pci_ata_maps(pcib, bus, dev, b, s, f, rl); 942 else 943 for (i = 0; i < cfg->nummaps;) 944 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 945 rl); 946 947 for (q = &pci_quirks[0]; q->devid; q++) { 948 if (q->devid == ((cfg->device << 16) | cfg->vendor) 949 && q->type == PCI_QUIRK_MAP_REG) 950 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl); 951 } 952 953 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 954 #if defined(__ia64__) || defined(__i386__) || defined(__amd64__) || \ 955 defined(__arm__) || defined(__alpha__) 956 /* 957 * Try to re-route interrupts. Sometimes the BIOS or 958 * firmware may leave bogus values in these registers. 959 * If the re-route fails, then just stick with what we 960 * have. 961 */ 962 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 963 if (PCI_INTERRUPT_VALID(irq)) { 964 pci_write_config(dev, PCIR_INTLINE, irq, 1); 965 cfg->intline = irq; 966 } else 967 #endif 968 irq = cfg->intline; 969 resource_list_add(rl, SYS_RES_IRQ, 0, irq, irq, 1); 970 } 971 } 972 973 void 974 pci_add_children(device_t dev, int busno, size_t dinfo_size) 975 { 976 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 977 device_t pcib = device_get_parent(dev); 978 struct pci_devinfo *dinfo; 979 int maxslots; 980 int s, f, pcifunchigh; 981 uint8_t hdrtype; 982 983 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 984 ("dinfo_size too small")); 985 maxslots = PCIB_MAXSLOTS(pcib); 986 for (s = 0; s <= maxslots; s++) { 987 pcifunchigh = 0; 988 f = 0; 989 hdrtype = REG(PCIR_HDRTYPE, 1); 990 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 991 continue; 992 if (hdrtype & PCIM_MFDEV) 993 pcifunchigh = PCI_FUNCMAX; 994 for (f = 0; f <= pcifunchigh; f++) { 995 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 996 if (dinfo != NULL) { 997 pci_add_child(dev, dinfo); 998 } 999 } 1000 } 1001 #undef REG 1002 } 1003 1004 void 1005 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1006 { 1007 device_t pcib; 1008 1009 pcib = device_get_parent(bus); 1010 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1011 device_set_ivars(dinfo->cfg.dev, dinfo); 1012 resource_list_init(&dinfo->resources); 1013 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 1014 pci_cfg_restore(dinfo->cfg.dev, dinfo); 1015 pci_print_verbose(dinfo); 1016 pci_add_resources(pcib, bus, dinfo->cfg.dev); 1017 } 1018 1019 static int 1020 pci_probe(device_t dev) 1021 { 1022 1023 device_set_desc(dev, "PCI bus"); 1024 1025 /* Allow other subclasses to override this driver. */ 1026 return (-1000); 1027 } 1028 1029 static int 1030 pci_attach(device_t dev) 1031 { 1032 int busno; 1033 1034 /* 1035 * Since there can be multiple independantly numbered PCI 1036 * busses on some large alpha systems, we can't use the unit 1037 * number to decide what bus we are probing. We ask the parent 1038 * pcib what our bus number is. 1039 */ 1040 busno = pcib_get_bus(dev); 1041 if (bootverbose) 1042 device_printf(dev, "physical bus=%d\n", busno); 1043 1044 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1045 1046 return (bus_generic_attach(dev)); 1047 } 1048 1049 int 1050 pci_suspend(device_t dev) 1051 { 1052 int dstate, error, i, numdevs; 1053 device_t acpi_dev, child, *devlist; 1054 struct pci_devinfo *dinfo; 1055 1056 /* 1057 * Save the PCI configuration space for each child and set the 1058 * device in the appropriate power state for this sleep state. 1059 */ 1060 acpi_dev = NULL; 1061 if (pci_do_powerstate) 1062 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1063 device_get_children(dev, &devlist, &numdevs); 1064 for (i = 0; i < numdevs; i++) { 1065 child = devlist[i]; 1066 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1067 pci_cfg_save(child, dinfo, 0); 1068 } 1069 1070 /* Suspend devices before potentially powering them down. */ 1071 error = bus_generic_suspend(dev); 1072 if (error) { 1073 free(devlist, M_TEMP); 1074 return (error); 1075 } 1076 1077 /* 1078 * Always set the device to D3. If ACPI suggests a different 1079 * power state, use it instead. If ACPI is not present, the 1080 * firmware is responsible for managing device power. Skip 1081 * children who aren't attached since they are powered down 1082 * separately. Only manage type 0 devices for now. 1083 */ 1084 for (i = 0; acpi_dev && i < numdevs; i++) { 1085 child = devlist[i]; 1086 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1087 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 1088 dstate = PCI_POWERSTATE_D3; 1089 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 1090 pci_set_powerstate(child, dstate); 1091 } 1092 } 1093 free(devlist, M_TEMP); 1094 return (0); 1095 } 1096 1097 int 1098 pci_resume(device_t dev) 1099 { 1100 int i, numdevs; 1101 device_t acpi_dev, child, *devlist; 1102 struct pci_devinfo *dinfo; 1103 1104 /* 1105 * Set each child to D0 and restore its PCI configuration space. 1106 */ 1107 acpi_dev = NULL; 1108 if (pci_do_powerstate) 1109 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1110 device_get_children(dev, &devlist, &numdevs); 1111 for (i = 0; i < numdevs; i++) { 1112 /* 1113 * Notify ACPI we're going to D0 but ignore the result. If 1114 * ACPI is not present, the firmware is responsible for 1115 * managing device power. Only manage type 0 devices for now. 1116 */ 1117 child = devlist[i]; 1118 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1119 if (acpi_dev && device_is_attached(child) && 1120 dinfo->cfg.hdrtype == 0) { 1121 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 1122 pci_set_powerstate(child, PCI_POWERSTATE_D0); 1123 } 1124 1125 /* Now the device is powered up, restore its config space. */ 1126 pci_cfg_restore(child, dinfo); 1127 } 1128 free(devlist, M_TEMP); 1129 return (bus_generic_resume(dev)); 1130 } 1131 1132 static void 1133 pci_load_vendor_data(void) 1134 { 1135 caddr_t vendordata, info; 1136 1137 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1138 info = preload_search_info(vendordata, MODINFO_ADDR); 1139 pci_vendordata = *(char **)info; 1140 info = preload_search_info(vendordata, MODINFO_SIZE); 1141 pci_vendordata_size = *(size_t *)info; 1142 /* terminate the database */ 1143 pci_vendordata[pci_vendordata_size] = '\n'; 1144 } 1145 } 1146 1147 void 1148 pci_driver_added(device_t dev, driver_t *driver) 1149 { 1150 int numdevs; 1151 device_t *devlist; 1152 device_t child; 1153 struct pci_devinfo *dinfo; 1154 int i; 1155 1156 if (bootverbose) 1157 device_printf(dev, "driver added\n"); 1158 DEVICE_IDENTIFY(driver, dev); 1159 device_get_children(dev, &devlist, &numdevs); 1160 for (i = 0; i < numdevs; i++) { 1161 child = devlist[i]; 1162 if (device_get_state(child) != DS_NOTPRESENT) 1163 continue; 1164 dinfo = device_get_ivars(child); 1165 pci_print_verbose(dinfo); 1166 if (bootverbose) 1167 printf("pci%d:%d:%d: reprobing on driver added\n", 1168 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1169 pci_cfg_restore(child, dinfo); 1170 if (device_probe_and_attach(child) != 0) 1171 pci_cfg_save(child, dinfo, 1); 1172 } 1173 free(devlist, M_TEMP); 1174 } 1175 1176 int 1177 pci_print_child(device_t dev, device_t child) 1178 { 1179 struct pci_devinfo *dinfo; 1180 struct resource_list *rl; 1181 int retval = 0; 1182 1183 dinfo = device_get_ivars(child); 1184 rl = &dinfo->resources; 1185 1186 retval += bus_print_child_header(dev, child); 1187 1188 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1189 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1190 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1191 if (device_get_flags(dev)) 1192 retval += printf(" flags %#x", device_get_flags(dev)); 1193 1194 retval += printf(" at device %d.%d", pci_get_slot(child), 1195 pci_get_function(child)); 1196 1197 retval += bus_print_child_footer(dev, child); 1198 1199 return (retval); 1200 } 1201 1202 static struct 1203 { 1204 int class; 1205 int subclass; 1206 char *desc; 1207 } pci_nomatch_tab[] = { 1208 {PCIC_OLD, -1, "old"}, 1209 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1210 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1211 {PCIC_STORAGE, -1, "mass storage"}, 1212 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1213 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1214 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1215 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1216 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1217 {PCIC_NETWORK, -1, "network"}, 1218 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1219 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1220 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1221 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1222 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"}, 1223 {PCIC_DISPLAY, -1, "display"}, 1224 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1225 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1226 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"}, 1227 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1228 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1229 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1230 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"}, 1231 {PCIC_MEMORY, -1, "memory"}, 1232 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1233 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1234 {PCIC_BRIDGE, -1, "bridge"}, 1235 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1236 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1237 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1238 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1239 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1240 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1241 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1242 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1243 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"}, 1244 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1245 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1246 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1247 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"}, 1248 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"}, 1249 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1250 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1251 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1252 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1253 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1254 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"}, 1255 {PCIC_INPUTDEV, -1, "input device"}, 1256 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1257 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1258 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1259 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"}, 1260 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"}, 1261 {PCIC_DOCKING, -1, "docking station"}, 1262 {PCIC_PROCESSOR, -1, "processor"}, 1263 {PCIC_SERIALBUS, -1, "serial bus"}, 1264 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1265 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1266 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1267 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1268 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1269 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1270 {PCIC_WIRELESS, -1, "wireless controller"}, 1271 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"}, 1272 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"}, 1273 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"}, 1274 {PCIC_INTELLIIO, -1, "intelligent I/O controller"}, 1275 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"}, 1276 {PCIC_SATCOM, -1, "satellite communication"}, 1277 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"}, 1278 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"}, 1279 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"}, 1280 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"}, 1281 {PCIC_CRYPTO, -1, "encrypt/decrypt"}, 1282 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"}, 1283 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "entertainment crypto"}, 1284 {PCIC_DASP, -1, "dasp"}, 1285 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"}, 1286 {0, 0, NULL} 1287 }; 1288 1289 void 1290 pci_probe_nomatch(device_t dev, device_t child) 1291 { 1292 int i; 1293 char *cp, *scp, *device; 1294 1295 /* 1296 * Look for a listing for this device in a loaded device database. 1297 */ 1298 if ((device = pci_describe_device(child)) != NULL) { 1299 device_printf(dev, "<%s>", device); 1300 free(device, M_DEVBUF); 1301 } else { 1302 /* 1303 * Scan the class/subclass descriptions for a general 1304 * description. 1305 */ 1306 cp = "unknown"; 1307 scp = NULL; 1308 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1309 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1310 if (pci_nomatch_tab[i].subclass == -1) { 1311 cp = pci_nomatch_tab[i].desc; 1312 } else if (pci_nomatch_tab[i].subclass == 1313 pci_get_subclass(child)) { 1314 scp = pci_nomatch_tab[i].desc; 1315 } 1316 } 1317 } 1318 device_printf(dev, "<%s%s%s>", 1319 cp ? cp : "", 1320 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1321 scp ? scp : ""); 1322 } 1323 printf(" at device %d.%d (no driver attached)\n", 1324 pci_get_slot(child), pci_get_function(child)); 1325 if (pci_do_powerstate) 1326 pci_cfg_save(child, 1327 (struct pci_devinfo *) device_get_ivars(child), 1); 1328 return; 1329 } 1330 1331 /* 1332 * Parse the PCI device database, if loaded, and return a pointer to a 1333 * description of the device. 1334 * 1335 * The database is flat text formatted as follows: 1336 * 1337 * Any line not in a valid format is ignored. 1338 * Lines are terminated with newline '\n' characters. 1339 * 1340 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1341 * the vendor name. 1342 * 1343 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1344 * - devices cannot be listed without a corresponding VENDOR line. 1345 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1346 * another TAB, then the device name. 1347 */ 1348 1349 /* 1350 * Assuming (ptr) points to the beginning of a line in the database, 1351 * return the vendor or device and description of the next entry. 1352 * The value of (vendor) or (device) inappropriate for the entry type 1353 * is set to -1. Returns nonzero at the end of the database. 1354 * 1355 * Note that this is slightly unrobust in the face of corrupt data; 1356 * we attempt to safeguard against this by spamming the end of the 1357 * database with a newline when we initialise. 1358 */ 1359 static int 1360 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1361 { 1362 char *cp = *ptr; 1363 int left; 1364 1365 *device = -1; 1366 *vendor = -1; 1367 **desc = '\0'; 1368 for (;;) { 1369 left = pci_vendordata_size - (cp - pci_vendordata); 1370 if (left <= 0) { 1371 *ptr = cp; 1372 return(1); 1373 } 1374 1375 /* vendor entry? */ 1376 if (*cp != '\t' && 1377 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1378 break; 1379 /* device entry? */ 1380 if (*cp == '\t' && 1381 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1382 break; 1383 1384 /* skip to next line */ 1385 while (*cp != '\n' && left > 0) { 1386 cp++; 1387 left--; 1388 } 1389 if (*cp == '\n') { 1390 cp++; 1391 left--; 1392 } 1393 } 1394 /* skip to next line */ 1395 while (*cp != '\n' && left > 0) { 1396 cp++; 1397 left--; 1398 } 1399 if (*cp == '\n' && left > 0) 1400 cp++; 1401 *ptr = cp; 1402 return(0); 1403 } 1404 1405 static char * 1406 pci_describe_device(device_t dev) 1407 { 1408 int vendor, device; 1409 char *desc, *vp, *dp, *line; 1410 1411 desc = vp = dp = NULL; 1412 1413 /* 1414 * If we have no vendor data, we can't do anything. 1415 */ 1416 if (pci_vendordata == NULL) 1417 goto out; 1418 1419 /* 1420 * Scan the vendor data looking for this device 1421 */ 1422 line = pci_vendordata; 1423 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1424 goto out; 1425 for (;;) { 1426 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1427 goto out; 1428 if (vendor == pci_get_vendor(dev)) 1429 break; 1430 } 1431 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1432 goto out; 1433 for (;;) { 1434 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1435 *dp = 0; 1436 break; 1437 } 1438 if (vendor != -1) { 1439 *dp = 0; 1440 break; 1441 } 1442 if (device == pci_get_device(dev)) 1443 break; 1444 } 1445 if (dp[0] == '\0') 1446 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1447 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1448 NULL) 1449 sprintf(desc, "%s, %s", vp, dp); 1450 out: 1451 if (vp != NULL) 1452 free(vp, M_DEVBUF); 1453 if (dp != NULL) 1454 free(dp, M_DEVBUF); 1455 return(desc); 1456 } 1457 1458 int 1459 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1460 { 1461 struct pci_devinfo *dinfo; 1462 pcicfgregs *cfg; 1463 1464 dinfo = device_get_ivars(child); 1465 cfg = &dinfo->cfg; 1466 1467 switch (which) { 1468 case PCI_IVAR_ETHADDR: 1469 /* 1470 * The generic accessor doesn't deal with failure, so 1471 * we set the return value, then return an error. 1472 */ 1473 *((uint8_t **) result) = NULL; 1474 return (EINVAL); 1475 case PCI_IVAR_SUBVENDOR: 1476 *result = cfg->subvendor; 1477 break; 1478 case PCI_IVAR_SUBDEVICE: 1479 *result = cfg->subdevice; 1480 break; 1481 case PCI_IVAR_VENDOR: 1482 *result = cfg->vendor; 1483 break; 1484 case PCI_IVAR_DEVICE: 1485 *result = cfg->device; 1486 break; 1487 case PCI_IVAR_DEVID: 1488 *result = (cfg->device << 16) | cfg->vendor; 1489 break; 1490 case PCI_IVAR_CLASS: 1491 *result = cfg->baseclass; 1492 break; 1493 case PCI_IVAR_SUBCLASS: 1494 *result = cfg->subclass; 1495 break; 1496 case PCI_IVAR_PROGIF: 1497 *result = cfg->progif; 1498 break; 1499 case PCI_IVAR_REVID: 1500 *result = cfg->revid; 1501 break; 1502 case PCI_IVAR_INTPIN: 1503 *result = cfg->intpin; 1504 break; 1505 case PCI_IVAR_IRQ: 1506 *result = cfg->intline; 1507 break; 1508 case PCI_IVAR_BUS: 1509 *result = cfg->bus; 1510 break; 1511 case PCI_IVAR_SLOT: 1512 *result = cfg->slot; 1513 break; 1514 case PCI_IVAR_FUNCTION: 1515 *result = cfg->func; 1516 break; 1517 default: 1518 return (ENOENT); 1519 } 1520 return (0); 1521 } 1522 1523 int 1524 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1525 { 1526 struct pci_devinfo *dinfo; 1527 1528 dinfo = device_get_ivars(child); 1529 1530 switch (which) { 1531 case PCI_IVAR_INTPIN: 1532 dinfo->cfg.intpin = value; 1533 return (0); 1534 case PCI_IVAR_ETHADDR: 1535 case PCI_IVAR_SUBVENDOR: 1536 case PCI_IVAR_SUBDEVICE: 1537 case PCI_IVAR_VENDOR: 1538 case PCI_IVAR_DEVICE: 1539 case PCI_IVAR_DEVID: 1540 case PCI_IVAR_CLASS: 1541 case PCI_IVAR_SUBCLASS: 1542 case PCI_IVAR_PROGIF: 1543 case PCI_IVAR_REVID: 1544 case PCI_IVAR_IRQ: 1545 case PCI_IVAR_BUS: 1546 case PCI_IVAR_SLOT: 1547 case PCI_IVAR_FUNCTION: 1548 return (EINVAL); /* disallow for now */ 1549 1550 default: 1551 return (ENOENT); 1552 } 1553 } 1554 1555 1556 #include "opt_ddb.h" 1557 #ifdef DDB 1558 #include <ddb/ddb.h> 1559 #include <sys/cons.h> 1560 1561 /* 1562 * List resources based on pci map registers, used for within ddb 1563 */ 1564 1565 DB_SHOW_COMMAND(pciregs, db_pci_dump) 1566 { 1567 struct pci_devinfo *dinfo; 1568 struct devlist *devlist_head; 1569 struct pci_conf *p; 1570 const char *name; 1571 int i, error, none_count, quit; 1572 1573 none_count = 0; 1574 /* get the head of the device queue */ 1575 devlist_head = &pci_devq; 1576 1577 /* 1578 * Go through the list of devices and print out devices 1579 */ 1580 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 1581 for (error = 0, i = 0, quit = 0, 1582 dinfo = STAILQ_FIRST(devlist_head); 1583 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1584 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1585 1586 /* Populate pd_name and pd_unit */ 1587 name = NULL; 1588 if (dinfo->cfg.dev) 1589 name = device_get_name(dinfo->cfg.dev); 1590 1591 p = &dinfo->conf; 1592 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1593 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1594 (name && *name) ? name : "none", 1595 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1596 none_count++, 1597 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1598 p->pc_sel.pc_func, (p->pc_class << 16) | 1599 (p->pc_subclass << 8) | p->pc_progif, 1600 (p->pc_subdevice << 16) | p->pc_subvendor, 1601 (p->pc_device << 16) | p->pc_vendor, 1602 p->pc_revid, p->pc_hdr); 1603 } 1604 } 1605 #endif /* DDB */ 1606 1607 static struct resource * 1608 pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1609 u_long start, u_long end, u_long count, u_int flags) 1610 { 1611 struct pci_devinfo *dinfo = device_get_ivars(child); 1612 struct resource_list *rl = &dinfo->resources; 1613 struct resource_list_entry *rle; 1614 struct resource *res; 1615 uint32_t map, testval; 1616 int mapsize; 1617 1618 /* 1619 * Weed out the bogons, and figure out how large the BAR/map 1620 * is. Bars that read back 0 here are bogus and unimplemented. 1621 * Note: atapci in legacy mode are special and handled elsewhere 1622 * in the code. If you have a atapci device in legacy mode and 1623 * it fails here, that other code is broken. 1624 */ 1625 res = NULL; 1626 map = pci_read_config(child, *rid, 4); 1627 pci_write_config(child, *rid, 0xffffffff, 4); 1628 testval = pci_read_config(child, *rid, 4); 1629 if (pci_mapbase(testval) == 0) 1630 goto out; 1631 if (pci_maptype(testval) & PCI_MAPMEM) { 1632 if (type != SYS_RES_MEMORY) { 1633 if (bootverbose) 1634 device_printf(child, 1635 "rid %#x is memory, requested %d\n", 1636 *rid, type); 1637 goto out; 1638 } 1639 } else { 1640 if (type != SYS_RES_IOPORT) { 1641 if (bootverbose) 1642 device_printf(child, 1643 "rid %#x is ioport, requested %d\n", 1644 *rid, type); 1645 goto out; 1646 } 1647 } 1648 /* 1649 * For real BARs, we need to override the size that 1650 * the driver requests, because that's what the BAR 1651 * actually uses and we would otherwise have a 1652 * situation where we might allocate the excess to 1653 * another driver, which won't work. 1654 */ 1655 mapsize = pci_mapsize(testval); 1656 count = 1 << mapsize; 1657 if (RF_ALIGNMENT(flags) < mapsize) 1658 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1659 1660 /* 1661 * Allocate enough resource, and then write back the 1662 * appropriate bar for that resource. 1663 */ 1664 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1665 start, end, count, flags); 1666 if (res == NULL) { 1667 device_printf(child, "%#lx bytes of rid %#x res %d failed.\n", 1668 count, *rid, type); 1669 goto out; 1670 } 1671 resource_list_add(rl, type, *rid, start, end, count); 1672 rle = resource_list_find(rl, type, *rid); 1673 if (rle == NULL) 1674 panic("pci_alloc_map: unexpectedly can't find resource."); 1675 rle->res = res; 1676 if (bootverbose) 1677 device_printf(child, 1678 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1679 count, *rid, type, rman_get_start(res)); 1680 map = rman_get_start(res); 1681 out:; 1682 pci_write_config(child, *rid, map, 4); 1683 return (res); 1684 } 1685 1686 1687 struct resource * 1688 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1689 u_long start, u_long end, u_long count, u_int flags) 1690 { 1691 struct pci_devinfo *dinfo = device_get_ivars(child); 1692 struct resource_list *rl = &dinfo->resources; 1693 struct resource_list_entry *rle; 1694 pcicfgregs *cfg = &dinfo->cfg; 1695 1696 /* 1697 * Perform lazy resource allocation 1698 */ 1699 if (device_get_parent(child) == dev) { 1700 switch (type) { 1701 case SYS_RES_IRQ: 1702 /* 1703 * If the child device doesn't have an 1704 * interrupt routed and is deserving of an 1705 * interrupt, try to assign it one. 1706 */ 1707 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1708 (cfg->intpin != 0)) { 1709 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1710 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1711 pci_write_config(child, PCIR_INTLINE, 1712 cfg->intline, 1); 1713 resource_list_add(rl, SYS_RES_IRQ, 0, 1714 cfg->intline, cfg->intline, 1); 1715 } 1716 } 1717 break; 1718 case SYS_RES_IOPORT: 1719 case SYS_RES_MEMORY: 1720 if (*rid < PCIR_BAR(cfg->nummaps)) { 1721 /* 1722 * Enable the I/O mode. We should 1723 * also be assigning resources too 1724 * when none are present. The 1725 * resource_list_alloc kind of sorta does 1726 * this... 1727 */ 1728 if (PCI_ENABLE_IO(dev, child, type)) 1729 return (NULL); 1730 } 1731 rle = resource_list_find(rl, type, *rid); 1732 if (rle == NULL) 1733 return (pci_alloc_map(dev, child, type, rid, 1734 start, end, count, flags)); 1735 break; 1736 } 1737 /* 1738 * If we've already allocated the resource, then 1739 * return it now. But first we may need to activate 1740 * it, since we don't allocate the resource as active 1741 * above. Normally this would be done down in the 1742 * nexus, but since we short-circuit that path we have 1743 * to do its job here. Not sure if we should free the 1744 * resource if it fails to activate. 1745 */ 1746 rle = resource_list_find(rl, type, *rid); 1747 if (rle != NULL && rle->res != NULL) { 1748 if (bootverbose) 1749 device_printf(child, 1750 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 1751 rman_get_size(rle->res), *rid, type, 1752 rman_get_start(rle->res)); 1753 if ((flags & RF_ACTIVE) && 1754 bus_generic_activate_resource(dev, child, type, 1755 *rid, rle->res) != 0) 1756 return NULL; 1757 return (rle->res); 1758 } 1759 } 1760 return (resource_list_alloc(rl, dev, child, type, rid, 1761 start, end, count, flags)); 1762 } 1763 1764 void 1765 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1766 { 1767 struct pci_devinfo *dinfo; 1768 struct resource_list *rl; 1769 struct resource_list_entry *rle; 1770 1771 if (device_get_parent(child) != dev) 1772 return; 1773 1774 dinfo = device_get_ivars(child); 1775 rl = &dinfo->resources; 1776 rle = resource_list_find(rl, type, rid); 1777 if (rle) { 1778 if (rle->res) { 1779 if (rman_get_device(rle->res) != dev || 1780 rman_get_flags(rle->res) & RF_ACTIVE) { 1781 device_printf(dev, "delete_resource: " 1782 "Resource still owned by child, oops. " 1783 "(type=%d, rid=%d, addr=%lx)\n", 1784 rle->type, rle->rid, 1785 rman_get_start(rle->res)); 1786 return; 1787 } 1788 bus_release_resource(dev, type, rid, rle->res); 1789 } 1790 resource_list_delete(rl, type, rid); 1791 } 1792 /* 1793 * Why do we turn off the PCI configuration BAR when we delete a 1794 * resource? -- imp 1795 */ 1796 pci_write_config(child, rid, 0, 4); 1797 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1798 } 1799 1800 struct resource_list * 1801 pci_get_resource_list (device_t dev, device_t child) 1802 { 1803 struct pci_devinfo *dinfo = device_get_ivars(child); 1804 1805 return (&dinfo->resources); 1806 } 1807 1808 uint32_t 1809 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1810 { 1811 struct pci_devinfo *dinfo = device_get_ivars(child); 1812 pcicfgregs *cfg = &dinfo->cfg; 1813 1814 return (PCIB_READ_CONFIG(device_get_parent(dev), 1815 cfg->bus, cfg->slot, cfg->func, reg, width)); 1816 } 1817 1818 void 1819 pci_write_config_method(device_t dev, device_t child, int reg, 1820 uint32_t val, int width) 1821 { 1822 struct pci_devinfo *dinfo = device_get_ivars(child); 1823 pcicfgregs *cfg = &dinfo->cfg; 1824 1825 PCIB_WRITE_CONFIG(device_get_parent(dev), 1826 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1827 } 1828 1829 int 1830 pci_child_location_str_method(device_t dev, device_t child, char *buf, 1831 size_t buflen) 1832 { 1833 1834 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1835 pci_get_function(child)); 1836 return (0); 1837 } 1838 1839 int 1840 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1841 size_t buflen) 1842 { 1843 struct pci_devinfo *dinfo; 1844 pcicfgregs *cfg; 1845 1846 dinfo = device_get_ivars(child); 1847 cfg = &dinfo->cfg; 1848 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1849 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1850 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1851 cfg->progif); 1852 return (0); 1853 } 1854 1855 int 1856 pci_assign_interrupt_method(device_t dev, device_t child) 1857 { 1858 struct pci_devinfo *dinfo = device_get_ivars(child); 1859 pcicfgregs *cfg = &dinfo->cfg; 1860 1861 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1862 cfg->intpin)); 1863 } 1864 1865 static int 1866 pci_modevent(module_t mod, int what, void *arg) 1867 { 1868 static struct cdev *pci_cdev; 1869 1870 switch (what) { 1871 case MOD_LOAD: 1872 STAILQ_INIT(&pci_devq); 1873 pci_generation = 0; 1874 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1875 "pci"); 1876 pci_load_vendor_data(); 1877 break; 1878 1879 case MOD_UNLOAD: 1880 destroy_dev(pci_cdev); 1881 break; 1882 } 1883 1884 return (0); 1885 } 1886 1887 void 1888 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 1889 { 1890 int i; 1891 1892 /* 1893 * Only do header type 0 devices. Type 1 devices are bridges, 1894 * which we know need special treatment. Type 2 devices are 1895 * cardbus bridges which also require special treatment. 1896 * Other types are unknown, and we err on the side of safety 1897 * by ignoring them. 1898 */ 1899 if (dinfo->cfg.hdrtype != 0) 1900 return; 1901 1902 /* 1903 * Restore the device to full power mode. We must do this 1904 * before we restore the registers because moving from D3 to 1905 * D0 will cause the chip's BARs and some other registers to 1906 * be reset to some unknown power on reset values. Cut down 1907 * the noise on boot by doing nothing if we are already in 1908 * state D0. 1909 */ 1910 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1911 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1912 } 1913 for (i = 0; i < dinfo->cfg.nummaps; i++) 1914 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 1915 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 1916 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 1917 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 1918 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 1919 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 1920 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 1921 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 1922 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 1923 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 1924 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 1925 } 1926 1927 void 1928 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 1929 { 1930 int i; 1931 uint32_t cls; 1932 int ps; 1933 1934 /* 1935 * Only do header type 0 devices. Type 1 devices are bridges, which 1936 * we know need special treatment. Type 2 devices are cardbus bridges 1937 * which also require special treatment. Other types are unknown, and 1938 * we err on the side of safety by ignoring them. Powering down 1939 * bridges should not be undertaken lightly. 1940 */ 1941 if (dinfo->cfg.hdrtype != 0) 1942 return; 1943 for (i = 0; i < dinfo->cfg.nummaps; i++) 1944 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1945 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 1946 1947 /* 1948 * Some drivers apparently write to these registers w/o updating our 1949 * cached copy. No harm happens if we update the copy, so do so here 1950 * so we can restore them. The COMMAND register is modified by the 1951 * bus w/o updating the cache. This should represent the normally 1952 * writable portion of the 'defined' part of type 0 headers. In 1953 * theory we also need to save/restore the PCI capability structures 1954 * we know about, but apart from power we don't know any that are 1955 * writable. 1956 */ 1957 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1958 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1959 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 1960 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 1961 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 1962 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 1963 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 1964 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 1965 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 1966 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1967 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1968 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 1969 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 1970 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 1971 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 1972 1973 /* 1974 * don't set the state for display devices, base peripherals and 1975 * memory devices since bad things happen when they are powered down. 1976 * We should (a) have drivers that can easily detach and (b) use 1977 * generic drivers for these devices so that some device actually 1978 * attaches. We need to make sure that when we implement (a) we don't 1979 * power the device down on a reattach. 1980 */ 1981 cls = pci_get_class(dev); 1982 if (setstate && cls != PCIC_DISPLAY && cls != PCIC_MEMORY && 1983 cls != PCIC_BASEPERIPH) { 1984 /* 1985 * PCI spec says we can only go into D3 state from D0 state. 1986 * Transition from D[12] into D0 before going to D3 state. 1987 */ 1988 ps = pci_get_powerstate(dev); 1989 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) { 1990 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1991 } 1992 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) { 1993 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 1994 } 1995 } 1996 } 1997