1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/linker.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/sysctl.h> 44 #include <sys/types.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 55 #include <sys/pciio.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pci_private.h> 59 60 #include "pcib_if.h" 61 #include "pci_if.h" 62 63 static uint32_t pci_mapbase(unsigned mapreg); 64 static int pci_maptype(unsigned mapreg); 65 static int pci_mapsize(unsigned testval); 66 static int pci_maprange(unsigned mapreg); 67 static void pci_fixancient(pcicfgregs *cfg); 68 69 static int pci_porten(device_t pcib, int b, int s, int f); 70 static int pci_memen(device_t pcib, int b, int s, int f); 71 static int pci_add_map(device_t pcib, device_t bus, device_t dev, 72 int b, int s, int f, int reg, 73 struct resource_list *rl); 74 static void pci_add_resources(device_t pcib, device_t bus, 75 device_t dev); 76 static int pci_probe(device_t dev); 77 static int pci_attach(device_t dev); 78 static void pci_load_vendor_data(void); 79 static int pci_describe_parse_line(char **ptr, int *vendor, 80 int *device, char **desc); 81 static char *pci_describe_device(device_t dev); 82 static int pci_modevent(module_t mod, int what, void *arg); 83 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 84 pcicfgregs *cfg); 85 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 86 static void pci_cfg_restore(device_t, struct pci_devinfo *); 87 static void pci_cfg_save(device_t, struct pci_devinfo *, int); 88 89 static device_method_t pci_methods[] = { 90 /* Device interface */ 91 DEVMETHOD(device_probe, pci_probe), 92 DEVMETHOD(device_attach, pci_attach), 93 DEVMETHOD(device_shutdown, bus_generic_shutdown), 94 DEVMETHOD(device_suspend, pci_suspend), 95 DEVMETHOD(device_resume, pci_resume), 96 97 /* Bus interface */ 98 DEVMETHOD(bus_print_child, pci_print_child), 99 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 100 DEVMETHOD(bus_read_ivar, pci_read_ivar), 101 DEVMETHOD(bus_write_ivar, pci_write_ivar), 102 DEVMETHOD(bus_driver_added, pci_driver_added), 103 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 104 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 105 106 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 107 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 108 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 109 DEVMETHOD(bus_delete_resource, pci_delete_resource), 110 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 111 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 112 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 113 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 114 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 115 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 116 117 /* PCI interface */ 118 DEVMETHOD(pci_read_config, pci_read_config_method), 119 DEVMETHOD(pci_write_config, pci_write_config_method), 120 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 121 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 122 DEVMETHOD(pci_enable_io, pci_enable_io_method), 123 DEVMETHOD(pci_disable_io, pci_disable_io_method), 124 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 125 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 126 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 127 128 { 0, 0 } 129 }; 130 131 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 132 133 devclass_t pci_devclass; 134 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 135 MODULE_VERSION(pci, 1); 136 137 static char *pci_vendordata; 138 static size_t pci_vendordata_size; 139 140 141 struct pci_quirk { 142 uint32_t devid; /* Vendor/device of the card */ 143 int type; 144 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 145 int arg1; 146 int arg2; 147 }; 148 149 struct pci_quirk pci_quirks[] = { 150 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 151 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 152 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 153 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 154 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 155 156 { 0 } 157 }; 158 159 /* map register information */ 160 #define PCI_MAPMEM 0x01 /* memory map */ 161 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 162 #define PCI_MAPPORT 0x04 /* port map */ 163 164 struct devlist pci_devq; 165 uint32_t pci_generation; 166 uint32_t pci_numdevs = 0; 167 168 /* sysctl vars */ 169 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 170 171 static int pci_enable_io_modes = 1; 172 TUNABLE_INT("hw.pci.enable_io_modes", (int *)&pci_enable_io_modes); 173 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 174 &pci_enable_io_modes, 1, 175 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 176 enable these bits correctly. We'd like to do this all the time, but there\n\ 177 are some peripherals that this causes problems with."); 178 179 static int pci_do_powerstate = 0; 180 TUNABLE_INT("hw.pci.do_powerstate", (int *)&pci_do_powerstate); 181 SYSCTL_INT(_hw_pci, OID_AUTO, do_powerstate, CTLFLAG_RW, 182 &pci_do_powerstate, 0, 183 "Power down devices into D3 state when no driver attaches to them.\n\ 184 Otherwise, leave the device in D0 state when no driver attaches."); 185 186 /* Find a device_t by bus/slot/function */ 187 188 device_t 189 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 190 { 191 struct pci_devinfo *dinfo; 192 193 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 194 if ((dinfo->cfg.bus == bus) && 195 (dinfo->cfg.slot == slot) && 196 (dinfo->cfg.func == func)) { 197 return (dinfo->cfg.dev); 198 } 199 } 200 201 return (NULL); 202 } 203 204 /* Find a device_t by vendor/device ID */ 205 206 device_t 207 pci_find_device(uint16_t vendor, uint16_t device) 208 { 209 struct pci_devinfo *dinfo; 210 211 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 212 if ((dinfo->cfg.vendor == vendor) && 213 (dinfo->cfg.device == device)) { 214 return (dinfo->cfg.dev); 215 } 216 } 217 218 return (NULL); 219 } 220 221 /* return base address of memory or port map */ 222 223 static uint32_t 224 pci_mapbase(unsigned mapreg) 225 { 226 int mask = 0x03; 227 if ((mapreg & 0x01) == 0) 228 mask = 0x0f; 229 return (mapreg & ~mask); 230 } 231 232 /* return map type of memory or port map */ 233 234 static int 235 pci_maptype(unsigned mapreg) 236 { 237 static uint8_t maptype[0x10] = { 238 PCI_MAPMEM, PCI_MAPPORT, 239 PCI_MAPMEM, 0, 240 PCI_MAPMEM, PCI_MAPPORT, 241 0, 0, 242 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 243 PCI_MAPMEM|PCI_MAPMEMP, 0, 244 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 245 0, 0, 246 }; 247 248 return maptype[mapreg & 0x0f]; 249 } 250 251 /* return log2 of map size decoded for memory or port map */ 252 253 static int 254 pci_mapsize(unsigned testval) 255 { 256 int ln2size; 257 258 testval = pci_mapbase(testval); 259 ln2size = 0; 260 if (testval != 0) { 261 while ((testval & 1) == 0) 262 { 263 ln2size++; 264 testval >>= 1; 265 } 266 } 267 return (ln2size); 268 } 269 270 /* return log2 of address range supported by map register */ 271 272 static int 273 pci_maprange(unsigned mapreg) 274 { 275 int ln2range = 0; 276 switch (mapreg & 0x07) { 277 case 0x00: 278 case 0x01: 279 case 0x05: 280 ln2range = 32; 281 break; 282 case 0x02: 283 ln2range = 20; 284 break; 285 case 0x04: 286 ln2range = 64; 287 break; 288 } 289 return (ln2range); 290 } 291 292 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 293 294 static void 295 pci_fixancient(pcicfgregs *cfg) 296 { 297 if (cfg->hdrtype != 0) 298 return; 299 300 /* PCI to PCI bridges use header type 1 */ 301 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 302 cfg->hdrtype = 1; 303 } 304 305 /* extract header type specific config data */ 306 307 static void 308 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 309 { 310 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 311 switch (cfg->hdrtype) { 312 case 0: 313 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 314 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 315 cfg->nummaps = PCI_MAXMAPS_0; 316 break; 317 case 1: 318 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 319 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 320 cfg->nummaps = PCI_MAXMAPS_1; 321 break; 322 case 2: 323 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 324 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 325 cfg->nummaps = PCI_MAXMAPS_2; 326 break; 327 } 328 #undef REG 329 } 330 331 /* read configuration header into pcicfgregs structure */ 332 333 struct pci_devinfo * 334 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 335 { 336 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 337 pcicfgregs *cfg = NULL; 338 struct pci_devinfo *devlist_entry; 339 struct devlist *devlist_head; 340 341 devlist_head = &pci_devq; 342 343 devlist_entry = NULL; 344 345 if (REG(PCIR_DEVVENDOR, 4) != -1) { 346 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 347 if (devlist_entry == NULL) 348 return (NULL); 349 350 cfg = &devlist_entry->cfg; 351 352 cfg->bus = b; 353 cfg->slot = s; 354 cfg->func = f; 355 cfg->vendor = REG(PCIR_VENDOR, 2); 356 cfg->device = REG(PCIR_DEVICE, 2); 357 cfg->cmdreg = REG(PCIR_COMMAND, 2); 358 cfg->statreg = REG(PCIR_STATUS, 2); 359 cfg->baseclass = REG(PCIR_CLASS, 1); 360 cfg->subclass = REG(PCIR_SUBCLASS, 1); 361 cfg->progif = REG(PCIR_PROGIF, 1); 362 cfg->revid = REG(PCIR_REVID, 1); 363 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 364 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 365 cfg->lattimer = REG(PCIR_LATTIMER, 1); 366 cfg->intpin = REG(PCIR_INTPIN, 1); 367 cfg->intline = REG(PCIR_INTLINE, 1); 368 369 cfg->mingnt = REG(PCIR_MINGNT, 1); 370 cfg->maxlat = REG(PCIR_MAXLAT, 1); 371 372 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 373 cfg->hdrtype &= ~PCIM_MFDEV; 374 375 pci_fixancient(cfg); 376 pci_hdrtypedata(pcib, b, s, f, cfg); 377 378 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 379 pci_read_extcap(pcib, cfg); 380 381 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 382 383 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 384 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 385 devlist_entry->conf.pc_sel.pc_func = cfg->func; 386 devlist_entry->conf.pc_hdr = cfg->hdrtype; 387 388 devlist_entry->conf.pc_subvendor = cfg->subvendor; 389 devlist_entry->conf.pc_subdevice = cfg->subdevice; 390 devlist_entry->conf.pc_vendor = cfg->vendor; 391 devlist_entry->conf.pc_device = cfg->device; 392 393 devlist_entry->conf.pc_class = cfg->baseclass; 394 devlist_entry->conf.pc_subclass = cfg->subclass; 395 devlist_entry->conf.pc_progif = cfg->progif; 396 devlist_entry->conf.pc_revid = cfg->revid; 397 398 pci_numdevs++; 399 pci_generation++; 400 } 401 return (devlist_entry); 402 #undef REG 403 } 404 405 static void 406 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 407 { 408 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 409 int ptr, nextptr, ptrptr; 410 411 switch (cfg->hdrtype & PCIM_HDRTYPE) { 412 case 0: 413 ptrptr = PCIR_CAP_PTR; 414 break; 415 case 2: 416 ptrptr = 0x14; 417 break; 418 default: 419 return; /* no extended capabilities support */ 420 } 421 nextptr = REG(ptrptr, 1); /* sanity check? */ 422 423 /* 424 * Read capability entries. 425 */ 426 while (nextptr != 0) { 427 /* Sanity check */ 428 if (nextptr > 255) { 429 printf("illegal PCI extended capability offset %d\n", 430 nextptr); 431 return; 432 } 433 /* Find the next entry */ 434 ptr = nextptr; 435 nextptr = REG(ptr + 1, 1); 436 437 /* Process this entry */ 438 switch (REG(ptr, 1)) { 439 case PCIY_PMG: /* PCI power management */ 440 if (cfg->pp.pp_cap == 0) { 441 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 442 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 443 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 444 if ((nextptr - ptr) > PCIR_POWER_DATA) 445 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 446 } 447 break; 448 case PCIY_MSI: /* PCI MSI */ 449 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 450 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 451 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 452 else 453 cfg->msi.msi_data = PCIR_MSI_DATA; 454 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 455 PCIM_MSICTRL_MMC_MASK)>>1); 456 default: 457 break; 458 } 459 } 460 #undef REG 461 } 462 463 /* free pcicfgregs structure and all depending data structures */ 464 465 int 466 pci_freecfg(struct pci_devinfo *dinfo) 467 { 468 struct devlist *devlist_head; 469 470 devlist_head = &pci_devq; 471 472 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 473 free(dinfo, M_DEVBUF); 474 475 /* increment the generation count */ 476 pci_generation++; 477 478 /* we're losing one device */ 479 pci_numdevs--; 480 return (0); 481 } 482 483 /* 484 * PCI power manangement 485 */ 486 int 487 pci_set_powerstate_method(device_t dev, device_t child, int state) 488 { 489 struct pci_devinfo *dinfo = device_get_ivars(child); 490 pcicfgregs *cfg = &dinfo->cfg; 491 uint16_t status; 492 int result; 493 494 /* 495 * Dx -> Dx is a nop always. 496 */ 497 if (pci_get_powerstate(child) == state) 498 return (0); 499 500 if (cfg->pp.pp_cap != 0) { 501 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 502 & ~PCIM_PSTAT_DMASK; 503 result = 0; 504 switch (state) { 505 case PCI_POWERSTATE_D0: 506 status |= PCIM_PSTAT_D0; 507 break; 508 case PCI_POWERSTATE_D1: 509 if (cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) { 510 status |= PCIM_PSTAT_D1; 511 } else { 512 result = EOPNOTSUPP; 513 } 514 break; 515 case PCI_POWERSTATE_D2: 516 if (cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) { 517 status |= PCIM_PSTAT_D2; 518 } else { 519 result = EOPNOTSUPP; 520 } 521 break; 522 case PCI_POWERSTATE_D3: 523 status |= PCIM_PSTAT_D3; 524 break; 525 default: 526 result = EINVAL; 527 } 528 if (result == 0) 529 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 530 2); 531 } else { 532 result = ENXIO; 533 } 534 return(result); 535 } 536 537 int 538 pci_get_powerstate_method(device_t dev, device_t child) 539 { 540 struct pci_devinfo *dinfo = device_get_ivars(child); 541 pcicfgregs *cfg = &dinfo->cfg; 542 uint16_t status; 543 int result; 544 545 if (cfg->pp.pp_cap != 0) { 546 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 547 switch (status & PCIM_PSTAT_DMASK) { 548 case PCIM_PSTAT_D0: 549 result = PCI_POWERSTATE_D0; 550 break; 551 case PCIM_PSTAT_D1: 552 result = PCI_POWERSTATE_D1; 553 break; 554 case PCIM_PSTAT_D2: 555 result = PCI_POWERSTATE_D2; 556 break; 557 case PCIM_PSTAT_D3: 558 result = PCI_POWERSTATE_D3; 559 break; 560 default: 561 result = PCI_POWERSTATE_UNKNOWN; 562 break; 563 } 564 } else { 565 /* No support, device is always at D0 */ 566 result = PCI_POWERSTATE_D0; 567 } 568 return(result); 569 } 570 571 /* 572 * Some convenience functions for PCI device drivers. 573 */ 574 575 static __inline void 576 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 577 { 578 uint16_t command; 579 580 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 581 command |= bit; 582 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 583 } 584 585 static __inline void 586 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 587 { 588 uint16_t command; 589 590 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 591 command &= ~bit; 592 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 593 } 594 595 int 596 pci_enable_busmaster_method(device_t dev, device_t child) 597 { 598 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 599 return (0); 600 } 601 602 int 603 pci_disable_busmaster_method(device_t dev, device_t child) 604 { 605 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 606 return (0); 607 } 608 609 int 610 pci_enable_io_method(device_t dev, device_t child, int space) 611 { 612 uint16_t command; 613 uint16_t bit; 614 char *error; 615 616 bit = 0; 617 error = NULL; 618 619 switch(space) { 620 case SYS_RES_IOPORT: 621 bit = PCIM_CMD_PORTEN; 622 error = "port"; 623 break; 624 case SYS_RES_MEMORY: 625 bit = PCIM_CMD_MEMEN; 626 error = "memory"; 627 break; 628 default: 629 return (EINVAL); 630 } 631 pci_set_command_bit(dev, child, bit); 632 /* Some devices seem to need a brief stall here, what do to? */ 633 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 634 if (command & bit) 635 return (0); 636 device_printf(child, "failed to enable %s mapping!\n", error); 637 return (ENXIO); 638 } 639 640 int 641 pci_disable_io_method(device_t dev, device_t child, int space) 642 { 643 uint16_t command; 644 uint16_t bit; 645 char *error; 646 647 bit = 0; 648 error = NULL; 649 650 switch(space) { 651 case SYS_RES_IOPORT: 652 bit = PCIM_CMD_PORTEN; 653 error = "port"; 654 break; 655 case SYS_RES_MEMORY: 656 bit = PCIM_CMD_MEMEN; 657 error = "memory"; 658 break; 659 default: 660 return (EINVAL); 661 } 662 pci_clear_command_bit(dev, child, bit); 663 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 664 if (command & bit) { 665 device_printf(child, "failed to disable %s mapping!\n", error); 666 return (ENXIO); 667 } 668 return (0); 669 } 670 671 /* 672 * New style pci driver. Parent device is either a pci-host-bridge or a 673 * pci-pci-bridge. Both kinds are represented by instances of pcib. 674 */ 675 676 void 677 pci_print_verbose(struct pci_devinfo *dinfo) 678 { 679 if (bootverbose) { 680 pcicfgregs *cfg = &dinfo->cfg; 681 682 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 683 cfg->vendor, cfg->device, cfg->revid); 684 printf("\tbus=%d, slot=%d, func=%d\n", 685 cfg->bus, cfg->slot, cfg->func); 686 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 687 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 688 cfg->mfdev); 689 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 690 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 691 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 692 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 693 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 694 if (cfg->intpin > 0) 695 printf("\tintpin=%c, irq=%d\n", 696 cfg->intpin +'a' -1, cfg->intline); 697 if (cfg->pp.pp_cap) { 698 uint16_t status; 699 700 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 701 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 702 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 703 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 704 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 705 status & PCIM_PSTAT_DMASK); 706 } 707 if (cfg->msi.msi_data) { 708 int ctrl; 709 710 ctrl = cfg->msi.msi_ctrl; 711 printf("\tMSI supports %d message%s%s%s\n", 712 cfg->msi.msi_msgnum, 713 (cfg->msi.msi_msgnum == 1) ? "" : "s", 714 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 715 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 716 } 717 } 718 } 719 720 static int 721 pci_porten(device_t pcib, int b, int s, int f) 722 { 723 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 724 & PCIM_CMD_PORTEN) != 0; 725 } 726 727 static int 728 pci_memen(device_t pcib, int b, int s, int f) 729 { 730 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 731 & PCIM_CMD_MEMEN) != 0; 732 } 733 734 /* 735 * Add a resource based on a pci map register. Return 1 if the map 736 * register is a 32bit map register or 2 if it is a 64bit register. 737 */ 738 static int 739 pci_add_map(device_t pcib, device_t bus, device_t dev, 740 int b, int s, int f, int reg, struct resource_list *rl) 741 { 742 uint32_t map; 743 uint64_t base; 744 uint64_t start, end, count; 745 uint8_t ln2size; 746 uint8_t ln2range; 747 uint32_t testval; 748 uint16_t cmd; 749 int type; 750 751 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 752 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 753 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 754 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 755 756 if (pci_maptype(map) & PCI_MAPMEM) 757 type = SYS_RES_MEMORY; 758 else 759 type = SYS_RES_IOPORT; 760 ln2size = pci_mapsize(testval); 761 ln2range = pci_maprange(testval); 762 base = pci_mapbase(map); 763 764 /* 765 * For I/O registers, if bottom bit is set, and the next bit up 766 * isn't clear, we know we have a BAR that doesn't conform to the 767 * spec, so ignore it. Also, sanity check the size of the data 768 * areas to the type of memory involved. Memory must be at least 769 * 32 bytes in size, while I/O ranges must be at least 4. 770 */ 771 if ((testval & 0x1) == 0x1 && 772 (testval & 0x2) != 0) 773 return (1); 774 if ((type == SYS_RES_MEMORY && ln2size < 5) || 775 (type == SYS_RES_IOPORT && ln2size < 2)) 776 return (1); 777 778 if (ln2range == 64) 779 /* Read the other half of a 64bit map register */ 780 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 781 782 if (bootverbose) { 783 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 784 reg, pci_maptype(map), ln2range, 785 (unsigned int) base, ln2size); 786 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 787 printf(", port disabled\n"); 788 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 789 printf(", memory disabled\n"); 790 else 791 printf(", enabled\n"); 792 } 793 794 /* 795 * This code theoretically does the right thing, but has 796 * undesirable side effects in some cases where peripherals 797 * respond oddly to having these bits enabled. Let the user 798 * be able to turn them off (since pci_enable_io_modes is 1 by 799 * default). 800 */ 801 if (pci_enable_io_modes) { 802 /* Turn on resources that have been left off by a lazy BIOS */ 803 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 804 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 805 cmd |= PCIM_CMD_PORTEN; 806 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 807 } 808 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 809 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 810 cmd |= PCIM_CMD_MEMEN; 811 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 812 } 813 } else { 814 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 815 return (1); 816 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 817 return (1); 818 } 819 /* 820 * If base is 0, then we have problems. It is best to ignore 821 * such entires for the moment. These will be allocated later if 822 * the driver specifically requests them. 823 */ 824 if (base == 0) 825 return 1; 826 827 start = base; 828 end = base + (1 << ln2size) - 1; 829 count = 1 << ln2size; 830 resource_list_add(rl, type, reg, start, end, count); 831 832 /* 833 * Not quite sure what to do on failure of allocating the resource 834 * since I can postulate several right answers. 835 */ 836 resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 0); 837 return ((ln2range == 64) ? 2 : 1); 838 } 839 840 /* 841 * For ATA devices we need to decide early what addressing mode to use. 842 * Legacy demands that the primary and secondary ATA ports sits on the 843 * same addresses that old ISA hardware did. This dictates that we use 844 * those addresses and ignore the BAR's if we cannot set PCI native 845 * addressing mode. 846 */ 847 static void 848 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 849 int s, int f, struct resource_list *rl) 850 { 851 int rid, type, progif; 852 #if 0 853 /* if this device supports PCI native addressing use it */ 854 progif = pci_read_config(dev, PCIR_PROGIF, 1); 855 if ((progif & 0x8a) == 0x8a) { 856 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 857 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 858 printf("Trying ATA native PCI addressing mode\n"); 859 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 860 } 861 } 862 #endif 863 progif = pci_read_config(dev, PCIR_PROGIF, 1); 864 type = SYS_RES_IOPORT; 865 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 866 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl); 867 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl); 868 } 869 else { 870 rid = PCIR_BAR(0); 871 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 872 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,8,0); 873 rid = PCIR_BAR(1); 874 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 875 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,1,0); 876 } 877 if (progif & PCIP_STORAGE_IDE_MODESEC) { 878 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl); 879 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl); 880 } 881 else { 882 rid = PCIR_BAR(2); 883 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 884 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,8,0); 885 rid = PCIR_BAR(3); 886 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 887 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,1,0); 888 } 889 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl); 890 } 891 892 static void 893 pci_add_resources(device_t pcib, device_t bus, device_t dev) 894 { 895 struct pci_devinfo *dinfo = device_get_ivars(dev); 896 pcicfgregs *cfg = &dinfo->cfg; 897 struct resource_list *rl = &dinfo->resources; 898 struct pci_quirk *q; 899 int b, i, irq, f, s; 900 901 b = cfg->bus; 902 s = cfg->slot; 903 f = cfg->func; 904 905 /* ATA devices needs special map treatment */ 906 if ((pci_get_class(dev) == PCIC_STORAGE) && 907 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 908 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 909 pci_ata_maps(pcib, bus, dev, b, s, f, rl); 910 else 911 for (i = 0; i < cfg->nummaps;) 912 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 913 rl); 914 915 for (q = &pci_quirks[0]; q->devid; q++) { 916 if (q->devid == ((cfg->device << 16) | cfg->vendor) 917 && q->type == PCI_QUIRK_MAP_REG) 918 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl); 919 } 920 921 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 922 #if defined(__ia64__) || defined(__i386__) || defined(__amd64__) || \ 923 defined(__arm__) 924 /* 925 * Try to re-route interrupts. Sometimes the BIOS or 926 * firmware may leave bogus values in these registers. 927 * If the re-route fails, then just stick with what we 928 * have. 929 */ 930 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 931 if (PCI_INTERRUPT_VALID(irq)) { 932 pci_write_config(dev, PCIR_INTLINE, irq, 1); 933 cfg->intline = irq; 934 } else 935 #endif 936 irq = cfg->intline; 937 resource_list_add(rl, SYS_RES_IRQ, 0, irq, irq, 1); 938 } 939 } 940 941 void 942 pci_add_children(device_t dev, int busno, size_t dinfo_size) 943 { 944 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 945 device_t pcib = device_get_parent(dev); 946 struct pci_devinfo *dinfo; 947 int maxslots; 948 int s, f, pcifunchigh; 949 uint8_t hdrtype; 950 951 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 952 ("dinfo_size too small")); 953 maxslots = PCIB_MAXSLOTS(pcib); 954 for (s = 0; s <= maxslots; s++) { 955 pcifunchigh = 0; 956 f = 0; 957 hdrtype = REG(PCIR_HDRTYPE, 1); 958 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 959 continue; 960 if (hdrtype & PCIM_MFDEV) 961 pcifunchigh = PCI_FUNCMAX; 962 for (f = 0; f <= pcifunchigh; f++) { 963 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 964 if (dinfo != NULL) { 965 pci_add_child(dev, dinfo); 966 } 967 } 968 } 969 #undef REG 970 } 971 972 void 973 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 974 { 975 device_t pcib; 976 977 pcib = device_get_parent(bus); 978 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 979 device_set_ivars(dinfo->cfg.dev, dinfo); 980 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 981 pci_cfg_restore(dinfo->cfg.dev, dinfo); 982 pci_add_resources(pcib, bus, dinfo->cfg.dev); 983 pci_print_verbose(dinfo); 984 } 985 986 static int 987 pci_probe(device_t dev) 988 { 989 990 device_set_desc(dev, "PCI bus"); 991 992 /* Allow other subclasses to override this driver. */ 993 return (-1000); 994 } 995 996 static int 997 pci_attach(device_t dev) 998 { 999 int busno; 1000 1001 /* 1002 * Since there can be multiple independantly numbered PCI 1003 * busses on some large alpha systems, we can't use the unit 1004 * number to decide what bus we are probing. We ask the parent 1005 * pcib what our bus number is. 1006 */ 1007 busno = pcib_get_bus(dev); 1008 if (bootverbose) 1009 device_printf(dev, "physical bus=%d\n", busno); 1010 1011 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1012 1013 return (bus_generic_attach(dev)); 1014 } 1015 1016 int 1017 pci_suspend(device_t dev) 1018 { 1019 int numdevs; 1020 device_t *devlist; 1021 device_t child; 1022 struct pci_devinfo *dinfo; 1023 int i; 1024 1025 /* 1026 * Save the pci configuration space for each child. We don't need 1027 * to do this, unless the BIOS suspend code powers down the bus and 1028 * the devices on the bus. 1029 */ 1030 device_get_children(dev, &devlist, &numdevs); 1031 for (i = 0; i < numdevs; i++) { 1032 child = devlist[i]; 1033 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1034 pci_cfg_save(child, dinfo, 0); 1035 } 1036 free(devlist, M_TEMP); 1037 return (bus_generic_suspend(dev)); 1038 } 1039 1040 int 1041 pci_resume(device_t dev) 1042 { 1043 int numdevs; 1044 device_t *devlist; 1045 device_t child; 1046 struct pci_devinfo *dinfo; 1047 int i; 1048 1049 /* 1050 * Restore the pci configuration space for each child. 1051 */ 1052 device_get_children(dev, &devlist, &numdevs); 1053 for (i = 0; i < numdevs; i++) { 1054 child = devlist[i]; 1055 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1056 pci_cfg_restore(child, dinfo); 1057 } 1058 free(devlist, M_TEMP); 1059 return (bus_generic_resume(dev)); 1060 } 1061 1062 static void 1063 pci_load_vendor_data(void) 1064 { 1065 caddr_t vendordata, info; 1066 1067 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1068 info = preload_search_info(vendordata, MODINFO_ADDR); 1069 pci_vendordata = *(char **)info; 1070 info = preload_search_info(vendordata, MODINFO_SIZE); 1071 pci_vendordata_size = *(size_t *)info; 1072 /* terminate the database */ 1073 pci_vendordata[pci_vendordata_size] = '\n'; 1074 } 1075 } 1076 1077 void 1078 pci_driver_added(device_t dev, driver_t *driver) 1079 { 1080 int numdevs; 1081 device_t *devlist; 1082 device_t child; 1083 struct pci_devinfo *dinfo; 1084 int i; 1085 1086 if (bootverbose) 1087 device_printf(dev, "driver added\n"); 1088 DEVICE_IDENTIFY(driver, dev); 1089 device_get_children(dev, &devlist, &numdevs); 1090 for (i = 0; i < numdevs; i++) { 1091 child = devlist[i]; 1092 if (device_get_state(child) != DS_NOTPRESENT) 1093 continue; 1094 dinfo = device_get_ivars(child); 1095 pci_print_verbose(dinfo); 1096 /*XXX???*/ /* resource_list_init(&dinfo->cfg.resources); */ 1097 if (bootverbose) 1098 printf("pci%d:%d:%d: reprobing on driver added\n", 1099 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1100 pci_cfg_restore(child, dinfo); 1101 if (device_probe_and_attach(child) != 0) 1102 pci_cfg_save(child, dinfo, 1); 1103 } 1104 free(devlist, M_TEMP); 1105 } 1106 1107 int 1108 pci_print_child(device_t dev, device_t child) 1109 { 1110 struct pci_devinfo *dinfo; 1111 struct resource_list *rl; 1112 int retval = 0; 1113 1114 dinfo = device_get_ivars(child); 1115 rl = &dinfo->resources; 1116 1117 retval += bus_print_child_header(dev, child); 1118 1119 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1120 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1121 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1122 if (device_get_flags(dev)) 1123 retval += printf(" flags %#x", device_get_flags(dev)); 1124 1125 retval += printf(" at device %d.%d", pci_get_slot(child), 1126 pci_get_function(child)); 1127 1128 retval += bus_print_child_footer(dev, child); 1129 1130 return (retval); 1131 } 1132 1133 static struct 1134 { 1135 int class; 1136 int subclass; 1137 char *desc; 1138 } pci_nomatch_tab[] = { 1139 {PCIC_OLD, -1, "old"}, 1140 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1141 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1142 {PCIC_STORAGE, -1, "mass storage"}, 1143 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1144 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1145 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1146 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1147 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1148 {PCIC_NETWORK, -1, "network"}, 1149 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1150 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1151 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1152 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1153 {PCIC_DISPLAY, -1, "display"}, 1154 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1155 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1156 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1157 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1158 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1159 {PCIC_MEMORY, -1, "memory"}, 1160 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1161 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1162 {PCIC_BRIDGE, -1, "bridge"}, 1163 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1164 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1165 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1166 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1167 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1168 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1169 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1170 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1171 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 1172 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1173 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1174 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1175 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1176 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1177 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1178 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1179 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1180 {PCIC_INPUTDEV, -1, "input device"}, 1181 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1182 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1183 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1184 {PCIC_DOCKING, -1, "docking station"}, 1185 {PCIC_PROCESSOR, -1, "processor"}, 1186 {PCIC_SERIALBUS, -1, "serial bus"}, 1187 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1188 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1189 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1190 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1191 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1192 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1193 {0, 0, NULL} 1194 }; 1195 1196 void 1197 pci_probe_nomatch(device_t dev, device_t child) 1198 { 1199 int i; 1200 char *cp, *scp, *device; 1201 1202 /* 1203 * Look for a listing for this device in a loaded device database. 1204 */ 1205 if ((device = pci_describe_device(child)) != NULL) { 1206 device_printf(dev, "<%s>", device); 1207 free(device, M_DEVBUF); 1208 } else { 1209 /* 1210 * Scan the class/subclass descriptions for a general 1211 * description. 1212 */ 1213 cp = "unknown"; 1214 scp = NULL; 1215 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1216 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1217 if (pci_nomatch_tab[i].subclass == -1) { 1218 cp = pci_nomatch_tab[i].desc; 1219 } else if (pci_nomatch_tab[i].subclass == 1220 pci_get_subclass(child)) { 1221 scp = pci_nomatch_tab[i].desc; 1222 } 1223 } 1224 } 1225 device_printf(dev, "<%s%s%s>", 1226 cp ? cp : "", 1227 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1228 scp ? scp : ""); 1229 } 1230 printf(" at device %d.%d (no driver attached)\n", 1231 pci_get_slot(child), pci_get_function(child)); 1232 if (pci_do_powerstate) 1233 pci_cfg_save(child, 1234 (struct pci_devinfo *) device_get_ivars(child), 1); 1235 return; 1236 } 1237 1238 /* 1239 * Parse the PCI device database, if loaded, and return a pointer to a 1240 * description of the device. 1241 * 1242 * The database is flat text formatted as follows: 1243 * 1244 * Any line not in a valid format is ignored. 1245 * Lines are terminated with newline '\n' characters. 1246 * 1247 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1248 * the vendor name. 1249 * 1250 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1251 * - devices cannot be listed without a corresponding VENDOR line. 1252 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1253 * another TAB, then the device name. 1254 */ 1255 1256 /* 1257 * Assuming (ptr) points to the beginning of a line in the database, 1258 * return the vendor or device and description of the next entry. 1259 * The value of (vendor) or (device) inappropriate for the entry type 1260 * is set to -1. Returns nonzero at the end of the database. 1261 * 1262 * Note that this is slightly unrobust in the face of corrupt data; 1263 * we attempt to safeguard against this by spamming the end of the 1264 * database with a newline when we initialise. 1265 */ 1266 static int 1267 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1268 { 1269 char *cp = *ptr; 1270 int left; 1271 1272 *device = -1; 1273 *vendor = -1; 1274 **desc = '\0'; 1275 for (;;) { 1276 left = pci_vendordata_size - (cp - pci_vendordata); 1277 if (left <= 0) { 1278 *ptr = cp; 1279 return(1); 1280 } 1281 1282 /* vendor entry? */ 1283 if (*cp != '\t' && 1284 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1285 break; 1286 /* device entry? */ 1287 if (*cp == '\t' && 1288 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1289 break; 1290 1291 /* skip to next line */ 1292 while (*cp != '\n' && left > 0) { 1293 cp++; 1294 left--; 1295 } 1296 if (*cp == '\n') { 1297 cp++; 1298 left--; 1299 } 1300 } 1301 /* skip to next line */ 1302 while (*cp != '\n' && left > 0) { 1303 cp++; 1304 left--; 1305 } 1306 if (*cp == '\n' && left > 0) 1307 cp++; 1308 *ptr = cp; 1309 return(0); 1310 } 1311 1312 static char * 1313 pci_describe_device(device_t dev) 1314 { 1315 int vendor, device; 1316 char *desc, *vp, *dp, *line; 1317 1318 desc = vp = dp = NULL; 1319 1320 /* 1321 * If we have no vendor data, we can't do anything. 1322 */ 1323 if (pci_vendordata == NULL) 1324 goto out; 1325 1326 /* 1327 * Scan the vendor data looking for this device 1328 */ 1329 line = pci_vendordata; 1330 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1331 goto out; 1332 for (;;) { 1333 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1334 goto out; 1335 if (vendor == pci_get_vendor(dev)) 1336 break; 1337 } 1338 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1339 goto out; 1340 for (;;) { 1341 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1342 *dp = 0; 1343 break; 1344 } 1345 if (vendor != -1) { 1346 *dp = 0; 1347 break; 1348 } 1349 if (device == pci_get_device(dev)) 1350 break; 1351 } 1352 if (dp[0] == '\0') 1353 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1354 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1355 NULL) 1356 sprintf(desc, "%s, %s", vp, dp); 1357 out: 1358 if (vp != NULL) 1359 free(vp, M_DEVBUF); 1360 if (dp != NULL) 1361 free(dp, M_DEVBUF); 1362 return(desc); 1363 } 1364 1365 int 1366 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1367 { 1368 struct pci_devinfo *dinfo; 1369 pcicfgregs *cfg; 1370 1371 dinfo = device_get_ivars(child); 1372 cfg = &dinfo->cfg; 1373 1374 switch (which) { 1375 case PCI_IVAR_ETHADDR: 1376 /* 1377 * The generic accessor doesn't deal with failure, so 1378 * we set the return value, then return an error. 1379 */ 1380 *((uint8_t **) result) = NULL; 1381 return (EINVAL); 1382 case PCI_IVAR_SUBVENDOR: 1383 *result = cfg->subvendor; 1384 break; 1385 case PCI_IVAR_SUBDEVICE: 1386 *result = cfg->subdevice; 1387 break; 1388 case PCI_IVAR_VENDOR: 1389 *result = cfg->vendor; 1390 break; 1391 case PCI_IVAR_DEVICE: 1392 *result = cfg->device; 1393 break; 1394 case PCI_IVAR_DEVID: 1395 *result = (cfg->device << 16) | cfg->vendor; 1396 break; 1397 case PCI_IVAR_CLASS: 1398 *result = cfg->baseclass; 1399 break; 1400 case PCI_IVAR_SUBCLASS: 1401 *result = cfg->subclass; 1402 break; 1403 case PCI_IVAR_PROGIF: 1404 *result = cfg->progif; 1405 break; 1406 case PCI_IVAR_REVID: 1407 *result = cfg->revid; 1408 break; 1409 case PCI_IVAR_INTPIN: 1410 *result = cfg->intpin; 1411 break; 1412 case PCI_IVAR_IRQ: 1413 *result = cfg->intline; 1414 break; 1415 case PCI_IVAR_BUS: 1416 *result = cfg->bus; 1417 break; 1418 case PCI_IVAR_SLOT: 1419 *result = cfg->slot; 1420 break; 1421 case PCI_IVAR_FUNCTION: 1422 *result = cfg->func; 1423 break; 1424 default: 1425 return (ENOENT); 1426 } 1427 return (0); 1428 } 1429 1430 int 1431 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1432 { 1433 struct pci_devinfo *dinfo; 1434 1435 dinfo = device_get_ivars(child); 1436 1437 switch (which) { 1438 case PCI_IVAR_INTPIN: 1439 dinfo->cfg.intpin = value; 1440 return (0); 1441 case PCI_IVAR_ETHADDR: 1442 case PCI_IVAR_SUBVENDOR: 1443 case PCI_IVAR_SUBDEVICE: 1444 case PCI_IVAR_VENDOR: 1445 case PCI_IVAR_DEVICE: 1446 case PCI_IVAR_DEVID: 1447 case PCI_IVAR_CLASS: 1448 case PCI_IVAR_SUBCLASS: 1449 case PCI_IVAR_PROGIF: 1450 case PCI_IVAR_REVID: 1451 case PCI_IVAR_IRQ: 1452 case PCI_IVAR_BUS: 1453 case PCI_IVAR_SLOT: 1454 case PCI_IVAR_FUNCTION: 1455 return (EINVAL); /* disallow for now */ 1456 1457 default: 1458 return (ENOENT); 1459 } 1460 } 1461 1462 1463 #include "opt_ddb.h" 1464 #ifdef DDB 1465 #include <ddb/ddb.h> 1466 #include <sys/cons.h> 1467 1468 /* 1469 * List resources based on pci map registers, used for within ddb 1470 */ 1471 1472 DB_SHOW_COMMAND(pciregs, db_pci_dump) 1473 { 1474 struct pci_devinfo *dinfo; 1475 struct devlist *devlist_head; 1476 struct pci_conf *p; 1477 const char *name; 1478 int i, error, none_count, quit; 1479 1480 none_count = 0; 1481 /* get the head of the device queue */ 1482 devlist_head = &pci_devq; 1483 1484 /* 1485 * Go through the list of devices and print out devices 1486 */ 1487 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 1488 for (error = 0, i = 0, quit = 0, 1489 dinfo = STAILQ_FIRST(devlist_head); 1490 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1491 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1492 1493 /* Populate pd_name and pd_unit */ 1494 name = NULL; 1495 if (dinfo->cfg.dev) 1496 name = device_get_name(dinfo->cfg.dev); 1497 1498 p = &dinfo->conf; 1499 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1500 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1501 (name && *name) ? name : "none", 1502 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1503 none_count++, 1504 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1505 p->pc_sel.pc_func, (p->pc_class << 16) | 1506 (p->pc_subclass << 8) | p->pc_progif, 1507 (p->pc_subdevice << 16) | p->pc_subvendor, 1508 (p->pc_device << 16) | p->pc_vendor, 1509 p->pc_revid, p->pc_hdr); 1510 } 1511 } 1512 #endif /* DDB */ 1513 1514 static struct resource * 1515 pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1516 u_long start, u_long end, u_long count, u_int flags) 1517 { 1518 struct pci_devinfo *dinfo = device_get_ivars(child); 1519 struct resource_list *rl = &dinfo->resources; 1520 struct resource_list_entry *rle; 1521 struct resource *res; 1522 uint32_t map, testval; 1523 int mapsize; 1524 1525 /* 1526 * Weed out the bogons, and figure out how large the BAR/map 1527 * is. Bars that read back 0 here are bogus and unimplemented. 1528 * Note: atapci in legacy mode are special and handled elsewhere 1529 * in the code. If you have a atapci device in legacy mode and 1530 * it fails here, that other code is broken. 1531 */ 1532 res = NULL; 1533 map = pci_read_config(child, *rid, 4); 1534 pci_write_config(child, *rid, 0xffffffff, 4); 1535 testval = pci_read_config(child, *rid, 4); 1536 if (testval == 0) 1537 return (NULL); 1538 if (pci_maptype(testval) & PCI_MAPMEM) { 1539 if (type != SYS_RES_MEMORY) { 1540 device_printf(child, 1541 "failed: rid %#x is memory, requested %d\n", 1542 *rid, type); 1543 goto out; 1544 } 1545 } else { 1546 if (type != SYS_RES_IOPORT) { 1547 device_printf(child, 1548 "failed: rid %#x is ioport, requested %d\n", 1549 *rid, type); 1550 goto out; 1551 } 1552 } 1553 /* 1554 * For real BARs, we need to override the size that 1555 * the driver requests, because that's what the BAR 1556 * actually uses and we would otherwise have a 1557 * situation where we might allocate the excess to 1558 * another driver, which won't work. 1559 */ 1560 mapsize = pci_mapsize(testval); 1561 count = 1 << mapsize; 1562 if (RF_ALIGNMENT(flags) < mapsize) 1563 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1564 1565 /* 1566 * Allocate enough resource, and then write back the 1567 * appropriate bar for that resource. 1568 */ 1569 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1570 start, end, count, flags); 1571 if (res == NULL) { 1572 device_printf(child, "%#lx bytes of rid %#x res %d failed.\n", 1573 count, *rid, type); 1574 goto out; 1575 } 1576 resource_list_add(rl, type, *rid, start, end, count); 1577 rle = resource_list_find(rl, type, *rid); 1578 if (rle == NULL) 1579 panic("pci_alloc_map: unexpectedly can't find resource."); 1580 rle->res = res; 1581 if (bootverbose) 1582 device_printf(child, 1583 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1584 count, *rid, type, rman_get_start(res)); 1585 map = rman_get_start(res); 1586 out:; 1587 pci_write_config(child, *rid, map, 4); 1588 return (res); 1589 } 1590 1591 1592 struct resource * 1593 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1594 u_long start, u_long end, u_long count, u_int flags) 1595 { 1596 struct pci_devinfo *dinfo = device_get_ivars(child); 1597 struct resource_list *rl = &dinfo->resources; 1598 struct resource_list_entry *rle; 1599 pcicfgregs *cfg = &dinfo->cfg; 1600 1601 /* 1602 * Perform lazy resource allocation 1603 */ 1604 if (device_get_parent(child) == dev) { 1605 switch (type) { 1606 case SYS_RES_IRQ: 1607 /* 1608 * If the child device doesn't have an 1609 * interrupt routed and is deserving of an 1610 * interrupt, try to assign it one. 1611 */ 1612 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1613 (cfg->intpin != 0)) { 1614 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1615 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1616 pci_write_config(child, PCIR_INTLINE, 1617 cfg->intline, 1); 1618 resource_list_add(rl, SYS_RES_IRQ, 0, 1619 cfg->intline, cfg->intline, 1); 1620 } 1621 } 1622 break; 1623 case SYS_RES_IOPORT: 1624 case SYS_RES_MEMORY: 1625 if (*rid < PCIR_BAR(cfg->nummaps)) { 1626 /* 1627 * Enable the I/O mode. We should 1628 * also be assigning resources too 1629 * when none are present. The 1630 * resource_list_alloc kind of sorta does 1631 * this... 1632 */ 1633 if (PCI_ENABLE_IO(dev, child, type)) 1634 return (NULL); 1635 } 1636 rle = resource_list_find(rl, type, *rid); 1637 if (rle == NULL) 1638 return (pci_alloc_map(dev, child, type, rid, 1639 start, end, count, flags)); 1640 break; 1641 } 1642 /* 1643 * If we've already allocated the resource, then 1644 * return it now. But first we may need to activate 1645 * it, since we don't allocate the resource as active 1646 * above. Normally this would be done down in the 1647 * nexus, but since we short-circuit that path we have 1648 * to do its job here. Not sure if we should free the 1649 * resource if it fails to activate. 1650 */ 1651 rle = resource_list_find(rl, type, *rid); 1652 if (rle != NULL && rle->res != NULL) { 1653 if (bootverbose) 1654 device_printf(child, 1655 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 1656 rman_get_size(rle->res), *rid, type, 1657 rman_get_start(rle->res)); 1658 if ((flags & RF_ACTIVE) && 1659 bus_generic_activate_resource(dev, child, type, 1660 *rid, rle->res) != 0) 1661 return NULL; 1662 return (rle->res); 1663 } 1664 } 1665 return (resource_list_alloc(rl, dev, child, type, rid, 1666 start, end, count, flags)); 1667 } 1668 1669 void 1670 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1671 { 1672 struct pci_devinfo *dinfo; 1673 struct resource_list *rl; 1674 struct resource_list_entry *rle; 1675 1676 if (device_get_parent(child) != dev) 1677 return; 1678 1679 dinfo = device_get_ivars(child); 1680 rl = &dinfo->resources; 1681 rle = resource_list_find(rl, type, rid); 1682 if (rle) { 1683 if (rle->res) { 1684 if (rman_get_device(rle->res) != dev || 1685 rman_get_flags(rle->res) & RF_ACTIVE) { 1686 device_printf(dev, "delete_resource: " 1687 "Resource still owned by child, oops. " 1688 "(type=%d, rid=%d, addr=%lx)\n", 1689 rle->type, rle->rid, 1690 rman_get_start(rle->res)); 1691 return; 1692 } 1693 bus_release_resource(dev, type, rid, rle->res); 1694 } 1695 resource_list_delete(rl, type, rid); 1696 } 1697 /* 1698 * Why do we turn off the PCI configuration BAR when we delete a 1699 * resource? -- imp 1700 */ 1701 pci_write_config(child, rid, 0, 4); 1702 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1703 } 1704 1705 struct resource_list * 1706 pci_get_resource_list (device_t dev, device_t child) 1707 { 1708 struct pci_devinfo *dinfo = device_get_ivars(child); 1709 1710 return (&dinfo->resources); 1711 } 1712 1713 uint32_t 1714 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1715 { 1716 struct pci_devinfo *dinfo = device_get_ivars(child); 1717 pcicfgregs *cfg = &dinfo->cfg; 1718 1719 return (PCIB_READ_CONFIG(device_get_parent(dev), 1720 cfg->bus, cfg->slot, cfg->func, reg, width)); 1721 } 1722 1723 void 1724 pci_write_config_method(device_t dev, device_t child, int reg, 1725 uint32_t val, int width) 1726 { 1727 struct pci_devinfo *dinfo = device_get_ivars(child); 1728 pcicfgregs *cfg = &dinfo->cfg; 1729 1730 PCIB_WRITE_CONFIG(device_get_parent(dev), 1731 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1732 } 1733 1734 int 1735 pci_child_location_str_method(device_t dev, device_t child, char *buf, 1736 size_t buflen) 1737 { 1738 struct pci_devinfo *dinfo; 1739 1740 dinfo = device_get_ivars(child); 1741 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1742 pci_get_function(child)); 1743 return (0); 1744 } 1745 1746 int 1747 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1748 size_t buflen) 1749 { 1750 struct pci_devinfo *dinfo; 1751 pcicfgregs *cfg; 1752 1753 dinfo = device_get_ivars(child); 1754 cfg = &dinfo->cfg; 1755 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1756 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1757 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1758 cfg->progif); 1759 return (0); 1760 } 1761 1762 int 1763 pci_assign_interrupt_method(device_t dev, device_t child) 1764 { 1765 struct pci_devinfo *dinfo = device_get_ivars(child); 1766 pcicfgregs *cfg = &dinfo->cfg; 1767 1768 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1769 cfg->intpin)); 1770 } 1771 1772 static int 1773 pci_modevent(module_t mod, int what, void *arg) 1774 { 1775 static struct cdev *pci_cdev; 1776 1777 switch (what) { 1778 case MOD_LOAD: 1779 STAILQ_INIT(&pci_devq); 1780 pci_generation = 0; 1781 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1782 "pci"); 1783 pci_load_vendor_data(); 1784 break; 1785 1786 case MOD_UNLOAD: 1787 destroy_dev(pci_cdev); 1788 break; 1789 } 1790 1791 return (0); 1792 } 1793 1794 static void 1795 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 1796 { 1797 int i; 1798 1799 /* 1800 * Only do header type 0 devices. Type 1 devices are bridges, 1801 * which we know need special treatment. Type 2 devices are 1802 * cardbus bridges which also require special treatment. 1803 * Other types are unknown, and we err on the side of safety 1804 * by ignoring them. 1805 */ 1806 if (dinfo->cfg.hdrtype != 0) 1807 return; 1808 1809 /* 1810 * Restore the device to full power mode. We must do this 1811 * before we restore the registers because moving from D3 to 1812 * D0 will cause the chip's BARs and some other registers to 1813 * be reset to some unknown power on reset values. Cut down 1814 * the noise on boot by doing nothing if we are already in 1815 * state D0. 1816 */ 1817 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1818 if (bootverbose) 1819 printf( 1820 "pci%d:%d:%d: Transition from D%d to D0\n", 1821 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 1822 pci_get_powerstate(dev)); 1823 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1824 } 1825 for (i = 0; i < dinfo->cfg.nummaps; i++) 1826 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 1827 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 1828 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 1829 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 1830 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 1831 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 1832 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 1833 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 1834 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 1835 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 1836 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 1837 } 1838 1839 static void 1840 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 1841 { 1842 int i; 1843 uint32_t cls; 1844 int ps; 1845 1846 /* 1847 * Only do header type 0 devices. Type 1 devices are bridges, which 1848 * we know need special treatment. Type 2 devices are cardbus bridges 1849 * which also require special treatment. Other types are unknown, and 1850 * we err on the side of safety by ignoring them. Powering down 1851 * bridges should not be undertaken lightly. 1852 */ 1853 if (dinfo->cfg.hdrtype != 0) 1854 return; 1855 for (i = 0; i < dinfo->cfg.nummaps; i++) 1856 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1857 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 1858 1859 /* 1860 * Some drivers apparently write to these registers w/o 1861 * updating our cahced copy. No harm happens if we update the 1862 * copy, so do so here so we can restore them. The COMMAND 1863 * register is modified by the bus w/o updating the cache. This 1864 * should represent the normally writable portion of the 'defined' 1865 * part of type 0 headers. In theory we also need to save/restore 1866 * the PCI capability structures we know about, but apart from power 1867 * we don't know any that are writable. 1868 */ 1869 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1870 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1871 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 1872 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 1873 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 1874 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 1875 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 1876 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 1877 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 1878 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1879 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1880 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 1881 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 1882 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 1883 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 1884 1885 /* 1886 * don't set the state for display devices and for memory devices 1887 * since bad things happen. we should (a) have drivers that can easily 1888 * detach and (b) use generic drivers for these devices so that some 1889 * device actually attaches. We need to make sure that when we 1890 * implement (a) we don't power the device down on a reattach. 1891 */ 1892 cls = pci_get_class(dev); 1893 if (setstate && cls != PCIC_DISPLAY && cls != PCIC_MEMORY) { 1894 /* 1895 * PCI spec is clear that we can only go into D3 state from 1896 * D0 state. Transition from D[12] into D0 before going 1897 * to D3 state. 1898 */ 1899 ps = pci_get_powerstate(dev); 1900 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) { 1901 if (bootverbose) 1902 printf( 1903 "pci%d:%d:%d: Transition from D%d to D0\n", 1904 dinfo->cfg.bus, dinfo->cfg.slot, 1905 dinfo->cfg.func, ps); 1906 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1907 } 1908 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) { 1909 if (bootverbose) 1910 printf( 1911 "pci%d:%d:%d: Transition from D0 to D3\n", 1912 dinfo->cfg.bus, dinfo->cfg.slot, 1913 dinfo->cfg.func); 1914 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 1915 } 1916 } 1917 } 1918