1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 * 30 */ 31 32 #include "opt_bus.h" 33 #include "opt_pci.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/linker.h> 40 #include <sys/fcntl.h> 41 #include <sys/conf.h> 42 #include <sys/kernel.h> 43 #include <sys/queue.h> 44 #include <sys/sysctl.h> 45 #include <sys/types.h> 46 47 #include <vm/vm.h> 48 #include <vm/pmap.h> 49 #include <vm/vm_extern.h> 50 51 #include <sys/bus.h> 52 #include <machine/bus.h> 53 #include <sys/rman.h> 54 #include <machine/resource.h> 55 56 #include <sys/pciio.h> 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pci_private.h> 60 61 #include "pcib_if.h" 62 #include "pci_if.h" 63 64 static u_int32_t pci_mapbase(unsigned mapreg); 65 static int pci_maptype(unsigned mapreg); 66 static int pci_mapsize(unsigned testval); 67 static int pci_maprange(unsigned mapreg); 68 static void pci_fixancient(pcicfgregs *cfg); 69 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 70 pcicfgregs *cfg); 71 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 72 73 static int pci_porten(device_t pcib, int b, int s, int f); 74 static int pci_memen(device_t pcib, int b, int s, int f); 75 static int pci_add_map(device_t pcib, int b, int s, int f, int reg, 76 struct resource_list *rl); 77 static void pci_add_resources(device_t pcib, int b, int s, int f, 78 device_t dev); 79 static void pci_add_children(device_t dev, int busno); 80 static int pci_probe(device_t dev); 81 static int pci_describe_parse_line(char **ptr, int *vendor, 82 int *device, char **desc); 83 static char *pci_describe_device(device_t dev); 84 static int pci_modevent(module_t mod, int what, void *arg); 85 86 static device_method_t pci_methods[] = { 87 /* Device interface */ 88 DEVMETHOD(device_probe, pci_probe), 89 DEVMETHOD(device_attach, bus_generic_attach), 90 DEVMETHOD(device_shutdown, bus_generic_shutdown), 91 DEVMETHOD(device_suspend, bus_generic_suspend), 92 DEVMETHOD(device_resume, bus_generic_resume), 93 94 /* Bus interface */ 95 DEVMETHOD(bus_print_child, pci_print_child), 96 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 97 DEVMETHOD(bus_read_ivar, pci_read_ivar), 98 DEVMETHOD(bus_write_ivar, pci_write_ivar), 99 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 100 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 101 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 102 103 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 104 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 105 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 106 DEVMETHOD(bus_delete_resource, pci_delete_resource), 107 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 108 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 109 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 110 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 111 112 /* PCI interface */ 113 DEVMETHOD(pci_read_config, pci_read_config_method), 114 DEVMETHOD(pci_write_config, pci_write_config_method), 115 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 116 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 117 DEVMETHOD(pci_enable_io, pci_enable_io_method), 118 DEVMETHOD(pci_disable_io, pci_disable_io_method), 119 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 120 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 121 122 { 0, 0 } 123 }; 124 125 static driver_t pci_driver = { 126 "pci", 127 pci_methods, 128 0, /* no softc */ 129 }; 130 131 static devclass_t pci_devclass; 132 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 133 DRIVER_MODULE(pci, acpi_pcib, pci_driver, pci_devclass, pci_modevent, 0); 134 MODULE_VERSION(pci, 1); 135 136 static char *pci_vendordata; 137 static size_t pci_vendordata_size; 138 139 140 struct pci_quirk { 141 u_int32_t devid; /* Vendor/device of the card */ 142 int type; 143 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 144 int arg1; 145 int arg2; 146 }; 147 148 struct pci_quirk pci_quirks[] = { 149 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 150 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 151 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 152 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 153 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 154 155 { 0 } 156 }; 157 158 /* map register information */ 159 #define PCI_MAPMEM 0x01 /* memory map */ 160 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 161 #define PCI_MAPPORT 0x04 /* port map */ 162 163 struct devlist pci_devq; 164 u_int32_t pci_generation; 165 u_int32_t pci_numdevs = 0; 166 167 /* sysctl vars */ 168 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 169 170 int pci_enable_io_modes = 1; 171 TUNABLE_INT("hw.pci.enable_io_modes", (int *)&pci_enable_io_modes); 172 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 173 &pci_enable_io_modes, 1, 174 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 175 enable these bits correctly. We'd like to do this all the time, but there\n\ 176 are some peripherals that this causes problems with."); 177 178 /* Find a device_t by bus/slot/function */ 179 180 device_t 181 pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func) 182 { 183 struct pci_devinfo *dinfo; 184 185 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 186 if ((dinfo->cfg.bus == bus) && 187 (dinfo->cfg.slot == slot) && 188 (dinfo->cfg.func == func)) { 189 return (dinfo->cfg.dev); 190 } 191 } 192 193 return (NULL); 194 } 195 196 /* Find a device_t by vendor/device ID */ 197 198 device_t 199 pci_find_device (u_int16_t vendor, u_int16_t device) 200 { 201 struct pci_devinfo *dinfo; 202 203 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 204 if ((dinfo->cfg.vendor == vendor) && 205 (dinfo->cfg.device == device)) { 206 return (dinfo->cfg.dev); 207 } 208 } 209 210 return (NULL); 211 } 212 213 /* return base address of memory or port map */ 214 215 static u_int32_t 216 pci_mapbase(unsigned mapreg) 217 { 218 int mask = 0x03; 219 if ((mapreg & 0x01) == 0) 220 mask = 0x0f; 221 return (mapreg & ~mask); 222 } 223 224 /* return map type of memory or port map */ 225 226 static int 227 pci_maptype(unsigned mapreg) 228 { 229 static u_int8_t maptype[0x10] = { 230 PCI_MAPMEM, PCI_MAPPORT, 231 PCI_MAPMEM, 0, 232 PCI_MAPMEM, PCI_MAPPORT, 233 0, 0, 234 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 235 PCI_MAPMEM|PCI_MAPMEMP, 0, 236 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 237 0, 0, 238 }; 239 240 return maptype[mapreg & 0x0f]; 241 } 242 243 /* return log2 of map size decoded for memory or port map */ 244 245 static int 246 pci_mapsize(unsigned testval) 247 { 248 int ln2size; 249 250 testval = pci_mapbase(testval); 251 ln2size = 0; 252 if (testval != 0) { 253 while ((testval & 1) == 0) 254 { 255 ln2size++; 256 testval >>= 1; 257 } 258 } 259 return (ln2size); 260 } 261 262 /* return log2 of address range supported by map register */ 263 264 static int 265 pci_maprange(unsigned mapreg) 266 { 267 int ln2range = 0; 268 switch (mapreg & 0x07) { 269 case 0x00: 270 case 0x01: 271 case 0x05: 272 ln2range = 32; 273 break; 274 case 0x02: 275 ln2range = 20; 276 break; 277 case 0x04: 278 ln2range = 64; 279 break; 280 } 281 return (ln2range); 282 } 283 284 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 285 286 static void 287 pci_fixancient(pcicfgregs *cfg) 288 { 289 if (cfg->hdrtype != 0) 290 return; 291 292 /* PCI to PCI bridges use header type 1 */ 293 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 294 cfg->hdrtype = 1; 295 } 296 297 /* extract header type specific config data */ 298 299 static void 300 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 301 { 302 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 303 switch (cfg->hdrtype) { 304 case 0: 305 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 306 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 307 cfg->nummaps = PCI_MAXMAPS_0; 308 break; 309 case 1: 310 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 311 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 312 cfg->nummaps = PCI_MAXMAPS_1; 313 break; 314 case 2: 315 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 316 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 317 cfg->nummaps = PCI_MAXMAPS_2; 318 break; 319 } 320 #undef REG 321 } 322 323 /* read configuration header into pcicfgregs structure */ 324 325 struct pci_devinfo * 326 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 327 { 328 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 329 pcicfgregs *cfg = NULL; 330 struct pci_devinfo *devlist_entry; 331 struct devlist *devlist_head; 332 333 devlist_head = &pci_devq; 334 335 devlist_entry = NULL; 336 337 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 338 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 339 if (devlist_entry == NULL) 340 return (NULL); 341 342 cfg = &devlist_entry->cfg; 343 344 cfg->bus = b; 345 cfg->slot = s; 346 cfg->func = f; 347 cfg->vendor = REG(PCIR_VENDOR, 2); 348 cfg->device = REG(PCIR_DEVICE, 2); 349 cfg->cmdreg = REG(PCIR_COMMAND, 2); 350 cfg->statreg = REG(PCIR_STATUS, 2); 351 cfg->baseclass = REG(PCIR_CLASS, 1); 352 cfg->subclass = REG(PCIR_SUBCLASS, 1); 353 cfg->progif = REG(PCIR_PROGIF, 1); 354 cfg->revid = REG(PCIR_REVID, 1); 355 cfg->hdrtype = REG(PCIR_HEADERTYPE, 1); 356 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 357 cfg->lattimer = REG(PCIR_LATTIMER, 1); 358 cfg->intpin = REG(PCIR_INTPIN, 1); 359 cfg->intline = REG(PCIR_INTLINE, 1); 360 361 cfg->mingnt = REG(PCIR_MINGNT, 1); 362 cfg->maxlat = REG(PCIR_MAXLAT, 1); 363 364 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 365 cfg->hdrtype &= ~PCIM_MFDEV; 366 367 pci_fixancient(cfg); 368 pci_hdrtypedata(pcib, b, s, f, cfg); 369 370 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 371 pci_read_extcap(pcib, cfg); 372 373 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 374 375 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 376 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 377 devlist_entry->conf.pc_sel.pc_func = cfg->func; 378 devlist_entry->conf.pc_hdr = cfg->hdrtype; 379 380 devlist_entry->conf.pc_subvendor = cfg->subvendor; 381 devlist_entry->conf.pc_subdevice = cfg->subdevice; 382 devlist_entry->conf.pc_vendor = cfg->vendor; 383 devlist_entry->conf.pc_device = cfg->device; 384 385 devlist_entry->conf.pc_class = cfg->baseclass; 386 devlist_entry->conf.pc_subclass = cfg->subclass; 387 devlist_entry->conf.pc_progif = cfg->progif; 388 devlist_entry->conf.pc_revid = cfg->revid; 389 390 pci_numdevs++; 391 pci_generation++; 392 } 393 return (devlist_entry); 394 #undef REG 395 } 396 397 static void 398 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 399 { 400 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 401 int ptr, nextptr, ptrptr; 402 403 switch (cfg->hdrtype) { 404 case 0: 405 ptrptr = 0x34; 406 break; 407 case 2: 408 ptrptr = 0x14; 409 break; 410 default: 411 return; /* no extended capabilities support */ 412 } 413 nextptr = REG(ptrptr, 1); /* sanity check? */ 414 415 /* 416 * Read capability entries. 417 */ 418 while (nextptr != 0) { 419 /* Sanity check */ 420 if (nextptr > 255) { 421 printf("illegal PCI extended capability offset %d\n", 422 nextptr); 423 return; 424 } 425 /* Find the next entry */ 426 ptr = nextptr; 427 nextptr = REG(ptr + 1, 1); 428 429 /* Process this entry */ 430 switch (REG(ptr, 1)) { 431 case 0x01: /* PCI power management */ 432 if (cfg->pp_cap == 0) { 433 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 434 cfg->pp_status = ptr + PCIR_POWER_STATUS; 435 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 436 if ((nextptr - ptr) > PCIR_POWER_DATA) 437 cfg->pp_data = ptr + PCIR_POWER_DATA; 438 } 439 break; 440 default: 441 break; 442 } 443 } 444 #undef REG 445 } 446 447 /* free pcicfgregs structure and all depending data structures */ 448 449 int 450 pci_freecfg(struct pci_devinfo *dinfo) 451 { 452 struct devlist *devlist_head; 453 454 devlist_head = &pci_devq; 455 456 /* XXX this hasn't been tested */ 457 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 458 free(dinfo, M_DEVBUF); 459 460 /* increment the generation count */ 461 pci_generation++; 462 463 /* we're losing one device */ 464 pci_numdevs--; 465 return (0); 466 } 467 468 /* 469 * PCI power manangement 470 */ 471 int 472 pci_set_powerstate_method(device_t dev, device_t child, int state) 473 { 474 struct pci_devinfo *dinfo = device_get_ivars(child); 475 pcicfgregs *cfg = &dinfo->cfg; 476 u_int16_t status; 477 int result; 478 479 if (cfg->pp_cap != 0) { 480 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK; 481 result = 0; 482 switch (state) { 483 case PCI_POWERSTATE_D0: 484 status |= PCIM_PSTAT_D0; 485 break; 486 case PCI_POWERSTATE_D1: 487 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) { 488 status |= PCIM_PSTAT_D1; 489 } else { 490 result = EOPNOTSUPP; 491 } 492 break; 493 case PCI_POWERSTATE_D2: 494 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) { 495 status |= PCIM_PSTAT_D2; 496 } else { 497 result = EOPNOTSUPP; 498 } 499 break; 500 case PCI_POWERSTATE_D3: 501 status |= PCIM_PSTAT_D3; 502 break; 503 default: 504 result = EINVAL; 505 } 506 if (result == 0) 507 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2); 508 } else { 509 result = ENXIO; 510 } 511 return(result); 512 } 513 514 int 515 pci_get_powerstate_method(device_t dev, device_t child) 516 { 517 struct pci_devinfo *dinfo = device_get_ivars(child); 518 pcicfgregs *cfg = &dinfo->cfg; 519 u_int16_t status; 520 int result; 521 522 if (cfg->pp_cap != 0) { 523 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2); 524 switch (status & PCIM_PSTAT_DMASK) { 525 case PCIM_PSTAT_D0: 526 result = PCI_POWERSTATE_D0; 527 break; 528 case PCIM_PSTAT_D1: 529 result = PCI_POWERSTATE_D1; 530 break; 531 case PCIM_PSTAT_D2: 532 result = PCI_POWERSTATE_D2; 533 break; 534 case PCIM_PSTAT_D3: 535 result = PCI_POWERSTATE_D3; 536 break; 537 default: 538 result = PCI_POWERSTATE_UNKNOWN; 539 break; 540 } 541 } else { 542 /* No support, device is always at D0 */ 543 result = PCI_POWERSTATE_D0; 544 } 545 return(result); 546 } 547 548 /* 549 * Some convenience functions for PCI device drivers. 550 */ 551 552 static __inline void 553 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit) 554 { 555 u_int16_t command; 556 557 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 558 command |= bit; 559 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 560 } 561 562 static __inline void 563 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit) 564 { 565 u_int16_t command; 566 567 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 568 command &= ~bit; 569 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 570 } 571 572 void 573 pci_enable_busmaster_method(device_t dev, device_t child) 574 { 575 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 576 } 577 578 void 579 pci_disable_busmaster_method(device_t dev, device_t child) 580 { 581 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 582 } 583 584 void 585 pci_enable_io_method(device_t dev, device_t child, int space) 586 { 587 switch(space) { 588 case SYS_RES_IOPORT: 589 pci_set_command_bit(dev, child, PCIM_CMD_PORTEN); 590 break; 591 case SYS_RES_MEMORY: 592 pci_set_command_bit(dev, child, PCIM_CMD_MEMEN); 593 break; 594 } 595 } 596 597 void 598 pci_disable_io_method(device_t dev, device_t child, int space) 599 { 600 switch(space) { 601 case SYS_RES_IOPORT: 602 pci_clear_command_bit(dev, child, PCIM_CMD_PORTEN); 603 break; 604 case SYS_RES_MEMORY: 605 pci_clear_command_bit(dev, child, PCIM_CMD_MEMEN); 606 break; 607 } 608 } 609 610 /* 611 * New style pci driver. Parent device is either a pci-host-bridge or a 612 * pci-pci-bridge. Both kinds are represented by instances of pcib. 613 */ 614 615 void 616 pci_print_verbose(struct pci_devinfo *dinfo) 617 { 618 if (bootverbose) { 619 pcicfgregs *cfg = &dinfo->cfg; 620 621 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 622 cfg->vendor, cfg->device, cfg->revid); 623 printf("\tbus=%d, slot=%d, func=%d\n", 624 cfg->bus, cfg->slot, cfg->func); 625 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 626 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 627 cfg->mfdev); 628 #ifdef PCI_DEBUG 629 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 630 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 631 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 632 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 633 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 634 #endif /* PCI_DEBUG */ 635 if (cfg->intpin > 0) 636 printf("\tintpin=%c, irq=%d\n", 637 cfg->intpin +'a' -1, cfg->intline); 638 if (cfg->pp_cap) { 639 u_int16_t status; 640 641 status = pci_read_config(cfg->dev, cfg->pp_status, 2); 642 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 643 cfg->pp_cap & PCIM_PCAP_SPEC, 644 cfg->pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 645 cfg->pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 646 status & PCIM_PSTAT_DMASK); 647 } 648 } 649 } 650 651 static int 652 pci_porten(device_t pcib, int b, int s, int f) 653 { 654 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 655 & PCIM_CMD_PORTEN) != 0; 656 } 657 658 static int 659 pci_memen(device_t pcib, int b, int s, int f) 660 { 661 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 662 & PCIM_CMD_MEMEN) != 0; 663 } 664 665 /* 666 * Add a resource based on a pci map register. Return 1 if the map 667 * register is a 32bit map register or 2 if it is a 64bit register. 668 */ 669 static int 670 pci_add_map(device_t pcib, int b, int s, int f, int reg, 671 struct resource_list *rl) 672 { 673 u_int32_t map; 674 u_int64_t base; 675 u_int8_t ln2size; 676 u_int8_t ln2range; 677 u_int32_t testval; 678 u_int16_t cmd; 679 int type; 680 681 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 682 683 if (map == 0 || map == 0xffffffff) 684 return (1); /* skip invalid entry */ 685 686 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 687 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 688 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 689 690 base = pci_mapbase(map); 691 if (pci_maptype(map) & PCI_MAPMEM) 692 type = SYS_RES_MEMORY; 693 else 694 type = SYS_RES_IOPORT; 695 ln2size = pci_mapsize(testval); 696 ln2range = pci_maprange(testval); 697 if (ln2range == 64) { 698 /* Read the other half of a 64bit map register */ 699 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 700 } 701 702 if (bootverbose) { 703 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 704 reg, pci_maptype(map), ln2range, 705 (unsigned int) base, ln2size); 706 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 707 printf(", port disabled\n"); 708 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 709 printf(", memory disabled\n"); 710 else 711 printf(", enabled\n"); 712 } 713 714 /* 715 * This code theoretically does the right thing, but has 716 * undesirable side effects in some cases where 717 * peripherals respond oddly to having these bits 718 * enabled. Leave them alone by default. 719 */ 720 if (pci_enable_io_modes) { 721 /* Turn on resources that have been left off by a lazy BIOS */ 722 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 723 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 724 cmd |= PCIM_CMD_PORTEN; 725 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 726 } 727 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 728 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 729 cmd |= PCIM_CMD_MEMEN; 730 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 731 } 732 } else { 733 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 734 return (1); 735 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 736 return (1); 737 } 738 resource_list_add(rl, type, reg, base, base + (1 << ln2size) - 1, 739 (1 << ln2size)); 740 741 return ((ln2range == 64) ? 2 : 1); 742 } 743 744 static void 745 pci_add_resources(device_t pcib, int b, int s, int f, device_t dev) 746 { 747 struct pci_devinfo *dinfo = device_get_ivars(dev); 748 pcicfgregs *cfg = &dinfo->cfg; 749 struct resource_list *rl = &dinfo->resources; 750 struct pci_quirk *q; 751 int i; 752 753 for (i = 0; i < cfg->nummaps;) { 754 i += pci_add_map(pcib, b, s, f, PCIR_MAPS + i*4, rl); 755 } 756 757 for (q = &pci_quirks[0]; q->devid; q++) { 758 if (q->devid == ((cfg->device << 16) | cfg->vendor) 759 && q->type == PCI_QUIRK_MAP_REG) 760 pci_add_map(pcib, b, s, f, q->arg1, rl); 761 } 762 763 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 764 #ifdef __ia64__ 765 /* 766 * Re-route interrupts on ia64 so that we can get the 767 * I/O SAPIC interrupt numbers (the BIOS leaves legacy 768 * PIC interrupt numbers in the intline registers). 769 */ 770 cfg->intline = PCIB_ROUTE_INTERRUPT(pcib, dev, cfg->intpin); 771 #endif 772 resource_list_add(rl, SYS_RES_IRQ, 0, cfg->intline, 773 cfg->intline, 1); 774 } 775 } 776 777 static void 778 pci_add_children(device_t dev, int busno) 779 { 780 device_t pcib = device_get_parent(dev); 781 int maxslots; 782 int s, f; 783 784 maxslots = PCIB_MAXSLOTS(pcib); 785 786 for (s = 0; s <= maxslots; s++) { 787 int pcifunchigh = 0; 788 for (f = 0; f <= pcifunchigh; f++) { 789 struct pci_devinfo *dinfo = pci_read_device(pcib, 790 busno, s, f, sizeof(struct pci_devinfo)); 791 if (dinfo != NULL) { 792 if (dinfo->cfg.mfdev) 793 pcifunchigh = PCI_FUNCMAX; 794 795 dinfo->cfg.dev = device_add_child(dev, NULL, -1); 796 device_set_ivars(dinfo->cfg.dev, dinfo); 797 pci_add_resources(pcib, busno, s, f, 798 dinfo->cfg.dev); 799 pci_print_verbose(dinfo); 800 } 801 } 802 } 803 } 804 805 static int 806 pci_probe(device_t dev) 807 { 808 static int once, busno; 809 caddr_t vendordata, info; 810 811 device_set_desc(dev, "PCI bus"); 812 813 if (bootverbose) 814 device_printf(dev, "physical bus=%d\n", pcib_get_bus(dev)); 815 816 /* 817 * Since there can be multiple independantly numbered PCI 818 * busses on some large alpha systems, we can't use the unit 819 * number to decide what bus we are probing. We ask the parent 820 * pcib what our bus number is. 821 */ 822 busno = pcib_get_bus(dev); 823 if (busno < 0) 824 return (ENXIO); 825 pci_add_children(dev, busno); 826 827 if (!once) { 828 make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, "pci"); 829 if ((vendordata = preload_search_by_type("pci_vendor_data")) 830 != NULL) { 831 info = preload_search_info(vendordata, MODINFO_ADDR); 832 pci_vendordata = *(char **)info; 833 info = preload_search_info(vendordata, MODINFO_SIZE); 834 pci_vendordata_size = *(size_t *)info; 835 /* terminate the database */ 836 pci_vendordata[pci_vendordata_size] = '\n'; 837 } 838 once++; 839 } 840 841 return (0); 842 } 843 844 int 845 pci_print_child(device_t dev, device_t child) 846 { 847 struct pci_devinfo *dinfo; 848 struct resource_list *rl; 849 pcicfgregs *cfg; 850 int retval = 0; 851 852 dinfo = device_get_ivars(child); 853 cfg = &dinfo->cfg; 854 rl = &dinfo->resources; 855 856 retval += bus_print_child_header(dev, child); 857 858 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 859 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 860 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 861 if (device_get_flags(dev)) 862 retval += printf(" flags %#x", device_get_flags(dev)); 863 864 retval += printf(" at device %d.%d", pci_get_slot(child), 865 pci_get_function(child)); 866 867 retval += bus_print_child_footer(dev, child); 868 869 return (retval); 870 } 871 872 static struct 873 { 874 int class; 875 int subclass; 876 char *desc; 877 } pci_nomatch_tab[] = { 878 {PCIC_OLD, -1, "old"}, 879 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 880 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 881 {PCIC_STORAGE, -1, "mass storage"}, 882 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 883 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 884 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 885 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 886 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 887 {PCIC_NETWORK, -1, "network"}, 888 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 889 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 890 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 891 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 892 {PCIC_DISPLAY, -1, "display"}, 893 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 894 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 895 {PCIC_MULTIMEDIA, -1, "multimedia"}, 896 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 897 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 898 {PCIC_MEMORY, -1, "memory"}, 899 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 900 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 901 {PCIC_BRIDGE, -1, "bridge"}, 902 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 903 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 904 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 905 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 906 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 907 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 908 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 909 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 910 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 911 {PCIC_SIMPLECOMM, -1, "simple comms"}, 912 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 913 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 914 {PCIC_BASEPERIPH, -1, "base peripheral"}, 915 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 916 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 917 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 918 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 919 {PCIC_INPUTDEV, -1, "input device"}, 920 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 921 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 922 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 923 {PCIC_DOCKING, -1, "docking station"}, 924 {PCIC_PROCESSOR, -1, "processor"}, 925 {PCIC_SERIALBUS, -1, "serial bus"}, 926 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 927 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 928 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 929 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 930 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 931 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 932 {0, 0, NULL} 933 }; 934 935 void 936 pci_probe_nomatch(device_t dev, device_t child) 937 { 938 int i; 939 char *cp, *scp, *device; 940 941 /* 942 * Look for a listing for this device in a loaded device database. 943 */ 944 if ((device = pci_describe_device(child)) != NULL) { 945 device_printf(dev, "<%s>", device); 946 free(device, M_DEVBUF); 947 } else { 948 /* 949 * Scan the class/subclass descriptions for a general 950 * description. 951 */ 952 cp = "unknown"; 953 scp = NULL; 954 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 955 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 956 if (pci_nomatch_tab[i].subclass == -1) { 957 cp = pci_nomatch_tab[i].desc; 958 } else if (pci_nomatch_tab[i].subclass == 959 pci_get_subclass(child)) { 960 scp = pci_nomatch_tab[i].desc; 961 } 962 } 963 } 964 device_printf(dev, "<%s%s%s>", 965 cp ? : "", ((cp != NULL) && (scp != NULL)) ? ", " : "", 966 scp ? : ""); 967 } 968 printf(" at device %d.%d (no driver attached)\n", 969 pci_get_slot(child), pci_get_function(child)); 970 return; 971 } 972 973 /* 974 * Parse the PCI device database, if loaded, and return a pointer to a 975 * description of the device. 976 * 977 * The database is flat text formatted as follows: 978 * 979 * Any line not in a valid format is ignored. 980 * Lines are terminated with newline '\n' characters. 981 * 982 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 983 * the vendor name. 984 * 985 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 986 * - devices cannot be listed without a corresponding VENDOR line. 987 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 988 * another TAB, then the device name. 989 */ 990 991 /* 992 * Assuming (ptr) points to the beginning of a line in the database, 993 * return the vendor or device and description of the next entry. 994 * The value of (vendor) or (device) inappropriate for the entry type 995 * is set to -1. Returns nonzero at the end of the database. 996 * 997 * Note that this is slightly unrobust in the face of corrupt data; 998 * we attempt to safeguard against this by spamming the end of the 999 * database with a newline when we initialise. 1000 */ 1001 static int 1002 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1003 { 1004 char *cp = *ptr; 1005 int left; 1006 1007 *device = -1; 1008 *vendor = -1; 1009 **desc = '\0'; 1010 for (;;) { 1011 left = pci_vendordata_size - (cp - pci_vendordata); 1012 if (left <= 0) { 1013 *ptr = cp; 1014 return(1); 1015 } 1016 1017 /* vendor entry? */ 1018 if (*cp != '\t' && 1019 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1020 break; 1021 /* device entry? */ 1022 if (*cp == '\t' && 1023 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1024 break; 1025 1026 /* skip to next line */ 1027 while (*cp != '\n' && left > 0) { 1028 cp++; 1029 left--; 1030 } 1031 if (*cp == '\n') { 1032 cp++; 1033 left--; 1034 } 1035 } 1036 /* skip to next line */ 1037 while (*cp != '\n' && left > 0) { 1038 cp++; 1039 left--; 1040 } 1041 if (*cp == '\n' && left > 0) 1042 cp++; 1043 *ptr = cp; 1044 return(0); 1045 } 1046 1047 static char * 1048 pci_describe_device(device_t dev) 1049 { 1050 int vendor, device; 1051 char *desc, *vp, *dp, *line; 1052 1053 desc = vp = dp = NULL; 1054 1055 /* 1056 * If we have no vendor data, we can't do anything. 1057 */ 1058 if (pci_vendordata == NULL) 1059 goto out; 1060 1061 /* 1062 * Scan the vendor data looking for this device 1063 */ 1064 line = pci_vendordata; 1065 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1066 goto out; 1067 for (;;) { 1068 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1069 goto out; 1070 if (vendor == pci_get_vendor(dev)) 1071 break; 1072 } 1073 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1074 goto out; 1075 for (;;) { 1076 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1077 *dp = 0; 1078 break; 1079 } 1080 if (vendor != -1) { 1081 *dp = 0; 1082 break; 1083 } 1084 if (device == pci_get_device(dev)) 1085 break; 1086 } 1087 if (dp[0] == '\0') 1088 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1089 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1090 NULL) 1091 sprintf(desc, "%s, %s", vp, dp); 1092 out: 1093 if (vp != NULL) 1094 free(vp, M_DEVBUF); 1095 if (dp != NULL) 1096 free(dp, M_DEVBUF); 1097 return(desc); 1098 } 1099 1100 int 1101 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1102 { 1103 struct pci_devinfo *dinfo; 1104 pcicfgregs *cfg; 1105 1106 dinfo = device_get_ivars(child); 1107 cfg = &dinfo->cfg; 1108 1109 switch (which) { 1110 case PCI_IVAR_SUBVENDOR: 1111 *result = cfg->subvendor; 1112 break; 1113 case PCI_IVAR_SUBDEVICE: 1114 *result = cfg->subdevice; 1115 break; 1116 case PCI_IVAR_VENDOR: 1117 *result = cfg->vendor; 1118 break; 1119 case PCI_IVAR_DEVICE: 1120 *result = cfg->device; 1121 break; 1122 case PCI_IVAR_DEVID: 1123 *result = (cfg->device << 16) | cfg->vendor; 1124 break; 1125 case PCI_IVAR_CLASS: 1126 *result = cfg->baseclass; 1127 break; 1128 case PCI_IVAR_SUBCLASS: 1129 *result = cfg->subclass; 1130 break; 1131 case PCI_IVAR_PROGIF: 1132 *result = cfg->progif; 1133 break; 1134 case PCI_IVAR_REVID: 1135 *result = cfg->revid; 1136 break; 1137 case PCI_IVAR_INTPIN: 1138 *result = cfg->intpin; 1139 break; 1140 case PCI_IVAR_IRQ: 1141 *result = cfg->intline; 1142 break; 1143 case PCI_IVAR_BUS: 1144 *result = cfg->bus; 1145 break; 1146 case PCI_IVAR_SLOT: 1147 *result = cfg->slot; 1148 break; 1149 case PCI_IVAR_FUNCTION: 1150 *result = cfg->func; 1151 break; 1152 default: 1153 return (ENOENT); 1154 } 1155 return (0); 1156 } 1157 1158 int 1159 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1160 { 1161 struct pci_devinfo *dinfo; 1162 pcicfgregs *cfg; 1163 1164 dinfo = device_get_ivars(child); 1165 cfg = &dinfo->cfg; 1166 1167 switch (which) { 1168 case PCI_IVAR_SUBVENDOR: 1169 case PCI_IVAR_SUBDEVICE: 1170 case PCI_IVAR_VENDOR: 1171 case PCI_IVAR_DEVICE: 1172 case PCI_IVAR_DEVID: 1173 case PCI_IVAR_CLASS: 1174 case PCI_IVAR_SUBCLASS: 1175 case PCI_IVAR_PROGIF: 1176 case PCI_IVAR_REVID: 1177 case PCI_IVAR_INTPIN: 1178 case PCI_IVAR_IRQ: 1179 case PCI_IVAR_BUS: 1180 case PCI_IVAR_SLOT: 1181 case PCI_IVAR_FUNCTION: 1182 return (EINVAL); /* disallow for now */ 1183 1184 default: 1185 return (ENOENT); 1186 } 1187 return (0); 1188 } 1189 1190 struct resource * 1191 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1192 u_long start, u_long end, u_long count, u_int flags) 1193 { 1194 struct pci_devinfo *dinfo = device_get_ivars(child); 1195 struct resource_list *rl = &dinfo->resources; 1196 pcicfgregs *cfg = &dinfo->cfg; 1197 1198 /* 1199 * You can share PCI interrupts. 1200 */ 1201 if (type == SYS_RES_IRQ) 1202 flags |= RF_SHAREABLE; 1203 1204 /* 1205 * Perform lazy resource allocation 1206 * 1207 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY 1208 */ 1209 if (device_get_parent(child) == dev) { 1210 /* 1211 * If device doesn't have an interrupt routed, and is 1212 * deserving of an interrupt, try to assign it one. 1213 */ 1214 if ((type == SYS_RES_IRQ) && 1215 !PCI_INTERRUPT_VALID(cfg->intline) && 1216 (cfg->intpin != 0)) { 1217 cfg->intline = PCIB_ROUTE_INTERRUPT( 1218 device_get_parent(dev), child, cfg->intpin); 1219 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1220 pci_write_config(child, PCIR_INTLINE, 1221 cfg->intline, 1); 1222 resource_list_add(rl, SYS_RES_IRQ, 0, 1223 cfg->intline, cfg->intline, 1); 1224 } 1225 } 1226 } 1227 1228 return (resource_list_alloc(rl, dev, child, type, rid, 1229 start, end, count, flags)); 1230 } 1231 1232 void 1233 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1234 { 1235 struct pci_devinfo *dinfo; 1236 struct resource_list *rl; 1237 struct resource_list_entry *rle; 1238 1239 if (device_get_parent(child) != dev) 1240 return; 1241 1242 dinfo = device_get_ivars(child); 1243 rl = &dinfo->resources; 1244 rle = resource_list_find(rl, type, rid); 1245 if (rle) { 1246 if (rle->res) { 1247 if (rle->res->r_dev != dev || 1248 rman_get_flags(rle->res) & RF_ACTIVE) { 1249 device_printf(dev, "delete_resource: " 1250 "Resource still owned by child, oops. " 1251 "(type=%d, rid=%d, addr=%lx)\n", 1252 rle->type, rle->rid, 1253 rman_get_start(rle->res)); 1254 return; 1255 } 1256 bus_release_resource(dev, type, rid, rle->res); 1257 } 1258 resource_list_delete(rl, type, rid); 1259 } 1260 /* 1261 * Why do we turn off the PCI configuration BAR when we delete a 1262 * resource? -- imp 1263 */ 1264 pci_write_config(child, rid, 0, 4); 1265 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1266 } 1267 1268 struct resource_list * 1269 pci_get_resource_list (device_t dev, device_t child) 1270 { 1271 struct pci_devinfo * dinfo = device_get_ivars(child); 1272 struct resource_list * rl = &dinfo->resources; 1273 1274 if (!rl) 1275 return (NULL); 1276 1277 return (rl); 1278 } 1279 1280 u_int32_t 1281 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1282 { 1283 struct pci_devinfo *dinfo = device_get_ivars(child); 1284 pcicfgregs *cfg = &dinfo->cfg; 1285 1286 return (PCIB_READ_CONFIG(device_get_parent(dev), 1287 cfg->bus, cfg->slot, cfg->func, reg, width)); 1288 } 1289 1290 void 1291 pci_write_config_method(device_t dev, device_t child, int reg, 1292 u_int32_t val, int width) 1293 { 1294 struct pci_devinfo *dinfo = device_get_ivars(child); 1295 pcicfgregs *cfg = &dinfo->cfg; 1296 1297 PCIB_WRITE_CONFIG(device_get_parent(dev), 1298 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1299 } 1300 1301 static int 1302 pci_modevent(module_t mod, int what, void *arg) 1303 { 1304 switch (what) { 1305 case MOD_LOAD: 1306 STAILQ_INIT(&pci_devq); 1307 pci_generation = 0; 1308 break; 1309 1310 case MOD_UNLOAD: 1311 break; 1312 } 1313 1314 return (0); 1315 } 1316