1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 5 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000, BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice unmodified, this list of conditions, and the following 14 * disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 #include "opt_acpi.h" 33 #include "opt_iommu.h" 34 #include "opt_bus.h" 35 36 #include <sys/param.h> 37 #include <sys/conf.h> 38 #include <sys/endian.h> 39 #include <sys/eventhandler.h> 40 #include <sys/fcntl.h> 41 #include <sys/kernel.h> 42 #include <sys/limits.h> 43 #include <sys/linker.h> 44 #include <sys/malloc.h> 45 #include <sys/module.h> 46 #include <sys/queue.h> 47 #include <sys/sbuf.h> 48 #include <sys/stdarg.h> 49 #include <sys/sysctl.h> 50 #include <sys/systm.h> 51 #include <sys/taskqueue.h> 52 #include <sys/tree.h> 53 54 #include <vm/vm.h> 55 #include <vm/pmap.h> 56 #include <vm/vm_extern.h> 57 58 #include <sys/bus.h> 59 #include <machine/bus.h> 60 #include <sys/rman.h> 61 #include <machine/resource.h> 62 63 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 64 #include <machine/intr_machdep.h> 65 #endif 66 67 #include <sys/pciio.h> 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pci_private.h> 71 72 #ifdef PCI_IOV 73 #include <sys/nv.h> 74 #include <dev/pci/pci_iov_private.h> 75 #endif 76 77 #include <dev/usb/controller/xhcireg.h> 78 #include <dev/usb/controller/ehcireg.h> 79 #include <dev/usb/controller/ohcireg.h> 80 #include <dev/usb/controller/uhcireg.h> 81 82 #include <dev/iommu/iommu.h> 83 84 #include <contrib/dev/acpica/include/acpi.h> 85 #include <dev/acpica/acpivar.h> 86 87 #include "pcib_if.h" 88 #include "pci_if.h" 89 90 #define PCIR_IS_BIOS(cfg, reg) \ 91 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ 92 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) 93 94 static device_probe_t pci_probe; 95 96 static bus_reset_post_t pci_reset_post; 97 static bus_reset_prepare_t pci_reset_prepare; 98 static bus_reset_child_t pci_reset_child; 99 static bus_hint_device_unit_t pci_hint_device_unit; 100 static bus_remap_intr_t pci_remap_intr_method; 101 102 static pci_get_id_t pci_get_id_method; 103 104 static int pci_has_quirk(uint32_t devid, int quirk); 105 static pci_addr_t pci_mapbase(uint64_t mapreg); 106 static const char *pci_maptype(uint64_t mapreg); 107 static int pci_maprange(uint64_t mapreg); 108 static pci_addr_t pci_rombase(uint64_t mapreg); 109 static int pci_romsize(uint64_t testval); 110 static void pci_fixancient(pcicfgregs *cfg); 111 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...); 112 113 static int pci_porten(device_t dev); 114 static int pci_memen(device_t dev); 115 static void pci_assign_interrupt(device_t bus, device_t dev, 116 int force_route); 117 static int pci_add_map(device_t bus, device_t dev, int reg, 118 struct resource_list *rl, int force, int prefetch); 119 static void pci_load_vendor_data(void); 120 static int pci_describe_parse_line(char **ptr, int *vendor, 121 int *device, char **desc); 122 static char *pci_describe_device(device_t dev); 123 static int pci_modevent(module_t mod, int what, void *arg); 124 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 125 pcicfgregs *cfg); 126 static void pci_read_cap(device_t pcib, pcicfgregs *cfg); 127 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 128 int reg, uint32_t *data); 129 #if 0 130 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 131 int reg, uint32_t data); 132 #endif 133 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 134 static void pci_mask_msix(device_t dev, u_int index); 135 static void pci_unmask_msix(device_t dev, u_int index); 136 static int pci_msi_blacklisted(void); 137 static int pci_msix_blacklisted(void); 138 static void pci_resume_msi(device_t dev); 139 static void pci_resume_msix(device_t dev); 140 static struct pci_devinfo * pci_fill_devinfo(device_t pcib, device_t bus, int d, 141 int b, int s, int f, uint16_t vid, uint16_t did); 142 143 static device_method_t pci_methods[] = { 144 /* Device interface */ 145 DEVMETHOD(device_probe, pci_probe), 146 DEVMETHOD(device_attach, pci_attach), 147 DEVMETHOD(device_detach, pci_detach), 148 DEVMETHOD(device_shutdown, bus_generic_shutdown), 149 DEVMETHOD(device_suspend, bus_generic_suspend), 150 DEVMETHOD(device_resume, pci_resume), 151 152 /* Bus interface */ 153 DEVMETHOD(bus_print_child, pci_print_child), 154 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 155 DEVMETHOD(bus_read_ivar, pci_read_ivar), 156 DEVMETHOD(bus_write_ivar, pci_write_ivar), 157 DEVMETHOD(bus_driver_added, pci_driver_added), 158 DEVMETHOD(bus_setup_intr, pci_setup_intr), 159 DEVMETHOD(bus_teardown_intr, pci_teardown_intr), 160 DEVMETHOD(bus_reset_prepare, pci_reset_prepare), 161 DEVMETHOD(bus_reset_post, pci_reset_post), 162 DEVMETHOD(bus_reset_child, pci_reset_child), 163 164 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag), 165 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 166 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 167 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 168 DEVMETHOD(bus_delete_resource, pci_delete_resource), 169 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 170 DEVMETHOD(bus_adjust_resource, pci_adjust_resource), 171 DEVMETHOD(bus_release_resource, pci_release_resource), 172 DEVMETHOD(bus_activate_resource, pci_activate_resource), 173 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource), 174 DEVMETHOD(bus_map_resource, pci_map_resource), 175 DEVMETHOD(bus_unmap_resource, pci_unmap_resource), 176 DEVMETHOD(bus_child_deleted, pci_child_deleted), 177 DEVMETHOD(bus_child_detached, pci_child_detached), 178 DEVMETHOD(bus_child_pnpinfo, pci_child_pnpinfo_method), 179 DEVMETHOD(bus_child_location, pci_child_location_method), 180 DEVMETHOD(bus_get_device_path, pci_get_device_path_method), 181 DEVMETHOD(bus_hint_device_unit, pci_hint_device_unit), 182 DEVMETHOD(bus_remap_intr, pci_remap_intr_method), 183 DEVMETHOD(bus_suspend_child, pci_suspend_child), 184 DEVMETHOD(bus_resume_child, pci_resume_child), 185 DEVMETHOD(bus_rescan, pci_rescan_method), 186 187 /* PCI interface */ 188 DEVMETHOD(pci_read_config, pci_read_config_method), 189 DEVMETHOD(pci_write_config, pci_write_config_method), 190 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 191 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 192 DEVMETHOD(pci_enable_io, pci_enable_io_method), 193 DEVMETHOD(pci_disable_io, pci_disable_io_method), 194 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 195 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 196 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 197 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 198 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 199 DEVMETHOD(pci_find_cap, pci_find_cap_method), 200 DEVMETHOD(pci_find_next_cap, pci_find_next_cap_method), 201 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 202 DEVMETHOD(pci_find_next_extcap, pci_find_next_extcap_method), 203 DEVMETHOD(pci_find_htcap, pci_find_htcap_method), 204 DEVMETHOD(pci_find_next_htcap, pci_find_next_htcap_method), 205 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 206 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), 207 DEVMETHOD(pci_enable_msi, pci_enable_msi_method), 208 DEVMETHOD(pci_enable_msix, pci_enable_msix_method), 209 DEVMETHOD(pci_disable_msi, pci_disable_msi_method), 210 DEVMETHOD(pci_remap_msix, pci_remap_msix_method), 211 DEVMETHOD(pci_release_msi, pci_release_msi_method), 212 DEVMETHOD(pci_msi_count, pci_msi_count_method), 213 DEVMETHOD(pci_msix_count, pci_msix_count_method), 214 DEVMETHOD(pci_msix_pba_bar, pci_msix_pba_bar_method), 215 DEVMETHOD(pci_msix_table_bar, pci_msix_table_bar_method), 216 DEVMETHOD(pci_get_id, pci_get_id_method), 217 DEVMETHOD(pci_alloc_devinfo, pci_alloc_devinfo_method), 218 DEVMETHOD(pci_child_added, pci_child_added_method), 219 #ifdef PCI_IOV 220 DEVMETHOD(pci_iov_attach, pci_iov_attach_method), 221 DEVMETHOD(pci_iov_detach, pci_iov_detach_method), 222 DEVMETHOD(pci_create_iov_child, pci_create_iov_child_method), 223 #endif 224 225 DEVMETHOD_END 226 }; 227 228 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc)); 229 230 EARLY_DRIVER_MODULE(pci, pcib, pci_driver, pci_modevent, NULL, BUS_PASS_BUS); 231 MODULE_VERSION(pci, 1); 232 233 static char *pci_vendordata; 234 static size_t pci_vendordata_size; 235 236 struct pci_quirk { 237 uint32_t devid; /* Vendor/device of the card */ 238 int type; 239 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 240 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */ 241 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */ 242 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */ 243 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */ 244 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */ 245 #define PCI_QUIRK_REALLOC_BAR 7 /* Can't allocate memory at the default address */ 246 int arg1; 247 int arg2; 248 }; 249 250 static const struct pci_quirk pci_quirks[] = { 251 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */ 252 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 253 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 254 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 255 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 256 257 /* 258 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge 259 * or the CMIC-SL (AKA ServerWorks GC_LE). 260 */ 261 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 262 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 263 264 /* 265 * MSI doesn't work on earlier Intel chipsets including 266 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855. 267 */ 268 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 269 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 270 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 271 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 272 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 273 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 274 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 275 276 /* 277 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX 278 * bridge. 279 */ 280 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 281 282 /* 283 * Some virtualization environments emulate an older chipset 284 * but support MSI just fine. QEMU uses the Intel 82440. 285 */ 286 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 }, 287 288 /* 289 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus 290 * controller depending on SoftPciRst register (PM_IO 0x55 [7]). 291 * It prevents us from attaching hpet(4) when the bit is unset. 292 * Note this quirk only affects SB600 revision A13 and earlier. 293 * For SB600 A21 and later, firmware must set the bit to hide it. 294 * For SB700 and later, it is unused and hardcoded to zero. 295 */ 296 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 }, 297 298 /* 299 * Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have 300 * a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit 301 * of the command register is set. 302 */ 303 { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 304 { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 305 { 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 306 { 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 307 { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 308 309 /* 310 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't 311 * issue MSI interrupts with PCIM_CMD_INTxDIS set either. 312 */ 313 { 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */ 314 { 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */ 315 { 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */ 316 { 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */ 317 { 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */ 318 { 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */ 319 320 /* 321 * HPE Gen 10 VGA has a memory range that can't be allocated in the 322 * expected place. 323 */ 324 { 0x98741002, PCI_QUIRK_REALLOC_BAR, 0, 0 }, 325 { 0 } 326 }; 327 328 /* map register information */ 329 #define PCI_MAPMEM 0x01 /* memory map */ 330 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 331 #define PCI_MAPPORT 0x04 /* port map */ 332 333 struct devlist pci_devq; 334 uint32_t pci_generation; 335 uint32_t pci_numdevs = 0; 336 static int pcie_chipset, pcix_chipset; 337 338 /* sysctl vars */ 339 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 340 "PCI bus tuning parameters"); 341 342 static int pci_enable_io_modes = 1; 343 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RWTUN, 344 &pci_enable_io_modes, 1, 345 "Enable I/O and memory bits in the config register. Some BIOSes do not" 346 " enable these bits correctly. We'd like to do this all the time, but" 347 " there are some peripherals that this causes problems with."); 348 349 static int pci_do_realloc_bars = 1; 350 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RWTUN, 351 &pci_do_realloc_bars, 0, 352 "Attempt to allocate a new range for any BARs whose original " 353 "firmware-assigned ranges fail to allocate during the initial device scan."); 354 355 static int pci_do_power_nodriver = 0; 356 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RWTUN, 357 &pci_do_power_nodriver, 0, 358 "Place a function into D3 state when no driver attaches to it. 0 means" 359 " disable. 1 means conservatively place function into D3 state. 2 means" 360 " aggressively place function into D3 state. 3 means put absolutely" 361 " everything in D3 state."); 362 363 int pci_do_power_resume = 1; 364 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RWTUN, 365 &pci_do_power_resume, 1, 366 "Transition from D3 -> D0 on resume."); 367 368 int pci_do_power_suspend = 1; 369 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RWTUN, 370 &pci_do_power_suspend, 1, 371 "Transition from D0 -> D3 on suspend."); 372 373 static int pci_do_msi = 1; 374 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RWTUN, &pci_do_msi, 1, 375 "Enable support for MSI interrupts"); 376 377 static int pci_do_msix = 1; 378 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RWTUN, &pci_do_msix, 1, 379 "Enable support for MSI-X interrupts"); 380 381 static int pci_msix_rewrite_table = 0; 382 SYSCTL_INT(_hw_pci, OID_AUTO, msix_rewrite_table, CTLFLAG_RWTUN, 383 &pci_msix_rewrite_table, 0, 384 "Rewrite entire MSI-X table when updating MSI-X entries"); 385 386 static int pci_honor_msi_blacklist = 1; 387 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RDTUN, 388 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X"); 389 390 #if defined(__i386__) || defined(__amd64__) 391 static int pci_usb_takeover = 1; 392 #else 393 static int pci_usb_takeover = 0; 394 #endif 395 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN, 396 &pci_usb_takeover, 1, 397 "Enable early takeover of USB controllers. Disable this if you depend on" 398 " BIOS emulation of USB devices, that is you use USB devices (like" 399 " keyboard or mouse) but do not load USB drivers"); 400 401 static int pci_clear_bars; 402 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0, 403 "Ignore firmware-assigned resources for BARs."); 404 405 static int pci_clear_buses; 406 SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0, 407 "Ignore firmware-assigned bus numbers."); 408 409 static int pci_enable_ari = 1; 410 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari, 411 0, "Enable support for PCIe Alternative RID Interpretation"); 412 413 /* 414 * Some x86 firmware only enables PCIe hotplug if we claim to support aspm, 415 * however enabling it breaks some arm64 firmware as it powers off devices. 416 */ 417 #if defined(__i386__) || defined(__amd64__) 418 int pci_enable_aspm = 1; 419 #else 420 int pci_enable_aspm = 0; 421 #endif 422 SYSCTL_INT(_hw_pci, OID_AUTO, enable_aspm, CTLFLAG_RDTUN, &pci_enable_aspm, 423 0, "Enable support for PCIe Active State Power Management"); 424 425 static int pci_clear_aer_on_attach = 0; 426 SYSCTL_INT(_hw_pci, OID_AUTO, clear_aer_on_attach, CTLFLAG_RWTUN, 427 &pci_clear_aer_on_attach, 0, 428 "Clear port and device AER state on driver attach"); 429 430 static bool pci_enable_mps_tune = true; 431 SYSCTL_BOOL(_hw_pci, OID_AUTO, enable_mps_tune, CTLFLAG_RWTUN, 432 &pci_enable_mps_tune, 1, 433 "Enable tuning of MPS(maximum payload size)." ); 434 435 static bool pci_intx_reroute = true; 436 SYSCTL_BOOL(_hw_pci, OID_AUTO, intx_reroute, CTLFLAG_RWTUN, 437 &pci_intx_reroute, 0, "Re-route INTx interrupts when scanning devices"); 438 439 static int 440 pci_has_quirk(uint32_t devid, int quirk) 441 { 442 const struct pci_quirk *q; 443 444 for (q = &pci_quirks[0]; q->devid; q++) { 445 if (q->devid == devid && q->type == quirk) 446 return (1); 447 } 448 return (0); 449 } 450 451 /* Find a device_t by bus/slot/function in domain 0 */ 452 453 device_t 454 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 455 { 456 457 return (pci_find_dbsf(0, bus, slot, func)); 458 } 459 460 /* Find a device_t by domain/bus/slot/function */ 461 462 device_t 463 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func) 464 { 465 struct pci_devinfo *dinfo = NULL; 466 467 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 468 if ((dinfo->cfg.domain == domain) && 469 (dinfo->cfg.bus == bus) && 470 (dinfo->cfg.slot == slot) && 471 (dinfo->cfg.func == func)) { 472 break; 473 } 474 } 475 476 return (dinfo != NULL ? dinfo->cfg.dev : NULL); 477 } 478 479 /* Find a device_t by vendor/device ID */ 480 481 device_t 482 pci_find_device(uint16_t vendor, uint16_t device) 483 { 484 struct pci_devinfo *dinfo; 485 486 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 487 if ((dinfo->cfg.vendor == vendor) && 488 (dinfo->cfg.device == device)) { 489 return (dinfo->cfg.dev); 490 } 491 } 492 493 return (NULL); 494 } 495 496 device_t 497 pci_find_class(uint8_t class, uint8_t subclass) 498 { 499 struct pci_devinfo *dinfo; 500 501 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 502 if (dinfo->cfg.baseclass == class && 503 dinfo->cfg.subclass == subclass) { 504 return (dinfo->cfg.dev); 505 } 506 } 507 508 return (NULL); 509 } 510 511 device_t 512 pci_find_class_from(uint8_t class, uint8_t subclass, device_t from) 513 { 514 struct pci_devinfo *dinfo; 515 bool found = false; 516 517 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 518 if (from != NULL && found == false) { 519 if (from != dinfo->cfg.dev) 520 continue; 521 found = true; 522 continue; 523 } 524 if (dinfo->cfg.baseclass == class && 525 dinfo->cfg.subclass == subclass) { 526 return (dinfo->cfg.dev); 527 } 528 } 529 530 return (NULL); 531 } 532 533 device_t 534 pci_find_base_class_from(uint8_t class, device_t from) 535 { 536 struct pci_devinfo *dinfo; 537 bool found = false; 538 539 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 540 if (from != NULL && found == false) { 541 if (from != dinfo->cfg.dev) 542 continue; 543 found = true; 544 continue; 545 } 546 if (dinfo->cfg.baseclass == class) { 547 return (dinfo->cfg.dev); 548 } 549 } 550 551 return (NULL); 552 } 553 554 static int 555 pci_printf(pcicfgregs *cfg, const char *fmt, ...) 556 { 557 va_list ap; 558 int retval; 559 560 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, 561 cfg->func); 562 va_start(ap, fmt); 563 retval += vprintf(fmt, ap); 564 va_end(ap); 565 return (retval); 566 } 567 568 /* return base address of memory or port map */ 569 570 static pci_addr_t 571 pci_mapbase(uint64_t mapreg) 572 { 573 574 if (PCI_BAR_MEM(mapreg)) 575 return (mapreg & PCIM_BAR_MEM_BASE); 576 else 577 return (mapreg & PCIM_BAR_IO_BASE); 578 } 579 580 /* return map type of memory or port map */ 581 582 static const char * 583 pci_maptype(uint64_t mapreg) 584 { 585 586 if (PCI_BAR_IO(mapreg)) 587 return ("I/O Port"); 588 if (mapreg & PCIM_BAR_MEM_PREFETCH) 589 return ("Prefetchable Memory"); 590 return ("Memory"); 591 } 592 593 /* return log2 of map size decoded for memory or port map */ 594 595 int 596 pci_mapsize(uint64_t testval) 597 { 598 int ln2size; 599 600 testval = pci_mapbase(testval); 601 ln2size = 0; 602 if (testval != 0) { 603 while ((testval & 1) == 0) 604 { 605 ln2size++; 606 testval >>= 1; 607 } 608 } 609 return (ln2size); 610 } 611 612 /* return base address of device ROM */ 613 614 static pci_addr_t 615 pci_rombase(uint64_t mapreg) 616 { 617 618 return (mapreg & PCIM_BIOS_ADDR_MASK); 619 } 620 621 /* return log2 of map size decided for device ROM */ 622 623 static int 624 pci_romsize(uint64_t testval) 625 { 626 int ln2size; 627 628 testval = pci_rombase(testval); 629 ln2size = 0; 630 if (testval != 0) { 631 while ((testval & 1) == 0) 632 { 633 ln2size++; 634 testval >>= 1; 635 } 636 } 637 return (ln2size); 638 } 639 640 /* return log2 of address range supported by map register */ 641 642 static int 643 pci_maprange(uint64_t mapreg) 644 { 645 int ln2range = 0; 646 647 if (PCI_BAR_IO(mapreg)) 648 ln2range = 32; 649 else 650 switch (mapreg & PCIM_BAR_MEM_TYPE) { 651 case PCIM_BAR_MEM_32: 652 ln2range = 32; 653 break; 654 case PCIM_BAR_MEM_1MB: 655 ln2range = 20; 656 break; 657 case PCIM_BAR_MEM_64: 658 ln2range = 64; 659 break; 660 } 661 return (ln2range); 662 } 663 664 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 665 666 static void 667 pci_fixancient(pcicfgregs *cfg) 668 { 669 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 670 return; 671 672 /* PCI to PCI bridges use header type 1 */ 673 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 674 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; 675 } 676 677 /* extract header type specific config data */ 678 679 static void 680 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 681 { 682 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 683 switch (cfg->hdrtype & PCIM_HDRTYPE) { 684 case PCIM_HDRTYPE_NORMAL: 685 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 686 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 687 cfg->mingnt = REG(PCIR_MINGNT, 1); 688 cfg->maxlat = REG(PCIR_MAXLAT, 1); 689 cfg->nummaps = PCI_MAXMAPS_0; 690 break; 691 case PCIM_HDRTYPE_BRIDGE: 692 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1); 693 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1); 694 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1); 695 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1); 696 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2); 697 cfg->nummaps = PCI_MAXMAPS_1; 698 break; 699 case PCIM_HDRTYPE_CARDBUS: 700 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1); 701 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1); 702 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1); 703 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1); 704 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2); 705 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 706 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 707 cfg->nummaps = PCI_MAXMAPS_2; 708 break; 709 } 710 #undef REG 711 } 712 713 /* read configuration header into pcicfgregs structure */ 714 struct pci_devinfo * 715 pci_read_device(device_t pcib, device_t bus, int d, int b, int s, int f) 716 { 717 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 718 uint16_t vid, did; 719 720 vid = REG(PCIR_VENDOR, 2); 721 if (vid == PCIV_INVALID) 722 return (NULL); 723 724 did = REG(PCIR_DEVICE, 2); 725 726 return (pci_fill_devinfo(pcib, bus, d, b, s, f, vid, did)); 727 } 728 729 struct pci_devinfo * 730 pci_alloc_devinfo_method(device_t dev) 731 { 732 733 return (malloc(sizeof(struct pci_devinfo), M_DEVBUF, 734 M_WAITOK | M_ZERO)); 735 } 736 737 static struct pci_devinfo * 738 pci_fill_devinfo(device_t pcib, device_t bus, int d, int b, int s, int f, 739 uint16_t vid, uint16_t did) 740 { 741 struct pci_devinfo *devlist_entry; 742 pcicfgregs *cfg; 743 744 devlist_entry = PCI_ALLOC_DEVINFO(bus); 745 746 cfg = &devlist_entry->cfg; 747 748 cfg->domain = d; 749 cfg->bus = b; 750 cfg->slot = s; 751 cfg->func = f; 752 cfg->vendor = vid; 753 cfg->device = did; 754 cfg->cmdreg = REG(PCIR_COMMAND, 2); 755 cfg->statreg = REG(PCIR_STATUS, 2); 756 cfg->baseclass = REG(PCIR_CLASS, 1); 757 cfg->subclass = REG(PCIR_SUBCLASS, 1); 758 cfg->progif = REG(PCIR_PROGIF, 1); 759 cfg->revid = REG(PCIR_REVID, 1); 760 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 761 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 762 cfg->lattimer = REG(PCIR_LATTIMER, 1); 763 cfg->intpin = REG(PCIR_INTPIN, 1); 764 cfg->intline = REG(PCIR_INTLINE, 1); 765 766 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 767 cfg->hdrtype &= ~PCIM_MFDEV; 768 STAILQ_INIT(&cfg->maps); 769 770 cfg->iov = NULL; 771 772 pci_fixancient(cfg); 773 pci_hdrtypedata(pcib, b, s, f, cfg); 774 775 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 776 pci_read_cap(pcib, cfg); 777 778 STAILQ_INSERT_TAIL(&pci_devq, devlist_entry, pci_links); 779 780 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; 781 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 782 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 783 devlist_entry->conf.pc_sel.pc_func = cfg->func; 784 devlist_entry->conf.pc_hdr = cfg->hdrtype; 785 786 devlist_entry->conf.pc_subvendor = cfg->subvendor; 787 devlist_entry->conf.pc_subdevice = cfg->subdevice; 788 devlist_entry->conf.pc_vendor = cfg->vendor; 789 devlist_entry->conf.pc_device = cfg->device; 790 791 devlist_entry->conf.pc_class = cfg->baseclass; 792 devlist_entry->conf.pc_subclass = cfg->subclass; 793 devlist_entry->conf.pc_progif = cfg->progif; 794 devlist_entry->conf.pc_revid = cfg->revid; 795 796 pci_numdevs++; 797 pci_generation++; 798 799 return (devlist_entry); 800 } 801 #undef REG 802 803 static void 804 pci_ea_fill_info(device_t pcib, pcicfgregs *cfg) 805 { 806 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \ 807 cfg->ea.ea_location + (n), w) 808 int num_ent; 809 int ptr; 810 int a, b; 811 uint32_t val; 812 int ent_size; 813 uint32_t dw[4]; 814 uint64_t base, max_offset; 815 struct pci_ea_entry *eae; 816 817 if (cfg->ea.ea_location == 0) 818 return; 819 820 STAILQ_INIT(&cfg->ea.ea_entries); 821 822 /* Determine the number of entries */ 823 num_ent = REG(PCIR_EA_NUM_ENT, 2); 824 num_ent &= PCIM_EA_NUM_ENT_MASK; 825 826 /* Find the first entry to care of */ 827 ptr = PCIR_EA_FIRST_ENT; 828 829 /* Skip DWORD 2 for type 1 functions */ 830 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) 831 ptr += 4; 832 833 for (a = 0; a < num_ent; a++) { 834 eae = malloc(sizeof(*eae), M_DEVBUF, M_WAITOK | M_ZERO); 835 eae->eae_cfg_offset = cfg->ea.ea_location + ptr; 836 837 /* Read a number of dwords in the entry */ 838 val = REG(ptr, 4); 839 ptr += 4; 840 ent_size = (val & PCIM_EA_ES); 841 842 for (b = 0; b < ent_size; b++) { 843 dw[b] = REG(ptr, 4); 844 ptr += 4; 845 } 846 847 eae->eae_flags = val; 848 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 849 850 base = dw[0] & PCIM_EA_FIELD_MASK; 851 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 852 b = 2; 853 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 854 base |= (uint64_t)dw[b] << 32UL; 855 b++; 856 } 857 if (((dw[1] & PCIM_EA_IS_64) != 0) 858 && (b < ent_size)) { 859 max_offset |= (uint64_t)dw[b] << 32UL; 860 b++; 861 } 862 863 eae->eae_base = base; 864 eae->eae_max_offset = max_offset; 865 866 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link); 867 868 if (bootverbose) { 869 printf("PCI(EA) dev %04x:%04x, bei %d, flags #%x, base #%jx, max_offset #%jx\n", 870 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags, 871 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset); 872 } 873 } 874 } 875 #undef REG 876 877 static void 878 pci_read_cap(device_t pcib, pcicfgregs *cfg) 879 { 880 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 881 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 882 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 883 uint64_t addr; 884 #endif 885 uint32_t val; 886 int ptr, nextptr, ptrptr; 887 888 switch (cfg->hdrtype & PCIM_HDRTYPE) { 889 case PCIM_HDRTYPE_NORMAL: 890 case PCIM_HDRTYPE_BRIDGE: 891 ptrptr = PCIR_CAP_PTR; 892 break; 893 case PCIM_HDRTYPE_CARDBUS: 894 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 895 break; 896 default: 897 return; /* no extended capabilities support */ 898 } 899 nextptr = REG(ptrptr, 1); /* sanity check? */ 900 901 /* 902 * Read capability entries. 903 */ 904 while (nextptr != 0) { 905 /* Sanity check */ 906 if (nextptr > 255) { 907 printf("illegal PCI extended capability offset %d\n", 908 nextptr); 909 return; 910 } 911 /* Find the next entry */ 912 ptr = nextptr; 913 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 914 915 /* Process this entry */ 916 switch (REG(ptr + PCICAP_ID, 1)) { 917 case PCIY_PMG: /* PCI power management */ 918 cfg->pp.pp_location = ptr; 919 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 920 break; 921 case PCIY_HT: /* HyperTransport */ 922 /* Determine HT-specific capability type. */ 923 val = REG(ptr + PCIR_HT_COMMAND, 2); 924 925 if ((val & 0xe000) == PCIM_HTCAP_SLAVE) 926 cfg->ht.ht_slave = ptr; 927 928 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 929 switch (val & PCIM_HTCMD_CAP_MASK) { 930 case PCIM_HTCAP_MSI_MAPPING: 931 if (!(val & PCIM_HTCMD_MSI_FIXED)) { 932 /* Sanity check the mapping window. */ 933 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 934 4); 935 addr <<= 32; 936 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 937 4); 938 if (addr != MSI_INTEL_ADDR_BASE) 939 device_printf(pcib, 940 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", 941 cfg->domain, cfg->bus, 942 cfg->slot, cfg->func, 943 (long long)addr); 944 } else 945 addr = MSI_INTEL_ADDR_BASE; 946 947 cfg->ht.ht_msimap = ptr; 948 cfg->ht.ht_msictrl = val; 949 cfg->ht.ht_msiaddr = addr; 950 break; 951 } 952 #endif 953 break; 954 case PCIY_MSI: /* PCI MSI */ 955 cfg->msi.msi_location = ptr; 956 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 957 break; 958 case PCIY_MSIX: /* PCI MSI-X */ 959 cfg->msix.msix_location = ptr; 960 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 961 val = REG(ptr + PCIR_MSIX_TABLE, 4); 962 cfg->msix.msix_table_bar = PCIR_BAR(val & 963 PCIM_MSIX_BIR_MASK); 964 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 965 val = REG(ptr + PCIR_MSIX_PBA, 4); 966 cfg->msix.msix_pba_bar = PCIR_BAR(val & 967 PCIM_MSIX_BIR_MASK); 968 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 969 break; 970 case PCIY_VPD: /* PCI Vital Product Data */ 971 cfg->vpd.vpd_reg = ptr; 972 break; 973 case PCIY_SUBVENDOR: 974 /* Should always be true. */ 975 if ((cfg->hdrtype & PCIM_HDRTYPE) == 976 PCIM_HDRTYPE_BRIDGE) { 977 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4); 978 cfg->subvendor = val & 0xffff; 979 cfg->subdevice = val >> 16; 980 } 981 break; 982 case PCIY_PCIX: /* PCI-X */ 983 /* 984 * Assume we have a PCI-X chipset if we have 985 * at least one PCI-PCI bridge with a PCI-X 986 * capability. Note that some systems with 987 * PCI-express or HT chipsets might match on 988 * this check as well. 989 */ 990 if ((cfg->hdrtype & PCIM_HDRTYPE) == 991 PCIM_HDRTYPE_BRIDGE) 992 pcix_chipset = 1; 993 cfg->pcix.pcix_location = ptr; 994 break; 995 case PCIY_EXPRESS: /* PCI-express */ 996 /* 997 * Assume we have a PCI-express chipset if we have 998 * at least one PCI-express device. 999 */ 1000 pcie_chipset = 1; 1001 cfg->pcie.pcie_location = ptr; 1002 val = REG(ptr + PCIER_FLAGS, 2); 1003 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; 1004 break; 1005 case PCIY_EA: /* Enhanced Allocation */ 1006 cfg->ea.ea_location = ptr; 1007 pci_ea_fill_info(pcib, cfg); 1008 break; 1009 default: 1010 break; 1011 } 1012 } 1013 1014 #if defined(__powerpc__) 1015 /* 1016 * Enable the MSI mapping window for all HyperTransport 1017 * slaves. PCI-PCI bridges have their windows enabled via 1018 * PCIB_MAP_MSI(). 1019 */ 1020 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && 1021 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { 1022 device_printf(pcib, 1023 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n", 1024 cfg->domain, cfg->bus, cfg->slot, cfg->func); 1025 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 1026 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, 1027 2); 1028 } 1029 #endif 1030 /* REG and WREG use carry through to next functions */ 1031 } 1032 1033 /* 1034 * PCI Vital Product Data 1035 */ 1036 1037 #define PCI_VPD_TIMEOUT 1000000 1038 1039 static int 1040 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data) 1041 { 1042 int count = PCI_VPD_TIMEOUT; 1043 1044 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1045 1046 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); 1047 1048 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { 1049 if (--count < 0) 1050 return (ENXIO); 1051 DELAY(1); /* limit looping */ 1052 } 1053 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); 1054 1055 return (0); 1056 } 1057 1058 #if 0 1059 static int 1060 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 1061 { 1062 int count = PCI_VPD_TIMEOUT; 1063 1064 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1065 1066 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4); 1067 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2); 1068 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) { 1069 if (--count < 0) 1070 return (ENXIO); 1071 DELAY(1); /* limit looping */ 1072 } 1073 1074 return (0); 1075 } 1076 #endif 1077 1078 #undef PCI_VPD_TIMEOUT 1079 1080 struct vpd_readstate { 1081 device_t pcib; 1082 pcicfgregs *cfg; 1083 uint32_t val; 1084 int bytesinval; 1085 int off; 1086 uint8_t cksum; 1087 }; 1088 1089 /* return 0 and one byte in *data if no read error, -1 else */ 1090 static int 1091 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data) 1092 { 1093 uint32_t reg; 1094 uint8_t byte; 1095 1096 if (vrs->bytesinval == 0) { 1097 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) 1098 return (-1); 1099 vrs->val = le32toh(reg); 1100 vrs->off += 4; 1101 byte = vrs->val & 0xff; 1102 vrs->bytesinval = 3; 1103 } else { 1104 vrs->val = vrs->val >> 8; 1105 byte = vrs->val & 0xff; 1106 vrs->bytesinval--; 1107 } 1108 1109 vrs->cksum += byte; 1110 *data = byte; 1111 return (0); 1112 } 1113 1114 /* return 0 on match, -1 and "unget" byte on no match */ 1115 static int 1116 vpd_expectbyte(struct vpd_readstate *vrs, uint8_t expected) 1117 { 1118 uint8_t data; 1119 1120 if (vpd_nextbyte(vrs, &data) != 0) 1121 return (-1); 1122 1123 if (data == expected) 1124 return (0); 1125 1126 vrs->cksum -= data; 1127 vrs->val = (vrs->val << 8) + data; 1128 vrs->bytesinval++; 1129 return (-1); 1130 } 1131 1132 /* return size if tag matches, -1 on no match, -2 on read error */ 1133 static int 1134 vpd_read_tag_size(struct vpd_readstate *vrs, uint8_t vpd_tag) 1135 { 1136 uint8_t byte1, byte2; 1137 1138 if (vpd_expectbyte(vrs, vpd_tag) != 0) 1139 return (-1); 1140 1141 if ((vpd_tag & 0x80) == 0) 1142 return (vpd_tag & 0x07); 1143 1144 if (vpd_nextbyte(vrs, &byte1) != 0) 1145 return (-2); 1146 if (vpd_nextbyte(vrs, &byte2) != 0) 1147 return (-2); 1148 1149 return ((byte2 << 8) + byte1); 1150 } 1151 1152 /* (re)allocate buffer in multiples of 8 elements */ 1153 static void* 1154 alloc_buffer(void* buffer, size_t element_size, int needed) 1155 { 1156 int alloc, new_alloc; 1157 1158 alloc = roundup2(needed, 8); 1159 new_alloc = roundup2(needed + 1, 8); 1160 if (alloc != new_alloc) { 1161 buffer = reallocf(buffer, 1162 new_alloc * element_size, M_DEVBUF, M_WAITOK | M_ZERO); 1163 } 1164 1165 return (buffer); 1166 } 1167 1168 /* read VPD keyword and return element size, return -1 on read error */ 1169 static int 1170 vpd_read_elem_head(struct vpd_readstate *vrs, char keyword[2]) 1171 { 1172 uint8_t data; 1173 1174 if (vpd_nextbyte(vrs, &keyword[0]) != 0) 1175 return (-1); 1176 if (vpd_nextbyte(vrs, &keyword[1]) != 0) 1177 return (-1); 1178 if (vpd_nextbyte(vrs, &data) != 0) 1179 return (-1); 1180 1181 return (data); 1182 } 1183 1184 /* read VPD data element of given size into allocated buffer */ 1185 static char * 1186 vpd_read_value(struct vpd_readstate *vrs, int size) 1187 { 1188 int i; 1189 char char1; 1190 char *value; 1191 1192 value = malloc(size + 1, M_DEVBUF, M_WAITOK); 1193 for (i = 0; i < size; i++) { 1194 if (vpd_nextbyte(vrs, &char1) != 0) { 1195 free(value, M_DEVBUF); 1196 return (NULL); 1197 } 1198 value[i] = char1; 1199 } 1200 value[size] = '\0'; 1201 1202 return (value); 1203 } 1204 1205 /* read VPD into *keyword and *value, return length of data element */ 1206 static int 1207 vpd_read_elem_data(struct vpd_readstate *vrs, char keyword[2], char **value, int maxlen) 1208 { 1209 int len; 1210 1211 len = vpd_read_elem_head(vrs, keyword); 1212 if (len < 0 || len > maxlen) 1213 return (-1); 1214 *value = vpd_read_value(vrs, len); 1215 1216 return (len); 1217 } 1218 1219 /* subtract all data following first byte from checksum of RV element */ 1220 static void 1221 vpd_fixup_cksum(struct vpd_readstate *vrs, char *rvstring, int len) 1222 { 1223 int i; 1224 uint8_t fixup; 1225 1226 fixup = 0; 1227 for (i = 1; i < len; i++) 1228 fixup += rvstring[i]; 1229 vrs->cksum -= fixup; 1230 } 1231 1232 /* fetch one read-only element and return size of heading + data */ 1233 static int 1234 next_vpd_ro_elem(struct vpd_readstate *vrs, int maxsize) 1235 { 1236 struct pcicfg_vpd *vpd; 1237 pcicfgregs *cfg; 1238 struct vpd_readonly *vpd_ros; 1239 int len; 1240 1241 cfg = vrs->cfg; 1242 vpd = &cfg->vpd; 1243 1244 if (maxsize < 3) 1245 return (-1); 1246 vpd->vpd_ros = alloc_buffer(vpd->vpd_ros, sizeof(*vpd->vpd_ros), vpd->vpd_rocnt); 1247 vpd_ros = &vpd->vpd_ros[vpd->vpd_rocnt]; 1248 maxsize -= 3; 1249 len = vpd_read_elem_data(vrs, vpd_ros->keyword, &vpd_ros->value, maxsize); 1250 if (vpd_ros->value == NULL) 1251 return (-1); 1252 vpd_ros->len = len; 1253 if (vpd_ros->keyword[0] == 'R' && vpd_ros->keyword[1] == 'V') { 1254 vpd_fixup_cksum(vrs, vpd_ros->value, len); 1255 if (vrs->cksum != 0) { 1256 pci_printf(cfg, 1257 "invalid VPD checksum %#hhx\n", vrs->cksum); 1258 return (-1); 1259 } 1260 } 1261 vpd->vpd_rocnt++; 1262 1263 return (len + 3); 1264 } 1265 1266 /* fetch one writable element and return size of heading + data */ 1267 static int 1268 next_vpd_rw_elem(struct vpd_readstate *vrs, int maxsize) 1269 { 1270 struct pcicfg_vpd *vpd; 1271 pcicfgregs *cfg; 1272 struct vpd_write *vpd_w; 1273 int len; 1274 1275 cfg = vrs->cfg; 1276 vpd = &cfg->vpd; 1277 1278 if (maxsize < 3) 1279 return (-1); 1280 vpd->vpd_w = alloc_buffer(vpd->vpd_w, sizeof(*vpd->vpd_w), vpd->vpd_wcnt); 1281 if (vpd->vpd_w == NULL) { 1282 pci_printf(cfg, "out of memory"); 1283 return (-1); 1284 } 1285 vpd_w = &vpd->vpd_w[vpd->vpd_wcnt]; 1286 maxsize -= 3; 1287 vpd_w->start = vrs->off + 3 - vrs->bytesinval; 1288 len = vpd_read_elem_data(vrs, vpd_w->keyword, &vpd_w->value, maxsize); 1289 if (vpd_w->value == NULL) 1290 return (-1); 1291 vpd_w->len = len; 1292 vpd->vpd_wcnt++; 1293 1294 return (len + 3); 1295 } 1296 1297 /* free all memory allocated for VPD data */ 1298 static void 1299 vpd_free(struct pcicfg_vpd *vpd) 1300 { 1301 int i; 1302 1303 free(vpd->vpd_ident, M_DEVBUF); 1304 for (i = 0; i < vpd->vpd_rocnt; i++) 1305 free(vpd->vpd_ros[i].value, M_DEVBUF); 1306 free(vpd->vpd_ros, M_DEVBUF); 1307 vpd->vpd_rocnt = 0; 1308 for (i = 0; i < vpd->vpd_wcnt; i++) 1309 free(vpd->vpd_w[i].value, M_DEVBUF); 1310 free(vpd->vpd_w, M_DEVBUF); 1311 vpd->vpd_wcnt = 0; 1312 } 1313 1314 #define VPD_TAG_END ((0x0f << 3) | 0) /* small tag, len == 0 */ 1315 #define VPD_TAG_IDENT (0x02 | 0x80) /* large tag */ 1316 #define VPD_TAG_RO (0x10 | 0x80) /* large tag */ 1317 #define VPD_TAG_RW (0x11 | 0x80) /* large tag */ 1318 1319 static int 1320 pci_parse_vpd(device_t pcib, pcicfgregs *cfg) 1321 { 1322 struct vpd_readstate vrs; 1323 int cksumvalid; 1324 int size, elem_size; 1325 1326 /* init vpd reader */ 1327 vrs.bytesinval = 0; 1328 vrs.off = 0; 1329 vrs.pcib = pcib; 1330 vrs.cfg = cfg; 1331 vrs.cksum = 0; 1332 1333 /* read VPD ident element - mandatory */ 1334 size = vpd_read_tag_size(&vrs, VPD_TAG_IDENT); 1335 if (size <= 0) { 1336 pci_printf(cfg, "no VPD ident found\n"); 1337 return (0); 1338 } 1339 cfg->vpd.vpd_ident = vpd_read_value(&vrs, size); 1340 if (cfg->vpd.vpd_ident == NULL) { 1341 pci_printf(cfg, "error accessing VPD ident data\n"); 1342 return (0); 1343 } 1344 1345 /* read VPD RO elements - mandatory */ 1346 size = vpd_read_tag_size(&vrs, VPD_TAG_RO); 1347 if (size <= 0) { 1348 pci_printf(cfg, "no read-only VPD data found\n"); 1349 return (0); 1350 } 1351 while (size > 0) { 1352 elem_size = next_vpd_ro_elem(&vrs, size); 1353 if (elem_size < 0) { 1354 pci_printf(cfg, "error accessing read-only VPD data\n"); 1355 return (-1); 1356 } 1357 size -= elem_size; 1358 } 1359 cksumvalid = (vrs.cksum == 0); 1360 if (!cksumvalid) 1361 return (-1); 1362 1363 /* read VPD RW elements - optional */ 1364 size = vpd_read_tag_size(&vrs, VPD_TAG_RW); 1365 if (size == -2) 1366 return (-1); 1367 while (size > 0) { 1368 elem_size = next_vpd_rw_elem(&vrs, size); 1369 if (elem_size < 0) { 1370 pci_printf(cfg, "error accessing writeable VPD data\n"); 1371 return (-1); 1372 } 1373 size -= elem_size; 1374 } 1375 1376 /* read empty END tag - mandatory */ 1377 size = vpd_read_tag_size(&vrs, VPD_TAG_END); 1378 if (size != 0) { 1379 pci_printf(cfg, "No valid VPD end tag found\n"); 1380 } 1381 return (0); 1382 } 1383 1384 static void 1385 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 1386 { 1387 int status; 1388 1389 status = pci_parse_vpd(pcib, cfg); 1390 if (status < 0) 1391 vpd_free(&cfg->vpd); 1392 cfg->vpd.vpd_cached = 1; 1393 #undef REG 1394 #undef WREG 1395 } 1396 1397 int 1398 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 1399 { 1400 struct pci_devinfo *dinfo = device_get_ivars(child); 1401 pcicfgregs *cfg = &dinfo->cfg; 1402 1403 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1404 pci_read_vpd(device_get_parent(dev), cfg); 1405 1406 *identptr = cfg->vpd.vpd_ident; 1407 1408 if (*identptr == NULL) 1409 return (ENXIO); 1410 1411 return (0); 1412 } 1413 1414 int 1415 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 1416 const char **vptr) 1417 { 1418 struct pci_devinfo *dinfo = device_get_ivars(child); 1419 pcicfgregs *cfg = &dinfo->cfg; 1420 int i; 1421 1422 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1423 pci_read_vpd(device_get_parent(dev), cfg); 1424 1425 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 1426 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 1427 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { 1428 *vptr = cfg->vpd.vpd_ros[i].value; 1429 return (0); 1430 } 1431 1432 *vptr = NULL; 1433 return (ENXIO); 1434 } 1435 1436 struct pcicfg_vpd * 1437 pci_fetch_vpd_list(device_t dev) 1438 { 1439 struct pci_devinfo *dinfo = device_get_ivars(dev); 1440 pcicfgregs *cfg = &dinfo->cfg; 1441 1442 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1443 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg); 1444 return (&cfg->vpd); 1445 } 1446 1447 /* 1448 * Find the requested HyperTransport capability and return the offset 1449 * in configuration space via the pointer provided. The function 1450 * returns 0 on success and an error code otherwise. 1451 */ 1452 int 1453 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg) 1454 { 1455 int ptr, error; 1456 uint16_t val; 1457 1458 error = pci_find_cap(child, PCIY_HT, &ptr); 1459 if (error) 1460 return (error); 1461 1462 /* 1463 * Traverse the capabilities list checking each HT capability 1464 * to see if it matches the requested HT capability. 1465 */ 1466 for (;;) { 1467 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1468 if (capability == PCIM_HTCAP_SLAVE || 1469 capability == PCIM_HTCAP_HOST) 1470 val &= 0xe000; 1471 else 1472 val &= PCIM_HTCMD_CAP_MASK; 1473 if (val == capability) { 1474 if (capreg != NULL) 1475 *capreg = ptr; 1476 return (0); 1477 } 1478 1479 /* Skip to the next HT capability. */ 1480 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1481 break; 1482 } 1483 1484 return (ENOENT); 1485 } 1486 1487 /* 1488 * Find the next requested HyperTransport capability after start and return 1489 * the offset in configuration space via the pointer provided. The function 1490 * returns 0 on success and an error code otherwise. 1491 */ 1492 int 1493 pci_find_next_htcap_method(device_t dev, device_t child, int capability, 1494 int start, int *capreg) 1495 { 1496 int ptr; 1497 uint16_t val; 1498 1499 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == PCIY_HT, 1500 ("start capability is not HyperTransport capability")); 1501 ptr = start; 1502 1503 /* 1504 * Traverse the capabilities list checking each HT capability 1505 * to see if it matches the requested HT capability. 1506 */ 1507 for (;;) { 1508 /* Skip to the next HT capability. */ 1509 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1510 break; 1511 1512 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1513 if (capability == PCIM_HTCAP_SLAVE || 1514 capability == PCIM_HTCAP_HOST) 1515 val &= 0xe000; 1516 else 1517 val &= PCIM_HTCMD_CAP_MASK; 1518 if (val == capability) { 1519 if (capreg != NULL) 1520 *capreg = ptr; 1521 return (0); 1522 } 1523 } 1524 1525 return (ENOENT); 1526 } 1527 1528 /* 1529 * Find the requested capability and return the offset in 1530 * configuration space via the pointer provided. The function returns 1531 * 0 on success and an error code otherwise. 1532 */ 1533 int 1534 pci_find_cap_method(device_t dev, device_t child, int capability, 1535 int *capreg) 1536 { 1537 struct pci_devinfo *dinfo = device_get_ivars(child); 1538 pcicfgregs *cfg = &dinfo->cfg; 1539 uint32_t status; 1540 uint8_t ptr; 1541 int cnt; 1542 1543 /* 1544 * Check the CAP_LIST bit of the PCI status register first. 1545 */ 1546 status = pci_read_config(child, PCIR_STATUS, 2); 1547 if (!(status & PCIM_STATUS_CAPPRESENT)) 1548 return (ENXIO); 1549 1550 /* 1551 * Determine the start pointer of the capabilities list. 1552 */ 1553 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1554 case PCIM_HDRTYPE_NORMAL: 1555 case PCIM_HDRTYPE_BRIDGE: 1556 ptr = PCIR_CAP_PTR; 1557 break; 1558 case PCIM_HDRTYPE_CARDBUS: 1559 ptr = PCIR_CAP_PTR_2; 1560 break; 1561 default: 1562 /* XXX: panic? */ 1563 return (ENXIO); /* no extended capabilities support */ 1564 } 1565 ptr = pci_read_config(child, ptr, 1); 1566 1567 /* 1568 * Traverse the capabilities list. Limit by total theoretical 1569 * maximum number of caps: capability needs at least id and 1570 * next registers, and any type X header cannot contain caps. 1571 */ 1572 for (cnt = 0; ptr != 0 && cnt < (PCIE_REGMAX - 0x40) / 2; cnt++) { 1573 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1574 if (capreg != NULL) 1575 *capreg = ptr; 1576 return (0); 1577 } 1578 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1579 } 1580 1581 return (ENOENT); 1582 } 1583 1584 /* 1585 * Find the next requested capability after start and return the offset in 1586 * configuration space via the pointer provided. The function returns 1587 * 0 on success and an error code otherwise. 1588 */ 1589 int 1590 pci_find_next_cap_method(device_t dev, device_t child, int capability, 1591 int start, int *capreg) 1592 { 1593 uint8_t ptr; 1594 1595 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == capability, 1596 ("start capability is not expected capability")); 1597 1598 ptr = pci_read_config(child, start + PCICAP_NEXTPTR, 1); 1599 while (ptr != 0) { 1600 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1601 if (capreg != NULL) 1602 *capreg = ptr; 1603 return (0); 1604 } 1605 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1606 } 1607 1608 return (ENOENT); 1609 } 1610 1611 /* 1612 * Find the requested extended capability and return the offset in 1613 * configuration space via the pointer provided. The function returns 1614 * 0 on success and an error code otherwise. 1615 */ 1616 int 1617 pci_find_extcap_method(device_t dev, device_t child, int capability, 1618 int *capreg) 1619 { 1620 struct pci_devinfo *dinfo = device_get_ivars(child); 1621 pcicfgregs *cfg = &dinfo->cfg; 1622 uint32_t ecap; 1623 uint16_t ptr; 1624 1625 /* Only supported for PCI-express devices. */ 1626 if (cfg->pcie.pcie_location == 0) 1627 return (ENXIO); 1628 1629 ptr = PCIR_EXTCAP; 1630 ecap = pci_read_config(child, ptr, 4); 1631 if (ecap == 0xffffffff || ecap == 0) 1632 return (ENOENT); 1633 for (;;) { 1634 if (PCI_EXTCAP_ID(ecap) == capability) { 1635 if (capreg != NULL) 1636 *capreg = ptr; 1637 return (0); 1638 } 1639 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1640 if (ptr == 0) 1641 break; 1642 ecap = pci_read_config(child, ptr, 4); 1643 } 1644 1645 return (ENOENT); 1646 } 1647 1648 /* 1649 * Find the next requested extended capability after start and return the 1650 * offset in configuration space via the pointer provided. The function 1651 * returns 0 on success and an error code otherwise. 1652 */ 1653 int 1654 pci_find_next_extcap_method(device_t dev, device_t child, int capability, 1655 int start, int *capreg) 1656 { 1657 struct pci_devinfo *dinfo = device_get_ivars(child); 1658 pcicfgregs *cfg = &dinfo->cfg; 1659 uint32_t ecap; 1660 uint16_t ptr; 1661 1662 /* Only supported for PCI-express devices. */ 1663 if (cfg->pcie.pcie_location == 0) 1664 return (ENXIO); 1665 1666 ecap = pci_read_config(child, start, 4); 1667 KASSERT(PCI_EXTCAP_ID(ecap) == capability, 1668 ("start extended capability is not expected capability")); 1669 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1670 while (ptr != 0) { 1671 ecap = pci_read_config(child, ptr, 4); 1672 if (PCI_EXTCAP_ID(ecap) == capability) { 1673 if (capreg != NULL) 1674 *capreg = ptr; 1675 return (0); 1676 } 1677 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1678 } 1679 1680 return (ENOENT); 1681 } 1682 1683 /* 1684 * Support for MSI-X message interrupts. 1685 */ 1686 static void 1687 pci_write_msix_entry(device_t dev, u_int index, uint64_t address, uint32_t data) 1688 { 1689 struct pci_devinfo *dinfo = device_get_ivars(dev); 1690 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1691 uint32_t offset; 1692 1693 KASSERT(msix->msix_table_len > index, ("bogus index")); 1694 offset = msix->msix_table_offset + index * 16; 1695 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); 1696 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); 1697 bus_write_4(msix->msix_table_res, offset + 8, data); 1698 } 1699 1700 void 1701 pci_enable_msix_method(device_t dev, device_t child, u_int index, 1702 uint64_t address, uint32_t data) 1703 { 1704 1705 if (pci_msix_rewrite_table) { 1706 struct pci_devinfo *dinfo = device_get_ivars(child); 1707 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1708 1709 /* 1710 * Some VM hosts require MSIX to be disabled in the 1711 * control register before updating the MSIX table 1712 * entries are allowed. It is not enough to only 1713 * disable MSIX while updating a single entry. MSIX 1714 * must be disabled while updating all entries in the 1715 * table. 1716 */ 1717 pci_write_config(child, 1718 msix->msix_location + PCIR_MSIX_CTRL, 1719 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2); 1720 pci_resume_msix(child); 1721 } else 1722 pci_write_msix_entry(child, index, address, data); 1723 1724 /* Enable MSI -> HT mapping. */ 1725 pci_ht_map_msi(child, address); 1726 } 1727 1728 void 1729 pci_mask_msix(device_t dev, u_int index) 1730 { 1731 struct pci_devinfo *dinfo = device_get_ivars(dev); 1732 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1733 uint32_t offset, val; 1734 1735 KASSERT(PCI_MSIX_MSGNUM(msix->msix_ctrl) > index, ("bogus index")); 1736 offset = msix->msix_table_offset + index * 16 + 12; 1737 val = bus_read_4(msix->msix_table_res, offset); 1738 val |= PCIM_MSIX_VCTRL_MASK; 1739 1740 /* 1741 * Some devices (e.g. Samsung PM961) do not support reads of this 1742 * register, so always write the new value. 1743 */ 1744 bus_write_4(msix->msix_table_res, offset, val); 1745 } 1746 1747 void 1748 pci_unmask_msix(device_t dev, u_int index) 1749 { 1750 struct pci_devinfo *dinfo = device_get_ivars(dev); 1751 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1752 uint32_t offset, val; 1753 1754 KASSERT(PCI_MSIX_MSGNUM(msix->msix_ctrl) > index, ("bogus index")); 1755 offset = msix->msix_table_offset + index * 16 + 12; 1756 val = bus_read_4(msix->msix_table_res, offset); 1757 val &= ~PCIM_MSIX_VCTRL_MASK; 1758 1759 /* 1760 * Some devices (e.g. Samsung PM961) do not support reads of this 1761 * register, so always write the new value. 1762 */ 1763 bus_write_4(msix->msix_table_res, offset, val); 1764 } 1765 1766 int 1767 pci_pending_msix(device_t dev, u_int index) 1768 { 1769 struct pci_devinfo *dinfo = device_get_ivars(dev); 1770 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1771 uint32_t offset, bit; 1772 1773 KASSERT(msix->msix_table_len > index, ("bogus index")); 1774 offset = msix->msix_pba_offset + (index / 32) * 4; 1775 bit = 1 << index % 32; 1776 return (bus_read_4(msix->msix_pba_res, offset) & bit); 1777 } 1778 1779 /* 1780 * Restore MSI-X registers and table during resume. If MSI-X is 1781 * enabled then walk the virtual table to restore the actual MSI-X 1782 * table. 1783 */ 1784 static void 1785 pci_resume_msix(device_t dev) 1786 { 1787 struct pci_devinfo *dinfo = device_get_ivars(dev); 1788 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1789 struct msix_table_entry *mte; 1790 struct msix_vector *mv; 1791 u_int i, msgnum; 1792 1793 if (msix->msix_alloc > 0) { 1794 msgnum = PCI_MSIX_MSGNUM(msix->msix_ctrl); 1795 1796 /* First, mask all vectors. */ 1797 for (i = 0; i < msgnum; i++) 1798 pci_mask_msix(dev, i); 1799 1800 /* Second, program any messages with at least one handler. */ 1801 for (i = 0; i < msix->msix_table_len; i++) { 1802 mte = &msix->msix_table[i]; 1803 if (mte->mte_vector == 0 || mte->mte_handlers == 0) 1804 continue; 1805 mv = &msix->msix_vectors[mte->mte_vector - 1]; 1806 pci_write_msix_entry(dev, i, mv->mv_address, 1807 mv->mv_data); 1808 pci_unmask_msix(dev, i); 1809 } 1810 } 1811 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, 1812 msix->msix_ctrl, 2); 1813 } 1814 1815 /* 1816 * Attempt to allocate *count MSI-X messages. The actual number allocated is 1817 * returned in *count. After this function returns, each message will be 1818 * available to the driver as SYS_RES_IRQ resources starting at rid 1. 1819 */ 1820 int 1821 pci_alloc_msix_method(device_t dev, device_t child, int *count) 1822 { 1823 struct pci_devinfo *dinfo = device_get_ivars(child); 1824 pcicfgregs *cfg = &dinfo->cfg; 1825 struct resource_list_entry *rle; 1826 u_int actual, i, max; 1827 int error, irq; 1828 uint16_t ctrl, msgnum; 1829 1830 /* Don't let count == 0 get us into trouble. */ 1831 if (*count < 1) 1832 return (EINVAL); 1833 1834 /* If rid 0 is allocated, then fail. */ 1835 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1836 if (rle != NULL && rle->res != NULL) 1837 return (ENXIO); 1838 1839 /* Already have allocated messages? */ 1840 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1841 return (ENXIO); 1842 1843 /* If MSI-X is blacklisted for this system, fail. */ 1844 if (pci_msix_blacklisted()) 1845 return (ENXIO); 1846 1847 /* MSI-X capability present? */ 1848 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1849 return (ENODEV); 1850 1851 /* Make sure the appropriate BARs are mapped. */ 1852 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1853 cfg->msix.msix_table_bar); 1854 if (rle == NULL || rle->res == NULL || 1855 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1856 return (ENXIO); 1857 cfg->msix.msix_table_res = rle->res; 1858 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1859 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1860 cfg->msix.msix_pba_bar); 1861 if (rle == NULL || rle->res == NULL || 1862 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1863 return (ENXIO); 1864 } 1865 cfg->msix.msix_pba_res = rle->res; 1866 1867 ctrl = pci_read_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1868 2); 1869 msgnum = PCI_MSIX_MSGNUM(ctrl); 1870 if (bootverbose) 1871 device_printf(child, 1872 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1873 *count, msgnum); 1874 max = min(*count, msgnum); 1875 for (i = 0; i < max; i++) { 1876 /* Allocate a message. */ 1877 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq); 1878 if (error) { 1879 if (i == 0) 1880 return (error); 1881 break; 1882 } 1883 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1884 irq, 1); 1885 } 1886 actual = i; 1887 1888 if (bootverbose) { 1889 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1890 if (actual == 1) 1891 device_printf(child, "using IRQ %ju for MSI-X\n", 1892 rle->start); 1893 else { 1894 bool run; 1895 1896 /* 1897 * Be fancy and try to print contiguous runs of 1898 * IRQ values as ranges. 'irq' is the previous IRQ. 1899 * 'run' is true if we are in a range. 1900 */ 1901 device_printf(child, "using IRQs %ju", rle->start); 1902 irq = rle->start; 1903 run = false; 1904 for (i = 1; i < actual; i++) { 1905 rle = resource_list_find(&dinfo->resources, 1906 SYS_RES_IRQ, i + 1); 1907 1908 /* Still in a run? */ 1909 if (rle->start == irq + 1) { 1910 run = true; 1911 irq++; 1912 continue; 1913 } 1914 1915 /* Finish previous range. */ 1916 if (run) { 1917 printf("-%d", irq); 1918 run = false; 1919 } 1920 1921 /* Start new range. */ 1922 printf(",%ju", rle->start); 1923 irq = rle->start; 1924 } 1925 1926 /* Unfinished range? */ 1927 if (run) 1928 printf("-%d", irq); 1929 printf(" for MSI-X\n"); 1930 } 1931 } 1932 1933 /* 1934 * Mask all vectors. Note that the message index assertion in 1935 * pci_mask_msix requires msix_ctrl to be set. 1936 */ 1937 cfg->msix.msix_ctrl = ctrl; 1938 for (i = 0; i < msgnum; i++) 1939 pci_mask_msix(child, i); 1940 1941 /* Allocate and initialize vector data and virtual table. */ 1942 cfg->msix.msix_vectors = mallocarray(actual, sizeof(struct msix_vector), 1943 M_DEVBUF, M_WAITOK | M_ZERO); 1944 cfg->msix.msix_table = mallocarray(actual, 1945 sizeof(struct msix_table_entry), M_DEVBUF, M_WAITOK | M_ZERO); 1946 for (i = 0; i < actual; i++) { 1947 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1948 cfg->msix.msix_vectors[i].mv_irq = rle->start; 1949 cfg->msix.msix_table[i].mte_vector = i + 1; 1950 } 1951 1952 /* Update control register to enable MSI-X. */ 1953 ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1954 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1955 ctrl, 2); 1956 cfg->msix.msix_ctrl = ctrl; 1957 1958 /* Update counts of alloc'd messages. */ 1959 cfg->msix.msix_alloc = actual; 1960 cfg->msix.msix_table_len = actual; 1961 *count = actual; 1962 return (0); 1963 } 1964 1965 /* 1966 * By default, pci_alloc_msix() will assign the allocated IRQ 1967 * resources consecutively to the first N messages in the MSI-X table. 1968 * However, device drivers may want to use different layouts if they 1969 * either receive fewer messages than they asked for, or they wish to 1970 * populate the MSI-X table sparsely. This method allows the driver 1971 * to specify what layout it wants. It must be called after a 1972 * successful pci_alloc_msix() but before any of the associated 1973 * SYS_RES_IRQ resources are allocated via bus_alloc_resource(). 1974 * 1975 * The 'vectors' array contains 'count' message vectors. The array 1976 * maps directly to the MSI-X table in that index 0 in the array 1977 * specifies the vector for the first message in the MSI-X table, etc. 1978 * The vector value in each array index can either be 0 to indicate 1979 * that no vector should be assigned to a message slot, or it can be a 1980 * number from 1 to N (where N is the count returned from a 1981 * succcessful call to pci_alloc_msix()) to indicate which message 1982 * vector (IRQ) to be used for the corresponding message. 1983 * 1984 * On successful return, each message with a non-zero vector will have 1985 * an associated SYS_RES_IRQ whose rid is equal to the array index + 1986 * 1. Additionally, if any of the IRQs allocated via the previous 1987 * call to pci_alloc_msix() are not used in the mapping, those IRQs 1988 * will be freed back to the system automatically. 1989 * 1990 * For example, suppose a driver has a MSI-X table with 6 messages and 1991 * asks for 6 messages, but pci_alloc_msix() only returns a count of 1992 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and 1993 * C. After the call to pci_alloc_msix(), the device will be setup to 1994 * have an MSI-X table of ABC--- (where - means no vector assigned). 1995 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 }, 1996 * then the MSI-X table will look like A-AB-B, and the 'C' vector will 1997 * be freed back to the system. This device will also have valid 1998 * SYS_RES_IRQ rids of 1, 3, 4, and 6. 1999 * 2000 * In any case, the SYS_RES_IRQ rid X will always map to the message 2001 * at MSI-X table index X - 1 and will only be valid if a vector is 2002 * assigned to that table entry. 2003 */ 2004 int 2005 pci_remap_msix_method(device_t dev, device_t child, int count, 2006 const u_int *vectors) 2007 { 2008 struct pci_devinfo *dinfo = device_get_ivars(child); 2009 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2010 struct resource_list_entry *rle; 2011 u_int i, irq, j; 2012 bool *used; 2013 2014 /* 2015 * Have to have at least one message in the table but the 2016 * table can't be bigger than the actual MSI-X table in the 2017 * device. 2018 */ 2019 if (count < 1 || count > PCI_MSIX_MSGNUM(msix->msix_ctrl)) 2020 return (EINVAL); 2021 2022 /* Sanity check the vectors. */ 2023 for (i = 0; i < count; i++) 2024 if (vectors[i] > msix->msix_alloc) 2025 return (EINVAL); 2026 2027 /* 2028 * Make sure there aren't any holes in the vectors to be used. 2029 * It's a big pain to support it, and it doesn't really make 2030 * sense anyway. Also, at least one vector must be used. 2031 */ 2032 used = mallocarray(msix->msix_alloc, sizeof(*used), M_DEVBUF, M_WAITOK | 2033 M_ZERO); 2034 for (i = 0; i < count; i++) 2035 if (vectors[i] != 0) 2036 used[vectors[i] - 1] = true; 2037 for (i = 0; i < msix->msix_alloc - 1; i++) 2038 if (!used[i] && used[i + 1]) { 2039 free(used, M_DEVBUF); 2040 return (EINVAL); 2041 } 2042 if (!used[0]) { 2043 free(used, M_DEVBUF); 2044 return (EINVAL); 2045 } 2046 2047 /* Make sure none of the resources are allocated. */ 2048 for (i = 0; i < msix->msix_table_len; i++) { 2049 if (msix->msix_table[i].mte_vector == 0) 2050 continue; 2051 if (msix->msix_table[i].mte_handlers > 0) { 2052 free(used, M_DEVBUF); 2053 return (EBUSY); 2054 } 2055 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2056 KASSERT(rle != NULL, ("missing resource")); 2057 if (rle->res != NULL) { 2058 free(used, M_DEVBUF); 2059 return (EBUSY); 2060 } 2061 } 2062 2063 /* Free the existing resource list entries. */ 2064 for (i = 0; i < msix->msix_table_len; i++) { 2065 if (msix->msix_table[i].mte_vector == 0) 2066 continue; 2067 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2068 } 2069 2070 /* 2071 * Build the new virtual table keeping track of which vectors are 2072 * used. 2073 */ 2074 free(msix->msix_table, M_DEVBUF); 2075 msix->msix_table = mallocarray(count, sizeof(struct msix_table_entry), 2076 M_DEVBUF, M_WAITOK | M_ZERO); 2077 for (i = 0; i < count; i++) 2078 msix->msix_table[i].mte_vector = vectors[i]; 2079 msix->msix_table_len = count; 2080 2081 /* Free any unused IRQs and resize the vectors array if necessary. */ 2082 j = msix->msix_alloc - 1; 2083 if (!used[j]) { 2084 struct msix_vector *vec; 2085 2086 while (!used[j]) { 2087 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2088 msix->msix_vectors[j].mv_irq); 2089 j--; 2090 } 2091 vec = mallocarray(j + 1, sizeof(struct msix_vector), M_DEVBUF, 2092 M_WAITOK); 2093 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * 2094 (j + 1)); 2095 free(msix->msix_vectors, M_DEVBUF); 2096 msix->msix_vectors = vec; 2097 msix->msix_alloc = j + 1; 2098 } 2099 free(used, M_DEVBUF); 2100 2101 /* Map the IRQs onto the rids. */ 2102 for (i = 0; i < count; i++) { 2103 if (vectors[i] == 0) 2104 continue; 2105 irq = msix->msix_vectors[vectors[i] - 1].mv_irq; 2106 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 2107 irq, 1); 2108 } 2109 2110 if (bootverbose) { 2111 device_printf(child, "Remapped MSI-X IRQs as: "); 2112 for (i = 0; i < count; i++) { 2113 if (i != 0) 2114 printf(", "); 2115 if (vectors[i] == 0) 2116 printf("---"); 2117 else 2118 printf("%d", 2119 msix->msix_vectors[vectors[i] - 1].mv_irq); 2120 } 2121 printf("\n"); 2122 } 2123 2124 return (0); 2125 } 2126 2127 static int 2128 pci_release_msix(device_t dev, device_t child) 2129 { 2130 struct pci_devinfo *dinfo = device_get_ivars(child); 2131 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2132 struct resource_list_entry *rle; 2133 u_int i; 2134 2135 /* Do we have any messages to release? */ 2136 if (msix->msix_alloc == 0) 2137 return (ENODEV); 2138 2139 /* Make sure none of the resources are allocated. */ 2140 for (i = 0; i < msix->msix_table_len; i++) { 2141 if (msix->msix_table[i].mte_vector == 0) 2142 continue; 2143 if (msix->msix_table[i].mte_handlers > 0) 2144 return (EBUSY); 2145 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2146 KASSERT(rle != NULL, ("missing resource")); 2147 if (rle->res != NULL) 2148 return (EBUSY); 2149 } 2150 2151 /* Update control register to disable MSI-X. */ 2152 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 2153 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, 2154 msix->msix_ctrl, 2); 2155 2156 /* Free the resource list entries. */ 2157 for (i = 0; i < msix->msix_table_len; i++) { 2158 if (msix->msix_table[i].mte_vector == 0) 2159 continue; 2160 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2161 } 2162 free(msix->msix_table, M_DEVBUF); 2163 msix->msix_table_len = 0; 2164 2165 /* Release the IRQs. */ 2166 for (i = 0; i < msix->msix_alloc; i++) 2167 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2168 msix->msix_vectors[i].mv_irq); 2169 free(msix->msix_vectors, M_DEVBUF); 2170 msix->msix_alloc = 0; 2171 return (0); 2172 } 2173 2174 /* 2175 * Return the max supported MSI-X messages this device supports. 2176 * Basically, assuming the MD code can alloc messages, this function 2177 * should return the maximum value that pci_alloc_msix() can return. 2178 * Thus, it is subject to the tunables, etc. 2179 */ 2180 int 2181 pci_msix_count_method(device_t dev, device_t child) 2182 { 2183 struct pci_devinfo *dinfo = device_get_ivars(child); 2184 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2185 uint16_t ctrl; 2186 2187 if (pci_do_msix && msix->msix_location != 0) { 2188 ctrl = pci_read_config(child, msix->msix_location + 2189 PCIR_MSI_CTRL, 2); 2190 return (PCI_MSIX_MSGNUM(ctrl)); 2191 } 2192 return (0); 2193 } 2194 2195 int 2196 pci_msix_pba_bar_method(device_t dev, device_t child) 2197 { 2198 struct pci_devinfo *dinfo = device_get_ivars(child); 2199 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2200 2201 if (pci_do_msix && msix->msix_location != 0) 2202 return (msix->msix_pba_bar); 2203 return (-1); 2204 } 2205 2206 int 2207 pci_msix_table_bar_method(device_t dev, device_t child) 2208 { 2209 struct pci_devinfo *dinfo = device_get_ivars(child); 2210 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2211 2212 if (pci_do_msix && msix->msix_location != 0) 2213 return (msix->msix_table_bar); 2214 return (-1); 2215 } 2216 2217 /* 2218 * HyperTransport MSI mapping control 2219 */ 2220 void 2221 pci_ht_map_msi(device_t dev, uint64_t addr) 2222 { 2223 struct pci_devinfo *dinfo = device_get_ivars(dev); 2224 struct pcicfg_ht *ht = &dinfo->cfg.ht; 2225 2226 if (!ht->ht_msimap) 2227 return; 2228 2229 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && 2230 ht->ht_msiaddr >> 20 == addr >> 20) { 2231 /* Enable MSI -> HT mapping. */ 2232 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 2233 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2234 ht->ht_msictrl, 2); 2235 } 2236 2237 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { 2238 /* Disable MSI -> HT mapping. */ 2239 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; 2240 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2241 ht->ht_msictrl, 2); 2242 } 2243 } 2244 2245 int 2246 pci_get_relaxed_ordering_enabled(device_t dev) 2247 { 2248 struct pci_devinfo *dinfo = device_get_ivars(dev); 2249 int cap; 2250 uint16_t val; 2251 2252 cap = dinfo->cfg.pcie.pcie_location; 2253 if (cap == 0) 2254 return (0); 2255 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2256 val &= PCIEM_CTL_RELAXED_ORD_ENABLE; 2257 return (val != 0); 2258 } 2259 2260 int 2261 pci_get_max_payload(device_t dev) 2262 { 2263 struct pci_devinfo *dinfo = device_get_ivars(dev); 2264 int cap; 2265 uint16_t val; 2266 2267 cap = dinfo->cfg.pcie.pcie_location; 2268 if (cap == 0) 2269 return (0); 2270 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2271 val &= PCIEM_CTL_MAX_PAYLOAD; 2272 val >>= 5; 2273 return (1 << (val + 7)); 2274 } 2275 2276 int 2277 pci_get_max_read_req(device_t dev) 2278 { 2279 struct pci_devinfo *dinfo = device_get_ivars(dev); 2280 int cap; 2281 uint16_t val; 2282 2283 cap = dinfo->cfg.pcie.pcie_location; 2284 if (cap == 0) 2285 return (0); 2286 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2287 val &= PCIEM_CTL_MAX_READ_REQUEST; 2288 val >>= 12; 2289 return (1 << (val + 7)); 2290 } 2291 2292 int 2293 pci_set_max_read_req(device_t dev, int size) 2294 { 2295 struct pci_devinfo *dinfo = device_get_ivars(dev); 2296 int cap; 2297 uint16_t val; 2298 2299 cap = dinfo->cfg.pcie.pcie_location; 2300 if (cap == 0) 2301 return (0); 2302 if (size < 128) 2303 size = 128; 2304 if (size > 4096) 2305 size = 4096; 2306 size = (1 << (fls(size) - 1)); 2307 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2308 val &= ~PCIEM_CTL_MAX_READ_REQUEST; 2309 val |= (fls(size) - 8) << 12; 2310 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2); 2311 return (size); 2312 } 2313 2314 uint32_t 2315 pcie_read_config(device_t dev, int reg, int width) 2316 { 2317 struct pci_devinfo *dinfo = device_get_ivars(dev); 2318 int cap; 2319 2320 cap = dinfo->cfg.pcie.pcie_location; 2321 if (cap == 0) { 2322 if (width == 2) 2323 return (0xffff); 2324 return (0xffffffff); 2325 } 2326 2327 return (pci_read_config(dev, cap + reg, width)); 2328 } 2329 2330 void 2331 pcie_write_config(device_t dev, int reg, uint32_t value, int width) 2332 { 2333 struct pci_devinfo *dinfo = device_get_ivars(dev); 2334 int cap; 2335 2336 cap = dinfo->cfg.pcie.pcie_location; 2337 if (cap == 0) 2338 return; 2339 pci_write_config(dev, cap + reg, value, width); 2340 } 2341 2342 /* 2343 * Adjusts a PCI-e capability register by clearing the bits in mask 2344 * and setting the bits in (value & mask). Bits not set in mask are 2345 * not adjusted. 2346 * 2347 * Returns the old value on success or all ones on failure. 2348 */ 2349 uint32_t 2350 pcie_adjust_config(device_t dev, int reg, uint32_t mask, uint32_t value, 2351 int width) 2352 { 2353 struct pci_devinfo *dinfo = device_get_ivars(dev); 2354 uint32_t old, new; 2355 int cap; 2356 2357 cap = dinfo->cfg.pcie.pcie_location; 2358 if (cap == 0) { 2359 if (width == 2) 2360 return (0xffff); 2361 return (0xffffffff); 2362 } 2363 2364 old = pci_read_config(dev, cap + reg, width); 2365 new = old & ~mask; 2366 new |= (value & mask); 2367 pci_write_config(dev, cap + reg, new, width); 2368 return (old); 2369 } 2370 2371 /* 2372 * Support for MSI message signalled interrupts. 2373 */ 2374 void 2375 pci_enable_msi_method(device_t dev, device_t child, uint64_t address, 2376 uint16_t data) 2377 { 2378 struct pci_devinfo *dinfo = device_get_ivars(child); 2379 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2380 2381 /* Write data and address values. */ 2382 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, 2383 address & 0xffffffff, 4); 2384 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2385 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, 2386 address >> 32, 4); 2387 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, 2388 data, 2); 2389 } else 2390 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, 2391 2); 2392 2393 /* Enable MSI in the control register. */ 2394 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 2395 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2396 msi->msi_ctrl, 2); 2397 2398 /* Enable MSI -> HT mapping. */ 2399 pci_ht_map_msi(child, address); 2400 } 2401 2402 void 2403 pci_disable_msi_method(device_t dev, device_t child) 2404 { 2405 struct pci_devinfo *dinfo = device_get_ivars(child); 2406 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2407 2408 /* Disable MSI -> HT mapping. */ 2409 pci_ht_map_msi(child, 0); 2410 2411 /* Disable MSI in the control register. */ 2412 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; 2413 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2414 msi->msi_ctrl, 2); 2415 } 2416 2417 /* 2418 * Restore MSI registers during resume. If MSI is enabled then 2419 * restore the data and address registers in addition to the control 2420 * register. 2421 */ 2422 static void 2423 pci_resume_msi(device_t dev) 2424 { 2425 struct pci_devinfo *dinfo = device_get_ivars(dev); 2426 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2427 uint64_t address; 2428 uint16_t data; 2429 2430 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 2431 address = msi->msi_addr; 2432 data = msi->msi_data; 2433 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 2434 address & 0xffffffff, 4); 2435 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2436 pci_write_config(dev, msi->msi_location + 2437 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 2438 pci_write_config(dev, msi->msi_location + 2439 PCIR_MSI_DATA_64BIT, data, 2); 2440 } else 2441 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, 2442 data, 2); 2443 } 2444 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 2445 2); 2446 } 2447 2448 static int 2449 pci_remap_intr_method(device_t bus, device_t dev, u_int irq) 2450 { 2451 struct pci_devinfo *dinfo = device_get_ivars(dev); 2452 pcicfgregs *cfg = &dinfo->cfg; 2453 struct resource_list_entry *rle; 2454 struct msix_table_entry *mte; 2455 struct msix_vector *mv; 2456 uint64_t addr; 2457 uint32_t data; 2458 u_int i, j; 2459 int error; 2460 2461 /* 2462 * Handle MSI first. We try to find this IRQ among our list 2463 * of MSI IRQs. If we find it, we request updated address and 2464 * data registers and apply the results. 2465 */ 2466 if (cfg->msi.msi_alloc > 0) { 2467 /* If we don't have any active handlers, nothing to do. */ 2468 if (cfg->msi.msi_handlers == 0) 2469 return (0); 2470 for (i = 0; i < cfg->msi.msi_alloc; i++) { 2471 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 2472 i + 1); 2473 if (rle->start == irq) { 2474 error = PCIB_MAP_MSI(device_get_parent(bus), 2475 dev, irq, &addr, &data); 2476 if (error) 2477 return (error); 2478 pci_disable_msi(dev); 2479 dinfo->cfg.msi.msi_addr = addr; 2480 dinfo->cfg.msi.msi_data = data; 2481 pci_enable_msi(dev, addr, data); 2482 return (0); 2483 } 2484 } 2485 return (ENOENT); 2486 } 2487 2488 /* 2489 * For MSI-X, we check to see if we have this IRQ. If we do, 2490 * we request the updated mapping info. If that works, we go 2491 * through all the slots that use this IRQ and update them. 2492 */ 2493 if (cfg->msix.msix_alloc > 0) { 2494 bool found = false; 2495 2496 for (i = 0; i < cfg->msix.msix_alloc; i++) { 2497 mv = &cfg->msix.msix_vectors[i]; 2498 if (mv->mv_irq == irq) { 2499 error = PCIB_MAP_MSI(device_get_parent(bus), 2500 dev, irq, &addr, &data); 2501 if (error) 2502 return (error); 2503 mv->mv_address = addr; 2504 mv->mv_data = data; 2505 for (j = 0; j < cfg->msix.msix_table_len; j++) { 2506 mte = &cfg->msix.msix_table[j]; 2507 if (mte->mte_vector != i + 1) 2508 continue; 2509 if (mte->mte_handlers == 0) 2510 continue; 2511 pci_mask_msix(dev, j); 2512 pci_enable_msix(dev, j, addr, data); 2513 pci_unmask_msix(dev, j); 2514 } 2515 found = true; 2516 } 2517 } 2518 return (found ? 0 : ENOENT); 2519 } 2520 2521 return (ENOENT); 2522 } 2523 2524 /* 2525 * Returns true if the specified device is blacklisted because MSI 2526 * doesn't work. 2527 */ 2528 int 2529 pci_msi_device_blacklisted(device_t dev) 2530 { 2531 2532 if (!pci_honor_msi_blacklist) 2533 return (0); 2534 2535 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI)); 2536 } 2537 2538 /* 2539 * Determine if MSI is blacklisted globally on this system. Currently, 2540 * we just check for blacklisted chipsets as represented by the 2541 * host-PCI bridge at device 0:0:0. In the future, it may become 2542 * necessary to check other system attributes, such as the kenv values 2543 * that give the motherboard manufacturer and model number. 2544 */ 2545 static int 2546 pci_msi_blacklisted(void) 2547 { 2548 device_t dev; 2549 2550 if (!pci_honor_msi_blacklist) 2551 return (0); 2552 2553 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ 2554 if (!(pcie_chipset || pcix_chipset)) { 2555 if (vm_guest != VM_GUEST_NO) { 2556 /* 2557 * Whitelist older chipsets in virtual 2558 * machines known to support MSI. 2559 */ 2560 dev = pci_find_bsf(0, 0, 0); 2561 if (dev != NULL) 2562 return (!pci_has_quirk(pci_get_devid(dev), 2563 PCI_QUIRK_ENABLE_MSI_VM)); 2564 } 2565 return (1); 2566 } 2567 2568 dev = pci_find_bsf(0, 0, 0); 2569 if (dev != NULL) 2570 return (pci_msi_device_blacklisted(dev)); 2571 return (0); 2572 } 2573 2574 /* 2575 * Returns true if the specified device is blacklisted because MSI-X 2576 * doesn't work. Note that this assumes that if MSI doesn't work, 2577 * MSI-X doesn't either. 2578 */ 2579 int 2580 pci_msix_device_blacklisted(device_t dev) 2581 { 2582 2583 if (!pci_honor_msi_blacklist) 2584 return (0); 2585 2586 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX)) 2587 return (1); 2588 2589 return (pci_msi_device_blacklisted(dev)); 2590 } 2591 2592 /* 2593 * Determine if MSI-X is blacklisted globally on this system. If MSI 2594 * is blacklisted, assume that MSI-X is as well. Check for additional 2595 * chipsets where MSI works but MSI-X does not. 2596 */ 2597 static int 2598 pci_msix_blacklisted(void) 2599 { 2600 device_t dev; 2601 2602 if (!pci_honor_msi_blacklist) 2603 return (0); 2604 2605 dev = pci_find_bsf(0, 0, 0); 2606 if (dev != NULL && pci_has_quirk(pci_get_devid(dev), 2607 PCI_QUIRK_DISABLE_MSIX)) 2608 return (1); 2609 2610 return (pci_msi_blacklisted()); 2611 } 2612 2613 /* 2614 * Attempt to allocate *count MSI messages. The actual number allocated is 2615 * returned in *count. After this function returns, each message will be 2616 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 2617 */ 2618 int 2619 pci_alloc_msi_method(device_t dev, device_t child, int *count) 2620 { 2621 struct pci_devinfo *dinfo = device_get_ivars(child); 2622 pcicfgregs *cfg = &dinfo->cfg; 2623 struct resource_list_entry *rle; 2624 u_int actual, i; 2625 int error, irqs[32]; 2626 uint16_t ctrl, msgnum; 2627 2628 /* Don't let count == 0 get us into trouble. */ 2629 if (*count < 1) 2630 return (EINVAL); 2631 2632 /* If rid 0 is allocated, then fail. */ 2633 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 2634 if (rle != NULL && rle->res != NULL) 2635 return (ENXIO); 2636 2637 /* Already have allocated messages? */ 2638 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 2639 return (ENXIO); 2640 2641 /* If MSI is blacklisted for this system, fail. */ 2642 if (pci_msi_blacklisted()) 2643 return (ENXIO); 2644 2645 /* MSI capability present? */ 2646 if (cfg->msi.msi_location == 0 || !pci_do_msi) 2647 return (ENODEV); 2648 2649 ctrl = pci_read_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, 2); 2650 msgnum = PCI_MSI_MSGNUM(ctrl); 2651 if (bootverbose) 2652 device_printf(child, 2653 "attempting to allocate %d MSI vectors (%u supported)\n", 2654 *count, msgnum); 2655 2656 /* Don't ask for more than the device supports. */ 2657 actual = min(*count, msgnum); 2658 2659 /* Don't ask for more than 32 messages. */ 2660 actual = min(actual, 32); 2661 2662 /* MSI requires power of 2 number of messages. */ 2663 if (!powerof2(actual)) 2664 return (EINVAL); 2665 2666 for (;;) { 2667 /* Try to allocate N messages. */ 2668 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 2669 actual, irqs); 2670 if (error == 0) 2671 break; 2672 if (actual == 1) 2673 return (error); 2674 2675 /* Try N / 2. */ 2676 actual >>= 1; 2677 } 2678 2679 /* 2680 * We now have N actual messages mapped onto SYS_RES_IRQ 2681 * resources in the irqs[] array, so add new resources 2682 * starting at rid 1. 2683 */ 2684 for (i = 0; i < actual; i++) 2685 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 2686 irqs[i], irqs[i], 1); 2687 2688 if (bootverbose) { 2689 if (actual == 1) 2690 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 2691 else { 2692 bool run; 2693 2694 /* 2695 * Be fancy and try to print contiguous runs 2696 * of IRQ values as ranges. 'run' is true if 2697 * we are in a range. 2698 */ 2699 device_printf(child, "using IRQs %d", irqs[0]); 2700 run = false; 2701 for (i = 1; i < actual; i++) { 2702 /* Still in a run? */ 2703 if (irqs[i] == irqs[i - 1] + 1) { 2704 run = true; 2705 continue; 2706 } 2707 2708 /* Finish previous range. */ 2709 if (run) { 2710 printf("-%d", irqs[i - 1]); 2711 run = false; 2712 } 2713 2714 /* Start new range. */ 2715 printf(",%d", irqs[i]); 2716 } 2717 2718 /* Unfinished range? */ 2719 if (run) 2720 printf("-%d", irqs[actual - 1]); 2721 printf(" for MSI\n"); 2722 } 2723 } 2724 2725 /* Update control register with actual count. */ 2726 ctrl &= ~PCIM_MSICTRL_MME_MASK; 2727 ctrl |= (ffs(actual) - 1) << 4; 2728 cfg->msi.msi_ctrl = ctrl; 2729 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 2730 2731 /* Update counts of alloc'd messages. */ 2732 cfg->msi.msi_alloc = actual; 2733 cfg->msi.msi_handlers = 0; 2734 *count = actual; 2735 return (0); 2736 } 2737 2738 /* Release the MSI messages associated with this device. */ 2739 int 2740 pci_release_msi_method(device_t dev, device_t child) 2741 { 2742 struct pci_devinfo *dinfo = device_get_ivars(child); 2743 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2744 struct resource_list_entry *rle; 2745 u_int i, irqs[32]; 2746 int error; 2747 2748 /* Try MSI-X first. */ 2749 error = pci_release_msix(dev, child); 2750 if (error != ENODEV) 2751 return (error); 2752 2753 /* Do we have any messages to release? */ 2754 if (msi->msi_alloc == 0) 2755 return (ENODEV); 2756 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); 2757 2758 /* Make sure none of the resources are allocated. */ 2759 if (msi->msi_handlers > 0) 2760 return (EBUSY); 2761 for (i = 0; i < msi->msi_alloc; i++) { 2762 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2763 KASSERT(rle != NULL, ("missing MSI resource")); 2764 if (rle->res != NULL) 2765 return (EBUSY); 2766 irqs[i] = rle->start; 2767 } 2768 2769 /* Update control register with 0 count. */ 2770 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), 2771 ("%s: MSI still enabled", __func__)); 2772 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; 2773 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2774 msi->msi_ctrl, 2); 2775 2776 /* Release the messages. */ 2777 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); 2778 for (i = 0; i < msi->msi_alloc; i++) 2779 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2780 2781 /* Update alloc count. */ 2782 msi->msi_alloc = 0; 2783 msi->msi_addr = 0; 2784 msi->msi_data = 0; 2785 return (0); 2786 } 2787 2788 /* 2789 * Return the max supported MSI messages this device supports. 2790 * Basically, assuming the MD code can alloc messages, this function 2791 * should return the maximum value that pci_alloc_msi() can return. 2792 * Thus, it is subject to the tunables, etc. 2793 */ 2794 int 2795 pci_msi_count_method(device_t dev, device_t child) 2796 { 2797 struct pci_devinfo *dinfo = device_get_ivars(child); 2798 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2799 uint16_t ctrl; 2800 2801 if (pci_do_msi && msi->msi_location != 0) { 2802 ctrl = pci_read_config(child, msi->msi_location + PCIR_MSI_CTRL, 2803 2); 2804 return (PCI_MSI_MSGNUM(ctrl)); 2805 } 2806 return (0); 2807 } 2808 2809 /* free pcicfgregs structure and all depending data structures */ 2810 2811 int 2812 pci_freecfg(struct pci_devinfo *dinfo) 2813 { 2814 struct devlist *devlist_head; 2815 struct pci_map *pm, *next; 2816 2817 devlist_head = &pci_devq; 2818 2819 if (dinfo->cfg.vpd.vpd_reg) 2820 vpd_free(&dinfo->cfg.vpd); 2821 2822 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { 2823 free(pm, M_DEVBUF); 2824 } 2825 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 2826 free(dinfo, M_DEVBUF); 2827 2828 /* increment the generation count */ 2829 pci_generation++; 2830 2831 /* we're losing one device */ 2832 pci_numdevs--; 2833 return (0); 2834 } 2835 2836 /* 2837 * PCI power manangement 2838 */ 2839 int 2840 pci_set_powerstate_method(device_t dev, device_t child, int state) 2841 { 2842 struct pci_devinfo *dinfo = device_get_ivars(child); 2843 pcicfgregs *cfg = &dinfo->cfg; 2844 uint16_t status; 2845 int oldstate, highest, delay; 2846 2847 if (cfg->pp.pp_location == 0) 2848 return (EOPNOTSUPP); 2849 2850 /* 2851 * Optimize a no state change request away. While it would be OK to 2852 * write to the hardware in theory, some devices have shown odd 2853 * behavior when going from D3 -> D3. 2854 */ 2855 oldstate = pci_get_powerstate(child); 2856 if (oldstate == state) 2857 return (0); 2858 2859 /* 2860 * The PCI power management specification states that after a state 2861 * transition between PCI power states, system software must 2862 * guarantee a minimal delay before the function accesses the device. 2863 * Compute the worst case delay that we need to guarantee before we 2864 * access the device. Many devices will be responsive much more 2865 * quickly than this delay, but there are some that don't respond 2866 * instantly to state changes. Transitions to/from D3 state require 2867 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 2868 * is done below with DELAY rather than a sleeper function because 2869 * this function can be called from contexts where we cannot sleep. 2870 */ 2871 highest = (oldstate > state) ? oldstate : state; 2872 if (highest == PCI_POWERSTATE_D3) 2873 delay = 10000; 2874 else if (highest == PCI_POWERSTATE_D2) 2875 delay = 200; 2876 else 2877 delay = 0; 2878 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_location + 2879 PCIR_POWER_STATUS, 2) & ~PCIM_PSTAT_DMASK; 2880 switch (state) { 2881 case PCI_POWERSTATE_D0: 2882 status |= PCIM_PSTAT_D0; 2883 break; 2884 case PCI_POWERSTATE_D1: 2885 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 2886 return (EOPNOTSUPP); 2887 status |= PCIM_PSTAT_D1; 2888 break; 2889 case PCI_POWERSTATE_D2: 2890 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 2891 return (EOPNOTSUPP); 2892 status |= PCIM_PSTAT_D2; 2893 break; 2894 case PCI_POWERSTATE_D3: 2895 status |= PCIM_PSTAT_D3; 2896 break; 2897 default: 2898 return (EINVAL); 2899 } 2900 2901 if (bootverbose) 2902 pci_printf(cfg, "Transition from %s to %s\n", 2903 acpi_d_state_to_str(oldstate), acpi_d_state_to_str(state)); 2904 2905 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_location + PCIR_POWER_STATUS, 2906 status, 2); 2907 if (delay) 2908 DELAY(delay); 2909 return (0); 2910 } 2911 2912 int 2913 pci_get_powerstate_method(device_t dev, device_t child) 2914 { 2915 struct pci_devinfo *dinfo = device_get_ivars(child); 2916 pcicfgregs *cfg = &dinfo->cfg; 2917 uint16_t status; 2918 int result; 2919 2920 if (cfg->pp.pp_location != 0) { 2921 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_location + 2922 PCIR_POWER_STATUS, 2); 2923 switch (status & PCIM_PSTAT_DMASK) { 2924 case PCIM_PSTAT_D0: 2925 result = PCI_POWERSTATE_D0; 2926 break; 2927 case PCIM_PSTAT_D1: 2928 result = PCI_POWERSTATE_D1; 2929 break; 2930 case PCIM_PSTAT_D2: 2931 result = PCI_POWERSTATE_D2; 2932 break; 2933 case PCIM_PSTAT_D3: 2934 result = PCI_POWERSTATE_D3; 2935 break; 2936 default: 2937 result = PCI_POWERSTATE_UNKNOWN; 2938 break; 2939 } 2940 } else { 2941 /* No support, device is always at D0 */ 2942 result = PCI_POWERSTATE_D0; 2943 } 2944 return (result); 2945 } 2946 2947 /* Clear any active PME# and disable PME# generation. */ 2948 void 2949 pci_clear_pme(device_t dev) 2950 { 2951 struct pci_devinfo *dinfo = device_get_ivars(dev); 2952 pcicfgregs *cfg = &dinfo->cfg; 2953 uint16_t status; 2954 2955 if (cfg->pp.pp_location != 0) { 2956 status = pci_read_config(dev, dinfo->cfg.pp.pp_location + 2957 PCIR_POWER_STATUS, 2); 2958 status &= ~PCIM_PSTAT_PMEENABLE; 2959 status |= PCIM_PSTAT_PME; 2960 pci_write_config(dev, dinfo->cfg.pp.pp_location + 2961 PCIR_POWER_STATUS, status, 2); 2962 } 2963 } 2964 2965 /* Clear any active PME# and enable PME# generation. */ 2966 void 2967 pci_enable_pme(device_t dev) 2968 { 2969 struct pci_devinfo *dinfo = device_get_ivars(dev); 2970 pcicfgregs *cfg = &dinfo->cfg; 2971 uint16_t status; 2972 2973 if (cfg->pp.pp_location != 0) { 2974 status = pci_read_config(dev, dinfo->cfg.pp.pp_location + 2975 PCIR_POWER_STATUS, 2); 2976 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2977 pci_write_config(dev, dinfo->cfg.pp.pp_location + 2978 PCIR_POWER_STATUS, status, 2); 2979 } 2980 } 2981 2982 bool 2983 pci_has_pm(device_t dev) 2984 { 2985 struct pci_devinfo *dinfo = device_get_ivars(dev); 2986 pcicfgregs *cfg = &dinfo->cfg; 2987 2988 return (cfg->pp.pp_location != 0); 2989 } 2990 2991 /* 2992 * Some convenience functions for PCI device drivers. 2993 */ 2994 2995 static __inline void 2996 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 2997 { 2998 uint16_t command; 2999 3000 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 3001 command |= bit; 3002 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 3003 } 3004 3005 static __inline void 3006 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 3007 { 3008 uint16_t command; 3009 3010 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 3011 command &= ~bit; 3012 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 3013 } 3014 3015 int 3016 pci_enable_busmaster_method(device_t dev, device_t child) 3017 { 3018 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 3019 return (0); 3020 } 3021 3022 int 3023 pci_disable_busmaster_method(device_t dev, device_t child) 3024 { 3025 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 3026 return (0); 3027 } 3028 3029 int 3030 pci_enable_io_method(device_t dev, device_t child, int space) 3031 { 3032 uint16_t bit; 3033 3034 switch(space) { 3035 case SYS_RES_IOPORT: 3036 bit = PCIM_CMD_PORTEN; 3037 break; 3038 case SYS_RES_MEMORY: 3039 bit = PCIM_CMD_MEMEN; 3040 break; 3041 default: 3042 return (EINVAL); 3043 } 3044 pci_set_command_bit(dev, child, bit); 3045 return (0); 3046 } 3047 3048 int 3049 pci_disable_io_method(device_t dev, device_t child, int space) 3050 { 3051 uint16_t bit; 3052 3053 switch(space) { 3054 case SYS_RES_IOPORT: 3055 bit = PCIM_CMD_PORTEN; 3056 break; 3057 case SYS_RES_MEMORY: 3058 bit = PCIM_CMD_MEMEN; 3059 break; 3060 default: 3061 return (EINVAL); 3062 } 3063 pci_clear_command_bit(dev, child, bit); 3064 return (0); 3065 } 3066 3067 /* 3068 * New style pci driver. Parent device is either a pci-host-bridge or a 3069 * pci-pci-bridge. Both kinds are represented by instances of pcib. 3070 */ 3071 3072 void 3073 pci_print_verbose(struct pci_devinfo *dinfo) 3074 { 3075 3076 if (bootverbose) { 3077 pcicfgregs *cfg = &dinfo->cfg; 3078 3079 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 3080 cfg->vendor, cfg->device, cfg->revid); 3081 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n", 3082 cfg->domain, cfg->bus, cfg->slot, cfg->func); 3083 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 3084 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 3085 cfg->mfdev); 3086 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 3087 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 3088 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 3089 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 3090 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 3091 if (cfg->intpin > 0) 3092 printf("\tintpin=%c, irq=%d\n", 3093 cfg->intpin +'a' -1, cfg->intline); 3094 if (cfg->pp.pp_location) { 3095 uint16_t status; 3096 3097 status = pci_read_config(cfg->dev, cfg->pp.pp_location + 3098 PCIR_POWER_STATUS, 2); 3099 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 3100 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 3101 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 3102 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 3103 status & PCIM_PSTAT_DMASK); 3104 } 3105 if (cfg->msi.msi_location) { 3106 uint16_t ctrl, msgnum; 3107 3108 ctrl = cfg->msi.msi_ctrl; 3109 msgnum = PCI_MSI_MSGNUM(ctrl); 3110 printf("\tMSI supports %d message%s%s%s\n", 3111 msgnum, (msgnum == 1) ? "" : "s", 3112 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 3113 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 3114 } 3115 if (cfg->msix.msix_location) { 3116 uint16_t msgnum; 3117 3118 msgnum = PCI_MSIX_MSGNUM(cfg->msix.msix_ctrl); 3119 printf("\tMSI-X supports %d message%s ", 3120 msgnum, (msgnum == 1) ? "" : "s"); 3121 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 3122 printf("in map 0x%x\n", 3123 cfg->msix.msix_table_bar); 3124 else 3125 printf("in maps 0x%x and 0x%x\n", 3126 cfg->msix.msix_table_bar, 3127 cfg->msix.msix_pba_bar); 3128 } 3129 } 3130 } 3131 3132 static int 3133 pci_porten(device_t dev) 3134 { 3135 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0; 3136 } 3137 3138 static int 3139 pci_memen(device_t dev) 3140 { 3141 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0; 3142 } 3143 3144 void 3145 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, 3146 int *bar64) 3147 { 3148 struct pci_devinfo *dinfo; 3149 pci_addr_t map, testval; 3150 int ln2range; 3151 uint16_t cmd; 3152 3153 /* 3154 * The device ROM BAR is special. It is always a 32-bit 3155 * memory BAR. Bit 0 is special and should not be set when 3156 * sizing the BAR. 3157 */ 3158 dinfo = device_get_ivars(dev); 3159 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { 3160 map = pci_read_config(dev, reg, 4); 3161 pci_write_config(dev, reg, 0xfffffffe, 4); 3162 testval = pci_read_config(dev, reg, 4); 3163 pci_write_config(dev, reg, map, 4); 3164 *mapp = map; 3165 *testvalp = testval; 3166 if (bar64 != NULL) 3167 *bar64 = 0; 3168 return; 3169 } 3170 3171 map = pci_read_config(dev, reg, 4); 3172 ln2range = pci_maprange(map); 3173 if (ln2range == 64) 3174 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3175 3176 /* 3177 * Disable decoding via the command register before 3178 * determining the BAR's length since we will be placing it in 3179 * a weird state. 3180 */ 3181 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3182 pci_write_config(dev, PCIR_COMMAND, 3183 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 3184 3185 /* 3186 * Determine the BAR's length by writing all 1's. The bottom 3187 * log_2(size) bits of the BAR will stick as 0 when we read 3188 * the value back. 3189 * 3190 * NB: according to the PCI Local Bus Specification, rev. 3.0: 3191 * "Software writes 0FFFFFFFFh to both registers, reads them back, 3192 * and combines the result into a 64-bit value." (section 6.2.5.1) 3193 * 3194 * Writes to both registers must be performed before attempting to 3195 * read back the size value. 3196 */ 3197 testval = 0; 3198 pci_write_config(dev, reg, 0xffffffff, 4); 3199 if (ln2range == 64) { 3200 pci_write_config(dev, reg + 4, 0xffffffff, 4); 3201 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3202 } 3203 testval |= pci_read_config(dev, reg, 4); 3204 3205 /* 3206 * Restore the original value of the BAR. We may have reprogrammed 3207 * the BAR of the low-level console device and when booting verbose, 3208 * we need the console device addressable. 3209 */ 3210 pci_write_config(dev, reg, map, 4); 3211 if (ln2range == 64) 3212 pci_write_config(dev, reg + 4, map >> 32, 4); 3213 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3214 3215 *mapp = map; 3216 *testvalp = testval; 3217 if (bar64 != NULL) 3218 *bar64 = (ln2range == 64); 3219 } 3220 3221 static void 3222 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base) 3223 { 3224 struct pci_devinfo *dinfo; 3225 int ln2range; 3226 3227 /* The device ROM BAR is always a 32-bit memory BAR. */ 3228 dinfo = device_get_ivars(dev); 3229 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3230 ln2range = 32; 3231 else 3232 ln2range = pci_maprange(pm->pm_value); 3233 pci_write_config(dev, pm->pm_reg, base, 4); 3234 if (ln2range == 64) 3235 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); 3236 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); 3237 if (ln2range == 64) 3238 pm->pm_value |= (pci_addr_t)pci_read_config(dev, 3239 pm->pm_reg + 4, 4) << 32; 3240 } 3241 3242 struct pci_map * 3243 pci_find_bar(device_t dev, int reg) 3244 { 3245 struct pci_devinfo *dinfo; 3246 struct pci_map *pm; 3247 3248 dinfo = device_get_ivars(dev); 3249 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3250 if (pm->pm_reg == reg) 3251 return (pm); 3252 } 3253 return (NULL); 3254 } 3255 3256 struct pci_map * 3257 pci_first_bar(device_t dev) 3258 { 3259 struct pci_devinfo *dinfo; 3260 3261 dinfo = device_get_ivars(dev); 3262 return (STAILQ_FIRST(&dinfo->cfg.maps)); 3263 } 3264 3265 struct pci_map * 3266 pci_next_bar(struct pci_map *pm) 3267 { 3268 return (STAILQ_NEXT(pm, pm_link)); 3269 } 3270 3271 int 3272 pci_bar_enabled(device_t dev, struct pci_map *pm) 3273 { 3274 struct pci_devinfo *dinfo; 3275 uint16_t cmd; 3276 3277 dinfo = device_get_ivars(dev); 3278 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && 3279 !(pm->pm_value & PCIM_BIOS_ENABLE)) 3280 return (0); 3281 #ifdef PCI_IOV 3282 if ((dinfo->cfg.flags & PCICFG_VF) != 0) { 3283 struct pcicfg_iov *iov; 3284 3285 iov = dinfo->cfg.iov; 3286 cmd = pci_read_config(iov->iov_pf, 3287 iov->iov_pos + PCIR_SRIOV_CTL, 2); 3288 return ((cmd & PCIM_SRIOV_VF_MSE) != 0); 3289 } 3290 #endif 3291 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3292 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) 3293 return ((cmd & PCIM_CMD_MEMEN) != 0); 3294 else 3295 return ((cmd & PCIM_CMD_PORTEN) != 0); 3296 } 3297 3298 struct pci_map * 3299 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size) 3300 { 3301 struct pci_devinfo *dinfo; 3302 struct pci_map *pm, *prev; 3303 3304 dinfo = device_get_ivars(dev); 3305 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO); 3306 pm->pm_reg = reg; 3307 pm->pm_value = value; 3308 pm->pm_size = size; 3309 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { 3310 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", 3311 reg)); 3312 if (STAILQ_NEXT(prev, pm_link) == NULL || 3313 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) 3314 break; 3315 } 3316 if (prev != NULL) 3317 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); 3318 else 3319 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); 3320 return (pm); 3321 } 3322 3323 static void 3324 pci_restore_bars(device_t dev) 3325 { 3326 struct pci_devinfo *dinfo; 3327 struct pci_map *pm; 3328 int ln2range; 3329 3330 dinfo = device_get_ivars(dev); 3331 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3332 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3333 ln2range = 32; 3334 else 3335 ln2range = pci_maprange(pm->pm_value); 3336 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); 3337 if (ln2range == 64) 3338 pci_write_config(dev, pm->pm_reg + 4, 3339 pm->pm_value >> 32, 4); 3340 } 3341 } 3342 3343 /* 3344 * Add a resource based on a pci map register. Return 1 if the map 3345 * register is a 32bit map register or 2 if it is a 64bit register. 3346 */ 3347 static int 3348 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, 3349 int force, int prefetch) 3350 { 3351 struct pci_map *pm; 3352 pci_addr_t base, map, testval; 3353 pci_addr_t start, end, count; 3354 int barlen, basezero, flags, maprange, mapsize, type; 3355 uint16_t cmd; 3356 struct resource *res; 3357 3358 /* 3359 * The BAR may already exist if the device is a CardBus card 3360 * whose CIS is stored in this BAR. 3361 */ 3362 pm = pci_find_bar(dev, reg); 3363 if (pm != NULL) { 3364 maprange = pci_maprange(pm->pm_value); 3365 barlen = maprange == 64 ? 2 : 1; 3366 return (barlen); 3367 } 3368 3369 pci_read_bar(dev, reg, &map, &testval, NULL); 3370 if (PCI_BAR_MEM(map)) { 3371 type = SYS_RES_MEMORY; 3372 if (map & PCIM_BAR_MEM_PREFETCH) 3373 prefetch = 1; 3374 } else 3375 type = SYS_RES_IOPORT; 3376 mapsize = pci_mapsize(testval); 3377 base = pci_mapbase(map); 3378 #ifdef __PCI_BAR_ZERO_VALID 3379 basezero = 0; 3380 #else 3381 basezero = base == 0; 3382 #endif 3383 maprange = pci_maprange(map); 3384 barlen = maprange == 64 ? 2 : 1; 3385 3386 /* 3387 * For I/O registers, if bottom bit is set, and the next bit up 3388 * isn't clear, we know we have a BAR that doesn't conform to the 3389 * spec, so ignore it. Also, sanity check the size of the data 3390 * areas to the type of memory involved. Memory must be at least 3391 * 16 bytes in size, while I/O ranges must be at least 4. 3392 */ 3393 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0) 3394 return (barlen); 3395 if ((type == SYS_RES_MEMORY && mapsize < 4) || 3396 (type == SYS_RES_IOPORT && mapsize < 2)) 3397 return (barlen); 3398 3399 /* Save a record of this BAR. */ 3400 pm = pci_add_bar(dev, reg, map, mapsize); 3401 if (bootverbose) { 3402 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d", 3403 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize); 3404 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3405 printf(", port disabled\n"); 3406 else if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3407 printf(", memory disabled\n"); 3408 else 3409 printf(", enabled\n"); 3410 } 3411 3412 /* 3413 * If base is 0, then we have problems if this architecture does 3414 * not allow that. It is best to ignore such entries for the 3415 * moment. These will be allocated later if the driver specifically 3416 * requests them. However, some removable buses look better when 3417 * all resources are allocated, so allow '0' to be overridden. 3418 * 3419 * Similarly treat maps whose values is the same as the test value 3420 * read back. These maps have had all f's written to them by the 3421 * BIOS in an attempt to disable the resources. 3422 */ 3423 if (!force && (basezero || map == testval)) 3424 return (barlen); 3425 if ((u_long)base != base) { 3426 device_printf(bus, 3427 "pci%d:%d:%d:%d bar %#x too many address bits", 3428 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev), 3429 pci_get_function(dev), reg); 3430 return (barlen); 3431 } 3432 3433 /* 3434 * This code theoretically does the right thing, but has 3435 * undesirable side effects in some cases where peripherals 3436 * respond oddly to having these bits enabled. Let the user 3437 * be able to turn them off (since pci_enable_io_modes is 1 by 3438 * default). 3439 */ 3440 if (pci_enable_io_modes) { 3441 /* Turn on resources that have been left off by a lazy BIOS */ 3442 if (type == SYS_RES_IOPORT && !pci_porten(dev)) { 3443 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3444 cmd |= PCIM_CMD_PORTEN; 3445 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3446 } 3447 if (type == SYS_RES_MEMORY && !pci_memen(dev)) { 3448 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3449 cmd |= PCIM_CMD_MEMEN; 3450 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3451 } 3452 } else { 3453 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3454 return (barlen); 3455 if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3456 return (barlen); 3457 } 3458 3459 count = (pci_addr_t)1 << mapsize; 3460 flags = RF_ALIGNMENT_LOG2(mapsize); 3461 if (prefetch) 3462 flags |= RF_PREFETCHABLE; 3463 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) { 3464 start = 0; /* Let the parent decide. */ 3465 end = ~0; 3466 } else { 3467 start = base; 3468 end = base + count - 1; 3469 } 3470 resource_list_add(rl, type, reg, start, end, count); 3471 3472 /* 3473 * Try to allocate the resource for this BAR from our parent 3474 * so that this resource range is already reserved. The 3475 * driver for this device will later inherit this resource in 3476 * pci_alloc_resource(). 3477 */ 3478 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count, 3479 flags); 3480 if ((pci_do_realloc_bars 3481 || pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_REALLOC_BAR)) 3482 && res == NULL && (start != 0 || end != ~0)) { 3483 /* 3484 * If the allocation fails, try to allocate a resource for 3485 * this BAR using any available range. The firmware felt 3486 * it was important enough to assign a resource, so don't 3487 * disable decoding if we can help it. 3488 */ 3489 resource_list_delete(rl, type, reg); 3490 resource_list_add(rl, type, reg, 0, ~0, count); 3491 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0, 3492 count, flags); 3493 } 3494 if (res == NULL) { 3495 /* 3496 * If the allocation fails, delete the resource list entry 3497 * and disable decoding for this device. 3498 * 3499 * If the driver requests this resource in the future, 3500 * pci_reserve_map() will try to allocate a fresh 3501 * resource range. 3502 */ 3503 resource_list_delete(rl, type, reg); 3504 pci_disable_io(dev, type); 3505 if (bootverbose) 3506 device_printf(bus, 3507 "pci%d:%d:%d:%d bar %#x failed to allocate\n", 3508 pci_get_domain(dev), pci_get_bus(dev), 3509 pci_get_slot(dev), pci_get_function(dev), reg); 3510 } else { 3511 start = rman_get_start(res); 3512 pci_write_bar(dev, pm, start); 3513 } 3514 return (barlen); 3515 } 3516 3517 /* 3518 * For ATA devices we need to decide early what addressing mode to use. 3519 * Legacy demands that the primary and secondary ATA ports sits on the 3520 * same addresses that old ISA hardware did. This dictates that we use 3521 * those addresses and ignore the BAR's if we cannot set PCI native 3522 * addressing mode. 3523 */ 3524 static void 3525 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, 3526 uint32_t prefetchmask) 3527 { 3528 int rid, type, progif; 3529 #if 0 3530 /* if this device supports PCI native addressing use it */ 3531 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3532 if ((progif & 0x8a) == 0x8a) { 3533 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 3534 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 3535 printf("Trying ATA native PCI addressing mode\n"); 3536 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 3537 } 3538 } 3539 #endif 3540 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3541 type = SYS_RES_IOPORT; 3542 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 3543 pci_add_map(bus, dev, PCIR_BAR(0), rl, force, 3544 prefetchmask & (1 << 0)); 3545 pci_add_map(bus, dev, PCIR_BAR(1), rl, force, 3546 prefetchmask & (1 << 1)); 3547 } else { 3548 rid = PCIR_BAR(0); 3549 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 3550 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0, 3551 0x1f7, 8, 0); 3552 rid = PCIR_BAR(1); 3553 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 3554 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6, 3555 0x3f6, 1, 0); 3556 } 3557 if (progif & PCIP_STORAGE_IDE_MODESEC) { 3558 pci_add_map(bus, dev, PCIR_BAR(2), rl, force, 3559 prefetchmask & (1 << 2)); 3560 pci_add_map(bus, dev, PCIR_BAR(3), rl, force, 3561 prefetchmask & (1 << 3)); 3562 } else { 3563 rid = PCIR_BAR(2); 3564 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 3565 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170, 3566 0x177, 8, 0); 3567 rid = PCIR_BAR(3); 3568 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 3569 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376, 3570 0x376, 1, 0); 3571 } 3572 pci_add_map(bus, dev, PCIR_BAR(4), rl, force, 3573 prefetchmask & (1 << 4)); 3574 pci_add_map(bus, dev, PCIR_BAR(5), rl, force, 3575 prefetchmask & (1 << 5)); 3576 } 3577 3578 static void 3579 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 3580 { 3581 struct pci_devinfo *dinfo = device_get_ivars(dev); 3582 pcicfgregs *cfg = &dinfo->cfg; 3583 char tunable_name[64]; 3584 int irq; 3585 3586 /* Has to have an intpin to have an interrupt. */ 3587 if (cfg->intpin == 0) 3588 return; 3589 3590 /* Let the user override the IRQ with a tunable. */ 3591 irq = PCI_INVALID_IRQ; 3592 snprintf(tunable_name, sizeof(tunable_name), 3593 "hw.pci%d.%d.%d.INT%c.irq", 3594 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 3595 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 3596 irq = PCI_INVALID_IRQ; 3597 3598 /* 3599 * If we didn't get an IRQ via the tunable, then we either use the 3600 * IRQ value in the intline register or we ask the bus to route an 3601 * interrupt for us. If force_route is true, then we only use the 3602 * value in the intline register if the bus was unable to assign an 3603 * IRQ. 3604 */ 3605 if (!PCI_INTERRUPT_VALID(irq)) { 3606 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 3607 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 3608 if (!PCI_INTERRUPT_VALID(irq)) 3609 irq = cfg->intline; 3610 } 3611 3612 /* If after all that we don't have an IRQ, just bail. */ 3613 if (!PCI_INTERRUPT_VALID(irq)) 3614 return; 3615 3616 /* Update the config register if it changed. */ 3617 if (irq != cfg->intline) { 3618 cfg->intline = irq; 3619 pci_write_config(dev, PCIR_INTLINE, irq, 1); 3620 } 3621 3622 /* Add this IRQ as rid 0 interrupt resource. */ 3623 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 3624 } 3625 3626 /* Perform early OHCI takeover from SMM. */ 3627 static void 3628 ohci_early_takeover(device_t self) 3629 { 3630 struct resource *res; 3631 uint32_t ctl; 3632 int rid; 3633 int i; 3634 3635 rid = PCIR_BAR(0); 3636 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3637 if (res == NULL) 3638 return; 3639 3640 ctl = bus_read_4(res, OHCI_CONTROL); 3641 if (ctl & OHCI_IR) { 3642 if (bootverbose) 3643 printf("ohci early: " 3644 "SMM active, request owner change\n"); 3645 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR); 3646 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 3647 DELAY(1000); 3648 ctl = bus_read_4(res, OHCI_CONTROL); 3649 } 3650 if (ctl & OHCI_IR) { 3651 if (bootverbose) 3652 printf("ohci early: " 3653 "SMM does not respond, resetting\n"); 3654 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET); 3655 } 3656 /* Disable interrupts */ 3657 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 3658 } 3659 3660 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3661 } 3662 3663 /* Perform early UHCI takeover from SMM. */ 3664 static void 3665 uhci_early_takeover(device_t self) 3666 { 3667 struct resource *res; 3668 int rid; 3669 3670 /* 3671 * Set the PIRQD enable bit and switch off all the others. We don't 3672 * want legacy support to interfere with us XXX Does this also mean 3673 * that the BIOS won't touch the keyboard anymore if it is connected 3674 * to the ports of the root hub? 3675 */ 3676 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2); 3677 3678 /* Disable interrupts */ 3679 rid = PCI_UHCI_BASE_REG; 3680 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE); 3681 if (res != NULL) { 3682 bus_write_2(res, UHCI_INTR, 0); 3683 bus_release_resource(self, SYS_RES_IOPORT, rid, res); 3684 } 3685 } 3686 3687 /* Perform early EHCI takeover from SMM. */ 3688 static void 3689 ehci_early_takeover(device_t self) 3690 { 3691 struct resource *res; 3692 uint32_t cparams; 3693 uint32_t eec; 3694 uint8_t eecp; 3695 uint8_t bios_sem; 3696 uint8_t offs; 3697 int rid; 3698 int i; 3699 3700 rid = PCIR_BAR(0); 3701 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3702 if (res == NULL) 3703 return; 3704 3705 cparams = bus_read_4(res, EHCI_HCCPARAMS); 3706 3707 /* Synchronise with the BIOS if it owns the controller. */ 3708 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0; 3709 eecp = EHCI_EECP_NEXT(eec)) { 3710 eec = pci_read_config(self, eecp, 4); 3711 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) { 3712 continue; 3713 } 3714 bios_sem = pci_read_config(self, eecp + 3715 EHCI_LEGSUP_BIOS_SEM, 1); 3716 if (bios_sem == 0) { 3717 continue; 3718 } 3719 if (bootverbose) 3720 printf("ehci early: " 3721 "SMM active, request owner change\n"); 3722 3723 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1); 3724 3725 for (i = 0; (i < 100) && (bios_sem != 0); i++) { 3726 DELAY(1000); 3727 bios_sem = pci_read_config(self, eecp + 3728 EHCI_LEGSUP_BIOS_SEM, 1); 3729 } 3730 3731 if (bios_sem != 0) { 3732 if (bootverbose) 3733 printf("ehci early: " 3734 "SMM does not respond\n"); 3735 } 3736 /* Disable interrupts */ 3737 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION)); 3738 bus_write_4(res, offs + EHCI_USBINTR, 0); 3739 } 3740 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3741 } 3742 3743 /* Perform early XHCI takeover from SMM. */ 3744 static void 3745 xhci_early_takeover(device_t self) 3746 { 3747 struct resource *res; 3748 uint32_t cparams; 3749 uint32_t eec; 3750 uint8_t eecp; 3751 uint8_t bios_sem; 3752 uint8_t offs; 3753 int rid; 3754 int i; 3755 3756 rid = PCIR_BAR(0); 3757 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3758 if (res == NULL) 3759 return; 3760 3761 cparams = bus_read_4(res, XHCI_HCSPARAMS0); 3762 3763 eec = -1; 3764 3765 /* Synchronise with the BIOS if it owns the controller. */ 3766 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 3767 eecp += XHCI_XECP_NEXT(eec) << 2) { 3768 eec = bus_read_4(res, eecp); 3769 3770 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 3771 continue; 3772 3773 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM); 3774 if (bios_sem == 0) 3775 continue; 3776 3777 if (bootverbose) 3778 printf("xhci early: " 3779 "SMM active, request owner change\n"); 3780 3781 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1); 3782 3783 /* wait a maximum of 5 second */ 3784 3785 for (i = 0; (i < 5000) && (bios_sem != 0); i++) { 3786 DELAY(1000); 3787 bios_sem = bus_read_1(res, eecp + 3788 XHCI_XECP_BIOS_SEM); 3789 } 3790 3791 if (bios_sem != 0) { 3792 if (bootverbose) 3793 printf("xhci early: " 3794 "SMM does not respond\n"); 3795 } 3796 3797 /* Disable interrupts */ 3798 offs = bus_read_1(res, XHCI_CAPLENGTH); 3799 bus_write_4(res, offs + XHCI_USBCMD, 0); 3800 bus_read_4(res, offs + XHCI_USBSTS); 3801 } 3802 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3803 } 3804 3805 static void 3806 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg, 3807 struct resource_list *rl) 3808 { 3809 struct resource *res; 3810 char *cp; 3811 rman_res_t start, end, count; 3812 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus; 3813 3814 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3815 case PCIM_HDRTYPE_BRIDGE: 3816 sec_reg = PCIR_SECBUS_1; 3817 sub_reg = PCIR_SUBBUS_1; 3818 break; 3819 case PCIM_HDRTYPE_CARDBUS: 3820 sec_reg = PCIR_SECBUS_2; 3821 sub_reg = PCIR_SUBBUS_2; 3822 break; 3823 default: 3824 return; 3825 } 3826 3827 /* 3828 * If the existing bus range is valid, attempt to reserve it 3829 * from our parent. If this fails for any reason, clear the 3830 * secbus and subbus registers. 3831 * 3832 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus? 3833 * This would at least preserve the existing sec_bus if it is 3834 * valid. 3835 */ 3836 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1); 3837 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1); 3838 3839 /* Quirk handling. */ 3840 switch (pci_get_devid(dev)) { 3841 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 3842 sup_bus = pci_read_config(dev, 0x41, 1); 3843 if (sup_bus != 0xff) { 3844 sec_bus = sup_bus + 1; 3845 sub_bus = sup_bus + 1; 3846 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1); 3847 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3848 } 3849 break; 3850 3851 case 0x00dd10de: 3852 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 3853 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 3854 break; 3855 if (strncmp(cp, "Compal", 6) != 0) { 3856 freeenv(cp); 3857 break; 3858 } 3859 freeenv(cp); 3860 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 3861 break; 3862 if (strncmp(cp, "08A0", 4) != 0) { 3863 freeenv(cp); 3864 break; 3865 } 3866 freeenv(cp); 3867 if (sub_bus < 0xa) { 3868 sub_bus = 0xa; 3869 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3870 } 3871 break; 3872 } 3873 3874 if (bootverbose) 3875 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus); 3876 if (sec_bus > 0 && sub_bus >= sec_bus) { 3877 start = sec_bus; 3878 end = sub_bus; 3879 count = end - start + 1; 3880 3881 resource_list_add(rl, PCI_RES_BUS, 0, 0, ~0, count); 3882 3883 /* 3884 * If requested, clear secondary bus registers in 3885 * bridge devices to force a complete renumbering 3886 * rather than reserving the existing range. However, 3887 * preserve the existing size. 3888 */ 3889 if (pci_clear_buses) 3890 goto clear; 3891 3892 rid = 0; 3893 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid, 3894 start, end, count, 0); 3895 if (res != NULL) 3896 return; 3897 3898 if (bootverbose) 3899 device_printf(bus, 3900 "pci%d:%d:%d:%d secbus failed to allocate\n", 3901 pci_get_domain(dev), pci_get_bus(dev), 3902 pci_get_slot(dev), pci_get_function(dev)); 3903 } 3904 3905 clear: 3906 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1); 3907 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1); 3908 } 3909 3910 static struct resource * 3911 pci_alloc_secbus(device_t dev, device_t child, int *rid, rman_res_t start, 3912 rman_res_t end, rman_res_t count, u_int flags) 3913 { 3914 struct pci_devinfo *dinfo; 3915 pcicfgregs *cfg; 3916 struct resource_list *rl; 3917 struct resource *res; 3918 int sec_reg, sub_reg; 3919 3920 dinfo = device_get_ivars(child); 3921 cfg = &dinfo->cfg; 3922 rl = &dinfo->resources; 3923 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3924 case PCIM_HDRTYPE_BRIDGE: 3925 sec_reg = PCIR_SECBUS_1; 3926 sub_reg = PCIR_SUBBUS_1; 3927 break; 3928 case PCIM_HDRTYPE_CARDBUS: 3929 sec_reg = PCIR_SECBUS_2; 3930 sub_reg = PCIR_SUBBUS_2; 3931 break; 3932 default: 3933 return (NULL); 3934 } 3935 3936 if (*rid != 0) 3937 return (NULL); 3938 3939 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL) 3940 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count); 3941 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) { 3942 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid, 3943 start, end, count, flags & ~RF_ACTIVE); 3944 if (res == NULL) { 3945 resource_list_delete(rl, PCI_RES_BUS, *rid); 3946 device_printf(child, "allocating %ju bus%s failed\n", 3947 count, count == 1 ? "" : "es"); 3948 return (NULL); 3949 } 3950 if (bootverbose) 3951 device_printf(child, 3952 "Lazy allocation of %ju bus%s at %ju\n", count, 3953 count == 1 ? "" : "es", rman_get_start(res)); 3954 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1); 3955 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1); 3956 } 3957 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start, 3958 end, count, flags)); 3959 } 3960 3961 static int 3962 pci_ea_bei_to_rid(device_t dev, int bei) 3963 { 3964 #ifdef PCI_IOV 3965 struct pci_devinfo *dinfo; 3966 int iov_pos; 3967 struct pcicfg_iov *iov; 3968 3969 dinfo = device_get_ivars(dev); 3970 iov = dinfo->cfg.iov; 3971 if (iov != NULL) 3972 iov_pos = iov->iov_pos; 3973 else 3974 iov_pos = 0; 3975 #endif 3976 3977 /* Check if matches BAR */ 3978 if ((bei >= PCIM_EA_BEI_BAR_0) && 3979 (bei <= PCIM_EA_BEI_BAR_5)) 3980 return (PCIR_BAR(bei)); 3981 3982 /* Check ROM */ 3983 if (bei == PCIM_EA_BEI_ROM) 3984 return (PCIR_BIOS); 3985 3986 #ifdef PCI_IOV 3987 /* Check if matches VF_BAR */ 3988 if ((iov != NULL) && (bei >= PCIM_EA_BEI_VF_BAR_0) && 3989 (bei <= PCIM_EA_BEI_VF_BAR_5)) 3990 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) + 3991 iov_pos); 3992 #endif 3993 3994 return (-1); 3995 } 3996 3997 int 3998 pci_ea_is_enabled(device_t dev, int rid) 3999 { 4000 struct pci_ea_entry *ea; 4001 struct pci_devinfo *dinfo; 4002 4003 dinfo = device_get_ivars(dev); 4004 4005 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 4006 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid) 4007 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0); 4008 } 4009 4010 return (0); 4011 } 4012 4013 void 4014 pci_add_resources_ea(device_t bus, device_t dev, int alloc_iov) 4015 { 4016 struct pci_ea_entry *ea; 4017 struct pci_devinfo *dinfo; 4018 pci_addr_t start, end, count; 4019 struct resource_list *rl; 4020 int type, flags, rid; 4021 struct resource *res; 4022 uint32_t tmp; 4023 #ifdef PCI_IOV 4024 struct pcicfg_iov *iov; 4025 #endif 4026 4027 dinfo = device_get_ivars(dev); 4028 rl = &dinfo->resources; 4029 flags = 0; 4030 4031 #ifdef PCI_IOV 4032 iov = dinfo->cfg.iov; 4033 #endif 4034 4035 if (dinfo->cfg.ea.ea_location == 0) 4036 return; 4037 4038 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 4039 /* 4040 * TODO: Ignore EA-BAR if is not enabled. 4041 * Currently the EA implementation supports 4042 * only situation, where EA structure contains 4043 * predefined entries. In case they are not enabled 4044 * leave them unallocated and proceed with 4045 * a legacy-BAR mechanism. 4046 */ 4047 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0) 4048 continue; 4049 4050 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) { 4051 case PCIM_EA_P_MEM_PREFETCH: 4052 case PCIM_EA_P_VF_MEM_PREFETCH: 4053 flags = RF_PREFETCHABLE; 4054 /* FALLTHROUGH */ 4055 case PCIM_EA_P_VF_MEM: 4056 case PCIM_EA_P_MEM: 4057 type = SYS_RES_MEMORY; 4058 break; 4059 case PCIM_EA_P_IO: 4060 type = SYS_RES_IOPORT; 4061 break; 4062 default: 4063 continue; 4064 } 4065 4066 if (alloc_iov != 0) { 4067 #ifdef PCI_IOV 4068 /* Allocating IOV, confirm BEI matches */ 4069 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) || 4070 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5)) 4071 continue; 4072 #else 4073 continue; 4074 #endif 4075 } else { 4076 /* Allocating BAR, confirm BEI matches */ 4077 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) || 4078 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) && 4079 (ea->eae_bei != PCIM_EA_BEI_ROM)) 4080 continue; 4081 } 4082 4083 rid = pci_ea_bei_to_rid(dev, ea->eae_bei); 4084 if (rid < 0) 4085 continue; 4086 4087 /* Skip resources already allocated by EA */ 4088 if ((resource_list_find(rl, SYS_RES_MEMORY, rid) != NULL) || 4089 (resource_list_find(rl, SYS_RES_IOPORT, rid) != NULL)) 4090 continue; 4091 4092 start = ea->eae_base; 4093 count = ea->eae_max_offset + 1; 4094 #ifdef PCI_IOV 4095 if (iov != NULL) 4096 count = count * iov->iov_num_vfs; 4097 #endif 4098 end = start + count - 1; 4099 if (count == 0) 4100 continue; 4101 4102 resource_list_add(rl, type, rid, start, end, count); 4103 res = resource_list_reserve(rl, bus, dev, type, &rid, start, end, count, 4104 flags); 4105 if (res == NULL) { 4106 resource_list_delete(rl, type, rid); 4107 4108 /* 4109 * Failed to allocate using EA, disable entry. 4110 * Another attempt to allocation will be performed 4111 * further, but this time using legacy BAR registers 4112 */ 4113 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4); 4114 tmp &= ~PCIM_EA_ENABLE; 4115 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4); 4116 4117 /* 4118 * Disabling entry might fail in case it is hardwired. 4119 * Read flags again to match current status. 4120 */ 4121 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4); 4122 4123 continue; 4124 } 4125 4126 /* As per specification, fill BAR with zeros */ 4127 pci_write_config(dev, rid, 0, 4); 4128 } 4129 } 4130 4131 void 4132 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 4133 { 4134 struct pci_devinfo *dinfo; 4135 pcicfgregs *cfg; 4136 struct resource_list *rl; 4137 const struct pci_quirk *q; 4138 uint32_t devid; 4139 int i; 4140 4141 dinfo = device_get_ivars(dev); 4142 cfg = &dinfo->cfg; 4143 rl = &dinfo->resources; 4144 devid = (cfg->device << 16) | cfg->vendor; 4145 4146 /* Allocate resources using Enhanced Allocation */ 4147 pci_add_resources_ea(bus, dev, 0); 4148 4149 /* ATA devices needs special map treatment */ 4150 if ((pci_get_class(dev) == PCIC_STORAGE) && 4151 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 4152 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 4153 (!pci_read_config(dev, PCIR_BAR(0), 4) && 4154 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 4155 pci_ata_maps(bus, dev, rl, force, prefetchmask); 4156 else 4157 for (i = 0; i < cfg->nummaps;) { 4158 /* Skip resources already managed by EA */ 4159 if ((resource_list_find(rl, SYS_RES_MEMORY, PCIR_BAR(i)) != NULL) || 4160 (resource_list_find(rl, SYS_RES_IOPORT, PCIR_BAR(i)) != NULL) || 4161 pci_ea_is_enabled(dev, PCIR_BAR(i))) { 4162 i++; 4163 continue; 4164 } 4165 4166 /* 4167 * Skip quirked resources. 4168 */ 4169 for (q = &pci_quirks[0]; q->devid != 0; q++) 4170 if (q->devid == devid && 4171 q->type == PCI_QUIRK_UNMAP_REG && 4172 q->arg1 == PCIR_BAR(i)) 4173 break; 4174 if (q->devid != 0) { 4175 i++; 4176 continue; 4177 } 4178 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force, 4179 prefetchmask & (1 << i)); 4180 } 4181 4182 /* 4183 * Add additional, quirked resources. 4184 */ 4185 for (q = &pci_quirks[0]; q->devid != 0; q++) 4186 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) 4187 pci_add_map(bus, dev, q->arg1, rl, force, 0); 4188 4189 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline) && 4190 pci_intx_reroute) { 4191 /* 4192 * Try to re-route interrupts. Sometimes the BIOS or 4193 * firmware may leave bogus values in these registers. 4194 * If the re-route fails, then just stick with what we 4195 * have. 4196 */ 4197 pci_assign_interrupt(bus, dev, 1); 4198 } 4199 4200 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS && 4201 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) { 4202 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI) 4203 xhci_early_takeover(dev); 4204 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI) 4205 ehci_early_takeover(dev); 4206 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI) 4207 ohci_early_takeover(dev); 4208 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI) 4209 uhci_early_takeover(dev); 4210 } 4211 4212 /* 4213 * Reserve resources for secondary bus ranges behind bridge 4214 * devices. 4215 */ 4216 pci_reserve_secbus(bus, dev, cfg, rl); 4217 } 4218 4219 static struct pci_devinfo * 4220 pci_identify_function(device_t pcib, device_t dev, int domain, int busno, 4221 int slot, int func) 4222 { 4223 struct pci_devinfo *dinfo; 4224 4225 dinfo = pci_read_device(pcib, dev, domain, busno, slot, func); 4226 if (dinfo != NULL) 4227 pci_add_child(dev, dinfo); 4228 4229 return (dinfo); 4230 } 4231 4232 void 4233 pci_add_children(device_t dev, int domain, int busno) 4234 { 4235 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4236 device_t pcib = device_get_parent(dev); 4237 struct pci_devinfo *dinfo; 4238 int maxslots; 4239 int s, f, pcifunchigh; 4240 uint8_t hdrtype; 4241 int first_func; 4242 4243 /* 4244 * Try to detect a device at slot 0, function 0. If it exists, try to 4245 * enable ARI. We must enable ARI before detecting the rest of the 4246 * functions on this bus as ARI changes the set of slots and functions 4247 * that are legal on this bus. 4248 */ 4249 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0); 4250 if (dinfo != NULL && pci_enable_ari) 4251 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); 4252 4253 /* 4254 * Start looking for new devices on slot 0 at function 1 because we 4255 * just identified the device at slot 0, function 0. 4256 */ 4257 first_func = 1; 4258 4259 maxslots = PCIB_MAXSLOTS(pcib); 4260 for (s = 0; s <= maxslots; s++, first_func = 0) { 4261 pcifunchigh = 0; 4262 f = 0; 4263 DELAY(1); 4264 4265 /* If function 0 is not present, skip to the next slot. */ 4266 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4267 continue; 4268 hdrtype = REG(PCIR_HDRTYPE, 1); 4269 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4270 continue; 4271 if (hdrtype & PCIM_MFDEV) 4272 pcifunchigh = PCIB_MAXFUNCS(pcib); 4273 for (f = first_func; f <= pcifunchigh; f++) 4274 pci_identify_function(pcib, dev, domain, busno, s, f); 4275 } 4276 #undef REG 4277 } 4278 4279 int 4280 pci_rescan_method(device_t dev) 4281 { 4282 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4283 device_t pcib = device_get_parent(dev); 4284 device_t child, *devlist, *unchanged; 4285 int devcount, error, i, j, maxslots, oldcount; 4286 int busno, domain, s, f, pcifunchigh; 4287 uint8_t hdrtype; 4288 4289 /* No need to check for ARI on a rescan. */ 4290 error = device_get_children(dev, &devlist, &devcount); 4291 if (error) 4292 return (error); 4293 if (devcount != 0) { 4294 unchanged = malloc(devcount * sizeof(device_t), M_TEMP, 4295 M_NOWAIT | M_ZERO); 4296 if (unchanged == NULL) { 4297 free(devlist, M_TEMP); 4298 return (ENOMEM); 4299 } 4300 } else 4301 unchanged = NULL; 4302 4303 domain = pcib_get_domain(dev); 4304 busno = pcib_get_bus(dev); 4305 maxslots = PCIB_MAXSLOTS(pcib); 4306 for (s = 0; s <= maxslots; s++) { 4307 /* If function 0 is not present, skip to the next slot. */ 4308 f = 0; 4309 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4310 continue; 4311 pcifunchigh = 0; 4312 hdrtype = REG(PCIR_HDRTYPE, 1); 4313 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4314 continue; 4315 if (hdrtype & PCIM_MFDEV) 4316 pcifunchigh = PCIB_MAXFUNCS(pcib); 4317 for (f = 0; f <= pcifunchigh; f++) { 4318 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4319 continue; 4320 4321 /* 4322 * Found a valid function. Check if a 4323 * device_t for this device already exists. 4324 */ 4325 for (i = 0; i < devcount; i++) { 4326 child = devlist[i]; 4327 if (child == NULL) 4328 continue; 4329 if (pci_get_slot(child) == s && 4330 pci_get_function(child) == f) { 4331 unchanged[i] = child; 4332 goto next_func; 4333 } 4334 } 4335 4336 pci_identify_function(pcib, dev, domain, busno, s, f); 4337 next_func:; 4338 } 4339 } 4340 4341 /* Remove devices that are no longer present. */ 4342 for (i = 0; i < devcount; i++) { 4343 if (unchanged[i] != NULL) 4344 continue; 4345 device_delete_child(dev, devlist[i]); 4346 } 4347 4348 free(devlist, M_TEMP); 4349 oldcount = devcount; 4350 4351 /* Try to attach the devices just added. */ 4352 error = device_get_children(dev, &devlist, &devcount); 4353 if (error) { 4354 free(unchanged, M_TEMP); 4355 return (error); 4356 } 4357 4358 for (i = 0; i < devcount; i++) { 4359 for (j = 0; j < oldcount; j++) { 4360 if (devlist[i] == unchanged[j]) 4361 goto next_device; 4362 } 4363 4364 device_probe_and_attach(devlist[i]); 4365 next_device:; 4366 } 4367 4368 free(unchanged, M_TEMP); 4369 free(devlist, M_TEMP); 4370 return (0); 4371 #undef REG 4372 } 4373 4374 #ifdef PCI_IOV 4375 device_t 4376 pci_add_iov_child(device_t bus, device_t pf, uint16_t rid, uint16_t vid, 4377 uint16_t did) 4378 { 4379 struct pci_devinfo *vf_dinfo; 4380 device_t pcib; 4381 int busno, slot, func; 4382 4383 pcib = device_get_parent(bus); 4384 4385 PCIB_DECODE_RID(pcib, rid, &busno, &slot, &func); 4386 4387 vf_dinfo = pci_fill_devinfo(pcib, bus, pci_get_domain(pcib), busno, 4388 slot, func, vid, did); 4389 4390 vf_dinfo->cfg.flags |= PCICFG_VF; 4391 pci_add_child(bus, vf_dinfo); 4392 4393 return (vf_dinfo->cfg.dev); 4394 } 4395 4396 device_t 4397 pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid, 4398 uint16_t vid, uint16_t did) 4399 { 4400 4401 return (pci_add_iov_child(bus, pf, rid, vid, did)); 4402 } 4403 #endif 4404 4405 /* 4406 * For PCIe device set Max_Payload_Size to match PCIe root's. 4407 */ 4408 static void 4409 pcie_setup_mps(device_t dev) 4410 { 4411 struct pci_devinfo *dinfo = device_get_ivars(dev); 4412 device_t root; 4413 uint16_t rmps, mmps, mps; 4414 4415 if (dinfo->cfg.pcie.pcie_location == 0) 4416 return; 4417 root = pci_find_pcie_root_port(dev); 4418 if (root == NULL) 4419 return; 4420 /* Check whether the MPS is already configured. */ 4421 rmps = pcie_read_config(root, PCIER_DEVICE_CTL, 2) & 4422 PCIEM_CTL_MAX_PAYLOAD; 4423 mps = pcie_read_config(dev, PCIER_DEVICE_CTL, 2) & 4424 PCIEM_CTL_MAX_PAYLOAD; 4425 if (mps == rmps) 4426 return; 4427 /* Check whether the device is capable of the root's MPS. */ 4428 mmps = (pcie_read_config(dev, PCIER_DEVICE_CAP, 2) & 4429 PCIEM_CAP_MAX_PAYLOAD) << 5; 4430 if (rmps > mmps) { 4431 /* 4432 * The device is unable to handle root's MPS. Limit root. 4433 * XXX: We should traverse through all the tree, applying 4434 * it to all the devices. 4435 */ 4436 pcie_adjust_config(root, PCIER_DEVICE_CTL, 4437 PCIEM_CTL_MAX_PAYLOAD, mmps, 2); 4438 } else { 4439 pcie_adjust_config(dev, PCIER_DEVICE_CTL, 4440 PCIEM_CTL_MAX_PAYLOAD, rmps, 2); 4441 } 4442 } 4443 4444 static void 4445 pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo) 4446 { 4447 int aer; 4448 uint32_t r; 4449 uint16_t r2; 4450 4451 if (dinfo->cfg.pcie.pcie_location != 0 && 4452 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) { 4453 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4454 PCIER_ROOT_CTL, 2); 4455 r2 &= ~(PCIEM_ROOT_CTL_SERR_CORR | 4456 PCIEM_ROOT_CTL_SERR_NONFATAL | PCIEM_ROOT_CTL_SERR_FATAL); 4457 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4458 PCIER_ROOT_CTL, r2, 2); 4459 } 4460 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 4461 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 4462 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 4463 if (r != 0 && bootverbose) { 4464 pci_printf(&dinfo->cfg, 4465 "clearing AER UC 0x%08x -> 0x%08x\n", 4466 r, pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4467 4)); 4468 } 4469 4470 r = pci_read_config(dev, aer + PCIR_AER_UC_MASK, 4); 4471 r &= ~(PCIM_AER_UC_TRAINING_ERROR | 4472 PCIM_AER_UC_DL_PROTOCOL_ERROR | 4473 PCIM_AER_UC_SURPRISE_LINK_DOWN | 4474 PCIM_AER_UC_POISONED_TLP | 4475 PCIM_AER_UC_FC_PROTOCOL_ERROR | 4476 PCIM_AER_UC_COMPLETION_TIMEOUT | 4477 PCIM_AER_UC_COMPLETER_ABORT | 4478 PCIM_AER_UC_UNEXPECTED_COMPLETION | 4479 PCIM_AER_UC_RECEIVER_OVERFLOW | 4480 PCIM_AER_UC_MALFORMED_TLP | 4481 PCIM_AER_UC_ECRC_ERROR | 4482 PCIM_AER_UC_UNSUPPORTED_REQUEST | 4483 PCIM_AER_UC_ACS_VIOLATION | 4484 PCIM_AER_UC_INTERNAL_ERROR | 4485 PCIM_AER_UC_MC_BLOCKED_TLP | 4486 PCIM_AER_UC_ATOMIC_EGRESS_BLK | 4487 PCIM_AER_UC_TLP_PREFIX_BLOCKED); 4488 pci_write_config(dev, aer + PCIR_AER_UC_MASK, r, 4); 4489 4490 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 4491 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 4492 if (r != 0 && bootverbose) { 4493 pci_printf(&dinfo->cfg, 4494 "clearing AER COR 0x%08x -> 0x%08x\n", 4495 r, pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4496 4)); 4497 } 4498 4499 r = pci_read_config(dev, aer + PCIR_AER_COR_MASK, 4); 4500 r &= ~(PCIM_AER_COR_RECEIVER_ERROR | 4501 PCIM_AER_COR_BAD_TLP | 4502 PCIM_AER_COR_BAD_DLLP | 4503 PCIM_AER_COR_REPLAY_ROLLOVER | 4504 PCIM_AER_COR_REPLAY_TIMEOUT | 4505 PCIM_AER_COR_ADVISORY_NF_ERROR | 4506 PCIM_AER_COR_INTERNAL_ERROR | 4507 PCIM_AER_COR_HEADER_LOG_OVFLOW); 4508 pci_write_config(dev, aer + PCIR_AER_COR_MASK, r, 4); 4509 4510 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4511 PCIER_DEVICE_CTL, 2); 4512 r |= PCIEM_CTL_COR_ENABLE | PCIEM_CTL_NFER_ENABLE | 4513 PCIEM_CTL_FER_ENABLE | PCIEM_CTL_URR_ENABLE; 4514 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4515 PCIER_DEVICE_CTL, r, 2); 4516 } 4517 } 4518 4519 void 4520 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 4521 { 4522 device_t dev; 4523 4524 dinfo->cfg.dev = dev = device_add_child(bus, NULL, DEVICE_UNIT_ANY); 4525 device_set_ivars(dev, dinfo); 4526 resource_list_init(&dinfo->resources); 4527 pci_cfg_save(dev, dinfo, 0); 4528 pci_cfg_restore(dev, dinfo); 4529 pci_clear_pme(dev); 4530 pci_print_verbose(dinfo); 4531 pci_add_resources(bus, dev, 0, 0); 4532 if (pci_enable_mps_tune) 4533 pcie_setup_mps(dev); 4534 pci_child_added(dinfo->cfg.dev); 4535 4536 if (pci_clear_aer_on_attach) 4537 pci_add_child_clear_aer(dev, dinfo); 4538 4539 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev); 4540 } 4541 4542 void 4543 pci_child_added_method(device_t dev, device_t child) 4544 { 4545 4546 } 4547 4548 static int 4549 pci_probe(device_t dev) 4550 { 4551 4552 device_set_desc(dev, "PCI bus"); 4553 4554 /* Allow other subclasses to override this driver. */ 4555 return (BUS_PROBE_GENERIC); 4556 } 4557 4558 int 4559 pci_attach_common(device_t dev) 4560 { 4561 struct pci_softc *sc; 4562 int busno, domain; 4563 int rid; 4564 4565 sc = device_get_softc(dev); 4566 domain = pcib_get_domain(dev); 4567 busno = pcib_get_bus(dev); 4568 rid = 0; 4569 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, 4570 1, 0); 4571 if (sc->sc_bus == NULL) { 4572 device_printf(dev, "failed to allocate bus number\n"); 4573 return (ENXIO); 4574 } 4575 if (bootverbose) 4576 device_printf(dev, "domain=%d, physical bus=%d\n", 4577 domain, busno); 4578 sc->sc_dma_tag = bus_get_dma_tag(dev); 4579 return (0); 4580 } 4581 4582 int 4583 pci_attach(device_t dev) 4584 { 4585 int busno, domain, error; 4586 4587 error = pci_attach_common(dev); 4588 if (error) 4589 return (error); 4590 4591 /* 4592 * Since there can be multiple independently numbered PCI 4593 * buses on systems with multiple PCI domains, we can't use 4594 * the unit number to decide which bus we are probing. We ask 4595 * the parent pcib what our domain and bus numbers are. 4596 */ 4597 domain = pcib_get_domain(dev); 4598 busno = pcib_get_bus(dev); 4599 pci_add_children(dev, domain, busno); 4600 bus_attach_children(dev); 4601 return (0); 4602 } 4603 4604 int 4605 pci_detach(device_t dev) 4606 { 4607 struct pci_softc *sc; 4608 int error; 4609 4610 error = bus_generic_detach(dev); 4611 if (error) 4612 return (error); 4613 sc = device_get_softc(dev); 4614 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus); 4615 return (error); 4616 } 4617 4618 static void 4619 pci_hint_device_unit(device_t dev, device_t child, const char *name, int *unitp) 4620 { 4621 int line, unit; 4622 const char *at; 4623 char me1[24], me2[32]; 4624 uint8_t b, s, f; 4625 uint32_t d; 4626 device_location_cache_t *cache; 4627 4628 d = pci_get_domain(child); 4629 b = pci_get_bus(child); 4630 s = pci_get_slot(child); 4631 f = pci_get_function(child); 4632 snprintf(me1, sizeof(me1), "pci%u:%u:%u", b, s, f); 4633 snprintf(me2, sizeof(me2), "pci%u:%u:%u:%u", d, b, s, f); 4634 line = 0; 4635 cache = dev_wired_cache_init(); 4636 while (resource_find_dev(&line, name, &unit, "at", NULL) == 0) { 4637 resource_string_value(name, unit, "at", &at); 4638 if (strcmp(at, me1) == 0 || strcmp(at, me2) == 0) { 4639 *unitp = unit; 4640 break; 4641 } 4642 if (dev_wired_cache_match(cache, child, at)) { 4643 *unitp = unit; 4644 break; 4645 } 4646 } 4647 dev_wired_cache_fini(cache); 4648 } 4649 4650 static void 4651 pci_set_power_child(device_t dev, device_t child, int state) 4652 { 4653 device_t pcib; 4654 int dstate; 4655 4656 /* 4657 * Set the device to the given state. If the firmware suggests 4658 * a different power state, use it instead. If power management 4659 * is not present, the firmware is responsible for managing 4660 * device power. Skip children who aren't attached since they 4661 * are handled separately. 4662 */ 4663 pcib = device_get_parent(dev); 4664 dstate = state; 4665 if (device_is_attached(child) && 4666 PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0) 4667 pci_set_powerstate(child, dstate); 4668 } 4669 4670 int 4671 pci_suspend_child(device_t dev, device_t child) 4672 { 4673 struct pci_devinfo *dinfo; 4674 struct resource_list_entry *rle; 4675 int error; 4676 4677 dinfo = device_get_ivars(child); 4678 4679 /* 4680 * Save the PCI configuration space for the child and set the 4681 * device in the appropriate power state for this sleep state. 4682 */ 4683 pci_cfg_save(child, dinfo, 0); 4684 4685 /* Suspend devices before potentially powering them down. */ 4686 error = bus_generic_suspend_child(dev, child); 4687 4688 if (error) 4689 return (error); 4690 4691 if (pci_do_power_suspend) { 4692 /* 4693 * Make sure this device's interrupt handler is not invoked 4694 * in the case the device uses a shared interrupt that can 4695 * be raised by some other device. 4696 * This is applicable only to regular (legacy) PCI interrupts 4697 * as MSI/MSI-X interrupts are never shared. 4698 */ 4699 rle = resource_list_find(&dinfo->resources, 4700 SYS_RES_IRQ, 0); 4701 if (rle != NULL && rle->res != NULL) 4702 (void)bus_suspend_intr(child, rle->res); 4703 pci_set_power_child(dev, child, PCI_POWERSTATE_D3); 4704 } 4705 4706 return (0); 4707 } 4708 4709 int 4710 pci_resume_child(device_t dev, device_t child) 4711 { 4712 struct pci_devinfo *dinfo; 4713 struct resource_list_entry *rle; 4714 4715 if (pci_do_power_resume) 4716 pci_set_power_child(dev, child, PCI_POWERSTATE_D0); 4717 4718 dinfo = device_get_ivars(child); 4719 pci_cfg_restore(child, dinfo); 4720 pci_clear_pme(child); 4721 if (!device_is_attached(child)) 4722 pci_cfg_save(child, dinfo, 1); 4723 4724 bus_generic_resume_child(dev, child); 4725 4726 /* 4727 * Allow interrupts only after fully resuming the driver and hardware. 4728 */ 4729 if (pci_do_power_suspend) { 4730 /* See pci_suspend_child for details. */ 4731 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 4732 if (rle != NULL && rle->res != NULL) 4733 (void)bus_resume_intr(child, rle->res); 4734 } 4735 4736 return (0); 4737 } 4738 4739 int 4740 pci_resume(device_t dev) 4741 { 4742 device_t child, *devlist; 4743 int error, i, numdevs; 4744 4745 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 4746 return (error); 4747 4748 /* 4749 * Resume critical devices first, then everything else later. 4750 */ 4751 for (i = 0; i < numdevs; i++) { 4752 child = devlist[i]; 4753 switch (pci_get_class(child)) { 4754 case PCIC_DISPLAY: 4755 case PCIC_MEMORY: 4756 case PCIC_BRIDGE: 4757 case PCIC_BASEPERIPH: 4758 BUS_RESUME_CHILD(dev, child); 4759 break; 4760 } 4761 } 4762 for (i = 0; i < numdevs; i++) { 4763 child = devlist[i]; 4764 switch (pci_get_class(child)) { 4765 case PCIC_DISPLAY: 4766 case PCIC_MEMORY: 4767 case PCIC_BRIDGE: 4768 case PCIC_BASEPERIPH: 4769 break; 4770 default: 4771 BUS_RESUME_CHILD(dev, child); 4772 } 4773 } 4774 free(devlist, M_TEMP); 4775 return (0); 4776 } 4777 4778 static void 4779 pci_load_vendor_data(void) 4780 { 4781 caddr_t data; 4782 void *ptr; 4783 size_t sz; 4784 4785 data = preload_search_by_type("pci_vendor_data"); 4786 if (data != NULL) { 4787 ptr = preload_fetch_addr(data); 4788 sz = preload_fetch_size(data); 4789 if (ptr != NULL && sz != 0) { 4790 pci_vendordata = ptr; 4791 pci_vendordata_size = sz; 4792 /* terminate the database */ 4793 pci_vendordata[pci_vendordata_size] = '\n'; 4794 } 4795 } 4796 } 4797 4798 void 4799 pci_driver_added(device_t dev, driver_t *driver) 4800 { 4801 int numdevs; 4802 device_t *devlist; 4803 device_t child; 4804 struct pci_devinfo *dinfo; 4805 int i; 4806 4807 if (bootverbose) 4808 device_printf(dev, "driver added\n"); 4809 DEVICE_IDENTIFY(driver, dev); 4810 if (device_get_children(dev, &devlist, &numdevs) != 0) 4811 return; 4812 for (i = 0; i < numdevs; i++) { 4813 child = devlist[i]; 4814 if (device_get_state(child) != DS_NOTPRESENT) 4815 continue; 4816 dinfo = device_get_ivars(child); 4817 pci_print_verbose(dinfo); 4818 if (bootverbose) 4819 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); 4820 pci_cfg_restore(child, dinfo); 4821 if (device_probe_and_attach(child) != 0) 4822 pci_child_detached(dev, child); 4823 } 4824 free(devlist, M_TEMP); 4825 } 4826 4827 int 4828 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, 4829 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep) 4830 { 4831 struct pci_devinfo *dinfo; 4832 struct msix_table_entry *mte; 4833 struct msix_vector *mv; 4834 uint64_t addr; 4835 uint32_t data; 4836 void *cookie; 4837 int error, rid; 4838 4839 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr, 4840 arg, &cookie); 4841 if (error) 4842 return (error); 4843 4844 /* If this is not a direct child, just bail out. */ 4845 if (device_get_parent(child) != dev) { 4846 *cookiep = cookie; 4847 return(0); 4848 } 4849 4850 rid = rman_get_rid(irq); 4851 if (rid == 0) { 4852 /* Make sure that INTx is enabled */ 4853 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4854 } else { 4855 /* 4856 * Check to see if the interrupt is MSI or MSI-X. 4857 * Ask our parent to map the MSI and give 4858 * us the address and data register values. 4859 * If we fail for some reason, teardown the 4860 * interrupt handler. 4861 */ 4862 dinfo = device_get_ivars(child); 4863 if (dinfo->cfg.msi.msi_alloc > 0) { 4864 if (dinfo->cfg.msi.msi_addr == 0) { 4865 KASSERT(dinfo->cfg.msi.msi_handlers == 0, 4866 ("MSI has handlers, but vectors not mapped")); 4867 error = PCIB_MAP_MSI(device_get_parent(dev), 4868 child, rman_get_start(irq), &addr, &data); 4869 if (error) 4870 goto bad; 4871 dinfo->cfg.msi.msi_addr = addr; 4872 dinfo->cfg.msi.msi_data = data; 4873 } 4874 if (dinfo->cfg.msi.msi_handlers == 0) 4875 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, 4876 dinfo->cfg.msi.msi_data); 4877 dinfo->cfg.msi.msi_handlers++; 4878 } else { 4879 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4880 ("No MSI or MSI-X interrupts allocated")); 4881 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4882 ("MSI-X index too high")); 4883 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4884 KASSERT(mte->mte_vector != 0, ("no message vector")); 4885 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; 4886 KASSERT(mv->mv_irq == rman_get_start(irq), 4887 ("IRQ mismatch")); 4888 if (mv->mv_address == 0) { 4889 KASSERT(mte->mte_handlers == 0, 4890 ("MSI-X table entry has handlers, but vector not mapped")); 4891 error = PCIB_MAP_MSI(device_get_parent(dev), 4892 child, rman_get_start(irq), &addr, &data); 4893 if (error) 4894 goto bad; 4895 mv->mv_address = addr; 4896 mv->mv_data = data; 4897 } 4898 4899 /* 4900 * The MSIX table entry must be made valid by 4901 * incrementing the mte_handlers before 4902 * calling pci_enable_msix() and 4903 * pci_resume_msix(). Else the MSIX rewrite 4904 * table quirk will not work as expected. 4905 */ 4906 mte->mte_handlers++; 4907 if (mte->mte_handlers == 1) { 4908 pci_enable_msix(child, rid - 1, mv->mv_address, 4909 mv->mv_data); 4910 pci_unmask_msix(child, rid - 1); 4911 } 4912 } 4913 4914 /* 4915 * Make sure that INTx is disabled if we are using MSI/MSI-X, 4916 * unless the device is affected by PCI_QUIRK_MSI_INTX_BUG, 4917 * in which case we "enable" INTx so MSI/MSI-X actually works. 4918 */ 4919 if (!pci_has_quirk(pci_get_devid(child), 4920 PCI_QUIRK_MSI_INTX_BUG)) 4921 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4922 else 4923 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4924 bad: 4925 if (error) { 4926 (void)bus_generic_teardown_intr(dev, child, irq, 4927 cookie); 4928 return (error); 4929 } 4930 } 4931 *cookiep = cookie; 4932 return (0); 4933 } 4934 4935 int 4936 pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 4937 void *cookie) 4938 { 4939 struct msix_table_entry *mte; 4940 struct resource_list_entry *rle; 4941 struct pci_devinfo *dinfo; 4942 int error, rid; 4943 4944 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE)) 4945 return (EINVAL); 4946 4947 /* If this isn't a direct child, just bail out */ 4948 if (device_get_parent(child) != dev) 4949 return(bus_generic_teardown_intr(dev, child, irq, cookie)); 4950 4951 rid = rman_get_rid(irq); 4952 if (rid == 0) { 4953 /* Mask INTx */ 4954 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4955 } else { 4956 /* 4957 * Check to see if the interrupt is MSI or MSI-X. If so, 4958 * decrement the appropriate handlers count and mask the 4959 * MSI-X message, or disable MSI messages if the count 4960 * drops to 0. 4961 */ 4962 dinfo = device_get_ivars(child); 4963 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); 4964 if (rle->res != irq) 4965 return (EINVAL); 4966 if (dinfo->cfg.msi.msi_alloc > 0) { 4967 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, 4968 ("MSI-X index too high")); 4969 if (dinfo->cfg.msi.msi_handlers == 0) 4970 return (EINVAL); 4971 dinfo->cfg.msi.msi_handlers--; 4972 if (dinfo->cfg.msi.msi_handlers == 0) 4973 pci_disable_msi(child); 4974 } else { 4975 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4976 ("No MSI or MSI-X interrupts allocated")); 4977 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4978 ("MSI-X index too high")); 4979 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4980 if (mte->mte_handlers == 0) 4981 return (EINVAL); 4982 mte->mte_handlers--; 4983 if (mte->mte_handlers == 0) 4984 pci_mask_msix(child, rid - 1); 4985 } 4986 } 4987 error = bus_generic_teardown_intr(dev, child, irq, cookie); 4988 if (rid > 0) 4989 KASSERT(error == 0, 4990 ("%s: generic teardown failed for MSI/MSI-X", __func__)); 4991 return (error); 4992 } 4993 4994 int 4995 pci_print_child(device_t dev, device_t child) 4996 { 4997 struct pci_devinfo *dinfo; 4998 struct resource_list *rl; 4999 int retval = 0; 5000 5001 dinfo = device_get_ivars(child); 5002 rl = &dinfo->resources; 5003 5004 retval += bus_print_child_header(dev, child); 5005 5006 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#jx"); 5007 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 5008 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 5009 if (device_get_flags(dev)) 5010 retval += printf(" flags %#x", device_get_flags(dev)); 5011 5012 retval += printf(" at device %d.%d", pci_get_slot(child), 5013 pci_get_function(child)); 5014 5015 retval += bus_print_child_domain(dev, child); 5016 retval += bus_print_child_footer(dev, child); 5017 5018 return (retval); 5019 } 5020 5021 static const struct 5022 { 5023 int class; 5024 int subclass; 5025 int report; /* 0 = bootverbose, 1 = always */ 5026 const char *desc; 5027 } pci_nomatch_tab[] = { 5028 {PCIC_OLD, -1, 1, "old"}, 5029 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"}, 5030 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"}, 5031 {PCIC_STORAGE, -1, 1, "mass storage"}, 5032 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"}, 5033 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"}, 5034 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"}, 5035 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"}, 5036 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"}, 5037 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"}, 5038 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"}, 5039 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"}, 5040 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"}, 5041 {PCIC_NETWORK, -1, 1, "network"}, 5042 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"}, 5043 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"}, 5044 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"}, 5045 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"}, 5046 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"}, 5047 {PCIC_DISPLAY, -1, 1, "display"}, 5048 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"}, 5049 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"}, 5050 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"}, 5051 {PCIC_MULTIMEDIA, -1, 1, "multimedia"}, 5052 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"}, 5053 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"}, 5054 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"}, 5055 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"}, 5056 {PCIC_MEMORY, -1, 1, "memory"}, 5057 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"}, 5058 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"}, 5059 {PCIC_BRIDGE, -1, 1, "bridge"}, 5060 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"}, 5061 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"}, 5062 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"}, 5063 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"}, 5064 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"}, 5065 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"}, 5066 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"}, 5067 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"}, 5068 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"}, 5069 {PCIC_SIMPLECOMM, -1, 1, "simple comms"}, 5070 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */ 5071 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"}, 5072 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"}, 5073 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"}, 5074 {PCIC_BASEPERIPH, -1, 0, "base peripheral"}, 5075 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"}, 5076 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"}, 5077 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"}, 5078 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"}, 5079 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"}, 5080 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"}, 5081 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"}, 5082 {PCIC_INPUTDEV, -1, 1, "input device"}, 5083 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"}, 5084 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"}, 5085 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"}, 5086 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"}, 5087 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"}, 5088 {PCIC_DOCKING, -1, 1, "docking station"}, 5089 {PCIC_PROCESSOR, -1, 1, "processor"}, 5090 {PCIC_SERIALBUS, -1, 1, "serial bus"}, 5091 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"}, 5092 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"}, 5093 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"}, 5094 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"}, 5095 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"}, 5096 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"}, 5097 {PCIC_WIRELESS, -1, 1, "wireless controller"}, 5098 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"}, 5099 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"}, 5100 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"}, 5101 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"}, 5102 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"}, 5103 {PCIC_SATCOM, -1, 1, "satellite communication"}, 5104 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"}, 5105 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"}, 5106 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"}, 5107 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"}, 5108 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"}, 5109 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"}, 5110 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"}, 5111 {PCIC_DASP, -1, 0, "dasp"}, 5112 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"}, 5113 {PCIC_DASP, PCIS_DASP_PERFCNTRS, 1, "performance counters"}, 5114 {PCIC_DASP, PCIS_DASP_COMM_SYNC, 1, "communication synchronizer"}, 5115 {PCIC_DASP, PCIS_DASP_MGMT_CARD, 1, "signal processing management"}, 5116 {PCIC_INSTRUMENT, -1, 0, "non-essential instrumentation"}, 5117 {0, 0, 0, NULL} 5118 }; 5119 5120 void 5121 pci_probe_nomatch(device_t dev, device_t child) 5122 { 5123 int i, report; 5124 const char *cp, *scp; 5125 char *device; 5126 5127 /* 5128 * Look for a listing for this device in a loaded device database. 5129 */ 5130 report = 1; 5131 if ((device = pci_describe_device(child)) != NULL) { 5132 device_printf(dev, "<%s>", device); 5133 free(device, M_DEVBUF); 5134 } else { 5135 /* 5136 * Scan the class/subclass descriptions for a general 5137 * description. 5138 */ 5139 cp = "unknown"; 5140 scp = NULL; 5141 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 5142 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 5143 if (pci_nomatch_tab[i].subclass == -1) { 5144 cp = pci_nomatch_tab[i].desc; 5145 report = pci_nomatch_tab[i].report; 5146 } else if (pci_nomatch_tab[i].subclass == 5147 pci_get_subclass(child)) { 5148 scp = pci_nomatch_tab[i].desc; 5149 report = pci_nomatch_tab[i].report; 5150 } 5151 } 5152 } 5153 if (report || bootverbose) { 5154 device_printf(dev, "<%s%s%s>", 5155 cp ? cp : "", 5156 ((cp != NULL) && (scp != NULL)) ? ", " : "", 5157 scp ? scp : ""); 5158 } 5159 } 5160 if (report || bootverbose) { 5161 printf(" at device %d.%d (no driver attached)\n", 5162 pci_get_slot(child), pci_get_function(child)); 5163 } 5164 pci_cfg_save(child, device_get_ivars(child), 1); 5165 } 5166 5167 void 5168 pci_child_detached(device_t dev, device_t child) 5169 { 5170 struct pci_devinfo *dinfo; 5171 struct resource_list *rl; 5172 5173 dinfo = device_get_ivars(child); 5174 rl = &dinfo->resources; 5175 5176 /* 5177 * Have to deallocate IRQs before releasing any MSI messages and 5178 * have to release MSI messages before deallocating any memory 5179 * BARs. 5180 */ 5181 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0) 5182 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); 5183 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { 5184 if (dinfo->cfg.msi.msi_alloc != 0) 5185 pci_printf(&dinfo->cfg, "Device leaked %d MSI " 5186 "vectors\n", dinfo->cfg.msi.msi_alloc); 5187 else 5188 pci_printf(&dinfo->cfg, "Device leaked %d MSI-X " 5189 "vectors\n", dinfo->cfg.msix.msix_alloc); 5190 (void)pci_release_msi(child); 5191 } 5192 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0) 5193 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); 5194 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0) 5195 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); 5196 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0) 5197 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); 5198 5199 pci_cfg_save(child, dinfo, 1); 5200 } 5201 5202 /* 5203 * Parse the PCI device database, if loaded, and return a pointer to a 5204 * description of the device. 5205 * 5206 * The database is flat text formatted as follows: 5207 * 5208 * Any line not in a valid format is ignored. 5209 * Lines are terminated with newline '\n' characters. 5210 * 5211 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 5212 * the vendor name. 5213 * 5214 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 5215 * - devices cannot be listed without a corresponding VENDOR line. 5216 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 5217 * another TAB, then the device name. 5218 */ 5219 5220 /* 5221 * Assuming (ptr) points to the beginning of a line in the database, 5222 * return the vendor or device and description of the next entry. 5223 * The value of (vendor) or (device) inappropriate for the entry type 5224 * is set to -1. Returns nonzero at the end of the database. 5225 * 5226 * Note that this is slightly unrobust in the face of corrupt data; 5227 * we attempt to safeguard against this by spamming the end of the 5228 * database with a newline when we initialise. 5229 */ 5230 static int 5231 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 5232 { 5233 char *cp = *ptr; 5234 int left; 5235 5236 *device = -1; 5237 *vendor = -1; 5238 **desc = '\0'; 5239 for (;;) { 5240 left = pci_vendordata_size - (cp - pci_vendordata); 5241 if (left <= 0) { 5242 *ptr = cp; 5243 return(1); 5244 } 5245 5246 /* vendor entry? */ 5247 if (*cp != '\t' && 5248 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 5249 break; 5250 /* device entry? */ 5251 if (*cp == '\t' && 5252 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 5253 break; 5254 5255 /* skip to next line */ 5256 while (*cp != '\n' && left > 0) { 5257 cp++; 5258 left--; 5259 } 5260 if (*cp == '\n') { 5261 cp++; 5262 left--; 5263 } 5264 } 5265 /* skip to next line */ 5266 while (*cp != '\n' && left > 0) { 5267 cp++; 5268 left--; 5269 } 5270 if (*cp == '\n' && left > 0) 5271 cp++; 5272 *ptr = cp; 5273 return(0); 5274 } 5275 5276 static char * 5277 pci_describe_device(device_t dev) 5278 { 5279 int vendor, device; 5280 char *desc, *vp, *dp, *line; 5281 5282 desc = vp = dp = NULL; 5283 5284 /* 5285 * If we have no vendor data, we can't do anything. 5286 */ 5287 if (pci_vendordata == NULL) 5288 goto out; 5289 5290 /* 5291 * Scan the vendor data looking for this device 5292 */ 5293 line = pci_vendordata; 5294 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5295 goto out; 5296 for (;;) { 5297 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 5298 goto out; 5299 if (vendor == pci_get_vendor(dev)) 5300 break; 5301 } 5302 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5303 goto out; 5304 for (;;) { 5305 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 5306 *dp = 0; 5307 break; 5308 } 5309 if (vendor != -1) { 5310 *dp = 0; 5311 break; 5312 } 5313 if (device == pci_get_device(dev)) 5314 break; 5315 } 5316 if (dp[0] == '\0') 5317 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 5318 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 5319 NULL) 5320 sprintf(desc, "%s, %s", vp, dp); 5321 out: 5322 if (vp != NULL) 5323 free(vp, M_DEVBUF); 5324 if (dp != NULL) 5325 free(dp, M_DEVBUF); 5326 return(desc); 5327 } 5328 5329 int 5330 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 5331 { 5332 struct pci_devinfo *dinfo; 5333 pcicfgregs *cfg; 5334 5335 dinfo = device_get_ivars(child); 5336 cfg = &dinfo->cfg; 5337 5338 switch (which) { 5339 case PCI_IVAR_ETHADDR: 5340 /* 5341 * The generic accessor doesn't deal with failure, so 5342 * we set the return value, then return an error. 5343 */ 5344 *((uint8_t **) result) = NULL; 5345 return (EINVAL); 5346 case PCI_IVAR_SUBVENDOR: 5347 *result = cfg->subvendor; 5348 break; 5349 case PCI_IVAR_SUBDEVICE: 5350 *result = cfg->subdevice; 5351 break; 5352 case PCI_IVAR_VENDOR: 5353 *result = cfg->vendor; 5354 break; 5355 case PCI_IVAR_DEVICE: 5356 *result = cfg->device; 5357 break; 5358 case PCI_IVAR_DEVID: 5359 *result = (cfg->device << 16) | cfg->vendor; 5360 break; 5361 case PCI_IVAR_CLASS: 5362 *result = cfg->baseclass; 5363 break; 5364 case PCI_IVAR_SUBCLASS: 5365 *result = cfg->subclass; 5366 break; 5367 case PCI_IVAR_PROGIF: 5368 *result = cfg->progif; 5369 break; 5370 case PCI_IVAR_REVID: 5371 *result = cfg->revid; 5372 break; 5373 case PCI_IVAR_INTPIN: 5374 *result = cfg->intpin; 5375 break; 5376 case PCI_IVAR_IRQ: 5377 *result = cfg->intline; 5378 break; 5379 case PCI_IVAR_DOMAIN: 5380 *result = cfg->domain; 5381 break; 5382 case PCI_IVAR_BUS: 5383 *result = cfg->bus; 5384 break; 5385 case PCI_IVAR_SLOT: 5386 *result = cfg->slot; 5387 break; 5388 case PCI_IVAR_FUNCTION: 5389 *result = cfg->func; 5390 break; 5391 case PCI_IVAR_CMDREG: 5392 *result = cfg->cmdreg; 5393 break; 5394 case PCI_IVAR_CACHELNSZ: 5395 *result = cfg->cachelnsz; 5396 break; 5397 case PCI_IVAR_MINGNT: 5398 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5399 *result = -1; 5400 return (EINVAL); 5401 } 5402 *result = cfg->mingnt; 5403 break; 5404 case PCI_IVAR_MAXLAT: 5405 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5406 *result = -1; 5407 return (EINVAL); 5408 } 5409 *result = cfg->maxlat; 5410 break; 5411 case PCI_IVAR_LATTIMER: 5412 *result = cfg->lattimer; 5413 break; 5414 default: 5415 return (ENOENT); 5416 } 5417 return (0); 5418 } 5419 5420 int 5421 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 5422 { 5423 struct pci_devinfo *dinfo; 5424 5425 dinfo = device_get_ivars(child); 5426 5427 switch (which) { 5428 case PCI_IVAR_INTPIN: 5429 dinfo->cfg.intpin = value; 5430 return (0); 5431 case PCI_IVAR_ETHADDR: 5432 case PCI_IVAR_SUBVENDOR: 5433 case PCI_IVAR_SUBDEVICE: 5434 case PCI_IVAR_VENDOR: 5435 case PCI_IVAR_DEVICE: 5436 case PCI_IVAR_DEVID: 5437 case PCI_IVAR_CLASS: 5438 case PCI_IVAR_SUBCLASS: 5439 case PCI_IVAR_PROGIF: 5440 case PCI_IVAR_REVID: 5441 case PCI_IVAR_IRQ: 5442 case PCI_IVAR_DOMAIN: 5443 case PCI_IVAR_BUS: 5444 case PCI_IVAR_SLOT: 5445 case PCI_IVAR_FUNCTION: 5446 return (EINVAL); /* disallow for now */ 5447 5448 default: 5449 return (ENOENT); 5450 } 5451 } 5452 5453 #include "opt_ddb.h" 5454 #ifdef DDB 5455 #include <ddb/ddb.h> 5456 #include <sys/cons.h> 5457 5458 /* 5459 * List resources based on pci map registers, used for within ddb 5460 */ 5461 5462 DB_SHOW_COMMAND_FLAGS(pciregs, db_pci_dump, DB_CMD_MEMSAFE) 5463 { 5464 struct pci_devinfo *dinfo; 5465 struct devlist *devlist_head; 5466 struct pci_conf *p; 5467 const char *name; 5468 int i, error, none_count; 5469 5470 none_count = 0; 5471 /* get the head of the device queue */ 5472 devlist_head = &pci_devq; 5473 5474 /* 5475 * Go through the list of devices and print out devices 5476 */ 5477 for (error = 0, i = 0, 5478 dinfo = STAILQ_FIRST(devlist_head); 5479 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 5480 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 5481 /* Populate pd_name and pd_unit */ 5482 name = NULL; 5483 if (dinfo->cfg.dev) 5484 name = device_get_name(dinfo->cfg.dev); 5485 5486 p = &dinfo->conf; 5487 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x " 5488 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 5489 (name && *name) ? name : "none", 5490 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 5491 none_count++, 5492 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, 5493 p->pc_sel.pc_func, (p->pc_class << 16) | 5494 (p->pc_subclass << 8) | p->pc_progif, 5495 (p->pc_subdevice << 16) | p->pc_subvendor, 5496 (p->pc_device << 16) | p->pc_vendor, 5497 p->pc_revid, p->pc_hdr); 5498 } 5499 } 5500 #endif /* DDB */ 5501 5502 struct resource * 5503 pci_reserve_map(device_t dev, device_t child, int type, int *rid, 5504 rman_res_t start, rman_res_t end, rman_res_t count, u_int num, 5505 u_int flags) 5506 { 5507 struct pci_devinfo *dinfo = device_get_ivars(child); 5508 struct resource_list *rl = &dinfo->resources; 5509 struct resource *res; 5510 struct pci_map *pm; 5511 uint16_t cmd; 5512 pci_addr_t map, testval; 5513 int mapsize; 5514 5515 res = NULL; 5516 5517 /* If rid is managed by EA, ignore it */ 5518 if (pci_ea_is_enabled(child, *rid)) 5519 goto out; 5520 5521 pm = pci_find_bar(child, *rid); 5522 if (pm != NULL) { 5523 /* This is a BAR that we failed to allocate earlier. */ 5524 mapsize = pm->pm_size; 5525 map = pm->pm_value; 5526 } else { 5527 /* 5528 * Weed out the bogons, and figure out how large the 5529 * BAR/map is. BARs that read back 0 here are bogus 5530 * and unimplemented. Note: atapci in legacy mode are 5531 * special and handled elsewhere in the code. If you 5532 * have a atapci device in legacy mode and it fails 5533 * here, that other code is broken. 5534 */ 5535 pci_read_bar(child, *rid, &map, &testval, NULL); 5536 5537 /* 5538 * Determine the size of the BAR and ignore BARs with a size 5539 * of 0. Device ROM BARs use a different mask value. 5540 */ 5541 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) 5542 mapsize = pci_romsize(testval); 5543 else 5544 mapsize = pci_mapsize(testval); 5545 if (mapsize == 0) 5546 goto out; 5547 pm = pci_add_bar(child, *rid, map, mapsize); 5548 } 5549 5550 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { 5551 if (type != SYS_RES_MEMORY) { 5552 if (bootverbose) 5553 device_printf(dev, 5554 "child %s requested type %d for rid %#x," 5555 " but the BAR says it is an memio\n", 5556 device_get_nameunit(child), type, *rid); 5557 goto out; 5558 } 5559 } else { 5560 if (type != SYS_RES_IOPORT) { 5561 if (bootverbose) 5562 device_printf(dev, 5563 "child %s requested type %d for rid %#x," 5564 " but the BAR says it is an ioport\n", 5565 device_get_nameunit(child), type, *rid); 5566 goto out; 5567 } 5568 } 5569 5570 /* 5571 * For real BARs, we need to override the size that 5572 * the driver requests, because that's what the BAR 5573 * actually uses and we would otherwise have a 5574 * situation where we might allocate the excess to 5575 * another driver, which won't work. 5576 */ 5577 count = ((pci_addr_t)1 << mapsize) * num; 5578 if (RF_ALIGNMENT(flags) < mapsize) 5579 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 5580 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH)) 5581 flags |= RF_PREFETCHABLE; 5582 5583 /* 5584 * Allocate enough resource, and then write back the 5585 * appropriate BAR for that resource. 5586 */ 5587 resource_list_add(rl, type, *rid, start, end, count); 5588 res = resource_list_reserve(rl, dev, child, type, rid, start, end, 5589 count, flags & ~RF_ACTIVE); 5590 if (res == NULL) { 5591 resource_list_delete(rl, type, *rid); 5592 device_printf(child, 5593 "%#jx bytes of rid %#x res %d failed (%#jx, %#jx).\n", 5594 count, *rid, type, start, end); 5595 goto out; 5596 } 5597 if (bootverbose) 5598 device_printf(child, 5599 "Lazy allocation of %#jx bytes rid %#x type %d at %#jx\n", 5600 count, *rid, type, rman_get_start(res)); 5601 5602 /* Disable decoding via the CMD register before updating the BAR */ 5603 cmd = pci_read_config(child, PCIR_COMMAND, 2); 5604 pci_write_config(child, PCIR_COMMAND, 5605 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 5606 5607 map = rman_get_start(res); 5608 pci_write_bar(child, pm, map); 5609 5610 /* Restore the original value of the CMD register */ 5611 pci_write_config(child, PCIR_COMMAND, cmd, 2); 5612 out: 5613 return (res); 5614 } 5615 5616 struct resource * 5617 pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid, 5618 rman_res_t start, rman_res_t end, rman_res_t count, u_long num, 5619 u_int flags) 5620 { 5621 struct pci_devinfo *dinfo; 5622 struct resource_list *rl; 5623 struct resource_list_entry *rle; 5624 struct resource *res; 5625 pcicfgregs *cfg; 5626 5627 /* 5628 * Perform lazy resource allocation 5629 */ 5630 dinfo = device_get_ivars(child); 5631 rl = &dinfo->resources; 5632 cfg = &dinfo->cfg; 5633 switch (type) { 5634 case PCI_RES_BUS: 5635 return (pci_alloc_secbus(dev, child, rid, start, end, count, 5636 flags)); 5637 case SYS_RES_IRQ: 5638 /* 5639 * Can't alloc legacy interrupt once MSI messages have 5640 * been allocated. 5641 */ 5642 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 5643 cfg->msix.msix_alloc > 0)) 5644 return (NULL); 5645 5646 /* 5647 * If the child device doesn't have an interrupt 5648 * routed and is deserving of an interrupt, try to 5649 * assign it one. 5650 */ 5651 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 5652 (cfg->intpin != 0)) 5653 pci_assign_interrupt(dev, child, 0); 5654 break; 5655 case SYS_RES_IOPORT: 5656 case SYS_RES_MEMORY: 5657 /* 5658 * PCI-PCI bridge I/O window resources are not BARs. 5659 * For those allocations just pass the request up the 5660 * tree. 5661 */ 5662 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { 5663 switch (*rid) { 5664 case PCIR_IOBASEL_1: 5665 case PCIR_MEMBASE_1: 5666 case PCIR_PMBASEL_1: 5667 /* 5668 * XXX: Should we bother creating a resource 5669 * list entry? 5670 */ 5671 return (bus_generic_alloc_resource(dev, child, 5672 type, rid, start, end, count, flags)); 5673 } 5674 } 5675 /* Reserve resources for this BAR if needed. */ 5676 rle = resource_list_find(rl, type, *rid); 5677 if (rle == NULL) { 5678 res = pci_reserve_map(dev, child, type, rid, start, end, 5679 count, num, flags); 5680 if (res == NULL) 5681 return (NULL); 5682 } 5683 } 5684 return (resource_list_alloc(rl, dev, child, type, rid, 5685 start, end, count, flags)); 5686 } 5687 5688 struct resource * 5689 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 5690 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 5691 { 5692 #ifdef PCI_IOV 5693 struct pci_devinfo *dinfo; 5694 #endif 5695 5696 if (device_get_parent(child) != dev) 5697 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 5698 type, rid, start, end, count, flags)); 5699 5700 #ifdef PCI_IOV 5701 dinfo = device_get_ivars(child); 5702 if (dinfo->cfg.flags & PCICFG_VF) { 5703 switch (type) { 5704 /* VFs can't have I/O BARs. */ 5705 case SYS_RES_IOPORT: 5706 return (NULL); 5707 case SYS_RES_MEMORY: 5708 return (pci_vf_alloc_mem_resource(dev, child, rid, 5709 start, end, count, flags)); 5710 } 5711 5712 /* Fall through for other types of resource allocations. */ 5713 } 5714 #endif 5715 5716 return (pci_alloc_multi_resource(dev, child, type, rid, start, end, 5717 count, 1, flags)); 5718 } 5719 5720 int 5721 pci_release_resource(device_t dev, device_t child, struct resource *r) 5722 { 5723 struct pci_devinfo *dinfo; 5724 struct resource_list *rl; 5725 pcicfgregs *cfg __unused; 5726 5727 if (device_get_parent(child) != dev) 5728 return (bus_generic_release_resource(dev, child, r)); 5729 5730 dinfo = device_get_ivars(child); 5731 cfg = &dinfo->cfg; 5732 5733 #ifdef PCI_IOV 5734 if (cfg->flags & PCICFG_VF) { 5735 switch (rman_get_type(r)) { 5736 /* VFs can't have I/O BARs. */ 5737 case SYS_RES_IOPORT: 5738 return (EDOOFUS); 5739 case SYS_RES_MEMORY: 5740 return (pci_vf_release_mem_resource(dev, child, r)); 5741 } 5742 5743 /* Fall through for other types of resource allocations. */ 5744 } 5745 #endif 5746 5747 /* 5748 * PCI-PCI bridge I/O window resources are not BARs. For 5749 * those allocations just pass the request up the tree. 5750 */ 5751 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && 5752 (rman_get_type(r) == SYS_RES_IOPORT || 5753 rman_get_type(r) == SYS_RES_MEMORY)) { 5754 switch (rman_get_rid(r)) { 5755 case PCIR_IOBASEL_1: 5756 case PCIR_MEMBASE_1: 5757 case PCIR_PMBASEL_1: 5758 return (bus_generic_release_resource(dev, child, r)); 5759 } 5760 } 5761 5762 rl = &dinfo->resources; 5763 return (resource_list_release(rl, dev, child, r)); 5764 } 5765 5766 int 5767 pci_activate_resource(device_t dev, device_t child, struct resource *r) 5768 { 5769 struct pci_devinfo *dinfo; 5770 int error, rid, type; 5771 5772 if (device_get_parent(child) != dev) 5773 return (bus_generic_activate_resource(dev, child, r)); 5774 5775 dinfo = device_get_ivars(child); 5776 #ifdef PCI_IOV 5777 if (dinfo->cfg.flags & PCICFG_VF) { 5778 switch (rman_get_type(r)) { 5779 /* VFs can't have I/O BARs. */ 5780 case SYS_RES_IOPORT: 5781 error = EINVAL; 5782 break; 5783 case SYS_RES_MEMORY: 5784 error = pci_vf_activate_mem_resource(dev, child, r); 5785 break; 5786 default: 5787 error = bus_generic_activate_resource(dev, child, r); 5788 break; 5789 } 5790 } else 5791 #endif 5792 error = bus_generic_activate_resource(dev, child, r); 5793 if (error) 5794 return (error); 5795 5796 rid = rman_get_rid(r); 5797 type = rman_get_type(r); 5798 5799 /* Device ROMs need their decoding explicitly enabled. */ 5800 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5801 pci_write_bar(child, pci_find_bar(child, rid), 5802 rman_get_start(r) | PCIM_BIOS_ENABLE); 5803 5804 /* Enable decoding in the command register when activating BARs. */ 5805 switch (type) { 5806 case SYS_RES_IOPORT: 5807 case SYS_RES_MEMORY: 5808 error = PCI_ENABLE_IO(dev, child, type); 5809 break; 5810 } 5811 return (error); 5812 } 5813 5814 int 5815 pci_deactivate_resource(device_t dev, device_t child, struct resource *r) 5816 { 5817 struct pci_devinfo *dinfo; 5818 int error, rid, type; 5819 5820 if (device_get_parent(child) != dev) 5821 return (bus_generic_deactivate_resource(dev, child, r)); 5822 5823 dinfo = device_get_ivars(child); 5824 #ifdef PCI_IOV 5825 if (dinfo->cfg.flags & PCICFG_VF) { 5826 switch (rman_get_type(r)) { 5827 /* VFs can't have I/O BARs. */ 5828 case SYS_RES_IOPORT: 5829 error = EINVAL; 5830 break; 5831 case SYS_RES_MEMORY: 5832 error = pci_vf_deactivate_mem_resource(dev, child, r); 5833 break; 5834 default: 5835 error = bus_generic_deactivate_resource(dev, child, r); 5836 break; 5837 } 5838 } else 5839 #endif 5840 error = bus_generic_deactivate_resource(dev, child, r); 5841 if (error) 5842 return (error); 5843 5844 /* Disable decoding for device ROMs. */ 5845 rid = rman_get_rid(r); 5846 type = rman_get_type(r); 5847 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5848 pci_write_bar(child, pci_find_bar(child, rid), 5849 rman_get_start(r)); 5850 return (0); 5851 } 5852 5853 int 5854 pci_adjust_resource(device_t dev, device_t child, struct resource *r, 5855 rman_res_t start, rman_res_t end) 5856 { 5857 #ifdef PCI_IOV 5858 struct pci_devinfo *dinfo; 5859 5860 if (device_get_parent(child) != dev) 5861 return (bus_generic_adjust_resource(dev, child, r, start, 5862 end)); 5863 5864 dinfo = device_get_ivars(child); 5865 if (dinfo->cfg.flags & PCICFG_VF) { 5866 switch (rman_get_type(r)) { 5867 /* VFs can't have I/O BARs. */ 5868 case SYS_RES_IOPORT: 5869 return (EINVAL); 5870 case SYS_RES_MEMORY: 5871 return (pci_vf_adjust_mem_resource(dev, child, r, 5872 start, end)); 5873 } 5874 5875 /* Fall through for other types of resource allocations. */ 5876 } 5877 #endif 5878 5879 return (bus_generic_adjust_resource(dev, child, r, start, end)); 5880 } 5881 5882 int 5883 pci_map_resource(device_t dev, device_t child, struct resource *r, 5884 struct resource_map_request *argsp, struct resource_map *map) 5885 { 5886 #ifdef PCI_IOV 5887 struct pci_devinfo *dinfo; 5888 5889 if (device_get_parent(child) != dev) 5890 return (bus_generic_map_resource(dev, child, r, argsp, 5891 map)); 5892 5893 dinfo = device_get_ivars(child); 5894 if (dinfo->cfg.flags & PCICFG_VF) { 5895 switch (rman_get_type(r)) { 5896 /* VFs can't have I/O BARs. */ 5897 case SYS_RES_IOPORT: 5898 return (EINVAL); 5899 case SYS_RES_MEMORY: 5900 return (pci_vf_map_mem_resource(dev, child, r, argsp, 5901 map)); 5902 } 5903 5904 /* Fall through for other types of resource allocations. */ 5905 } 5906 #endif 5907 5908 return (bus_generic_map_resource(dev, child, r, argsp, map)); 5909 } 5910 5911 int 5912 pci_unmap_resource(device_t dev, device_t child, struct resource *r, 5913 struct resource_map *map) 5914 { 5915 #ifdef PCI_IOV 5916 struct pci_devinfo *dinfo; 5917 5918 if (device_get_parent(child) != dev) 5919 return (bus_generic_unmap_resource(dev, child, r, map)); 5920 5921 dinfo = device_get_ivars(child); 5922 if (dinfo->cfg.flags & PCICFG_VF) { 5923 switch (rman_get_type(r)) { 5924 /* VFs can't have I/O BARs. */ 5925 case SYS_RES_IOPORT: 5926 return (EINVAL); 5927 case SYS_RES_MEMORY: 5928 return (pci_vf_unmap_mem_resource(dev, child, r, map)); 5929 } 5930 5931 /* Fall through for other types of resource allocations. */ 5932 } 5933 #endif 5934 5935 return (bus_generic_unmap_resource(dev, child, r, map)); 5936 } 5937 5938 void 5939 pci_child_deleted(device_t dev, device_t child) 5940 { 5941 struct resource_list_entry *rle; 5942 struct resource_list *rl; 5943 struct pci_devinfo *dinfo; 5944 5945 dinfo = device_get_ivars(child); 5946 rl = &dinfo->resources; 5947 5948 EVENTHANDLER_INVOKE(pci_delete_device, child); 5949 5950 /* Turn off access to resources we're about to free */ 5951 if (bus_child_present(child) != 0) { 5952 pci_write_config(child, PCIR_COMMAND, pci_read_config(child, 5953 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2); 5954 5955 pci_disable_busmaster(child); 5956 } 5957 5958 /* Free all allocated resources */ 5959 STAILQ_FOREACH(rle, rl, link) { 5960 if (rle->res) { 5961 if (rman_get_flags(rle->res) & RF_ACTIVE || 5962 resource_list_busy(rl, rle->type, rle->rid)) { 5963 pci_printf(&dinfo->cfg, 5964 "Resource still owned, oops. " 5965 "(type=%d, rid=%d, addr=%lx)\n", 5966 rle->type, rle->rid, 5967 rman_get_start(rle->res)); 5968 bus_release_resource(child, rle->type, rle->rid, 5969 rle->res); 5970 } 5971 resource_list_unreserve(rl, dev, child, rle->type, 5972 rle->rid); 5973 } 5974 } 5975 resource_list_free(rl); 5976 5977 pci_freecfg(dinfo); 5978 } 5979 5980 void 5981 pci_delete_resource(device_t dev, device_t child, int type, int rid) 5982 { 5983 struct pci_devinfo *dinfo; 5984 struct resource_list *rl; 5985 struct resource_list_entry *rle; 5986 5987 if (device_get_parent(child) != dev) 5988 return; 5989 5990 dinfo = device_get_ivars(child); 5991 rl = &dinfo->resources; 5992 rle = resource_list_find(rl, type, rid); 5993 if (rle == NULL) 5994 return; 5995 5996 if (rle->res) { 5997 if (rman_get_flags(rle->res) & RF_ACTIVE || 5998 resource_list_busy(rl, type, rid)) { 5999 device_printf(dev, "delete_resource: " 6000 "Resource still owned by child, oops. " 6001 "(type=%d, rid=%d, addr=%jx)\n", 6002 type, rid, rman_get_start(rle->res)); 6003 return; 6004 } 6005 resource_list_unreserve(rl, dev, child, type, rid); 6006 } 6007 resource_list_delete(rl, type, rid); 6008 } 6009 6010 struct resource_list * 6011 pci_get_resource_list (device_t dev, device_t child) 6012 { 6013 struct pci_devinfo *dinfo = device_get_ivars(child); 6014 6015 return (&dinfo->resources); 6016 } 6017 6018 #ifdef IOMMU 6019 bus_dma_tag_t 6020 pci_get_dma_tag(device_t bus, device_t dev) 6021 { 6022 bus_dma_tag_t tag; 6023 struct pci_softc *sc; 6024 6025 if (device_get_parent(dev) == bus) { 6026 /* try iommu and return if it works */ 6027 tag = iommu_get_dma_tag(bus, dev); 6028 } else 6029 tag = NULL; 6030 if (tag == NULL) { 6031 sc = device_get_softc(bus); 6032 tag = sc->sc_dma_tag; 6033 } 6034 return (tag); 6035 } 6036 #else 6037 bus_dma_tag_t 6038 pci_get_dma_tag(device_t bus, device_t dev) 6039 { 6040 struct pci_softc *sc = device_get_softc(bus); 6041 6042 return (sc->sc_dma_tag); 6043 } 6044 #endif 6045 6046 uint32_t 6047 pci_read_config_method(device_t dev, device_t child, int reg, int width) 6048 { 6049 struct pci_devinfo *dinfo = device_get_ivars(child); 6050 pcicfgregs *cfg = &dinfo->cfg; 6051 6052 #ifdef PCI_IOV 6053 /* 6054 * SR-IOV VFs don't implement the VID or DID registers, so we have to 6055 * emulate them here. 6056 */ 6057 if (cfg->flags & PCICFG_VF) { 6058 if (reg == PCIR_VENDOR) { 6059 switch (width) { 6060 case 4: 6061 return (cfg->device << 16 | cfg->vendor); 6062 case 2: 6063 return (cfg->vendor); 6064 case 1: 6065 return (cfg->vendor & 0xff); 6066 default: 6067 return (0xffffffff); 6068 } 6069 } else if (reg == PCIR_DEVICE) { 6070 switch (width) { 6071 /* Note that an unaligned 4-byte read is an error. */ 6072 case 2: 6073 return (cfg->device); 6074 case 1: 6075 return (cfg->device & 0xff); 6076 default: 6077 return (0xffffffff); 6078 } 6079 } 6080 } 6081 #endif 6082 6083 return (PCIB_READ_CONFIG(device_get_parent(dev), 6084 cfg->bus, cfg->slot, cfg->func, reg, width)); 6085 } 6086 6087 void 6088 pci_write_config_method(device_t dev, device_t child, int reg, 6089 uint32_t val, int width) 6090 { 6091 struct pci_devinfo *dinfo = device_get_ivars(child); 6092 pcicfgregs *cfg = &dinfo->cfg; 6093 6094 PCIB_WRITE_CONFIG(device_get_parent(dev), 6095 cfg->bus, cfg->slot, cfg->func, reg, val, width); 6096 } 6097 6098 int 6099 pci_child_location_method(device_t dev, device_t child, struct sbuf *sb) 6100 { 6101 6102 sbuf_printf(sb, "slot=%d function=%d dbsf=pci%d:%d:%d:%d", 6103 pci_get_slot(child), pci_get_function(child), pci_get_domain(child), 6104 pci_get_bus(child), pci_get_slot(child), pci_get_function(child)); 6105 return (0); 6106 } 6107 6108 int 6109 pci_child_pnpinfo_method(device_t dev, device_t child, struct sbuf *sb) 6110 { 6111 struct pci_devinfo *dinfo; 6112 pcicfgregs *cfg; 6113 6114 dinfo = device_get_ivars(child); 6115 cfg = &dinfo->cfg; 6116 sbuf_printf(sb, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 6117 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 6118 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 6119 cfg->progif); 6120 return (0); 6121 } 6122 6123 int 6124 pci_get_device_path_method(device_t bus, device_t child, const char *locator, 6125 struct sbuf *sb) 6126 { 6127 device_t parent = device_get_parent(bus); 6128 int rv; 6129 6130 if (strcmp(locator, BUS_LOCATOR_UEFI) == 0) { 6131 rv = bus_generic_get_device_path(parent, bus, locator, sb); 6132 if (rv == 0) { 6133 sbuf_printf(sb, "/Pci(0x%x,0x%x)", pci_get_slot(child), 6134 pci_get_function(child)); 6135 } 6136 return (0); 6137 } 6138 return (bus_generic_get_device_path(bus, child, locator, sb)); 6139 } 6140 6141 int 6142 pci_assign_interrupt_method(device_t dev, device_t child) 6143 { 6144 struct pci_devinfo *dinfo = device_get_ivars(child); 6145 pcicfgregs *cfg = &dinfo->cfg; 6146 6147 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 6148 cfg->intpin)); 6149 } 6150 6151 static void 6152 pci_lookup(void *arg, const char *name, device_t *dev) 6153 { 6154 long val; 6155 char *end; 6156 int domain, bus, slot, func; 6157 6158 if (*dev != NULL) 6159 return; 6160 6161 /* 6162 * Accept pciconf-style selectors of either pciD:B:S:F or 6163 * pciB:S:F. In the latter case, the domain is assumed to 6164 * be zero. 6165 */ 6166 if (strncmp(name, "pci", 3) != 0) 6167 return; 6168 val = strtol(name + 3, &end, 10); 6169 if (val < 0 || val > INT_MAX || *end != ':') 6170 return; 6171 domain = val; 6172 val = strtol(end + 1, &end, 10); 6173 if (val < 0 || val > INT_MAX || *end != ':') 6174 return; 6175 bus = val; 6176 val = strtol(end + 1, &end, 10); 6177 if (val < 0 || val > INT_MAX) 6178 return; 6179 slot = val; 6180 if (*end == ':') { 6181 val = strtol(end + 1, &end, 10); 6182 if (val < 0 || val > INT_MAX || *end != '\0') 6183 return; 6184 func = val; 6185 } else if (*end == '\0') { 6186 func = slot; 6187 slot = bus; 6188 bus = domain; 6189 domain = 0; 6190 } else 6191 return; 6192 6193 if (domain > PCI_DOMAINMAX || bus > PCI_BUSMAX || slot > PCI_SLOTMAX || 6194 func > PCIE_ARI_FUNCMAX || (slot != 0 && func > PCI_FUNCMAX)) 6195 return; 6196 6197 *dev = pci_find_dbsf(domain, bus, slot, func); 6198 } 6199 6200 static int 6201 pci_modevent(module_t mod, int what, void *arg) 6202 { 6203 static struct cdev *pci_cdev; 6204 static eventhandler_tag tag; 6205 6206 switch (what) { 6207 case MOD_LOAD: 6208 STAILQ_INIT(&pci_devq); 6209 pci_generation = 0; 6210 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 6211 "pci"); 6212 pci_load_vendor_data(); 6213 tag = EVENTHANDLER_REGISTER(dev_lookup, pci_lookup, NULL, 6214 1000); 6215 break; 6216 6217 case MOD_UNLOAD: 6218 if (tag != NULL) 6219 EVENTHANDLER_DEREGISTER(dev_lookup, tag); 6220 destroy_dev(pci_cdev); 6221 break; 6222 } 6223 6224 return (0); 6225 } 6226 6227 static void 6228 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo) 6229 { 6230 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2) 6231 struct pcicfg_pcie *cfg; 6232 int version, pos; 6233 6234 cfg = &dinfo->cfg.pcie; 6235 pos = cfg->pcie_location; 6236 6237 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6238 6239 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); 6240 6241 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6242 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6243 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6244 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); 6245 6246 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6247 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6248 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6249 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); 6250 6251 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6252 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6253 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); 6254 6255 if (version > 1) { 6256 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); 6257 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); 6258 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); 6259 } 6260 #undef WREG 6261 } 6262 6263 static void 6264 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo) 6265 { 6266 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 6267 dinfo->cfg.pcix.pcix_command, 2); 6268 } 6269 6270 void 6271 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 6272 { 6273 6274 /* 6275 * Restore the device to full power mode. We must do this 6276 * before we restore the registers because moving from D3 to 6277 * D0 will cause the chip's BARs and some other registers to 6278 * be reset to some unknown power on reset values. Cut down 6279 * the noise on boot by doing nothing if we are already in 6280 * state D0. 6281 */ 6282 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) 6283 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6284 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 6285 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 6286 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 6287 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 6288 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 6289 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 6290 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6291 case PCIM_HDRTYPE_NORMAL: 6292 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 6293 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 6294 break; 6295 case PCIM_HDRTYPE_BRIDGE: 6296 pci_write_config(dev, PCIR_SECLAT_1, 6297 dinfo->cfg.bridge.br_seclat, 1); 6298 pci_write_config(dev, PCIR_SUBBUS_1, 6299 dinfo->cfg.bridge.br_subbus, 1); 6300 pci_write_config(dev, PCIR_SECBUS_1, 6301 dinfo->cfg.bridge.br_secbus, 1); 6302 pci_write_config(dev, PCIR_PRIBUS_1, 6303 dinfo->cfg.bridge.br_pribus, 1); 6304 pci_write_config(dev, PCIR_BRIDGECTL_1, 6305 dinfo->cfg.bridge.br_control, 2); 6306 break; 6307 case PCIM_HDRTYPE_CARDBUS: 6308 pci_write_config(dev, PCIR_SECLAT_2, 6309 dinfo->cfg.bridge.br_seclat, 1); 6310 pci_write_config(dev, PCIR_SUBBUS_2, 6311 dinfo->cfg.bridge.br_subbus, 1); 6312 pci_write_config(dev, PCIR_SECBUS_2, 6313 dinfo->cfg.bridge.br_secbus, 1); 6314 pci_write_config(dev, PCIR_PRIBUS_2, 6315 dinfo->cfg.bridge.br_pribus, 1); 6316 pci_write_config(dev, PCIR_BRIDGECTL_2, 6317 dinfo->cfg.bridge.br_control, 2); 6318 break; 6319 } 6320 pci_restore_bars(dev); 6321 6322 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE) 6323 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 6324 6325 /* 6326 * Restore extended capabilities for PCI-Express and PCI-X 6327 */ 6328 if (dinfo->cfg.pcie.pcie_location != 0) 6329 pci_cfg_restore_pcie(dev, dinfo); 6330 if (dinfo->cfg.pcix.pcix_location != 0) 6331 pci_cfg_restore_pcix(dev, dinfo); 6332 6333 /* Restore MSI and MSI-X configurations if they are present. */ 6334 if (dinfo->cfg.msi.msi_location != 0) 6335 pci_resume_msi(dev); 6336 if (dinfo->cfg.msix.msix_location != 0) 6337 pci_resume_msix(dev); 6338 6339 #ifdef PCI_IOV 6340 if (dinfo->cfg.iov != NULL) 6341 pci_iov_cfg_restore(dev, dinfo); 6342 #endif 6343 } 6344 6345 static void 6346 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo) 6347 { 6348 #define RREG(n) pci_read_config(dev, pos + (n), 2) 6349 struct pcicfg_pcie *cfg; 6350 int version, pos; 6351 6352 cfg = &dinfo->cfg.pcie; 6353 pos = cfg->pcie_location; 6354 6355 cfg->pcie_flags = RREG(PCIER_FLAGS); 6356 6357 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6358 6359 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); 6360 6361 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6362 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6363 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6364 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); 6365 6366 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6367 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6368 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6369 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); 6370 6371 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6372 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6373 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); 6374 6375 if (version > 1) { 6376 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); 6377 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); 6378 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); 6379 } 6380 #undef RREG 6381 } 6382 6383 static void 6384 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo) 6385 { 6386 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, 6387 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); 6388 } 6389 6390 void 6391 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 6392 { 6393 uint32_t cls; 6394 int ps; 6395 6396 /* 6397 * Some drivers apparently write to these registers w/o updating our 6398 * cached copy. No harm happens if we update the copy, so do so here 6399 * so we can restore them. The COMMAND register is modified by the 6400 * bus w/o updating the cache. This should represent the normally 6401 * writable portion of the 'defined' part of type 0/1/2 headers. 6402 */ 6403 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 6404 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 6405 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 6406 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 6407 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 6408 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 6409 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 6410 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 6411 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 6412 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 6413 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 6414 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6415 case PCIM_HDRTYPE_NORMAL: 6416 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 6417 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 6418 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 6419 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 6420 break; 6421 case PCIM_HDRTYPE_BRIDGE: 6422 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6423 PCIR_SECLAT_1, 1); 6424 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6425 PCIR_SUBBUS_1, 1); 6426 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6427 PCIR_SECBUS_1, 1); 6428 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6429 PCIR_PRIBUS_1, 1); 6430 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6431 PCIR_BRIDGECTL_1, 2); 6432 break; 6433 case PCIM_HDRTYPE_CARDBUS: 6434 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6435 PCIR_SECLAT_2, 1); 6436 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6437 PCIR_SUBBUS_2, 1); 6438 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6439 PCIR_SECBUS_2, 1); 6440 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6441 PCIR_PRIBUS_2, 1); 6442 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6443 PCIR_BRIDGECTL_2, 2); 6444 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2); 6445 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2); 6446 break; 6447 } 6448 6449 if (dinfo->cfg.pcie.pcie_location != 0) 6450 pci_cfg_save_pcie(dev, dinfo); 6451 6452 if (dinfo->cfg.pcix.pcix_location != 0) 6453 pci_cfg_save_pcix(dev, dinfo); 6454 6455 #ifdef PCI_IOV 6456 if (dinfo->cfg.iov != NULL) 6457 pci_iov_cfg_save(dev, dinfo); 6458 #endif 6459 6460 /* 6461 * don't set the state for display devices, base peripherals and 6462 * memory devices since bad things happen when they are powered down. 6463 * We should (a) have drivers that can easily detach and (b) use 6464 * generic drivers for these devices so that some device actually 6465 * attaches. We need to make sure that when we implement (a) we don't 6466 * power the device down on a reattach. 6467 */ 6468 cls = pci_get_class(dev); 6469 if (!setstate) 6470 return; 6471 switch (pci_do_power_nodriver) 6472 { 6473 case 0: /* NO powerdown at all */ 6474 return; 6475 case 1: /* Conservative about what to power down */ 6476 if (cls == PCIC_STORAGE) 6477 return; 6478 /*FALLTHROUGH*/ 6479 case 2: /* Aggressive about what to power down */ 6480 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 6481 cls == PCIC_BASEPERIPH) 6482 return; 6483 /*FALLTHROUGH*/ 6484 case 3: /* Power down everything */ 6485 break; 6486 } 6487 /* 6488 * PCI spec says we can only go into D3 state from D0 state. 6489 * Transition from D[12] into D0 before going to D3 state. 6490 */ 6491 ps = pci_get_powerstate(dev); 6492 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6493 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6494 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 6495 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6496 } 6497 6498 /* Wrapper APIs suitable for device driver use. */ 6499 void 6500 pci_save_state(device_t dev) 6501 { 6502 struct pci_devinfo *dinfo; 6503 6504 dinfo = device_get_ivars(dev); 6505 pci_cfg_save(dev, dinfo, 0); 6506 } 6507 6508 void 6509 pci_restore_state(device_t dev) 6510 { 6511 struct pci_devinfo *dinfo; 6512 6513 dinfo = device_get_ivars(dev); 6514 pci_cfg_restore(dev, dinfo); 6515 } 6516 6517 static int 6518 pci_get_id_method(device_t dev, device_t child, enum pci_id_type type, 6519 uintptr_t *id) 6520 { 6521 6522 return (PCIB_GET_ID(device_get_parent(dev), child, type, id)); 6523 } 6524 6525 /* Find the upstream port of a given PCI device in a root complex. */ 6526 device_t 6527 pci_find_pcie_root_port(device_t dev) 6528 { 6529 struct pci_devinfo *dinfo; 6530 devclass_t pci_class; 6531 device_t pcib, bus; 6532 6533 pci_class = devclass_find("pci"); 6534 KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class, 6535 ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); 6536 6537 /* 6538 * Walk the bridge hierarchy until we find a PCI-e root 6539 * port or a non-PCI device. 6540 */ 6541 for (;;) { 6542 bus = device_get_parent(dev); 6543 KASSERT(bus != NULL, ("%s: null parent of %s", __func__, 6544 device_get_nameunit(dev))); 6545 6546 pcib = device_get_parent(bus); 6547 KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__, 6548 device_get_nameunit(bus))); 6549 6550 /* 6551 * pcib's parent must be a PCI bus for this to be a 6552 * PCI-PCI bridge. 6553 */ 6554 if (device_get_devclass(device_get_parent(pcib)) != pci_class) 6555 return (NULL); 6556 6557 dinfo = device_get_ivars(pcib); 6558 if (dinfo->cfg.pcie.pcie_location != 0 && 6559 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) 6560 return (pcib); 6561 6562 dev = pcib; 6563 } 6564 } 6565 6566 /* 6567 * Wait for pending transactions to complete on a PCI-express function. 6568 * 6569 * The maximum delay is specified in milliseconds in max_delay. Note 6570 * that this function may sleep. 6571 * 6572 * Returns true if the function is idle and false if the timeout is 6573 * exceeded. If dev is not a PCI-express function, this returns true. 6574 */ 6575 bool 6576 pcie_wait_for_pending_transactions(device_t dev, u_int max_delay) 6577 { 6578 struct pci_devinfo *dinfo = device_get_ivars(dev); 6579 uint16_t sta; 6580 int cap; 6581 6582 cap = dinfo->cfg.pcie.pcie_location; 6583 if (cap == 0) 6584 return (true); 6585 6586 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6587 while (sta & PCIEM_STA_TRANSACTION_PND) { 6588 if (max_delay == 0) 6589 return (false); 6590 6591 /* Poll once every 100 milliseconds up to the timeout. */ 6592 if (max_delay > 100) { 6593 pause_sbt("pcietp", 100 * SBT_1MS, 0, C_HARDCLOCK); 6594 max_delay -= 100; 6595 } else { 6596 pause_sbt("pcietp", max_delay * SBT_1MS, 0, 6597 C_HARDCLOCK); 6598 max_delay = 0; 6599 } 6600 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6601 } 6602 6603 return (true); 6604 } 6605 6606 /* 6607 * Determine the maximum Completion Timeout in microseconds. 6608 * 6609 * For non-PCI-express functions this returns 0. 6610 */ 6611 int 6612 pcie_get_max_completion_timeout(device_t dev) 6613 { 6614 struct pci_devinfo *dinfo = device_get_ivars(dev); 6615 int cap; 6616 6617 cap = dinfo->cfg.pcie.pcie_location; 6618 if (cap == 0) 6619 return (0); 6620 6621 /* 6622 * Functions using the 1.x spec use the default timeout range of 6623 * 50 microseconds to 50 milliseconds. Functions that do not 6624 * support programmable timeouts also use this range. 6625 */ 6626 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 || 6627 (pci_read_config(dev, cap + PCIER_DEVICE_CAP2, 4) & 6628 PCIEM_CAP2_COMP_TIMO_RANGES) == 0) 6629 return (50 * 1000); 6630 6631 switch (pci_read_config(dev, cap + PCIER_DEVICE_CTL2, 2) & 6632 PCIEM_CTL2_COMP_TIMO_VAL) { 6633 case PCIEM_CTL2_COMP_TIMO_100US: 6634 return (100); 6635 case PCIEM_CTL2_COMP_TIMO_10MS: 6636 return (10 * 1000); 6637 case PCIEM_CTL2_COMP_TIMO_55MS: 6638 return (55 * 1000); 6639 case PCIEM_CTL2_COMP_TIMO_210MS: 6640 return (210 * 1000); 6641 case PCIEM_CTL2_COMP_TIMO_900MS: 6642 return (900 * 1000); 6643 case PCIEM_CTL2_COMP_TIMO_3500MS: 6644 return (3500 * 1000); 6645 case PCIEM_CTL2_COMP_TIMO_13S: 6646 return (13 * 1000 * 1000); 6647 case PCIEM_CTL2_COMP_TIMO_64S: 6648 return (64 * 1000 * 1000); 6649 default: 6650 return (50 * 1000); 6651 } 6652 } 6653 6654 void 6655 pcie_apei_error(device_t dev, int sev, uint8_t *aerp) 6656 { 6657 struct pci_devinfo *dinfo = device_get_ivars(dev); 6658 const char *s; 6659 int aer; 6660 uint32_t r, r1; 6661 uint16_t rs; 6662 6663 if (sev == PCIEM_STA_CORRECTABLE_ERROR) 6664 s = "Correctable"; 6665 else if (sev == PCIEM_STA_NON_FATAL_ERROR) 6666 s = "Uncorrectable (Non-Fatal)"; 6667 else 6668 s = "Uncorrectable (Fatal)"; 6669 device_printf(dev, "%s PCIe error reported by APEI\n", s); 6670 if (aerp) { 6671 if (sev == PCIEM_STA_CORRECTABLE_ERROR) { 6672 r = le32dec(aerp + PCIR_AER_COR_STATUS); 6673 r1 = le32dec(aerp + PCIR_AER_COR_MASK); 6674 } else { 6675 r = le32dec(aerp + PCIR_AER_UC_STATUS); 6676 r1 = le32dec(aerp + PCIR_AER_UC_MASK); 6677 } 6678 device_printf(dev, "status 0x%08x mask 0x%08x", r, r1); 6679 if (sev != PCIEM_STA_CORRECTABLE_ERROR) { 6680 r = le32dec(aerp + PCIR_AER_UC_SEVERITY); 6681 rs = le16dec(aerp + PCIR_AER_CAP_CONTROL); 6682 printf(" severity 0x%08x first %d\n", 6683 r, rs & 0x1f); 6684 } else 6685 printf("\n"); 6686 } 6687 6688 /* As kind of recovery just report and clear the error statuses. */ 6689 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6690 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6691 if (r != 0) { 6692 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6693 device_printf(dev, "Clearing UC AER errors 0x%08x\n", r); 6694 } 6695 6696 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6697 if (r != 0) { 6698 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6699 device_printf(dev, "Clearing COR AER errors 0x%08x\n", r); 6700 } 6701 } 6702 if (dinfo->cfg.pcie.pcie_location != 0) { 6703 rs = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6704 PCIER_DEVICE_STA, 2); 6705 if ((rs & (PCIEM_STA_CORRECTABLE_ERROR | 6706 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6707 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6708 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6709 PCIER_DEVICE_STA, rs, 2); 6710 device_printf(dev, "Clearing PCIe errors 0x%04x\n", rs); 6711 } 6712 } 6713 } 6714 6715 /* 6716 * Perform a Function Level Reset (FLR) on a device. 6717 * 6718 * This function first waits for any pending transactions to complete 6719 * within the timeout specified by max_delay. If transactions are 6720 * still pending, the function will return false without attempting a 6721 * reset. 6722 * 6723 * If dev is not a PCI-express function or does not support FLR, this 6724 * function returns false. 6725 * 6726 * Note that no registers are saved or restored. The caller is 6727 * responsible for saving and restoring any registers including 6728 * PCI-standard registers via pci_save_state() and 6729 * pci_restore_state(). 6730 */ 6731 bool 6732 pcie_flr(device_t dev, u_int max_delay, bool force) 6733 { 6734 struct pci_devinfo *dinfo = device_get_ivars(dev); 6735 uint16_t cmd, ctl; 6736 int compl_delay; 6737 int cap; 6738 6739 cap = dinfo->cfg.pcie.pcie_location; 6740 if (cap == 0) 6741 return (false); 6742 6743 if (!(pci_read_config(dev, cap + PCIER_DEVICE_CAP, 4) & PCIEM_CAP_FLR)) 6744 return (false); 6745 6746 /* 6747 * Disable busmastering to prevent generation of new 6748 * transactions while waiting for the device to go idle. If 6749 * the idle timeout fails, the command register is restored 6750 * which will re-enable busmastering. 6751 */ 6752 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 6753 pci_write_config(dev, PCIR_COMMAND, cmd & ~(PCIM_CMD_BUSMASTEREN), 2); 6754 if (!pcie_wait_for_pending_transactions(dev, max_delay)) { 6755 if (!force) { 6756 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 6757 return (false); 6758 } 6759 pci_printf(&dinfo->cfg, 6760 "Resetting with transactions pending after %d ms\n", 6761 max_delay); 6762 6763 /* 6764 * Extend the post-FLR delay to cover the maximum 6765 * Completion Timeout delay of anything in flight 6766 * during the FLR delay. Enforce a minimum delay of 6767 * at least 10ms. 6768 */ 6769 compl_delay = pcie_get_max_completion_timeout(dev) / 1000; 6770 if (compl_delay < 10) 6771 compl_delay = 10; 6772 } else 6773 compl_delay = 0; 6774 6775 /* Initiate the reset. */ 6776 ctl = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 6777 pci_write_config(dev, cap + PCIER_DEVICE_CTL, ctl | 6778 PCIEM_CTL_INITIATE_FLR, 2); 6779 6780 /* Wait for 100ms. */ 6781 pause_sbt("pcieflr", (100 + compl_delay) * SBT_1MS, 0, C_HARDCLOCK); 6782 6783 if (pci_read_config(dev, cap + PCIER_DEVICE_STA, 2) & 6784 PCIEM_STA_TRANSACTION_PND) 6785 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n"); 6786 return (true); 6787 } 6788 6789 /* 6790 * Attempt a power-management reset by cycling the device in/out of D3 6791 * state. PCI spec says we can only go into D3 state from D0 state. 6792 * Transition from D[12] into D0 before going to D3 state. 6793 */ 6794 int 6795 pci_power_reset(device_t dev) 6796 { 6797 int ps; 6798 6799 ps = pci_get_powerstate(dev); 6800 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6801 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6802 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6803 pci_set_powerstate(dev, ps); 6804 return (0); 6805 } 6806 6807 /* 6808 * Try link drop and retrain of the downstream port of upstream 6809 * switch, for PCIe. According to the PCIe 3.0 spec 6.6.1, this must 6810 * cause Conventional Hot reset of the device in the slot. 6811 * Alternative, for PCIe, could be the secondary bus reset initiatied 6812 * on the upstream switch PCIR_BRIDGECTL_1, bit 6. 6813 */ 6814 int 6815 pcie_link_reset(device_t port, int pcie_location) 6816 { 6817 uint16_t v; 6818 6819 v = pci_read_config(port, pcie_location + PCIER_LINK_CTL, 2); 6820 v |= PCIEM_LINK_CTL_LINK_DIS; 6821 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6822 pause_sbt("pcier1", mstosbt(20), 0, 0); 6823 v &= ~PCIEM_LINK_CTL_LINK_DIS; 6824 v |= PCIEM_LINK_CTL_RETRAIN_LINK; 6825 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6826 pause_sbt("pcier2", mstosbt(100), 0, 0); /* 100 ms */ 6827 v = pci_read_config(port, pcie_location + PCIER_LINK_STA, 2); 6828 return ((v & PCIEM_LINK_STA_TRAINING) != 0 ? ETIMEDOUT : 0); 6829 } 6830 6831 static int 6832 pci_reset_post(device_t dev, device_t child) 6833 { 6834 6835 if (dev == device_get_parent(child)) 6836 pci_restore_state(child); 6837 return (0); 6838 } 6839 6840 static int 6841 pci_reset_prepare(device_t dev, device_t child) 6842 { 6843 6844 if (dev == device_get_parent(child)) 6845 pci_save_state(child); 6846 return (0); 6847 } 6848 6849 static int 6850 pci_reset_child(device_t dev, device_t child, int flags) 6851 { 6852 int error; 6853 6854 if (dev == NULL || device_get_parent(child) != dev) 6855 return (0); 6856 if ((flags & DEVF_RESET_DETACH) != 0) { 6857 error = device_get_state(child) == DS_ATTACHED ? 6858 device_detach(child) : 0; 6859 } else { 6860 error = BUS_SUSPEND_CHILD(dev, child); 6861 } 6862 if (error == 0) { 6863 if (!pcie_flr(child, 1000, false)) { 6864 error = BUS_RESET_PREPARE(dev, child); 6865 if (error == 0) 6866 pci_power_reset(child); 6867 BUS_RESET_POST(dev, child); 6868 } 6869 if ((flags & DEVF_RESET_DETACH) != 0) 6870 device_probe_and_attach(child); 6871 else 6872 BUS_RESUME_CHILD(dev, child); 6873 } 6874 return (error); 6875 } 6876 6877 const struct pci_device_table * 6878 pci_match_device(device_t child, const struct pci_device_table *id, size_t nelt) 6879 { 6880 bool match; 6881 uint16_t vendor, device, subvendor, subdevice, class, subclass, revid; 6882 6883 vendor = pci_get_vendor(child); 6884 device = pci_get_device(child); 6885 subvendor = pci_get_subvendor(child); 6886 subdevice = pci_get_subdevice(child); 6887 class = pci_get_class(child); 6888 subclass = pci_get_subclass(child); 6889 revid = pci_get_revid(child); 6890 while (nelt-- > 0) { 6891 match = true; 6892 if (id->match_flag_vendor) 6893 match &= vendor == id->vendor; 6894 if (id->match_flag_device) 6895 match &= device == id->device; 6896 if (id->match_flag_subvendor) 6897 match &= subvendor == id->subvendor; 6898 if (id->match_flag_subdevice) 6899 match &= subdevice == id->subdevice; 6900 if (id->match_flag_class) 6901 match &= class == id->class_id; 6902 if (id->match_flag_subclass) 6903 match &= subclass == id->subclass; 6904 if (id->match_flag_revid) 6905 match &= revid == id->revid; 6906 if (match) 6907 return (id); 6908 id++; 6909 } 6910 return (NULL); 6911 } 6912 6913 static void 6914 pci_print_faulted_dev_name(const struct pci_devinfo *dinfo) 6915 { 6916 const char *dev_name; 6917 device_t dev; 6918 6919 dev = dinfo->cfg.dev; 6920 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus, 6921 dinfo->cfg.slot, dinfo->cfg.func); 6922 dev_name = device_get_name(dev); 6923 if (dev_name != NULL) 6924 printf(" (%s%d)", dev_name, device_get_unit(dev)); 6925 } 6926 6927 void 6928 pci_print_faulted_dev(void) 6929 { 6930 struct pci_devinfo *dinfo; 6931 device_t dev; 6932 int aer, i; 6933 uint32_t r1, r2; 6934 uint16_t status; 6935 6936 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6937 dev = dinfo->cfg.dev; 6938 status = pci_read_config(dev, PCIR_STATUS, 2); 6939 status &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6940 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6941 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6942 if (status != 0) { 6943 pci_print_faulted_dev_name(dinfo); 6944 printf(" error 0x%04x\n", status); 6945 } 6946 if (dinfo->cfg.pcie.pcie_location != 0) { 6947 status = pci_read_config(dev, 6948 dinfo->cfg.pcie.pcie_location + 6949 PCIER_DEVICE_STA, 2); 6950 if ((status & (PCIEM_STA_CORRECTABLE_ERROR | 6951 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6952 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6953 pci_print_faulted_dev_name(dinfo); 6954 printf(" PCIe DEVCTL 0x%04x DEVSTA 0x%04x\n", 6955 pci_read_config(dev, 6956 dinfo->cfg.pcie.pcie_location + 6957 PCIER_DEVICE_CTL, 2), 6958 status); 6959 } 6960 } 6961 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6962 r1 = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6963 r2 = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6964 if (r1 != 0 || r2 != 0) { 6965 pci_print_faulted_dev_name(dinfo); 6966 printf(" AER UC 0x%08x Mask 0x%08x Svr 0x%08x\n" 6967 " COR 0x%08x Mask 0x%08x Ctl 0x%08x\n", 6968 r1, pci_read_config(dev, aer + 6969 PCIR_AER_UC_MASK, 4), 6970 pci_read_config(dev, aer + 6971 PCIR_AER_UC_SEVERITY, 4), 6972 r2, pci_read_config(dev, aer + 6973 PCIR_AER_COR_MASK, 4), 6974 pci_read_config(dev, aer + 6975 PCIR_AER_CAP_CONTROL, 4)); 6976 for (i = 0; i < 4; i++) { 6977 r1 = pci_read_config(dev, aer + 6978 PCIR_AER_HEADER_LOG + i * 4, 4); 6979 printf(" HL%d: 0x%08x\n", i, r1); 6980 } 6981 } 6982 } 6983 } 6984 } 6985 6986 #ifdef DDB 6987 DB_SHOW_COMMAND_FLAGS(pcierr, pci_print_faulted_dev_db, DB_CMD_MEMSAFE) 6988 { 6989 6990 pci_print_faulted_dev(); 6991 } 6992 6993 static void 6994 db_clear_pcie_errors(const struct pci_devinfo *dinfo) 6995 { 6996 device_t dev; 6997 int aer; 6998 uint32_t r; 6999 7000 dev = dinfo->cfg.dev; 7001 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 7002 PCIER_DEVICE_STA, 2); 7003 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 7004 PCIER_DEVICE_STA, r, 2); 7005 7006 if (pci_find_extcap(dev, PCIZ_AER, &aer) != 0) 7007 return; 7008 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 7009 if (r != 0) 7010 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 7011 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 7012 if (r != 0) 7013 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 7014 } 7015 7016 DB_COMMAND_FLAGS(pci_clearerr, db_pci_clearerr, DB_CMD_MEMSAFE) 7017 { 7018 struct pci_devinfo *dinfo; 7019 device_t dev; 7020 uint16_t status, status1; 7021 7022 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 7023 dev = dinfo->cfg.dev; 7024 status1 = status = pci_read_config(dev, PCIR_STATUS, 2); 7025 status1 &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 7026 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 7027 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 7028 if (status1 != 0) { 7029 status &= ~status1; 7030 pci_write_config(dev, PCIR_STATUS, status, 2); 7031 } 7032 if (dinfo->cfg.pcie.pcie_location != 0) 7033 db_clear_pcie_errors(dinfo); 7034 } 7035 } 7036 #endif 7037