1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/linker.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/sysctl.h> 44 #include <sys/types.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 55 #include <sys/pciio.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pci_private.h> 59 60 #include "pcib_if.h" 61 #include "pci_if.h" 62 63 #if (defined(__i386__) && !defined(PC98)) || defined(__amd64__) || \ 64 defined (__ia64__) 65 #include <contrib/dev/acpica/acpi.h> 66 #include "acpi_if.h" 67 #else 68 #define ACPI_PWR_FOR_SLEEP(x, y, z) 69 #endif 70 71 static uint32_t pci_mapbase(unsigned mapreg); 72 static int pci_maptype(unsigned mapreg); 73 static int pci_mapsize(unsigned testval); 74 static int pci_maprange(unsigned mapreg); 75 static void pci_fixancient(pcicfgregs *cfg); 76 77 static int pci_porten(device_t pcib, int b, int s, int f); 78 static int pci_memen(device_t pcib, int b, int s, int f); 79 static int pci_add_map(device_t pcib, device_t bus, device_t dev, 80 int b, int s, int f, int reg, 81 struct resource_list *rl); 82 static void pci_add_resources(device_t pcib, device_t bus, 83 device_t dev); 84 static int pci_probe(device_t dev); 85 static int pci_attach(device_t dev); 86 static void pci_load_vendor_data(void); 87 static int pci_describe_parse_line(char **ptr, int *vendor, 88 int *device, char **desc); 89 static char *pci_describe_device(device_t dev); 90 static int pci_modevent(module_t mod, int what, void *arg); 91 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 92 pcicfgregs *cfg); 93 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 94 95 static device_method_t pci_methods[] = { 96 /* Device interface */ 97 DEVMETHOD(device_probe, pci_probe), 98 DEVMETHOD(device_attach, pci_attach), 99 DEVMETHOD(device_shutdown, bus_generic_shutdown), 100 DEVMETHOD(device_suspend, pci_suspend), 101 DEVMETHOD(device_resume, pci_resume), 102 103 /* Bus interface */ 104 DEVMETHOD(bus_print_child, pci_print_child), 105 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 106 DEVMETHOD(bus_read_ivar, pci_read_ivar), 107 DEVMETHOD(bus_write_ivar, pci_write_ivar), 108 DEVMETHOD(bus_driver_added, pci_driver_added), 109 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 110 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 111 112 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 113 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 114 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 115 DEVMETHOD(bus_delete_resource, pci_delete_resource), 116 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 117 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 118 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 119 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 120 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 121 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 122 123 /* PCI interface */ 124 DEVMETHOD(pci_read_config, pci_read_config_method), 125 DEVMETHOD(pci_write_config, pci_write_config_method), 126 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 127 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 128 DEVMETHOD(pci_enable_io, pci_enable_io_method), 129 DEVMETHOD(pci_disable_io, pci_disable_io_method), 130 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 131 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 132 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 133 134 { 0, 0 } 135 }; 136 137 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 138 139 devclass_t pci_devclass; 140 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 141 MODULE_VERSION(pci, 1); 142 143 static char *pci_vendordata; 144 static size_t pci_vendordata_size; 145 146 147 struct pci_quirk { 148 uint32_t devid; /* Vendor/device of the card */ 149 int type; 150 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 151 int arg1; 152 int arg2; 153 }; 154 155 struct pci_quirk pci_quirks[] = { 156 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 157 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 158 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 159 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 160 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 161 162 { 0 } 163 }; 164 165 /* map register information */ 166 #define PCI_MAPMEM 0x01 /* memory map */ 167 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 168 #define PCI_MAPPORT 0x04 /* port map */ 169 170 struct devlist pci_devq; 171 uint32_t pci_generation; 172 uint32_t pci_numdevs = 0; 173 174 /* sysctl vars */ 175 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 176 177 static int pci_enable_io_modes = 1; 178 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 179 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 180 &pci_enable_io_modes, 1, 181 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 182 enable these bits correctly. We'd like to do this all the time, but there\n\ 183 are some peripherals that this causes problems with."); 184 185 static int pci_do_powerstate = 1; 186 TUNABLE_INT("hw.pci.do_powerstate", &pci_do_powerstate); 187 SYSCTL_INT(_hw_pci, OID_AUTO, do_powerstate, CTLFLAG_RW, 188 &pci_do_powerstate, 1, 189 "Power down devices into D3 state when no driver attaches to them.\n\ 190 Otherwise, leave the device in D0 state when no driver attaches."); 191 192 /* Find a device_t by bus/slot/function */ 193 194 device_t 195 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 196 { 197 struct pci_devinfo *dinfo; 198 199 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 200 if ((dinfo->cfg.bus == bus) && 201 (dinfo->cfg.slot == slot) && 202 (dinfo->cfg.func == func)) { 203 return (dinfo->cfg.dev); 204 } 205 } 206 207 return (NULL); 208 } 209 210 /* Find a device_t by vendor/device ID */ 211 212 device_t 213 pci_find_device(uint16_t vendor, uint16_t device) 214 { 215 struct pci_devinfo *dinfo; 216 217 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 218 if ((dinfo->cfg.vendor == vendor) && 219 (dinfo->cfg.device == device)) { 220 return (dinfo->cfg.dev); 221 } 222 } 223 224 return (NULL); 225 } 226 227 /* return base address of memory or port map */ 228 229 static uint32_t 230 pci_mapbase(unsigned mapreg) 231 { 232 int mask = 0x03; 233 if ((mapreg & 0x01) == 0) 234 mask = 0x0f; 235 return (mapreg & ~mask); 236 } 237 238 /* return map type of memory or port map */ 239 240 static int 241 pci_maptype(unsigned mapreg) 242 { 243 static uint8_t maptype[0x10] = { 244 PCI_MAPMEM, PCI_MAPPORT, 245 PCI_MAPMEM, 0, 246 PCI_MAPMEM, PCI_MAPPORT, 247 0, 0, 248 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 249 PCI_MAPMEM|PCI_MAPMEMP, 0, 250 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 251 0, 0, 252 }; 253 254 return maptype[mapreg & 0x0f]; 255 } 256 257 /* return log2 of map size decoded for memory or port map */ 258 259 static int 260 pci_mapsize(unsigned testval) 261 { 262 int ln2size; 263 264 testval = pci_mapbase(testval); 265 ln2size = 0; 266 if (testval != 0) { 267 while ((testval & 1) == 0) 268 { 269 ln2size++; 270 testval >>= 1; 271 } 272 } 273 return (ln2size); 274 } 275 276 /* return log2 of address range supported by map register */ 277 278 static int 279 pci_maprange(unsigned mapreg) 280 { 281 int ln2range = 0; 282 switch (mapreg & 0x07) { 283 case 0x00: 284 case 0x01: 285 case 0x05: 286 ln2range = 32; 287 break; 288 case 0x02: 289 ln2range = 20; 290 break; 291 case 0x04: 292 ln2range = 64; 293 break; 294 } 295 return (ln2range); 296 } 297 298 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 299 300 static void 301 pci_fixancient(pcicfgregs *cfg) 302 { 303 if (cfg->hdrtype != 0) 304 return; 305 306 /* PCI to PCI bridges use header type 1 */ 307 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 308 cfg->hdrtype = 1; 309 } 310 311 /* extract header type specific config data */ 312 313 static void 314 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 315 { 316 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 317 switch (cfg->hdrtype) { 318 case 0: 319 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 320 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 321 cfg->nummaps = PCI_MAXMAPS_0; 322 break; 323 case 1: 324 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 325 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 326 cfg->nummaps = PCI_MAXMAPS_1; 327 break; 328 case 2: 329 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 330 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 331 cfg->nummaps = PCI_MAXMAPS_2; 332 break; 333 } 334 #undef REG 335 } 336 337 /* read configuration header into pcicfgregs structure */ 338 339 struct pci_devinfo * 340 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 341 { 342 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 343 pcicfgregs *cfg = NULL; 344 struct pci_devinfo *devlist_entry; 345 struct devlist *devlist_head; 346 347 devlist_head = &pci_devq; 348 349 devlist_entry = NULL; 350 351 if (REG(PCIR_DEVVENDOR, 4) != -1) { 352 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 353 if (devlist_entry == NULL) 354 return (NULL); 355 356 cfg = &devlist_entry->cfg; 357 358 cfg->bus = b; 359 cfg->slot = s; 360 cfg->func = f; 361 cfg->vendor = REG(PCIR_VENDOR, 2); 362 cfg->device = REG(PCIR_DEVICE, 2); 363 cfg->cmdreg = REG(PCIR_COMMAND, 2); 364 cfg->statreg = REG(PCIR_STATUS, 2); 365 cfg->baseclass = REG(PCIR_CLASS, 1); 366 cfg->subclass = REG(PCIR_SUBCLASS, 1); 367 cfg->progif = REG(PCIR_PROGIF, 1); 368 cfg->revid = REG(PCIR_REVID, 1); 369 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 370 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 371 cfg->lattimer = REG(PCIR_LATTIMER, 1); 372 cfg->intpin = REG(PCIR_INTPIN, 1); 373 cfg->intline = REG(PCIR_INTLINE, 1); 374 375 cfg->mingnt = REG(PCIR_MINGNT, 1); 376 cfg->maxlat = REG(PCIR_MAXLAT, 1); 377 378 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 379 cfg->hdrtype &= ~PCIM_MFDEV; 380 381 pci_fixancient(cfg); 382 pci_hdrtypedata(pcib, b, s, f, cfg); 383 384 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 385 pci_read_extcap(pcib, cfg); 386 387 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 388 389 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 390 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 391 devlist_entry->conf.pc_sel.pc_func = cfg->func; 392 devlist_entry->conf.pc_hdr = cfg->hdrtype; 393 394 devlist_entry->conf.pc_subvendor = cfg->subvendor; 395 devlist_entry->conf.pc_subdevice = cfg->subdevice; 396 devlist_entry->conf.pc_vendor = cfg->vendor; 397 devlist_entry->conf.pc_device = cfg->device; 398 399 devlist_entry->conf.pc_class = cfg->baseclass; 400 devlist_entry->conf.pc_subclass = cfg->subclass; 401 devlist_entry->conf.pc_progif = cfg->progif; 402 devlist_entry->conf.pc_revid = cfg->revid; 403 404 pci_numdevs++; 405 pci_generation++; 406 } 407 return (devlist_entry); 408 #undef REG 409 } 410 411 static void 412 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 413 { 414 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 415 int ptr, nextptr, ptrptr; 416 417 switch (cfg->hdrtype & PCIM_HDRTYPE) { 418 case 0: 419 ptrptr = PCIR_CAP_PTR; 420 break; 421 case 2: 422 ptrptr = 0x14; 423 break; 424 default: 425 return; /* no extended capabilities support */ 426 } 427 nextptr = REG(ptrptr, 1); /* sanity check? */ 428 429 /* 430 * Read capability entries. 431 */ 432 while (nextptr != 0) { 433 /* Sanity check */ 434 if (nextptr > 255) { 435 printf("illegal PCI extended capability offset %d\n", 436 nextptr); 437 return; 438 } 439 /* Find the next entry */ 440 ptr = nextptr; 441 nextptr = REG(ptr + 1, 1); 442 443 /* Process this entry */ 444 switch (REG(ptr, 1)) { 445 case PCIY_PMG: /* PCI power management */ 446 if (cfg->pp.pp_cap == 0) { 447 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 448 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 449 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 450 if ((nextptr - ptr) > PCIR_POWER_DATA) 451 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 452 } 453 break; 454 case PCIY_MSI: /* PCI MSI */ 455 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 456 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 457 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 458 else 459 cfg->msi.msi_data = PCIR_MSI_DATA; 460 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 461 PCIM_MSICTRL_MMC_MASK)>>1); 462 default: 463 break; 464 } 465 } 466 #undef REG 467 } 468 469 /* free pcicfgregs structure and all depending data structures */ 470 471 int 472 pci_freecfg(struct pci_devinfo *dinfo) 473 { 474 struct devlist *devlist_head; 475 476 devlist_head = &pci_devq; 477 478 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 479 free(dinfo, M_DEVBUF); 480 481 /* increment the generation count */ 482 pci_generation++; 483 484 /* we're losing one device */ 485 pci_numdevs--; 486 return (0); 487 } 488 489 /* 490 * PCI power manangement 491 */ 492 int 493 pci_set_powerstate_method(device_t dev, device_t child, int state) 494 { 495 struct pci_devinfo *dinfo = device_get_ivars(child); 496 pcicfgregs *cfg = &dinfo->cfg; 497 uint16_t status; 498 int result, oldstate, highest, delay; 499 500 if (cfg->pp.pp_cap == 0) 501 return (EOPNOTSUPP); 502 503 /* 504 * Optimize a no state change request away. While it would be OK to 505 * write to the hardware in theory, some devices have shown odd 506 * behavior when going from D3 -> D3. 507 */ 508 oldstate = pci_get_powerstate(child); 509 if (oldstate == state) 510 return (0); 511 512 /* 513 * The PCI power management specification states that after a state 514 * transition between PCI power states, system software must 515 * guarantee a minimal delay before the function accesses the device. 516 * Compute the worst case delay that we need to guarantee before we 517 * access the device. Many devices will be responsive much more 518 * quickly than this delay, but there are some that don't respond 519 * instantly to state changes. Transitions to/from D3 state require 520 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 521 * is done below with DELAY rather than a sleeper function because 522 * this function can be called from contexts where we cannot sleep. 523 */ 524 highest = (oldstate > state) ? oldstate : state; 525 if (highest == PCI_POWERSTATE_D3) 526 delay = 10000; 527 else if (highest == PCI_POWERSTATE_D2) 528 delay = 200; 529 else 530 delay = 0; 531 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 532 & ~PCIM_PSTAT_DMASK; 533 result = 0; 534 switch (state) { 535 case PCI_POWERSTATE_D0: 536 status |= PCIM_PSTAT_D0; 537 break; 538 case PCI_POWERSTATE_D1: 539 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 540 return (EOPNOTSUPP); 541 status |= PCIM_PSTAT_D1; 542 break; 543 case PCI_POWERSTATE_D2: 544 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 545 return (EOPNOTSUPP); 546 status |= PCIM_PSTAT_D2; 547 break; 548 case PCI_POWERSTATE_D3: 549 status |= PCIM_PSTAT_D3; 550 break; 551 default: 552 return (EINVAL); 553 } 554 555 if (bootverbose) 556 printf( 557 "pci%d:%d:%d: Transition from D%d to D%d\n", 558 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 559 oldstate, state); 560 561 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 562 if (delay) 563 DELAY(delay); 564 return (0); 565 } 566 567 int 568 pci_get_powerstate_method(device_t dev, device_t child) 569 { 570 struct pci_devinfo *dinfo = device_get_ivars(child); 571 pcicfgregs *cfg = &dinfo->cfg; 572 uint16_t status; 573 int result; 574 575 if (cfg->pp.pp_cap != 0) { 576 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 577 switch (status & PCIM_PSTAT_DMASK) { 578 case PCIM_PSTAT_D0: 579 result = PCI_POWERSTATE_D0; 580 break; 581 case PCIM_PSTAT_D1: 582 result = PCI_POWERSTATE_D1; 583 break; 584 case PCIM_PSTAT_D2: 585 result = PCI_POWERSTATE_D2; 586 break; 587 case PCIM_PSTAT_D3: 588 result = PCI_POWERSTATE_D3; 589 break; 590 default: 591 result = PCI_POWERSTATE_UNKNOWN; 592 break; 593 } 594 } else { 595 /* No support, device is always at D0 */ 596 result = PCI_POWERSTATE_D0; 597 } 598 return (result); 599 } 600 601 /* 602 * Some convenience functions for PCI device drivers. 603 */ 604 605 static __inline void 606 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 607 { 608 uint16_t command; 609 610 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 611 command |= bit; 612 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 613 } 614 615 static __inline void 616 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 617 { 618 uint16_t command; 619 620 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 621 command &= ~bit; 622 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 623 } 624 625 int 626 pci_enable_busmaster_method(device_t dev, device_t child) 627 { 628 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 629 return (0); 630 } 631 632 int 633 pci_disable_busmaster_method(device_t dev, device_t child) 634 { 635 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 636 return (0); 637 } 638 639 int 640 pci_enable_io_method(device_t dev, device_t child, int space) 641 { 642 uint16_t command; 643 uint16_t bit; 644 char *error; 645 646 bit = 0; 647 error = NULL; 648 649 switch(space) { 650 case SYS_RES_IOPORT: 651 bit = PCIM_CMD_PORTEN; 652 error = "port"; 653 break; 654 case SYS_RES_MEMORY: 655 bit = PCIM_CMD_MEMEN; 656 error = "memory"; 657 break; 658 default: 659 return (EINVAL); 660 } 661 pci_set_command_bit(dev, child, bit); 662 /* Some devices seem to need a brief stall here, what do to? */ 663 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 664 if (command & bit) 665 return (0); 666 device_printf(child, "failed to enable %s mapping!\n", error); 667 return (ENXIO); 668 } 669 670 int 671 pci_disable_io_method(device_t dev, device_t child, int space) 672 { 673 uint16_t command; 674 uint16_t bit; 675 char *error; 676 677 bit = 0; 678 error = NULL; 679 680 switch(space) { 681 case SYS_RES_IOPORT: 682 bit = PCIM_CMD_PORTEN; 683 error = "port"; 684 break; 685 case SYS_RES_MEMORY: 686 bit = PCIM_CMD_MEMEN; 687 error = "memory"; 688 break; 689 default: 690 return (EINVAL); 691 } 692 pci_clear_command_bit(dev, child, bit); 693 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 694 if (command & bit) { 695 device_printf(child, "failed to disable %s mapping!\n", error); 696 return (ENXIO); 697 } 698 return (0); 699 } 700 701 /* 702 * New style pci driver. Parent device is either a pci-host-bridge or a 703 * pci-pci-bridge. Both kinds are represented by instances of pcib. 704 */ 705 706 void 707 pci_print_verbose(struct pci_devinfo *dinfo) 708 { 709 if (bootverbose) { 710 pcicfgregs *cfg = &dinfo->cfg; 711 712 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 713 cfg->vendor, cfg->device, cfg->revid); 714 printf("\tbus=%d, slot=%d, func=%d\n", 715 cfg->bus, cfg->slot, cfg->func); 716 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 717 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 718 cfg->mfdev); 719 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 720 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 721 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 722 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 723 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 724 if (cfg->intpin > 0) 725 printf("\tintpin=%c, irq=%d\n", 726 cfg->intpin +'a' -1, cfg->intline); 727 if (cfg->pp.pp_cap) { 728 uint16_t status; 729 730 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 731 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 732 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 733 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 734 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 735 status & PCIM_PSTAT_DMASK); 736 } 737 if (cfg->msi.msi_data) { 738 int ctrl; 739 740 ctrl = cfg->msi.msi_ctrl; 741 printf("\tMSI supports %d message%s%s%s\n", 742 cfg->msi.msi_msgnum, 743 (cfg->msi.msi_msgnum == 1) ? "" : "s", 744 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 745 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 746 } 747 } 748 } 749 750 static int 751 pci_porten(device_t pcib, int b, int s, int f) 752 { 753 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 754 & PCIM_CMD_PORTEN) != 0; 755 } 756 757 static int 758 pci_memen(device_t pcib, int b, int s, int f) 759 { 760 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 761 & PCIM_CMD_MEMEN) != 0; 762 } 763 764 /* 765 * Add a resource based on a pci map register. Return 1 if the map 766 * register is a 32bit map register or 2 if it is a 64bit register. 767 */ 768 static int 769 pci_add_map(device_t pcib, device_t bus, device_t dev, 770 int b, int s, int f, int reg, struct resource_list *rl) 771 { 772 uint32_t map; 773 uint64_t base; 774 uint64_t start, end, count; 775 uint8_t ln2size; 776 uint8_t ln2range; 777 uint32_t testval; 778 uint16_t cmd; 779 int type; 780 781 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 782 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 783 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 784 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 785 786 if (pci_maptype(map) & PCI_MAPMEM) 787 type = SYS_RES_MEMORY; 788 else 789 type = SYS_RES_IOPORT; 790 ln2size = pci_mapsize(testval); 791 ln2range = pci_maprange(testval); 792 base = pci_mapbase(map); 793 794 /* 795 * For I/O registers, if bottom bit is set, and the next bit up 796 * isn't clear, we know we have a BAR that doesn't conform to the 797 * spec, so ignore it. Also, sanity check the size of the data 798 * areas to the type of memory involved. Memory must be at least 799 * 32 bytes in size, while I/O ranges must be at least 4. 800 */ 801 if ((testval & 0x1) == 0x1 && 802 (testval & 0x2) != 0) 803 return (1); 804 if ((type == SYS_RES_MEMORY && ln2size < 5) || 805 (type == SYS_RES_IOPORT && ln2size < 2)) 806 return (1); 807 808 if (ln2range == 64) 809 /* Read the other half of a 64bit map register */ 810 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 811 812 if (bootverbose) { 813 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 814 reg, pci_maptype(map), ln2range, 815 (unsigned int) base, ln2size); 816 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 817 printf(", port disabled\n"); 818 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 819 printf(", memory disabled\n"); 820 else 821 printf(", enabled\n"); 822 } 823 824 /* 825 * This code theoretically does the right thing, but has 826 * undesirable side effects in some cases where peripherals 827 * respond oddly to having these bits enabled. Let the user 828 * be able to turn them off (since pci_enable_io_modes is 1 by 829 * default). 830 */ 831 if (pci_enable_io_modes) { 832 /* Turn on resources that have been left off by a lazy BIOS */ 833 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 834 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 835 cmd |= PCIM_CMD_PORTEN; 836 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 837 } 838 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 839 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 840 cmd |= PCIM_CMD_MEMEN; 841 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 842 } 843 } else { 844 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 845 return (1); 846 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 847 return (1); 848 } 849 /* 850 * If base is 0, then we have problems. It is best to ignore 851 * such entires for the moment. These will be allocated later if 852 * the driver specifically requests them. 853 */ 854 if (base == 0) 855 return 1; 856 857 start = base; 858 end = base + (1 << ln2size) - 1; 859 count = 1 << ln2size; 860 resource_list_add(rl, type, reg, start, end, count); 861 862 /* 863 * Not quite sure what to do on failure of allocating the resource 864 * since I can postulate several right answers. 865 */ 866 resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 0); 867 return ((ln2range == 64) ? 2 : 1); 868 } 869 870 /* 871 * For ATA devices we need to decide early what addressing mode to use. 872 * Legacy demands that the primary and secondary ATA ports sits on the 873 * same addresses that old ISA hardware did. This dictates that we use 874 * those addresses and ignore the BAR's if we cannot set PCI native 875 * addressing mode. 876 */ 877 static void 878 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 879 int s, int f, struct resource_list *rl) 880 { 881 int rid, type, progif; 882 #if 0 883 /* if this device supports PCI native addressing use it */ 884 progif = pci_read_config(dev, PCIR_PROGIF, 1); 885 if ((progif & 0x8a) == 0x8a) { 886 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 887 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 888 printf("Trying ATA native PCI addressing mode\n"); 889 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 890 } 891 } 892 #endif 893 progif = pci_read_config(dev, PCIR_PROGIF, 1); 894 type = SYS_RES_IOPORT; 895 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 896 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl); 897 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl); 898 } 899 else { 900 rid = PCIR_BAR(0); 901 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 902 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,8,0); 903 rid = PCIR_BAR(1); 904 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 905 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,1,0); 906 } 907 if (progif & PCIP_STORAGE_IDE_MODESEC) { 908 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl); 909 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl); 910 } 911 else { 912 rid = PCIR_BAR(2); 913 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 914 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,8,0); 915 rid = PCIR_BAR(3); 916 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 917 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,1,0); 918 } 919 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl); 920 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl); 921 } 922 923 static void 924 pci_add_resources(device_t pcib, device_t bus, device_t dev) 925 { 926 struct pci_devinfo *dinfo = device_get_ivars(dev); 927 pcicfgregs *cfg = &dinfo->cfg; 928 struct resource_list *rl = &dinfo->resources; 929 struct pci_quirk *q; 930 int b, i, irq, f, s; 931 932 b = cfg->bus; 933 s = cfg->slot; 934 f = cfg->func; 935 936 /* ATA devices needs special map treatment */ 937 if ((pci_get_class(dev) == PCIC_STORAGE) && 938 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 939 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 940 pci_ata_maps(pcib, bus, dev, b, s, f, rl); 941 else 942 for (i = 0; i < cfg->nummaps;) 943 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 944 rl); 945 946 for (q = &pci_quirks[0]; q->devid; q++) { 947 if (q->devid == ((cfg->device << 16) | cfg->vendor) 948 && q->type == PCI_QUIRK_MAP_REG) 949 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl); 950 } 951 952 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 953 #if defined(__ia64__) || defined(__i386__) || defined(__amd64__) || \ 954 defined(__arm__) || defined(__alpha__) 955 /* 956 * Try to re-route interrupts. Sometimes the BIOS or 957 * firmware may leave bogus values in these registers. 958 * If the re-route fails, then just stick with what we 959 * have. 960 */ 961 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 962 if (PCI_INTERRUPT_VALID(irq)) { 963 pci_write_config(dev, PCIR_INTLINE, irq, 1); 964 cfg->intline = irq; 965 } else 966 #endif 967 irq = cfg->intline; 968 resource_list_add(rl, SYS_RES_IRQ, 0, irq, irq, 1); 969 } 970 } 971 972 void 973 pci_add_children(device_t dev, int busno, size_t dinfo_size) 974 { 975 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 976 device_t pcib = device_get_parent(dev); 977 struct pci_devinfo *dinfo; 978 int maxslots; 979 int s, f, pcifunchigh; 980 uint8_t hdrtype; 981 982 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 983 ("dinfo_size too small")); 984 maxslots = PCIB_MAXSLOTS(pcib); 985 for (s = 0; s <= maxslots; s++) { 986 pcifunchigh = 0; 987 f = 0; 988 hdrtype = REG(PCIR_HDRTYPE, 1); 989 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 990 continue; 991 if (hdrtype & PCIM_MFDEV) 992 pcifunchigh = PCI_FUNCMAX; 993 for (f = 0; f <= pcifunchigh; f++) { 994 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 995 if (dinfo != NULL) { 996 pci_add_child(dev, dinfo); 997 } 998 } 999 } 1000 #undef REG 1001 } 1002 1003 void 1004 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1005 { 1006 device_t pcib; 1007 1008 pcib = device_get_parent(bus); 1009 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1010 device_set_ivars(dinfo->cfg.dev, dinfo); 1011 resource_list_init(&dinfo->resources); 1012 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 1013 pci_cfg_restore(dinfo->cfg.dev, dinfo); 1014 pci_print_verbose(dinfo); 1015 pci_add_resources(pcib, bus, dinfo->cfg.dev); 1016 } 1017 1018 static int 1019 pci_probe(device_t dev) 1020 { 1021 1022 device_set_desc(dev, "PCI bus"); 1023 1024 /* Allow other subclasses to override this driver. */ 1025 return (-1000); 1026 } 1027 1028 static int 1029 pci_attach(device_t dev) 1030 { 1031 int busno; 1032 1033 /* 1034 * Since there can be multiple independantly numbered PCI 1035 * busses on some large alpha systems, we can't use the unit 1036 * number to decide what bus we are probing. We ask the parent 1037 * pcib what our bus number is. 1038 */ 1039 busno = pcib_get_bus(dev); 1040 if (bootverbose) 1041 device_printf(dev, "physical bus=%d\n", busno); 1042 1043 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1044 1045 return (bus_generic_attach(dev)); 1046 } 1047 1048 int 1049 pci_suspend(device_t dev) 1050 { 1051 int dstate, error, i, numdevs; 1052 device_t acpi_dev, child, *devlist; 1053 struct pci_devinfo *dinfo; 1054 1055 /* 1056 * Save the PCI configuration space for each child and set the 1057 * device in the appropriate power state for this sleep state. 1058 */ 1059 acpi_dev = NULL; 1060 if (pci_do_powerstate) 1061 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1062 device_get_children(dev, &devlist, &numdevs); 1063 for (i = 0; i < numdevs; i++) { 1064 child = devlist[i]; 1065 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1066 pci_cfg_save(child, dinfo, 0); 1067 } 1068 1069 /* Suspend devices before potentially powering them down. */ 1070 error = bus_generic_suspend(dev); 1071 if (error) { 1072 free(devlist, M_TEMP); 1073 return (error); 1074 } 1075 1076 /* 1077 * Always set the device to D3. If ACPI suggests a different 1078 * power state, use it instead. If ACPI is not present, the 1079 * firmware is responsible for managing device power. Skip 1080 * children who aren't attached since they are powered down 1081 * separately. Only manage type 0 devices for now. 1082 */ 1083 for (i = 0; acpi_dev && i < numdevs; i++) { 1084 child = devlist[i]; 1085 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1086 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 1087 dstate = PCI_POWERSTATE_D3; 1088 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 1089 pci_set_powerstate(child, dstate); 1090 } 1091 } 1092 free(devlist, M_TEMP); 1093 return (0); 1094 } 1095 1096 int 1097 pci_resume(device_t dev) 1098 { 1099 int i, numdevs; 1100 device_t acpi_dev, child, *devlist; 1101 struct pci_devinfo *dinfo; 1102 1103 /* 1104 * Set each child to D0 and restore its PCI configuration space. 1105 */ 1106 acpi_dev = NULL; 1107 if (pci_do_powerstate) 1108 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1109 device_get_children(dev, &devlist, &numdevs); 1110 for (i = 0; i < numdevs; i++) { 1111 /* 1112 * Notify ACPI we're going to D0 but ignore the result. If 1113 * ACPI is not present, the firmware is responsible for 1114 * managing device power. Only manage type 0 devices for now. 1115 */ 1116 child = devlist[i]; 1117 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1118 if (acpi_dev && device_is_attached(child) && 1119 dinfo->cfg.hdrtype == 0) { 1120 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 1121 pci_set_powerstate(child, PCI_POWERSTATE_D0); 1122 } 1123 1124 /* Now the device is powered up, restore its config space. */ 1125 pci_cfg_restore(child, dinfo); 1126 } 1127 free(devlist, M_TEMP); 1128 return (bus_generic_resume(dev)); 1129 } 1130 1131 static void 1132 pci_load_vendor_data(void) 1133 { 1134 caddr_t vendordata, info; 1135 1136 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1137 info = preload_search_info(vendordata, MODINFO_ADDR); 1138 pci_vendordata = *(char **)info; 1139 info = preload_search_info(vendordata, MODINFO_SIZE); 1140 pci_vendordata_size = *(size_t *)info; 1141 /* terminate the database */ 1142 pci_vendordata[pci_vendordata_size] = '\n'; 1143 } 1144 } 1145 1146 void 1147 pci_driver_added(device_t dev, driver_t *driver) 1148 { 1149 int numdevs; 1150 device_t *devlist; 1151 device_t child; 1152 struct pci_devinfo *dinfo; 1153 int i; 1154 1155 if (bootverbose) 1156 device_printf(dev, "driver added\n"); 1157 DEVICE_IDENTIFY(driver, dev); 1158 device_get_children(dev, &devlist, &numdevs); 1159 for (i = 0; i < numdevs; i++) { 1160 child = devlist[i]; 1161 if (device_get_state(child) != DS_NOTPRESENT) 1162 continue; 1163 dinfo = device_get_ivars(child); 1164 pci_print_verbose(dinfo); 1165 if (bootverbose) 1166 printf("pci%d:%d:%d: reprobing on driver added\n", 1167 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1168 pci_cfg_restore(child, dinfo); 1169 if (device_probe_and_attach(child) != 0) 1170 pci_cfg_save(child, dinfo, 1); 1171 } 1172 free(devlist, M_TEMP); 1173 } 1174 1175 int 1176 pci_print_child(device_t dev, device_t child) 1177 { 1178 struct pci_devinfo *dinfo; 1179 struct resource_list *rl; 1180 int retval = 0; 1181 1182 dinfo = device_get_ivars(child); 1183 rl = &dinfo->resources; 1184 1185 retval += bus_print_child_header(dev, child); 1186 1187 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1188 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1189 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1190 if (device_get_flags(dev)) 1191 retval += printf(" flags %#x", device_get_flags(dev)); 1192 1193 retval += printf(" at device %d.%d", pci_get_slot(child), 1194 pci_get_function(child)); 1195 1196 retval += bus_print_child_footer(dev, child); 1197 1198 return (retval); 1199 } 1200 1201 static struct 1202 { 1203 int class; 1204 int subclass; 1205 char *desc; 1206 } pci_nomatch_tab[] = { 1207 {PCIC_OLD, -1, "old"}, 1208 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1209 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1210 {PCIC_STORAGE, -1, "mass storage"}, 1211 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1212 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1213 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1214 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1215 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1216 {PCIC_NETWORK, -1, "network"}, 1217 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1218 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1219 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1220 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1221 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"}, 1222 {PCIC_DISPLAY, -1, "display"}, 1223 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1224 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1225 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"}, 1226 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1227 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1228 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1229 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"}, 1230 {PCIC_MEMORY, -1, "memory"}, 1231 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1232 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1233 {PCIC_BRIDGE, -1, "bridge"}, 1234 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1235 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1236 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1237 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1238 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1239 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1240 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1241 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1242 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"}, 1243 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1244 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1245 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1246 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"}, 1247 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"}, 1248 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1249 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1250 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1251 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1252 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1253 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"}, 1254 {PCIC_INPUTDEV, -1, "input device"}, 1255 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1256 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1257 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1258 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"}, 1259 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"}, 1260 {PCIC_DOCKING, -1, "docking station"}, 1261 {PCIC_PROCESSOR, -1, "processor"}, 1262 {PCIC_SERIALBUS, -1, "serial bus"}, 1263 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1264 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1265 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1266 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1267 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1268 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1269 {PCIC_WIRELESS, -1, "wireless controller"}, 1270 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"}, 1271 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"}, 1272 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"}, 1273 {PCIC_INTELLIIO, -1, "intelligent I/O controller"}, 1274 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"}, 1275 {PCIC_SATCOM, -1, "satellite communication"}, 1276 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"}, 1277 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"}, 1278 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"}, 1279 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"}, 1280 {PCIC_CRYPTO, -1, "encrypt/decrypt"}, 1281 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"}, 1282 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "entertainment crypto"}, 1283 {PCIC_DASP, -1, "dasp"}, 1284 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"}, 1285 {0, 0, NULL} 1286 }; 1287 1288 void 1289 pci_probe_nomatch(device_t dev, device_t child) 1290 { 1291 int i; 1292 char *cp, *scp, *device; 1293 1294 /* 1295 * Look for a listing for this device in a loaded device database. 1296 */ 1297 if ((device = pci_describe_device(child)) != NULL) { 1298 device_printf(dev, "<%s>", device); 1299 free(device, M_DEVBUF); 1300 } else { 1301 /* 1302 * Scan the class/subclass descriptions for a general 1303 * description. 1304 */ 1305 cp = "unknown"; 1306 scp = NULL; 1307 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1308 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1309 if (pci_nomatch_tab[i].subclass == -1) { 1310 cp = pci_nomatch_tab[i].desc; 1311 } else if (pci_nomatch_tab[i].subclass == 1312 pci_get_subclass(child)) { 1313 scp = pci_nomatch_tab[i].desc; 1314 } 1315 } 1316 } 1317 device_printf(dev, "<%s%s%s>", 1318 cp ? cp : "", 1319 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1320 scp ? scp : ""); 1321 } 1322 printf(" at device %d.%d (no driver attached)\n", 1323 pci_get_slot(child), pci_get_function(child)); 1324 if (pci_do_powerstate) 1325 pci_cfg_save(child, 1326 (struct pci_devinfo *) device_get_ivars(child), 1); 1327 return; 1328 } 1329 1330 /* 1331 * Parse the PCI device database, if loaded, and return a pointer to a 1332 * description of the device. 1333 * 1334 * The database is flat text formatted as follows: 1335 * 1336 * Any line not in a valid format is ignored. 1337 * Lines are terminated with newline '\n' characters. 1338 * 1339 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1340 * the vendor name. 1341 * 1342 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1343 * - devices cannot be listed without a corresponding VENDOR line. 1344 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1345 * another TAB, then the device name. 1346 */ 1347 1348 /* 1349 * Assuming (ptr) points to the beginning of a line in the database, 1350 * return the vendor or device and description of the next entry. 1351 * The value of (vendor) or (device) inappropriate for the entry type 1352 * is set to -1. Returns nonzero at the end of the database. 1353 * 1354 * Note that this is slightly unrobust in the face of corrupt data; 1355 * we attempt to safeguard against this by spamming the end of the 1356 * database with a newline when we initialise. 1357 */ 1358 static int 1359 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1360 { 1361 char *cp = *ptr; 1362 int left; 1363 1364 *device = -1; 1365 *vendor = -1; 1366 **desc = '\0'; 1367 for (;;) { 1368 left = pci_vendordata_size - (cp - pci_vendordata); 1369 if (left <= 0) { 1370 *ptr = cp; 1371 return(1); 1372 } 1373 1374 /* vendor entry? */ 1375 if (*cp != '\t' && 1376 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1377 break; 1378 /* device entry? */ 1379 if (*cp == '\t' && 1380 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1381 break; 1382 1383 /* skip to next line */ 1384 while (*cp != '\n' && left > 0) { 1385 cp++; 1386 left--; 1387 } 1388 if (*cp == '\n') { 1389 cp++; 1390 left--; 1391 } 1392 } 1393 /* skip to next line */ 1394 while (*cp != '\n' && left > 0) { 1395 cp++; 1396 left--; 1397 } 1398 if (*cp == '\n' && left > 0) 1399 cp++; 1400 *ptr = cp; 1401 return(0); 1402 } 1403 1404 static char * 1405 pci_describe_device(device_t dev) 1406 { 1407 int vendor, device; 1408 char *desc, *vp, *dp, *line; 1409 1410 desc = vp = dp = NULL; 1411 1412 /* 1413 * If we have no vendor data, we can't do anything. 1414 */ 1415 if (pci_vendordata == NULL) 1416 goto out; 1417 1418 /* 1419 * Scan the vendor data looking for this device 1420 */ 1421 line = pci_vendordata; 1422 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1423 goto out; 1424 for (;;) { 1425 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1426 goto out; 1427 if (vendor == pci_get_vendor(dev)) 1428 break; 1429 } 1430 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1431 goto out; 1432 for (;;) { 1433 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1434 *dp = 0; 1435 break; 1436 } 1437 if (vendor != -1) { 1438 *dp = 0; 1439 break; 1440 } 1441 if (device == pci_get_device(dev)) 1442 break; 1443 } 1444 if (dp[0] == '\0') 1445 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1446 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1447 NULL) 1448 sprintf(desc, "%s, %s", vp, dp); 1449 out: 1450 if (vp != NULL) 1451 free(vp, M_DEVBUF); 1452 if (dp != NULL) 1453 free(dp, M_DEVBUF); 1454 return(desc); 1455 } 1456 1457 int 1458 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1459 { 1460 struct pci_devinfo *dinfo; 1461 pcicfgregs *cfg; 1462 1463 dinfo = device_get_ivars(child); 1464 cfg = &dinfo->cfg; 1465 1466 switch (which) { 1467 case PCI_IVAR_ETHADDR: 1468 /* 1469 * The generic accessor doesn't deal with failure, so 1470 * we set the return value, then return an error. 1471 */ 1472 *((uint8_t **) result) = NULL; 1473 return (EINVAL); 1474 case PCI_IVAR_SUBVENDOR: 1475 *result = cfg->subvendor; 1476 break; 1477 case PCI_IVAR_SUBDEVICE: 1478 *result = cfg->subdevice; 1479 break; 1480 case PCI_IVAR_VENDOR: 1481 *result = cfg->vendor; 1482 break; 1483 case PCI_IVAR_DEVICE: 1484 *result = cfg->device; 1485 break; 1486 case PCI_IVAR_DEVID: 1487 *result = (cfg->device << 16) | cfg->vendor; 1488 break; 1489 case PCI_IVAR_CLASS: 1490 *result = cfg->baseclass; 1491 break; 1492 case PCI_IVAR_SUBCLASS: 1493 *result = cfg->subclass; 1494 break; 1495 case PCI_IVAR_PROGIF: 1496 *result = cfg->progif; 1497 break; 1498 case PCI_IVAR_REVID: 1499 *result = cfg->revid; 1500 break; 1501 case PCI_IVAR_INTPIN: 1502 *result = cfg->intpin; 1503 break; 1504 case PCI_IVAR_IRQ: 1505 *result = cfg->intline; 1506 break; 1507 case PCI_IVAR_BUS: 1508 *result = cfg->bus; 1509 break; 1510 case PCI_IVAR_SLOT: 1511 *result = cfg->slot; 1512 break; 1513 case PCI_IVAR_FUNCTION: 1514 *result = cfg->func; 1515 break; 1516 default: 1517 return (ENOENT); 1518 } 1519 return (0); 1520 } 1521 1522 int 1523 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1524 { 1525 struct pci_devinfo *dinfo; 1526 1527 dinfo = device_get_ivars(child); 1528 1529 switch (which) { 1530 case PCI_IVAR_INTPIN: 1531 dinfo->cfg.intpin = value; 1532 return (0); 1533 case PCI_IVAR_ETHADDR: 1534 case PCI_IVAR_SUBVENDOR: 1535 case PCI_IVAR_SUBDEVICE: 1536 case PCI_IVAR_VENDOR: 1537 case PCI_IVAR_DEVICE: 1538 case PCI_IVAR_DEVID: 1539 case PCI_IVAR_CLASS: 1540 case PCI_IVAR_SUBCLASS: 1541 case PCI_IVAR_PROGIF: 1542 case PCI_IVAR_REVID: 1543 case PCI_IVAR_IRQ: 1544 case PCI_IVAR_BUS: 1545 case PCI_IVAR_SLOT: 1546 case PCI_IVAR_FUNCTION: 1547 return (EINVAL); /* disallow for now */ 1548 1549 default: 1550 return (ENOENT); 1551 } 1552 } 1553 1554 1555 #include "opt_ddb.h" 1556 #ifdef DDB 1557 #include <ddb/ddb.h> 1558 #include <sys/cons.h> 1559 1560 /* 1561 * List resources based on pci map registers, used for within ddb 1562 */ 1563 1564 DB_SHOW_COMMAND(pciregs, db_pci_dump) 1565 { 1566 struct pci_devinfo *dinfo; 1567 struct devlist *devlist_head; 1568 struct pci_conf *p; 1569 const char *name; 1570 int i, error, none_count, quit; 1571 1572 none_count = 0; 1573 /* get the head of the device queue */ 1574 devlist_head = &pci_devq; 1575 1576 /* 1577 * Go through the list of devices and print out devices 1578 */ 1579 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 1580 for (error = 0, i = 0, quit = 0, 1581 dinfo = STAILQ_FIRST(devlist_head); 1582 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1583 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1584 1585 /* Populate pd_name and pd_unit */ 1586 name = NULL; 1587 if (dinfo->cfg.dev) 1588 name = device_get_name(dinfo->cfg.dev); 1589 1590 p = &dinfo->conf; 1591 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1592 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1593 (name && *name) ? name : "none", 1594 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1595 none_count++, 1596 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1597 p->pc_sel.pc_func, (p->pc_class << 16) | 1598 (p->pc_subclass << 8) | p->pc_progif, 1599 (p->pc_subdevice << 16) | p->pc_subvendor, 1600 (p->pc_device << 16) | p->pc_vendor, 1601 p->pc_revid, p->pc_hdr); 1602 } 1603 } 1604 #endif /* DDB */ 1605 1606 static struct resource * 1607 pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1608 u_long start, u_long end, u_long count, u_int flags) 1609 { 1610 struct pci_devinfo *dinfo = device_get_ivars(child); 1611 struct resource_list *rl = &dinfo->resources; 1612 struct resource_list_entry *rle; 1613 struct resource *res; 1614 uint32_t map, testval; 1615 int mapsize; 1616 1617 /* 1618 * Weed out the bogons, and figure out how large the BAR/map 1619 * is. Bars that read back 0 here are bogus and unimplemented. 1620 * Note: atapci in legacy mode are special and handled elsewhere 1621 * in the code. If you have a atapci device in legacy mode and 1622 * it fails here, that other code is broken. 1623 */ 1624 res = NULL; 1625 map = pci_read_config(child, *rid, 4); 1626 pci_write_config(child, *rid, 0xffffffff, 4); 1627 testval = pci_read_config(child, *rid, 4); 1628 if (testval == 0) 1629 return (NULL); 1630 if (pci_maptype(testval) & PCI_MAPMEM) { 1631 if (type != SYS_RES_MEMORY) { 1632 if (bootverbose) 1633 device_printf(child, 1634 "rid %#x is memory, requested %d\n", 1635 *rid, type); 1636 goto out; 1637 } 1638 } else { 1639 if (type != SYS_RES_IOPORT) { 1640 if (bootverbose) 1641 device_printf(child, 1642 "rid %#x is ioport, requested %d\n", 1643 *rid, type); 1644 goto out; 1645 } 1646 } 1647 /* 1648 * For real BARs, we need to override the size that 1649 * the driver requests, because that's what the BAR 1650 * actually uses and we would otherwise have a 1651 * situation where we might allocate the excess to 1652 * another driver, which won't work. 1653 */ 1654 mapsize = pci_mapsize(testval); 1655 count = 1 << mapsize; 1656 if (RF_ALIGNMENT(flags) < mapsize) 1657 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1658 1659 /* 1660 * Allocate enough resource, and then write back the 1661 * appropriate bar for that resource. 1662 */ 1663 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1664 start, end, count, flags); 1665 if (res == NULL) { 1666 device_printf(child, "%#lx bytes of rid %#x res %d failed.\n", 1667 count, *rid, type); 1668 goto out; 1669 } 1670 resource_list_add(rl, type, *rid, start, end, count); 1671 rle = resource_list_find(rl, type, *rid); 1672 if (rle == NULL) 1673 panic("pci_alloc_map: unexpectedly can't find resource."); 1674 rle->res = res; 1675 if (bootverbose) 1676 device_printf(child, 1677 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1678 count, *rid, type, rman_get_start(res)); 1679 map = rman_get_start(res); 1680 out:; 1681 pci_write_config(child, *rid, map, 4); 1682 return (res); 1683 } 1684 1685 1686 struct resource * 1687 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1688 u_long start, u_long end, u_long count, u_int flags) 1689 { 1690 struct pci_devinfo *dinfo = device_get_ivars(child); 1691 struct resource_list *rl = &dinfo->resources; 1692 struct resource_list_entry *rle; 1693 pcicfgregs *cfg = &dinfo->cfg; 1694 1695 /* 1696 * Perform lazy resource allocation 1697 */ 1698 if (device_get_parent(child) == dev) { 1699 switch (type) { 1700 case SYS_RES_IRQ: 1701 /* 1702 * If the child device doesn't have an 1703 * interrupt routed and is deserving of an 1704 * interrupt, try to assign it one. 1705 */ 1706 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1707 (cfg->intpin != 0)) { 1708 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1709 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1710 pci_write_config(child, PCIR_INTLINE, 1711 cfg->intline, 1); 1712 resource_list_add(rl, SYS_RES_IRQ, 0, 1713 cfg->intline, cfg->intline, 1); 1714 } 1715 } 1716 break; 1717 case SYS_RES_IOPORT: 1718 case SYS_RES_MEMORY: 1719 if (*rid < PCIR_BAR(cfg->nummaps)) { 1720 /* 1721 * Enable the I/O mode. We should 1722 * also be assigning resources too 1723 * when none are present. The 1724 * resource_list_alloc kind of sorta does 1725 * this... 1726 */ 1727 if (PCI_ENABLE_IO(dev, child, type)) 1728 return (NULL); 1729 } 1730 rle = resource_list_find(rl, type, *rid); 1731 if (rle == NULL) 1732 return (pci_alloc_map(dev, child, type, rid, 1733 start, end, count, flags)); 1734 break; 1735 } 1736 /* 1737 * If we've already allocated the resource, then 1738 * return it now. But first we may need to activate 1739 * it, since we don't allocate the resource as active 1740 * above. Normally this would be done down in the 1741 * nexus, but since we short-circuit that path we have 1742 * to do its job here. Not sure if we should free the 1743 * resource if it fails to activate. 1744 */ 1745 rle = resource_list_find(rl, type, *rid); 1746 if (rle != NULL && rle->res != NULL) { 1747 if (bootverbose) 1748 device_printf(child, 1749 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 1750 rman_get_size(rle->res), *rid, type, 1751 rman_get_start(rle->res)); 1752 if ((flags & RF_ACTIVE) && 1753 bus_generic_activate_resource(dev, child, type, 1754 *rid, rle->res) != 0) 1755 return NULL; 1756 return (rle->res); 1757 } 1758 } 1759 return (resource_list_alloc(rl, dev, child, type, rid, 1760 start, end, count, flags)); 1761 } 1762 1763 void 1764 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1765 { 1766 struct pci_devinfo *dinfo; 1767 struct resource_list *rl; 1768 struct resource_list_entry *rle; 1769 1770 if (device_get_parent(child) != dev) 1771 return; 1772 1773 dinfo = device_get_ivars(child); 1774 rl = &dinfo->resources; 1775 rle = resource_list_find(rl, type, rid); 1776 if (rle) { 1777 if (rle->res) { 1778 if (rman_get_device(rle->res) != dev || 1779 rman_get_flags(rle->res) & RF_ACTIVE) { 1780 device_printf(dev, "delete_resource: " 1781 "Resource still owned by child, oops. " 1782 "(type=%d, rid=%d, addr=%lx)\n", 1783 rle->type, rle->rid, 1784 rman_get_start(rle->res)); 1785 return; 1786 } 1787 bus_release_resource(dev, type, rid, rle->res); 1788 } 1789 resource_list_delete(rl, type, rid); 1790 } 1791 /* 1792 * Why do we turn off the PCI configuration BAR when we delete a 1793 * resource? -- imp 1794 */ 1795 pci_write_config(child, rid, 0, 4); 1796 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1797 } 1798 1799 struct resource_list * 1800 pci_get_resource_list (device_t dev, device_t child) 1801 { 1802 struct pci_devinfo *dinfo = device_get_ivars(child); 1803 1804 return (&dinfo->resources); 1805 } 1806 1807 uint32_t 1808 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1809 { 1810 struct pci_devinfo *dinfo = device_get_ivars(child); 1811 pcicfgregs *cfg = &dinfo->cfg; 1812 1813 return (PCIB_READ_CONFIG(device_get_parent(dev), 1814 cfg->bus, cfg->slot, cfg->func, reg, width)); 1815 } 1816 1817 void 1818 pci_write_config_method(device_t dev, device_t child, int reg, 1819 uint32_t val, int width) 1820 { 1821 struct pci_devinfo *dinfo = device_get_ivars(child); 1822 pcicfgregs *cfg = &dinfo->cfg; 1823 1824 PCIB_WRITE_CONFIG(device_get_parent(dev), 1825 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1826 } 1827 1828 int 1829 pci_child_location_str_method(device_t dev, device_t child, char *buf, 1830 size_t buflen) 1831 { 1832 1833 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1834 pci_get_function(child)); 1835 return (0); 1836 } 1837 1838 int 1839 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1840 size_t buflen) 1841 { 1842 struct pci_devinfo *dinfo; 1843 pcicfgregs *cfg; 1844 1845 dinfo = device_get_ivars(child); 1846 cfg = &dinfo->cfg; 1847 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1848 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1849 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1850 cfg->progif); 1851 return (0); 1852 } 1853 1854 int 1855 pci_assign_interrupt_method(device_t dev, device_t child) 1856 { 1857 struct pci_devinfo *dinfo = device_get_ivars(child); 1858 pcicfgregs *cfg = &dinfo->cfg; 1859 1860 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1861 cfg->intpin)); 1862 } 1863 1864 static int 1865 pci_modevent(module_t mod, int what, void *arg) 1866 { 1867 static struct cdev *pci_cdev; 1868 1869 switch (what) { 1870 case MOD_LOAD: 1871 STAILQ_INIT(&pci_devq); 1872 pci_generation = 0; 1873 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1874 "pci"); 1875 pci_load_vendor_data(); 1876 break; 1877 1878 case MOD_UNLOAD: 1879 destroy_dev(pci_cdev); 1880 break; 1881 } 1882 1883 return (0); 1884 } 1885 1886 void 1887 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 1888 { 1889 int i; 1890 1891 /* 1892 * Only do header type 0 devices. Type 1 devices are bridges, 1893 * which we know need special treatment. Type 2 devices are 1894 * cardbus bridges which also require special treatment. 1895 * Other types are unknown, and we err on the side of safety 1896 * by ignoring them. 1897 */ 1898 if (dinfo->cfg.hdrtype != 0) 1899 return; 1900 1901 /* 1902 * Restore the device to full power mode. We must do this 1903 * before we restore the registers because moving from D3 to 1904 * D0 will cause the chip's BARs and some other registers to 1905 * be reset to some unknown power on reset values. Cut down 1906 * the noise on boot by doing nothing if we are already in 1907 * state D0. 1908 */ 1909 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1910 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1911 } 1912 for (i = 0; i < dinfo->cfg.nummaps; i++) 1913 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 1914 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 1915 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 1916 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 1917 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 1918 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 1919 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 1920 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 1921 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 1922 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 1923 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 1924 } 1925 1926 void 1927 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 1928 { 1929 int i; 1930 uint32_t cls; 1931 int ps; 1932 1933 /* 1934 * Only do header type 0 devices. Type 1 devices are bridges, which 1935 * we know need special treatment. Type 2 devices are cardbus bridges 1936 * which also require special treatment. Other types are unknown, and 1937 * we err on the side of safety by ignoring them. Powering down 1938 * bridges should not be undertaken lightly. 1939 */ 1940 if (dinfo->cfg.hdrtype != 0) 1941 return; 1942 for (i = 0; i < dinfo->cfg.nummaps; i++) 1943 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1944 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 1945 1946 /* 1947 * Some drivers apparently write to these registers w/o updating our 1948 * cached copy. No harm happens if we update the copy, so do so here 1949 * so we can restore them. The COMMAND register is modified by the 1950 * bus w/o updating the cache. This should represent the normally 1951 * writable portion of the 'defined' part of type 0 headers. In 1952 * theory we also need to save/restore the PCI capability structures 1953 * we know about, but apart from power we don't know any that are 1954 * writable. 1955 */ 1956 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1957 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1958 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 1959 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 1960 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 1961 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 1962 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 1963 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 1964 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 1965 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1966 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1967 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 1968 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 1969 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 1970 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 1971 1972 /* 1973 * don't set the state for display devices, base peripherals and 1974 * memory devices since bad things happen when they are powered down. 1975 * We should (a) have drivers that can easily detach and (b) use 1976 * generic drivers for these devices so that some device actually 1977 * attaches. We need to make sure that when we implement (a) we don't 1978 * power the device down on a reattach. 1979 */ 1980 cls = pci_get_class(dev); 1981 if (setstate && cls != PCIC_DISPLAY && cls != PCIC_MEMORY && 1982 cls != PCIC_BASEPERIPH) { 1983 /* 1984 * PCI spec says we can only go into D3 state from D0 state. 1985 * Transition from D[12] into D0 before going to D3 state. 1986 */ 1987 ps = pci_get_powerstate(dev); 1988 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) { 1989 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1990 } 1991 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) { 1992 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 1993 } 1994 } 1995 } 1996