1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $Id: pci.c,v 1.2 1997/06/25 20:16:02 smp Exp smp $ 27 * 28 */ 29 30 #include "pci.h" 31 #if NPCI > 0 32 33 #include <stddef.h> 34 35 #include <sys/types.h> 36 #include <sys/param.h> 37 #include <sys/time.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/fcntl.h> 41 #include <sys/conf.h> 42 #include <sys/kernel.h> 43 #ifdef DEVFS 44 #include <sys/devfsext.h> 45 #endif /* DEVFS */ 46 47 #include <vm/vm.h> 48 #include <vm/pmap.h> 49 50 #include <pci/pcireg.h> 51 #include <pci/pcivar.h> 52 #include <pci/pci_ioctl.h> 53 54 #ifdef APIC_IO 55 #include <machine/smp.h> 56 #endif /* APIC_IO */ 57 58 /* return highest PCI bus number known to be used, or -1 if none */ 59 60 static int 61 pci_bushigh(void) 62 { 63 if (pci_cfgopen() == 0) 64 return (-1); 65 return (0); 66 } 67 68 /* return base address of memory or port map */ 69 70 static int 71 pci_mapbase(unsigned mapreg) 72 { 73 int mask = 0x03; 74 if ((mapreg & 0x01) == 0) 75 mask = 0x0f; 76 return (mapreg & ~mask); 77 } 78 79 /* return map type of memory or port map */ 80 81 static int 82 pci_maptype(unsigned mapreg) 83 { 84 static u_int8_t maptype[0x10] = { 85 PCI_MAPMEM, PCI_MAPPORT, 86 PCI_MAPMEM, 0, 87 PCI_MAPMEM, PCI_MAPPORT, 88 0, 0, 89 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 90 PCI_MAPMEM|PCI_MAPMEMP, 0, 91 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 92 0, 0, 93 }; 94 95 return maptype[mapreg & 0x0f]; 96 } 97 98 /* return log2 of map size decoded for memory or port map */ 99 100 static int 101 pci_mapsize(unsigned testval) 102 { 103 int ln2size; 104 105 testval = pci_mapbase(testval); 106 ln2size = 0; 107 if (testval != 0) { 108 while ((testval & 1) == 0) 109 { 110 ln2size++; 111 testval >>= 1; 112 } 113 } 114 return (ln2size); 115 } 116 117 /* return log2 of address range supported by map register */ 118 119 static int 120 pci_maprange(unsigned mapreg) 121 { 122 int ln2range = 0; 123 switch (mapreg & 0x07) { 124 case 0x00: 125 case 0x01: 126 case 0x05: 127 ln2range = 32; 128 break; 129 case 0x02: 130 ln2range = 20; 131 break; 132 case 0x04: 133 ln2range = 64; 134 break; 135 } 136 return (ln2range); 137 } 138 139 /* extract map parameters into newly allocated array of pcimap structures */ 140 141 static pcimap * 142 pci_readmaps(pcicfgregs *cfg, int maxmaps) 143 { 144 int i; 145 pcimap *map; 146 int map64 = 0; 147 148 for (i = 0; i < maxmaps; i++) { 149 int reg = PCIR_MAPS + i*4; 150 u_int32_t base; 151 u_int32_t ln2range; 152 153 base = pci_cfgread(cfg, reg, 4); 154 ln2range = pci_maprange(base); 155 156 if (base == 0 || ln2range == 0) 157 maxmaps = i; 158 else if (ln2range > 32) 159 i++; 160 } 161 162 map = malloc(maxmaps * sizeof (pcimap), M_DEVBUF, M_WAITOK); 163 if (map != NULL) { 164 bzero(map, sizeof(pcimap) * maxmaps); 165 166 for (i = 0; i < maxmaps; i++) { 167 int reg = PCIR_MAPS + i*4; 168 u_int32_t base; 169 u_int32_t testval; 170 171 base = pci_cfgread(cfg, reg, 4); 172 173 if (map64 == 0) { 174 pci_cfgwrite(cfg, reg, 0xffffffff, 4); 175 testval = pci_cfgread(cfg, reg, 4); 176 pci_cfgwrite(cfg, reg, base, 4); 177 178 map[i].base = pci_mapbase(base); 179 map[i].type = pci_maptype(base); 180 map[i].ln2size = pci_mapsize(testval); 181 map[i].ln2range = pci_maprange(testval); 182 map64 = map[i].ln2range == 64; 183 } else { 184 /* only fill in base, other fields are 0 */ 185 map[i].base = base; 186 map64 = 0; 187 } 188 } 189 cfg->nummaps = maxmaps; 190 } 191 return (map); 192 } 193 194 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 195 196 static void 197 pci_fixancient(pcicfgregs *cfg) 198 { 199 if (cfg->hdrtype != 0) 200 return; 201 202 /* PCI to PCI bridges use header type 1 */ 203 if (cfg->class == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 204 cfg->hdrtype = 1; 205 } 206 207 /* read config data specific to header type 1 device (PCI to PCI bridge) */ 208 209 static void * 210 pci_readppb(pcicfgregs *cfg) 211 { 212 pcih1cfgregs *p; 213 214 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK); 215 if (p == NULL) 216 return (NULL); 217 218 bzero(p, sizeof *p); 219 220 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_1, 2); 221 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_1, 2); 222 223 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_1, 1); 224 225 p->iobase = PCI_PPBIOBASE (pci_cfgread(cfg, PCIR_IOBASEH_1, 2), 226 pci_cfgread(cfg, PCIR_IOBASEL_1, 1)); 227 p->iolimit = PCI_PPBIOLIMIT (pci_cfgread(cfg, PCIR_IOLIMITH_1, 2), 228 pci_cfgread(cfg, PCIR_IOLIMITL_1, 1)); 229 230 p->membase = PCI_PPBMEMBASE (0, 231 pci_cfgread(cfg, PCIR_MEMBASE_1, 2)); 232 p->memlimit = PCI_PPBMEMLIMIT (0, 233 pci_cfgread(cfg, PCIR_MEMLIMIT_1, 2)); 234 235 p->pmembase = PCI_PPBMEMBASE ( 236 (pci_addr_t)pci_cfgread(cfg, PCIR_PMBASEH_1, 4), 237 pci_cfgread(cfg, PCIR_PMBASEL_1, 2)); 238 239 p->pmemlimit = PCI_PPBMEMLIMIT ( 240 (pci_addr_t)pci_cfgread(cfg, PCIR_PMLIMITH_1, 4), 241 pci_cfgread(cfg, PCIR_PMLIMITL_1, 2)); 242 return (p); 243 } 244 245 /* read config data specific to header type 2 device (PCI to CardBus bridge) */ 246 247 static void * 248 pci_readpcb(pcicfgregs *cfg) 249 { 250 pcih2cfgregs *p; 251 252 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK); 253 if (p == NULL) 254 return (NULL); 255 256 bzero(p, sizeof *p); 257 258 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_2, 2); 259 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_2, 2); 260 261 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_2, 1); 262 263 p->membase0 = pci_cfgread(cfg, PCIR_MEMBASE0_2, 4); 264 p->memlimit0 = pci_cfgread(cfg, PCIR_MEMLIMIT0_2, 4); 265 p->membase1 = pci_cfgread(cfg, PCIR_MEMBASE1_2, 4); 266 p->memlimit1 = pci_cfgread(cfg, PCIR_MEMLIMIT1_2, 4); 267 268 p->iobase0 = pci_cfgread(cfg, PCIR_IOBASE0_2, 4); 269 p->iolimit0 = pci_cfgread(cfg, PCIR_IOLIMIT0_2, 4); 270 p->iobase1 = pci_cfgread(cfg, PCIR_IOBASE1_2, 4); 271 p->iolimit1 = pci_cfgread(cfg, PCIR_IOLIMIT1_2, 4); 272 273 p->pccardif = pci_cfgread(cfg, PCIR_PCCARDIF_2, 4); 274 return p; 275 } 276 277 /* extract header type specific config data */ 278 279 static void 280 pci_hdrtypedata(pcicfgregs *cfg) 281 { 282 switch (cfg->hdrtype) { 283 case 0: 284 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_0, 2); 285 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_0, 2); 286 cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_0); 287 break; 288 case 1: 289 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_1, 2); 290 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_1, 2); 291 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_1, 1); 292 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_1, 1); 293 cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_1); 294 cfg->hdrspec = pci_readppb(cfg); 295 break; 296 case 2: 297 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_2, 2); 298 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_2, 2); 299 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_2, 1); 300 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_2, 1); 301 cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_2); 302 cfg->hdrspec = pci_readpcb(cfg); 303 break; 304 } 305 } 306 307 /* read configuration header into pcicfgrect structure */ 308 309 static pcicfgregs * 310 pci_readcfg(pcicfgregs *probe) 311 { 312 pcicfgregs *cfg = NULL; 313 314 if (pci_cfgread(probe, PCIR_DEVVENDOR, 4) != -1) { 315 cfg = malloc(sizeof (pcicfgregs), M_DEVBUF, M_WAITOK); 316 if (cfg == NULL) 317 return (cfg); 318 319 bzero(cfg, sizeof *cfg); 320 321 cfg->bus = probe->bus; 322 cfg->slot = probe->slot; 323 cfg->func = probe->func; 324 cfg->parent = probe->parent; 325 326 cfg->vendor = pci_cfgread(cfg, PCIR_VENDOR, 2); 327 cfg->device = pci_cfgread(cfg, PCIR_DEVICE, 2); 328 cfg->cmdreg = pci_cfgread(cfg, PCIR_COMMAND, 2); 329 cfg->statreg = pci_cfgread(cfg, PCIR_STATUS, 2); 330 cfg->class = pci_cfgread(cfg, PCIR_CLASS, 1); 331 cfg->subclass = pci_cfgread(cfg, PCIR_SUBCLASS, 1); 332 cfg->progif = pci_cfgread(cfg, PCIR_PROGIF, 1); 333 cfg->revid = pci_cfgread(cfg, PCIR_REVID, 1); 334 cfg->hdrtype = pci_cfgread(cfg, PCIR_HEADERTYPE, 1); 335 cfg->cachelnsz = pci_cfgread(cfg, PCIR_CACHELNSZ, 1); 336 cfg->lattimer = pci_cfgread(cfg, PCIR_LATTIMER, 1); 337 cfg->intpin = pci_cfgread(cfg, PCIR_INTPIN, 1); 338 cfg->intline = pci_cfgread(cfg, PCIR_INTLINE, 1); 339 340 #ifdef APIC_IO 341 if (cfg->intpin != 0) { 342 int airq; 343 344 airq = pci_apic_pin(cfg->bus, cfg->slot, cfg->intpin); 345 if ((airq >= 0) && (airq != cfg->intline)) { 346 undirect_pci_irq(cfg->intline); 347 cfg->intline = airq; 348 } 349 } 350 #endif /* APIC_IO */ 351 352 cfg->mingnt = pci_cfgread(cfg, PCIR_MINGNT, 1); 353 cfg->maxlat = pci_cfgread(cfg, PCIR_MAXLAT, 1); 354 355 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 356 cfg->hdrtype &= ~PCIM_MFDEV; 357 358 pci_fixancient(cfg); 359 pci_hdrtypedata(cfg); 360 } 361 return (cfg); 362 } 363 364 /* free pcicfgregs structure and all depending data structures */ 365 366 static int 367 pci_freecfg(pcicfgregs *cfg) 368 { 369 if (cfg->hdrspec != NULL) 370 free(cfg->hdrspec, M_DEVBUF); 371 if (cfg->map != NULL) 372 free(cfg->map, M_DEVBUF); 373 free(cfg, M_DEVBUF); 374 return (0); 375 } 376 377 static void 378 pci_addcfg(pcicfgregs *cfg) 379 { 380 if (bootverbose) { 381 int i; 382 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 383 cfg->vendor, cfg->device, cfg->revid); 384 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 385 cfg->class, cfg->subclass, cfg->progif, cfg->hdrtype, cfg->mfdev); 386 #ifdef PCI_DEBUG 387 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 388 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 389 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 390 cfg->lattimer, cfg->lattimer * 30, 391 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 392 #endif /* PCI_DEBUG */ 393 if (cfg->intpin > 0) 394 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 395 396 for (i = 0; i < cfg->nummaps; i++) { 397 pcimap *m = &cfg->map[i]; 398 printf("\tmap[%d]: type %x, range %2d, base %08x, size %2d\n", 399 i, m->type, m->ln2range, m->base, m->ln2size); 400 } 401 } 402 pci_drvattach(cfg); /* XXX currently defined in pci_compat.c */ 403 } 404 405 /* return pointer to device that is a bridge to this bus */ 406 407 static pcicfgregs * 408 pci_bridgeto(int bus) 409 { 410 return (NULL); /* XXX not yet implemented */ 411 } 412 413 /* scan one PCI bus for devices */ 414 415 static int 416 pci_probebus(int bus) 417 { 418 pcicfgregs probe; 419 int bushigh = bus; 420 421 bzero(&probe, sizeof probe); 422 probe.parent = pci_bridgeto(bus); 423 probe.bus = bus; 424 for (probe.slot = 0; probe.slot <= PCI_SLOTMAX; probe.slot++) { 425 int pcifunchigh = 0; 426 for (probe.func = 0; probe.func <= pcifunchigh; probe.func++) { 427 pcicfgregs *cfg = pci_readcfg(&probe); 428 if (cfg != NULL) { 429 if (cfg->mfdev) 430 pcifunchigh = 7; 431 /* 432 * XXX: Temporarily move pci_addcfg() up before 433 * the use of cfg->subordinatebus. This is 434 * necessary, since pci_addcfg() calls the 435 * device's probe(), which may read the bus# 436 * from some device dependent register of 437 * some host to PCI bridges. The probe will 438 * eventually be moved to pci_readcfg(), and 439 * pci_addcfg() will then be moved back down 440 * below the conditional statement ... 441 */ 442 pci_addcfg(cfg); 443 444 if (bushigh < cfg->subordinatebus) 445 bushigh = cfg->subordinatebus; 446 447 cfg = NULL; /* we don't own this anymore ... */ 448 } 449 } 450 } 451 return (bushigh); 452 } 453 454 /* scan a PCI bus tree reached through one PCI attachment point */ 455 456 int 457 pci_probe(pciattach *parent) 458 { 459 int bushigh; 460 int bus = 0; 461 462 bushigh = pci_bushigh(); 463 while (bus <= bushigh) { 464 int newbushigh; 465 466 printf("Probing for devices on PCI bus %d:\n", bus); 467 newbushigh = pci_probebus(bus); 468 469 if (bushigh < newbushigh) 470 bushigh = newbushigh; 471 bus++; 472 } 473 return (bushigh); 474 } 475 476 /* 477 * This is the user interface to PCI configuration space. 478 */ 479 480 static int 481 pci_open(dev_t dev, int oflags, int devtype, struct proc *p) 482 { 483 if ((oflags & FWRITE) && securelevel > 0) { 484 return EPERM; 485 } 486 return 0; 487 } 488 489 static int 490 pci_close(dev_t dev, int flag, int devtype, struct proc *p) 491 { 492 return 0; 493 } 494 495 static int 496 pci_ioctl(dev_t dev, int cmd, caddr_t data, int flag, struct proc *p) 497 { 498 struct pci_conf_io *cio; 499 struct pci_io *io; 500 size_t iolen; 501 int error; 502 503 if (cmd != PCIOCGETCONF && !(flag & FWRITE)) 504 return EPERM; 505 506 switch(cmd) { 507 case PCIOCGETCONF: 508 #ifdef NOTYET 509 static struct pci_conf *pci_dev_list; 510 static unsigned pci_dev_list_count; 511 static unsigned pci_dev_list_size; 512 513 cio = (struct pci_conf_io *)data; 514 iolen = min(cio->pci_len, 515 pci_dev_list_count * sizeof(struct pci_conf)); 516 cio->pci_len = pci_dev_list_count * sizeof(struct pci_conf); 517 518 error = copyout(pci_dev_list, cio->pci_buf, iolen); 519 #else 520 error = ENODEV; 521 #endif 522 break; 523 524 case PCIOCREAD: 525 io = (struct pci_io *)data; 526 switch(io->pi_width) { 527 pcicfgregs probe; 528 case 4: 529 case 2: 530 case 1: 531 probe.bus = io->pi_sel.pc_bus; 532 probe.slot = io->pi_sel.pc_dev; 533 probe.func = io->pi_sel.pc_func; 534 io->pi_data = pci_cfgread(&probe, 535 io->pi_reg, io->pi_width); 536 error = 0; 537 break; 538 default: 539 error = ENODEV; 540 break; 541 } 542 break; 543 544 case PCIOCWRITE: 545 io = (struct pci_io *)data; 546 switch(io->pi_width) { 547 pcicfgregs probe; 548 case 4: 549 case 2: 550 case 1: 551 probe.bus = io->pi_sel.pc_bus; 552 probe.slot = io->pi_sel.pc_dev; 553 probe.func = io->pi_sel.pc_func; 554 pci_cfgwrite(&probe, 555 io->pi_reg, io->pi_data, io->pi_width); 556 error = 0; 557 break; 558 default: 559 error = ENODEV; 560 break; 561 } 562 break; 563 564 default: 565 error = ENOTTY; 566 break; 567 } 568 569 return (error); 570 } 571 572 #define PCI_CDEV 78 573 574 static struct cdevsw pcicdev = { 575 pci_open, pci_close, noread, nowrite, pci_ioctl, nostop, noreset, 576 nodevtotty, noselect, nommap, nostrategy, "pci", 0, PCI_CDEV 577 }; 578 579 #ifdef DEVFS 580 static void *pci_devfs_token; 581 #endif 582 583 static void 584 pci_cdevinit(void *dummy) 585 { 586 dev_t dev; 587 588 dev = makedev(PCI_CDEV, 0); 589 cdevsw_add(&dev, &pcicdev, NULL); 590 #ifdef DEVFS 591 pci_devfs_token = devfs_add_devswf(&pcicdev, 0, DV_CHR, 592 UID_ROOT, GID_WHEEL, 0644, "pci"); 593 #endif 594 } 595 596 SYSINIT(pcidev, SI_SUB_DRIVERS, SI_ORDER_MIDDLE+PCI_CDEV, pci_cdevinit, NULL); 597 598 #endif /* NPCI > 0 */ 599