1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/limits.h> 39 #include <sys/linker.h> 40 #include <sys/fcntl.h> 41 #include <sys/conf.h> 42 #include <sys/kernel.h> 43 #include <sys/queue.h> 44 #include <sys/sysctl.h> 45 #include <sys/endian.h> 46 47 #include <vm/vm.h> 48 #include <vm/pmap.h> 49 #include <vm/vm_extern.h> 50 51 #include <sys/bus.h> 52 #include <machine/bus.h> 53 #include <sys/rman.h> 54 #include <machine/resource.h> 55 #include <machine/stdarg.h> 56 57 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 58 #include <machine/intr_machdep.h> 59 #endif 60 61 #include <sys/pciio.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pci_private.h> 65 66 #include <dev/usb/controller/xhcireg.h> 67 #include <dev/usb/controller/ehcireg.h> 68 #include <dev/usb/controller/ohcireg.h> 69 #include <dev/usb/controller/uhcireg.h> 70 71 #include "pcib_if.h" 72 #include "pci_if.h" 73 74 #define PCIR_IS_BIOS(cfg, reg) \ 75 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ 76 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) 77 78 static int pci_has_quirk(uint32_t devid, int quirk); 79 static pci_addr_t pci_mapbase(uint64_t mapreg); 80 static const char *pci_maptype(uint64_t mapreg); 81 static int pci_mapsize(uint64_t testval); 82 static int pci_maprange(uint64_t mapreg); 83 static pci_addr_t pci_rombase(uint64_t mapreg); 84 static int pci_romsize(uint64_t testval); 85 static void pci_fixancient(pcicfgregs *cfg); 86 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...); 87 88 static int pci_porten(device_t dev); 89 static int pci_memen(device_t dev); 90 static void pci_assign_interrupt(device_t bus, device_t dev, 91 int force_route); 92 static int pci_add_map(device_t bus, device_t dev, int reg, 93 struct resource_list *rl, int force, int prefetch); 94 static int pci_probe(device_t dev); 95 static int pci_attach(device_t dev); 96 #ifdef PCI_RES_BUS 97 static int pci_detach(device_t dev); 98 #endif 99 static void pci_load_vendor_data(void); 100 static int pci_describe_parse_line(char **ptr, int *vendor, 101 int *device, char **desc); 102 static char *pci_describe_device(device_t dev); 103 static int pci_modevent(module_t mod, int what, void *arg); 104 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 105 pcicfgregs *cfg); 106 static void pci_read_cap(device_t pcib, pcicfgregs *cfg); 107 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 108 int reg, uint32_t *data); 109 #if 0 110 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 111 int reg, uint32_t data); 112 #endif 113 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 114 static void pci_mask_msix(device_t dev, u_int index); 115 static void pci_unmask_msix(device_t dev, u_int index); 116 static int pci_msi_blacklisted(void); 117 static int pci_msix_blacklisted(void); 118 static void pci_resume_msi(device_t dev); 119 static void pci_resume_msix(device_t dev); 120 static int pci_remap_intr_method(device_t bus, device_t dev, 121 u_int irq); 122 123 static uint16_t pci_get_rid_method(device_t dev, device_t child); 124 125 static device_method_t pci_methods[] = { 126 /* Device interface */ 127 DEVMETHOD(device_probe, pci_probe), 128 DEVMETHOD(device_attach, pci_attach), 129 #ifdef PCI_RES_BUS 130 DEVMETHOD(device_detach, pci_detach), 131 #else 132 DEVMETHOD(device_detach, bus_generic_detach), 133 #endif 134 DEVMETHOD(device_shutdown, bus_generic_shutdown), 135 DEVMETHOD(device_suspend, bus_generic_suspend), 136 DEVMETHOD(device_resume, pci_resume), 137 138 /* Bus interface */ 139 DEVMETHOD(bus_print_child, pci_print_child), 140 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 141 DEVMETHOD(bus_read_ivar, pci_read_ivar), 142 DEVMETHOD(bus_write_ivar, pci_write_ivar), 143 DEVMETHOD(bus_driver_added, pci_driver_added), 144 DEVMETHOD(bus_setup_intr, pci_setup_intr), 145 DEVMETHOD(bus_teardown_intr, pci_teardown_intr), 146 147 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag), 148 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 149 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 150 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 151 DEVMETHOD(bus_delete_resource, pci_delete_resource), 152 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 153 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 154 DEVMETHOD(bus_release_resource, pci_release_resource), 155 DEVMETHOD(bus_activate_resource, pci_activate_resource), 156 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource), 157 DEVMETHOD(bus_child_detached, pci_child_detached), 158 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 159 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 160 DEVMETHOD(bus_remap_intr, pci_remap_intr_method), 161 DEVMETHOD(bus_suspend_child, pci_suspend_child), 162 DEVMETHOD(bus_resume_child, pci_resume_child), 163 164 /* PCI interface */ 165 DEVMETHOD(pci_read_config, pci_read_config_method), 166 DEVMETHOD(pci_write_config, pci_write_config_method), 167 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 168 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 169 DEVMETHOD(pci_enable_io, pci_enable_io_method), 170 DEVMETHOD(pci_disable_io, pci_disable_io_method), 171 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 172 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 173 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 174 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 175 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 176 DEVMETHOD(pci_find_cap, pci_find_cap_method), 177 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 178 DEVMETHOD(pci_find_htcap, pci_find_htcap_method), 179 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 180 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), 181 DEVMETHOD(pci_enable_msi, pci_enable_msi_method), 182 DEVMETHOD(pci_enable_msix, pci_enable_msix_method), 183 DEVMETHOD(pci_disable_msi, pci_disable_msi_method), 184 DEVMETHOD(pci_remap_msix, pci_remap_msix_method), 185 DEVMETHOD(pci_release_msi, pci_release_msi_method), 186 DEVMETHOD(pci_msi_count, pci_msi_count_method), 187 DEVMETHOD(pci_msix_count, pci_msix_count_method), 188 DEVMETHOD(pci_get_rid, pci_get_rid_method), 189 DEVMETHOD(pci_child_added, pci_child_added_method), 190 191 DEVMETHOD_END 192 }; 193 194 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc)); 195 196 static devclass_t pci_devclass; 197 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL); 198 MODULE_VERSION(pci, 1); 199 200 static char *pci_vendordata; 201 static size_t pci_vendordata_size; 202 203 struct pci_quirk { 204 uint32_t devid; /* Vendor/device of the card */ 205 int type; 206 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 207 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */ 208 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */ 209 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */ 210 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */ 211 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */ 212 int arg1; 213 int arg2; 214 }; 215 216 static const struct pci_quirk pci_quirks[] = { 217 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */ 218 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 219 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 220 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 221 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 222 223 /* 224 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge 225 * or the CMIC-SL (AKA ServerWorks GC_LE). 226 */ 227 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 228 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 229 230 /* 231 * MSI doesn't work on earlier Intel chipsets including 232 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855. 233 */ 234 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 235 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 236 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 237 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 238 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 239 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 240 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 241 242 /* 243 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX 244 * bridge. 245 */ 246 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 247 248 /* 249 * MSI-X allocation doesn't work properly for devices passed through 250 * by VMware up to at least ESXi 5.1. 251 */ 252 { 0x079015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCI/PCI-X */ 253 { 0x07a015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCIe */ 254 255 /* 256 * Some virtualization environments emulate an older chipset 257 * but support MSI just fine. QEMU uses the Intel 82440. 258 */ 259 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 }, 260 261 /* 262 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus 263 * controller depending on SoftPciRst register (PM_IO 0x55 [7]). 264 * It prevents us from attaching hpet(4) when the bit is unset. 265 * Note this quirk only affects SB600 revision A13 and earlier. 266 * For SB600 A21 and later, firmware must set the bit to hide it. 267 * For SB700 and later, it is unused and hardcoded to zero. 268 */ 269 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 }, 270 271 /* 272 * Atheros AR8161/AR8162/E2200 Ethernet controllers have a bug that 273 * MSI interrupt does not assert if PCIM_CMD_INTxDIS bit of the 274 * command register is set. 275 */ 276 { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 277 { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 278 { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 279 280 /* 281 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't 282 * issue MSI interrupts with PCIM_CMD_INTxDIS set either. 283 */ 284 { 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */ 285 { 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */ 286 { 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */ 287 { 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */ 288 { 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */ 289 { 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */ 290 291 { 0 } 292 }; 293 294 /* map register information */ 295 #define PCI_MAPMEM 0x01 /* memory map */ 296 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 297 #define PCI_MAPPORT 0x04 /* port map */ 298 299 struct devlist pci_devq; 300 uint32_t pci_generation; 301 uint32_t pci_numdevs = 0; 302 static int pcie_chipset, pcix_chipset; 303 304 /* sysctl vars */ 305 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 306 307 static int pci_enable_io_modes = 1; 308 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RWTUN, 309 &pci_enable_io_modes, 1, 310 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 311 enable these bits correctly. We'd like to do this all the time, but there\n\ 312 are some peripherals that this causes problems with."); 313 314 static int pci_do_realloc_bars = 0; 315 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RWTUN, 316 &pci_do_realloc_bars, 0, 317 "Attempt to allocate a new range for any BARs whose original " 318 "firmware-assigned ranges fail to allocate during the initial device scan."); 319 320 static int pci_do_power_nodriver = 0; 321 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RWTUN, 322 &pci_do_power_nodriver, 0, 323 "Place a function into D3 state when no driver attaches to it. 0 means\n\ 324 disable. 1 means conservatively place devices into D3 state. 2 means\n\ 325 agressively place devices into D3 state. 3 means put absolutely everything\n\ 326 in D3 state."); 327 328 int pci_do_power_resume = 1; 329 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RWTUN, 330 &pci_do_power_resume, 1, 331 "Transition from D3 -> D0 on resume."); 332 333 int pci_do_power_suspend = 1; 334 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RWTUN, 335 &pci_do_power_suspend, 1, 336 "Transition from D0 -> D3 on suspend."); 337 338 static int pci_do_msi = 1; 339 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RWTUN, &pci_do_msi, 1, 340 "Enable support for MSI interrupts"); 341 342 static int pci_do_msix = 1; 343 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RWTUN, &pci_do_msix, 1, 344 "Enable support for MSI-X interrupts"); 345 346 static int pci_honor_msi_blacklist = 1; 347 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RDTUN, 348 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X"); 349 350 #if defined(__i386__) || defined(__amd64__) 351 static int pci_usb_takeover = 1; 352 #else 353 static int pci_usb_takeover = 0; 354 #endif 355 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN, 356 &pci_usb_takeover, 1, "Enable early takeover of USB controllers.\n\ 357 Disable this if you depend on BIOS emulation of USB devices, that is\n\ 358 you use USB devices (like keyboard or mouse) but do not load USB drivers"); 359 360 static int pci_clear_bars; 361 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0, 362 "Ignore firmware-assigned resources for BARs."); 363 364 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 365 static int pci_clear_buses; 366 SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0, 367 "Ignore firmware-assigned bus numbers."); 368 #endif 369 370 static int pci_enable_ari = 1; 371 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari, 372 0, "Enable support for PCIe Alternative RID Interpretation"); 373 374 static int 375 pci_has_quirk(uint32_t devid, int quirk) 376 { 377 const struct pci_quirk *q; 378 379 for (q = &pci_quirks[0]; q->devid; q++) { 380 if (q->devid == devid && q->type == quirk) 381 return (1); 382 } 383 return (0); 384 } 385 386 /* Find a device_t by bus/slot/function in domain 0 */ 387 388 device_t 389 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 390 { 391 392 return (pci_find_dbsf(0, bus, slot, func)); 393 } 394 395 /* Find a device_t by domain/bus/slot/function */ 396 397 device_t 398 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func) 399 { 400 struct pci_devinfo *dinfo; 401 402 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 403 if ((dinfo->cfg.domain == domain) && 404 (dinfo->cfg.bus == bus) && 405 (dinfo->cfg.slot == slot) && 406 (dinfo->cfg.func == func)) { 407 return (dinfo->cfg.dev); 408 } 409 } 410 411 return (NULL); 412 } 413 414 /* Find a device_t by vendor/device ID */ 415 416 device_t 417 pci_find_device(uint16_t vendor, uint16_t device) 418 { 419 struct pci_devinfo *dinfo; 420 421 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 422 if ((dinfo->cfg.vendor == vendor) && 423 (dinfo->cfg.device == device)) { 424 return (dinfo->cfg.dev); 425 } 426 } 427 428 return (NULL); 429 } 430 431 device_t 432 pci_find_class(uint8_t class, uint8_t subclass) 433 { 434 struct pci_devinfo *dinfo; 435 436 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 437 if (dinfo->cfg.baseclass == class && 438 dinfo->cfg.subclass == subclass) { 439 return (dinfo->cfg.dev); 440 } 441 } 442 443 return (NULL); 444 } 445 446 static int 447 pci_printf(pcicfgregs *cfg, const char *fmt, ...) 448 { 449 va_list ap; 450 int retval; 451 452 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, 453 cfg->func); 454 va_start(ap, fmt); 455 retval += vprintf(fmt, ap); 456 va_end(ap); 457 return (retval); 458 } 459 460 /* return base address of memory or port map */ 461 462 static pci_addr_t 463 pci_mapbase(uint64_t mapreg) 464 { 465 466 if (PCI_BAR_MEM(mapreg)) 467 return (mapreg & PCIM_BAR_MEM_BASE); 468 else 469 return (mapreg & PCIM_BAR_IO_BASE); 470 } 471 472 /* return map type of memory or port map */ 473 474 static const char * 475 pci_maptype(uint64_t mapreg) 476 { 477 478 if (PCI_BAR_IO(mapreg)) 479 return ("I/O Port"); 480 if (mapreg & PCIM_BAR_MEM_PREFETCH) 481 return ("Prefetchable Memory"); 482 return ("Memory"); 483 } 484 485 /* return log2 of map size decoded for memory or port map */ 486 487 static int 488 pci_mapsize(uint64_t testval) 489 { 490 int ln2size; 491 492 testval = pci_mapbase(testval); 493 ln2size = 0; 494 if (testval != 0) { 495 while ((testval & 1) == 0) 496 { 497 ln2size++; 498 testval >>= 1; 499 } 500 } 501 return (ln2size); 502 } 503 504 /* return base address of device ROM */ 505 506 static pci_addr_t 507 pci_rombase(uint64_t mapreg) 508 { 509 510 return (mapreg & PCIM_BIOS_ADDR_MASK); 511 } 512 513 /* return log2 of map size decided for device ROM */ 514 515 static int 516 pci_romsize(uint64_t testval) 517 { 518 int ln2size; 519 520 testval = pci_rombase(testval); 521 ln2size = 0; 522 if (testval != 0) { 523 while ((testval & 1) == 0) 524 { 525 ln2size++; 526 testval >>= 1; 527 } 528 } 529 return (ln2size); 530 } 531 532 /* return log2 of address range supported by map register */ 533 534 static int 535 pci_maprange(uint64_t mapreg) 536 { 537 int ln2range = 0; 538 539 if (PCI_BAR_IO(mapreg)) 540 ln2range = 32; 541 else 542 switch (mapreg & PCIM_BAR_MEM_TYPE) { 543 case PCIM_BAR_MEM_32: 544 ln2range = 32; 545 break; 546 case PCIM_BAR_MEM_1MB: 547 ln2range = 20; 548 break; 549 case PCIM_BAR_MEM_64: 550 ln2range = 64; 551 break; 552 } 553 return (ln2range); 554 } 555 556 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 557 558 static void 559 pci_fixancient(pcicfgregs *cfg) 560 { 561 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 562 return; 563 564 /* PCI to PCI bridges use header type 1 */ 565 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 566 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; 567 } 568 569 /* extract header type specific config data */ 570 571 static void 572 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 573 { 574 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 575 switch (cfg->hdrtype & PCIM_HDRTYPE) { 576 case PCIM_HDRTYPE_NORMAL: 577 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 578 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 579 cfg->nummaps = PCI_MAXMAPS_0; 580 break; 581 case PCIM_HDRTYPE_BRIDGE: 582 cfg->nummaps = PCI_MAXMAPS_1; 583 break; 584 case PCIM_HDRTYPE_CARDBUS: 585 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 586 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 587 cfg->nummaps = PCI_MAXMAPS_2; 588 break; 589 } 590 #undef REG 591 } 592 593 /* read configuration header into pcicfgregs structure */ 594 struct pci_devinfo * 595 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size) 596 { 597 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 598 pcicfgregs *cfg = NULL; 599 struct pci_devinfo *devlist_entry; 600 struct devlist *devlist_head; 601 602 devlist_head = &pci_devq; 603 604 devlist_entry = NULL; 605 606 if (REG(PCIR_DEVVENDOR, 4) != 0xfffffffful) { 607 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 608 609 cfg = &devlist_entry->cfg; 610 611 cfg->domain = d; 612 cfg->bus = b; 613 cfg->slot = s; 614 cfg->func = f; 615 cfg->vendor = REG(PCIR_VENDOR, 2); 616 cfg->device = REG(PCIR_DEVICE, 2); 617 cfg->cmdreg = REG(PCIR_COMMAND, 2); 618 cfg->statreg = REG(PCIR_STATUS, 2); 619 cfg->baseclass = REG(PCIR_CLASS, 1); 620 cfg->subclass = REG(PCIR_SUBCLASS, 1); 621 cfg->progif = REG(PCIR_PROGIF, 1); 622 cfg->revid = REG(PCIR_REVID, 1); 623 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 624 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 625 cfg->lattimer = REG(PCIR_LATTIMER, 1); 626 cfg->intpin = REG(PCIR_INTPIN, 1); 627 cfg->intline = REG(PCIR_INTLINE, 1); 628 629 cfg->mingnt = REG(PCIR_MINGNT, 1); 630 cfg->maxlat = REG(PCIR_MAXLAT, 1); 631 632 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 633 cfg->hdrtype &= ~PCIM_MFDEV; 634 STAILQ_INIT(&cfg->maps); 635 636 pci_fixancient(cfg); 637 pci_hdrtypedata(pcib, b, s, f, cfg); 638 639 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 640 pci_read_cap(pcib, cfg); 641 642 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 643 644 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; 645 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 646 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 647 devlist_entry->conf.pc_sel.pc_func = cfg->func; 648 devlist_entry->conf.pc_hdr = cfg->hdrtype; 649 650 devlist_entry->conf.pc_subvendor = cfg->subvendor; 651 devlist_entry->conf.pc_subdevice = cfg->subdevice; 652 devlist_entry->conf.pc_vendor = cfg->vendor; 653 devlist_entry->conf.pc_device = cfg->device; 654 655 devlist_entry->conf.pc_class = cfg->baseclass; 656 devlist_entry->conf.pc_subclass = cfg->subclass; 657 devlist_entry->conf.pc_progif = cfg->progif; 658 devlist_entry->conf.pc_revid = cfg->revid; 659 660 pci_numdevs++; 661 pci_generation++; 662 } 663 return (devlist_entry); 664 #undef REG 665 } 666 667 static void 668 pci_read_cap(device_t pcib, pcicfgregs *cfg) 669 { 670 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 671 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 672 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 673 uint64_t addr; 674 #endif 675 uint32_t val; 676 int ptr, nextptr, ptrptr; 677 678 switch (cfg->hdrtype & PCIM_HDRTYPE) { 679 case PCIM_HDRTYPE_NORMAL: 680 case PCIM_HDRTYPE_BRIDGE: 681 ptrptr = PCIR_CAP_PTR; 682 break; 683 case PCIM_HDRTYPE_CARDBUS: 684 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 685 break; 686 default: 687 return; /* no extended capabilities support */ 688 } 689 nextptr = REG(ptrptr, 1); /* sanity check? */ 690 691 /* 692 * Read capability entries. 693 */ 694 while (nextptr != 0) { 695 /* Sanity check */ 696 if (nextptr > 255) { 697 printf("illegal PCI extended capability offset %d\n", 698 nextptr); 699 return; 700 } 701 /* Find the next entry */ 702 ptr = nextptr; 703 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 704 705 /* Process this entry */ 706 switch (REG(ptr + PCICAP_ID, 1)) { 707 case PCIY_PMG: /* PCI power management */ 708 if (cfg->pp.pp_cap == 0) { 709 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 710 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 711 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE; 712 if ((nextptr - ptr) > PCIR_POWER_DATA) 713 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 714 } 715 break; 716 case PCIY_HT: /* HyperTransport */ 717 /* Determine HT-specific capability type. */ 718 val = REG(ptr + PCIR_HT_COMMAND, 2); 719 720 if ((val & 0xe000) == PCIM_HTCAP_SLAVE) 721 cfg->ht.ht_slave = ptr; 722 723 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 724 switch (val & PCIM_HTCMD_CAP_MASK) { 725 case PCIM_HTCAP_MSI_MAPPING: 726 if (!(val & PCIM_HTCMD_MSI_FIXED)) { 727 /* Sanity check the mapping window. */ 728 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 729 4); 730 addr <<= 32; 731 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 732 4); 733 if (addr != MSI_INTEL_ADDR_BASE) 734 device_printf(pcib, 735 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", 736 cfg->domain, cfg->bus, 737 cfg->slot, cfg->func, 738 (long long)addr); 739 } else 740 addr = MSI_INTEL_ADDR_BASE; 741 742 cfg->ht.ht_msimap = ptr; 743 cfg->ht.ht_msictrl = val; 744 cfg->ht.ht_msiaddr = addr; 745 break; 746 } 747 #endif 748 break; 749 case PCIY_MSI: /* PCI MSI */ 750 cfg->msi.msi_location = ptr; 751 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 752 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 753 PCIM_MSICTRL_MMC_MASK)>>1); 754 break; 755 case PCIY_MSIX: /* PCI MSI-X */ 756 cfg->msix.msix_location = ptr; 757 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 758 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl & 759 PCIM_MSIXCTRL_TABLE_SIZE) + 1; 760 val = REG(ptr + PCIR_MSIX_TABLE, 4); 761 cfg->msix.msix_table_bar = PCIR_BAR(val & 762 PCIM_MSIX_BIR_MASK); 763 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 764 val = REG(ptr + PCIR_MSIX_PBA, 4); 765 cfg->msix.msix_pba_bar = PCIR_BAR(val & 766 PCIM_MSIX_BIR_MASK); 767 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 768 break; 769 case PCIY_VPD: /* PCI Vital Product Data */ 770 cfg->vpd.vpd_reg = ptr; 771 break; 772 case PCIY_SUBVENDOR: 773 /* Should always be true. */ 774 if ((cfg->hdrtype & PCIM_HDRTYPE) == 775 PCIM_HDRTYPE_BRIDGE) { 776 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4); 777 cfg->subvendor = val & 0xffff; 778 cfg->subdevice = val >> 16; 779 } 780 break; 781 case PCIY_PCIX: /* PCI-X */ 782 /* 783 * Assume we have a PCI-X chipset if we have 784 * at least one PCI-PCI bridge with a PCI-X 785 * capability. Note that some systems with 786 * PCI-express or HT chipsets might match on 787 * this check as well. 788 */ 789 if ((cfg->hdrtype & PCIM_HDRTYPE) == 790 PCIM_HDRTYPE_BRIDGE) 791 pcix_chipset = 1; 792 cfg->pcix.pcix_location = ptr; 793 break; 794 case PCIY_EXPRESS: /* PCI-express */ 795 /* 796 * Assume we have a PCI-express chipset if we have 797 * at least one PCI-express device. 798 */ 799 pcie_chipset = 1; 800 cfg->pcie.pcie_location = ptr; 801 val = REG(ptr + PCIER_FLAGS, 2); 802 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; 803 break; 804 default: 805 break; 806 } 807 } 808 809 #if defined(__powerpc__) 810 /* 811 * Enable the MSI mapping window for all HyperTransport 812 * slaves. PCI-PCI bridges have their windows enabled via 813 * PCIB_MAP_MSI(). 814 */ 815 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && 816 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { 817 device_printf(pcib, 818 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n", 819 cfg->domain, cfg->bus, cfg->slot, cfg->func); 820 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 821 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, 822 2); 823 } 824 #endif 825 /* REG and WREG use carry through to next functions */ 826 } 827 828 /* 829 * PCI Vital Product Data 830 */ 831 832 #define PCI_VPD_TIMEOUT 1000000 833 834 static int 835 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data) 836 { 837 int count = PCI_VPD_TIMEOUT; 838 839 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 840 841 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); 842 843 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { 844 if (--count < 0) 845 return (ENXIO); 846 DELAY(1); /* limit looping */ 847 } 848 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); 849 850 return (0); 851 } 852 853 #if 0 854 static int 855 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 856 { 857 int count = PCI_VPD_TIMEOUT; 858 859 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 860 861 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4); 862 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2); 863 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) { 864 if (--count < 0) 865 return (ENXIO); 866 DELAY(1); /* limit looping */ 867 } 868 869 return (0); 870 } 871 #endif 872 873 #undef PCI_VPD_TIMEOUT 874 875 struct vpd_readstate { 876 device_t pcib; 877 pcicfgregs *cfg; 878 uint32_t val; 879 int bytesinval; 880 int off; 881 uint8_t cksum; 882 }; 883 884 static int 885 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data) 886 { 887 uint32_t reg; 888 uint8_t byte; 889 890 if (vrs->bytesinval == 0) { 891 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) 892 return (ENXIO); 893 vrs->val = le32toh(reg); 894 vrs->off += 4; 895 byte = vrs->val & 0xff; 896 vrs->bytesinval = 3; 897 } else { 898 vrs->val = vrs->val >> 8; 899 byte = vrs->val & 0xff; 900 vrs->bytesinval--; 901 } 902 903 vrs->cksum += byte; 904 *data = byte; 905 return (0); 906 } 907 908 static void 909 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 910 { 911 struct vpd_readstate vrs; 912 int state; 913 int name; 914 int remain; 915 int i; 916 int alloc, off; /* alloc/off for RO/W arrays */ 917 int cksumvalid; 918 int dflen; 919 uint8_t byte; 920 uint8_t byte2; 921 922 /* init vpd reader */ 923 vrs.bytesinval = 0; 924 vrs.off = 0; 925 vrs.pcib = pcib; 926 vrs.cfg = cfg; 927 vrs.cksum = 0; 928 929 state = 0; 930 name = remain = i = 0; /* shut up stupid gcc */ 931 alloc = off = 0; /* shut up stupid gcc */ 932 dflen = 0; /* shut up stupid gcc */ 933 cksumvalid = -1; 934 while (state >= 0) { 935 if (vpd_nextbyte(&vrs, &byte)) { 936 state = -2; 937 break; 938 } 939 #if 0 940 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \ 941 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val, 942 vrs.off, vrs.bytesinval, byte, state, remain, name, i); 943 #endif 944 switch (state) { 945 case 0: /* item name */ 946 if (byte & 0x80) { 947 if (vpd_nextbyte(&vrs, &byte2)) { 948 state = -2; 949 break; 950 } 951 remain = byte2; 952 if (vpd_nextbyte(&vrs, &byte2)) { 953 state = -2; 954 break; 955 } 956 remain |= byte2 << 8; 957 if (remain > (0x7f*4 - vrs.off)) { 958 state = -1; 959 pci_printf(cfg, 960 "invalid VPD data, remain %#x\n", 961 remain); 962 } 963 name = byte & 0x7f; 964 } else { 965 remain = byte & 0x7; 966 name = (byte >> 3) & 0xf; 967 } 968 switch (name) { 969 case 0x2: /* String */ 970 cfg->vpd.vpd_ident = malloc(remain + 1, 971 M_DEVBUF, M_WAITOK); 972 i = 0; 973 state = 1; 974 break; 975 case 0xf: /* End */ 976 state = -1; 977 break; 978 case 0x10: /* VPD-R */ 979 alloc = 8; 980 off = 0; 981 cfg->vpd.vpd_ros = malloc(alloc * 982 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF, 983 M_WAITOK | M_ZERO); 984 state = 2; 985 break; 986 case 0x11: /* VPD-W */ 987 alloc = 8; 988 off = 0; 989 cfg->vpd.vpd_w = malloc(alloc * 990 sizeof(*cfg->vpd.vpd_w), M_DEVBUF, 991 M_WAITOK | M_ZERO); 992 state = 5; 993 break; 994 default: /* Invalid data, abort */ 995 state = -1; 996 break; 997 } 998 break; 999 1000 case 1: /* Identifier String */ 1001 cfg->vpd.vpd_ident[i++] = byte; 1002 remain--; 1003 if (remain == 0) { 1004 cfg->vpd.vpd_ident[i] = '\0'; 1005 state = 0; 1006 } 1007 break; 1008 1009 case 2: /* VPD-R Keyword Header */ 1010 if (off == alloc) { 1011 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1012 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros), 1013 M_DEVBUF, M_WAITOK | M_ZERO); 1014 } 1015 cfg->vpd.vpd_ros[off].keyword[0] = byte; 1016 if (vpd_nextbyte(&vrs, &byte2)) { 1017 state = -2; 1018 break; 1019 } 1020 cfg->vpd.vpd_ros[off].keyword[1] = byte2; 1021 if (vpd_nextbyte(&vrs, &byte2)) { 1022 state = -2; 1023 break; 1024 } 1025 cfg->vpd.vpd_ros[off].len = dflen = byte2; 1026 if (dflen == 0 && 1027 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV", 1028 2) == 0) { 1029 /* 1030 * if this happens, we can't trust the rest 1031 * of the VPD. 1032 */ 1033 pci_printf(cfg, "bad keyword length: %d\n", 1034 dflen); 1035 cksumvalid = 0; 1036 state = -1; 1037 break; 1038 } else if (dflen == 0) { 1039 cfg->vpd.vpd_ros[off].value = malloc(1 * 1040 sizeof(*cfg->vpd.vpd_ros[off].value), 1041 M_DEVBUF, M_WAITOK); 1042 cfg->vpd.vpd_ros[off].value[0] = '\x00'; 1043 } else 1044 cfg->vpd.vpd_ros[off].value = malloc( 1045 (dflen + 1) * 1046 sizeof(*cfg->vpd.vpd_ros[off].value), 1047 M_DEVBUF, M_WAITOK); 1048 remain -= 3; 1049 i = 0; 1050 /* keep in sync w/ state 3's transistions */ 1051 if (dflen == 0 && remain == 0) 1052 state = 0; 1053 else if (dflen == 0) 1054 state = 2; 1055 else 1056 state = 3; 1057 break; 1058 1059 case 3: /* VPD-R Keyword Value */ 1060 cfg->vpd.vpd_ros[off].value[i++] = byte; 1061 if (strncmp(cfg->vpd.vpd_ros[off].keyword, 1062 "RV", 2) == 0 && cksumvalid == -1) { 1063 if (vrs.cksum == 0) 1064 cksumvalid = 1; 1065 else { 1066 if (bootverbose) 1067 pci_printf(cfg, 1068 "bad VPD cksum, remain %hhu\n", 1069 vrs.cksum); 1070 cksumvalid = 0; 1071 state = -1; 1072 break; 1073 } 1074 } 1075 dflen--; 1076 remain--; 1077 /* keep in sync w/ state 2's transistions */ 1078 if (dflen == 0) 1079 cfg->vpd.vpd_ros[off++].value[i++] = '\0'; 1080 if (dflen == 0 && remain == 0) { 1081 cfg->vpd.vpd_rocnt = off; 1082 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1083 off * sizeof(*cfg->vpd.vpd_ros), 1084 M_DEVBUF, M_WAITOK | M_ZERO); 1085 state = 0; 1086 } else if (dflen == 0) 1087 state = 2; 1088 break; 1089 1090 case 4: 1091 remain--; 1092 if (remain == 0) 1093 state = 0; 1094 break; 1095 1096 case 5: /* VPD-W Keyword Header */ 1097 if (off == alloc) { 1098 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1099 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w), 1100 M_DEVBUF, M_WAITOK | M_ZERO); 1101 } 1102 cfg->vpd.vpd_w[off].keyword[0] = byte; 1103 if (vpd_nextbyte(&vrs, &byte2)) { 1104 state = -2; 1105 break; 1106 } 1107 cfg->vpd.vpd_w[off].keyword[1] = byte2; 1108 if (vpd_nextbyte(&vrs, &byte2)) { 1109 state = -2; 1110 break; 1111 } 1112 cfg->vpd.vpd_w[off].len = dflen = byte2; 1113 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval; 1114 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) * 1115 sizeof(*cfg->vpd.vpd_w[off].value), 1116 M_DEVBUF, M_WAITOK); 1117 remain -= 3; 1118 i = 0; 1119 /* keep in sync w/ state 6's transistions */ 1120 if (dflen == 0 && remain == 0) 1121 state = 0; 1122 else if (dflen == 0) 1123 state = 5; 1124 else 1125 state = 6; 1126 break; 1127 1128 case 6: /* VPD-W Keyword Value */ 1129 cfg->vpd.vpd_w[off].value[i++] = byte; 1130 dflen--; 1131 remain--; 1132 /* keep in sync w/ state 5's transistions */ 1133 if (dflen == 0) 1134 cfg->vpd.vpd_w[off++].value[i++] = '\0'; 1135 if (dflen == 0 && remain == 0) { 1136 cfg->vpd.vpd_wcnt = off; 1137 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1138 off * sizeof(*cfg->vpd.vpd_w), 1139 M_DEVBUF, M_WAITOK | M_ZERO); 1140 state = 0; 1141 } else if (dflen == 0) 1142 state = 5; 1143 break; 1144 1145 default: 1146 pci_printf(cfg, "invalid state: %d\n", state); 1147 state = -1; 1148 break; 1149 } 1150 } 1151 1152 if (cksumvalid == 0 || state < -1) { 1153 /* read-only data bad, clean up */ 1154 if (cfg->vpd.vpd_ros != NULL) { 1155 for (off = 0; cfg->vpd.vpd_ros[off].value; off++) 1156 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF); 1157 free(cfg->vpd.vpd_ros, M_DEVBUF); 1158 cfg->vpd.vpd_ros = NULL; 1159 } 1160 } 1161 if (state < -1) { 1162 /* I/O error, clean up */ 1163 pci_printf(cfg, "failed to read VPD data.\n"); 1164 if (cfg->vpd.vpd_ident != NULL) { 1165 free(cfg->vpd.vpd_ident, M_DEVBUF); 1166 cfg->vpd.vpd_ident = NULL; 1167 } 1168 if (cfg->vpd.vpd_w != NULL) { 1169 for (off = 0; cfg->vpd.vpd_w[off].value; off++) 1170 free(cfg->vpd.vpd_w[off].value, M_DEVBUF); 1171 free(cfg->vpd.vpd_w, M_DEVBUF); 1172 cfg->vpd.vpd_w = NULL; 1173 } 1174 } 1175 cfg->vpd.vpd_cached = 1; 1176 #undef REG 1177 #undef WREG 1178 } 1179 1180 int 1181 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 1182 { 1183 struct pci_devinfo *dinfo = device_get_ivars(child); 1184 pcicfgregs *cfg = &dinfo->cfg; 1185 1186 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1187 pci_read_vpd(device_get_parent(dev), cfg); 1188 1189 *identptr = cfg->vpd.vpd_ident; 1190 1191 if (*identptr == NULL) 1192 return (ENXIO); 1193 1194 return (0); 1195 } 1196 1197 int 1198 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 1199 const char **vptr) 1200 { 1201 struct pci_devinfo *dinfo = device_get_ivars(child); 1202 pcicfgregs *cfg = &dinfo->cfg; 1203 int i; 1204 1205 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1206 pci_read_vpd(device_get_parent(dev), cfg); 1207 1208 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 1209 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 1210 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { 1211 *vptr = cfg->vpd.vpd_ros[i].value; 1212 return (0); 1213 } 1214 1215 *vptr = NULL; 1216 return (ENXIO); 1217 } 1218 1219 struct pcicfg_vpd * 1220 pci_fetch_vpd_list(device_t dev) 1221 { 1222 struct pci_devinfo *dinfo = device_get_ivars(dev); 1223 pcicfgregs *cfg = &dinfo->cfg; 1224 1225 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1226 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg); 1227 return (&cfg->vpd); 1228 } 1229 1230 /* 1231 * Find the requested HyperTransport capability and return the offset 1232 * in configuration space via the pointer provided. The function 1233 * returns 0 on success and an error code otherwise. 1234 */ 1235 int 1236 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg) 1237 { 1238 int ptr, error; 1239 uint16_t val; 1240 1241 error = pci_find_cap(child, PCIY_HT, &ptr); 1242 if (error) 1243 return (error); 1244 1245 /* 1246 * Traverse the capabilities list checking each HT capability 1247 * to see if it matches the requested HT capability. 1248 */ 1249 while (ptr != 0) { 1250 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1251 if (capability == PCIM_HTCAP_SLAVE || 1252 capability == PCIM_HTCAP_HOST) 1253 val &= 0xe000; 1254 else 1255 val &= PCIM_HTCMD_CAP_MASK; 1256 if (val == capability) { 1257 if (capreg != NULL) 1258 *capreg = ptr; 1259 return (0); 1260 } 1261 1262 /* Skip to the next HT capability. */ 1263 while (ptr != 0) { 1264 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1265 if (pci_read_config(child, ptr + PCICAP_ID, 1) == 1266 PCIY_HT) 1267 break; 1268 } 1269 } 1270 return (ENOENT); 1271 } 1272 1273 /* 1274 * Find the requested capability and return the offset in 1275 * configuration space via the pointer provided. The function returns 1276 * 0 on success and an error code otherwise. 1277 */ 1278 int 1279 pci_find_cap_method(device_t dev, device_t child, int capability, 1280 int *capreg) 1281 { 1282 struct pci_devinfo *dinfo = device_get_ivars(child); 1283 pcicfgregs *cfg = &dinfo->cfg; 1284 u_int32_t status; 1285 u_int8_t ptr; 1286 1287 /* 1288 * Check the CAP_LIST bit of the PCI status register first. 1289 */ 1290 status = pci_read_config(child, PCIR_STATUS, 2); 1291 if (!(status & PCIM_STATUS_CAPPRESENT)) 1292 return (ENXIO); 1293 1294 /* 1295 * Determine the start pointer of the capabilities list. 1296 */ 1297 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1298 case PCIM_HDRTYPE_NORMAL: 1299 case PCIM_HDRTYPE_BRIDGE: 1300 ptr = PCIR_CAP_PTR; 1301 break; 1302 case PCIM_HDRTYPE_CARDBUS: 1303 ptr = PCIR_CAP_PTR_2; 1304 break; 1305 default: 1306 /* XXX: panic? */ 1307 return (ENXIO); /* no extended capabilities support */ 1308 } 1309 ptr = pci_read_config(child, ptr, 1); 1310 1311 /* 1312 * Traverse the capabilities list. 1313 */ 1314 while (ptr != 0) { 1315 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1316 if (capreg != NULL) 1317 *capreg = ptr; 1318 return (0); 1319 } 1320 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1321 } 1322 1323 return (ENOENT); 1324 } 1325 1326 /* 1327 * Find the requested extended capability and return the offset in 1328 * configuration space via the pointer provided. The function returns 1329 * 0 on success and an error code otherwise. 1330 */ 1331 int 1332 pci_find_extcap_method(device_t dev, device_t child, int capability, 1333 int *capreg) 1334 { 1335 struct pci_devinfo *dinfo = device_get_ivars(child); 1336 pcicfgregs *cfg = &dinfo->cfg; 1337 uint32_t ecap; 1338 uint16_t ptr; 1339 1340 /* Only supported for PCI-express devices. */ 1341 if (cfg->pcie.pcie_location == 0) 1342 return (ENXIO); 1343 1344 ptr = PCIR_EXTCAP; 1345 ecap = pci_read_config(child, ptr, 4); 1346 if (ecap == 0xffffffff || ecap == 0) 1347 return (ENOENT); 1348 for (;;) { 1349 if (PCI_EXTCAP_ID(ecap) == capability) { 1350 if (capreg != NULL) 1351 *capreg = ptr; 1352 return (0); 1353 } 1354 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1355 if (ptr == 0) 1356 break; 1357 ecap = pci_read_config(child, ptr, 4); 1358 } 1359 1360 return (ENOENT); 1361 } 1362 1363 /* 1364 * Support for MSI-X message interrupts. 1365 */ 1366 void 1367 pci_enable_msix_method(device_t dev, device_t child, u_int index, 1368 uint64_t address, uint32_t data) 1369 { 1370 struct pci_devinfo *dinfo = device_get_ivars(child); 1371 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1372 uint32_t offset; 1373 1374 KASSERT(msix->msix_table_len > index, ("bogus index")); 1375 offset = msix->msix_table_offset + index * 16; 1376 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); 1377 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); 1378 bus_write_4(msix->msix_table_res, offset + 8, data); 1379 1380 /* Enable MSI -> HT mapping. */ 1381 pci_ht_map_msi(child, address); 1382 } 1383 1384 void 1385 pci_mask_msix(device_t dev, u_int index) 1386 { 1387 struct pci_devinfo *dinfo = device_get_ivars(dev); 1388 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1389 uint32_t offset, val; 1390 1391 KASSERT(msix->msix_msgnum > index, ("bogus index")); 1392 offset = msix->msix_table_offset + index * 16 + 12; 1393 val = bus_read_4(msix->msix_table_res, offset); 1394 if (!(val & PCIM_MSIX_VCTRL_MASK)) { 1395 val |= PCIM_MSIX_VCTRL_MASK; 1396 bus_write_4(msix->msix_table_res, offset, val); 1397 } 1398 } 1399 1400 void 1401 pci_unmask_msix(device_t dev, u_int index) 1402 { 1403 struct pci_devinfo *dinfo = device_get_ivars(dev); 1404 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1405 uint32_t offset, val; 1406 1407 KASSERT(msix->msix_table_len > index, ("bogus index")); 1408 offset = msix->msix_table_offset + index * 16 + 12; 1409 val = bus_read_4(msix->msix_table_res, offset); 1410 if (val & PCIM_MSIX_VCTRL_MASK) { 1411 val &= ~PCIM_MSIX_VCTRL_MASK; 1412 bus_write_4(msix->msix_table_res, offset, val); 1413 } 1414 } 1415 1416 int 1417 pci_pending_msix(device_t dev, u_int index) 1418 { 1419 struct pci_devinfo *dinfo = device_get_ivars(dev); 1420 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1421 uint32_t offset, bit; 1422 1423 KASSERT(msix->msix_table_len > index, ("bogus index")); 1424 offset = msix->msix_pba_offset + (index / 32) * 4; 1425 bit = 1 << index % 32; 1426 return (bus_read_4(msix->msix_pba_res, offset) & bit); 1427 } 1428 1429 /* 1430 * Restore MSI-X registers and table during resume. If MSI-X is 1431 * enabled then walk the virtual table to restore the actual MSI-X 1432 * table. 1433 */ 1434 static void 1435 pci_resume_msix(device_t dev) 1436 { 1437 struct pci_devinfo *dinfo = device_get_ivars(dev); 1438 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1439 struct msix_table_entry *mte; 1440 struct msix_vector *mv; 1441 int i; 1442 1443 if (msix->msix_alloc > 0) { 1444 /* First, mask all vectors. */ 1445 for (i = 0; i < msix->msix_msgnum; i++) 1446 pci_mask_msix(dev, i); 1447 1448 /* Second, program any messages with at least one handler. */ 1449 for (i = 0; i < msix->msix_table_len; i++) { 1450 mte = &msix->msix_table[i]; 1451 if (mte->mte_vector == 0 || mte->mte_handlers == 0) 1452 continue; 1453 mv = &msix->msix_vectors[mte->mte_vector - 1]; 1454 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data); 1455 pci_unmask_msix(dev, i); 1456 } 1457 } 1458 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, 1459 msix->msix_ctrl, 2); 1460 } 1461 1462 /* 1463 * Attempt to allocate *count MSI-X messages. The actual number allocated is 1464 * returned in *count. After this function returns, each message will be 1465 * available to the driver as SYS_RES_IRQ resources starting at rid 1. 1466 */ 1467 int 1468 pci_alloc_msix_method(device_t dev, device_t child, int *count) 1469 { 1470 struct pci_devinfo *dinfo = device_get_ivars(child); 1471 pcicfgregs *cfg = &dinfo->cfg; 1472 struct resource_list_entry *rle; 1473 int actual, error, i, irq, max; 1474 1475 /* Don't let count == 0 get us into trouble. */ 1476 if (*count == 0) 1477 return (EINVAL); 1478 1479 /* If rid 0 is allocated, then fail. */ 1480 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1481 if (rle != NULL && rle->res != NULL) 1482 return (ENXIO); 1483 1484 /* Already have allocated messages? */ 1485 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1486 return (ENXIO); 1487 1488 /* If MSI-X is blacklisted for this system, fail. */ 1489 if (pci_msix_blacklisted()) 1490 return (ENXIO); 1491 1492 /* MSI-X capability present? */ 1493 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1494 return (ENODEV); 1495 1496 /* Make sure the appropriate BARs are mapped. */ 1497 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1498 cfg->msix.msix_table_bar); 1499 if (rle == NULL || rle->res == NULL || 1500 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1501 return (ENXIO); 1502 cfg->msix.msix_table_res = rle->res; 1503 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1504 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1505 cfg->msix.msix_pba_bar); 1506 if (rle == NULL || rle->res == NULL || 1507 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1508 return (ENXIO); 1509 } 1510 cfg->msix.msix_pba_res = rle->res; 1511 1512 if (bootverbose) 1513 device_printf(child, 1514 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1515 *count, cfg->msix.msix_msgnum); 1516 max = min(*count, cfg->msix.msix_msgnum); 1517 for (i = 0; i < max; i++) { 1518 /* Allocate a message. */ 1519 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq); 1520 if (error) { 1521 if (i == 0) 1522 return (error); 1523 break; 1524 } 1525 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1526 irq, 1); 1527 } 1528 actual = i; 1529 1530 if (bootverbose) { 1531 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1532 if (actual == 1) 1533 device_printf(child, "using IRQ %lu for MSI-X\n", 1534 rle->start); 1535 else { 1536 int run; 1537 1538 /* 1539 * Be fancy and try to print contiguous runs of 1540 * IRQ values as ranges. 'irq' is the previous IRQ. 1541 * 'run' is true if we are in a range. 1542 */ 1543 device_printf(child, "using IRQs %lu", rle->start); 1544 irq = rle->start; 1545 run = 0; 1546 for (i = 1; i < actual; i++) { 1547 rle = resource_list_find(&dinfo->resources, 1548 SYS_RES_IRQ, i + 1); 1549 1550 /* Still in a run? */ 1551 if (rle->start == irq + 1) { 1552 run = 1; 1553 irq++; 1554 continue; 1555 } 1556 1557 /* Finish previous range. */ 1558 if (run) { 1559 printf("-%d", irq); 1560 run = 0; 1561 } 1562 1563 /* Start new range. */ 1564 printf(",%lu", rle->start); 1565 irq = rle->start; 1566 } 1567 1568 /* Unfinished range? */ 1569 if (run) 1570 printf("-%d", irq); 1571 printf(" for MSI-X\n"); 1572 } 1573 } 1574 1575 /* Mask all vectors. */ 1576 for (i = 0; i < cfg->msix.msix_msgnum; i++) 1577 pci_mask_msix(child, i); 1578 1579 /* Allocate and initialize vector data and virtual table. */ 1580 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual, 1581 M_DEVBUF, M_WAITOK | M_ZERO); 1582 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual, 1583 M_DEVBUF, M_WAITOK | M_ZERO); 1584 for (i = 0; i < actual; i++) { 1585 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1586 cfg->msix.msix_vectors[i].mv_irq = rle->start; 1587 cfg->msix.msix_table[i].mte_vector = i + 1; 1588 } 1589 1590 /* Update control register to enable MSI-X. */ 1591 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1592 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1593 cfg->msix.msix_ctrl, 2); 1594 1595 /* Update counts of alloc'd messages. */ 1596 cfg->msix.msix_alloc = actual; 1597 cfg->msix.msix_table_len = actual; 1598 *count = actual; 1599 return (0); 1600 } 1601 1602 /* 1603 * By default, pci_alloc_msix() will assign the allocated IRQ 1604 * resources consecutively to the first N messages in the MSI-X table. 1605 * However, device drivers may want to use different layouts if they 1606 * either receive fewer messages than they asked for, or they wish to 1607 * populate the MSI-X table sparsely. This method allows the driver 1608 * to specify what layout it wants. It must be called after a 1609 * successful pci_alloc_msix() but before any of the associated 1610 * SYS_RES_IRQ resources are allocated via bus_alloc_resource(). 1611 * 1612 * The 'vectors' array contains 'count' message vectors. The array 1613 * maps directly to the MSI-X table in that index 0 in the array 1614 * specifies the vector for the first message in the MSI-X table, etc. 1615 * The vector value in each array index can either be 0 to indicate 1616 * that no vector should be assigned to a message slot, or it can be a 1617 * number from 1 to N (where N is the count returned from a 1618 * succcessful call to pci_alloc_msix()) to indicate which message 1619 * vector (IRQ) to be used for the corresponding message. 1620 * 1621 * On successful return, each message with a non-zero vector will have 1622 * an associated SYS_RES_IRQ whose rid is equal to the array index + 1623 * 1. Additionally, if any of the IRQs allocated via the previous 1624 * call to pci_alloc_msix() are not used in the mapping, those IRQs 1625 * will be freed back to the system automatically. 1626 * 1627 * For example, suppose a driver has a MSI-X table with 6 messages and 1628 * asks for 6 messages, but pci_alloc_msix() only returns a count of 1629 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and 1630 * C. After the call to pci_alloc_msix(), the device will be setup to 1631 * have an MSI-X table of ABC--- (where - means no vector assigned). 1632 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 }, 1633 * then the MSI-X table will look like A-AB-B, and the 'C' vector will 1634 * be freed back to the system. This device will also have valid 1635 * SYS_RES_IRQ rids of 1, 3, 4, and 6. 1636 * 1637 * In any case, the SYS_RES_IRQ rid X will always map to the message 1638 * at MSI-X table index X - 1 and will only be valid if a vector is 1639 * assigned to that table entry. 1640 */ 1641 int 1642 pci_remap_msix_method(device_t dev, device_t child, int count, 1643 const u_int *vectors) 1644 { 1645 struct pci_devinfo *dinfo = device_get_ivars(child); 1646 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1647 struct resource_list_entry *rle; 1648 int i, irq, j, *used; 1649 1650 /* 1651 * Have to have at least one message in the table but the 1652 * table can't be bigger than the actual MSI-X table in the 1653 * device. 1654 */ 1655 if (count == 0 || count > msix->msix_msgnum) 1656 return (EINVAL); 1657 1658 /* Sanity check the vectors. */ 1659 for (i = 0; i < count; i++) 1660 if (vectors[i] > msix->msix_alloc) 1661 return (EINVAL); 1662 1663 /* 1664 * Make sure there aren't any holes in the vectors to be used. 1665 * It's a big pain to support it, and it doesn't really make 1666 * sense anyway. Also, at least one vector must be used. 1667 */ 1668 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK | 1669 M_ZERO); 1670 for (i = 0; i < count; i++) 1671 if (vectors[i] != 0) 1672 used[vectors[i] - 1] = 1; 1673 for (i = 0; i < msix->msix_alloc - 1; i++) 1674 if (used[i] == 0 && used[i + 1] == 1) { 1675 free(used, M_DEVBUF); 1676 return (EINVAL); 1677 } 1678 if (used[0] != 1) { 1679 free(used, M_DEVBUF); 1680 return (EINVAL); 1681 } 1682 1683 /* Make sure none of the resources are allocated. */ 1684 for (i = 0; i < msix->msix_table_len; i++) { 1685 if (msix->msix_table[i].mte_vector == 0) 1686 continue; 1687 if (msix->msix_table[i].mte_handlers > 0) 1688 return (EBUSY); 1689 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1690 KASSERT(rle != NULL, ("missing resource")); 1691 if (rle->res != NULL) 1692 return (EBUSY); 1693 } 1694 1695 /* Free the existing resource list entries. */ 1696 for (i = 0; i < msix->msix_table_len; i++) { 1697 if (msix->msix_table[i].mte_vector == 0) 1698 continue; 1699 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1700 } 1701 1702 /* 1703 * Build the new virtual table keeping track of which vectors are 1704 * used. 1705 */ 1706 free(msix->msix_table, M_DEVBUF); 1707 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count, 1708 M_DEVBUF, M_WAITOK | M_ZERO); 1709 for (i = 0; i < count; i++) 1710 msix->msix_table[i].mte_vector = vectors[i]; 1711 msix->msix_table_len = count; 1712 1713 /* Free any unused IRQs and resize the vectors array if necessary. */ 1714 j = msix->msix_alloc - 1; 1715 if (used[j] == 0) { 1716 struct msix_vector *vec; 1717 1718 while (used[j] == 0) { 1719 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 1720 msix->msix_vectors[j].mv_irq); 1721 j--; 1722 } 1723 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF, 1724 M_WAITOK); 1725 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * 1726 (j + 1)); 1727 free(msix->msix_vectors, M_DEVBUF); 1728 msix->msix_vectors = vec; 1729 msix->msix_alloc = j + 1; 1730 } 1731 free(used, M_DEVBUF); 1732 1733 /* Map the IRQs onto the rids. */ 1734 for (i = 0; i < count; i++) { 1735 if (vectors[i] == 0) 1736 continue; 1737 irq = msix->msix_vectors[vectors[i]].mv_irq; 1738 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1739 irq, 1); 1740 } 1741 1742 if (bootverbose) { 1743 device_printf(child, "Remapped MSI-X IRQs as: "); 1744 for (i = 0; i < count; i++) { 1745 if (i != 0) 1746 printf(", "); 1747 if (vectors[i] == 0) 1748 printf("---"); 1749 else 1750 printf("%d", 1751 msix->msix_vectors[vectors[i]].mv_irq); 1752 } 1753 printf("\n"); 1754 } 1755 1756 return (0); 1757 } 1758 1759 static int 1760 pci_release_msix(device_t dev, device_t child) 1761 { 1762 struct pci_devinfo *dinfo = device_get_ivars(child); 1763 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1764 struct resource_list_entry *rle; 1765 int i; 1766 1767 /* Do we have any messages to release? */ 1768 if (msix->msix_alloc == 0) 1769 return (ENODEV); 1770 1771 /* Make sure none of the resources are allocated. */ 1772 for (i = 0; i < msix->msix_table_len; i++) { 1773 if (msix->msix_table[i].mte_vector == 0) 1774 continue; 1775 if (msix->msix_table[i].mte_handlers > 0) 1776 return (EBUSY); 1777 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1778 KASSERT(rle != NULL, ("missing resource")); 1779 if (rle->res != NULL) 1780 return (EBUSY); 1781 } 1782 1783 /* Update control register to disable MSI-X. */ 1784 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 1785 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, 1786 msix->msix_ctrl, 2); 1787 1788 /* Free the resource list entries. */ 1789 for (i = 0; i < msix->msix_table_len; i++) { 1790 if (msix->msix_table[i].mte_vector == 0) 1791 continue; 1792 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1793 } 1794 free(msix->msix_table, M_DEVBUF); 1795 msix->msix_table_len = 0; 1796 1797 /* Release the IRQs. */ 1798 for (i = 0; i < msix->msix_alloc; i++) 1799 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 1800 msix->msix_vectors[i].mv_irq); 1801 free(msix->msix_vectors, M_DEVBUF); 1802 msix->msix_alloc = 0; 1803 return (0); 1804 } 1805 1806 /* 1807 * Return the max supported MSI-X messages this device supports. 1808 * Basically, assuming the MD code can alloc messages, this function 1809 * should return the maximum value that pci_alloc_msix() can return. 1810 * Thus, it is subject to the tunables, etc. 1811 */ 1812 int 1813 pci_msix_count_method(device_t dev, device_t child) 1814 { 1815 struct pci_devinfo *dinfo = device_get_ivars(child); 1816 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1817 1818 if (pci_do_msix && msix->msix_location != 0) 1819 return (msix->msix_msgnum); 1820 return (0); 1821 } 1822 1823 /* 1824 * HyperTransport MSI mapping control 1825 */ 1826 void 1827 pci_ht_map_msi(device_t dev, uint64_t addr) 1828 { 1829 struct pci_devinfo *dinfo = device_get_ivars(dev); 1830 struct pcicfg_ht *ht = &dinfo->cfg.ht; 1831 1832 if (!ht->ht_msimap) 1833 return; 1834 1835 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && 1836 ht->ht_msiaddr >> 20 == addr >> 20) { 1837 /* Enable MSI -> HT mapping. */ 1838 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 1839 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 1840 ht->ht_msictrl, 2); 1841 } 1842 1843 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { 1844 /* Disable MSI -> HT mapping. */ 1845 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; 1846 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 1847 ht->ht_msictrl, 2); 1848 } 1849 } 1850 1851 int 1852 pci_get_max_read_req(device_t dev) 1853 { 1854 struct pci_devinfo *dinfo = device_get_ivars(dev); 1855 int cap; 1856 uint16_t val; 1857 1858 cap = dinfo->cfg.pcie.pcie_location; 1859 if (cap == 0) 1860 return (0); 1861 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 1862 val &= PCIEM_CTL_MAX_READ_REQUEST; 1863 val >>= 12; 1864 return (1 << (val + 7)); 1865 } 1866 1867 int 1868 pci_set_max_read_req(device_t dev, int size) 1869 { 1870 struct pci_devinfo *dinfo = device_get_ivars(dev); 1871 int cap; 1872 uint16_t val; 1873 1874 cap = dinfo->cfg.pcie.pcie_location; 1875 if (cap == 0) 1876 return (0); 1877 if (size < 128) 1878 size = 128; 1879 if (size > 4096) 1880 size = 4096; 1881 size = (1 << (fls(size) - 1)); 1882 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 1883 val &= ~PCIEM_CTL_MAX_READ_REQUEST; 1884 val |= (fls(size) - 8) << 12; 1885 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2); 1886 return (size); 1887 } 1888 1889 /* 1890 * Support for MSI message signalled interrupts. 1891 */ 1892 void 1893 pci_enable_msi_method(device_t dev, device_t child, uint64_t address, 1894 uint16_t data) 1895 { 1896 struct pci_devinfo *dinfo = device_get_ivars(child); 1897 struct pcicfg_msi *msi = &dinfo->cfg.msi; 1898 1899 /* Write data and address values. */ 1900 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, 1901 address & 0xffffffff, 4); 1902 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 1903 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, 1904 address >> 32, 4); 1905 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, 1906 data, 2); 1907 } else 1908 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, 1909 2); 1910 1911 /* Enable MSI in the control register. */ 1912 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 1913 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 1914 msi->msi_ctrl, 2); 1915 1916 /* Enable MSI -> HT mapping. */ 1917 pci_ht_map_msi(child, address); 1918 } 1919 1920 void 1921 pci_disable_msi_method(device_t dev, device_t child) 1922 { 1923 struct pci_devinfo *dinfo = device_get_ivars(child); 1924 struct pcicfg_msi *msi = &dinfo->cfg.msi; 1925 1926 /* Disable MSI -> HT mapping. */ 1927 pci_ht_map_msi(child, 0); 1928 1929 /* Disable MSI in the control register. */ 1930 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; 1931 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 1932 msi->msi_ctrl, 2); 1933 } 1934 1935 /* 1936 * Restore MSI registers during resume. If MSI is enabled then 1937 * restore the data and address registers in addition to the control 1938 * register. 1939 */ 1940 static void 1941 pci_resume_msi(device_t dev) 1942 { 1943 struct pci_devinfo *dinfo = device_get_ivars(dev); 1944 struct pcicfg_msi *msi = &dinfo->cfg.msi; 1945 uint64_t address; 1946 uint16_t data; 1947 1948 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 1949 address = msi->msi_addr; 1950 data = msi->msi_data; 1951 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 1952 address & 0xffffffff, 4); 1953 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 1954 pci_write_config(dev, msi->msi_location + 1955 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 1956 pci_write_config(dev, msi->msi_location + 1957 PCIR_MSI_DATA_64BIT, data, 2); 1958 } else 1959 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, 1960 data, 2); 1961 } 1962 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 1963 2); 1964 } 1965 1966 static int 1967 pci_remap_intr_method(device_t bus, device_t dev, u_int irq) 1968 { 1969 struct pci_devinfo *dinfo = device_get_ivars(dev); 1970 pcicfgregs *cfg = &dinfo->cfg; 1971 struct resource_list_entry *rle; 1972 struct msix_table_entry *mte; 1973 struct msix_vector *mv; 1974 uint64_t addr; 1975 uint32_t data; 1976 int error, i, j; 1977 1978 /* 1979 * Handle MSI first. We try to find this IRQ among our list 1980 * of MSI IRQs. If we find it, we request updated address and 1981 * data registers and apply the results. 1982 */ 1983 if (cfg->msi.msi_alloc > 0) { 1984 1985 /* If we don't have any active handlers, nothing to do. */ 1986 if (cfg->msi.msi_handlers == 0) 1987 return (0); 1988 for (i = 0; i < cfg->msi.msi_alloc; i++) { 1989 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1990 i + 1); 1991 if (rle->start == irq) { 1992 error = PCIB_MAP_MSI(device_get_parent(bus), 1993 dev, irq, &addr, &data); 1994 if (error) 1995 return (error); 1996 pci_disable_msi(dev); 1997 dinfo->cfg.msi.msi_addr = addr; 1998 dinfo->cfg.msi.msi_data = data; 1999 pci_enable_msi(dev, addr, data); 2000 return (0); 2001 } 2002 } 2003 return (ENOENT); 2004 } 2005 2006 /* 2007 * For MSI-X, we check to see if we have this IRQ. If we do, 2008 * we request the updated mapping info. If that works, we go 2009 * through all the slots that use this IRQ and update them. 2010 */ 2011 if (cfg->msix.msix_alloc > 0) { 2012 for (i = 0; i < cfg->msix.msix_alloc; i++) { 2013 mv = &cfg->msix.msix_vectors[i]; 2014 if (mv->mv_irq == irq) { 2015 error = PCIB_MAP_MSI(device_get_parent(bus), 2016 dev, irq, &addr, &data); 2017 if (error) 2018 return (error); 2019 mv->mv_address = addr; 2020 mv->mv_data = data; 2021 for (j = 0; j < cfg->msix.msix_table_len; j++) { 2022 mte = &cfg->msix.msix_table[j]; 2023 if (mte->mte_vector != i + 1) 2024 continue; 2025 if (mte->mte_handlers == 0) 2026 continue; 2027 pci_mask_msix(dev, j); 2028 pci_enable_msix(dev, j, addr, data); 2029 pci_unmask_msix(dev, j); 2030 } 2031 } 2032 } 2033 return (ENOENT); 2034 } 2035 2036 return (ENOENT); 2037 } 2038 2039 /* 2040 * Returns true if the specified device is blacklisted because MSI 2041 * doesn't work. 2042 */ 2043 int 2044 pci_msi_device_blacklisted(device_t dev) 2045 { 2046 2047 if (!pci_honor_msi_blacklist) 2048 return (0); 2049 2050 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI)); 2051 } 2052 2053 /* 2054 * Determine if MSI is blacklisted globally on this system. Currently, 2055 * we just check for blacklisted chipsets as represented by the 2056 * host-PCI bridge at device 0:0:0. In the future, it may become 2057 * necessary to check other system attributes, such as the kenv values 2058 * that give the motherboard manufacturer and model number. 2059 */ 2060 static int 2061 pci_msi_blacklisted(void) 2062 { 2063 device_t dev; 2064 2065 if (!pci_honor_msi_blacklist) 2066 return (0); 2067 2068 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ 2069 if (!(pcie_chipset || pcix_chipset)) { 2070 if (vm_guest != VM_GUEST_NO) { 2071 /* 2072 * Whitelist older chipsets in virtual 2073 * machines known to support MSI. 2074 */ 2075 dev = pci_find_bsf(0, 0, 0); 2076 if (dev != NULL) 2077 return (!pci_has_quirk(pci_get_devid(dev), 2078 PCI_QUIRK_ENABLE_MSI_VM)); 2079 } 2080 return (1); 2081 } 2082 2083 dev = pci_find_bsf(0, 0, 0); 2084 if (dev != NULL) 2085 return (pci_msi_device_blacklisted(dev)); 2086 return (0); 2087 } 2088 2089 /* 2090 * Returns true if the specified device is blacklisted because MSI-X 2091 * doesn't work. Note that this assumes that if MSI doesn't work, 2092 * MSI-X doesn't either. 2093 */ 2094 int 2095 pci_msix_device_blacklisted(device_t dev) 2096 { 2097 2098 if (!pci_honor_msi_blacklist) 2099 return (0); 2100 2101 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX)) 2102 return (1); 2103 2104 return (pci_msi_device_blacklisted(dev)); 2105 } 2106 2107 /* 2108 * Determine if MSI-X is blacklisted globally on this system. If MSI 2109 * is blacklisted, assume that MSI-X is as well. Check for additional 2110 * chipsets where MSI works but MSI-X does not. 2111 */ 2112 static int 2113 pci_msix_blacklisted(void) 2114 { 2115 device_t dev; 2116 2117 if (!pci_honor_msi_blacklist) 2118 return (0); 2119 2120 dev = pci_find_bsf(0, 0, 0); 2121 if (dev != NULL && pci_has_quirk(pci_get_devid(dev), 2122 PCI_QUIRK_DISABLE_MSIX)) 2123 return (1); 2124 2125 return (pci_msi_blacklisted()); 2126 } 2127 2128 /* 2129 * Attempt to allocate *count MSI messages. The actual number allocated is 2130 * returned in *count. After this function returns, each message will be 2131 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 2132 */ 2133 int 2134 pci_alloc_msi_method(device_t dev, device_t child, int *count) 2135 { 2136 struct pci_devinfo *dinfo = device_get_ivars(child); 2137 pcicfgregs *cfg = &dinfo->cfg; 2138 struct resource_list_entry *rle; 2139 int actual, error, i, irqs[32]; 2140 uint16_t ctrl; 2141 2142 /* Don't let count == 0 get us into trouble. */ 2143 if (*count == 0) 2144 return (EINVAL); 2145 2146 /* If rid 0 is allocated, then fail. */ 2147 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 2148 if (rle != NULL && rle->res != NULL) 2149 return (ENXIO); 2150 2151 /* Already have allocated messages? */ 2152 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 2153 return (ENXIO); 2154 2155 /* If MSI is blacklisted for this system, fail. */ 2156 if (pci_msi_blacklisted()) 2157 return (ENXIO); 2158 2159 /* MSI capability present? */ 2160 if (cfg->msi.msi_location == 0 || !pci_do_msi) 2161 return (ENODEV); 2162 2163 if (bootverbose) 2164 device_printf(child, 2165 "attempting to allocate %d MSI vectors (%d supported)\n", 2166 *count, cfg->msi.msi_msgnum); 2167 2168 /* Don't ask for more than the device supports. */ 2169 actual = min(*count, cfg->msi.msi_msgnum); 2170 2171 /* Don't ask for more than 32 messages. */ 2172 actual = min(actual, 32); 2173 2174 /* MSI requires power of 2 number of messages. */ 2175 if (!powerof2(actual)) 2176 return (EINVAL); 2177 2178 for (;;) { 2179 /* Try to allocate N messages. */ 2180 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 2181 actual, irqs); 2182 if (error == 0) 2183 break; 2184 if (actual == 1) 2185 return (error); 2186 2187 /* Try N / 2. */ 2188 actual >>= 1; 2189 } 2190 2191 /* 2192 * We now have N actual messages mapped onto SYS_RES_IRQ 2193 * resources in the irqs[] array, so add new resources 2194 * starting at rid 1. 2195 */ 2196 for (i = 0; i < actual; i++) 2197 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 2198 irqs[i], irqs[i], 1); 2199 2200 if (bootverbose) { 2201 if (actual == 1) 2202 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 2203 else { 2204 int run; 2205 2206 /* 2207 * Be fancy and try to print contiguous runs 2208 * of IRQ values as ranges. 'run' is true if 2209 * we are in a range. 2210 */ 2211 device_printf(child, "using IRQs %d", irqs[0]); 2212 run = 0; 2213 for (i = 1; i < actual; i++) { 2214 2215 /* Still in a run? */ 2216 if (irqs[i] == irqs[i - 1] + 1) { 2217 run = 1; 2218 continue; 2219 } 2220 2221 /* Finish previous range. */ 2222 if (run) { 2223 printf("-%d", irqs[i - 1]); 2224 run = 0; 2225 } 2226 2227 /* Start new range. */ 2228 printf(",%d", irqs[i]); 2229 } 2230 2231 /* Unfinished range? */ 2232 if (run) 2233 printf("-%d", irqs[actual - 1]); 2234 printf(" for MSI\n"); 2235 } 2236 } 2237 2238 /* Update control register with actual count. */ 2239 ctrl = cfg->msi.msi_ctrl; 2240 ctrl &= ~PCIM_MSICTRL_MME_MASK; 2241 ctrl |= (ffs(actual) - 1) << 4; 2242 cfg->msi.msi_ctrl = ctrl; 2243 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 2244 2245 /* Update counts of alloc'd messages. */ 2246 cfg->msi.msi_alloc = actual; 2247 cfg->msi.msi_handlers = 0; 2248 *count = actual; 2249 return (0); 2250 } 2251 2252 /* Release the MSI messages associated with this device. */ 2253 int 2254 pci_release_msi_method(device_t dev, device_t child) 2255 { 2256 struct pci_devinfo *dinfo = device_get_ivars(child); 2257 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2258 struct resource_list_entry *rle; 2259 int error, i, irqs[32]; 2260 2261 /* Try MSI-X first. */ 2262 error = pci_release_msix(dev, child); 2263 if (error != ENODEV) 2264 return (error); 2265 2266 /* Do we have any messages to release? */ 2267 if (msi->msi_alloc == 0) 2268 return (ENODEV); 2269 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); 2270 2271 /* Make sure none of the resources are allocated. */ 2272 if (msi->msi_handlers > 0) 2273 return (EBUSY); 2274 for (i = 0; i < msi->msi_alloc; i++) { 2275 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2276 KASSERT(rle != NULL, ("missing MSI resource")); 2277 if (rle->res != NULL) 2278 return (EBUSY); 2279 irqs[i] = rle->start; 2280 } 2281 2282 /* Update control register with 0 count. */ 2283 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), 2284 ("%s: MSI still enabled", __func__)); 2285 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; 2286 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2287 msi->msi_ctrl, 2); 2288 2289 /* Release the messages. */ 2290 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); 2291 for (i = 0; i < msi->msi_alloc; i++) 2292 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2293 2294 /* Update alloc count. */ 2295 msi->msi_alloc = 0; 2296 msi->msi_addr = 0; 2297 msi->msi_data = 0; 2298 return (0); 2299 } 2300 2301 /* 2302 * Return the max supported MSI messages this device supports. 2303 * Basically, assuming the MD code can alloc messages, this function 2304 * should return the maximum value that pci_alloc_msi() can return. 2305 * Thus, it is subject to the tunables, etc. 2306 */ 2307 int 2308 pci_msi_count_method(device_t dev, device_t child) 2309 { 2310 struct pci_devinfo *dinfo = device_get_ivars(child); 2311 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2312 2313 if (pci_do_msi && msi->msi_location != 0) 2314 return (msi->msi_msgnum); 2315 return (0); 2316 } 2317 2318 /* free pcicfgregs structure and all depending data structures */ 2319 2320 int 2321 pci_freecfg(struct pci_devinfo *dinfo) 2322 { 2323 struct devlist *devlist_head; 2324 struct pci_map *pm, *next; 2325 int i; 2326 2327 devlist_head = &pci_devq; 2328 2329 if (dinfo->cfg.vpd.vpd_reg) { 2330 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF); 2331 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++) 2332 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF); 2333 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF); 2334 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++) 2335 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF); 2336 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF); 2337 } 2338 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { 2339 free(pm, M_DEVBUF); 2340 } 2341 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 2342 free(dinfo, M_DEVBUF); 2343 2344 /* increment the generation count */ 2345 pci_generation++; 2346 2347 /* we're losing one device */ 2348 pci_numdevs--; 2349 return (0); 2350 } 2351 2352 /* 2353 * PCI power manangement 2354 */ 2355 int 2356 pci_set_powerstate_method(device_t dev, device_t child, int state) 2357 { 2358 struct pci_devinfo *dinfo = device_get_ivars(child); 2359 pcicfgregs *cfg = &dinfo->cfg; 2360 uint16_t status; 2361 int result, oldstate, highest, delay; 2362 2363 if (cfg->pp.pp_cap == 0) 2364 return (EOPNOTSUPP); 2365 2366 /* 2367 * Optimize a no state change request away. While it would be OK to 2368 * write to the hardware in theory, some devices have shown odd 2369 * behavior when going from D3 -> D3. 2370 */ 2371 oldstate = pci_get_powerstate(child); 2372 if (oldstate == state) 2373 return (0); 2374 2375 /* 2376 * The PCI power management specification states that after a state 2377 * transition between PCI power states, system software must 2378 * guarantee a minimal delay before the function accesses the device. 2379 * Compute the worst case delay that we need to guarantee before we 2380 * access the device. Many devices will be responsive much more 2381 * quickly than this delay, but there are some that don't respond 2382 * instantly to state changes. Transitions to/from D3 state require 2383 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 2384 * is done below with DELAY rather than a sleeper function because 2385 * this function can be called from contexts where we cannot sleep. 2386 */ 2387 highest = (oldstate > state) ? oldstate : state; 2388 if (highest == PCI_POWERSTATE_D3) 2389 delay = 10000; 2390 else if (highest == PCI_POWERSTATE_D2) 2391 delay = 200; 2392 else 2393 delay = 0; 2394 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 2395 & ~PCIM_PSTAT_DMASK; 2396 result = 0; 2397 switch (state) { 2398 case PCI_POWERSTATE_D0: 2399 status |= PCIM_PSTAT_D0; 2400 break; 2401 case PCI_POWERSTATE_D1: 2402 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 2403 return (EOPNOTSUPP); 2404 status |= PCIM_PSTAT_D1; 2405 break; 2406 case PCI_POWERSTATE_D2: 2407 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 2408 return (EOPNOTSUPP); 2409 status |= PCIM_PSTAT_D2; 2410 break; 2411 case PCI_POWERSTATE_D3: 2412 status |= PCIM_PSTAT_D3; 2413 break; 2414 default: 2415 return (EINVAL); 2416 } 2417 2418 if (bootverbose) 2419 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate, 2420 state); 2421 2422 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 2423 if (delay) 2424 DELAY(delay); 2425 return (0); 2426 } 2427 2428 int 2429 pci_get_powerstate_method(device_t dev, device_t child) 2430 { 2431 struct pci_devinfo *dinfo = device_get_ivars(child); 2432 pcicfgregs *cfg = &dinfo->cfg; 2433 uint16_t status; 2434 int result; 2435 2436 if (cfg->pp.pp_cap != 0) { 2437 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 2438 switch (status & PCIM_PSTAT_DMASK) { 2439 case PCIM_PSTAT_D0: 2440 result = PCI_POWERSTATE_D0; 2441 break; 2442 case PCIM_PSTAT_D1: 2443 result = PCI_POWERSTATE_D1; 2444 break; 2445 case PCIM_PSTAT_D2: 2446 result = PCI_POWERSTATE_D2; 2447 break; 2448 case PCIM_PSTAT_D3: 2449 result = PCI_POWERSTATE_D3; 2450 break; 2451 default: 2452 result = PCI_POWERSTATE_UNKNOWN; 2453 break; 2454 } 2455 } else { 2456 /* No support, device is always at D0 */ 2457 result = PCI_POWERSTATE_D0; 2458 } 2459 return (result); 2460 } 2461 2462 /* 2463 * Some convenience functions for PCI device drivers. 2464 */ 2465 2466 static __inline void 2467 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 2468 { 2469 uint16_t command; 2470 2471 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2472 command |= bit; 2473 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2474 } 2475 2476 static __inline void 2477 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 2478 { 2479 uint16_t command; 2480 2481 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2482 command &= ~bit; 2483 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2484 } 2485 2486 int 2487 pci_enable_busmaster_method(device_t dev, device_t child) 2488 { 2489 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2490 return (0); 2491 } 2492 2493 int 2494 pci_disable_busmaster_method(device_t dev, device_t child) 2495 { 2496 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2497 return (0); 2498 } 2499 2500 int 2501 pci_enable_io_method(device_t dev, device_t child, int space) 2502 { 2503 uint16_t bit; 2504 2505 switch(space) { 2506 case SYS_RES_IOPORT: 2507 bit = PCIM_CMD_PORTEN; 2508 break; 2509 case SYS_RES_MEMORY: 2510 bit = PCIM_CMD_MEMEN; 2511 break; 2512 default: 2513 return (EINVAL); 2514 } 2515 pci_set_command_bit(dev, child, bit); 2516 return (0); 2517 } 2518 2519 int 2520 pci_disable_io_method(device_t dev, device_t child, int space) 2521 { 2522 uint16_t bit; 2523 2524 switch(space) { 2525 case SYS_RES_IOPORT: 2526 bit = PCIM_CMD_PORTEN; 2527 break; 2528 case SYS_RES_MEMORY: 2529 bit = PCIM_CMD_MEMEN; 2530 break; 2531 default: 2532 return (EINVAL); 2533 } 2534 pci_clear_command_bit(dev, child, bit); 2535 return (0); 2536 } 2537 2538 /* 2539 * New style pci driver. Parent device is either a pci-host-bridge or a 2540 * pci-pci-bridge. Both kinds are represented by instances of pcib. 2541 */ 2542 2543 void 2544 pci_print_verbose(struct pci_devinfo *dinfo) 2545 { 2546 2547 if (bootverbose) { 2548 pcicfgregs *cfg = &dinfo->cfg; 2549 2550 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 2551 cfg->vendor, cfg->device, cfg->revid); 2552 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n", 2553 cfg->domain, cfg->bus, cfg->slot, cfg->func); 2554 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 2555 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 2556 cfg->mfdev); 2557 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 2558 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 2559 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 2560 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 2561 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 2562 if (cfg->intpin > 0) 2563 printf("\tintpin=%c, irq=%d\n", 2564 cfg->intpin +'a' -1, cfg->intline); 2565 if (cfg->pp.pp_cap) { 2566 uint16_t status; 2567 2568 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 2569 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 2570 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 2571 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 2572 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 2573 status & PCIM_PSTAT_DMASK); 2574 } 2575 if (cfg->msi.msi_location) { 2576 int ctrl; 2577 2578 ctrl = cfg->msi.msi_ctrl; 2579 printf("\tMSI supports %d message%s%s%s\n", 2580 cfg->msi.msi_msgnum, 2581 (cfg->msi.msi_msgnum == 1) ? "" : "s", 2582 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 2583 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 2584 } 2585 if (cfg->msix.msix_location) { 2586 printf("\tMSI-X supports %d message%s ", 2587 cfg->msix.msix_msgnum, 2588 (cfg->msix.msix_msgnum == 1) ? "" : "s"); 2589 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 2590 printf("in map 0x%x\n", 2591 cfg->msix.msix_table_bar); 2592 else 2593 printf("in maps 0x%x and 0x%x\n", 2594 cfg->msix.msix_table_bar, 2595 cfg->msix.msix_pba_bar); 2596 } 2597 } 2598 } 2599 2600 static int 2601 pci_porten(device_t dev) 2602 { 2603 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0; 2604 } 2605 2606 static int 2607 pci_memen(device_t dev) 2608 { 2609 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0; 2610 } 2611 2612 static void 2613 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp) 2614 { 2615 struct pci_devinfo *dinfo; 2616 pci_addr_t map, testval; 2617 int ln2range; 2618 uint16_t cmd; 2619 2620 /* 2621 * The device ROM BAR is special. It is always a 32-bit 2622 * memory BAR. Bit 0 is special and should not be set when 2623 * sizing the BAR. 2624 */ 2625 dinfo = device_get_ivars(dev); 2626 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { 2627 map = pci_read_config(dev, reg, 4); 2628 pci_write_config(dev, reg, 0xfffffffe, 4); 2629 testval = pci_read_config(dev, reg, 4); 2630 pci_write_config(dev, reg, map, 4); 2631 *mapp = map; 2632 *testvalp = testval; 2633 return; 2634 } 2635 2636 map = pci_read_config(dev, reg, 4); 2637 ln2range = pci_maprange(map); 2638 if (ln2range == 64) 2639 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 2640 2641 /* 2642 * Disable decoding via the command register before 2643 * determining the BAR's length since we will be placing it in 2644 * a weird state. 2645 */ 2646 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 2647 pci_write_config(dev, PCIR_COMMAND, 2648 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 2649 2650 /* 2651 * Determine the BAR's length by writing all 1's. The bottom 2652 * log_2(size) bits of the BAR will stick as 0 when we read 2653 * the value back. 2654 */ 2655 pci_write_config(dev, reg, 0xffffffff, 4); 2656 testval = pci_read_config(dev, reg, 4); 2657 if (ln2range == 64) { 2658 pci_write_config(dev, reg + 4, 0xffffffff, 4); 2659 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 2660 } 2661 2662 /* 2663 * Restore the original value of the BAR. We may have reprogrammed 2664 * the BAR of the low-level console device and when booting verbose, 2665 * we need the console device addressable. 2666 */ 2667 pci_write_config(dev, reg, map, 4); 2668 if (ln2range == 64) 2669 pci_write_config(dev, reg + 4, map >> 32, 4); 2670 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 2671 2672 *mapp = map; 2673 *testvalp = testval; 2674 } 2675 2676 static void 2677 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base) 2678 { 2679 struct pci_devinfo *dinfo; 2680 int ln2range; 2681 2682 /* The device ROM BAR is always a 32-bit memory BAR. */ 2683 dinfo = device_get_ivars(dev); 2684 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 2685 ln2range = 32; 2686 else 2687 ln2range = pci_maprange(pm->pm_value); 2688 pci_write_config(dev, pm->pm_reg, base, 4); 2689 if (ln2range == 64) 2690 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); 2691 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); 2692 if (ln2range == 64) 2693 pm->pm_value |= (pci_addr_t)pci_read_config(dev, 2694 pm->pm_reg + 4, 4) << 32; 2695 } 2696 2697 struct pci_map * 2698 pci_find_bar(device_t dev, int reg) 2699 { 2700 struct pci_devinfo *dinfo; 2701 struct pci_map *pm; 2702 2703 dinfo = device_get_ivars(dev); 2704 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 2705 if (pm->pm_reg == reg) 2706 return (pm); 2707 } 2708 return (NULL); 2709 } 2710 2711 int 2712 pci_bar_enabled(device_t dev, struct pci_map *pm) 2713 { 2714 struct pci_devinfo *dinfo; 2715 uint16_t cmd; 2716 2717 dinfo = device_get_ivars(dev); 2718 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && 2719 !(pm->pm_value & PCIM_BIOS_ENABLE)) 2720 return (0); 2721 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 2722 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) 2723 return ((cmd & PCIM_CMD_MEMEN) != 0); 2724 else 2725 return ((cmd & PCIM_CMD_PORTEN) != 0); 2726 } 2727 2728 static struct pci_map * 2729 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size) 2730 { 2731 struct pci_devinfo *dinfo; 2732 struct pci_map *pm, *prev; 2733 2734 dinfo = device_get_ivars(dev); 2735 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO); 2736 pm->pm_reg = reg; 2737 pm->pm_value = value; 2738 pm->pm_size = size; 2739 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { 2740 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", 2741 reg)); 2742 if (STAILQ_NEXT(prev, pm_link) == NULL || 2743 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) 2744 break; 2745 } 2746 if (prev != NULL) 2747 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); 2748 else 2749 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); 2750 return (pm); 2751 } 2752 2753 static void 2754 pci_restore_bars(device_t dev) 2755 { 2756 struct pci_devinfo *dinfo; 2757 struct pci_map *pm; 2758 int ln2range; 2759 2760 dinfo = device_get_ivars(dev); 2761 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 2762 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 2763 ln2range = 32; 2764 else 2765 ln2range = pci_maprange(pm->pm_value); 2766 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); 2767 if (ln2range == 64) 2768 pci_write_config(dev, pm->pm_reg + 4, 2769 pm->pm_value >> 32, 4); 2770 } 2771 } 2772 2773 /* 2774 * Add a resource based on a pci map register. Return 1 if the map 2775 * register is a 32bit map register or 2 if it is a 64bit register. 2776 */ 2777 static int 2778 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, 2779 int force, int prefetch) 2780 { 2781 struct pci_map *pm; 2782 pci_addr_t base, map, testval; 2783 pci_addr_t start, end, count; 2784 int barlen, basezero, flags, maprange, mapsize, type; 2785 uint16_t cmd; 2786 struct resource *res; 2787 2788 /* 2789 * The BAR may already exist if the device is a CardBus card 2790 * whose CIS is stored in this BAR. 2791 */ 2792 pm = pci_find_bar(dev, reg); 2793 if (pm != NULL) { 2794 maprange = pci_maprange(pm->pm_value); 2795 barlen = maprange == 64 ? 2 : 1; 2796 return (barlen); 2797 } 2798 2799 pci_read_bar(dev, reg, &map, &testval); 2800 if (PCI_BAR_MEM(map)) { 2801 type = SYS_RES_MEMORY; 2802 if (map & PCIM_BAR_MEM_PREFETCH) 2803 prefetch = 1; 2804 } else 2805 type = SYS_RES_IOPORT; 2806 mapsize = pci_mapsize(testval); 2807 base = pci_mapbase(map); 2808 #ifdef __PCI_BAR_ZERO_VALID 2809 basezero = 0; 2810 #else 2811 basezero = base == 0; 2812 #endif 2813 maprange = pci_maprange(map); 2814 barlen = maprange == 64 ? 2 : 1; 2815 2816 /* 2817 * For I/O registers, if bottom bit is set, and the next bit up 2818 * isn't clear, we know we have a BAR that doesn't conform to the 2819 * spec, so ignore it. Also, sanity check the size of the data 2820 * areas to the type of memory involved. Memory must be at least 2821 * 16 bytes in size, while I/O ranges must be at least 4. 2822 */ 2823 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0) 2824 return (barlen); 2825 if ((type == SYS_RES_MEMORY && mapsize < 4) || 2826 (type == SYS_RES_IOPORT && mapsize < 2)) 2827 return (barlen); 2828 2829 /* Save a record of this BAR. */ 2830 pm = pci_add_bar(dev, reg, map, mapsize); 2831 if (bootverbose) { 2832 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d", 2833 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize); 2834 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 2835 printf(", port disabled\n"); 2836 else if (type == SYS_RES_MEMORY && !pci_memen(dev)) 2837 printf(", memory disabled\n"); 2838 else 2839 printf(", enabled\n"); 2840 } 2841 2842 /* 2843 * If base is 0, then we have problems if this architecture does 2844 * not allow that. It is best to ignore such entries for the 2845 * moment. These will be allocated later if the driver specifically 2846 * requests them. However, some removable busses look better when 2847 * all resources are allocated, so allow '0' to be overriden. 2848 * 2849 * Similarly treat maps whose values is the same as the test value 2850 * read back. These maps have had all f's written to them by the 2851 * BIOS in an attempt to disable the resources. 2852 */ 2853 if (!force && (basezero || map == testval)) 2854 return (barlen); 2855 if ((u_long)base != base) { 2856 device_printf(bus, 2857 "pci%d:%d:%d:%d bar %#x too many address bits", 2858 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev), 2859 pci_get_function(dev), reg); 2860 return (barlen); 2861 } 2862 2863 /* 2864 * This code theoretically does the right thing, but has 2865 * undesirable side effects in some cases where peripherals 2866 * respond oddly to having these bits enabled. Let the user 2867 * be able to turn them off (since pci_enable_io_modes is 1 by 2868 * default). 2869 */ 2870 if (pci_enable_io_modes) { 2871 /* Turn on resources that have been left off by a lazy BIOS */ 2872 if (type == SYS_RES_IOPORT && !pci_porten(dev)) { 2873 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 2874 cmd |= PCIM_CMD_PORTEN; 2875 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 2876 } 2877 if (type == SYS_RES_MEMORY && !pci_memen(dev)) { 2878 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 2879 cmd |= PCIM_CMD_MEMEN; 2880 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 2881 } 2882 } else { 2883 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 2884 return (barlen); 2885 if (type == SYS_RES_MEMORY && !pci_memen(dev)) 2886 return (barlen); 2887 } 2888 2889 count = (pci_addr_t)1 << mapsize; 2890 flags = RF_ALIGNMENT_LOG2(mapsize); 2891 if (prefetch) 2892 flags |= RF_PREFETCHABLE; 2893 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) { 2894 start = 0; /* Let the parent decide. */ 2895 end = ~0ul; 2896 } else { 2897 start = base; 2898 end = base + count - 1; 2899 } 2900 resource_list_add(rl, type, reg, start, end, count); 2901 2902 /* 2903 * Try to allocate the resource for this BAR from our parent 2904 * so that this resource range is already reserved. The 2905 * driver for this device will later inherit this resource in 2906 * pci_alloc_resource(). 2907 */ 2908 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count, 2909 flags); 2910 if (pci_do_realloc_bars && res == NULL && (start != 0 || end != ~0ul)) { 2911 /* 2912 * If the allocation fails, try to allocate a resource for 2913 * this BAR using any available range. The firmware felt 2914 * it was important enough to assign a resource, so don't 2915 * disable decoding if we can help it. 2916 */ 2917 resource_list_delete(rl, type, reg); 2918 resource_list_add(rl, type, reg, 0, ~0ul, count); 2919 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0ul, 2920 count, flags); 2921 } 2922 if (res == NULL) { 2923 /* 2924 * If the allocation fails, delete the resource list entry 2925 * and disable decoding for this device. 2926 * 2927 * If the driver requests this resource in the future, 2928 * pci_reserve_map() will try to allocate a fresh 2929 * resource range. 2930 */ 2931 resource_list_delete(rl, type, reg); 2932 pci_disable_io(dev, type); 2933 if (bootverbose) 2934 device_printf(bus, 2935 "pci%d:%d:%d:%d bar %#x failed to allocate\n", 2936 pci_get_domain(dev), pci_get_bus(dev), 2937 pci_get_slot(dev), pci_get_function(dev), reg); 2938 } else { 2939 start = rman_get_start(res); 2940 pci_write_bar(dev, pm, start); 2941 } 2942 return (barlen); 2943 } 2944 2945 /* 2946 * For ATA devices we need to decide early what addressing mode to use. 2947 * Legacy demands that the primary and secondary ATA ports sits on the 2948 * same addresses that old ISA hardware did. This dictates that we use 2949 * those addresses and ignore the BAR's if we cannot set PCI native 2950 * addressing mode. 2951 */ 2952 static void 2953 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, 2954 uint32_t prefetchmask) 2955 { 2956 struct resource *r; 2957 int rid, type, progif; 2958 #if 0 2959 /* if this device supports PCI native addressing use it */ 2960 progif = pci_read_config(dev, PCIR_PROGIF, 1); 2961 if ((progif & 0x8a) == 0x8a) { 2962 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 2963 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 2964 printf("Trying ATA native PCI addressing mode\n"); 2965 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 2966 } 2967 } 2968 #endif 2969 progif = pci_read_config(dev, PCIR_PROGIF, 1); 2970 type = SYS_RES_IOPORT; 2971 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 2972 pci_add_map(bus, dev, PCIR_BAR(0), rl, force, 2973 prefetchmask & (1 << 0)); 2974 pci_add_map(bus, dev, PCIR_BAR(1), rl, force, 2975 prefetchmask & (1 << 1)); 2976 } else { 2977 rid = PCIR_BAR(0); 2978 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 2979 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0, 2980 0x1f7, 8, 0); 2981 rid = PCIR_BAR(1); 2982 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 2983 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6, 2984 0x3f6, 1, 0); 2985 } 2986 if (progif & PCIP_STORAGE_IDE_MODESEC) { 2987 pci_add_map(bus, dev, PCIR_BAR(2), rl, force, 2988 prefetchmask & (1 << 2)); 2989 pci_add_map(bus, dev, PCIR_BAR(3), rl, force, 2990 prefetchmask & (1 << 3)); 2991 } else { 2992 rid = PCIR_BAR(2); 2993 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 2994 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x170, 2995 0x177, 8, 0); 2996 rid = PCIR_BAR(3); 2997 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 2998 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x376, 2999 0x376, 1, 0); 3000 } 3001 pci_add_map(bus, dev, PCIR_BAR(4), rl, force, 3002 prefetchmask & (1 << 4)); 3003 pci_add_map(bus, dev, PCIR_BAR(5), rl, force, 3004 prefetchmask & (1 << 5)); 3005 } 3006 3007 static void 3008 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 3009 { 3010 struct pci_devinfo *dinfo = device_get_ivars(dev); 3011 pcicfgregs *cfg = &dinfo->cfg; 3012 char tunable_name[64]; 3013 int irq; 3014 3015 /* Has to have an intpin to have an interrupt. */ 3016 if (cfg->intpin == 0) 3017 return; 3018 3019 /* Let the user override the IRQ with a tunable. */ 3020 irq = PCI_INVALID_IRQ; 3021 snprintf(tunable_name, sizeof(tunable_name), 3022 "hw.pci%d.%d.%d.INT%c.irq", 3023 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 3024 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 3025 irq = PCI_INVALID_IRQ; 3026 3027 /* 3028 * If we didn't get an IRQ via the tunable, then we either use the 3029 * IRQ value in the intline register or we ask the bus to route an 3030 * interrupt for us. If force_route is true, then we only use the 3031 * value in the intline register if the bus was unable to assign an 3032 * IRQ. 3033 */ 3034 if (!PCI_INTERRUPT_VALID(irq)) { 3035 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 3036 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 3037 if (!PCI_INTERRUPT_VALID(irq)) 3038 irq = cfg->intline; 3039 } 3040 3041 /* If after all that we don't have an IRQ, just bail. */ 3042 if (!PCI_INTERRUPT_VALID(irq)) 3043 return; 3044 3045 /* Update the config register if it changed. */ 3046 if (irq != cfg->intline) { 3047 cfg->intline = irq; 3048 pci_write_config(dev, PCIR_INTLINE, irq, 1); 3049 } 3050 3051 /* Add this IRQ as rid 0 interrupt resource. */ 3052 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 3053 } 3054 3055 /* Perform early OHCI takeover from SMM. */ 3056 static void 3057 ohci_early_takeover(device_t self) 3058 { 3059 struct resource *res; 3060 uint32_t ctl; 3061 int rid; 3062 int i; 3063 3064 rid = PCIR_BAR(0); 3065 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3066 if (res == NULL) 3067 return; 3068 3069 ctl = bus_read_4(res, OHCI_CONTROL); 3070 if (ctl & OHCI_IR) { 3071 if (bootverbose) 3072 printf("ohci early: " 3073 "SMM active, request owner change\n"); 3074 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR); 3075 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 3076 DELAY(1000); 3077 ctl = bus_read_4(res, OHCI_CONTROL); 3078 } 3079 if (ctl & OHCI_IR) { 3080 if (bootverbose) 3081 printf("ohci early: " 3082 "SMM does not respond, resetting\n"); 3083 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET); 3084 } 3085 /* Disable interrupts */ 3086 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 3087 } 3088 3089 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3090 } 3091 3092 /* Perform early UHCI takeover from SMM. */ 3093 static void 3094 uhci_early_takeover(device_t self) 3095 { 3096 struct resource *res; 3097 int rid; 3098 3099 /* 3100 * Set the PIRQD enable bit and switch off all the others. We don't 3101 * want legacy support to interfere with us XXX Does this also mean 3102 * that the BIOS won't touch the keyboard anymore if it is connected 3103 * to the ports of the root hub? 3104 */ 3105 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2); 3106 3107 /* Disable interrupts */ 3108 rid = PCI_UHCI_BASE_REG; 3109 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE); 3110 if (res != NULL) { 3111 bus_write_2(res, UHCI_INTR, 0); 3112 bus_release_resource(self, SYS_RES_IOPORT, rid, res); 3113 } 3114 } 3115 3116 /* Perform early EHCI takeover from SMM. */ 3117 static void 3118 ehci_early_takeover(device_t self) 3119 { 3120 struct resource *res; 3121 uint32_t cparams; 3122 uint32_t eec; 3123 uint8_t eecp; 3124 uint8_t bios_sem; 3125 uint8_t offs; 3126 int rid; 3127 int i; 3128 3129 rid = PCIR_BAR(0); 3130 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3131 if (res == NULL) 3132 return; 3133 3134 cparams = bus_read_4(res, EHCI_HCCPARAMS); 3135 3136 /* Synchronise with the BIOS if it owns the controller. */ 3137 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0; 3138 eecp = EHCI_EECP_NEXT(eec)) { 3139 eec = pci_read_config(self, eecp, 4); 3140 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) { 3141 continue; 3142 } 3143 bios_sem = pci_read_config(self, eecp + 3144 EHCI_LEGSUP_BIOS_SEM, 1); 3145 if (bios_sem == 0) { 3146 continue; 3147 } 3148 if (bootverbose) 3149 printf("ehci early: " 3150 "SMM active, request owner change\n"); 3151 3152 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1); 3153 3154 for (i = 0; (i < 100) && (bios_sem != 0); i++) { 3155 DELAY(1000); 3156 bios_sem = pci_read_config(self, eecp + 3157 EHCI_LEGSUP_BIOS_SEM, 1); 3158 } 3159 3160 if (bios_sem != 0) { 3161 if (bootverbose) 3162 printf("ehci early: " 3163 "SMM does not respond\n"); 3164 } 3165 /* Disable interrupts */ 3166 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION)); 3167 bus_write_4(res, offs + EHCI_USBINTR, 0); 3168 } 3169 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3170 } 3171 3172 /* Perform early XHCI takeover from SMM. */ 3173 static void 3174 xhci_early_takeover(device_t self) 3175 { 3176 struct resource *res; 3177 uint32_t cparams; 3178 uint32_t eec; 3179 uint8_t eecp; 3180 uint8_t bios_sem; 3181 uint8_t offs; 3182 int rid; 3183 int i; 3184 3185 rid = PCIR_BAR(0); 3186 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3187 if (res == NULL) 3188 return; 3189 3190 cparams = bus_read_4(res, XHCI_HCSPARAMS0); 3191 3192 eec = -1; 3193 3194 /* Synchronise with the BIOS if it owns the controller. */ 3195 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 3196 eecp += XHCI_XECP_NEXT(eec) << 2) { 3197 eec = bus_read_4(res, eecp); 3198 3199 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 3200 continue; 3201 3202 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM); 3203 if (bios_sem == 0) 3204 continue; 3205 3206 if (bootverbose) 3207 printf("xhci early: " 3208 "SMM active, request owner change\n"); 3209 3210 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1); 3211 3212 /* wait a maximum of 5 second */ 3213 3214 for (i = 0; (i < 5000) && (bios_sem != 0); i++) { 3215 DELAY(1000); 3216 bios_sem = bus_read_1(res, eecp + 3217 XHCI_XECP_BIOS_SEM); 3218 } 3219 3220 if (bios_sem != 0) { 3221 if (bootverbose) 3222 printf("xhci early: " 3223 "SMM does not respond\n"); 3224 } 3225 3226 /* Disable interrupts */ 3227 offs = bus_read_1(res, XHCI_CAPLENGTH); 3228 bus_write_4(res, offs + XHCI_USBCMD, 0); 3229 bus_read_4(res, offs + XHCI_USBSTS); 3230 } 3231 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3232 } 3233 3234 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 3235 static void 3236 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg, 3237 struct resource_list *rl) 3238 { 3239 struct resource *res; 3240 char *cp; 3241 u_long start, end, count; 3242 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus; 3243 3244 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3245 case PCIM_HDRTYPE_BRIDGE: 3246 sec_reg = PCIR_SECBUS_1; 3247 sub_reg = PCIR_SUBBUS_1; 3248 break; 3249 case PCIM_HDRTYPE_CARDBUS: 3250 sec_reg = PCIR_SECBUS_2; 3251 sub_reg = PCIR_SUBBUS_2; 3252 break; 3253 default: 3254 return; 3255 } 3256 3257 /* 3258 * If the existing bus range is valid, attempt to reserve it 3259 * from our parent. If this fails for any reason, clear the 3260 * secbus and subbus registers. 3261 * 3262 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus? 3263 * This would at least preserve the existing sec_bus if it is 3264 * valid. 3265 */ 3266 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1); 3267 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1); 3268 3269 /* Quirk handling. */ 3270 switch (pci_get_devid(dev)) { 3271 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 3272 sup_bus = pci_read_config(dev, 0x41, 1); 3273 if (sup_bus != 0xff) { 3274 sec_bus = sup_bus + 1; 3275 sub_bus = sup_bus + 1; 3276 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1); 3277 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3278 } 3279 break; 3280 3281 case 0x00dd10de: 3282 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 3283 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 3284 break; 3285 if (strncmp(cp, "Compal", 6) != 0) { 3286 freeenv(cp); 3287 break; 3288 } 3289 freeenv(cp); 3290 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 3291 break; 3292 if (strncmp(cp, "08A0", 4) != 0) { 3293 freeenv(cp); 3294 break; 3295 } 3296 freeenv(cp); 3297 if (sub_bus < 0xa) { 3298 sub_bus = 0xa; 3299 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3300 } 3301 break; 3302 } 3303 3304 if (bootverbose) 3305 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus); 3306 if (sec_bus > 0 && sub_bus >= sec_bus) { 3307 start = sec_bus; 3308 end = sub_bus; 3309 count = end - start + 1; 3310 3311 resource_list_add(rl, PCI_RES_BUS, 0, 0ul, ~0ul, count); 3312 3313 /* 3314 * If requested, clear secondary bus registers in 3315 * bridge devices to force a complete renumbering 3316 * rather than reserving the existing range. However, 3317 * preserve the existing size. 3318 */ 3319 if (pci_clear_buses) 3320 goto clear; 3321 3322 rid = 0; 3323 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid, 3324 start, end, count, 0); 3325 if (res != NULL) 3326 return; 3327 3328 if (bootverbose) 3329 device_printf(bus, 3330 "pci%d:%d:%d:%d secbus failed to allocate\n", 3331 pci_get_domain(dev), pci_get_bus(dev), 3332 pci_get_slot(dev), pci_get_function(dev)); 3333 } 3334 3335 clear: 3336 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1); 3337 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1); 3338 } 3339 3340 static struct resource * 3341 pci_alloc_secbus(device_t dev, device_t child, int *rid, u_long start, 3342 u_long end, u_long count, u_int flags) 3343 { 3344 struct pci_devinfo *dinfo; 3345 pcicfgregs *cfg; 3346 struct resource_list *rl; 3347 struct resource *res; 3348 int sec_reg, sub_reg; 3349 3350 dinfo = device_get_ivars(child); 3351 cfg = &dinfo->cfg; 3352 rl = &dinfo->resources; 3353 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3354 case PCIM_HDRTYPE_BRIDGE: 3355 sec_reg = PCIR_SECBUS_1; 3356 sub_reg = PCIR_SUBBUS_1; 3357 break; 3358 case PCIM_HDRTYPE_CARDBUS: 3359 sec_reg = PCIR_SECBUS_2; 3360 sub_reg = PCIR_SUBBUS_2; 3361 break; 3362 default: 3363 return (NULL); 3364 } 3365 3366 if (*rid != 0) 3367 return (NULL); 3368 3369 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL) 3370 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count); 3371 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) { 3372 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid, 3373 start, end, count, flags & ~RF_ACTIVE); 3374 if (res == NULL) { 3375 resource_list_delete(rl, PCI_RES_BUS, *rid); 3376 device_printf(child, "allocating %lu bus%s failed\n", 3377 count, count == 1 ? "" : "es"); 3378 return (NULL); 3379 } 3380 if (bootverbose) 3381 device_printf(child, 3382 "Lazy allocation of %lu bus%s at %lu\n", count, 3383 count == 1 ? "" : "es", rman_get_start(res)); 3384 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1); 3385 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1); 3386 } 3387 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start, 3388 end, count, flags)); 3389 } 3390 #endif 3391 3392 void 3393 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 3394 { 3395 struct pci_devinfo *dinfo; 3396 pcicfgregs *cfg; 3397 struct resource_list *rl; 3398 const struct pci_quirk *q; 3399 uint32_t devid; 3400 int i; 3401 3402 dinfo = device_get_ivars(dev); 3403 cfg = &dinfo->cfg; 3404 rl = &dinfo->resources; 3405 devid = (cfg->device << 16) | cfg->vendor; 3406 3407 /* ATA devices needs special map treatment */ 3408 if ((pci_get_class(dev) == PCIC_STORAGE) && 3409 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 3410 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 3411 (!pci_read_config(dev, PCIR_BAR(0), 4) && 3412 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 3413 pci_ata_maps(bus, dev, rl, force, prefetchmask); 3414 else 3415 for (i = 0; i < cfg->nummaps;) { 3416 /* 3417 * Skip quirked resources. 3418 */ 3419 for (q = &pci_quirks[0]; q->devid != 0; q++) 3420 if (q->devid == devid && 3421 q->type == PCI_QUIRK_UNMAP_REG && 3422 q->arg1 == PCIR_BAR(i)) 3423 break; 3424 if (q->devid != 0) { 3425 i++; 3426 continue; 3427 } 3428 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force, 3429 prefetchmask & (1 << i)); 3430 } 3431 3432 /* 3433 * Add additional, quirked resources. 3434 */ 3435 for (q = &pci_quirks[0]; q->devid != 0; q++) 3436 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) 3437 pci_add_map(bus, dev, q->arg1, rl, force, 0); 3438 3439 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 3440 #ifdef __PCI_REROUTE_INTERRUPT 3441 /* 3442 * Try to re-route interrupts. Sometimes the BIOS or 3443 * firmware may leave bogus values in these registers. 3444 * If the re-route fails, then just stick with what we 3445 * have. 3446 */ 3447 pci_assign_interrupt(bus, dev, 1); 3448 #else 3449 pci_assign_interrupt(bus, dev, 0); 3450 #endif 3451 } 3452 3453 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS && 3454 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) { 3455 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI) 3456 xhci_early_takeover(dev); 3457 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI) 3458 ehci_early_takeover(dev); 3459 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI) 3460 ohci_early_takeover(dev); 3461 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI) 3462 uhci_early_takeover(dev); 3463 } 3464 3465 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 3466 /* 3467 * Reserve resources for secondary bus ranges behind bridge 3468 * devices. 3469 */ 3470 pci_reserve_secbus(bus, dev, cfg, rl); 3471 #endif 3472 } 3473 3474 static struct pci_devinfo * 3475 pci_identify_function(device_t pcib, device_t dev, int domain, int busno, 3476 int slot, int func, size_t dinfo_size) 3477 { 3478 struct pci_devinfo *dinfo; 3479 3480 dinfo = pci_read_device(pcib, domain, busno, slot, func, dinfo_size); 3481 if (dinfo != NULL) 3482 pci_add_child(dev, dinfo); 3483 3484 return (dinfo); 3485 } 3486 3487 void 3488 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size) 3489 { 3490 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 3491 device_t pcib = device_get_parent(dev); 3492 struct pci_devinfo *dinfo; 3493 int maxslots; 3494 int s, f, pcifunchigh; 3495 uint8_t hdrtype; 3496 int first_func; 3497 3498 /* 3499 * Try to detect a device at slot 0, function 0. If it exists, try to 3500 * enable ARI. We must enable ARI before detecting the rest of the 3501 * functions on this bus as ARI changes the set of slots and functions 3502 * that are legal on this bus. 3503 */ 3504 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0, 3505 dinfo_size); 3506 if (dinfo != NULL && pci_enable_ari) 3507 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); 3508 3509 /* 3510 * Start looking for new devices on slot 0 at function 1 because we 3511 * just identified the device at slot 0, function 0. 3512 */ 3513 first_func = 1; 3514 3515 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 3516 ("dinfo_size too small")); 3517 maxslots = PCIB_MAXSLOTS(pcib); 3518 for (s = 0; s <= maxslots; s++, first_func = 0) { 3519 pcifunchigh = 0; 3520 f = 0; 3521 DELAY(1); 3522 hdrtype = REG(PCIR_HDRTYPE, 1); 3523 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 3524 continue; 3525 if (hdrtype & PCIM_MFDEV) 3526 pcifunchigh = PCIB_MAXFUNCS(pcib); 3527 for (f = first_func; f <= pcifunchigh; f++) 3528 pci_identify_function(pcib, dev, domain, busno, s, f, 3529 dinfo_size); 3530 } 3531 #undef REG 3532 } 3533 3534 void 3535 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 3536 { 3537 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 3538 device_set_ivars(dinfo->cfg.dev, dinfo); 3539 resource_list_init(&dinfo->resources); 3540 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 3541 pci_cfg_restore(dinfo->cfg.dev, dinfo); 3542 pci_print_verbose(dinfo); 3543 pci_add_resources(bus, dinfo->cfg.dev, 0, 0); 3544 pci_child_added(dinfo->cfg.dev); 3545 } 3546 3547 void 3548 pci_child_added_method(device_t dev, device_t child) 3549 { 3550 3551 } 3552 3553 static int 3554 pci_probe(device_t dev) 3555 { 3556 3557 device_set_desc(dev, "PCI bus"); 3558 3559 /* Allow other subclasses to override this driver. */ 3560 return (BUS_PROBE_GENERIC); 3561 } 3562 3563 int 3564 pci_attach_common(device_t dev) 3565 { 3566 struct pci_softc *sc; 3567 int busno, domain; 3568 #ifdef PCI_DMA_BOUNDARY 3569 int error, tag_valid; 3570 #endif 3571 #ifdef PCI_RES_BUS 3572 int rid; 3573 #endif 3574 3575 sc = device_get_softc(dev); 3576 domain = pcib_get_domain(dev); 3577 busno = pcib_get_bus(dev); 3578 #ifdef PCI_RES_BUS 3579 rid = 0; 3580 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, 3581 1, 0); 3582 if (sc->sc_bus == NULL) { 3583 device_printf(dev, "failed to allocate bus number\n"); 3584 return (ENXIO); 3585 } 3586 #endif 3587 if (bootverbose) 3588 device_printf(dev, "domain=%d, physical bus=%d\n", 3589 domain, busno); 3590 #ifdef PCI_DMA_BOUNDARY 3591 tag_valid = 0; 3592 if (device_get_devclass(device_get_parent(device_get_parent(dev))) != 3593 devclass_find("pci")) { 3594 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 3595 PCI_DMA_BOUNDARY, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3596 NULL, NULL, BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, 3597 BUS_SPACE_MAXSIZE, 0, NULL, NULL, &sc->sc_dma_tag); 3598 if (error) 3599 device_printf(dev, "Failed to create DMA tag: %d\n", 3600 error); 3601 else 3602 tag_valid = 1; 3603 } 3604 if (!tag_valid) 3605 #endif 3606 sc->sc_dma_tag = bus_get_dma_tag(dev); 3607 return (0); 3608 } 3609 3610 static int 3611 pci_attach(device_t dev) 3612 { 3613 int busno, domain, error; 3614 3615 error = pci_attach_common(dev); 3616 if (error) 3617 return (error); 3618 3619 /* 3620 * Since there can be multiple independantly numbered PCI 3621 * busses on systems with multiple PCI domains, we can't use 3622 * the unit number to decide which bus we are probing. We ask 3623 * the parent pcib what our domain and bus numbers are. 3624 */ 3625 domain = pcib_get_domain(dev); 3626 busno = pcib_get_bus(dev); 3627 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo)); 3628 return (bus_generic_attach(dev)); 3629 } 3630 3631 #ifdef PCI_RES_BUS 3632 static int 3633 pci_detach(device_t dev) 3634 { 3635 struct pci_softc *sc; 3636 int error; 3637 3638 error = bus_generic_detach(dev); 3639 if (error) 3640 return (error); 3641 sc = device_get_softc(dev); 3642 return (bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus)); 3643 } 3644 #endif 3645 3646 static void 3647 pci_set_power_child(device_t dev, device_t child, int state) 3648 { 3649 struct pci_devinfo *dinfo; 3650 device_t pcib; 3651 int dstate; 3652 3653 /* 3654 * Set the device to the given state. If the firmware suggests 3655 * a different power state, use it instead. If power management 3656 * is not present, the firmware is responsible for managing 3657 * device power. Skip children who aren't attached since they 3658 * are handled separately. 3659 */ 3660 pcib = device_get_parent(dev); 3661 dinfo = device_get_ivars(child); 3662 dstate = state; 3663 if (device_is_attached(child) && 3664 PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0) 3665 pci_set_powerstate(child, dstate); 3666 } 3667 3668 int 3669 pci_suspend_child(device_t dev, device_t child) 3670 { 3671 struct pci_devinfo *dinfo; 3672 int error; 3673 3674 dinfo = device_get_ivars(child); 3675 3676 /* 3677 * Save the PCI configuration space for the child and set the 3678 * device in the appropriate power state for this sleep state. 3679 */ 3680 pci_cfg_save(child, dinfo, 0); 3681 3682 /* Suspend devices before potentially powering them down. */ 3683 error = bus_generic_suspend_child(dev, child); 3684 3685 if (error) 3686 return (error); 3687 3688 if (pci_do_power_suspend) 3689 pci_set_power_child(dev, child, PCI_POWERSTATE_D3); 3690 3691 return (0); 3692 } 3693 3694 int 3695 pci_resume_child(device_t dev, device_t child) 3696 { 3697 struct pci_devinfo *dinfo; 3698 3699 if (pci_do_power_resume) 3700 pci_set_power_child(dev, child, PCI_POWERSTATE_D0); 3701 3702 dinfo = device_get_ivars(child); 3703 pci_cfg_restore(child, dinfo); 3704 if (!device_is_attached(child)) 3705 pci_cfg_save(child, dinfo, 1); 3706 3707 bus_generic_resume_child(dev, child); 3708 3709 return (0); 3710 } 3711 3712 int 3713 pci_resume(device_t dev) 3714 { 3715 device_t child, *devlist; 3716 int error, i, numdevs; 3717 3718 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 3719 return (error); 3720 3721 /* 3722 * Resume critical devices first, then everything else later. 3723 */ 3724 for (i = 0; i < numdevs; i++) { 3725 child = devlist[i]; 3726 switch (pci_get_class(child)) { 3727 case PCIC_DISPLAY: 3728 case PCIC_MEMORY: 3729 case PCIC_BRIDGE: 3730 case PCIC_BASEPERIPH: 3731 BUS_RESUME_CHILD(dev, child); 3732 break; 3733 } 3734 } 3735 for (i = 0; i < numdevs; i++) { 3736 child = devlist[i]; 3737 switch (pci_get_class(child)) { 3738 case PCIC_DISPLAY: 3739 case PCIC_MEMORY: 3740 case PCIC_BRIDGE: 3741 case PCIC_BASEPERIPH: 3742 break; 3743 default: 3744 BUS_RESUME_CHILD(dev, child); 3745 } 3746 } 3747 free(devlist, M_TEMP); 3748 return (0); 3749 } 3750 3751 static void 3752 pci_load_vendor_data(void) 3753 { 3754 caddr_t data; 3755 void *ptr; 3756 size_t sz; 3757 3758 data = preload_search_by_type("pci_vendor_data"); 3759 if (data != NULL) { 3760 ptr = preload_fetch_addr(data); 3761 sz = preload_fetch_size(data); 3762 if (ptr != NULL && sz != 0) { 3763 pci_vendordata = ptr; 3764 pci_vendordata_size = sz; 3765 /* terminate the database */ 3766 pci_vendordata[pci_vendordata_size] = '\n'; 3767 } 3768 } 3769 } 3770 3771 void 3772 pci_driver_added(device_t dev, driver_t *driver) 3773 { 3774 int numdevs; 3775 device_t *devlist; 3776 device_t child; 3777 struct pci_devinfo *dinfo; 3778 int i; 3779 3780 if (bootverbose) 3781 device_printf(dev, "driver added\n"); 3782 DEVICE_IDENTIFY(driver, dev); 3783 if (device_get_children(dev, &devlist, &numdevs) != 0) 3784 return; 3785 for (i = 0; i < numdevs; i++) { 3786 child = devlist[i]; 3787 if (device_get_state(child) != DS_NOTPRESENT) 3788 continue; 3789 dinfo = device_get_ivars(child); 3790 pci_print_verbose(dinfo); 3791 if (bootverbose) 3792 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); 3793 pci_cfg_restore(child, dinfo); 3794 if (device_probe_and_attach(child) != 0) 3795 pci_child_detached(dev, child); 3796 } 3797 free(devlist, M_TEMP); 3798 } 3799 3800 int 3801 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, 3802 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep) 3803 { 3804 struct pci_devinfo *dinfo; 3805 struct msix_table_entry *mte; 3806 struct msix_vector *mv; 3807 uint64_t addr; 3808 uint32_t data; 3809 void *cookie; 3810 int error, rid; 3811 3812 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr, 3813 arg, &cookie); 3814 if (error) 3815 return (error); 3816 3817 /* If this is not a direct child, just bail out. */ 3818 if (device_get_parent(child) != dev) { 3819 *cookiep = cookie; 3820 return(0); 3821 } 3822 3823 rid = rman_get_rid(irq); 3824 if (rid == 0) { 3825 /* Make sure that INTx is enabled */ 3826 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 3827 } else { 3828 /* 3829 * Check to see if the interrupt is MSI or MSI-X. 3830 * Ask our parent to map the MSI and give 3831 * us the address and data register values. 3832 * If we fail for some reason, teardown the 3833 * interrupt handler. 3834 */ 3835 dinfo = device_get_ivars(child); 3836 if (dinfo->cfg.msi.msi_alloc > 0) { 3837 if (dinfo->cfg.msi.msi_addr == 0) { 3838 KASSERT(dinfo->cfg.msi.msi_handlers == 0, 3839 ("MSI has handlers, but vectors not mapped")); 3840 error = PCIB_MAP_MSI(device_get_parent(dev), 3841 child, rman_get_start(irq), &addr, &data); 3842 if (error) 3843 goto bad; 3844 dinfo->cfg.msi.msi_addr = addr; 3845 dinfo->cfg.msi.msi_data = data; 3846 } 3847 if (dinfo->cfg.msi.msi_handlers == 0) 3848 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, 3849 dinfo->cfg.msi.msi_data); 3850 dinfo->cfg.msi.msi_handlers++; 3851 } else { 3852 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 3853 ("No MSI or MSI-X interrupts allocated")); 3854 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 3855 ("MSI-X index too high")); 3856 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 3857 KASSERT(mte->mte_vector != 0, ("no message vector")); 3858 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; 3859 KASSERT(mv->mv_irq == rman_get_start(irq), 3860 ("IRQ mismatch")); 3861 if (mv->mv_address == 0) { 3862 KASSERT(mte->mte_handlers == 0, 3863 ("MSI-X table entry has handlers, but vector not mapped")); 3864 error = PCIB_MAP_MSI(device_get_parent(dev), 3865 child, rman_get_start(irq), &addr, &data); 3866 if (error) 3867 goto bad; 3868 mv->mv_address = addr; 3869 mv->mv_data = data; 3870 } 3871 if (mte->mte_handlers == 0) { 3872 pci_enable_msix(child, rid - 1, mv->mv_address, 3873 mv->mv_data); 3874 pci_unmask_msix(child, rid - 1); 3875 } 3876 mte->mte_handlers++; 3877 } 3878 3879 /* 3880 * Make sure that INTx is disabled if we are using MSI/MSI-X, 3881 * unless the device is affected by PCI_QUIRK_MSI_INTX_BUG, 3882 * in which case we "enable" INTx so MSI/MSI-X actually works. 3883 */ 3884 if (!pci_has_quirk(pci_get_devid(child), 3885 PCI_QUIRK_MSI_INTX_BUG)) 3886 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 3887 else 3888 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 3889 bad: 3890 if (error) { 3891 (void)bus_generic_teardown_intr(dev, child, irq, 3892 cookie); 3893 return (error); 3894 } 3895 } 3896 *cookiep = cookie; 3897 return (0); 3898 } 3899 3900 int 3901 pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 3902 void *cookie) 3903 { 3904 struct msix_table_entry *mte; 3905 struct resource_list_entry *rle; 3906 struct pci_devinfo *dinfo; 3907 int error, rid; 3908 3909 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE)) 3910 return (EINVAL); 3911 3912 /* If this isn't a direct child, just bail out */ 3913 if (device_get_parent(child) != dev) 3914 return(bus_generic_teardown_intr(dev, child, irq, cookie)); 3915 3916 rid = rman_get_rid(irq); 3917 if (rid == 0) { 3918 /* Mask INTx */ 3919 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 3920 } else { 3921 /* 3922 * Check to see if the interrupt is MSI or MSI-X. If so, 3923 * decrement the appropriate handlers count and mask the 3924 * MSI-X message, or disable MSI messages if the count 3925 * drops to 0. 3926 */ 3927 dinfo = device_get_ivars(child); 3928 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); 3929 if (rle->res != irq) 3930 return (EINVAL); 3931 if (dinfo->cfg.msi.msi_alloc > 0) { 3932 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, 3933 ("MSI-X index too high")); 3934 if (dinfo->cfg.msi.msi_handlers == 0) 3935 return (EINVAL); 3936 dinfo->cfg.msi.msi_handlers--; 3937 if (dinfo->cfg.msi.msi_handlers == 0) 3938 pci_disable_msi(child); 3939 } else { 3940 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 3941 ("No MSI or MSI-X interrupts allocated")); 3942 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 3943 ("MSI-X index too high")); 3944 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 3945 if (mte->mte_handlers == 0) 3946 return (EINVAL); 3947 mte->mte_handlers--; 3948 if (mte->mte_handlers == 0) 3949 pci_mask_msix(child, rid - 1); 3950 } 3951 } 3952 error = bus_generic_teardown_intr(dev, child, irq, cookie); 3953 if (rid > 0) 3954 KASSERT(error == 0, 3955 ("%s: generic teardown failed for MSI/MSI-X", __func__)); 3956 return (error); 3957 } 3958 3959 int 3960 pci_print_child(device_t dev, device_t child) 3961 { 3962 struct pci_devinfo *dinfo; 3963 struct resource_list *rl; 3964 int retval = 0; 3965 3966 dinfo = device_get_ivars(child); 3967 rl = &dinfo->resources; 3968 3969 retval += bus_print_child_header(dev, child); 3970 3971 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 3972 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 3973 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 3974 if (device_get_flags(dev)) 3975 retval += printf(" flags %#x", device_get_flags(dev)); 3976 3977 retval += printf(" at device %d.%d", pci_get_slot(child), 3978 pci_get_function(child)); 3979 3980 retval += bus_print_child_domain(dev, child); 3981 retval += bus_print_child_footer(dev, child); 3982 3983 return (retval); 3984 } 3985 3986 static const struct 3987 { 3988 int class; 3989 int subclass; 3990 int report; /* 0 = bootverbose, 1 = always */ 3991 const char *desc; 3992 } pci_nomatch_tab[] = { 3993 {PCIC_OLD, -1, 1, "old"}, 3994 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"}, 3995 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"}, 3996 {PCIC_STORAGE, -1, 1, "mass storage"}, 3997 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"}, 3998 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"}, 3999 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"}, 4000 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"}, 4001 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"}, 4002 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"}, 4003 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"}, 4004 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"}, 4005 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"}, 4006 {PCIC_NETWORK, -1, 1, "network"}, 4007 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"}, 4008 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"}, 4009 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"}, 4010 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"}, 4011 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"}, 4012 {PCIC_DISPLAY, -1, 1, "display"}, 4013 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"}, 4014 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"}, 4015 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"}, 4016 {PCIC_MULTIMEDIA, -1, 1, "multimedia"}, 4017 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"}, 4018 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"}, 4019 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"}, 4020 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"}, 4021 {PCIC_MEMORY, -1, 1, "memory"}, 4022 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"}, 4023 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"}, 4024 {PCIC_BRIDGE, -1, 1, "bridge"}, 4025 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"}, 4026 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"}, 4027 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"}, 4028 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"}, 4029 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"}, 4030 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"}, 4031 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"}, 4032 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"}, 4033 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"}, 4034 {PCIC_SIMPLECOMM, -1, 1, "simple comms"}, 4035 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */ 4036 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"}, 4037 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"}, 4038 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"}, 4039 {PCIC_BASEPERIPH, -1, 0, "base peripheral"}, 4040 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"}, 4041 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"}, 4042 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"}, 4043 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"}, 4044 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"}, 4045 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"}, 4046 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"}, 4047 {PCIC_INPUTDEV, -1, 1, "input device"}, 4048 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"}, 4049 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"}, 4050 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"}, 4051 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"}, 4052 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"}, 4053 {PCIC_DOCKING, -1, 1, "docking station"}, 4054 {PCIC_PROCESSOR, -1, 1, "processor"}, 4055 {PCIC_SERIALBUS, -1, 1, "serial bus"}, 4056 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"}, 4057 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"}, 4058 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"}, 4059 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"}, 4060 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"}, 4061 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"}, 4062 {PCIC_WIRELESS, -1, 1, "wireless controller"}, 4063 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"}, 4064 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"}, 4065 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"}, 4066 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"}, 4067 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"}, 4068 {PCIC_SATCOM, -1, 1, "satellite communication"}, 4069 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"}, 4070 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"}, 4071 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"}, 4072 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"}, 4073 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"}, 4074 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"}, 4075 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"}, 4076 {PCIC_DASP, -1, 0, "dasp"}, 4077 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"}, 4078 {0, 0, 0, NULL} 4079 }; 4080 4081 void 4082 pci_probe_nomatch(device_t dev, device_t child) 4083 { 4084 int i, report; 4085 const char *cp, *scp; 4086 char *device; 4087 4088 /* 4089 * Look for a listing for this device in a loaded device database. 4090 */ 4091 report = 1; 4092 if ((device = pci_describe_device(child)) != NULL) { 4093 device_printf(dev, "<%s>", device); 4094 free(device, M_DEVBUF); 4095 } else { 4096 /* 4097 * Scan the class/subclass descriptions for a general 4098 * description. 4099 */ 4100 cp = "unknown"; 4101 scp = NULL; 4102 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 4103 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 4104 if (pci_nomatch_tab[i].subclass == -1) { 4105 cp = pci_nomatch_tab[i].desc; 4106 report = pci_nomatch_tab[i].report; 4107 } else if (pci_nomatch_tab[i].subclass == 4108 pci_get_subclass(child)) { 4109 scp = pci_nomatch_tab[i].desc; 4110 report = pci_nomatch_tab[i].report; 4111 } 4112 } 4113 } 4114 if (report || bootverbose) { 4115 device_printf(dev, "<%s%s%s>", 4116 cp ? cp : "", 4117 ((cp != NULL) && (scp != NULL)) ? ", " : "", 4118 scp ? scp : ""); 4119 } 4120 } 4121 if (report || bootverbose) { 4122 printf(" at device %d.%d (no driver attached)\n", 4123 pci_get_slot(child), pci_get_function(child)); 4124 } 4125 pci_cfg_save(child, device_get_ivars(child), 1); 4126 } 4127 4128 void 4129 pci_child_detached(device_t dev, device_t child) 4130 { 4131 struct pci_devinfo *dinfo; 4132 struct resource_list *rl; 4133 4134 dinfo = device_get_ivars(child); 4135 rl = &dinfo->resources; 4136 4137 /* 4138 * Have to deallocate IRQs before releasing any MSI messages and 4139 * have to release MSI messages before deallocating any memory 4140 * BARs. 4141 */ 4142 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0) 4143 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); 4144 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { 4145 pci_printf(&dinfo->cfg, "Device leaked MSI vectors\n"); 4146 (void)pci_release_msi(child); 4147 } 4148 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0) 4149 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); 4150 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0) 4151 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); 4152 #ifdef PCI_RES_BUS 4153 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0) 4154 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); 4155 #endif 4156 4157 pci_cfg_save(child, dinfo, 1); 4158 } 4159 4160 /* 4161 * Parse the PCI device database, if loaded, and return a pointer to a 4162 * description of the device. 4163 * 4164 * The database is flat text formatted as follows: 4165 * 4166 * Any line not in a valid format is ignored. 4167 * Lines are terminated with newline '\n' characters. 4168 * 4169 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 4170 * the vendor name. 4171 * 4172 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 4173 * - devices cannot be listed without a corresponding VENDOR line. 4174 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 4175 * another TAB, then the device name. 4176 */ 4177 4178 /* 4179 * Assuming (ptr) points to the beginning of a line in the database, 4180 * return the vendor or device and description of the next entry. 4181 * The value of (vendor) or (device) inappropriate for the entry type 4182 * is set to -1. Returns nonzero at the end of the database. 4183 * 4184 * Note that this is slightly unrobust in the face of corrupt data; 4185 * we attempt to safeguard against this by spamming the end of the 4186 * database with a newline when we initialise. 4187 */ 4188 static int 4189 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 4190 { 4191 char *cp = *ptr; 4192 int left; 4193 4194 *device = -1; 4195 *vendor = -1; 4196 **desc = '\0'; 4197 for (;;) { 4198 left = pci_vendordata_size - (cp - pci_vendordata); 4199 if (left <= 0) { 4200 *ptr = cp; 4201 return(1); 4202 } 4203 4204 /* vendor entry? */ 4205 if (*cp != '\t' && 4206 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 4207 break; 4208 /* device entry? */ 4209 if (*cp == '\t' && 4210 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 4211 break; 4212 4213 /* skip to next line */ 4214 while (*cp != '\n' && left > 0) { 4215 cp++; 4216 left--; 4217 } 4218 if (*cp == '\n') { 4219 cp++; 4220 left--; 4221 } 4222 } 4223 /* skip to next line */ 4224 while (*cp != '\n' && left > 0) { 4225 cp++; 4226 left--; 4227 } 4228 if (*cp == '\n' && left > 0) 4229 cp++; 4230 *ptr = cp; 4231 return(0); 4232 } 4233 4234 static char * 4235 pci_describe_device(device_t dev) 4236 { 4237 int vendor, device; 4238 char *desc, *vp, *dp, *line; 4239 4240 desc = vp = dp = NULL; 4241 4242 /* 4243 * If we have no vendor data, we can't do anything. 4244 */ 4245 if (pci_vendordata == NULL) 4246 goto out; 4247 4248 /* 4249 * Scan the vendor data looking for this device 4250 */ 4251 line = pci_vendordata; 4252 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 4253 goto out; 4254 for (;;) { 4255 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 4256 goto out; 4257 if (vendor == pci_get_vendor(dev)) 4258 break; 4259 } 4260 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 4261 goto out; 4262 for (;;) { 4263 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 4264 *dp = 0; 4265 break; 4266 } 4267 if (vendor != -1) { 4268 *dp = 0; 4269 break; 4270 } 4271 if (device == pci_get_device(dev)) 4272 break; 4273 } 4274 if (dp[0] == '\0') 4275 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 4276 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 4277 NULL) 4278 sprintf(desc, "%s, %s", vp, dp); 4279 out: 4280 if (vp != NULL) 4281 free(vp, M_DEVBUF); 4282 if (dp != NULL) 4283 free(dp, M_DEVBUF); 4284 return(desc); 4285 } 4286 4287 int 4288 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 4289 { 4290 struct pci_devinfo *dinfo; 4291 pcicfgregs *cfg; 4292 4293 dinfo = device_get_ivars(child); 4294 cfg = &dinfo->cfg; 4295 4296 switch (which) { 4297 case PCI_IVAR_ETHADDR: 4298 /* 4299 * The generic accessor doesn't deal with failure, so 4300 * we set the return value, then return an error. 4301 */ 4302 *((uint8_t **) result) = NULL; 4303 return (EINVAL); 4304 case PCI_IVAR_SUBVENDOR: 4305 *result = cfg->subvendor; 4306 break; 4307 case PCI_IVAR_SUBDEVICE: 4308 *result = cfg->subdevice; 4309 break; 4310 case PCI_IVAR_VENDOR: 4311 *result = cfg->vendor; 4312 break; 4313 case PCI_IVAR_DEVICE: 4314 *result = cfg->device; 4315 break; 4316 case PCI_IVAR_DEVID: 4317 *result = (cfg->device << 16) | cfg->vendor; 4318 break; 4319 case PCI_IVAR_CLASS: 4320 *result = cfg->baseclass; 4321 break; 4322 case PCI_IVAR_SUBCLASS: 4323 *result = cfg->subclass; 4324 break; 4325 case PCI_IVAR_PROGIF: 4326 *result = cfg->progif; 4327 break; 4328 case PCI_IVAR_REVID: 4329 *result = cfg->revid; 4330 break; 4331 case PCI_IVAR_INTPIN: 4332 *result = cfg->intpin; 4333 break; 4334 case PCI_IVAR_IRQ: 4335 *result = cfg->intline; 4336 break; 4337 case PCI_IVAR_DOMAIN: 4338 *result = cfg->domain; 4339 break; 4340 case PCI_IVAR_BUS: 4341 *result = cfg->bus; 4342 break; 4343 case PCI_IVAR_SLOT: 4344 *result = cfg->slot; 4345 break; 4346 case PCI_IVAR_FUNCTION: 4347 *result = cfg->func; 4348 break; 4349 case PCI_IVAR_CMDREG: 4350 *result = cfg->cmdreg; 4351 break; 4352 case PCI_IVAR_CACHELNSZ: 4353 *result = cfg->cachelnsz; 4354 break; 4355 case PCI_IVAR_MINGNT: 4356 *result = cfg->mingnt; 4357 break; 4358 case PCI_IVAR_MAXLAT: 4359 *result = cfg->maxlat; 4360 break; 4361 case PCI_IVAR_LATTIMER: 4362 *result = cfg->lattimer; 4363 break; 4364 default: 4365 return (ENOENT); 4366 } 4367 return (0); 4368 } 4369 4370 int 4371 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 4372 { 4373 struct pci_devinfo *dinfo; 4374 4375 dinfo = device_get_ivars(child); 4376 4377 switch (which) { 4378 case PCI_IVAR_INTPIN: 4379 dinfo->cfg.intpin = value; 4380 return (0); 4381 case PCI_IVAR_ETHADDR: 4382 case PCI_IVAR_SUBVENDOR: 4383 case PCI_IVAR_SUBDEVICE: 4384 case PCI_IVAR_VENDOR: 4385 case PCI_IVAR_DEVICE: 4386 case PCI_IVAR_DEVID: 4387 case PCI_IVAR_CLASS: 4388 case PCI_IVAR_SUBCLASS: 4389 case PCI_IVAR_PROGIF: 4390 case PCI_IVAR_REVID: 4391 case PCI_IVAR_IRQ: 4392 case PCI_IVAR_DOMAIN: 4393 case PCI_IVAR_BUS: 4394 case PCI_IVAR_SLOT: 4395 case PCI_IVAR_FUNCTION: 4396 return (EINVAL); /* disallow for now */ 4397 4398 default: 4399 return (ENOENT); 4400 } 4401 } 4402 4403 #include "opt_ddb.h" 4404 #ifdef DDB 4405 #include <ddb/ddb.h> 4406 #include <sys/cons.h> 4407 4408 /* 4409 * List resources based on pci map registers, used for within ddb 4410 */ 4411 4412 DB_SHOW_COMMAND(pciregs, db_pci_dump) 4413 { 4414 struct pci_devinfo *dinfo; 4415 struct devlist *devlist_head; 4416 struct pci_conf *p; 4417 const char *name; 4418 int i, error, none_count; 4419 4420 none_count = 0; 4421 /* get the head of the device queue */ 4422 devlist_head = &pci_devq; 4423 4424 /* 4425 * Go through the list of devices and print out devices 4426 */ 4427 for (error = 0, i = 0, 4428 dinfo = STAILQ_FIRST(devlist_head); 4429 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 4430 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 4431 4432 /* Populate pd_name and pd_unit */ 4433 name = NULL; 4434 if (dinfo->cfg.dev) 4435 name = device_get_name(dinfo->cfg.dev); 4436 4437 p = &dinfo->conf; 4438 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x " 4439 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 4440 (name && *name) ? name : "none", 4441 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 4442 none_count++, 4443 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, 4444 p->pc_sel.pc_func, (p->pc_class << 16) | 4445 (p->pc_subclass << 8) | p->pc_progif, 4446 (p->pc_subdevice << 16) | p->pc_subvendor, 4447 (p->pc_device << 16) | p->pc_vendor, 4448 p->pc_revid, p->pc_hdr); 4449 } 4450 } 4451 #endif /* DDB */ 4452 4453 static struct resource * 4454 pci_reserve_map(device_t dev, device_t child, int type, int *rid, 4455 u_long start, u_long end, u_long count, u_int flags) 4456 { 4457 struct pci_devinfo *dinfo = device_get_ivars(child); 4458 struct resource_list *rl = &dinfo->resources; 4459 struct resource *res; 4460 struct pci_map *pm; 4461 pci_addr_t map, testval; 4462 int mapsize; 4463 4464 res = NULL; 4465 pm = pci_find_bar(child, *rid); 4466 if (pm != NULL) { 4467 /* This is a BAR that we failed to allocate earlier. */ 4468 mapsize = pm->pm_size; 4469 map = pm->pm_value; 4470 } else { 4471 /* 4472 * Weed out the bogons, and figure out how large the 4473 * BAR/map is. BARs that read back 0 here are bogus 4474 * and unimplemented. Note: atapci in legacy mode are 4475 * special and handled elsewhere in the code. If you 4476 * have a atapci device in legacy mode and it fails 4477 * here, that other code is broken. 4478 */ 4479 pci_read_bar(child, *rid, &map, &testval); 4480 4481 /* 4482 * Determine the size of the BAR and ignore BARs with a size 4483 * of 0. Device ROM BARs use a different mask value. 4484 */ 4485 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) 4486 mapsize = pci_romsize(testval); 4487 else 4488 mapsize = pci_mapsize(testval); 4489 if (mapsize == 0) 4490 goto out; 4491 pm = pci_add_bar(child, *rid, map, mapsize); 4492 } 4493 4494 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { 4495 if (type != SYS_RES_MEMORY) { 4496 if (bootverbose) 4497 device_printf(dev, 4498 "child %s requested type %d for rid %#x," 4499 " but the BAR says it is an memio\n", 4500 device_get_nameunit(child), type, *rid); 4501 goto out; 4502 } 4503 } else { 4504 if (type != SYS_RES_IOPORT) { 4505 if (bootverbose) 4506 device_printf(dev, 4507 "child %s requested type %d for rid %#x," 4508 " but the BAR says it is an ioport\n", 4509 device_get_nameunit(child), type, *rid); 4510 goto out; 4511 } 4512 } 4513 4514 /* 4515 * For real BARs, we need to override the size that 4516 * the driver requests, because that's what the BAR 4517 * actually uses and we would otherwise have a 4518 * situation where we might allocate the excess to 4519 * another driver, which won't work. 4520 */ 4521 count = (pci_addr_t)1 << mapsize; 4522 if (RF_ALIGNMENT(flags) < mapsize) 4523 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 4524 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH)) 4525 flags |= RF_PREFETCHABLE; 4526 4527 /* 4528 * Allocate enough resource, and then write back the 4529 * appropriate BAR for that resource. 4530 */ 4531 resource_list_add(rl, type, *rid, start, end, count); 4532 res = resource_list_reserve(rl, dev, child, type, rid, start, end, 4533 count, flags & ~RF_ACTIVE); 4534 if (res == NULL) { 4535 resource_list_delete(rl, type, *rid); 4536 device_printf(child, 4537 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n", 4538 count, *rid, type, start, end); 4539 goto out; 4540 } 4541 if (bootverbose) 4542 device_printf(child, 4543 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 4544 count, *rid, type, rman_get_start(res)); 4545 map = rman_get_start(res); 4546 pci_write_bar(child, pm, map); 4547 out: 4548 return (res); 4549 } 4550 4551 struct resource * 4552 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 4553 u_long start, u_long end, u_long count, u_int flags) 4554 { 4555 struct pci_devinfo *dinfo; 4556 struct resource_list *rl; 4557 struct resource_list_entry *rle; 4558 struct resource *res; 4559 pcicfgregs *cfg; 4560 4561 if (device_get_parent(child) != dev) 4562 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 4563 type, rid, start, end, count, flags)); 4564 4565 /* 4566 * Perform lazy resource allocation 4567 */ 4568 dinfo = device_get_ivars(child); 4569 rl = &dinfo->resources; 4570 cfg = &dinfo->cfg; 4571 switch (type) { 4572 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 4573 case PCI_RES_BUS: 4574 return (pci_alloc_secbus(dev, child, rid, start, end, count, 4575 flags)); 4576 #endif 4577 case SYS_RES_IRQ: 4578 /* 4579 * Can't alloc legacy interrupt once MSI messages have 4580 * been allocated. 4581 */ 4582 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 4583 cfg->msix.msix_alloc > 0)) 4584 return (NULL); 4585 4586 /* 4587 * If the child device doesn't have an interrupt 4588 * routed and is deserving of an interrupt, try to 4589 * assign it one. 4590 */ 4591 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 4592 (cfg->intpin != 0)) 4593 pci_assign_interrupt(dev, child, 0); 4594 break; 4595 case SYS_RES_IOPORT: 4596 case SYS_RES_MEMORY: 4597 #ifdef NEW_PCIB 4598 /* 4599 * PCI-PCI bridge I/O window resources are not BARs. 4600 * For those allocations just pass the request up the 4601 * tree. 4602 */ 4603 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { 4604 switch (*rid) { 4605 case PCIR_IOBASEL_1: 4606 case PCIR_MEMBASE_1: 4607 case PCIR_PMBASEL_1: 4608 /* 4609 * XXX: Should we bother creating a resource 4610 * list entry? 4611 */ 4612 return (bus_generic_alloc_resource(dev, child, 4613 type, rid, start, end, count, flags)); 4614 } 4615 } 4616 #endif 4617 /* Reserve resources for this BAR if needed. */ 4618 rle = resource_list_find(rl, type, *rid); 4619 if (rle == NULL) { 4620 res = pci_reserve_map(dev, child, type, rid, start, end, 4621 count, flags); 4622 if (res == NULL) 4623 return (NULL); 4624 } 4625 } 4626 return (resource_list_alloc(rl, dev, child, type, rid, 4627 start, end, count, flags)); 4628 } 4629 4630 int 4631 pci_release_resource(device_t dev, device_t child, int type, int rid, 4632 struct resource *r) 4633 { 4634 struct pci_devinfo *dinfo; 4635 struct resource_list *rl; 4636 pcicfgregs *cfg; 4637 4638 if (device_get_parent(child) != dev) 4639 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 4640 type, rid, r)); 4641 4642 dinfo = device_get_ivars(child); 4643 cfg = &dinfo->cfg; 4644 #ifdef NEW_PCIB 4645 /* 4646 * PCI-PCI bridge I/O window resources are not BARs. For 4647 * those allocations just pass the request up the tree. 4648 */ 4649 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && 4650 (type == SYS_RES_IOPORT || type == SYS_RES_MEMORY)) { 4651 switch (rid) { 4652 case PCIR_IOBASEL_1: 4653 case PCIR_MEMBASE_1: 4654 case PCIR_PMBASEL_1: 4655 return (bus_generic_release_resource(dev, child, type, 4656 rid, r)); 4657 } 4658 } 4659 #endif 4660 4661 rl = &dinfo->resources; 4662 return (resource_list_release(rl, dev, child, type, rid, r)); 4663 } 4664 4665 int 4666 pci_activate_resource(device_t dev, device_t child, int type, int rid, 4667 struct resource *r) 4668 { 4669 struct pci_devinfo *dinfo; 4670 int error; 4671 4672 error = bus_generic_activate_resource(dev, child, type, rid, r); 4673 if (error) 4674 return (error); 4675 4676 /* Enable decoding in the command register when activating BARs. */ 4677 if (device_get_parent(child) == dev) { 4678 /* Device ROMs need their decoding explicitly enabled. */ 4679 dinfo = device_get_ivars(child); 4680 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 4681 pci_write_bar(child, pci_find_bar(child, rid), 4682 rman_get_start(r) | PCIM_BIOS_ENABLE); 4683 switch (type) { 4684 case SYS_RES_IOPORT: 4685 case SYS_RES_MEMORY: 4686 error = PCI_ENABLE_IO(dev, child, type); 4687 break; 4688 } 4689 } 4690 return (error); 4691 } 4692 4693 int 4694 pci_deactivate_resource(device_t dev, device_t child, int type, 4695 int rid, struct resource *r) 4696 { 4697 struct pci_devinfo *dinfo; 4698 int error; 4699 4700 error = bus_generic_deactivate_resource(dev, child, type, rid, r); 4701 if (error) 4702 return (error); 4703 4704 /* Disable decoding for device ROMs. */ 4705 if (device_get_parent(child) == dev) { 4706 dinfo = device_get_ivars(child); 4707 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 4708 pci_write_bar(child, pci_find_bar(child, rid), 4709 rman_get_start(r)); 4710 } 4711 return (0); 4712 } 4713 4714 void 4715 pci_delete_child(device_t dev, device_t child) 4716 { 4717 struct resource_list_entry *rle; 4718 struct resource_list *rl; 4719 struct pci_devinfo *dinfo; 4720 4721 dinfo = device_get_ivars(child); 4722 rl = &dinfo->resources; 4723 4724 if (device_is_attached(child)) 4725 device_detach(child); 4726 4727 /* Turn off access to resources we're about to free */ 4728 pci_write_config(child, PCIR_COMMAND, pci_read_config(child, 4729 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2); 4730 4731 /* Free all allocated resources */ 4732 STAILQ_FOREACH(rle, rl, link) { 4733 if (rle->res) { 4734 if (rman_get_flags(rle->res) & RF_ACTIVE || 4735 resource_list_busy(rl, rle->type, rle->rid)) { 4736 pci_printf(&dinfo->cfg, 4737 "Resource still owned, oops. " 4738 "(type=%d, rid=%d, addr=%lx)\n", 4739 rle->type, rle->rid, 4740 rman_get_start(rle->res)); 4741 bus_release_resource(child, rle->type, rle->rid, 4742 rle->res); 4743 } 4744 resource_list_unreserve(rl, dev, child, rle->type, 4745 rle->rid); 4746 } 4747 } 4748 resource_list_free(rl); 4749 4750 device_delete_child(dev, child); 4751 pci_freecfg(dinfo); 4752 } 4753 4754 void 4755 pci_delete_resource(device_t dev, device_t child, int type, int rid) 4756 { 4757 struct pci_devinfo *dinfo; 4758 struct resource_list *rl; 4759 struct resource_list_entry *rle; 4760 4761 if (device_get_parent(child) != dev) 4762 return; 4763 4764 dinfo = device_get_ivars(child); 4765 rl = &dinfo->resources; 4766 rle = resource_list_find(rl, type, rid); 4767 if (rle == NULL) 4768 return; 4769 4770 if (rle->res) { 4771 if (rman_get_flags(rle->res) & RF_ACTIVE || 4772 resource_list_busy(rl, type, rid)) { 4773 device_printf(dev, "delete_resource: " 4774 "Resource still owned by child, oops. " 4775 "(type=%d, rid=%d, addr=%lx)\n", 4776 type, rid, rman_get_start(rle->res)); 4777 return; 4778 } 4779 resource_list_unreserve(rl, dev, child, type, rid); 4780 } 4781 resource_list_delete(rl, type, rid); 4782 } 4783 4784 struct resource_list * 4785 pci_get_resource_list (device_t dev, device_t child) 4786 { 4787 struct pci_devinfo *dinfo = device_get_ivars(child); 4788 4789 return (&dinfo->resources); 4790 } 4791 4792 bus_dma_tag_t 4793 pci_get_dma_tag(device_t bus, device_t dev) 4794 { 4795 struct pci_softc *sc = device_get_softc(bus); 4796 4797 return (sc->sc_dma_tag); 4798 } 4799 4800 uint32_t 4801 pci_read_config_method(device_t dev, device_t child, int reg, int width) 4802 { 4803 struct pci_devinfo *dinfo = device_get_ivars(child); 4804 pcicfgregs *cfg = &dinfo->cfg; 4805 4806 return (PCIB_READ_CONFIG(device_get_parent(dev), 4807 cfg->bus, cfg->slot, cfg->func, reg, width)); 4808 } 4809 4810 void 4811 pci_write_config_method(device_t dev, device_t child, int reg, 4812 uint32_t val, int width) 4813 { 4814 struct pci_devinfo *dinfo = device_get_ivars(child); 4815 pcicfgregs *cfg = &dinfo->cfg; 4816 4817 PCIB_WRITE_CONFIG(device_get_parent(dev), 4818 cfg->bus, cfg->slot, cfg->func, reg, val, width); 4819 } 4820 4821 int 4822 pci_child_location_str_method(device_t dev, device_t child, char *buf, 4823 size_t buflen) 4824 { 4825 4826 snprintf(buf, buflen, "pci%d:%d:%d:%d", pci_get_domain(child), 4827 pci_get_bus(child), pci_get_slot(child), pci_get_function(child)); 4828 return (0); 4829 } 4830 4831 int 4832 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 4833 size_t buflen) 4834 { 4835 struct pci_devinfo *dinfo; 4836 pcicfgregs *cfg; 4837 4838 dinfo = device_get_ivars(child); 4839 cfg = &dinfo->cfg; 4840 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 4841 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 4842 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 4843 cfg->progif); 4844 return (0); 4845 } 4846 4847 int 4848 pci_assign_interrupt_method(device_t dev, device_t child) 4849 { 4850 struct pci_devinfo *dinfo = device_get_ivars(child); 4851 pcicfgregs *cfg = &dinfo->cfg; 4852 4853 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 4854 cfg->intpin)); 4855 } 4856 4857 static void 4858 pci_lookup(void *arg, const char *name, device_t *dev) 4859 { 4860 long val; 4861 char *end; 4862 int domain, bus, slot, func; 4863 4864 if (*dev != NULL) 4865 return; 4866 4867 /* 4868 * Accept pciconf-style selectors of either pciD:B:S:F or 4869 * pciB:S:F. In the latter case, the domain is assumed to 4870 * be zero. 4871 */ 4872 if (strncmp(name, "pci", 3) != 0) 4873 return; 4874 val = strtol(name + 3, &end, 10); 4875 if (val < 0 || val > INT_MAX || *end != ':') 4876 return; 4877 domain = val; 4878 val = strtol(end + 1, &end, 10); 4879 if (val < 0 || val > INT_MAX || *end != ':') 4880 return; 4881 bus = val; 4882 val = strtol(end + 1, &end, 10); 4883 if (val < 0 || val > INT_MAX) 4884 return; 4885 slot = val; 4886 if (*end == ':') { 4887 val = strtol(end + 1, &end, 10); 4888 if (val < 0 || val > INT_MAX || *end != '\0') 4889 return; 4890 func = val; 4891 } else if (*end == '\0') { 4892 func = slot; 4893 slot = bus; 4894 bus = domain; 4895 domain = 0; 4896 } else 4897 return; 4898 4899 if (domain > PCI_DOMAINMAX || bus > PCI_BUSMAX || slot > PCI_SLOTMAX || 4900 func > PCIE_ARI_FUNCMAX || (slot != 0 && func > PCI_FUNCMAX)) 4901 return; 4902 4903 *dev = pci_find_dbsf(domain, bus, slot, func); 4904 } 4905 4906 static int 4907 pci_modevent(module_t mod, int what, void *arg) 4908 { 4909 static struct cdev *pci_cdev; 4910 static eventhandler_tag tag; 4911 4912 switch (what) { 4913 case MOD_LOAD: 4914 STAILQ_INIT(&pci_devq); 4915 pci_generation = 0; 4916 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 4917 "pci"); 4918 pci_load_vendor_data(); 4919 tag = EVENTHANDLER_REGISTER(dev_lookup, pci_lookup, NULL, 4920 1000); 4921 break; 4922 4923 case MOD_UNLOAD: 4924 if (tag != NULL) 4925 EVENTHANDLER_DEREGISTER(dev_lookup, tag); 4926 destroy_dev(pci_cdev); 4927 break; 4928 } 4929 4930 return (0); 4931 } 4932 4933 static void 4934 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo) 4935 { 4936 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2) 4937 struct pcicfg_pcie *cfg; 4938 int version, pos; 4939 4940 cfg = &dinfo->cfg.pcie; 4941 pos = cfg->pcie_location; 4942 4943 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 4944 4945 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); 4946 4947 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 4948 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 4949 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 4950 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); 4951 4952 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 4953 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 4954 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 4955 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); 4956 4957 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 4958 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 4959 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); 4960 4961 if (version > 1) { 4962 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); 4963 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); 4964 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); 4965 } 4966 #undef WREG 4967 } 4968 4969 static void 4970 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo) 4971 { 4972 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 4973 dinfo->cfg.pcix.pcix_command, 2); 4974 } 4975 4976 void 4977 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 4978 { 4979 4980 /* 4981 * Only do header type 0 devices. Type 1 devices are bridges, 4982 * which we know need special treatment. Type 2 devices are 4983 * cardbus bridges which also require special treatment. 4984 * Other types are unknown, and we err on the side of safety 4985 * by ignoring them. 4986 */ 4987 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 4988 return; 4989 4990 /* 4991 * Restore the device to full power mode. We must do this 4992 * before we restore the registers because moving from D3 to 4993 * D0 will cause the chip's BARs and some other registers to 4994 * be reset to some unknown power on reset values. Cut down 4995 * the noise on boot by doing nothing if we are already in 4996 * state D0. 4997 */ 4998 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) 4999 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 5000 pci_restore_bars(dev); 5001 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 5002 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 5003 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 5004 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 5005 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 5006 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 5007 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 5008 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 5009 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 5010 5011 /* 5012 * Restore extended capabilities for PCI-Express and PCI-X 5013 */ 5014 if (dinfo->cfg.pcie.pcie_location != 0) 5015 pci_cfg_restore_pcie(dev, dinfo); 5016 if (dinfo->cfg.pcix.pcix_location != 0) 5017 pci_cfg_restore_pcix(dev, dinfo); 5018 5019 /* Restore MSI and MSI-X configurations if they are present. */ 5020 if (dinfo->cfg.msi.msi_location != 0) 5021 pci_resume_msi(dev); 5022 if (dinfo->cfg.msix.msix_location != 0) 5023 pci_resume_msix(dev); 5024 } 5025 5026 static void 5027 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo) 5028 { 5029 #define RREG(n) pci_read_config(dev, pos + (n), 2) 5030 struct pcicfg_pcie *cfg; 5031 int version, pos; 5032 5033 cfg = &dinfo->cfg.pcie; 5034 pos = cfg->pcie_location; 5035 5036 cfg->pcie_flags = RREG(PCIER_FLAGS); 5037 5038 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 5039 5040 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); 5041 5042 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5043 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 5044 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 5045 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); 5046 5047 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5048 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 5049 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 5050 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); 5051 5052 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5053 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 5054 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); 5055 5056 if (version > 1) { 5057 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); 5058 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); 5059 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); 5060 } 5061 #undef RREG 5062 } 5063 5064 static void 5065 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo) 5066 { 5067 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, 5068 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); 5069 } 5070 5071 void 5072 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 5073 { 5074 uint32_t cls; 5075 int ps; 5076 5077 /* 5078 * Only do header type 0 devices. Type 1 devices are bridges, which 5079 * we know need special treatment. Type 2 devices are cardbus bridges 5080 * which also require special treatment. Other types are unknown, and 5081 * we err on the side of safety by ignoring them. Powering down 5082 * bridges should not be undertaken lightly. 5083 */ 5084 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 5085 return; 5086 5087 /* 5088 * Some drivers apparently write to these registers w/o updating our 5089 * cached copy. No harm happens if we update the copy, so do so here 5090 * so we can restore them. The COMMAND register is modified by the 5091 * bus w/o updating the cache. This should represent the normally 5092 * writable portion of the 'defined' part of type 0 headers. In 5093 * theory we also need to save/restore the PCI capability structures 5094 * we know about, but apart from power we don't know any that are 5095 * writable. 5096 */ 5097 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 5098 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 5099 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 5100 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 5101 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 5102 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 5103 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 5104 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 5105 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 5106 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 5107 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 5108 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 5109 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 5110 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 5111 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 5112 5113 if (dinfo->cfg.pcie.pcie_location != 0) 5114 pci_cfg_save_pcie(dev, dinfo); 5115 5116 if (dinfo->cfg.pcix.pcix_location != 0) 5117 pci_cfg_save_pcix(dev, dinfo); 5118 5119 /* 5120 * don't set the state for display devices, base peripherals and 5121 * memory devices since bad things happen when they are powered down. 5122 * We should (a) have drivers that can easily detach and (b) use 5123 * generic drivers for these devices so that some device actually 5124 * attaches. We need to make sure that when we implement (a) we don't 5125 * power the device down on a reattach. 5126 */ 5127 cls = pci_get_class(dev); 5128 if (!setstate) 5129 return; 5130 switch (pci_do_power_nodriver) 5131 { 5132 case 0: /* NO powerdown at all */ 5133 return; 5134 case 1: /* Conservative about what to power down */ 5135 if (cls == PCIC_STORAGE) 5136 return; 5137 /*FALLTHROUGH*/ 5138 case 2: /* Agressive about what to power down */ 5139 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 5140 cls == PCIC_BASEPERIPH) 5141 return; 5142 /*FALLTHROUGH*/ 5143 case 3: /* Power down everything */ 5144 break; 5145 } 5146 /* 5147 * PCI spec says we can only go into D3 state from D0 state. 5148 * Transition from D[12] into D0 before going to D3 state. 5149 */ 5150 ps = pci_get_powerstate(dev); 5151 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 5152 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 5153 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 5154 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 5155 } 5156 5157 /* Wrapper APIs suitable for device driver use. */ 5158 void 5159 pci_save_state(device_t dev) 5160 { 5161 struct pci_devinfo *dinfo; 5162 5163 dinfo = device_get_ivars(dev); 5164 pci_cfg_save(dev, dinfo, 0); 5165 } 5166 5167 void 5168 pci_restore_state(device_t dev) 5169 { 5170 struct pci_devinfo *dinfo; 5171 5172 dinfo = device_get_ivars(dev); 5173 pci_cfg_restore(dev, dinfo); 5174 } 5175 5176 static uint16_t 5177 pci_get_rid_method(device_t dev, device_t child) 5178 { 5179 5180 return (PCIB_GET_RID(device_get_parent(dev), child)); 5181 } 5182