1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 5 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000, BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice unmodified, this list of conditions, and the following 14 * disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 #include "opt_acpi.h" 33 #include "opt_iommu.h" 34 #include "opt_bus.h" 35 36 #include <sys/param.h> 37 #include <sys/conf.h> 38 #include <sys/endian.h> 39 #include <sys/eventhandler.h> 40 #include <sys/fcntl.h> 41 #include <sys/kernel.h> 42 #include <sys/limits.h> 43 #include <sys/linker.h> 44 #include <sys/malloc.h> 45 #include <sys/module.h> 46 #include <sys/queue.h> 47 #include <sys/sbuf.h> 48 #include <sys/stdarg.h> 49 #include <sys/sysctl.h> 50 #include <sys/systm.h> 51 #include <sys/taskqueue.h> 52 #include <sys/tree.h> 53 54 #include <vm/vm.h> 55 #include <vm/pmap.h> 56 #include <vm/vm_extern.h> 57 58 #include <sys/bus.h> 59 #include <machine/bus.h> 60 #include <sys/rman.h> 61 #include <machine/resource.h> 62 63 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 64 #include <machine/intr_machdep.h> 65 #endif 66 67 #include <sys/pciio.h> 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pci_private.h> 71 72 #ifdef PCI_IOV 73 #include <sys/nv.h> 74 #include <dev/pci/pci_iov_private.h> 75 #endif 76 77 #include <dev/usb/controller/xhcireg.h> 78 #include <dev/usb/controller/ehcireg.h> 79 #include <dev/usb/controller/ohcireg.h> 80 #include <dev/usb/controller/uhcireg.h> 81 82 #include <dev/iommu/iommu.h> 83 84 #include "pcib_if.h" 85 #include "pci_if.h" 86 87 #define PCIR_IS_BIOS(cfg, reg) \ 88 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ 89 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) 90 91 static device_probe_t pci_probe; 92 93 static bus_reset_post_t pci_reset_post; 94 static bus_reset_prepare_t pci_reset_prepare; 95 static bus_reset_child_t pci_reset_child; 96 static bus_hint_device_unit_t pci_hint_device_unit; 97 static bus_remap_intr_t pci_remap_intr_method; 98 99 static pci_get_id_t pci_get_id_method; 100 101 static int pci_has_quirk(uint32_t devid, int quirk); 102 static pci_addr_t pci_mapbase(uint64_t mapreg); 103 static const char *pci_maptype(uint64_t mapreg); 104 static int pci_maprange(uint64_t mapreg); 105 static pci_addr_t pci_rombase(uint64_t mapreg); 106 static int pci_romsize(uint64_t testval); 107 static void pci_fixancient(pcicfgregs *cfg); 108 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...); 109 110 static int pci_porten(device_t dev); 111 static int pci_memen(device_t dev); 112 static void pci_assign_interrupt(device_t bus, device_t dev, 113 int force_route); 114 static int pci_add_map(device_t bus, device_t dev, int reg, 115 struct resource_list *rl, int force, int prefetch); 116 static void pci_load_vendor_data(void); 117 static int pci_describe_parse_line(char **ptr, int *vendor, 118 int *device, char **desc); 119 static char *pci_describe_device(device_t dev); 120 static int pci_modevent(module_t mod, int what, void *arg); 121 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 122 pcicfgregs *cfg); 123 static void pci_read_cap(device_t pcib, pcicfgregs *cfg); 124 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 125 int reg, uint32_t *data); 126 #if 0 127 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 128 int reg, uint32_t data); 129 #endif 130 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 131 static void pci_mask_msix(device_t dev, u_int index); 132 static void pci_unmask_msix(device_t dev, u_int index); 133 static int pci_msi_blacklisted(void); 134 static int pci_msix_blacklisted(void); 135 static void pci_resume_msi(device_t dev); 136 static void pci_resume_msix(device_t dev); 137 static struct pci_devinfo * pci_fill_devinfo(device_t pcib, device_t bus, int d, 138 int b, int s, int f, uint16_t vid, uint16_t did); 139 140 static device_method_t pci_methods[] = { 141 /* Device interface */ 142 DEVMETHOD(device_probe, pci_probe), 143 DEVMETHOD(device_attach, pci_attach), 144 DEVMETHOD(device_detach, pci_detach), 145 DEVMETHOD(device_shutdown, bus_generic_shutdown), 146 DEVMETHOD(device_suspend, bus_generic_suspend), 147 DEVMETHOD(device_resume, pci_resume), 148 149 /* Bus interface */ 150 DEVMETHOD(bus_print_child, pci_print_child), 151 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 152 DEVMETHOD(bus_read_ivar, pci_read_ivar), 153 DEVMETHOD(bus_write_ivar, pci_write_ivar), 154 DEVMETHOD(bus_driver_added, pci_driver_added), 155 DEVMETHOD(bus_setup_intr, pci_setup_intr), 156 DEVMETHOD(bus_teardown_intr, pci_teardown_intr), 157 DEVMETHOD(bus_reset_prepare, pci_reset_prepare), 158 DEVMETHOD(bus_reset_post, pci_reset_post), 159 DEVMETHOD(bus_reset_child, pci_reset_child), 160 161 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag), 162 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 163 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 164 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 165 DEVMETHOD(bus_delete_resource, pci_delete_resource), 166 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 167 DEVMETHOD(bus_adjust_resource, pci_adjust_resource), 168 DEVMETHOD(bus_release_resource, pci_release_resource), 169 DEVMETHOD(bus_activate_resource, pci_activate_resource), 170 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource), 171 DEVMETHOD(bus_map_resource, pci_map_resource), 172 DEVMETHOD(bus_unmap_resource, pci_unmap_resource), 173 DEVMETHOD(bus_child_deleted, pci_child_deleted), 174 DEVMETHOD(bus_child_detached, pci_child_detached), 175 DEVMETHOD(bus_child_pnpinfo, pci_child_pnpinfo_method), 176 DEVMETHOD(bus_child_location, pci_child_location_method), 177 DEVMETHOD(bus_get_device_path, pci_get_device_path_method), 178 DEVMETHOD(bus_hint_device_unit, pci_hint_device_unit), 179 DEVMETHOD(bus_remap_intr, pci_remap_intr_method), 180 DEVMETHOD(bus_suspend_child, pci_suspend_child), 181 DEVMETHOD(bus_resume_child, pci_resume_child), 182 DEVMETHOD(bus_rescan, pci_rescan_method), 183 184 /* PCI interface */ 185 DEVMETHOD(pci_read_config, pci_read_config_method), 186 DEVMETHOD(pci_write_config, pci_write_config_method), 187 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 188 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 189 DEVMETHOD(pci_enable_io, pci_enable_io_method), 190 DEVMETHOD(pci_disable_io, pci_disable_io_method), 191 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 192 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 193 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 194 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 195 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 196 DEVMETHOD(pci_find_cap, pci_find_cap_method), 197 DEVMETHOD(pci_find_next_cap, pci_find_next_cap_method), 198 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 199 DEVMETHOD(pci_find_next_extcap, pci_find_next_extcap_method), 200 DEVMETHOD(pci_find_htcap, pci_find_htcap_method), 201 DEVMETHOD(pci_find_next_htcap, pci_find_next_htcap_method), 202 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 203 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), 204 DEVMETHOD(pci_enable_msi, pci_enable_msi_method), 205 DEVMETHOD(pci_enable_msix, pci_enable_msix_method), 206 DEVMETHOD(pci_disable_msi, pci_disable_msi_method), 207 DEVMETHOD(pci_remap_msix, pci_remap_msix_method), 208 DEVMETHOD(pci_release_msi, pci_release_msi_method), 209 DEVMETHOD(pci_msi_count, pci_msi_count_method), 210 DEVMETHOD(pci_msix_count, pci_msix_count_method), 211 DEVMETHOD(pci_msix_pba_bar, pci_msix_pba_bar_method), 212 DEVMETHOD(pci_msix_table_bar, pci_msix_table_bar_method), 213 DEVMETHOD(pci_get_id, pci_get_id_method), 214 DEVMETHOD(pci_alloc_devinfo, pci_alloc_devinfo_method), 215 DEVMETHOD(pci_child_added, pci_child_added_method), 216 #ifdef PCI_IOV 217 DEVMETHOD(pci_iov_attach, pci_iov_attach_method), 218 DEVMETHOD(pci_iov_detach, pci_iov_detach_method), 219 DEVMETHOD(pci_create_iov_child, pci_create_iov_child_method), 220 #endif 221 222 DEVMETHOD_END 223 }; 224 225 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc)); 226 227 EARLY_DRIVER_MODULE(pci, pcib, pci_driver, pci_modevent, NULL, BUS_PASS_BUS); 228 MODULE_VERSION(pci, 1); 229 230 static char *pci_vendordata; 231 static size_t pci_vendordata_size; 232 233 struct pci_quirk { 234 uint32_t devid; /* Vendor/device of the card */ 235 int type; 236 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 237 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */ 238 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */ 239 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */ 240 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */ 241 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */ 242 #define PCI_QUIRK_REALLOC_BAR 7 /* Can't allocate memory at the default address */ 243 int arg1; 244 int arg2; 245 }; 246 247 static const struct pci_quirk pci_quirks[] = { 248 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */ 249 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 250 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 251 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 252 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 253 254 /* 255 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge 256 * or the CMIC-SL (AKA ServerWorks GC_LE). 257 */ 258 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 259 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 260 261 /* 262 * MSI doesn't work on earlier Intel chipsets including 263 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855. 264 */ 265 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 266 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 267 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 268 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 269 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 270 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 271 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 272 273 /* 274 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX 275 * bridge. 276 */ 277 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 278 279 /* 280 * Some virtualization environments emulate an older chipset 281 * but support MSI just fine. QEMU uses the Intel 82440. 282 */ 283 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 }, 284 285 /* 286 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus 287 * controller depending on SoftPciRst register (PM_IO 0x55 [7]). 288 * It prevents us from attaching hpet(4) when the bit is unset. 289 * Note this quirk only affects SB600 revision A13 and earlier. 290 * For SB600 A21 and later, firmware must set the bit to hide it. 291 * For SB700 and later, it is unused and hardcoded to zero. 292 */ 293 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 }, 294 295 /* 296 * Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have 297 * a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit 298 * of the command register is set. 299 */ 300 { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 301 { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 302 { 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 303 { 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 304 { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 305 306 /* 307 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't 308 * issue MSI interrupts with PCIM_CMD_INTxDIS set either. 309 */ 310 { 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */ 311 { 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */ 312 { 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */ 313 { 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */ 314 { 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */ 315 { 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */ 316 317 /* 318 * HPE Gen 10 VGA has a memory range that can't be allocated in the 319 * expected place. 320 */ 321 { 0x98741002, PCI_QUIRK_REALLOC_BAR, 0, 0 }, 322 { 0 } 323 }; 324 325 /* map register information */ 326 #define PCI_MAPMEM 0x01 /* memory map */ 327 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 328 #define PCI_MAPPORT 0x04 /* port map */ 329 330 struct devlist pci_devq; 331 uint32_t pci_generation; 332 uint32_t pci_numdevs = 0; 333 static int pcie_chipset, pcix_chipset; 334 335 /* sysctl vars */ 336 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 337 "PCI bus tuning parameters"); 338 339 static int pci_enable_io_modes = 1; 340 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RWTUN, 341 &pci_enable_io_modes, 1, 342 "Enable I/O and memory bits in the config register. Some BIOSes do not" 343 " enable these bits correctly. We'd like to do this all the time, but" 344 " there are some peripherals that this causes problems with."); 345 346 static int pci_do_realloc_bars = 1; 347 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RWTUN, 348 &pci_do_realloc_bars, 0, 349 "Attempt to allocate a new range for any BARs whose original " 350 "firmware-assigned ranges fail to allocate during the initial device scan."); 351 352 static int pci_do_power_nodriver = 0; 353 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RWTUN, 354 &pci_do_power_nodriver, 0, 355 "Place a function into D3 state when no driver attaches to it. 0 means" 356 " disable. 1 means conservatively place function into D3 state. 2 means" 357 " aggressively place function into D3 state. 3 means put absolutely" 358 " everything in D3 state."); 359 360 int pci_do_power_resume = 1; 361 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RWTUN, 362 &pci_do_power_resume, 1, 363 "Transition from D3 -> D0 on resume."); 364 365 int pci_do_power_suspend = 1; 366 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RWTUN, 367 &pci_do_power_suspend, 1, 368 "Transition from D0 -> D3 on suspend."); 369 370 static int pci_do_msi = 1; 371 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RWTUN, &pci_do_msi, 1, 372 "Enable support for MSI interrupts"); 373 374 static int pci_do_msix = 1; 375 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RWTUN, &pci_do_msix, 1, 376 "Enable support for MSI-X interrupts"); 377 378 static int pci_msix_rewrite_table = 0; 379 SYSCTL_INT(_hw_pci, OID_AUTO, msix_rewrite_table, CTLFLAG_RWTUN, 380 &pci_msix_rewrite_table, 0, 381 "Rewrite entire MSI-X table when updating MSI-X entries"); 382 383 static int pci_honor_msi_blacklist = 1; 384 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RDTUN, 385 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X"); 386 387 #if defined(__i386__) || defined(__amd64__) 388 static int pci_usb_takeover = 1; 389 #else 390 static int pci_usb_takeover = 0; 391 #endif 392 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN, 393 &pci_usb_takeover, 1, 394 "Enable early takeover of USB controllers. Disable this if you depend on" 395 " BIOS emulation of USB devices, that is you use USB devices (like" 396 " keyboard or mouse) but do not load USB drivers"); 397 398 static int pci_clear_bars; 399 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0, 400 "Ignore firmware-assigned resources for BARs."); 401 402 static int pci_clear_buses; 403 SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0, 404 "Ignore firmware-assigned bus numbers."); 405 406 static int pci_enable_ari = 1; 407 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari, 408 0, "Enable support for PCIe Alternative RID Interpretation"); 409 410 /* 411 * Some x86 firmware only enables PCIe hotplug if we claim to support aspm, 412 * however enabling it breaks some arm64 firmware as it powers off devices. 413 */ 414 #if defined(__i386__) || defined(__amd64__) 415 int pci_enable_aspm = 1; 416 #else 417 int pci_enable_aspm = 0; 418 #endif 419 SYSCTL_INT(_hw_pci, OID_AUTO, enable_aspm, CTLFLAG_RDTUN, &pci_enable_aspm, 420 0, "Enable support for PCIe Active State Power Management"); 421 422 static int pci_clear_aer_on_attach = 0; 423 SYSCTL_INT(_hw_pci, OID_AUTO, clear_aer_on_attach, CTLFLAG_RWTUN, 424 &pci_clear_aer_on_attach, 0, 425 "Clear port and device AER state on driver attach"); 426 427 static bool pci_enable_mps_tune = true; 428 SYSCTL_BOOL(_hw_pci, OID_AUTO, enable_mps_tune, CTLFLAG_RWTUN, 429 &pci_enable_mps_tune, 1, 430 "Enable tuning of MPS(maximum payload size)." ); 431 432 static bool pci_intx_reroute = true; 433 SYSCTL_BOOL(_hw_pci, OID_AUTO, intx_reroute, CTLFLAG_RWTUN, 434 &pci_intx_reroute, 0, "Re-route INTx interrupts when scanning devices"); 435 436 static int 437 pci_has_quirk(uint32_t devid, int quirk) 438 { 439 const struct pci_quirk *q; 440 441 for (q = &pci_quirks[0]; q->devid; q++) { 442 if (q->devid == devid && q->type == quirk) 443 return (1); 444 } 445 return (0); 446 } 447 448 /* Find a device_t by bus/slot/function in domain 0 */ 449 450 device_t 451 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 452 { 453 454 return (pci_find_dbsf(0, bus, slot, func)); 455 } 456 457 /* Find a device_t by domain/bus/slot/function */ 458 459 device_t 460 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func) 461 { 462 struct pci_devinfo *dinfo = NULL; 463 464 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 465 if ((dinfo->cfg.domain == domain) && 466 (dinfo->cfg.bus == bus) && 467 (dinfo->cfg.slot == slot) && 468 (dinfo->cfg.func == func)) { 469 break; 470 } 471 } 472 473 return (dinfo != NULL ? dinfo->cfg.dev : NULL); 474 } 475 476 /* Find a device_t by vendor/device ID */ 477 478 device_t 479 pci_find_device(uint16_t vendor, uint16_t device) 480 { 481 struct pci_devinfo *dinfo; 482 483 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 484 if ((dinfo->cfg.vendor == vendor) && 485 (dinfo->cfg.device == device)) { 486 return (dinfo->cfg.dev); 487 } 488 } 489 490 return (NULL); 491 } 492 493 device_t 494 pci_find_class(uint8_t class, uint8_t subclass) 495 { 496 struct pci_devinfo *dinfo; 497 498 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 499 if (dinfo->cfg.baseclass == class && 500 dinfo->cfg.subclass == subclass) { 501 return (dinfo->cfg.dev); 502 } 503 } 504 505 return (NULL); 506 } 507 508 device_t 509 pci_find_class_from(uint8_t class, uint8_t subclass, device_t from) 510 { 511 struct pci_devinfo *dinfo; 512 bool found = false; 513 514 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 515 if (from != NULL && found == false) { 516 if (from != dinfo->cfg.dev) 517 continue; 518 found = true; 519 continue; 520 } 521 if (dinfo->cfg.baseclass == class && 522 dinfo->cfg.subclass == subclass) { 523 return (dinfo->cfg.dev); 524 } 525 } 526 527 return (NULL); 528 } 529 530 device_t 531 pci_find_base_class_from(uint8_t class, device_t from) 532 { 533 struct pci_devinfo *dinfo; 534 bool found = false; 535 536 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 537 if (from != NULL && found == false) { 538 if (from != dinfo->cfg.dev) 539 continue; 540 found = true; 541 continue; 542 } 543 if (dinfo->cfg.baseclass == class) { 544 return (dinfo->cfg.dev); 545 } 546 } 547 548 return (NULL); 549 } 550 551 static int 552 pci_printf(pcicfgregs *cfg, const char *fmt, ...) 553 { 554 va_list ap; 555 int retval; 556 557 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, 558 cfg->func); 559 va_start(ap, fmt); 560 retval += vprintf(fmt, ap); 561 va_end(ap); 562 return (retval); 563 } 564 565 /* return base address of memory or port map */ 566 567 static pci_addr_t 568 pci_mapbase(uint64_t mapreg) 569 { 570 571 if (PCI_BAR_MEM(mapreg)) 572 return (mapreg & PCIM_BAR_MEM_BASE); 573 else 574 return (mapreg & PCIM_BAR_IO_BASE); 575 } 576 577 /* return map type of memory or port map */ 578 579 static const char * 580 pci_maptype(uint64_t mapreg) 581 { 582 583 if (PCI_BAR_IO(mapreg)) 584 return ("I/O Port"); 585 if (mapreg & PCIM_BAR_MEM_PREFETCH) 586 return ("Prefetchable Memory"); 587 return ("Memory"); 588 } 589 590 /* return log2 of map size decoded for memory or port map */ 591 592 int 593 pci_mapsize(uint64_t testval) 594 { 595 int ln2size; 596 597 testval = pci_mapbase(testval); 598 ln2size = 0; 599 if (testval != 0) { 600 while ((testval & 1) == 0) 601 { 602 ln2size++; 603 testval >>= 1; 604 } 605 } 606 return (ln2size); 607 } 608 609 /* return base address of device ROM */ 610 611 static pci_addr_t 612 pci_rombase(uint64_t mapreg) 613 { 614 615 return (mapreg & PCIM_BIOS_ADDR_MASK); 616 } 617 618 /* return log2 of map size decided for device ROM */ 619 620 static int 621 pci_romsize(uint64_t testval) 622 { 623 int ln2size; 624 625 testval = pci_rombase(testval); 626 ln2size = 0; 627 if (testval != 0) { 628 while ((testval & 1) == 0) 629 { 630 ln2size++; 631 testval >>= 1; 632 } 633 } 634 return (ln2size); 635 } 636 637 /* return log2 of address range supported by map register */ 638 639 static int 640 pci_maprange(uint64_t mapreg) 641 { 642 int ln2range = 0; 643 644 if (PCI_BAR_IO(mapreg)) 645 ln2range = 32; 646 else 647 switch (mapreg & PCIM_BAR_MEM_TYPE) { 648 case PCIM_BAR_MEM_32: 649 ln2range = 32; 650 break; 651 case PCIM_BAR_MEM_1MB: 652 ln2range = 20; 653 break; 654 case PCIM_BAR_MEM_64: 655 ln2range = 64; 656 break; 657 } 658 return (ln2range); 659 } 660 661 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 662 663 static void 664 pci_fixancient(pcicfgregs *cfg) 665 { 666 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 667 return; 668 669 /* PCI to PCI bridges use header type 1 */ 670 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 671 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; 672 } 673 674 /* extract header type specific config data */ 675 676 static void 677 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 678 { 679 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 680 switch (cfg->hdrtype & PCIM_HDRTYPE) { 681 case PCIM_HDRTYPE_NORMAL: 682 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 683 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 684 cfg->mingnt = REG(PCIR_MINGNT, 1); 685 cfg->maxlat = REG(PCIR_MAXLAT, 1); 686 cfg->nummaps = PCI_MAXMAPS_0; 687 break; 688 case PCIM_HDRTYPE_BRIDGE: 689 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1); 690 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1); 691 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1); 692 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1); 693 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2); 694 cfg->nummaps = PCI_MAXMAPS_1; 695 break; 696 case PCIM_HDRTYPE_CARDBUS: 697 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1); 698 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1); 699 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1); 700 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1); 701 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2); 702 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 703 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 704 cfg->nummaps = PCI_MAXMAPS_2; 705 break; 706 } 707 #undef REG 708 } 709 710 /* read configuration header into pcicfgregs structure */ 711 struct pci_devinfo * 712 pci_read_device(device_t pcib, device_t bus, int d, int b, int s, int f) 713 { 714 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 715 uint16_t vid, did; 716 717 vid = REG(PCIR_VENDOR, 2); 718 if (vid == PCIV_INVALID) 719 return (NULL); 720 721 did = REG(PCIR_DEVICE, 2); 722 723 return (pci_fill_devinfo(pcib, bus, d, b, s, f, vid, did)); 724 } 725 726 struct pci_devinfo * 727 pci_alloc_devinfo_method(device_t dev) 728 { 729 730 return (malloc(sizeof(struct pci_devinfo), M_DEVBUF, 731 M_WAITOK | M_ZERO)); 732 } 733 734 static struct pci_devinfo * 735 pci_fill_devinfo(device_t pcib, device_t bus, int d, int b, int s, int f, 736 uint16_t vid, uint16_t did) 737 { 738 struct pci_devinfo *devlist_entry; 739 pcicfgregs *cfg; 740 741 devlist_entry = PCI_ALLOC_DEVINFO(bus); 742 743 cfg = &devlist_entry->cfg; 744 745 cfg->domain = d; 746 cfg->bus = b; 747 cfg->slot = s; 748 cfg->func = f; 749 cfg->vendor = vid; 750 cfg->device = did; 751 cfg->cmdreg = REG(PCIR_COMMAND, 2); 752 cfg->statreg = REG(PCIR_STATUS, 2); 753 cfg->baseclass = REG(PCIR_CLASS, 1); 754 cfg->subclass = REG(PCIR_SUBCLASS, 1); 755 cfg->progif = REG(PCIR_PROGIF, 1); 756 cfg->revid = REG(PCIR_REVID, 1); 757 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 758 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 759 cfg->lattimer = REG(PCIR_LATTIMER, 1); 760 cfg->intpin = REG(PCIR_INTPIN, 1); 761 cfg->intline = REG(PCIR_INTLINE, 1); 762 763 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 764 cfg->hdrtype &= ~PCIM_MFDEV; 765 STAILQ_INIT(&cfg->maps); 766 767 cfg->iov = NULL; 768 769 pci_fixancient(cfg); 770 pci_hdrtypedata(pcib, b, s, f, cfg); 771 772 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 773 pci_read_cap(pcib, cfg); 774 775 STAILQ_INSERT_TAIL(&pci_devq, devlist_entry, pci_links); 776 777 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; 778 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 779 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 780 devlist_entry->conf.pc_sel.pc_func = cfg->func; 781 devlist_entry->conf.pc_hdr = cfg->hdrtype; 782 783 devlist_entry->conf.pc_subvendor = cfg->subvendor; 784 devlist_entry->conf.pc_subdevice = cfg->subdevice; 785 devlist_entry->conf.pc_vendor = cfg->vendor; 786 devlist_entry->conf.pc_device = cfg->device; 787 788 devlist_entry->conf.pc_class = cfg->baseclass; 789 devlist_entry->conf.pc_subclass = cfg->subclass; 790 devlist_entry->conf.pc_progif = cfg->progif; 791 devlist_entry->conf.pc_revid = cfg->revid; 792 793 pci_numdevs++; 794 pci_generation++; 795 796 return (devlist_entry); 797 } 798 #undef REG 799 800 static void 801 pci_ea_fill_info(device_t pcib, pcicfgregs *cfg) 802 { 803 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \ 804 cfg->ea.ea_location + (n), w) 805 int num_ent; 806 int ptr; 807 int a, b; 808 uint32_t val; 809 int ent_size; 810 uint32_t dw[4]; 811 uint64_t base, max_offset; 812 struct pci_ea_entry *eae; 813 814 if (cfg->ea.ea_location == 0) 815 return; 816 817 STAILQ_INIT(&cfg->ea.ea_entries); 818 819 /* Determine the number of entries */ 820 num_ent = REG(PCIR_EA_NUM_ENT, 2); 821 num_ent &= PCIM_EA_NUM_ENT_MASK; 822 823 /* Find the first entry to care of */ 824 ptr = PCIR_EA_FIRST_ENT; 825 826 /* Skip DWORD 2 for type 1 functions */ 827 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) 828 ptr += 4; 829 830 for (a = 0; a < num_ent; a++) { 831 eae = malloc(sizeof(*eae), M_DEVBUF, M_WAITOK | M_ZERO); 832 eae->eae_cfg_offset = cfg->ea.ea_location + ptr; 833 834 /* Read a number of dwords in the entry */ 835 val = REG(ptr, 4); 836 ptr += 4; 837 ent_size = (val & PCIM_EA_ES); 838 839 for (b = 0; b < ent_size; b++) { 840 dw[b] = REG(ptr, 4); 841 ptr += 4; 842 } 843 844 eae->eae_flags = val; 845 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 846 847 base = dw[0] & PCIM_EA_FIELD_MASK; 848 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 849 b = 2; 850 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 851 base |= (uint64_t)dw[b] << 32UL; 852 b++; 853 } 854 if (((dw[1] & PCIM_EA_IS_64) != 0) 855 && (b < ent_size)) { 856 max_offset |= (uint64_t)dw[b] << 32UL; 857 b++; 858 } 859 860 eae->eae_base = base; 861 eae->eae_max_offset = max_offset; 862 863 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link); 864 865 if (bootverbose) { 866 printf("PCI(EA) dev %04x:%04x, bei %d, flags #%x, base #%jx, max_offset #%jx\n", 867 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags, 868 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset); 869 } 870 } 871 } 872 #undef REG 873 874 static void 875 pci_read_cap(device_t pcib, pcicfgregs *cfg) 876 { 877 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 878 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 879 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 880 uint64_t addr; 881 #endif 882 uint32_t val; 883 int ptr, nextptr, ptrptr; 884 885 switch (cfg->hdrtype & PCIM_HDRTYPE) { 886 case PCIM_HDRTYPE_NORMAL: 887 case PCIM_HDRTYPE_BRIDGE: 888 ptrptr = PCIR_CAP_PTR; 889 break; 890 case PCIM_HDRTYPE_CARDBUS: 891 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 892 break; 893 default: 894 return; /* no extended capabilities support */ 895 } 896 nextptr = REG(ptrptr, 1); /* sanity check? */ 897 898 /* 899 * Read capability entries. 900 */ 901 while (nextptr != 0) { 902 /* Sanity check */ 903 if (nextptr > 255) { 904 printf("illegal PCI extended capability offset %d\n", 905 nextptr); 906 return; 907 } 908 /* Find the next entry */ 909 ptr = nextptr; 910 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 911 912 /* Process this entry */ 913 switch (REG(ptr + PCICAP_ID, 1)) { 914 case PCIY_PMG: /* PCI power management */ 915 cfg->pp.pp_location = ptr; 916 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 917 break; 918 case PCIY_HT: /* HyperTransport */ 919 /* Determine HT-specific capability type. */ 920 val = REG(ptr + PCIR_HT_COMMAND, 2); 921 922 if ((val & 0xe000) == PCIM_HTCAP_SLAVE) 923 cfg->ht.ht_slave = ptr; 924 925 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 926 switch (val & PCIM_HTCMD_CAP_MASK) { 927 case PCIM_HTCAP_MSI_MAPPING: 928 if (!(val & PCIM_HTCMD_MSI_FIXED)) { 929 /* Sanity check the mapping window. */ 930 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 931 4); 932 addr <<= 32; 933 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 934 4); 935 if (addr != MSI_INTEL_ADDR_BASE) 936 device_printf(pcib, 937 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", 938 cfg->domain, cfg->bus, 939 cfg->slot, cfg->func, 940 (long long)addr); 941 } else 942 addr = MSI_INTEL_ADDR_BASE; 943 944 cfg->ht.ht_msimap = ptr; 945 cfg->ht.ht_msictrl = val; 946 cfg->ht.ht_msiaddr = addr; 947 break; 948 } 949 #endif 950 break; 951 case PCIY_MSI: /* PCI MSI */ 952 cfg->msi.msi_location = ptr; 953 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 954 break; 955 case PCIY_MSIX: /* PCI MSI-X */ 956 cfg->msix.msix_location = ptr; 957 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 958 val = REG(ptr + PCIR_MSIX_TABLE, 4); 959 cfg->msix.msix_table_bar = PCIR_BAR(val & 960 PCIM_MSIX_BIR_MASK); 961 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 962 val = REG(ptr + PCIR_MSIX_PBA, 4); 963 cfg->msix.msix_pba_bar = PCIR_BAR(val & 964 PCIM_MSIX_BIR_MASK); 965 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 966 break; 967 case PCIY_VPD: /* PCI Vital Product Data */ 968 cfg->vpd.vpd_reg = ptr; 969 break; 970 case PCIY_SUBVENDOR: 971 /* Should always be true. */ 972 if ((cfg->hdrtype & PCIM_HDRTYPE) == 973 PCIM_HDRTYPE_BRIDGE) { 974 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4); 975 cfg->subvendor = val & 0xffff; 976 cfg->subdevice = val >> 16; 977 } 978 break; 979 case PCIY_PCIX: /* PCI-X */ 980 /* 981 * Assume we have a PCI-X chipset if we have 982 * at least one PCI-PCI bridge with a PCI-X 983 * capability. Note that some systems with 984 * PCI-express or HT chipsets might match on 985 * this check as well. 986 */ 987 if ((cfg->hdrtype & PCIM_HDRTYPE) == 988 PCIM_HDRTYPE_BRIDGE) 989 pcix_chipset = 1; 990 cfg->pcix.pcix_location = ptr; 991 break; 992 case PCIY_EXPRESS: /* PCI-express */ 993 /* 994 * Assume we have a PCI-express chipset if we have 995 * at least one PCI-express device. 996 */ 997 pcie_chipset = 1; 998 cfg->pcie.pcie_location = ptr; 999 val = REG(ptr + PCIER_FLAGS, 2); 1000 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; 1001 break; 1002 case PCIY_EA: /* Enhanced Allocation */ 1003 cfg->ea.ea_location = ptr; 1004 pci_ea_fill_info(pcib, cfg); 1005 break; 1006 default: 1007 break; 1008 } 1009 } 1010 1011 #if defined(__powerpc__) 1012 /* 1013 * Enable the MSI mapping window for all HyperTransport 1014 * slaves. PCI-PCI bridges have their windows enabled via 1015 * PCIB_MAP_MSI(). 1016 */ 1017 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && 1018 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { 1019 device_printf(pcib, 1020 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n", 1021 cfg->domain, cfg->bus, cfg->slot, cfg->func); 1022 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 1023 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, 1024 2); 1025 } 1026 #endif 1027 /* REG and WREG use carry through to next functions */ 1028 } 1029 1030 /* 1031 * PCI Vital Product Data 1032 */ 1033 1034 #define PCI_VPD_TIMEOUT 1000000 1035 1036 static int 1037 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data) 1038 { 1039 int count = PCI_VPD_TIMEOUT; 1040 1041 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1042 1043 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); 1044 1045 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { 1046 if (--count < 0) 1047 return (ENXIO); 1048 DELAY(1); /* limit looping */ 1049 } 1050 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); 1051 1052 return (0); 1053 } 1054 1055 #if 0 1056 static int 1057 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 1058 { 1059 int count = PCI_VPD_TIMEOUT; 1060 1061 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1062 1063 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4); 1064 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2); 1065 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) { 1066 if (--count < 0) 1067 return (ENXIO); 1068 DELAY(1); /* limit looping */ 1069 } 1070 1071 return (0); 1072 } 1073 #endif 1074 1075 #undef PCI_VPD_TIMEOUT 1076 1077 struct vpd_readstate { 1078 device_t pcib; 1079 pcicfgregs *cfg; 1080 uint32_t val; 1081 int bytesinval; 1082 int off; 1083 uint8_t cksum; 1084 }; 1085 1086 /* return 0 and one byte in *data if no read error, -1 else */ 1087 static int 1088 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data) 1089 { 1090 uint32_t reg; 1091 uint8_t byte; 1092 1093 if (vrs->bytesinval == 0) { 1094 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) 1095 return (-1); 1096 vrs->val = le32toh(reg); 1097 vrs->off += 4; 1098 byte = vrs->val & 0xff; 1099 vrs->bytesinval = 3; 1100 } else { 1101 vrs->val = vrs->val >> 8; 1102 byte = vrs->val & 0xff; 1103 vrs->bytesinval--; 1104 } 1105 1106 vrs->cksum += byte; 1107 *data = byte; 1108 return (0); 1109 } 1110 1111 /* return 0 on match, -1 and "unget" byte on no match */ 1112 static int 1113 vpd_expectbyte(struct vpd_readstate *vrs, uint8_t expected) 1114 { 1115 uint8_t data; 1116 1117 if (vpd_nextbyte(vrs, &data) != 0) 1118 return (-1); 1119 1120 if (data == expected) 1121 return (0); 1122 1123 vrs->cksum -= data; 1124 vrs->val = (vrs->val << 8) + data; 1125 vrs->bytesinval++; 1126 return (-1); 1127 } 1128 1129 /* return size if tag matches, -1 on no match, -2 on read error */ 1130 static int 1131 vpd_read_tag_size(struct vpd_readstate *vrs, uint8_t vpd_tag) 1132 { 1133 uint8_t byte1, byte2; 1134 1135 if (vpd_expectbyte(vrs, vpd_tag) != 0) 1136 return (-1); 1137 1138 if ((vpd_tag & 0x80) == 0) 1139 return (vpd_tag & 0x07); 1140 1141 if (vpd_nextbyte(vrs, &byte1) != 0) 1142 return (-2); 1143 if (vpd_nextbyte(vrs, &byte2) != 0) 1144 return (-2); 1145 1146 return ((byte2 << 8) + byte1); 1147 } 1148 1149 /* (re)allocate buffer in multiples of 8 elements */ 1150 static void* 1151 alloc_buffer(void* buffer, size_t element_size, int needed) 1152 { 1153 int alloc, new_alloc; 1154 1155 alloc = roundup2(needed, 8); 1156 new_alloc = roundup2(needed + 1, 8); 1157 if (alloc != new_alloc) { 1158 buffer = reallocf(buffer, 1159 new_alloc * element_size, M_DEVBUF, M_WAITOK | M_ZERO); 1160 } 1161 1162 return (buffer); 1163 } 1164 1165 /* read VPD keyword and return element size, return -1 on read error */ 1166 static int 1167 vpd_read_elem_head(struct vpd_readstate *vrs, char keyword[2]) 1168 { 1169 uint8_t data; 1170 1171 if (vpd_nextbyte(vrs, &keyword[0]) != 0) 1172 return (-1); 1173 if (vpd_nextbyte(vrs, &keyword[1]) != 0) 1174 return (-1); 1175 if (vpd_nextbyte(vrs, &data) != 0) 1176 return (-1); 1177 1178 return (data); 1179 } 1180 1181 /* read VPD data element of given size into allocated buffer */ 1182 static char * 1183 vpd_read_value(struct vpd_readstate *vrs, int size) 1184 { 1185 int i; 1186 char char1; 1187 char *value; 1188 1189 value = malloc(size + 1, M_DEVBUF, M_WAITOK); 1190 for (i = 0; i < size; i++) { 1191 if (vpd_nextbyte(vrs, &char1) != 0) { 1192 free(value, M_DEVBUF); 1193 return (NULL); 1194 } 1195 value[i] = char1; 1196 } 1197 value[size] = '\0'; 1198 1199 return (value); 1200 } 1201 1202 /* read VPD into *keyword and *value, return length of data element */ 1203 static int 1204 vpd_read_elem_data(struct vpd_readstate *vrs, char keyword[2], char **value, int maxlen) 1205 { 1206 int len; 1207 1208 len = vpd_read_elem_head(vrs, keyword); 1209 if (len < 0 || len > maxlen) 1210 return (-1); 1211 *value = vpd_read_value(vrs, len); 1212 1213 return (len); 1214 } 1215 1216 /* subtract all data following first byte from checksum of RV element */ 1217 static void 1218 vpd_fixup_cksum(struct vpd_readstate *vrs, char *rvstring, int len) 1219 { 1220 int i; 1221 uint8_t fixup; 1222 1223 fixup = 0; 1224 for (i = 1; i < len; i++) 1225 fixup += rvstring[i]; 1226 vrs->cksum -= fixup; 1227 } 1228 1229 /* fetch one read-only element and return size of heading + data */ 1230 static int 1231 next_vpd_ro_elem(struct vpd_readstate *vrs, int maxsize) 1232 { 1233 struct pcicfg_vpd *vpd; 1234 pcicfgregs *cfg; 1235 struct vpd_readonly *vpd_ros; 1236 int len; 1237 1238 cfg = vrs->cfg; 1239 vpd = &cfg->vpd; 1240 1241 if (maxsize < 3) 1242 return (-1); 1243 vpd->vpd_ros = alloc_buffer(vpd->vpd_ros, sizeof(*vpd->vpd_ros), vpd->vpd_rocnt); 1244 vpd_ros = &vpd->vpd_ros[vpd->vpd_rocnt]; 1245 maxsize -= 3; 1246 len = vpd_read_elem_data(vrs, vpd_ros->keyword, &vpd_ros->value, maxsize); 1247 if (vpd_ros->value == NULL) 1248 return (-1); 1249 vpd_ros->len = len; 1250 if (vpd_ros->keyword[0] == 'R' && vpd_ros->keyword[1] == 'V') { 1251 vpd_fixup_cksum(vrs, vpd_ros->value, len); 1252 if (vrs->cksum != 0) { 1253 pci_printf(cfg, 1254 "invalid VPD checksum %#hhx\n", vrs->cksum); 1255 return (-1); 1256 } 1257 } 1258 vpd->vpd_rocnt++; 1259 1260 return (len + 3); 1261 } 1262 1263 /* fetch one writable element and return size of heading + data */ 1264 static int 1265 next_vpd_rw_elem(struct vpd_readstate *vrs, int maxsize) 1266 { 1267 struct pcicfg_vpd *vpd; 1268 pcicfgregs *cfg; 1269 struct vpd_write *vpd_w; 1270 int len; 1271 1272 cfg = vrs->cfg; 1273 vpd = &cfg->vpd; 1274 1275 if (maxsize < 3) 1276 return (-1); 1277 vpd->vpd_w = alloc_buffer(vpd->vpd_w, sizeof(*vpd->vpd_w), vpd->vpd_wcnt); 1278 if (vpd->vpd_w == NULL) { 1279 pci_printf(cfg, "out of memory"); 1280 return (-1); 1281 } 1282 vpd_w = &vpd->vpd_w[vpd->vpd_wcnt]; 1283 maxsize -= 3; 1284 vpd_w->start = vrs->off + 3 - vrs->bytesinval; 1285 len = vpd_read_elem_data(vrs, vpd_w->keyword, &vpd_w->value, maxsize); 1286 if (vpd_w->value == NULL) 1287 return (-1); 1288 vpd_w->len = len; 1289 vpd->vpd_wcnt++; 1290 1291 return (len + 3); 1292 } 1293 1294 /* free all memory allocated for VPD data */ 1295 static void 1296 vpd_free(struct pcicfg_vpd *vpd) 1297 { 1298 int i; 1299 1300 free(vpd->vpd_ident, M_DEVBUF); 1301 for (i = 0; i < vpd->vpd_rocnt; i++) 1302 free(vpd->vpd_ros[i].value, M_DEVBUF); 1303 free(vpd->vpd_ros, M_DEVBUF); 1304 vpd->vpd_rocnt = 0; 1305 for (i = 0; i < vpd->vpd_wcnt; i++) 1306 free(vpd->vpd_w[i].value, M_DEVBUF); 1307 free(vpd->vpd_w, M_DEVBUF); 1308 vpd->vpd_wcnt = 0; 1309 } 1310 1311 #define VPD_TAG_END ((0x0f << 3) | 0) /* small tag, len == 0 */ 1312 #define VPD_TAG_IDENT (0x02 | 0x80) /* large tag */ 1313 #define VPD_TAG_RO (0x10 | 0x80) /* large tag */ 1314 #define VPD_TAG_RW (0x11 | 0x80) /* large tag */ 1315 1316 static int 1317 pci_parse_vpd(device_t pcib, pcicfgregs *cfg) 1318 { 1319 struct vpd_readstate vrs; 1320 int cksumvalid; 1321 int size, elem_size; 1322 1323 /* init vpd reader */ 1324 vrs.bytesinval = 0; 1325 vrs.off = 0; 1326 vrs.pcib = pcib; 1327 vrs.cfg = cfg; 1328 vrs.cksum = 0; 1329 1330 /* read VPD ident element - mandatory */ 1331 size = vpd_read_tag_size(&vrs, VPD_TAG_IDENT); 1332 if (size <= 0) { 1333 pci_printf(cfg, "no VPD ident found\n"); 1334 return (0); 1335 } 1336 cfg->vpd.vpd_ident = vpd_read_value(&vrs, size); 1337 if (cfg->vpd.vpd_ident == NULL) { 1338 pci_printf(cfg, "error accessing VPD ident data\n"); 1339 return (0); 1340 } 1341 1342 /* read VPD RO elements - mandatory */ 1343 size = vpd_read_tag_size(&vrs, VPD_TAG_RO); 1344 if (size <= 0) { 1345 pci_printf(cfg, "no read-only VPD data found\n"); 1346 return (0); 1347 } 1348 while (size > 0) { 1349 elem_size = next_vpd_ro_elem(&vrs, size); 1350 if (elem_size < 0) { 1351 pci_printf(cfg, "error accessing read-only VPD data\n"); 1352 return (-1); 1353 } 1354 size -= elem_size; 1355 } 1356 cksumvalid = (vrs.cksum == 0); 1357 if (!cksumvalid) 1358 return (-1); 1359 1360 /* read VPD RW elements - optional */ 1361 size = vpd_read_tag_size(&vrs, VPD_TAG_RW); 1362 if (size == -2) 1363 return (-1); 1364 while (size > 0) { 1365 elem_size = next_vpd_rw_elem(&vrs, size); 1366 if (elem_size < 0) { 1367 pci_printf(cfg, "error accessing writeable VPD data\n"); 1368 return (-1); 1369 } 1370 size -= elem_size; 1371 } 1372 1373 /* read empty END tag - mandatory */ 1374 size = vpd_read_tag_size(&vrs, VPD_TAG_END); 1375 if (size != 0) { 1376 pci_printf(cfg, "No valid VPD end tag found\n"); 1377 } 1378 return (0); 1379 } 1380 1381 static void 1382 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 1383 { 1384 int status; 1385 1386 status = pci_parse_vpd(pcib, cfg); 1387 if (status < 0) 1388 vpd_free(&cfg->vpd); 1389 cfg->vpd.vpd_cached = 1; 1390 #undef REG 1391 #undef WREG 1392 } 1393 1394 int 1395 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 1396 { 1397 struct pci_devinfo *dinfo = device_get_ivars(child); 1398 pcicfgregs *cfg = &dinfo->cfg; 1399 1400 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1401 pci_read_vpd(device_get_parent(dev), cfg); 1402 1403 *identptr = cfg->vpd.vpd_ident; 1404 1405 if (*identptr == NULL) 1406 return (ENXIO); 1407 1408 return (0); 1409 } 1410 1411 int 1412 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 1413 const char **vptr) 1414 { 1415 struct pci_devinfo *dinfo = device_get_ivars(child); 1416 pcicfgregs *cfg = &dinfo->cfg; 1417 int i; 1418 1419 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1420 pci_read_vpd(device_get_parent(dev), cfg); 1421 1422 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 1423 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 1424 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { 1425 *vptr = cfg->vpd.vpd_ros[i].value; 1426 return (0); 1427 } 1428 1429 *vptr = NULL; 1430 return (ENXIO); 1431 } 1432 1433 struct pcicfg_vpd * 1434 pci_fetch_vpd_list(device_t dev) 1435 { 1436 struct pci_devinfo *dinfo = device_get_ivars(dev); 1437 pcicfgregs *cfg = &dinfo->cfg; 1438 1439 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1440 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg); 1441 return (&cfg->vpd); 1442 } 1443 1444 /* 1445 * Find the requested HyperTransport capability and return the offset 1446 * in configuration space via the pointer provided. The function 1447 * returns 0 on success and an error code otherwise. 1448 */ 1449 int 1450 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg) 1451 { 1452 int ptr, error; 1453 uint16_t val; 1454 1455 error = pci_find_cap(child, PCIY_HT, &ptr); 1456 if (error) 1457 return (error); 1458 1459 /* 1460 * Traverse the capabilities list checking each HT capability 1461 * to see if it matches the requested HT capability. 1462 */ 1463 for (;;) { 1464 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1465 if (capability == PCIM_HTCAP_SLAVE || 1466 capability == PCIM_HTCAP_HOST) 1467 val &= 0xe000; 1468 else 1469 val &= PCIM_HTCMD_CAP_MASK; 1470 if (val == capability) { 1471 if (capreg != NULL) 1472 *capreg = ptr; 1473 return (0); 1474 } 1475 1476 /* Skip to the next HT capability. */ 1477 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1478 break; 1479 } 1480 1481 return (ENOENT); 1482 } 1483 1484 /* 1485 * Find the next requested HyperTransport capability after start and return 1486 * the offset in configuration space via the pointer provided. The function 1487 * returns 0 on success and an error code otherwise. 1488 */ 1489 int 1490 pci_find_next_htcap_method(device_t dev, device_t child, int capability, 1491 int start, int *capreg) 1492 { 1493 int ptr; 1494 uint16_t val; 1495 1496 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == PCIY_HT, 1497 ("start capability is not HyperTransport capability")); 1498 ptr = start; 1499 1500 /* 1501 * Traverse the capabilities list checking each HT capability 1502 * to see if it matches the requested HT capability. 1503 */ 1504 for (;;) { 1505 /* Skip to the next HT capability. */ 1506 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1507 break; 1508 1509 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1510 if (capability == PCIM_HTCAP_SLAVE || 1511 capability == PCIM_HTCAP_HOST) 1512 val &= 0xe000; 1513 else 1514 val &= PCIM_HTCMD_CAP_MASK; 1515 if (val == capability) { 1516 if (capreg != NULL) 1517 *capreg = ptr; 1518 return (0); 1519 } 1520 } 1521 1522 return (ENOENT); 1523 } 1524 1525 /* 1526 * Find the requested capability and return the offset in 1527 * configuration space via the pointer provided. The function returns 1528 * 0 on success and an error code otherwise. 1529 */ 1530 int 1531 pci_find_cap_method(device_t dev, device_t child, int capability, 1532 int *capreg) 1533 { 1534 struct pci_devinfo *dinfo = device_get_ivars(child); 1535 pcicfgregs *cfg = &dinfo->cfg; 1536 uint32_t status; 1537 uint8_t ptr; 1538 int cnt; 1539 1540 /* 1541 * Check the CAP_LIST bit of the PCI status register first. 1542 */ 1543 status = pci_read_config(child, PCIR_STATUS, 2); 1544 if (!(status & PCIM_STATUS_CAPPRESENT)) 1545 return (ENXIO); 1546 1547 /* 1548 * Determine the start pointer of the capabilities list. 1549 */ 1550 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1551 case PCIM_HDRTYPE_NORMAL: 1552 case PCIM_HDRTYPE_BRIDGE: 1553 ptr = PCIR_CAP_PTR; 1554 break; 1555 case PCIM_HDRTYPE_CARDBUS: 1556 ptr = PCIR_CAP_PTR_2; 1557 break; 1558 default: 1559 /* XXX: panic? */ 1560 return (ENXIO); /* no extended capabilities support */ 1561 } 1562 ptr = pci_read_config(child, ptr, 1); 1563 1564 /* 1565 * Traverse the capabilities list. Limit by total theoretical 1566 * maximum number of caps: capability needs at least id and 1567 * next registers, and any type X header cannot contain caps. 1568 */ 1569 for (cnt = 0; ptr != 0 && cnt < (PCIE_REGMAX - 0x40) / 2; cnt++) { 1570 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1571 if (capreg != NULL) 1572 *capreg = ptr; 1573 return (0); 1574 } 1575 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1576 } 1577 1578 return (ENOENT); 1579 } 1580 1581 /* 1582 * Find the next requested capability after start and return the offset in 1583 * configuration space via the pointer provided. The function returns 1584 * 0 on success and an error code otherwise. 1585 */ 1586 int 1587 pci_find_next_cap_method(device_t dev, device_t child, int capability, 1588 int start, int *capreg) 1589 { 1590 uint8_t ptr; 1591 1592 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == capability, 1593 ("start capability is not expected capability")); 1594 1595 ptr = pci_read_config(child, start + PCICAP_NEXTPTR, 1); 1596 while (ptr != 0) { 1597 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1598 if (capreg != NULL) 1599 *capreg = ptr; 1600 return (0); 1601 } 1602 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1603 } 1604 1605 return (ENOENT); 1606 } 1607 1608 /* 1609 * Find the requested extended capability and return the offset in 1610 * configuration space via the pointer provided. The function returns 1611 * 0 on success and an error code otherwise. 1612 */ 1613 int 1614 pci_find_extcap_method(device_t dev, device_t child, int capability, 1615 int *capreg) 1616 { 1617 struct pci_devinfo *dinfo = device_get_ivars(child); 1618 pcicfgregs *cfg = &dinfo->cfg; 1619 uint32_t ecap; 1620 uint16_t ptr; 1621 1622 /* Only supported for PCI-express devices. */ 1623 if (cfg->pcie.pcie_location == 0) 1624 return (ENXIO); 1625 1626 ptr = PCIR_EXTCAP; 1627 ecap = pci_read_config(child, ptr, 4); 1628 if (ecap == 0xffffffff || ecap == 0) 1629 return (ENOENT); 1630 for (;;) { 1631 if (PCI_EXTCAP_ID(ecap) == capability) { 1632 if (capreg != NULL) 1633 *capreg = ptr; 1634 return (0); 1635 } 1636 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1637 if (ptr == 0) 1638 break; 1639 ecap = pci_read_config(child, ptr, 4); 1640 } 1641 1642 return (ENOENT); 1643 } 1644 1645 /* 1646 * Find the next requested extended capability after start and return the 1647 * offset in configuration space via the pointer provided. The function 1648 * returns 0 on success and an error code otherwise. 1649 */ 1650 int 1651 pci_find_next_extcap_method(device_t dev, device_t child, int capability, 1652 int start, int *capreg) 1653 { 1654 struct pci_devinfo *dinfo = device_get_ivars(child); 1655 pcicfgregs *cfg = &dinfo->cfg; 1656 uint32_t ecap; 1657 uint16_t ptr; 1658 1659 /* Only supported for PCI-express devices. */ 1660 if (cfg->pcie.pcie_location == 0) 1661 return (ENXIO); 1662 1663 ecap = pci_read_config(child, start, 4); 1664 KASSERT(PCI_EXTCAP_ID(ecap) == capability, 1665 ("start extended capability is not expected capability")); 1666 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1667 while (ptr != 0) { 1668 ecap = pci_read_config(child, ptr, 4); 1669 if (PCI_EXTCAP_ID(ecap) == capability) { 1670 if (capreg != NULL) 1671 *capreg = ptr; 1672 return (0); 1673 } 1674 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1675 } 1676 1677 return (ENOENT); 1678 } 1679 1680 /* 1681 * Support for MSI-X message interrupts. 1682 */ 1683 static void 1684 pci_write_msix_entry(device_t dev, u_int index, uint64_t address, uint32_t data) 1685 { 1686 struct pci_devinfo *dinfo = device_get_ivars(dev); 1687 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1688 uint32_t offset; 1689 1690 KASSERT(msix->msix_table_len > index, ("bogus index")); 1691 offset = msix->msix_table_offset + index * 16; 1692 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); 1693 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); 1694 bus_write_4(msix->msix_table_res, offset + 8, data); 1695 } 1696 1697 void 1698 pci_enable_msix_method(device_t dev, device_t child, u_int index, 1699 uint64_t address, uint32_t data) 1700 { 1701 1702 if (pci_msix_rewrite_table) { 1703 struct pci_devinfo *dinfo = device_get_ivars(child); 1704 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1705 1706 /* 1707 * Some VM hosts require MSIX to be disabled in the 1708 * control register before updating the MSIX table 1709 * entries are allowed. It is not enough to only 1710 * disable MSIX while updating a single entry. MSIX 1711 * must be disabled while updating all entries in the 1712 * table. 1713 */ 1714 pci_write_config(child, 1715 msix->msix_location + PCIR_MSIX_CTRL, 1716 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2); 1717 pci_resume_msix(child); 1718 } else 1719 pci_write_msix_entry(child, index, address, data); 1720 1721 /* Enable MSI -> HT mapping. */ 1722 pci_ht_map_msi(child, address); 1723 } 1724 1725 void 1726 pci_mask_msix(device_t dev, u_int index) 1727 { 1728 struct pci_devinfo *dinfo = device_get_ivars(dev); 1729 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1730 uint32_t offset, val; 1731 1732 KASSERT(PCI_MSIX_MSGNUM(msix->msix_ctrl) > index, ("bogus index")); 1733 offset = msix->msix_table_offset + index * 16 + 12; 1734 val = bus_read_4(msix->msix_table_res, offset); 1735 val |= PCIM_MSIX_VCTRL_MASK; 1736 1737 /* 1738 * Some devices (e.g. Samsung PM961) do not support reads of this 1739 * register, so always write the new value. 1740 */ 1741 bus_write_4(msix->msix_table_res, offset, val); 1742 } 1743 1744 void 1745 pci_unmask_msix(device_t dev, u_int index) 1746 { 1747 struct pci_devinfo *dinfo = device_get_ivars(dev); 1748 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1749 uint32_t offset, val; 1750 1751 KASSERT(PCI_MSIX_MSGNUM(msix->msix_ctrl) > index, ("bogus index")); 1752 offset = msix->msix_table_offset + index * 16 + 12; 1753 val = bus_read_4(msix->msix_table_res, offset); 1754 val &= ~PCIM_MSIX_VCTRL_MASK; 1755 1756 /* 1757 * Some devices (e.g. Samsung PM961) do not support reads of this 1758 * register, so always write the new value. 1759 */ 1760 bus_write_4(msix->msix_table_res, offset, val); 1761 } 1762 1763 int 1764 pci_pending_msix(device_t dev, u_int index) 1765 { 1766 struct pci_devinfo *dinfo = device_get_ivars(dev); 1767 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1768 uint32_t offset, bit; 1769 1770 KASSERT(msix->msix_table_len > index, ("bogus index")); 1771 offset = msix->msix_pba_offset + (index / 32) * 4; 1772 bit = 1 << index % 32; 1773 return (bus_read_4(msix->msix_pba_res, offset) & bit); 1774 } 1775 1776 /* 1777 * Restore MSI-X registers and table during resume. If MSI-X is 1778 * enabled then walk the virtual table to restore the actual MSI-X 1779 * table. 1780 */ 1781 static void 1782 pci_resume_msix(device_t dev) 1783 { 1784 struct pci_devinfo *dinfo = device_get_ivars(dev); 1785 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1786 struct msix_table_entry *mte; 1787 struct msix_vector *mv; 1788 u_int i, msgnum; 1789 1790 if (msix->msix_alloc > 0) { 1791 msgnum = PCI_MSIX_MSGNUM(msix->msix_ctrl); 1792 1793 /* First, mask all vectors. */ 1794 for (i = 0; i < msgnum; i++) 1795 pci_mask_msix(dev, i); 1796 1797 /* Second, program any messages with at least one handler. */ 1798 for (i = 0; i < msix->msix_table_len; i++) { 1799 mte = &msix->msix_table[i]; 1800 if (mte->mte_vector == 0 || mte->mte_handlers == 0) 1801 continue; 1802 mv = &msix->msix_vectors[mte->mte_vector - 1]; 1803 pci_write_msix_entry(dev, i, mv->mv_address, 1804 mv->mv_data); 1805 pci_unmask_msix(dev, i); 1806 } 1807 } 1808 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, 1809 msix->msix_ctrl, 2); 1810 } 1811 1812 /* 1813 * Attempt to allocate *count MSI-X messages. The actual number allocated is 1814 * returned in *count. After this function returns, each message will be 1815 * available to the driver as SYS_RES_IRQ resources starting at rid 1. 1816 */ 1817 int 1818 pci_alloc_msix_method(device_t dev, device_t child, int *count) 1819 { 1820 struct pci_devinfo *dinfo = device_get_ivars(child); 1821 pcicfgregs *cfg = &dinfo->cfg; 1822 struct resource_list_entry *rle; 1823 u_int actual, i, max; 1824 int error, irq; 1825 uint16_t ctrl, msgnum; 1826 1827 /* Don't let count == 0 get us into trouble. */ 1828 if (*count < 1) 1829 return (EINVAL); 1830 1831 /* If rid 0 is allocated, then fail. */ 1832 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1833 if (rle != NULL && rle->res != NULL) 1834 return (ENXIO); 1835 1836 /* Already have allocated messages? */ 1837 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1838 return (ENXIO); 1839 1840 /* If MSI-X is blacklisted for this system, fail. */ 1841 if (pci_msix_blacklisted()) 1842 return (ENXIO); 1843 1844 /* MSI-X capability present? */ 1845 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1846 return (ENODEV); 1847 1848 /* Make sure the appropriate BARs are mapped. */ 1849 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1850 cfg->msix.msix_table_bar); 1851 if (rle == NULL || rle->res == NULL || 1852 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1853 return (ENXIO); 1854 cfg->msix.msix_table_res = rle->res; 1855 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1856 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1857 cfg->msix.msix_pba_bar); 1858 if (rle == NULL || rle->res == NULL || 1859 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1860 return (ENXIO); 1861 } 1862 cfg->msix.msix_pba_res = rle->res; 1863 1864 ctrl = pci_read_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1865 2); 1866 msgnum = PCI_MSIX_MSGNUM(ctrl); 1867 if (bootverbose) 1868 device_printf(child, 1869 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1870 *count, msgnum); 1871 max = min(*count, msgnum); 1872 for (i = 0; i < max; i++) { 1873 /* Allocate a message. */ 1874 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq); 1875 if (error) { 1876 if (i == 0) 1877 return (error); 1878 break; 1879 } 1880 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1881 irq, 1); 1882 } 1883 actual = i; 1884 1885 if (bootverbose) { 1886 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1887 if (actual == 1) 1888 device_printf(child, "using IRQ %ju for MSI-X\n", 1889 rle->start); 1890 else { 1891 bool run; 1892 1893 /* 1894 * Be fancy and try to print contiguous runs of 1895 * IRQ values as ranges. 'irq' is the previous IRQ. 1896 * 'run' is true if we are in a range. 1897 */ 1898 device_printf(child, "using IRQs %ju", rle->start); 1899 irq = rle->start; 1900 run = false; 1901 for (i = 1; i < actual; i++) { 1902 rle = resource_list_find(&dinfo->resources, 1903 SYS_RES_IRQ, i + 1); 1904 1905 /* Still in a run? */ 1906 if (rle->start == irq + 1) { 1907 run = true; 1908 irq++; 1909 continue; 1910 } 1911 1912 /* Finish previous range. */ 1913 if (run) { 1914 printf("-%d", irq); 1915 run = false; 1916 } 1917 1918 /* Start new range. */ 1919 printf(",%ju", rle->start); 1920 irq = rle->start; 1921 } 1922 1923 /* Unfinished range? */ 1924 if (run) 1925 printf("-%d", irq); 1926 printf(" for MSI-X\n"); 1927 } 1928 } 1929 1930 /* 1931 * Mask all vectors. Note that the message index assertion in 1932 * pci_mask_msix requires msix_ctrl to be set. 1933 */ 1934 cfg->msix.msix_ctrl = ctrl; 1935 for (i = 0; i < msgnum; i++) 1936 pci_mask_msix(child, i); 1937 1938 /* Allocate and initialize vector data and virtual table. */ 1939 cfg->msix.msix_vectors = mallocarray(actual, sizeof(struct msix_vector), 1940 M_DEVBUF, M_WAITOK | M_ZERO); 1941 cfg->msix.msix_table = mallocarray(actual, 1942 sizeof(struct msix_table_entry), M_DEVBUF, M_WAITOK | M_ZERO); 1943 for (i = 0; i < actual; i++) { 1944 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1945 cfg->msix.msix_vectors[i].mv_irq = rle->start; 1946 cfg->msix.msix_table[i].mte_vector = i + 1; 1947 } 1948 1949 /* Update control register to enable MSI-X. */ 1950 ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1951 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1952 ctrl, 2); 1953 cfg->msix.msix_ctrl = ctrl; 1954 1955 /* Update counts of alloc'd messages. */ 1956 cfg->msix.msix_alloc = actual; 1957 cfg->msix.msix_table_len = actual; 1958 *count = actual; 1959 return (0); 1960 } 1961 1962 /* 1963 * By default, pci_alloc_msix() will assign the allocated IRQ 1964 * resources consecutively to the first N messages in the MSI-X table. 1965 * However, device drivers may want to use different layouts if they 1966 * either receive fewer messages than they asked for, or they wish to 1967 * populate the MSI-X table sparsely. This method allows the driver 1968 * to specify what layout it wants. It must be called after a 1969 * successful pci_alloc_msix() but before any of the associated 1970 * SYS_RES_IRQ resources are allocated via bus_alloc_resource(). 1971 * 1972 * The 'vectors' array contains 'count' message vectors. The array 1973 * maps directly to the MSI-X table in that index 0 in the array 1974 * specifies the vector for the first message in the MSI-X table, etc. 1975 * The vector value in each array index can either be 0 to indicate 1976 * that no vector should be assigned to a message slot, or it can be a 1977 * number from 1 to N (where N is the count returned from a 1978 * succcessful call to pci_alloc_msix()) to indicate which message 1979 * vector (IRQ) to be used for the corresponding message. 1980 * 1981 * On successful return, each message with a non-zero vector will have 1982 * an associated SYS_RES_IRQ whose rid is equal to the array index + 1983 * 1. Additionally, if any of the IRQs allocated via the previous 1984 * call to pci_alloc_msix() are not used in the mapping, those IRQs 1985 * will be freed back to the system automatically. 1986 * 1987 * For example, suppose a driver has a MSI-X table with 6 messages and 1988 * asks for 6 messages, but pci_alloc_msix() only returns a count of 1989 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and 1990 * C. After the call to pci_alloc_msix(), the device will be setup to 1991 * have an MSI-X table of ABC--- (where - means no vector assigned). 1992 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 }, 1993 * then the MSI-X table will look like A-AB-B, and the 'C' vector will 1994 * be freed back to the system. This device will also have valid 1995 * SYS_RES_IRQ rids of 1, 3, 4, and 6. 1996 * 1997 * In any case, the SYS_RES_IRQ rid X will always map to the message 1998 * at MSI-X table index X - 1 and will only be valid if a vector is 1999 * assigned to that table entry. 2000 */ 2001 int 2002 pci_remap_msix_method(device_t dev, device_t child, int count, 2003 const u_int *vectors) 2004 { 2005 struct pci_devinfo *dinfo = device_get_ivars(child); 2006 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2007 struct resource_list_entry *rle; 2008 u_int i, irq, j; 2009 bool *used; 2010 2011 /* 2012 * Have to have at least one message in the table but the 2013 * table can't be bigger than the actual MSI-X table in the 2014 * device. 2015 */ 2016 if (count < 1 || count > PCI_MSIX_MSGNUM(msix->msix_ctrl)) 2017 return (EINVAL); 2018 2019 /* Sanity check the vectors. */ 2020 for (i = 0; i < count; i++) 2021 if (vectors[i] > msix->msix_alloc) 2022 return (EINVAL); 2023 2024 /* 2025 * Make sure there aren't any holes in the vectors to be used. 2026 * It's a big pain to support it, and it doesn't really make 2027 * sense anyway. Also, at least one vector must be used. 2028 */ 2029 used = mallocarray(msix->msix_alloc, sizeof(*used), M_DEVBUF, M_WAITOK | 2030 M_ZERO); 2031 for (i = 0; i < count; i++) 2032 if (vectors[i] != 0) 2033 used[vectors[i] - 1] = true; 2034 for (i = 0; i < msix->msix_alloc - 1; i++) 2035 if (!used[i] && used[i + 1]) { 2036 free(used, M_DEVBUF); 2037 return (EINVAL); 2038 } 2039 if (!used[0]) { 2040 free(used, M_DEVBUF); 2041 return (EINVAL); 2042 } 2043 2044 /* Make sure none of the resources are allocated. */ 2045 for (i = 0; i < msix->msix_table_len; i++) { 2046 if (msix->msix_table[i].mte_vector == 0) 2047 continue; 2048 if (msix->msix_table[i].mte_handlers > 0) { 2049 free(used, M_DEVBUF); 2050 return (EBUSY); 2051 } 2052 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2053 KASSERT(rle != NULL, ("missing resource")); 2054 if (rle->res != NULL) { 2055 free(used, M_DEVBUF); 2056 return (EBUSY); 2057 } 2058 } 2059 2060 /* Free the existing resource list entries. */ 2061 for (i = 0; i < msix->msix_table_len; i++) { 2062 if (msix->msix_table[i].mte_vector == 0) 2063 continue; 2064 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2065 } 2066 2067 /* 2068 * Build the new virtual table keeping track of which vectors are 2069 * used. 2070 */ 2071 free(msix->msix_table, M_DEVBUF); 2072 msix->msix_table = mallocarray(count, sizeof(struct msix_table_entry), 2073 M_DEVBUF, M_WAITOK | M_ZERO); 2074 for (i = 0; i < count; i++) 2075 msix->msix_table[i].mte_vector = vectors[i]; 2076 msix->msix_table_len = count; 2077 2078 /* Free any unused IRQs and resize the vectors array if necessary. */ 2079 j = msix->msix_alloc - 1; 2080 if (!used[j]) { 2081 struct msix_vector *vec; 2082 2083 while (!used[j]) { 2084 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2085 msix->msix_vectors[j].mv_irq); 2086 j--; 2087 } 2088 vec = mallocarray(j + 1, sizeof(struct msix_vector), M_DEVBUF, 2089 M_WAITOK); 2090 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * 2091 (j + 1)); 2092 free(msix->msix_vectors, M_DEVBUF); 2093 msix->msix_vectors = vec; 2094 msix->msix_alloc = j + 1; 2095 } 2096 free(used, M_DEVBUF); 2097 2098 /* Map the IRQs onto the rids. */ 2099 for (i = 0; i < count; i++) { 2100 if (vectors[i] == 0) 2101 continue; 2102 irq = msix->msix_vectors[vectors[i] - 1].mv_irq; 2103 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 2104 irq, 1); 2105 } 2106 2107 if (bootverbose) { 2108 device_printf(child, "Remapped MSI-X IRQs as: "); 2109 for (i = 0; i < count; i++) { 2110 if (i != 0) 2111 printf(", "); 2112 if (vectors[i] == 0) 2113 printf("---"); 2114 else 2115 printf("%d", 2116 msix->msix_vectors[vectors[i] - 1].mv_irq); 2117 } 2118 printf("\n"); 2119 } 2120 2121 return (0); 2122 } 2123 2124 static int 2125 pci_release_msix(device_t dev, device_t child) 2126 { 2127 struct pci_devinfo *dinfo = device_get_ivars(child); 2128 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2129 struct resource_list_entry *rle; 2130 u_int i; 2131 2132 /* Do we have any messages to release? */ 2133 if (msix->msix_alloc == 0) 2134 return (ENODEV); 2135 2136 /* Make sure none of the resources are allocated. */ 2137 for (i = 0; i < msix->msix_table_len; i++) { 2138 if (msix->msix_table[i].mte_vector == 0) 2139 continue; 2140 if (msix->msix_table[i].mte_handlers > 0) 2141 return (EBUSY); 2142 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2143 KASSERT(rle != NULL, ("missing resource")); 2144 if (rle->res != NULL) 2145 return (EBUSY); 2146 } 2147 2148 /* Update control register to disable MSI-X. */ 2149 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 2150 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, 2151 msix->msix_ctrl, 2); 2152 2153 /* Free the resource list entries. */ 2154 for (i = 0; i < msix->msix_table_len; i++) { 2155 if (msix->msix_table[i].mte_vector == 0) 2156 continue; 2157 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2158 } 2159 free(msix->msix_table, M_DEVBUF); 2160 msix->msix_table_len = 0; 2161 2162 /* Release the IRQs. */ 2163 for (i = 0; i < msix->msix_alloc; i++) 2164 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2165 msix->msix_vectors[i].mv_irq); 2166 free(msix->msix_vectors, M_DEVBUF); 2167 msix->msix_alloc = 0; 2168 return (0); 2169 } 2170 2171 /* 2172 * Return the max supported MSI-X messages this device supports. 2173 * Basically, assuming the MD code can alloc messages, this function 2174 * should return the maximum value that pci_alloc_msix() can return. 2175 * Thus, it is subject to the tunables, etc. 2176 */ 2177 int 2178 pci_msix_count_method(device_t dev, device_t child) 2179 { 2180 struct pci_devinfo *dinfo = device_get_ivars(child); 2181 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2182 uint16_t ctrl; 2183 2184 if (pci_do_msix && msix->msix_location != 0) { 2185 ctrl = pci_read_config(child, msix->msix_location + 2186 PCIR_MSI_CTRL, 2); 2187 return (PCI_MSIX_MSGNUM(ctrl)); 2188 } 2189 return (0); 2190 } 2191 2192 int 2193 pci_msix_pba_bar_method(device_t dev, device_t child) 2194 { 2195 struct pci_devinfo *dinfo = device_get_ivars(child); 2196 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2197 2198 if (pci_do_msix && msix->msix_location != 0) 2199 return (msix->msix_pba_bar); 2200 return (-1); 2201 } 2202 2203 int 2204 pci_msix_table_bar_method(device_t dev, device_t child) 2205 { 2206 struct pci_devinfo *dinfo = device_get_ivars(child); 2207 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2208 2209 if (pci_do_msix && msix->msix_location != 0) 2210 return (msix->msix_table_bar); 2211 return (-1); 2212 } 2213 2214 /* 2215 * HyperTransport MSI mapping control 2216 */ 2217 void 2218 pci_ht_map_msi(device_t dev, uint64_t addr) 2219 { 2220 struct pci_devinfo *dinfo = device_get_ivars(dev); 2221 struct pcicfg_ht *ht = &dinfo->cfg.ht; 2222 2223 if (!ht->ht_msimap) 2224 return; 2225 2226 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && 2227 ht->ht_msiaddr >> 20 == addr >> 20) { 2228 /* Enable MSI -> HT mapping. */ 2229 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 2230 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2231 ht->ht_msictrl, 2); 2232 } 2233 2234 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { 2235 /* Disable MSI -> HT mapping. */ 2236 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; 2237 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2238 ht->ht_msictrl, 2); 2239 } 2240 } 2241 2242 int 2243 pci_get_relaxed_ordering_enabled(device_t dev) 2244 { 2245 struct pci_devinfo *dinfo = device_get_ivars(dev); 2246 int cap; 2247 uint16_t val; 2248 2249 cap = dinfo->cfg.pcie.pcie_location; 2250 if (cap == 0) 2251 return (0); 2252 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2253 val &= PCIEM_CTL_RELAXED_ORD_ENABLE; 2254 return (val != 0); 2255 } 2256 2257 int 2258 pci_get_max_payload(device_t dev) 2259 { 2260 struct pci_devinfo *dinfo = device_get_ivars(dev); 2261 int cap; 2262 uint16_t val; 2263 2264 cap = dinfo->cfg.pcie.pcie_location; 2265 if (cap == 0) 2266 return (0); 2267 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2268 val &= PCIEM_CTL_MAX_PAYLOAD; 2269 val >>= 5; 2270 return (1 << (val + 7)); 2271 } 2272 2273 int 2274 pci_get_max_read_req(device_t dev) 2275 { 2276 struct pci_devinfo *dinfo = device_get_ivars(dev); 2277 int cap; 2278 uint16_t val; 2279 2280 cap = dinfo->cfg.pcie.pcie_location; 2281 if (cap == 0) 2282 return (0); 2283 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2284 val &= PCIEM_CTL_MAX_READ_REQUEST; 2285 val >>= 12; 2286 return (1 << (val + 7)); 2287 } 2288 2289 int 2290 pci_set_max_read_req(device_t dev, int size) 2291 { 2292 struct pci_devinfo *dinfo = device_get_ivars(dev); 2293 int cap; 2294 uint16_t val; 2295 2296 cap = dinfo->cfg.pcie.pcie_location; 2297 if (cap == 0) 2298 return (0); 2299 if (size < 128) 2300 size = 128; 2301 if (size > 4096) 2302 size = 4096; 2303 size = (1 << (fls(size) - 1)); 2304 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2305 val &= ~PCIEM_CTL_MAX_READ_REQUEST; 2306 val |= (fls(size) - 8) << 12; 2307 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2); 2308 return (size); 2309 } 2310 2311 uint32_t 2312 pcie_read_config(device_t dev, int reg, int width) 2313 { 2314 struct pci_devinfo *dinfo = device_get_ivars(dev); 2315 int cap; 2316 2317 cap = dinfo->cfg.pcie.pcie_location; 2318 if (cap == 0) { 2319 if (width == 2) 2320 return (0xffff); 2321 return (0xffffffff); 2322 } 2323 2324 return (pci_read_config(dev, cap + reg, width)); 2325 } 2326 2327 void 2328 pcie_write_config(device_t dev, int reg, uint32_t value, int width) 2329 { 2330 struct pci_devinfo *dinfo = device_get_ivars(dev); 2331 int cap; 2332 2333 cap = dinfo->cfg.pcie.pcie_location; 2334 if (cap == 0) 2335 return; 2336 pci_write_config(dev, cap + reg, value, width); 2337 } 2338 2339 /* 2340 * Adjusts a PCI-e capability register by clearing the bits in mask 2341 * and setting the bits in (value & mask). Bits not set in mask are 2342 * not adjusted. 2343 * 2344 * Returns the old value on success or all ones on failure. 2345 */ 2346 uint32_t 2347 pcie_adjust_config(device_t dev, int reg, uint32_t mask, uint32_t value, 2348 int width) 2349 { 2350 struct pci_devinfo *dinfo = device_get_ivars(dev); 2351 uint32_t old, new; 2352 int cap; 2353 2354 cap = dinfo->cfg.pcie.pcie_location; 2355 if (cap == 0) { 2356 if (width == 2) 2357 return (0xffff); 2358 return (0xffffffff); 2359 } 2360 2361 old = pci_read_config(dev, cap + reg, width); 2362 new = old & ~mask; 2363 new |= (value & mask); 2364 pci_write_config(dev, cap + reg, new, width); 2365 return (old); 2366 } 2367 2368 /* 2369 * Support for MSI message signalled interrupts. 2370 */ 2371 void 2372 pci_enable_msi_method(device_t dev, device_t child, uint64_t address, 2373 uint16_t data) 2374 { 2375 struct pci_devinfo *dinfo = device_get_ivars(child); 2376 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2377 2378 /* Write data and address values. */ 2379 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, 2380 address & 0xffffffff, 4); 2381 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2382 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, 2383 address >> 32, 4); 2384 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, 2385 data, 2); 2386 } else 2387 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, 2388 2); 2389 2390 /* Enable MSI in the control register. */ 2391 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 2392 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2393 msi->msi_ctrl, 2); 2394 2395 /* Enable MSI -> HT mapping. */ 2396 pci_ht_map_msi(child, address); 2397 } 2398 2399 void 2400 pci_disable_msi_method(device_t dev, device_t child) 2401 { 2402 struct pci_devinfo *dinfo = device_get_ivars(child); 2403 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2404 2405 /* Disable MSI -> HT mapping. */ 2406 pci_ht_map_msi(child, 0); 2407 2408 /* Disable MSI in the control register. */ 2409 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; 2410 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2411 msi->msi_ctrl, 2); 2412 } 2413 2414 /* 2415 * Restore MSI registers during resume. If MSI is enabled then 2416 * restore the data and address registers in addition to the control 2417 * register. 2418 */ 2419 static void 2420 pci_resume_msi(device_t dev) 2421 { 2422 struct pci_devinfo *dinfo = device_get_ivars(dev); 2423 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2424 uint64_t address; 2425 uint16_t data; 2426 2427 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 2428 address = msi->msi_addr; 2429 data = msi->msi_data; 2430 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 2431 address & 0xffffffff, 4); 2432 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2433 pci_write_config(dev, msi->msi_location + 2434 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 2435 pci_write_config(dev, msi->msi_location + 2436 PCIR_MSI_DATA_64BIT, data, 2); 2437 } else 2438 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, 2439 data, 2); 2440 } 2441 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 2442 2); 2443 } 2444 2445 static int 2446 pci_remap_intr_method(device_t bus, device_t dev, u_int irq) 2447 { 2448 struct pci_devinfo *dinfo = device_get_ivars(dev); 2449 pcicfgregs *cfg = &dinfo->cfg; 2450 struct resource_list_entry *rle; 2451 struct msix_table_entry *mte; 2452 struct msix_vector *mv; 2453 uint64_t addr; 2454 uint32_t data; 2455 u_int i, j; 2456 int error; 2457 2458 /* 2459 * Handle MSI first. We try to find this IRQ among our list 2460 * of MSI IRQs. If we find it, we request updated address and 2461 * data registers and apply the results. 2462 */ 2463 if (cfg->msi.msi_alloc > 0) { 2464 /* If we don't have any active handlers, nothing to do. */ 2465 if (cfg->msi.msi_handlers == 0) 2466 return (0); 2467 for (i = 0; i < cfg->msi.msi_alloc; i++) { 2468 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 2469 i + 1); 2470 if (rle->start == irq) { 2471 error = PCIB_MAP_MSI(device_get_parent(bus), 2472 dev, irq, &addr, &data); 2473 if (error) 2474 return (error); 2475 pci_disable_msi(dev); 2476 dinfo->cfg.msi.msi_addr = addr; 2477 dinfo->cfg.msi.msi_data = data; 2478 pci_enable_msi(dev, addr, data); 2479 return (0); 2480 } 2481 } 2482 return (ENOENT); 2483 } 2484 2485 /* 2486 * For MSI-X, we check to see if we have this IRQ. If we do, 2487 * we request the updated mapping info. If that works, we go 2488 * through all the slots that use this IRQ and update them. 2489 */ 2490 if (cfg->msix.msix_alloc > 0) { 2491 bool found = false; 2492 2493 for (i = 0; i < cfg->msix.msix_alloc; i++) { 2494 mv = &cfg->msix.msix_vectors[i]; 2495 if (mv->mv_irq == irq) { 2496 error = PCIB_MAP_MSI(device_get_parent(bus), 2497 dev, irq, &addr, &data); 2498 if (error) 2499 return (error); 2500 mv->mv_address = addr; 2501 mv->mv_data = data; 2502 for (j = 0; j < cfg->msix.msix_table_len; j++) { 2503 mte = &cfg->msix.msix_table[j]; 2504 if (mte->mte_vector != i + 1) 2505 continue; 2506 if (mte->mte_handlers == 0) 2507 continue; 2508 pci_mask_msix(dev, j); 2509 pci_enable_msix(dev, j, addr, data); 2510 pci_unmask_msix(dev, j); 2511 } 2512 found = true; 2513 } 2514 } 2515 return (found ? 0 : ENOENT); 2516 } 2517 2518 return (ENOENT); 2519 } 2520 2521 /* 2522 * Returns true if the specified device is blacklisted because MSI 2523 * doesn't work. 2524 */ 2525 int 2526 pci_msi_device_blacklisted(device_t dev) 2527 { 2528 2529 if (!pci_honor_msi_blacklist) 2530 return (0); 2531 2532 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI)); 2533 } 2534 2535 /* 2536 * Determine if MSI is blacklisted globally on this system. Currently, 2537 * we just check for blacklisted chipsets as represented by the 2538 * host-PCI bridge at device 0:0:0. In the future, it may become 2539 * necessary to check other system attributes, such as the kenv values 2540 * that give the motherboard manufacturer and model number. 2541 */ 2542 static int 2543 pci_msi_blacklisted(void) 2544 { 2545 device_t dev; 2546 2547 if (!pci_honor_msi_blacklist) 2548 return (0); 2549 2550 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ 2551 if (!(pcie_chipset || pcix_chipset)) { 2552 if (vm_guest != VM_GUEST_NO) { 2553 /* 2554 * Whitelist older chipsets in virtual 2555 * machines known to support MSI. 2556 */ 2557 dev = pci_find_bsf(0, 0, 0); 2558 if (dev != NULL) 2559 return (!pci_has_quirk(pci_get_devid(dev), 2560 PCI_QUIRK_ENABLE_MSI_VM)); 2561 } 2562 return (1); 2563 } 2564 2565 dev = pci_find_bsf(0, 0, 0); 2566 if (dev != NULL) 2567 return (pci_msi_device_blacklisted(dev)); 2568 return (0); 2569 } 2570 2571 /* 2572 * Returns true if the specified device is blacklisted because MSI-X 2573 * doesn't work. Note that this assumes that if MSI doesn't work, 2574 * MSI-X doesn't either. 2575 */ 2576 int 2577 pci_msix_device_blacklisted(device_t dev) 2578 { 2579 2580 if (!pci_honor_msi_blacklist) 2581 return (0); 2582 2583 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX)) 2584 return (1); 2585 2586 return (pci_msi_device_blacklisted(dev)); 2587 } 2588 2589 /* 2590 * Determine if MSI-X is blacklisted globally on this system. If MSI 2591 * is blacklisted, assume that MSI-X is as well. Check for additional 2592 * chipsets where MSI works but MSI-X does not. 2593 */ 2594 static int 2595 pci_msix_blacklisted(void) 2596 { 2597 device_t dev; 2598 2599 if (!pci_honor_msi_blacklist) 2600 return (0); 2601 2602 dev = pci_find_bsf(0, 0, 0); 2603 if (dev != NULL && pci_has_quirk(pci_get_devid(dev), 2604 PCI_QUIRK_DISABLE_MSIX)) 2605 return (1); 2606 2607 return (pci_msi_blacklisted()); 2608 } 2609 2610 /* 2611 * Attempt to allocate *count MSI messages. The actual number allocated is 2612 * returned in *count. After this function returns, each message will be 2613 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 2614 */ 2615 int 2616 pci_alloc_msi_method(device_t dev, device_t child, int *count) 2617 { 2618 struct pci_devinfo *dinfo = device_get_ivars(child); 2619 pcicfgregs *cfg = &dinfo->cfg; 2620 struct resource_list_entry *rle; 2621 u_int actual, i; 2622 int error, irqs[32]; 2623 uint16_t ctrl, msgnum; 2624 2625 /* Don't let count == 0 get us into trouble. */ 2626 if (*count < 1) 2627 return (EINVAL); 2628 2629 /* If rid 0 is allocated, then fail. */ 2630 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 2631 if (rle != NULL && rle->res != NULL) 2632 return (ENXIO); 2633 2634 /* Already have allocated messages? */ 2635 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 2636 return (ENXIO); 2637 2638 /* If MSI is blacklisted for this system, fail. */ 2639 if (pci_msi_blacklisted()) 2640 return (ENXIO); 2641 2642 /* MSI capability present? */ 2643 if (cfg->msi.msi_location == 0 || !pci_do_msi) 2644 return (ENODEV); 2645 2646 ctrl = pci_read_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, 2); 2647 msgnum = PCI_MSI_MSGNUM(ctrl); 2648 if (bootverbose) 2649 device_printf(child, 2650 "attempting to allocate %d MSI vectors (%u supported)\n", 2651 *count, msgnum); 2652 2653 /* Don't ask for more than the device supports. */ 2654 actual = min(*count, msgnum); 2655 2656 /* Don't ask for more than 32 messages. */ 2657 actual = min(actual, 32); 2658 2659 /* MSI requires power of 2 number of messages. */ 2660 if (!powerof2(actual)) 2661 return (EINVAL); 2662 2663 for (;;) { 2664 /* Try to allocate N messages. */ 2665 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 2666 actual, irqs); 2667 if (error == 0) 2668 break; 2669 if (actual == 1) 2670 return (error); 2671 2672 /* Try N / 2. */ 2673 actual >>= 1; 2674 } 2675 2676 /* 2677 * We now have N actual messages mapped onto SYS_RES_IRQ 2678 * resources in the irqs[] array, so add new resources 2679 * starting at rid 1. 2680 */ 2681 for (i = 0; i < actual; i++) 2682 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 2683 irqs[i], irqs[i], 1); 2684 2685 if (bootverbose) { 2686 if (actual == 1) 2687 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 2688 else { 2689 bool run; 2690 2691 /* 2692 * Be fancy and try to print contiguous runs 2693 * of IRQ values as ranges. 'run' is true if 2694 * we are in a range. 2695 */ 2696 device_printf(child, "using IRQs %d", irqs[0]); 2697 run = false; 2698 for (i = 1; i < actual; i++) { 2699 /* Still in a run? */ 2700 if (irqs[i] == irqs[i - 1] + 1) { 2701 run = true; 2702 continue; 2703 } 2704 2705 /* Finish previous range. */ 2706 if (run) { 2707 printf("-%d", irqs[i - 1]); 2708 run = false; 2709 } 2710 2711 /* Start new range. */ 2712 printf(",%d", irqs[i]); 2713 } 2714 2715 /* Unfinished range? */ 2716 if (run) 2717 printf("-%d", irqs[actual - 1]); 2718 printf(" for MSI\n"); 2719 } 2720 } 2721 2722 /* Update control register with actual count. */ 2723 ctrl &= ~PCIM_MSICTRL_MME_MASK; 2724 ctrl |= (ffs(actual) - 1) << 4; 2725 cfg->msi.msi_ctrl = ctrl; 2726 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 2727 2728 /* Update counts of alloc'd messages. */ 2729 cfg->msi.msi_alloc = actual; 2730 cfg->msi.msi_handlers = 0; 2731 *count = actual; 2732 return (0); 2733 } 2734 2735 /* Release the MSI messages associated with this device. */ 2736 int 2737 pci_release_msi_method(device_t dev, device_t child) 2738 { 2739 struct pci_devinfo *dinfo = device_get_ivars(child); 2740 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2741 struct resource_list_entry *rle; 2742 u_int i, irqs[32]; 2743 int error; 2744 2745 /* Try MSI-X first. */ 2746 error = pci_release_msix(dev, child); 2747 if (error != ENODEV) 2748 return (error); 2749 2750 /* Do we have any messages to release? */ 2751 if (msi->msi_alloc == 0) 2752 return (ENODEV); 2753 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); 2754 2755 /* Make sure none of the resources are allocated. */ 2756 if (msi->msi_handlers > 0) 2757 return (EBUSY); 2758 for (i = 0; i < msi->msi_alloc; i++) { 2759 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2760 KASSERT(rle != NULL, ("missing MSI resource")); 2761 if (rle->res != NULL) 2762 return (EBUSY); 2763 irqs[i] = rle->start; 2764 } 2765 2766 /* Update control register with 0 count. */ 2767 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), 2768 ("%s: MSI still enabled", __func__)); 2769 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; 2770 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2771 msi->msi_ctrl, 2); 2772 2773 /* Release the messages. */ 2774 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); 2775 for (i = 0; i < msi->msi_alloc; i++) 2776 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2777 2778 /* Update alloc count. */ 2779 msi->msi_alloc = 0; 2780 msi->msi_addr = 0; 2781 msi->msi_data = 0; 2782 return (0); 2783 } 2784 2785 /* 2786 * Return the max supported MSI messages this device supports. 2787 * Basically, assuming the MD code can alloc messages, this function 2788 * should return the maximum value that pci_alloc_msi() can return. 2789 * Thus, it is subject to the tunables, etc. 2790 */ 2791 int 2792 pci_msi_count_method(device_t dev, device_t child) 2793 { 2794 struct pci_devinfo *dinfo = device_get_ivars(child); 2795 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2796 uint16_t ctrl; 2797 2798 if (pci_do_msi && msi->msi_location != 0) { 2799 ctrl = pci_read_config(child, msi->msi_location + PCIR_MSI_CTRL, 2800 2); 2801 return (PCI_MSI_MSGNUM(ctrl)); 2802 } 2803 return (0); 2804 } 2805 2806 /* free pcicfgregs structure and all depending data structures */ 2807 2808 int 2809 pci_freecfg(struct pci_devinfo *dinfo) 2810 { 2811 struct devlist *devlist_head; 2812 struct pci_map *pm, *next; 2813 2814 devlist_head = &pci_devq; 2815 2816 if (dinfo->cfg.vpd.vpd_reg) 2817 vpd_free(&dinfo->cfg.vpd); 2818 2819 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { 2820 free(pm, M_DEVBUF); 2821 } 2822 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 2823 free(dinfo, M_DEVBUF); 2824 2825 /* increment the generation count */ 2826 pci_generation++; 2827 2828 /* we're losing one device */ 2829 pci_numdevs--; 2830 return (0); 2831 } 2832 2833 /* 2834 * PCI power manangement 2835 */ 2836 int 2837 pci_set_powerstate_method(device_t dev, device_t child, int state) 2838 { 2839 struct pci_devinfo *dinfo = device_get_ivars(child); 2840 pcicfgregs *cfg = &dinfo->cfg; 2841 uint16_t status; 2842 int oldstate, highest, delay; 2843 2844 if (cfg->pp.pp_location == 0) 2845 return (EOPNOTSUPP); 2846 2847 /* 2848 * Optimize a no state change request away. While it would be OK to 2849 * write to the hardware in theory, some devices have shown odd 2850 * behavior when going from D3 -> D3. 2851 */ 2852 oldstate = pci_get_powerstate(child); 2853 if (oldstate == state) 2854 return (0); 2855 2856 /* 2857 * The PCI power management specification states that after a state 2858 * transition between PCI power states, system software must 2859 * guarantee a minimal delay before the function accesses the device. 2860 * Compute the worst case delay that we need to guarantee before we 2861 * access the device. Many devices will be responsive much more 2862 * quickly than this delay, but there are some that don't respond 2863 * instantly to state changes. Transitions to/from D3 state require 2864 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 2865 * is done below with DELAY rather than a sleeper function because 2866 * this function can be called from contexts where we cannot sleep. 2867 */ 2868 highest = (oldstate > state) ? oldstate : state; 2869 if (highest == PCI_POWERSTATE_D3) 2870 delay = 10000; 2871 else if (highest == PCI_POWERSTATE_D2) 2872 delay = 200; 2873 else 2874 delay = 0; 2875 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_location + 2876 PCIR_POWER_STATUS, 2) & ~PCIM_PSTAT_DMASK; 2877 switch (state) { 2878 case PCI_POWERSTATE_D0: 2879 status |= PCIM_PSTAT_D0; 2880 break; 2881 case PCI_POWERSTATE_D1: 2882 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 2883 return (EOPNOTSUPP); 2884 status |= PCIM_PSTAT_D1; 2885 break; 2886 case PCI_POWERSTATE_D2: 2887 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 2888 return (EOPNOTSUPP); 2889 status |= PCIM_PSTAT_D2; 2890 break; 2891 case PCI_POWERSTATE_D3: 2892 status |= PCIM_PSTAT_D3; 2893 break; 2894 default: 2895 return (EINVAL); 2896 } 2897 2898 if (bootverbose) 2899 pci_printf(cfg, "Transition from %s to %s\n", 2900 pci_powerstate_to_str(oldstate), 2901 pci_powerstate_to_str(state)); 2902 2903 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_location + PCIR_POWER_STATUS, 2904 status, 2); 2905 if (delay) 2906 DELAY(delay); 2907 return (0); 2908 } 2909 2910 int 2911 pci_get_powerstate_method(device_t dev, device_t child) 2912 { 2913 struct pci_devinfo *dinfo = device_get_ivars(child); 2914 pcicfgregs *cfg = &dinfo->cfg; 2915 uint16_t status; 2916 int result; 2917 2918 if (cfg->pp.pp_location != 0) { 2919 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_location + 2920 PCIR_POWER_STATUS, 2); 2921 switch (status & PCIM_PSTAT_DMASK) { 2922 case PCIM_PSTAT_D0: 2923 result = PCI_POWERSTATE_D0; 2924 break; 2925 case PCIM_PSTAT_D1: 2926 result = PCI_POWERSTATE_D1; 2927 break; 2928 case PCIM_PSTAT_D2: 2929 result = PCI_POWERSTATE_D2; 2930 break; 2931 case PCIM_PSTAT_D3: 2932 result = PCI_POWERSTATE_D3; 2933 break; 2934 default: 2935 result = PCI_POWERSTATE_UNKNOWN; 2936 break; 2937 } 2938 } else { 2939 /* No support, device is always at D0 */ 2940 result = PCI_POWERSTATE_D0; 2941 } 2942 return (result); 2943 } 2944 2945 /* Clear any active PME# and disable PME# generation. */ 2946 void 2947 pci_clear_pme(device_t dev) 2948 { 2949 struct pci_devinfo *dinfo = device_get_ivars(dev); 2950 pcicfgregs *cfg = &dinfo->cfg; 2951 uint16_t status; 2952 2953 if (cfg->pp.pp_location != 0) { 2954 status = pci_read_config(dev, dinfo->cfg.pp.pp_location + 2955 PCIR_POWER_STATUS, 2); 2956 status &= ~PCIM_PSTAT_PMEENABLE; 2957 status |= PCIM_PSTAT_PME; 2958 pci_write_config(dev, dinfo->cfg.pp.pp_location + 2959 PCIR_POWER_STATUS, status, 2); 2960 } 2961 } 2962 2963 /* Clear any active PME# and enable PME# generation. */ 2964 void 2965 pci_enable_pme(device_t dev) 2966 { 2967 struct pci_devinfo *dinfo = device_get_ivars(dev); 2968 pcicfgregs *cfg = &dinfo->cfg; 2969 uint16_t status; 2970 2971 if (cfg->pp.pp_location != 0) { 2972 status = pci_read_config(dev, dinfo->cfg.pp.pp_location + 2973 PCIR_POWER_STATUS, 2); 2974 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2975 pci_write_config(dev, dinfo->cfg.pp.pp_location + 2976 PCIR_POWER_STATUS, status, 2); 2977 } 2978 } 2979 2980 bool 2981 pci_has_pm(device_t dev) 2982 { 2983 struct pci_devinfo *dinfo = device_get_ivars(dev); 2984 pcicfgregs *cfg = &dinfo->cfg; 2985 2986 return (cfg->pp.pp_location != 0); 2987 } 2988 2989 /* 2990 * Some convenience functions for PCI device drivers. 2991 */ 2992 2993 static __inline void 2994 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 2995 { 2996 uint16_t command; 2997 2998 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2999 command |= bit; 3000 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 3001 } 3002 3003 static __inline void 3004 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 3005 { 3006 uint16_t command; 3007 3008 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 3009 command &= ~bit; 3010 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 3011 } 3012 3013 int 3014 pci_enable_busmaster_method(device_t dev, device_t child) 3015 { 3016 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 3017 return (0); 3018 } 3019 3020 int 3021 pci_disable_busmaster_method(device_t dev, device_t child) 3022 { 3023 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 3024 return (0); 3025 } 3026 3027 int 3028 pci_enable_io_method(device_t dev, device_t child, int space) 3029 { 3030 uint16_t bit; 3031 3032 switch(space) { 3033 case SYS_RES_IOPORT: 3034 bit = PCIM_CMD_PORTEN; 3035 break; 3036 case SYS_RES_MEMORY: 3037 bit = PCIM_CMD_MEMEN; 3038 break; 3039 default: 3040 return (EINVAL); 3041 } 3042 pci_set_command_bit(dev, child, bit); 3043 return (0); 3044 } 3045 3046 int 3047 pci_disable_io_method(device_t dev, device_t child, int space) 3048 { 3049 uint16_t bit; 3050 3051 switch(space) { 3052 case SYS_RES_IOPORT: 3053 bit = PCIM_CMD_PORTEN; 3054 break; 3055 case SYS_RES_MEMORY: 3056 bit = PCIM_CMD_MEMEN; 3057 break; 3058 default: 3059 return (EINVAL); 3060 } 3061 pci_clear_command_bit(dev, child, bit); 3062 return (0); 3063 } 3064 3065 /* 3066 * New style pci driver. Parent device is either a pci-host-bridge or a 3067 * pci-pci-bridge. Both kinds are represented by instances of pcib. 3068 */ 3069 3070 void 3071 pci_print_verbose(struct pci_devinfo *dinfo) 3072 { 3073 3074 if (bootverbose) { 3075 pcicfgregs *cfg = &dinfo->cfg; 3076 3077 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 3078 cfg->vendor, cfg->device, cfg->revid); 3079 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n", 3080 cfg->domain, cfg->bus, cfg->slot, cfg->func); 3081 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 3082 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 3083 cfg->mfdev); 3084 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 3085 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 3086 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 3087 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 3088 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 3089 if (cfg->intpin > 0) 3090 printf("\tintpin=%c, irq=%d\n", 3091 cfg->intpin +'a' -1, cfg->intline); 3092 if (cfg->pp.pp_location) { 3093 uint16_t status; 3094 3095 status = pci_read_config(cfg->dev, cfg->pp.pp_location + 3096 PCIR_POWER_STATUS, 2); 3097 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 3098 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 3099 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 3100 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 3101 status & PCIM_PSTAT_DMASK); 3102 } 3103 if (cfg->msi.msi_location) { 3104 uint16_t ctrl, msgnum; 3105 3106 ctrl = cfg->msi.msi_ctrl; 3107 msgnum = PCI_MSI_MSGNUM(ctrl); 3108 printf("\tMSI supports %d message%s%s%s\n", 3109 msgnum, (msgnum == 1) ? "" : "s", 3110 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 3111 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 3112 } 3113 if (cfg->msix.msix_location) { 3114 uint16_t msgnum; 3115 3116 msgnum = PCI_MSIX_MSGNUM(cfg->msix.msix_ctrl); 3117 printf("\tMSI-X supports %d message%s ", 3118 msgnum, (msgnum == 1) ? "" : "s"); 3119 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 3120 printf("in map 0x%x\n", 3121 cfg->msix.msix_table_bar); 3122 else 3123 printf("in maps 0x%x and 0x%x\n", 3124 cfg->msix.msix_table_bar, 3125 cfg->msix.msix_pba_bar); 3126 } 3127 } 3128 } 3129 3130 static int 3131 pci_porten(device_t dev) 3132 { 3133 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0; 3134 } 3135 3136 static int 3137 pci_memen(device_t dev) 3138 { 3139 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0; 3140 } 3141 3142 void 3143 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, 3144 int *bar64) 3145 { 3146 struct pci_devinfo *dinfo; 3147 pci_addr_t map, testval; 3148 int ln2range; 3149 uint16_t cmd; 3150 3151 /* 3152 * The device ROM BAR is special. It is always a 32-bit 3153 * memory BAR. Bit 0 is special and should not be set when 3154 * sizing the BAR. 3155 */ 3156 dinfo = device_get_ivars(dev); 3157 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { 3158 map = pci_read_config(dev, reg, 4); 3159 pci_write_config(dev, reg, 0xfffffffe, 4); 3160 testval = pci_read_config(dev, reg, 4); 3161 pci_write_config(dev, reg, map, 4); 3162 *mapp = map; 3163 *testvalp = testval; 3164 if (bar64 != NULL) 3165 *bar64 = 0; 3166 return; 3167 } 3168 3169 map = pci_read_config(dev, reg, 4); 3170 ln2range = pci_maprange(map); 3171 if (ln2range == 64) 3172 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3173 3174 /* 3175 * Disable decoding via the command register before 3176 * determining the BAR's length since we will be placing it in 3177 * a weird state. 3178 */ 3179 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3180 pci_write_config(dev, PCIR_COMMAND, 3181 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 3182 3183 /* 3184 * Determine the BAR's length by writing all 1's. The bottom 3185 * log_2(size) bits of the BAR will stick as 0 when we read 3186 * the value back. 3187 * 3188 * NB: according to the PCI Local Bus Specification, rev. 3.0: 3189 * "Software writes 0FFFFFFFFh to both registers, reads them back, 3190 * and combines the result into a 64-bit value." (section 6.2.5.1) 3191 * 3192 * Writes to both registers must be performed before attempting to 3193 * read back the size value. 3194 */ 3195 testval = 0; 3196 pci_write_config(dev, reg, 0xffffffff, 4); 3197 if (ln2range == 64) { 3198 pci_write_config(dev, reg + 4, 0xffffffff, 4); 3199 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3200 } 3201 testval |= pci_read_config(dev, reg, 4); 3202 3203 /* 3204 * Restore the original value of the BAR. We may have reprogrammed 3205 * the BAR of the low-level console device and when booting verbose, 3206 * we need the console device addressable. 3207 */ 3208 pci_write_config(dev, reg, map, 4); 3209 if (ln2range == 64) 3210 pci_write_config(dev, reg + 4, map >> 32, 4); 3211 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3212 3213 *mapp = map; 3214 *testvalp = testval; 3215 if (bar64 != NULL) 3216 *bar64 = (ln2range == 64); 3217 } 3218 3219 static void 3220 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base) 3221 { 3222 struct pci_devinfo *dinfo; 3223 int ln2range; 3224 3225 /* The device ROM BAR is always a 32-bit memory BAR. */ 3226 dinfo = device_get_ivars(dev); 3227 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3228 ln2range = 32; 3229 else 3230 ln2range = pci_maprange(pm->pm_value); 3231 pci_write_config(dev, pm->pm_reg, base, 4); 3232 if (ln2range == 64) 3233 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); 3234 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); 3235 if (ln2range == 64) 3236 pm->pm_value |= (pci_addr_t)pci_read_config(dev, 3237 pm->pm_reg + 4, 4) << 32; 3238 } 3239 3240 struct pci_map * 3241 pci_find_bar(device_t dev, int reg) 3242 { 3243 struct pci_devinfo *dinfo; 3244 struct pci_map *pm; 3245 3246 dinfo = device_get_ivars(dev); 3247 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3248 if (pm->pm_reg == reg) 3249 return (pm); 3250 } 3251 return (NULL); 3252 } 3253 3254 struct pci_map * 3255 pci_first_bar(device_t dev) 3256 { 3257 struct pci_devinfo *dinfo; 3258 3259 dinfo = device_get_ivars(dev); 3260 return (STAILQ_FIRST(&dinfo->cfg.maps)); 3261 } 3262 3263 struct pci_map * 3264 pci_next_bar(struct pci_map *pm) 3265 { 3266 return (STAILQ_NEXT(pm, pm_link)); 3267 } 3268 3269 int 3270 pci_bar_enabled(device_t dev, struct pci_map *pm) 3271 { 3272 struct pci_devinfo *dinfo; 3273 uint16_t cmd; 3274 3275 dinfo = device_get_ivars(dev); 3276 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && 3277 !(pm->pm_value & PCIM_BIOS_ENABLE)) 3278 return (0); 3279 #ifdef PCI_IOV 3280 if ((dinfo->cfg.flags & PCICFG_VF) != 0) { 3281 struct pcicfg_iov *iov; 3282 3283 iov = dinfo->cfg.iov; 3284 cmd = pci_read_config(iov->iov_pf, 3285 iov->iov_pos + PCIR_SRIOV_CTL, 2); 3286 return ((cmd & PCIM_SRIOV_VF_MSE) != 0); 3287 } 3288 #endif 3289 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3290 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) 3291 return ((cmd & PCIM_CMD_MEMEN) != 0); 3292 else 3293 return ((cmd & PCIM_CMD_PORTEN) != 0); 3294 } 3295 3296 struct pci_map * 3297 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size) 3298 { 3299 struct pci_devinfo *dinfo; 3300 struct pci_map *pm, *prev; 3301 3302 dinfo = device_get_ivars(dev); 3303 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO); 3304 pm->pm_reg = reg; 3305 pm->pm_value = value; 3306 pm->pm_size = size; 3307 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { 3308 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", 3309 reg)); 3310 if (STAILQ_NEXT(prev, pm_link) == NULL || 3311 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) 3312 break; 3313 } 3314 if (prev != NULL) 3315 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); 3316 else 3317 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); 3318 return (pm); 3319 } 3320 3321 static void 3322 pci_restore_bars(device_t dev) 3323 { 3324 struct pci_devinfo *dinfo; 3325 struct pci_map *pm; 3326 int ln2range; 3327 3328 dinfo = device_get_ivars(dev); 3329 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3330 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3331 ln2range = 32; 3332 else 3333 ln2range = pci_maprange(pm->pm_value); 3334 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); 3335 if (ln2range == 64) 3336 pci_write_config(dev, pm->pm_reg + 4, 3337 pm->pm_value >> 32, 4); 3338 } 3339 } 3340 3341 /* 3342 * Add a resource based on a pci map register. Return 1 if the map 3343 * register is a 32bit map register or 2 if it is a 64bit register. 3344 */ 3345 static int 3346 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, 3347 int force, int prefetch) 3348 { 3349 struct pci_map *pm; 3350 pci_addr_t base, map, testval; 3351 pci_addr_t start, end, count; 3352 int barlen, basezero, flags, maprange, mapsize, type; 3353 uint16_t cmd; 3354 struct resource *res; 3355 3356 /* 3357 * The BAR may already exist if the device is a CardBus card 3358 * whose CIS is stored in this BAR. 3359 */ 3360 pm = pci_find_bar(dev, reg); 3361 if (pm != NULL) { 3362 maprange = pci_maprange(pm->pm_value); 3363 barlen = maprange == 64 ? 2 : 1; 3364 return (barlen); 3365 } 3366 3367 pci_read_bar(dev, reg, &map, &testval, NULL); 3368 if (PCI_BAR_MEM(map)) { 3369 type = SYS_RES_MEMORY; 3370 if (map & PCIM_BAR_MEM_PREFETCH) 3371 prefetch = 1; 3372 } else 3373 type = SYS_RES_IOPORT; 3374 mapsize = pci_mapsize(testval); 3375 base = pci_mapbase(map); 3376 #ifdef __PCI_BAR_ZERO_VALID 3377 basezero = 0; 3378 #else 3379 basezero = base == 0; 3380 #endif 3381 maprange = pci_maprange(map); 3382 barlen = maprange == 64 ? 2 : 1; 3383 3384 /* 3385 * For I/O registers, if bottom bit is set, and the next bit up 3386 * isn't clear, we know we have a BAR that doesn't conform to the 3387 * spec, so ignore it. Also, sanity check the size of the data 3388 * areas to the type of memory involved. Memory must be at least 3389 * 16 bytes in size, while I/O ranges must be at least 4. 3390 */ 3391 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0) 3392 return (barlen); 3393 if ((type == SYS_RES_MEMORY && mapsize < 4) || 3394 (type == SYS_RES_IOPORT && mapsize < 2)) 3395 return (barlen); 3396 3397 /* Save a record of this BAR. */ 3398 pm = pci_add_bar(dev, reg, map, mapsize); 3399 if (bootverbose) { 3400 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d", 3401 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize); 3402 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3403 printf(", port disabled\n"); 3404 else if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3405 printf(", memory disabled\n"); 3406 else 3407 printf(", enabled\n"); 3408 } 3409 3410 /* 3411 * If base is 0, then we have problems if this architecture does 3412 * not allow that. It is best to ignore such entries for the 3413 * moment. These will be allocated later if the driver specifically 3414 * requests them. However, some removable buses look better when 3415 * all resources are allocated, so allow '0' to be overridden. 3416 * 3417 * Similarly treat maps whose values is the same as the test value 3418 * read back. These maps have had all f's written to them by the 3419 * BIOS in an attempt to disable the resources. 3420 */ 3421 if (!force && (basezero || map == testval)) 3422 return (barlen); 3423 if ((u_long)base != base) { 3424 device_printf(bus, 3425 "pci%d:%d:%d:%d bar %#x too many address bits", 3426 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev), 3427 pci_get_function(dev), reg); 3428 return (barlen); 3429 } 3430 3431 /* 3432 * This code theoretically does the right thing, but has 3433 * undesirable side effects in some cases where peripherals 3434 * respond oddly to having these bits enabled. Let the user 3435 * be able to turn them off (since pci_enable_io_modes is 1 by 3436 * default). 3437 */ 3438 if (pci_enable_io_modes) { 3439 /* Turn on resources that have been left off by a lazy BIOS */ 3440 if (type == SYS_RES_IOPORT && !pci_porten(dev)) { 3441 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3442 cmd |= PCIM_CMD_PORTEN; 3443 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3444 } 3445 if (type == SYS_RES_MEMORY && !pci_memen(dev)) { 3446 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3447 cmd |= PCIM_CMD_MEMEN; 3448 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3449 } 3450 } else { 3451 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3452 return (barlen); 3453 if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3454 return (barlen); 3455 } 3456 3457 count = (pci_addr_t)1 << mapsize; 3458 flags = RF_ALIGNMENT_LOG2(mapsize); 3459 if (prefetch) 3460 flags |= RF_PREFETCHABLE; 3461 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) { 3462 start = 0; /* Let the parent decide. */ 3463 end = ~0; 3464 } else { 3465 start = base; 3466 end = base + count - 1; 3467 } 3468 resource_list_add(rl, type, reg, start, end, count); 3469 3470 /* 3471 * Try to allocate the resource for this BAR from our parent 3472 * so that this resource range is already reserved. The 3473 * driver for this device will later inherit this resource in 3474 * pci_alloc_resource(). 3475 */ 3476 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count, 3477 flags); 3478 if ((pci_do_realloc_bars 3479 || pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_REALLOC_BAR)) 3480 && res == NULL && (start != 0 || end != ~0)) { 3481 /* 3482 * If the allocation fails, try to allocate a resource for 3483 * this BAR using any available range. The firmware felt 3484 * it was important enough to assign a resource, so don't 3485 * disable decoding if we can help it. 3486 */ 3487 resource_list_delete(rl, type, reg); 3488 resource_list_add(rl, type, reg, 0, ~0, count); 3489 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0, 3490 count, flags); 3491 } 3492 if (res == NULL) { 3493 /* 3494 * If the allocation fails, delete the resource list entry 3495 * and disable decoding for this device. 3496 * 3497 * If the driver requests this resource in the future, 3498 * pci_reserve_map() will try to allocate a fresh 3499 * resource range. 3500 */ 3501 resource_list_delete(rl, type, reg); 3502 pci_disable_io(dev, type); 3503 if (bootverbose) 3504 device_printf(bus, 3505 "pci%d:%d:%d:%d bar %#x failed to allocate\n", 3506 pci_get_domain(dev), pci_get_bus(dev), 3507 pci_get_slot(dev), pci_get_function(dev), reg); 3508 } else { 3509 start = rman_get_start(res); 3510 pci_write_bar(dev, pm, start); 3511 } 3512 return (barlen); 3513 } 3514 3515 /* 3516 * For ATA devices we need to decide early what addressing mode to use. 3517 * Legacy demands that the primary and secondary ATA ports sits on the 3518 * same addresses that old ISA hardware did. This dictates that we use 3519 * those addresses and ignore the BAR's if we cannot set PCI native 3520 * addressing mode. 3521 */ 3522 static void 3523 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, 3524 uint32_t prefetchmask) 3525 { 3526 int rid, type, progif; 3527 #if 0 3528 /* if this device supports PCI native addressing use it */ 3529 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3530 if ((progif & 0x8a) == 0x8a) { 3531 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 3532 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 3533 printf("Trying ATA native PCI addressing mode\n"); 3534 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 3535 } 3536 } 3537 #endif 3538 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3539 type = SYS_RES_IOPORT; 3540 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 3541 pci_add_map(bus, dev, PCIR_BAR(0), rl, force, 3542 prefetchmask & (1 << 0)); 3543 pci_add_map(bus, dev, PCIR_BAR(1), rl, force, 3544 prefetchmask & (1 << 1)); 3545 } else { 3546 rid = PCIR_BAR(0); 3547 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 3548 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0, 3549 0x1f7, 8, 0); 3550 rid = PCIR_BAR(1); 3551 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 3552 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6, 3553 0x3f6, 1, 0); 3554 } 3555 if (progif & PCIP_STORAGE_IDE_MODESEC) { 3556 pci_add_map(bus, dev, PCIR_BAR(2), rl, force, 3557 prefetchmask & (1 << 2)); 3558 pci_add_map(bus, dev, PCIR_BAR(3), rl, force, 3559 prefetchmask & (1 << 3)); 3560 } else { 3561 rid = PCIR_BAR(2); 3562 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 3563 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170, 3564 0x177, 8, 0); 3565 rid = PCIR_BAR(3); 3566 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 3567 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376, 3568 0x376, 1, 0); 3569 } 3570 pci_add_map(bus, dev, PCIR_BAR(4), rl, force, 3571 prefetchmask & (1 << 4)); 3572 pci_add_map(bus, dev, PCIR_BAR(5), rl, force, 3573 prefetchmask & (1 << 5)); 3574 } 3575 3576 static void 3577 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 3578 { 3579 struct pci_devinfo *dinfo = device_get_ivars(dev); 3580 pcicfgregs *cfg = &dinfo->cfg; 3581 char tunable_name[64]; 3582 int irq; 3583 3584 /* Has to have an intpin to have an interrupt. */ 3585 if (cfg->intpin == 0) 3586 return; 3587 3588 /* Let the user override the IRQ with a tunable. */ 3589 irq = PCI_INVALID_IRQ; 3590 snprintf(tunable_name, sizeof(tunable_name), 3591 "hw.pci%d.%d.%d.INT%c.irq", 3592 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 3593 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 3594 irq = PCI_INVALID_IRQ; 3595 3596 /* 3597 * If we didn't get an IRQ via the tunable, then we either use the 3598 * IRQ value in the intline register or we ask the bus to route an 3599 * interrupt for us. If force_route is true, then we only use the 3600 * value in the intline register if the bus was unable to assign an 3601 * IRQ. 3602 */ 3603 if (!PCI_INTERRUPT_VALID(irq)) { 3604 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 3605 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 3606 if (!PCI_INTERRUPT_VALID(irq)) 3607 irq = cfg->intline; 3608 } 3609 3610 /* If after all that we don't have an IRQ, just bail. */ 3611 if (!PCI_INTERRUPT_VALID(irq)) 3612 return; 3613 3614 /* Update the config register if it changed. */ 3615 if (irq != cfg->intline) { 3616 cfg->intline = irq; 3617 pci_write_config(dev, PCIR_INTLINE, irq, 1); 3618 } 3619 3620 /* Add this IRQ as rid 0 interrupt resource. */ 3621 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 3622 } 3623 3624 /* Perform early OHCI takeover from SMM. */ 3625 static void 3626 ohci_early_takeover(device_t self) 3627 { 3628 struct resource *res; 3629 uint32_t ctl; 3630 int rid; 3631 int i; 3632 3633 rid = PCIR_BAR(0); 3634 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3635 if (res == NULL) 3636 return; 3637 3638 ctl = bus_read_4(res, OHCI_CONTROL); 3639 if (ctl & OHCI_IR) { 3640 if (bootverbose) 3641 printf("ohci early: " 3642 "SMM active, request owner change\n"); 3643 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR); 3644 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 3645 DELAY(1000); 3646 ctl = bus_read_4(res, OHCI_CONTROL); 3647 } 3648 if (ctl & OHCI_IR) { 3649 if (bootverbose) 3650 printf("ohci early: " 3651 "SMM does not respond, resetting\n"); 3652 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET); 3653 } 3654 /* Disable interrupts */ 3655 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 3656 } 3657 3658 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3659 } 3660 3661 /* Perform early UHCI takeover from SMM. */ 3662 static void 3663 uhci_early_takeover(device_t self) 3664 { 3665 struct resource *res; 3666 int rid; 3667 3668 /* 3669 * Set the PIRQD enable bit and switch off all the others. We don't 3670 * want legacy support to interfere with us XXX Does this also mean 3671 * that the BIOS won't touch the keyboard anymore if it is connected 3672 * to the ports of the root hub? 3673 */ 3674 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2); 3675 3676 /* Disable interrupts */ 3677 rid = PCI_UHCI_BASE_REG; 3678 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE); 3679 if (res != NULL) { 3680 bus_write_2(res, UHCI_INTR, 0); 3681 bus_release_resource(self, SYS_RES_IOPORT, rid, res); 3682 } 3683 } 3684 3685 /* Perform early EHCI takeover from SMM. */ 3686 static void 3687 ehci_early_takeover(device_t self) 3688 { 3689 struct resource *res; 3690 uint32_t cparams; 3691 uint32_t eec; 3692 uint8_t eecp; 3693 uint8_t bios_sem; 3694 uint8_t offs; 3695 int rid; 3696 int i; 3697 3698 rid = PCIR_BAR(0); 3699 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3700 if (res == NULL) 3701 return; 3702 3703 cparams = bus_read_4(res, EHCI_HCCPARAMS); 3704 3705 /* Synchronise with the BIOS if it owns the controller. */ 3706 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0; 3707 eecp = EHCI_EECP_NEXT(eec)) { 3708 eec = pci_read_config(self, eecp, 4); 3709 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) { 3710 continue; 3711 } 3712 bios_sem = pci_read_config(self, eecp + 3713 EHCI_LEGSUP_BIOS_SEM, 1); 3714 if (bios_sem == 0) { 3715 continue; 3716 } 3717 if (bootverbose) 3718 printf("ehci early: " 3719 "SMM active, request owner change\n"); 3720 3721 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1); 3722 3723 for (i = 0; (i < 100) && (bios_sem != 0); i++) { 3724 DELAY(1000); 3725 bios_sem = pci_read_config(self, eecp + 3726 EHCI_LEGSUP_BIOS_SEM, 1); 3727 } 3728 3729 if (bios_sem != 0) { 3730 if (bootverbose) 3731 printf("ehci early: " 3732 "SMM does not respond\n"); 3733 } 3734 /* Disable interrupts */ 3735 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION)); 3736 bus_write_4(res, offs + EHCI_USBINTR, 0); 3737 } 3738 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3739 } 3740 3741 /* Perform early XHCI takeover from SMM. */ 3742 static void 3743 xhci_early_takeover(device_t self) 3744 { 3745 struct resource *res; 3746 uint32_t cparams; 3747 uint32_t eec; 3748 uint8_t eecp; 3749 uint8_t bios_sem; 3750 uint8_t offs; 3751 int rid; 3752 int i; 3753 3754 rid = PCIR_BAR(0); 3755 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3756 if (res == NULL) 3757 return; 3758 3759 cparams = bus_read_4(res, XHCI_HCSPARAMS0); 3760 3761 eec = -1; 3762 3763 /* Synchronise with the BIOS if it owns the controller. */ 3764 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 3765 eecp += XHCI_XECP_NEXT(eec) << 2) { 3766 eec = bus_read_4(res, eecp); 3767 3768 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 3769 continue; 3770 3771 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM); 3772 if (bios_sem == 0) 3773 continue; 3774 3775 if (bootverbose) 3776 printf("xhci early: " 3777 "SMM active, request owner change\n"); 3778 3779 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1); 3780 3781 /* wait a maximum of 5 second */ 3782 3783 for (i = 0; (i < 5000) && (bios_sem != 0); i++) { 3784 DELAY(1000); 3785 bios_sem = bus_read_1(res, eecp + 3786 XHCI_XECP_BIOS_SEM); 3787 } 3788 3789 if (bios_sem != 0) { 3790 if (bootverbose) 3791 printf("xhci early: " 3792 "SMM does not respond\n"); 3793 } 3794 3795 /* Disable interrupts */ 3796 offs = bus_read_1(res, XHCI_CAPLENGTH); 3797 bus_write_4(res, offs + XHCI_USBCMD, 0); 3798 bus_read_4(res, offs + XHCI_USBSTS); 3799 } 3800 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3801 } 3802 3803 static void 3804 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg, 3805 struct resource_list *rl) 3806 { 3807 struct resource *res; 3808 char *cp; 3809 rman_res_t start, end, count; 3810 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus; 3811 3812 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3813 case PCIM_HDRTYPE_BRIDGE: 3814 sec_reg = PCIR_SECBUS_1; 3815 sub_reg = PCIR_SUBBUS_1; 3816 break; 3817 case PCIM_HDRTYPE_CARDBUS: 3818 sec_reg = PCIR_SECBUS_2; 3819 sub_reg = PCIR_SUBBUS_2; 3820 break; 3821 default: 3822 return; 3823 } 3824 3825 /* 3826 * If the existing bus range is valid, attempt to reserve it 3827 * from our parent. If this fails for any reason, clear the 3828 * secbus and subbus registers. 3829 * 3830 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus? 3831 * This would at least preserve the existing sec_bus if it is 3832 * valid. 3833 */ 3834 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1); 3835 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1); 3836 3837 /* Quirk handling. */ 3838 switch (pci_get_devid(dev)) { 3839 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 3840 sup_bus = pci_read_config(dev, 0x41, 1); 3841 if (sup_bus != 0xff) { 3842 sec_bus = sup_bus + 1; 3843 sub_bus = sup_bus + 1; 3844 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1); 3845 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3846 } 3847 break; 3848 3849 case 0x00dd10de: 3850 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 3851 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 3852 break; 3853 if (strncmp(cp, "Compal", 6) != 0) { 3854 freeenv(cp); 3855 break; 3856 } 3857 freeenv(cp); 3858 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 3859 break; 3860 if (strncmp(cp, "08A0", 4) != 0) { 3861 freeenv(cp); 3862 break; 3863 } 3864 freeenv(cp); 3865 if (sub_bus < 0xa) { 3866 sub_bus = 0xa; 3867 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3868 } 3869 break; 3870 } 3871 3872 if (bootverbose) 3873 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus); 3874 if (sec_bus > 0 && sub_bus >= sec_bus) { 3875 start = sec_bus; 3876 end = sub_bus; 3877 count = end - start + 1; 3878 3879 resource_list_add(rl, PCI_RES_BUS, 0, 0, ~0, count); 3880 3881 /* 3882 * If requested, clear secondary bus registers in 3883 * bridge devices to force a complete renumbering 3884 * rather than reserving the existing range. However, 3885 * preserve the existing size. 3886 */ 3887 if (pci_clear_buses) 3888 goto clear; 3889 3890 rid = 0; 3891 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid, 3892 start, end, count, 0); 3893 if (res != NULL) 3894 return; 3895 3896 if (bootverbose) 3897 device_printf(bus, 3898 "pci%d:%d:%d:%d secbus failed to allocate\n", 3899 pci_get_domain(dev), pci_get_bus(dev), 3900 pci_get_slot(dev), pci_get_function(dev)); 3901 } 3902 3903 clear: 3904 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1); 3905 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1); 3906 } 3907 3908 static struct resource * 3909 pci_alloc_secbus(device_t dev, device_t child, int *rid, rman_res_t start, 3910 rman_res_t end, rman_res_t count, u_int flags) 3911 { 3912 struct pci_devinfo *dinfo; 3913 pcicfgregs *cfg; 3914 struct resource_list *rl; 3915 struct resource *res; 3916 int sec_reg, sub_reg; 3917 3918 dinfo = device_get_ivars(child); 3919 cfg = &dinfo->cfg; 3920 rl = &dinfo->resources; 3921 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3922 case PCIM_HDRTYPE_BRIDGE: 3923 sec_reg = PCIR_SECBUS_1; 3924 sub_reg = PCIR_SUBBUS_1; 3925 break; 3926 case PCIM_HDRTYPE_CARDBUS: 3927 sec_reg = PCIR_SECBUS_2; 3928 sub_reg = PCIR_SUBBUS_2; 3929 break; 3930 default: 3931 return (NULL); 3932 } 3933 3934 if (*rid != 0) 3935 return (NULL); 3936 3937 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL) 3938 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count); 3939 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) { 3940 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid, 3941 start, end, count, flags & ~RF_ACTIVE); 3942 if (res == NULL) { 3943 resource_list_delete(rl, PCI_RES_BUS, *rid); 3944 device_printf(child, "allocating %ju bus%s failed\n", 3945 count, count == 1 ? "" : "es"); 3946 return (NULL); 3947 } 3948 if (bootverbose) 3949 device_printf(child, 3950 "Lazy allocation of %ju bus%s at %ju\n", count, 3951 count == 1 ? "" : "es", rman_get_start(res)); 3952 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1); 3953 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1); 3954 } 3955 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start, 3956 end, count, flags)); 3957 } 3958 3959 static int 3960 pci_ea_bei_to_rid(device_t dev, int bei) 3961 { 3962 #ifdef PCI_IOV 3963 struct pci_devinfo *dinfo; 3964 int iov_pos; 3965 struct pcicfg_iov *iov; 3966 3967 dinfo = device_get_ivars(dev); 3968 iov = dinfo->cfg.iov; 3969 if (iov != NULL) 3970 iov_pos = iov->iov_pos; 3971 else 3972 iov_pos = 0; 3973 #endif 3974 3975 /* Check if matches BAR */ 3976 if ((bei >= PCIM_EA_BEI_BAR_0) && 3977 (bei <= PCIM_EA_BEI_BAR_5)) 3978 return (PCIR_BAR(bei)); 3979 3980 /* Check ROM */ 3981 if (bei == PCIM_EA_BEI_ROM) 3982 return (PCIR_BIOS); 3983 3984 #ifdef PCI_IOV 3985 /* Check if matches VF_BAR */ 3986 if ((iov != NULL) && (bei >= PCIM_EA_BEI_VF_BAR_0) && 3987 (bei <= PCIM_EA_BEI_VF_BAR_5)) 3988 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) + 3989 iov_pos); 3990 #endif 3991 3992 return (-1); 3993 } 3994 3995 int 3996 pci_ea_is_enabled(device_t dev, int rid) 3997 { 3998 struct pci_ea_entry *ea; 3999 struct pci_devinfo *dinfo; 4000 4001 dinfo = device_get_ivars(dev); 4002 4003 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 4004 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid) 4005 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0); 4006 } 4007 4008 return (0); 4009 } 4010 4011 void 4012 pci_add_resources_ea(device_t bus, device_t dev, int alloc_iov) 4013 { 4014 struct pci_ea_entry *ea; 4015 struct pci_devinfo *dinfo; 4016 pci_addr_t start, end, count; 4017 struct resource_list *rl; 4018 int type, flags, rid; 4019 struct resource *res; 4020 uint32_t tmp; 4021 #ifdef PCI_IOV 4022 struct pcicfg_iov *iov; 4023 #endif 4024 4025 dinfo = device_get_ivars(dev); 4026 rl = &dinfo->resources; 4027 flags = 0; 4028 4029 #ifdef PCI_IOV 4030 iov = dinfo->cfg.iov; 4031 #endif 4032 4033 if (dinfo->cfg.ea.ea_location == 0) 4034 return; 4035 4036 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 4037 /* 4038 * TODO: Ignore EA-BAR if is not enabled. 4039 * Currently the EA implementation supports 4040 * only situation, where EA structure contains 4041 * predefined entries. In case they are not enabled 4042 * leave them unallocated and proceed with 4043 * a legacy-BAR mechanism. 4044 */ 4045 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0) 4046 continue; 4047 4048 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) { 4049 case PCIM_EA_P_MEM_PREFETCH: 4050 case PCIM_EA_P_VF_MEM_PREFETCH: 4051 flags = RF_PREFETCHABLE; 4052 /* FALLTHROUGH */ 4053 case PCIM_EA_P_VF_MEM: 4054 case PCIM_EA_P_MEM: 4055 type = SYS_RES_MEMORY; 4056 break; 4057 case PCIM_EA_P_IO: 4058 type = SYS_RES_IOPORT; 4059 break; 4060 default: 4061 continue; 4062 } 4063 4064 if (alloc_iov != 0) { 4065 #ifdef PCI_IOV 4066 /* Allocating IOV, confirm BEI matches */ 4067 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) || 4068 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5)) 4069 continue; 4070 #else 4071 continue; 4072 #endif 4073 } else { 4074 /* Allocating BAR, confirm BEI matches */ 4075 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) || 4076 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) && 4077 (ea->eae_bei != PCIM_EA_BEI_ROM)) 4078 continue; 4079 } 4080 4081 rid = pci_ea_bei_to_rid(dev, ea->eae_bei); 4082 if (rid < 0) 4083 continue; 4084 4085 /* Skip resources already allocated by EA */ 4086 if ((resource_list_find(rl, SYS_RES_MEMORY, rid) != NULL) || 4087 (resource_list_find(rl, SYS_RES_IOPORT, rid) != NULL)) 4088 continue; 4089 4090 start = ea->eae_base; 4091 count = ea->eae_max_offset + 1; 4092 #ifdef PCI_IOV 4093 if (iov != NULL) 4094 count = count * iov->iov_num_vfs; 4095 #endif 4096 end = start + count - 1; 4097 if (count == 0) 4098 continue; 4099 4100 resource_list_add(rl, type, rid, start, end, count); 4101 res = resource_list_reserve(rl, bus, dev, type, &rid, start, end, count, 4102 flags); 4103 if (res == NULL) { 4104 resource_list_delete(rl, type, rid); 4105 4106 /* 4107 * Failed to allocate using EA, disable entry. 4108 * Another attempt to allocation will be performed 4109 * further, but this time using legacy BAR registers 4110 */ 4111 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4); 4112 tmp &= ~PCIM_EA_ENABLE; 4113 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4); 4114 4115 /* 4116 * Disabling entry might fail in case it is hardwired. 4117 * Read flags again to match current status. 4118 */ 4119 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4); 4120 4121 continue; 4122 } 4123 4124 /* As per specification, fill BAR with zeros */ 4125 pci_write_config(dev, rid, 0, 4); 4126 } 4127 } 4128 4129 void 4130 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 4131 { 4132 struct pci_devinfo *dinfo; 4133 pcicfgregs *cfg; 4134 struct resource_list *rl; 4135 const struct pci_quirk *q; 4136 uint32_t devid; 4137 int i; 4138 4139 dinfo = device_get_ivars(dev); 4140 cfg = &dinfo->cfg; 4141 rl = &dinfo->resources; 4142 devid = (cfg->device << 16) | cfg->vendor; 4143 4144 /* Allocate resources using Enhanced Allocation */ 4145 pci_add_resources_ea(bus, dev, 0); 4146 4147 /* ATA devices needs special map treatment */ 4148 if ((pci_get_class(dev) == PCIC_STORAGE) && 4149 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 4150 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 4151 (!pci_read_config(dev, PCIR_BAR(0), 4) && 4152 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 4153 pci_ata_maps(bus, dev, rl, force, prefetchmask); 4154 else 4155 for (i = 0; i < cfg->nummaps;) { 4156 /* Skip resources already managed by EA */ 4157 if ((resource_list_find(rl, SYS_RES_MEMORY, PCIR_BAR(i)) != NULL) || 4158 (resource_list_find(rl, SYS_RES_IOPORT, PCIR_BAR(i)) != NULL) || 4159 pci_ea_is_enabled(dev, PCIR_BAR(i))) { 4160 i++; 4161 continue; 4162 } 4163 4164 /* 4165 * Skip quirked resources. 4166 */ 4167 for (q = &pci_quirks[0]; q->devid != 0; q++) 4168 if (q->devid == devid && 4169 q->type == PCI_QUIRK_UNMAP_REG && 4170 q->arg1 == PCIR_BAR(i)) 4171 break; 4172 if (q->devid != 0) { 4173 i++; 4174 continue; 4175 } 4176 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force, 4177 prefetchmask & (1 << i)); 4178 } 4179 4180 /* 4181 * Add additional, quirked resources. 4182 */ 4183 for (q = &pci_quirks[0]; q->devid != 0; q++) 4184 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) 4185 pci_add_map(bus, dev, q->arg1, rl, force, 0); 4186 4187 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline) && 4188 pci_intx_reroute) { 4189 /* 4190 * Try to re-route interrupts. Sometimes the BIOS or 4191 * firmware may leave bogus values in these registers. 4192 * If the re-route fails, then just stick with what we 4193 * have. 4194 */ 4195 pci_assign_interrupt(bus, dev, 1); 4196 } 4197 4198 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS && 4199 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) { 4200 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI) 4201 xhci_early_takeover(dev); 4202 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI) 4203 ehci_early_takeover(dev); 4204 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI) 4205 ohci_early_takeover(dev); 4206 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI) 4207 uhci_early_takeover(dev); 4208 } 4209 4210 /* 4211 * Reserve resources for secondary bus ranges behind bridge 4212 * devices. 4213 */ 4214 pci_reserve_secbus(bus, dev, cfg, rl); 4215 } 4216 4217 static struct pci_devinfo * 4218 pci_identify_function(device_t pcib, device_t dev, int domain, int busno, 4219 int slot, int func) 4220 { 4221 struct pci_devinfo *dinfo; 4222 4223 dinfo = pci_read_device(pcib, dev, domain, busno, slot, func); 4224 if (dinfo != NULL) 4225 pci_add_child(dev, dinfo); 4226 4227 return (dinfo); 4228 } 4229 4230 void 4231 pci_add_children(device_t dev, int domain, int busno) 4232 { 4233 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4234 device_t pcib = device_get_parent(dev); 4235 struct pci_devinfo *dinfo; 4236 int maxslots; 4237 int s, f, pcifunchigh; 4238 uint8_t hdrtype; 4239 int first_func; 4240 4241 /* 4242 * Try to detect a device at slot 0, function 0. If it exists, try to 4243 * enable ARI. We must enable ARI before detecting the rest of the 4244 * functions on this bus as ARI changes the set of slots and functions 4245 * that are legal on this bus. 4246 */ 4247 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0); 4248 if (dinfo != NULL && pci_enable_ari) 4249 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); 4250 4251 /* 4252 * Start looking for new devices on slot 0 at function 1 because we 4253 * just identified the device at slot 0, function 0. 4254 */ 4255 first_func = 1; 4256 4257 maxslots = PCIB_MAXSLOTS(pcib); 4258 for (s = 0; s <= maxslots; s++, first_func = 0) { 4259 pcifunchigh = 0; 4260 f = 0; 4261 DELAY(1); 4262 4263 /* If function 0 is not present, skip to the next slot. */ 4264 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4265 continue; 4266 hdrtype = REG(PCIR_HDRTYPE, 1); 4267 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4268 continue; 4269 if (hdrtype & PCIM_MFDEV) 4270 pcifunchigh = PCIB_MAXFUNCS(pcib); 4271 for (f = first_func; f <= pcifunchigh; f++) 4272 pci_identify_function(pcib, dev, domain, busno, s, f); 4273 } 4274 #undef REG 4275 } 4276 4277 int 4278 pci_rescan_method(device_t dev) 4279 { 4280 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4281 device_t pcib = device_get_parent(dev); 4282 device_t child, *devlist, *unchanged; 4283 int devcount, error, i, j, maxslots, oldcount; 4284 int busno, domain, s, f, pcifunchigh; 4285 uint8_t hdrtype; 4286 4287 /* No need to check for ARI on a rescan. */ 4288 error = device_get_children(dev, &devlist, &devcount); 4289 if (error) 4290 return (error); 4291 if (devcount != 0) { 4292 unchanged = malloc(devcount * sizeof(device_t), M_TEMP, 4293 M_NOWAIT | M_ZERO); 4294 if (unchanged == NULL) { 4295 free(devlist, M_TEMP); 4296 return (ENOMEM); 4297 } 4298 } else 4299 unchanged = NULL; 4300 4301 domain = pcib_get_domain(dev); 4302 busno = pcib_get_bus(dev); 4303 maxslots = PCIB_MAXSLOTS(pcib); 4304 for (s = 0; s <= maxslots; s++) { 4305 /* If function 0 is not present, skip to the next slot. */ 4306 f = 0; 4307 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4308 continue; 4309 pcifunchigh = 0; 4310 hdrtype = REG(PCIR_HDRTYPE, 1); 4311 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4312 continue; 4313 if (hdrtype & PCIM_MFDEV) 4314 pcifunchigh = PCIB_MAXFUNCS(pcib); 4315 for (f = 0; f <= pcifunchigh; f++) { 4316 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4317 continue; 4318 4319 /* 4320 * Found a valid function. Check if a 4321 * device_t for this device already exists. 4322 */ 4323 for (i = 0; i < devcount; i++) { 4324 child = devlist[i]; 4325 if (child == NULL) 4326 continue; 4327 if (pci_get_slot(child) == s && 4328 pci_get_function(child) == f) { 4329 unchanged[i] = child; 4330 goto next_func; 4331 } 4332 } 4333 4334 pci_identify_function(pcib, dev, domain, busno, s, f); 4335 next_func:; 4336 } 4337 } 4338 4339 /* Remove devices that are no longer present. */ 4340 for (i = 0; i < devcount; i++) { 4341 if (unchanged[i] != NULL) 4342 continue; 4343 device_delete_child(dev, devlist[i]); 4344 } 4345 4346 free(devlist, M_TEMP); 4347 oldcount = devcount; 4348 4349 /* Try to attach the devices just added. */ 4350 error = device_get_children(dev, &devlist, &devcount); 4351 if (error) { 4352 free(unchanged, M_TEMP); 4353 return (error); 4354 } 4355 4356 for (i = 0; i < devcount; i++) { 4357 for (j = 0; j < oldcount; j++) { 4358 if (devlist[i] == unchanged[j]) 4359 goto next_device; 4360 } 4361 4362 device_probe_and_attach(devlist[i]); 4363 next_device:; 4364 } 4365 4366 free(unchanged, M_TEMP); 4367 free(devlist, M_TEMP); 4368 return (0); 4369 #undef REG 4370 } 4371 4372 #ifdef PCI_IOV 4373 device_t 4374 pci_add_iov_child(device_t bus, device_t pf, uint16_t rid, uint16_t vid, 4375 uint16_t did) 4376 { 4377 struct pci_devinfo *vf_dinfo; 4378 device_t pcib; 4379 int busno, slot, func; 4380 4381 pcib = device_get_parent(bus); 4382 4383 PCIB_DECODE_RID(pcib, rid, &busno, &slot, &func); 4384 4385 vf_dinfo = pci_fill_devinfo(pcib, bus, pci_get_domain(pcib), busno, 4386 slot, func, vid, did); 4387 4388 vf_dinfo->cfg.flags |= PCICFG_VF; 4389 pci_add_child(bus, vf_dinfo); 4390 4391 return (vf_dinfo->cfg.dev); 4392 } 4393 4394 device_t 4395 pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid, 4396 uint16_t vid, uint16_t did) 4397 { 4398 4399 return (pci_add_iov_child(bus, pf, rid, vid, did)); 4400 } 4401 #endif 4402 4403 /* 4404 * For PCIe device set Max_Payload_Size to match PCIe root's. 4405 */ 4406 static void 4407 pcie_setup_mps(device_t dev) 4408 { 4409 struct pci_devinfo *dinfo = device_get_ivars(dev); 4410 device_t root; 4411 uint16_t rmps, mmps, mps; 4412 4413 if (dinfo->cfg.pcie.pcie_location == 0) 4414 return; 4415 root = pci_find_pcie_root_port(dev); 4416 if (root == NULL) 4417 return; 4418 /* Check whether the MPS is already configured. */ 4419 rmps = pcie_read_config(root, PCIER_DEVICE_CTL, 2) & 4420 PCIEM_CTL_MAX_PAYLOAD; 4421 mps = pcie_read_config(dev, PCIER_DEVICE_CTL, 2) & 4422 PCIEM_CTL_MAX_PAYLOAD; 4423 if (mps == rmps) 4424 return; 4425 /* Check whether the device is capable of the root's MPS. */ 4426 mmps = (pcie_read_config(dev, PCIER_DEVICE_CAP, 2) & 4427 PCIEM_CAP_MAX_PAYLOAD) << 5; 4428 if (rmps > mmps) { 4429 /* 4430 * The device is unable to handle root's MPS. Limit root. 4431 * XXX: We should traverse through all the tree, applying 4432 * it to all the devices. 4433 */ 4434 pcie_adjust_config(root, PCIER_DEVICE_CTL, 4435 PCIEM_CTL_MAX_PAYLOAD, mmps, 2); 4436 } else { 4437 pcie_adjust_config(dev, PCIER_DEVICE_CTL, 4438 PCIEM_CTL_MAX_PAYLOAD, rmps, 2); 4439 } 4440 } 4441 4442 static void 4443 pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo) 4444 { 4445 int aer; 4446 uint32_t r; 4447 uint16_t r2; 4448 4449 if (dinfo->cfg.pcie.pcie_location != 0 && 4450 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) { 4451 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4452 PCIER_ROOT_CTL, 2); 4453 r2 &= ~(PCIEM_ROOT_CTL_SERR_CORR | 4454 PCIEM_ROOT_CTL_SERR_NONFATAL | PCIEM_ROOT_CTL_SERR_FATAL); 4455 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4456 PCIER_ROOT_CTL, r2, 2); 4457 } 4458 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 4459 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 4460 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 4461 if (r != 0 && bootverbose) { 4462 pci_printf(&dinfo->cfg, 4463 "clearing AER UC 0x%08x -> 0x%08x\n", 4464 r, pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4465 4)); 4466 } 4467 4468 r = pci_read_config(dev, aer + PCIR_AER_UC_MASK, 4); 4469 r &= ~(PCIM_AER_UC_TRAINING_ERROR | 4470 PCIM_AER_UC_DL_PROTOCOL_ERROR | 4471 PCIM_AER_UC_SURPRISE_LINK_DOWN | 4472 PCIM_AER_UC_POISONED_TLP | 4473 PCIM_AER_UC_FC_PROTOCOL_ERROR | 4474 PCIM_AER_UC_COMPLETION_TIMEOUT | 4475 PCIM_AER_UC_COMPLETER_ABORT | 4476 PCIM_AER_UC_UNEXPECTED_COMPLETION | 4477 PCIM_AER_UC_RECEIVER_OVERFLOW | 4478 PCIM_AER_UC_MALFORMED_TLP | 4479 PCIM_AER_UC_ECRC_ERROR | 4480 PCIM_AER_UC_UNSUPPORTED_REQUEST | 4481 PCIM_AER_UC_ACS_VIOLATION | 4482 PCIM_AER_UC_INTERNAL_ERROR | 4483 PCIM_AER_UC_MC_BLOCKED_TLP | 4484 PCIM_AER_UC_ATOMIC_EGRESS_BLK | 4485 PCIM_AER_UC_TLP_PREFIX_BLOCKED); 4486 pci_write_config(dev, aer + PCIR_AER_UC_MASK, r, 4); 4487 4488 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 4489 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 4490 if (r != 0 && bootverbose) { 4491 pci_printf(&dinfo->cfg, 4492 "clearing AER COR 0x%08x -> 0x%08x\n", 4493 r, pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4494 4)); 4495 } 4496 4497 r = pci_read_config(dev, aer + PCIR_AER_COR_MASK, 4); 4498 r &= ~(PCIM_AER_COR_RECEIVER_ERROR | 4499 PCIM_AER_COR_BAD_TLP | 4500 PCIM_AER_COR_BAD_DLLP | 4501 PCIM_AER_COR_REPLAY_ROLLOVER | 4502 PCIM_AER_COR_REPLAY_TIMEOUT | 4503 PCIM_AER_COR_ADVISORY_NF_ERROR | 4504 PCIM_AER_COR_INTERNAL_ERROR | 4505 PCIM_AER_COR_HEADER_LOG_OVFLOW); 4506 pci_write_config(dev, aer + PCIR_AER_COR_MASK, r, 4); 4507 4508 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4509 PCIER_DEVICE_CTL, 2); 4510 r |= PCIEM_CTL_COR_ENABLE | PCIEM_CTL_NFER_ENABLE | 4511 PCIEM_CTL_FER_ENABLE | PCIEM_CTL_URR_ENABLE; 4512 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4513 PCIER_DEVICE_CTL, r, 2); 4514 } 4515 } 4516 4517 void 4518 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 4519 { 4520 device_t dev; 4521 4522 dinfo->cfg.dev = dev = device_add_child(bus, NULL, DEVICE_UNIT_ANY); 4523 device_set_ivars(dev, dinfo); 4524 resource_list_init(&dinfo->resources); 4525 pci_cfg_save(dev, dinfo, 0); 4526 pci_cfg_restore(dev, dinfo); 4527 pci_clear_pme(dev); 4528 pci_print_verbose(dinfo); 4529 pci_add_resources(bus, dev, 0, 0); 4530 if (pci_enable_mps_tune) 4531 pcie_setup_mps(dev); 4532 pci_child_added(dinfo->cfg.dev); 4533 4534 if (pci_clear_aer_on_attach) 4535 pci_add_child_clear_aer(dev, dinfo); 4536 4537 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev); 4538 } 4539 4540 void 4541 pci_child_added_method(device_t dev, device_t child) 4542 { 4543 4544 } 4545 4546 static int 4547 pci_probe(device_t dev) 4548 { 4549 4550 device_set_desc(dev, "PCI bus"); 4551 4552 /* Allow other subclasses to override this driver. */ 4553 return (BUS_PROBE_GENERIC); 4554 } 4555 4556 int 4557 pci_attach_common(device_t dev) 4558 { 4559 struct pci_softc *sc; 4560 int busno, domain; 4561 int rid; 4562 4563 sc = device_get_softc(dev); 4564 domain = pcib_get_domain(dev); 4565 busno = pcib_get_bus(dev); 4566 rid = 0; 4567 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, 4568 1, 0); 4569 if (sc->sc_bus == NULL) { 4570 device_printf(dev, "failed to allocate bus number\n"); 4571 return (ENXIO); 4572 } 4573 if (bootverbose) 4574 device_printf(dev, "domain=%d, physical bus=%d\n", 4575 domain, busno); 4576 sc->sc_dma_tag = bus_get_dma_tag(dev); 4577 return (0); 4578 } 4579 4580 int 4581 pci_attach(device_t dev) 4582 { 4583 int busno, domain, error; 4584 4585 error = pci_attach_common(dev); 4586 if (error) 4587 return (error); 4588 4589 /* 4590 * Since there can be multiple independently numbered PCI 4591 * buses on systems with multiple PCI domains, we can't use 4592 * the unit number to decide which bus we are probing. We ask 4593 * the parent pcib what our domain and bus numbers are. 4594 */ 4595 domain = pcib_get_domain(dev); 4596 busno = pcib_get_bus(dev); 4597 pci_add_children(dev, domain, busno); 4598 bus_attach_children(dev); 4599 return (0); 4600 } 4601 4602 int 4603 pci_detach(device_t dev) 4604 { 4605 struct pci_softc *sc; 4606 int error; 4607 4608 error = bus_generic_detach(dev); 4609 if (error) 4610 return (error); 4611 sc = device_get_softc(dev); 4612 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus); 4613 return (error); 4614 } 4615 4616 static void 4617 pci_hint_device_unit(device_t dev, device_t child, const char *name, int *unitp) 4618 { 4619 int line, unit; 4620 const char *at; 4621 char me1[24], me2[32]; 4622 uint8_t b, s, f; 4623 uint32_t d; 4624 device_location_cache_t *cache; 4625 4626 d = pci_get_domain(child); 4627 b = pci_get_bus(child); 4628 s = pci_get_slot(child); 4629 f = pci_get_function(child); 4630 snprintf(me1, sizeof(me1), "pci%u:%u:%u", b, s, f); 4631 snprintf(me2, sizeof(me2), "pci%u:%u:%u:%u", d, b, s, f); 4632 line = 0; 4633 cache = dev_wired_cache_init(); 4634 while (resource_find_dev(&line, name, &unit, "at", NULL) == 0) { 4635 resource_string_value(name, unit, "at", &at); 4636 if (strcmp(at, me1) == 0 || strcmp(at, me2) == 0) { 4637 *unitp = unit; 4638 break; 4639 } 4640 if (dev_wired_cache_match(cache, child, at)) { 4641 *unitp = unit; 4642 break; 4643 } 4644 } 4645 dev_wired_cache_fini(cache); 4646 } 4647 4648 static void 4649 pci_set_power_child(device_t dev, device_t child, int state) 4650 { 4651 device_t pcib; 4652 int dstate; 4653 4654 /* 4655 * Set the device to the given state. If the firmware suggests 4656 * a different power state, use it instead. If power management 4657 * is not present, the firmware is responsible for managing 4658 * device power. Skip children who aren't attached since they 4659 * are handled separately. 4660 */ 4661 pcib = device_get_parent(dev); 4662 dstate = state; 4663 if (device_is_attached(child) && 4664 PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0) 4665 pci_set_powerstate(child, dstate); 4666 } 4667 4668 int 4669 pci_suspend_child(device_t dev, device_t child) 4670 { 4671 struct pci_devinfo *dinfo; 4672 struct resource_list_entry *rle; 4673 int error; 4674 4675 dinfo = device_get_ivars(child); 4676 4677 /* 4678 * Save the PCI configuration space for the child and set the 4679 * device in the appropriate power state for this sleep state. 4680 */ 4681 pci_cfg_save(child, dinfo, 0); 4682 4683 /* Suspend devices before potentially powering them down. */ 4684 error = bus_generic_suspend_child(dev, child); 4685 4686 if (error) 4687 return (error); 4688 4689 if (pci_do_power_suspend) { 4690 /* 4691 * Make sure this device's interrupt handler is not invoked 4692 * in the case the device uses a shared interrupt that can 4693 * be raised by some other device. 4694 * This is applicable only to regular (legacy) PCI interrupts 4695 * as MSI/MSI-X interrupts are never shared. 4696 */ 4697 rle = resource_list_find(&dinfo->resources, 4698 SYS_RES_IRQ, 0); 4699 if (rle != NULL && rle->res != NULL) 4700 (void)bus_suspend_intr(child, rle->res); 4701 pci_set_power_child(dev, child, PCI_POWERSTATE_D3); 4702 } 4703 4704 return (0); 4705 } 4706 4707 int 4708 pci_resume_child(device_t dev, device_t child) 4709 { 4710 struct pci_devinfo *dinfo; 4711 struct resource_list_entry *rle; 4712 4713 if (pci_do_power_resume) 4714 pci_set_power_child(dev, child, PCI_POWERSTATE_D0); 4715 4716 dinfo = device_get_ivars(child); 4717 pci_cfg_restore(child, dinfo); 4718 pci_clear_pme(child); 4719 if (!device_is_attached(child)) 4720 pci_cfg_save(child, dinfo, 1); 4721 4722 bus_generic_resume_child(dev, child); 4723 4724 /* 4725 * Allow interrupts only after fully resuming the driver and hardware. 4726 */ 4727 if (pci_do_power_suspend) { 4728 /* See pci_suspend_child for details. */ 4729 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 4730 if (rle != NULL && rle->res != NULL) 4731 (void)bus_resume_intr(child, rle->res); 4732 } 4733 4734 return (0); 4735 } 4736 4737 int 4738 pci_resume(device_t dev) 4739 { 4740 device_t child, *devlist; 4741 int error, i, numdevs; 4742 4743 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 4744 return (error); 4745 4746 /* 4747 * Resume critical devices first, then everything else later. 4748 */ 4749 for (i = 0; i < numdevs; i++) { 4750 child = devlist[i]; 4751 switch (pci_get_class(child)) { 4752 case PCIC_DISPLAY: 4753 case PCIC_MEMORY: 4754 case PCIC_BRIDGE: 4755 case PCIC_BASEPERIPH: 4756 BUS_RESUME_CHILD(dev, child); 4757 break; 4758 } 4759 } 4760 for (i = 0; i < numdevs; i++) { 4761 child = devlist[i]; 4762 switch (pci_get_class(child)) { 4763 case PCIC_DISPLAY: 4764 case PCIC_MEMORY: 4765 case PCIC_BRIDGE: 4766 case PCIC_BASEPERIPH: 4767 break; 4768 default: 4769 BUS_RESUME_CHILD(dev, child); 4770 } 4771 } 4772 free(devlist, M_TEMP); 4773 return (0); 4774 } 4775 4776 static void 4777 pci_load_vendor_data(void) 4778 { 4779 caddr_t data; 4780 void *ptr; 4781 size_t sz; 4782 4783 data = preload_search_by_type("pci_vendor_data"); 4784 if (data != NULL) { 4785 ptr = preload_fetch_addr(data); 4786 sz = preload_fetch_size(data); 4787 if (ptr != NULL && sz != 0) { 4788 pci_vendordata = ptr; 4789 pci_vendordata_size = sz; 4790 /* terminate the database */ 4791 pci_vendordata[pci_vendordata_size] = '\n'; 4792 } 4793 } 4794 } 4795 4796 void 4797 pci_driver_added(device_t dev, driver_t *driver) 4798 { 4799 int numdevs; 4800 device_t *devlist; 4801 device_t child; 4802 struct pci_devinfo *dinfo; 4803 int i; 4804 4805 if (bootverbose) 4806 device_printf(dev, "driver added\n"); 4807 DEVICE_IDENTIFY(driver, dev); 4808 if (device_get_children(dev, &devlist, &numdevs) != 0) 4809 return; 4810 for (i = 0; i < numdevs; i++) { 4811 child = devlist[i]; 4812 if (device_get_state(child) != DS_NOTPRESENT) 4813 continue; 4814 dinfo = device_get_ivars(child); 4815 pci_print_verbose(dinfo); 4816 if (bootverbose) 4817 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); 4818 pci_cfg_restore(child, dinfo); 4819 if (device_probe_and_attach(child) != 0) 4820 pci_child_detached(dev, child); 4821 } 4822 free(devlist, M_TEMP); 4823 } 4824 4825 int 4826 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, 4827 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep) 4828 { 4829 struct pci_devinfo *dinfo; 4830 struct msix_table_entry *mte; 4831 struct msix_vector *mv; 4832 uint64_t addr; 4833 uint32_t data; 4834 void *cookie; 4835 int error, rid; 4836 4837 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr, 4838 arg, &cookie); 4839 if (error) 4840 return (error); 4841 4842 /* If this is not a direct child, just bail out. */ 4843 if (device_get_parent(child) != dev) { 4844 *cookiep = cookie; 4845 return(0); 4846 } 4847 4848 rid = rman_get_rid(irq); 4849 if (rid == 0) { 4850 /* Make sure that INTx is enabled */ 4851 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4852 } else { 4853 /* 4854 * Check to see if the interrupt is MSI or MSI-X. 4855 * Ask our parent to map the MSI and give 4856 * us the address and data register values. 4857 * If we fail for some reason, teardown the 4858 * interrupt handler. 4859 */ 4860 dinfo = device_get_ivars(child); 4861 if (dinfo->cfg.msi.msi_alloc > 0) { 4862 if (dinfo->cfg.msi.msi_addr == 0) { 4863 KASSERT(dinfo->cfg.msi.msi_handlers == 0, 4864 ("MSI has handlers, but vectors not mapped")); 4865 error = PCIB_MAP_MSI(device_get_parent(dev), 4866 child, rman_get_start(irq), &addr, &data); 4867 if (error) 4868 goto bad; 4869 dinfo->cfg.msi.msi_addr = addr; 4870 dinfo->cfg.msi.msi_data = data; 4871 } 4872 if (dinfo->cfg.msi.msi_handlers == 0) 4873 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, 4874 dinfo->cfg.msi.msi_data); 4875 dinfo->cfg.msi.msi_handlers++; 4876 } else { 4877 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4878 ("No MSI or MSI-X interrupts allocated")); 4879 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4880 ("MSI-X index too high")); 4881 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4882 KASSERT(mte->mte_vector != 0, ("no message vector")); 4883 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; 4884 KASSERT(mv->mv_irq == rman_get_start(irq), 4885 ("IRQ mismatch")); 4886 if (mv->mv_address == 0) { 4887 KASSERT(mte->mte_handlers == 0, 4888 ("MSI-X table entry has handlers, but vector not mapped")); 4889 error = PCIB_MAP_MSI(device_get_parent(dev), 4890 child, rman_get_start(irq), &addr, &data); 4891 if (error) 4892 goto bad; 4893 mv->mv_address = addr; 4894 mv->mv_data = data; 4895 } 4896 4897 /* 4898 * The MSIX table entry must be made valid by 4899 * incrementing the mte_handlers before 4900 * calling pci_enable_msix() and 4901 * pci_resume_msix(). Else the MSIX rewrite 4902 * table quirk will not work as expected. 4903 */ 4904 mte->mte_handlers++; 4905 if (mte->mte_handlers == 1) { 4906 pci_enable_msix(child, rid - 1, mv->mv_address, 4907 mv->mv_data); 4908 pci_unmask_msix(child, rid - 1); 4909 } 4910 } 4911 4912 /* 4913 * Make sure that INTx is disabled if we are using MSI/MSI-X, 4914 * unless the device is affected by PCI_QUIRK_MSI_INTX_BUG, 4915 * in which case we "enable" INTx so MSI/MSI-X actually works. 4916 */ 4917 if (!pci_has_quirk(pci_get_devid(child), 4918 PCI_QUIRK_MSI_INTX_BUG)) 4919 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4920 else 4921 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4922 bad: 4923 if (error) { 4924 (void)bus_generic_teardown_intr(dev, child, irq, 4925 cookie); 4926 return (error); 4927 } 4928 } 4929 *cookiep = cookie; 4930 return (0); 4931 } 4932 4933 int 4934 pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 4935 void *cookie) 4936 { 4937 struct msix_table_entry *mte; 4938 struct resource_list_entry *rle; 4939 struct pci_devinfo *dinfo; 4940 int error, rid; 4941 4942 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE)) 4943 return (EINVAL); 4944 4945 /* If this isn't a direct child, just bail out */ 4946 if (device_get_parent(child) != dev) 4947 return(bus_generic_teardown_intr(dev, child, irq, cookie)); 4948 4949 rid = rman_get_rid(irq); 4950 if (rid == 0) { 4951 /* Mask INTx */ 4952 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4953 } else { 4954 /* 4955 * Check to see if the interrupt is MSI or MSI-X. If so, 4956 * decrement the appropriate handlers count and mask the 4957 * MSI-X message, or disable MSI messages if the count 4958 * drops to 0. 4959 */ 4960 dinfo = device_get_ivars(child); 4961 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); 4962 if (rle->res != irq) 4963 return (EINVAL); 4964 if (dinfo->cfg.msi.msi_alloc > 0) { 4965 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, 4966 ("MSI-X index too high")); 4967 if (dinfo->cfg.msi.msi_handlers == 0) 4968 return (EINVAL); 4969 dinfo->cfg.msi.msi_handlers--; 4970 if (dinfo->cfg.msi.msi_handlers == 0) 4971 pci_disable_msi(child); 4972 } else { 4973 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4974 ("No MSI or MSI-X interrupts allocated")); 4975 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4976 ("MSI-X index too high")); 4977 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4978 if (mte->mte_handlers == 0) 4979 return (EINVAL); 4980 mte->mte_handlers--; 4981 if (mte->mte_handlers == 0) 4982 pci_mask_msix(child, rid - 1); 4983 } 4984 } 4985 error = bus_generic_teardown_intr(dev, child, irq, cookie); 4986 if (rid > 0) 4987 KASSERT(error == 0, 4988 ("%s: generic teardown failed for MSI/MSI-X", __func__)); 4989 return (error); 4990 } 4991 4992 int 4993 pci_print_child(device_t dev, device_t child) 4994 { 4995 struct pci_devinfo *dinfo; 4996 struct resource_list *rl; 4997 int retval = 0; 4998 4999 dinfo = device_get_ivars(child); 5000 rl = &dinfo->resources; 5001 5002 retval += bus_print_child_header(dev, child); 5003 5004 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#jx"); 5005 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 5006 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 5007 if (device_get_flags(dev)) 5008 retval += printf(" flags %#x", device_get_flags(dev)); 5009 5010 retval += printf(" at device %d.%d", pci_get_slot(child), 5011 pci_get_function(child)); 5012 5013 retval += bus_print_child_domain(dev, child); 5014 retval += bus_print_child_footer(dev, child); 5015 5016 return (retval); 5017 } 5018 5019 static const struct 5020 { 5021 int class; 5022 int subclass; 5023 int report; /* 0 = bootverbose, 1 = always */ 5024 const char *desc; 5025 } pci_nomatch_tab[] = { 5026 {PCIC_OLD, -1, 1, "old"}, 5027 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"}, 5028 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"}, 5029 {PCIC_STORAGE, -1, 1, "mass storage"}, 5030 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"}, 5031 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"}, 5032 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"}, 5033 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"}, 5034 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"}, 5035 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"}, 5036 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"}, 5037 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"}, 5038 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"}, 5039 {PCIC_NETWORK, -1, 1, "network"}, 5040 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"}, 5041 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"}, 5042 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"}, 5043 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"}, 5044 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"}, 5045 {PCIC_DISPLAY, -1, 1, "display"}, 5046 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"}, 5047 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"}, 5048 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"}, 5049 {PCIC_MULTIMEDIA, -1, 1, "multimedia"}, 5050 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"}, 5051 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"}, 5052 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"}, 5053 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"}, 5054 {PCIC_MEMORY, -1, 1, "memory"}, 5055 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"}, 5056 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"}, 5057 {PCIC_BRIDGE, -1, 1, "bridge"}, 5058 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"}, 5059 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"}, 5060 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"}, 5061 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"}, 5062 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"}, 5063 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"}, 5064 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"}, 5065 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"}, 5066 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"}, 5067 {PCIC_SIMPLECOMM, -1, 1, "simple comms"}, 5068 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */ 5069 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"}, 5070 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"}, 5071 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"}, 5072 {PCIC_BASEPERIPH, -1, 0, "base peripheral"}, 5073 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"}, 5074 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"}, 5075 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"}, 5076 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"}, 5077 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"}, 5078 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"}, 5079 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"}, 5080 {PCIC_INPUTDEV, -1, 1, "input device"}, 5081 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"}, 5082 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"}, 5083 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"}, 5084 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"}, 5085 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"}, 5086 {PCIC_DOCKING, -1, 1, "docking station"}, 5087 {PCIC_PROCESSOR, -1, 1, "processor"}, 5088 {PCIC_SERIALBUS, -1, 1, "serial bus"}, 5089 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"}, 5090 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"}, 5091 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"}, 5092 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"}, 5093 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"}, 5094 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"}, 5095 {PCIC_WIRELESS, -1, 1, "wireless controller"}, 5096 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"}, 5097 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"}, 5098 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"}, 5099 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"}, 5100 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"}, 5101 {PCIC_SATCOM, -1, 1, "satellite communication"}, 5102 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"}, 5103 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"}, 5104 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"}, 5105 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"}, 5106 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"}, 5107 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"}, 5108 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"}, 5109 {PCIC_DASP, -1, 0, "dasp"}, 5110 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"}, 5111 {PCIC_DASP, PCIS_DASP_PERFCNTRS, 1, "performance counters"}, 5112 {PCIC_DASP, PCIS_DASP_COMM_SYNC, 1, "communication synchronizer"}, 5113 {PCIC_DASP, PCIS_DASP_MGMT_CARD, 1, "signal processing management"}, 5114 {PCIC_INSTRUMENT, -1, 0, "non-essential instrumentation"}, 5115 {0, 0, 0, NULL} 5116 }; 5117 5118 void 5119 pci_probe_nomatch(device_t dev, device_t child) 5120 { 5121 int i, report; 5122 const char *cp, *scp; 5123 char *device; 5124 5125 /* 5126 * Look for a listing for this device in a loaded device database. 5127 */ 5128 report = 1; 5129 if ((device = pci_describe_device(child)) != NULL) { 5130 device_printf(dev, "<%s>", device); 5131 free(device, M_DEVBUF); 5132 } else { 5133 /* 5134 * Scan the class/subclass descriptions for a general 5135 * description. 5136 */ 5137 cp = "unknown"; 5138 scp = NULL; 5139 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 5140 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 5141 if (pci_nomatch_tab[i].subclass == -1) { 5142 cp = pci_nomatch_tab[i].desc; 5143 report = pci_nomatch_tab[i].report; 5144 } else if (pci_nomatch_tab[i].subclass == 5145 pci_get_subclass(child)) { 5146 scp = pci_nomatch_tab[i].desc; 5147 report = pci_nomatch_tab[i].report; 5148 } 5149 } 5150 } 5151 if (report || bootverbose) { 5152 device_printf(dev, "<%s%s%s>", 5153 cp ? cp : "", 5154 ((cp != NULL) && (scp != NULL)) ? ", " : "", 5155 scp ? scp : ""); 5156 } 5157 } 5158 if (report || bootverbose) { 5159 printf(" at device %d.%d (no driver attached)\n", 5160 pci_get_slot(child), pci_get_function(child)); 5161 } 5162 pci_cfg_save(child, device_get_ivars(child), 1); 5163 } 5164 5165 void 5166 pci_child_detached(device_t dev, device_t child) 5167 { 5168 struct pci_devinfo *dinfo; 5169 struct resource_list *rl; 5170 5171 dinfo = device_get_ivars(child); 5172 rl = &dinfo->resources; 5173 5174 /* 5175 * Have to deallocate IRQs before releasing any MSI messages and 5176 * have to release MSI messages before deallocating any memory 5177 * BARs. 5178 */ 5179 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0) 5180 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); 5181 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { 5182 if (dinfo->cfg.msi.msi_alloc != 0) 5183 pci_printf(&dinfo->cfg, "Device leaked %d MSI " 5184 "vectors\n", dinfo->cfg.msi.msi_alloc); 5185 else 5186 pci_printf(&dinfo->cfg, "Device leaked %d MSI-X " 5187 "vectors\n", dinfo->cfg.msix.msix_alloc); 5188 (void)pci_release_msi(child); 5189 } 5190 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0) 5191 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); 5192 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0) 5193 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); 5194 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0) 5195 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); 5196 5197 pci_cfg_save(child, dinfo, 1); 5198 } 5199 5200 /* 5201 * Parse the PCI device database, if loaded, and return a pointer to a 5202 * description of the device. 5203 * 5204 * The database is flat text formatted as follows: 5205 * 5206 * Any line not in a valid format is ignored. 5207 * Lines are terminated with newline '\n' characters. 5208 * 5209 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 5210 * the vendor name. 5211 * 5212 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 5213 * - devices cannot be listed without a corresponding VENDOR line. 5214 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 5215 * another TAB, then the device name. 5216 */ 5217 5218 /* 5219 * Assuming (ptr) points to the beginning of a line in the database, 5220 * return the vendor or device and description of the next entry. 5221 * The value of (vendor) or (device) inappropriate for the entry type 5222 * is set to -1. Returns nonzero at the end of the database. 5223 * 5224 * Note that this is slightly unrobust in the face of corrupt data; 5225 * we attempt to safeguard against this by spamming the end of the 5226 * database with a newline when we initialise. 5227 */ 5228 static int 5229 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 5230 { 5231 char *cp = *ptr; 5232 int left; 5233 5234 *device = -1; 5235 *vendor = -1; 5236 **desc = '\0'; 5237 for (;;) { 5238 left = pci_vendordata_size - (cp - pci_vendordata); 5239 if (left <= 0) { 5240 *ptr = cp; 5241 return(1); 5242 } 5243 5244 /* vendor entry? */ 5245 if (*cp != '\t' && 5246 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 5247 break; 5248 /* device entry? */ 5249 if (*cp == '\t' && 5250 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 5251 break; 5252 5253 /* skip to next line */ 5254 while (*cp != '\n' && left > 0) { 5255 cp++; 5256 left--; 5257 } 5258 if (*cp == '\n') { 5259 cp++; 5260 left--; 5261 } 5262 } 5263 /* skip to next line */ 5264 while (*cp != '\n' && left > 0) { 5265 cp++; 5266 left--; 5267 } 5268 if (*cp == '\n' && left > 0) 5269 cp++; 5270 *ptr = cp; 5271 return(0); 5272 } 5273 5274 static char * 5275 pci_describe_device(device_t dev) 5276 { 5277 int vendor, device; 5278 char *desc, *vp, *dp, *line; 5279 5280 desc = vp = dp = NULL; 5281 5282 /* 5283 * If we have no vendor data, we can't do anything. 5284 */ 5285 if (pci_vendordata == NULL) 5286 goto out; 5287 5288 /* 5289 * Scan the vendor data looking for this device 5290 */ 5291 line = pci_vendordata; 5292 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5293 goto out; 5294 for (;;) { 5295 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 5296 goto out; 5297 if (vendor == pci_get_vendor(dev)) 5298 break; 5299 } 5300 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5301 goto out; 5302 for (;;) { 5303 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 5304 *dp = 0; 5305 break; 5306 } 5307 if (vendor != -1) { 5308 *dp = 0; 5309 break; 5310 } 5311 if (device == pci_get_device(dev)) 5312 break; 5313 } 5314 if (dp[0] == '\0') 5315 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 5316 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 5317 NULL) 5318 sprintf(desc, "%s, %s", vp, dp); 5319 out: 5320 if (vp != NULL) 5321 free(vp, M_DEVBUF); 5322 if (dp != NULL) 5323 free(dp, M_DEVBUF); 5324 return(desc); 5325 } 5326 5327 int 5328 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 5329 { 5330 struct pci_devinfo *dinfo; 5331 pcicfgregs *cfg; 5332 5333 dinfo = device_get_ivars(child); 5334 cfg = &dinfo->cfg; 5335 5336 switch (which) { 5337 case PCI_IVAR_ETHADDR: 5338 /* 5339 * The generic accessor doesn't deal with failure, so 5340 * we set the return value, then return an error. 5341 */ 5342 *((uint8_t **) result) = NULL; 5343 return (EINVAL); 5344 case PCI_IVAR_SUBVENDOR: 5345 *result = cfg->subvendor; 5346 break; 5347 case PCI_IVAR_SUBDEVICE: 5348 *result = cfg->subdevice; 5349 break; 5350 case PCI_IVAR_VENDOR: 5351 *result = cfg->vendor; 5352 break; 5353 case PCI_IVAR_DEVICE: 5354 *result = cfg->device; 5355 break; 5356 case PCI_IVAR_DEVID: 5357 *result = (cfg->device << 16) | cfg->vendor; 5358 break; 5359 case PCI_IVAR_CLASS: 5360 *result = cfg->baseclass; 5361 break; 5362 case PCI_IVAR_SUBCLASS: 5363 *result = cfg->subclass; 5364 break; 5365 case PCI_IVAR_PROGIF: 5366 *result = cfg->progif; 5367 break; 5368 case PCI_IVAR_REVID: 5369 *result = cfg->revid; 5370 break; 5371 case PCI_IVAR_INTPIN: 5372 *result = cfg->intpin; 5373 break; 5374 case PCI_IVAR_IRQ: 5375 *result = cfg->intline; 5376 break; 5377 case PCI_IVAR_DOMAIN: 5378 *result = cfg->domain; 5379 break; 5380 case PCI_IVAR_BUS: 5381 *result = cfg->bus; 5382 break; 5383 case PCI_IVAR_SLOT: 5384 *result = cfg->slot; 5385 break; 5386 case PCI_IVAR_FUNCTION: 5387 *result = cfg->func; 5388 break; 5389 case PCI_IVAR_CMDREG: 5390 *result = cfg->cmdreg; 5391 break; 5392 case PCI_IVAR_CACHELNSZ: 5393 *result = cfg->cachelnsz; 5394 break; 5395 case PCI_IVAR_MINGNT: 5396 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5397 *result = -1; 5398 return (EINVAL); 5399 } 5400 *result = cfg->mingnt; 5401 break; 5402 case PCI_IVAR_MAXLAT: 5403 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5404 *result = -1; 5405 return (EINVAL); 5406 } 5407 *result = cfg->maxlat; 5408 break; 5409 case PCI_IVAR_LATTIMER: 5410 *result = cfg->lattimer; 5411 break; 5412 default: 5413 return (ENOENT); 5414 } 5415 return (0); 5416 } 5417 5418 int 5419 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 5420 { 5421 struct pci_devinfo *dinfo; 5422 5423 dinfo = device_get_ivars(child); 5424 5425 switch (which) { 5426 case PCI_IVAR_INTPIN: 5427 dinfo->cfg.intpin = value; 5428 return (0); 5429 case PCI_IVAR_ETHADDR: 5430 case PCI_IVAR_SUBVENDOR: 5431 case PCI_IVAR_SUBDEVICE: 5432 case PCI_IVAR_VENDOR: 5433 case PCI_IVAR_DEVICE: 5434 case PCI_IVAR_DEVID: 5435 case PCI_IVAR_CLASS: 5436 case PCI_IVAR_SUBCLASS: 5437 case PCI_IVAR_PROGIF: 5438 case PCI_IVAR_REVID: 5439 case PCI_IVAR_IRQ: 5440 case PCI_IVAR_DOMAIN: 5441 case PCI_IVAR_BUS: 5442 case PCI_IVAR_SLOT: 5443 case PCI_IVAR_FUNCTION: 5444 return (EINVAL); /* disallow for now */ 5445 5446 default: 5447 return (ENOENT); 5448 } 5449 } 5450 5451 #include "opt_ddb.h" 5452 #ifdef DDB 5453 #include <ddb/ddb.h> 5454 #include <sys/cons.h> 5455 5456 /* 5457 * List resources based on pci map registers, used for within ddb 5458 */ 5459 5460 DB_SHOW_COMMAND_FLAGS(pciregs, db_pci_dump, DB_CMD_MEMSAFE) 5461 { 5462 struct pci_devinfo *dinfo; 5463 struct devlist *devlist_head; 5464 struct pci_conf *p; 5465 const char *name; 5466 int i, error, none_count; 5467 5468 none_count = 0; 5469 /* get the head of the device queue */ 5470 devlist_head = &pci_devq; 5471 5472 /* 5473 * Go through the list of devices and print out devices 5474 */ 5475 for (error = 0, i = 0, 5476 dinfo = STAILQ_FIRST(devlist_head); 5477 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 5478 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 5479 /* Populate pd_name and pd_unit */ 5480 name = NULL; 5481 if (dinfo->cfg.dev) 5482 name = device_get_name(dinfo->cfg.dev); 5483 5484 p = &dinfo->conf; 5485 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x " 5486 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 5487 (name && *name) ? name : "none", 5488 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 5489 none_count++, 5490 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, 5491 p->pc_sel.pc_func, (p->pc_class << 16) | 5492 (p->pc_subclass << 8) | p->pc_progif, 5493 (p->pc_subdevice << 16) | p->pc_subvendor, 5494 (p->pc_device << 16) | p->pc_vendor, 5495 p->pc_revid, p->pc_hdr); 5496 } 5497 } 5498 #endif /* DDB */ 5499 5500 struct resource * 5501 pci_reserve_map(device_t dev, device_t child, int type, int *rid, 5502 rman_res_t start, rman_res_t end, rman_res_t count, u_int num, 5503 u_int flags) 5504 { 5505 struct pci_devinfo *dinfo = device_get_ivars(child); 5506 struct resource_list *rl = &dinfo->resources; 5507 struct resource *res; 5508 struct pci_map *pm; 5509 uint16_t cmd; 5510 pci_addr_t map, testval; 5511 int mapsize; 5512 5513 res = NULL; 5514 5515 /* If rid is managed by EA, ignore it */ 5516 if (pci_ea_is_enabled(child, *rid)) 5517 goto out; 5518 5519 pm = pci_find_bar(child, *rid); 5520 if (pm != NULL) { 5521 /* This is a BAR that we failed to allocate earlier. */ 5522 mapsize = pm->pm_size; 5523 map = pm->pm_value; 5524 } else { 5525 /* 5526 * Weed out the bogons, and figure out how large the 5527 * BAR/map is. BARs that read back 0 here are bogus 5528 * and unimplemented. Note: atapci in legacy mode are 5529 * special and handled elsewhere in the code. If you 5530 * have a atapci device in legacy mode and it fails 5531 * here, that other code is broken. 5532 */ 5533 pci_read_bar(child, *rid, &map, &testval, NULL); 5534 5535 /* 5536 * Determine the size of the BAR and ignore BARs with a size 5537 * of 0. Device ROM BARs use a different mask value. 5538 */ 5539 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) 5540 mapsize = pci_romsize(testval); 5541 else 5542 mapsize = pci_mapsize(testval); 5543 if (mapsize == 0) 5544 goto out; 5545 pm = pci_add_bar(child, *rid, map, mapsize); 5546 } 5547 5548 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { 5549 if (type != SYS_RES_MEMORY) { 5550 if (bootverbose) 5551 device_printf(dev, 5552 "child %s requested type %d for rid %#x," 5553 " but the BAR says it is an memio\n", 5554 device_get_nameunit(child), type, *rid); 5555 goto out; 5556 } 5557 } else { 5558 if (type != SYS_RES_IOPORT) { 5559 if (bootverbose) 5560 device_printf(dev, 5561 "child %s requested type %d for rid %#x," 5562 " but the BAR says it is an ioport\n", 5563 device_get_nameunit(child), type, *rid); 5564 goto out; 5565 } 5566 } 5567 5568 /* 5569 * For real BARs, we need to override the size that 5570 * the driver requests, because that's what the BAR 5571 * actually uses and we would otherwise have a 5572 * situation where we might allocate the excess to 5573 * another driver, which won't work. 5574 */ 5575 count = ((pci_addr_t)1 << mapsize) * num; 5576 if (RF_ALIGNMENT(flags) < mapsize) 5577 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 5578 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH)) 5579 flags |= RF_PREFETCHABLE; 5580 5581 /* 5582 * Allocate enough resource, and then write back the 5583 * appropriate BAR for that resource. 5584 */ 5585 resource_list_add(rl, type, *rid, start, end, count); 5586 res = resource_list_reserve(rl, dev, child, type, rid, start, end, 5587 count, flags & ~RF_ACTIVE); 5588 if (res == NULL) { 5589 resource_list_delete(rl, type, *rid); 5590 device_printf(child, 5591 "%#jx bytes of rid %#x res %d failed (%#jx, %#jx).\n", 5592 count, *rid, type, start, end); 5593 goto out; 5594 } 5595 if (bootverbose) 5596 device_printf(child, 5597 "Lazy allocation of %#jx bytes rid %#x type %d at %#jx\n", 5598 count, *rid, type, rman_get_start(res)); 5599 5600 /* Disable decoding via the CMD register before updating the BAR */ 5601 cmd = pci_read_config(child, PCIR_COMMAND, 2); 5602 pci_write_config(child, PCIR_COMMAND, 5603 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 5604 5605 map = rman_get_start(res); 5606 pci_write_bar(child, pm, map); 5607 5608 /* Restore the original value of the CMD register */ 5609 pci_write_config(child, PCIR_COMMAND, cmd, 2); 5610 out: 5611 return (res); 5612 } 5613 5614 struct resource * 5615 pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid, 5616 rman_res_t start, rman_res_t end, rman_res_t count, u_long num, 5617 u_int flags) 5618 { 5619 struct pci_devinfo *dinfo; 5620 struct resource_list *rl; 5621 struct resource_list_entry *rle; 5622 struct resource *res; 5623 pcicfgregs *cfg; 5624 5625 /* 5626 * Perform lazy resource allocation 5627 */ 5628 dinfo = device_get_ivars(child); 5629 rl = &dinfo->resources; 5630 cfg = &dinfo->cfg; 5631 switch (type) { 5632 case PCI_RES_BUS: 5633 return (pci_alloc_secbus(dev, child, rid, start, end, count, 5634 flags)); 5635 case SYS_RES_IRQ: 5636 /* 5637 * Can't alloc legacy interrupt once MSI messages have 5638 * been allocated. 5639 */ 5640 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 5641 cfg->msix.msix_alloc > 0)) 5642 return (NULL); 5643 5644 /* 5645 * If the child device doesn't have an interrupt 5646 * routed and is deserving of an interrupt, try to 5647 * assign it one. 5648 */ 5649 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 5650 (cfg->intpin != 0)) 5651 pci_assign_interrupt(dev, child, 0); 5652 break; 5653 case SYS_RES_IOPORT: 5654 case SYS_RES_MEMORY: 5655 /* 5656 * PCI-PCI bridge I/O window resources are not BARs. 5657 * For those allocations just pass the request up the 5658 * tree. 5659 */ 5660 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { 5661 switch (*rid) { 5662 case PCIR_IOBASEL_1: 5663 case PCIR_MEMBASE_1: 5664 case PCIR_PMBASEL_1: 5665 /* 5666 * XXX: Should we bother creating a resource 5667 * list entry? 5668 */ 5669 return (bus_generic_alloc_resource(dev, child, 5670 type, rid, start, end, count, flags)); 5671 } 5672 } 5673 /* Reserve resources for this BAR if needed. */ 5674 rle = resource_list_find(rl, type, *rid); 5675 if (rle == NULL) { 5676 res = pci_reserve_map(dev, child, type, rid, start, end, 5677 count, num, flags); 5678 if (res == NULL) 5679 return (NULL); 5680 } 5681 } 5682 return (resource_list_alloc(rl, dev, child, type, rid, 5683 start, end, count, flags)); 5684 } 5685 5686 struct resource * 5687 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 5688 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 5689 { 5690 #ifdef PCI_IOV 5691 struct pci_devinfo *dinfo; 5692 #endif 5693 5694 if (device_get_parent(child) != dev) 5695 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 5696 type, rid, start, end, count, flags)); 5697 5698 #ifdef PCI_IOV 5699 dinfo = device_get_ivars(child); 5700 if (dinfo->cfg.flags & PCICFG_VF) { 5701 switch (type) { 5702 /* VFs can't have I/O BARs. */ 5703 case SYS_RES_IOPORT: 5704 return (NULL); 5705 case SYS_RES_MEMORY: 5706 return (pci_vf_alloc_mem_resource(dev, child, rid, 5707 start, end, count, flags)); 5708 } 5709 5710 /* Fall through for other types of resource allocations. */ 5711 } 5712 #endif 5713 5714 return (pci_alloc_multi_resource(dev, child, type, rid, start, end, 5715 count, 1, flags)); 5716 } 5717 5718 int 5719 pci_release_resource(device_t dev, device_t child, struct resource *r) 5720 { 5721 struct pci_devinfo *dinfo; 5722 struct resource_list *rl; 5723 pcicfgregs *cfg __unused; 5724 5725 if (device_get_parent(child) != dev) 5726 return (bus_generic_release_resource(dev, child, r)); 5727 5728 dinfo = device_get_ivars(child); 5729 cfg = &dinfo->cfg; 5730 5731 #ifdef PCI_IOV 5732 if (cfg->flags & PCICFG_VF) { 5733 switch (rman_get_type(r)) { 5734 /* VFs can't have I/O BARs. */ 5735 case SYS_RES_IOPORT: 5736 return (EDOOFUS); 5737 case SYS_RES_MEMORY: 5738 return (pci_vf_release_mem_resource(dev, child, r)); 5739 } 5740 5741 /* Fall through for other types of resource allocations. */ 5742 } 5743 #endif 5744 5745 /* 5746 * PCI-PCI bridge I/O window resources are not BARs. For 5747 * those allocations just pass the request up the tree. 5748 */ 5749 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && 5750 (rman_get_type(r) == SYS_RES_IOPORT || 5751 rman_get_type(r) == SYS_RES_MEMORY)) { 5752 switch (rman_get_rid(r)) { 5753 case PCIR_IOBASEL_1: 5754 case PCIR_MEMBASE_1: 5755 case PCIR_PMBASEL_1: 5756 return (bus_generic_release_resource(dev, child, r)); 5757 } 5758 } 5759 5760 rl = &dinfo->resources; 5761 return (resource_list_release(rl, dev, child, r)); 5762 } 5763 5764 int 5765 pci_activate_resource(device_t dev, device_t child, struct resource *r) 5766 { 5767 struct pci_devinfo *dinfo; 5768 int error, rid, type; 5769 5770 if (device_get_parent(child) != dev) 5771 return (bus_generic_activate_resource(dev, child, r)); 5772 5773 dinfo = device_get_ivars(child); 5774 #ifdef PCI_IOV 5775 if (dinfo->cfg.flags & PCICFG_VF) { 5776 switch (rman_get_type(r)) { 5777 /* VFs can't have I/O BARs. */ 5778 case SYS_RES_IOPORT: 5779 error = EINVAL; 5780 break; 5781 case SYS_RES_MEMORY: 5782 error = pci_vf_activate_mem_resource(dev, child, r); 5783 break; 5784 default: 5785 error = bus_generic_activate_resource(dev, child, r); 5786 break; 5787 } 5788 } else 5789 #endif 5790 error = bus_generic_activate_resource(dev, child, r); 5791 if (error) 5792 return (error); 5793 5794 rid = rman_get_rid(r); 5795 type = rman_get_type(r); 5796 5797 /* Device ROMs need their decoding explicitly enabled. */ 5798 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5799 pci_write_bar(child, pci_find_bar(child, rid), 5800 rman_get_start(r) | PCIM_BIOS_ENABLE); 5801 5802 /* Enable decoding in the command register when activating BARs. */ 5803 switch (type) { 5804 case SYS_RES_IOPORT: 5805 case SYS_RES_MEMORY: 5806 error = PCI_ENABLE_IO(dev, child, type); 5807 break; 5808 } 5809 return (error); 5810 } 5811 5812 int 5813 pci_deactivate_resource(device_t dev, device_t child, struct resource *r) 5814 { 5815 struct pci_devinfo *dinfo; 5816 int error, rid, type; 5817 5818 if (device_get_parent(child) != dev) 5819 return (bus_generic_deactivate_resource(dev, child, r)); 5820 5821 dinfo = device_get_ivars(child); 5822 #ifdef PCI_IOV 5823 if (dinfo->cfg.flags & PCICFG_VF) { 5824 switch (rman_get_type(r)) { 5825 /* VFs can't have I/O BARs. */ 5826 case SYS_RES_IOPORT: 5827 error = EINVAL; 5828 break; 5829 case SYS_RES_MEMORY: 5830 error = pci_vf_deactivate_mem_resource(dev, child, r); 5831 break; 5832 default: 5833 error = bus_generic_deactivate_resource(dev, child, r); 5834 break; 5835 } 5836 } else 5837 #endif 5838 error = bus_generic_deactivate_resource(dev, child, r); 5839 if (error) 5840 return (error); 5841 5842 /* Disable decoding for device ROMs. */ 5843 rid = rman_get_rid(r); 5844 type = rman_get_type(r); 5845 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5846 pci_write_bar(child, pci_find_bar(child, rid), 5847 rman_get_start(r)); 5848 return (0); 5849 } 5850 5851 int 5852 pci_adjust_resource(device_t dev, device_t child, struct resource *r, 5853 rman_res_t start, rman_res_t end) 5854 { 5855 #ifdef PCI_IOV 5856 struct pci_devinfo *dinfo; 5857 5858 if (device_get_parent(child) != dev) 5859 return (bus_generic_adjust_resource(dev, child, r, start, 5860 end)); 5861 5862 dinfo = device_get_ivars(child); 5863 if (dinfo->cfg.flags & PCICFG_VF) { 5864 switch (rman_get_type(r)) { 5865 /* VFs can't have I/O BARs. */ 5866 case SYS_RES_IOPORT: 5867 return (EINVAL); 5868 case SYS_RES_MEMORY: 5869 return (pci_vf_adjust_mem_resource(dev, child, r, 5870 start, end)); 5871 } 5872 5873 /* Fall through for other types of resource allocations. */ 5874 } 5875 #endif 5876 5877 return (bus_generic_adjust_resource(dev, child, r, start, end)); 5878 } 5879 5880 int 5881 pci_map_resource(device_t dev, device_t child, struct resource *r, 5882 struct resource_map_request *argsp, struct resource_map *map) 5883 { 5884 #ifdef PCI_IOV 5885 struct pci_devinfo *dinfo; 5886 5887 if (device_get_parent(child) != dev) 5888 return (bus_generic_map_resource(dev, child, r, argsp, 5889 map)); 5890 5891 dinfo = device_get_ivars(child); 5892 if (dinfo->cfg.flags & PCICFG_VF) { 5893 switch (rman_get_type(r)) { 5894 /* VFs can't have I/O BARs. */ 5895 case SYS_RES_IOPORT: 5896 return (EINVAL); 5897 case SYS_RES_MEMORY: 5898 return (pci_vf_map_mem_resource(dev, child, r, argsp, 5899 map)); 5900 } 5901 5902 /* Fall through for other types of resource allocations. */ 5903 } 5904 #endif 5905 5906 return (bus_generic_map_resource(dev, child, r, argsp, map)); 5907 } 5908 5909 int 5910 pci_unmap_resource(device_t dev, device_t child, struct resource *r, 5911 struct resource_map *map) 5912 { 5913 #ifdef PCI_IOV 5914 struct pci_devinfo *dinfo; 5915 5916 if (device_get_parent(child) != dev) 5917 return (bus_generic_unmap_resource(dev, child, r, map)); 5918 5919 dinfo = device_get_ivars(child); 5920 if (dinfo->cfg.flags & PCICFG_VF) { 5921 switch (rman_get_type(r)) { 5922 /* VFs can't have I/O BARs. */ 5923 case SYS_RES_IOPORT: 5924 return (EINVAL); 5925 case SYS_RES_MEMORY: 5926 return (pci_vf_unmap_mem_resource(dev, child, r, map)); 5927 } 5928 5929 /* Fall through for other types of resource allocations. */ 5930 } 5931 #endif 5932 5933 return (bus_generic_unmap_resource(dev, child, r, map)); 5934 } 5935 5936 void 5937 pci_child_deleted(device_t dev, device_t child) 5938 { 5939 struct resource_list_entry *rle; 5940 struct resource_list *rl; 5941 struct pci_devinfo *dinfo; 5942 5943 dinfo = device_get_ivars(child); 5944 rl = &dinfo->resources; 5945 5946 EVENTHANDLER_INVOKE(pci_delete_device, child); 5947 5948 /* Turn off access to resources we're about to free */ 5949 if (bus_child_present(child) != 0) { 5950 pci_write_config(child, PCIR_COMMAND, pci_read_config(child, 5951 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2); 5952 5953 pci_disable_busmaster(child); 5954 } 5955 5956 /* Free all allocated resources */ 5957 STAILQ_FOREACH(rle, rl, link) { 5958 if (rle->res) { 5959 if (rman_get_flags(rle->res) & RF_ACTIVE || 5960 resource_list_busy(rl, rle->type, rle->rid)) { 5961 pci_printf(&dinfo->cfg, 5962 "Resource still owned, oops. " 5963 "(type=%d, rid=%d, addr=%lx)\n", 5964 rle->type, rle->rid, 5965 rman_get_start(rle->res)); 5966 bus_release_resource(child, rle->type, rle->rid, 5967 rle->res); 5968 } 5969 resource_list_unreserve(rl, dev, child, rle->type, 5970 rle->rid); 5971 } 5972 } 5973 resource_list_free(rl); 5974 5975 pci_freecfg(dinfo); 5976 } 5977 5978 void 5979 pci_delete_resource(device_t dev, device_t child, int type, int rid) 5980 { 5981 struct pci_devinfo *dinfo; 5982 struct resource_list *rl; 5983 struct resource_list_entry *rle; 5984 5985 if (device_get_parent(child) != dev) 5986 return; 5987 5988 dinfo = device_get_ivars(child); 5989 rl = &dinfo->resources; 5990 rle = resource_list_find(rl, type, rid); 5991 if (rle == NULL) 5992 return; 5993 5994 if (rle->res) { 5995 if (rman_get_flags(rle->res) & RF_ACTIVE || 5996 resource_list_busy(rl, type, rid)) { 5997 device_printf(dev, "delete_resource: " 5998 "Resource still owned by child, oops. " 5999 "(type=%d, rid=%d, addr=%jx)\n", 6000 type, rid, rman_get_start(rle->res)); 6001 return; 6002 } 6003 resource_list_unreserve(rl, dev, child, type, rid); 6004 } 6005 resource_list_delete(rl, type, rid); 6006 } 6007 6008 struct resource_list * 6009 pci_get_resource_list (device_t dev, device_t child) 6010 { 6011 struct pci_devinfo *dinfo = device_get_ivars(child); 6012 6013 return (&dinfo->resources); 6014 } 6015 6016 #ifdef IOMMU 6017 bus_dma_tag_t 6018 pci_get_dma_tag(device_t bus, device_t dev) 6019 { 6020 bus_dma_tag_t tag; 6021 struct pci_softc *sc; 6022 6023 if (device_get_parent(dev) == bus) { 6024 /* try iommu and return if it works */ 6025 tag = iommu_get_dma_tag(bus, dev); 6026 } else 6027 tag = NULL; 6028 if (tag == NULL) { 6029 sc = device_get_softc(bus); 6030 tag = sc->sc_dma_tag; 6031 } 6032 return (tag); 6033 } 6034 #else 6035 bus_dma_tag_t 6036 pci_get_dma_tag(device_t bus, device_t dev) 6037 { 6038 struct pci_softc *sc = device_get_softc(bus); 6039 6040 return (sc->sc_dma_tag); 6041 } 6042 #endif 6043 6044 uint32_t 6045 pci_read_config_method(device_t dev, device_t child, int reg, int width) 6046 { 6047 struct pci_devinfo *dinfo = device_get_ivars(child); 6048 pcicfgregs *cfg = &dinfo->cfg; 6049 6050 #ifdef PCI_IOV 6051 /* 6052 * SR-IOV VFs don't implement the VID or DID registers, so we have to 6053 * emulate them here. 6054 */ 6055 if (cfg->flags & PCICFG_VF) { 6056 if (reg == PCIR_VENDOR) { 6057 switch (width) { 6058 case 4: 6059 return (cfg->device << 16 | cfg->vendor); 6060 case 2: 6061 return (cfg->vendor); 6062 case 1: 6063 return (cfg->vendor & 0xff); 6064 default: 6065 return (0xffffffff); 6066 } 6067 } else if (reg == PCIR_DEVICE) { 6068 switch (width) { 6069 /* Note that an unaligned 4-byte read is an error. */ 6070 case 2: 6071 return (cfg->device); 6072 case 1: 6073 return (cfg->device & 0xff); 6074 default: 6075 return (0xffffffff); 6076 } 6077 } 6078 } 6079 #endif 6080 6081 return (PCIB_READ_CONFIG(device_get_parent(dev), 6082 cfg->bus, cfg->slot, cfg->func, reg, width)); 6083 } 6084 6085 void 6086 pci_write_config_method(device_t dev, device_t child, int reg, 6087 uint32_t val, int width) 6088 { 6089 struct pci_devinfo *dinfo = device_get_ivars(child); 6090 pcicfgregs *cfg = &dinfo->cfg; 6091 6092 PCIB_WRITE_CONFIG(device_get_parent(dev), 6093 cfg->bus, cfg->slot, cfg->func, reg, val, width); 6094 } 6095 6096 int 6097 pci_child_location_method(device_t dev, device_t child, struct sbuf *sb) 6098 { 6099 6100 sbuf_printf(sb, "slot=%d function=%d dbsf=pci%d:%d:%d:%d", 6101 pci_get_slot(child), pci_get_function(child), pci_get_domain(child), 6102 pci_get_bus(child), pci_get_slot(child), pci_get_function(child)); 6103 return (0); 6104 } 6105 6106 int 6107 pci_child_pnpinfo_method(device_t dev, device_t child, struct sbuf *sb) 6108 { 6109 struct pci_devinfo *dinfo; 6110 pcicfgregs *cfg; 6111 6112 dinfo = device_get_ivars(child); 6113 cfg = &dinfo->cfg; 6114 sbuf_printf(sb, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 6115 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 6116 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 6117 cfg->progif); 6118 return (0); 6119 } 6120 6121 int 6122 pci_get_device_path_method(device_t bus, device_t child, const char *locator, 6123 struct sbuf *sb) 6124 { 6125 device_t parent = device_get_parent(bus); 6126 int rv; 6127 6128 if (strcmp(locator, BUS_LOCATOR_UEFI) == 0) { 6129 rv = bus_generic_get_device_path(parent, bus, locator, sb); 6130 if (rv == 0) { 6131 sbuf_printf(sb, "/Pci(0x%x,0x%x)", pci_get_slot(child), 6132 pci_get_function(child)); 6133 } 6134 return (0); 6135 } 6136 return (bus_generic_get_device_path(bus, child, locator, sb)); 6137 } 6138 6139 int 6140 pci_assign_interrupt_method(device_t dev, device_t child) 6141 { 6142 struct pci_devinfo *dinfo = device_get_ivars(child); 6143 pcicfgregs *cfg = &dinfo->cfg; 6144 6145 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 6146 cfg->intpin)); 6147 } 6148 6149 static void 6150 pci_lookup(void *arg, const char *name, device_t *dev) 6151 { 6152 long val; 6153 char *end; 6154 int domain, bus, slot, func; 6155 6156 if (*dev != NULL) 6157 return; 6158 6159 /* 6160 * Accept pciconf-style selectors of either pciD:B:S:F or 6161 * pciB:S:F. In the latter case, the domain is assumed to 6162 * be zero. 6163 */ 6164 if (strncmp(name, "pci", 3) != 0) 6165 return; 6166 val = strtol(name + 3, &end, 10); 6167 if (val < 0 || val > INT_MAX || *end != ':') 6168 return; 6169 domain = val; 6170 val = strtol(end + 1, &end, 10); 6171 if (val < 0 || val > INT_MAX || *end != ':') 6172 return; 6173 bus = val; 6174 val = strtol(end + 1, &end, 10); 6175 if (val < 0 || val > INT_MAX) 6176 return; 6177 slot = val; 6178 if (*end == ':') { 6179 val = strtol(end + 1, &end, 10); 6180 if (val < 0 || val > INT_MAX || *end != '\0') 6181 return; 6182 func = val; 6183 } else if (*end == '\0') { 6184 func = slot; 6185 slot = bus; 6186 bus = domain; 6187 domain = 0; 6188 } else 6189 return; 6190 6191 if (domain > PCI_DOMAINMAX || bus > PCI_BUSMAX || slot > PCI_SLOTMAX || 6192 func > PCIE_ARI_FUNCMAX || (slot != 0 && func > PCI_FUNCMAX)) 6193 return; 6194 6195 *dev = pci_find_dbsf(domain, bus, slot, func); 6196 } 6197 6198 static int 6199 pci_modevent(module_t mod, int what, void *arg) 6200 { 6201 static struct cdev *pci_cdev; 6202 static eventhandler_tag tag; 6203 6204 switch (what) { 6205 case MOD_LOAD: 6206 STAILQ_INIT(&pci_devq); 6207 pci_generation = 0; 6208 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 6209 "pci"); 6210 pci_load_vendor_data(); 6211 tag = EVENTHANDLER_REGISTER(dev_lookup, pci_lookup, NULL, 6212 1000); 6213 break; 6214 6215 case MOD_UNLOAD: 6216 if (tag != NULL) 6217 EVENTHANDLER_DEREGISTER(dev_lookup, tag); 6218 destroy_dev(pci_cdev); 6219 break; 6220 } 6221 6222 return (0); 6223 } 6224 6225 static void 6226 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo) 6227 { 6228 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2) 6229 struct pcicfg_pcie *cfg; 6230 int version, pos; 6231 6232 cfg = &dinfo->cfg.pcie; 6233 pos = cfg->pcie_location; 6234 6235 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6236 6237 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); 6238 6239 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6240 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6241 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6242 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); 6243 6244 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6245 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6246 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6247 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); 6248 6249 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6250 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6251 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); 6252 6253 if (version > 1) { 6254 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); 6255 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); 6256 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); 6257 } 6258 #undef WREG 6259 } 6260 6261 static void 6262 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo) 6263 { 6264 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 6265 dinfo->cfg.pcix.pcix_command, 2); 6266 } 6267 6268 void 6269 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 6270 { 6271 6272 /* 6273 * Restore the device to full power mode. We must do this 6274 * before we restore the registers because moving from D3 to 6275 * D0 will cause the chip's BARs and some other registers to 6276 * be reset to some unknown power on reset values. Cut down 6277 * the noise on boot by doing nothing if we are already in 6278 * state D0. 6279 */ 6280 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) 6281 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6282 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 6283 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 6284 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 6285 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 6286 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 6287 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 6288 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6289 case PCIM_HDRTYPE_NORMAL: 6290 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 6291 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 6292 break; 6293 case PCIM_HDRTYPE_BRIDGE: 6294 pci_write_config(dev, PCIR_SECLAT_1, 6295 dinfo->cfg.bridge.br_seclat, 1); 6296 pci_write_config(dev, PCIR_SUBBUS_1, 6297 dinfo->cfg.bridge.br_subbus, 1); 6298 pci_write_config(dev, PCIR_SECBUS_1, 6299 dinfo->cfg.bridge.br_secbus, 1); 6300 pci_write_config(dev, PCIR_PRIBUS_1, 6301 dinfo->cfg.bridge.br_pribus, 1); 6302 pci_write_config(dev, PCIR_BRIDGECTL_1, 6303 dinfo->cfg.bridge.br_control, 2); 6304 break; 6305 case PCIM_HDRTYPE_CARDBUS: 6306 pci_write_config(dev, PCIR_SECLAT_2, 6307 dinfo->cfg.bridge.br_seclat, 1); 6308 pci_write_config(dev, PCIR_SUBBUS_2, 6309 dinfo->cfg.bridge.br_subbus, 1); 6310 pci_write_config(dev, PCIR_SECBUS_2, 6311 dinfo->cfg.bridge.br_secbus, 1); 6312 pci_write_config(dev, PCIR_PRIBUS_2, 6313 dinfo->cfg.bridge.br_pribus, 1); 6314 pci_write_config(dev, PCIR_BRIDGECTL_2, 6315 dinfo->cfg.bridge.br_control, 2); 6316 break; 6317 } 6318 pci_restore_bars(dev); 6319 6320 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE) 6321 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 6322 6323 /* 6324 * Restore extended capabilities for PCI-Express and PCI-X 6325 */ 6326 if (dinfo->cfg.pcie.pcie_location != 0) 6327 pci_cfg_restore_pcie(dev, dinfo); 6328 if (dinfo->cfg.pcix.pcix_location != 0) 6329 pci_cfg_restore_pcix(dev, dinfo); 6330 6331 /* Restore MSI and MSI-X configurations if they are present. */ 6332 if (dinfo->cfg.msi.msi_location != 0) 6333 pci_resume_msi(dev); 6334 if (dinfo->cfg.msix.msix_location != 0) 6335 pci_resume_msix(dev); 6336 6337 #ifdef PCI_IOV 6338 if (dinfo->cfg.iov != NULL) 6339 pci_iov_cfg_restore(dev, dinfo); 6340 #endif 6341 } 6342 6343 static void 6344 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo) 6345 { 6346 #define RREG(n) pci_read_config(dev, pos + (n), 2) 6347 struct pcicfg_pcie *cfg; 6348 int version, pos; 6349 6350 cfg = &dinfo->cfg.pcie; 6351 pos = cfg->pcie_location; 6352 6353 cfg->pcie_flags = RREG(PCIER_FLAGS); 6354 6355 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6356 6357 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); 6358 6359 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6360 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6361 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6362 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); 6363 6364 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6365 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6366 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6367 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); 6368 6369 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6370 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6371 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); 6372 6373 if (version > 1) { 6374 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); 6375 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); 6376 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); 6377 } 6378 #undef RREG 6379 } 6380 6381 static void 6382 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo) 6383 { 6384 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, 6385 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); 6386 } 6387 6388 void 6389 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 6390 { 6391 uint32_t cls; 6392 int ps; 6393 6394 /* 6395 * Some drivers apparently write to these registers w/o updating our 6396 * cached copy. No harm happens if we update the copy, so do so here 6397 * so we can restore them. The COMMAND register is modified by the 6398 * bus w/o updating the cache. This should represent the normally 6399 * writable portion of the 'defined' part of type 0/1/2 headers. 6400 */ 6401 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 6402 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 6403 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 6404 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 6405 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 6406 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 6407 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 6408 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 6409 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 6410 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 6411 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 6412 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6413 case PCIM_HDRTYPE_NORMAL: 6414 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 6415 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 6416 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 6417 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 6418 break; 6419 case PCIM_HDRTYPE_BRIDGE: 6420 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6421 PCIR_SECLAT_1, 1); 6422 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6423 PCIR_SUBBUS_1, 1); 6424 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6425 PCIR_SECBUS_1, 1); 6426 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6427 PCIR_PRIBUS_1, 1); 6428 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6429 PCIR_BRIDGECTL_1, 2); 6430 break; 6431 case PCIM_HDRTYPE_CARDBUS: 6432 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6433 PCIR_SECLAT_2, 1); 6434 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6435 PCIR_SUBBUS_2, 1); 6436 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6437 PCIR_SECBUS_2, 1); 6438 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6439 PCIR_PRIBUS_2, 1); 6440 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6441 PCIR_BRIDGECTL_2, 2); 6442 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2); 6443 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2); 6444 break; 6445 } 6446 6447 if (dinfo->cfg.pcie.pcie_location != 0) 6448 pci_cfg_save_pcie(dev, dinfo); 6449 6450 if (dinfo->cfg.pcix.pcix_location != 0) 6451 pci_cfg_save_pcix(dev, dinfo); 6452 6453 #ifdef PCI_IOV 6454 if (dinfo->cfg.iov != NULL) 6455 pci_iov_cfg_save(dev, dinfo); 6456 #endif 6457 6458 /* 6459 * don't set the state for display devices, base peripherals and 6460 * memory devices since bad things happen when they are powered down. 6461 * We should (a) have drivers that can easily detach and (b) use 6462 * generic drivers for these devices so that some device actually 6463 * attaches. We need to make sure that when we implement (a) we don't 6464 * power the device down on a reattach. 6465 */ 6466 cls = pci_get_class(dev); 6467 if (!setstate) 6468 return; 6469 switch (pci_do_power_nodriver) 6470 { 6471 case 0: /* NO powerdown at all */ 6472 return; 6473 case 1: /* Conservative about what to power down */ 6474 if (cls == PCIC_STORAGE) 6475 return; 6476 /*FALLTHROUGH*/ 6477 case 2: /* Aggressive about what to power down */ 6478 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 6479 cls == PCIC_BASEPERIPH) 6480 return; 6481 /*FALLTHROUGH*/ 6482 case 3: /* Power down everything */ 6483 break; 6484 } 6485 /* 6486 * PCI spec says we can only go into D3 state from D0 state. 6487 * Transition from D[12] into D0 before going to D3 state. 6488 */ 6489 ps = pci_get_powerstate(dev); 6490 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6491 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6492 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 6493 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6494 } 6495 6496 /* Wrapper APIs suitable for device driver use. */ 6497 void 6498 pci_save_state(device_t dev) 6499 { 6500 struct pci_devinfo *dinfo; 6501 6502 dinfo = device_get_ivars(dev); 6503 pci_cfg_save(dev, dinfo, 0); 6504 } 6505 6506 void 6507 pci_restore_state(device_t dev) 6508 { 6509 struct pci_devinfo *dinfo; 6510 6511 dinfo = device_get_ivars(dev); 6512 pci_cfg_restore(dev, dinfo); 6513 } 6514 6515 static int 6516 pci_get_id_method(device_t dev, device_t child, enum pci_id_type type, 6517 uintptr_t *id) 6518 { 6519 6520 return (PCIB_GET_ID(device_get_parent(dev), child, type, id)); 6521 } 6522 6523 /* Find the upstream port of a given PCI device in a root complex. */ 6524 device_t 6525 pci_find_pcie_root_port(device_t dev) 6526 { 6527 struct pci_devinfo *dinfo; 6528 devclass_t pci_class; 6529 device_t pcib, bus; 6530 6531 pci_class = devclass_find("pci"); 6532 KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class, 6533 ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); 6534 6535 /* 6536 * Walk the bridge hierarchy until we find a PCI-e root 6537 * port or a non-PCI device. 6538 */ 6539 for (;;) { 6540 bus = device_get_parent(dev); 6541 KASSERT(bus != NULL, ("%s: null parent of %s", __func__, 6542 device_get_nameunit(dev))); 6543 6544 pcib = device_get_parent(bus); 6545 KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__, 6546 device_get_nameunit(bus))); 6547 6548 /* 6549 * pcib's parent must be a PCI bus for this to be a 6550 * PCI-PCI bridge. 6551 */ 6552 if (device_get_devclass(device_get_parent(pcib)) != pci_class) 6553 return (NULL); 6554 6555 dinfo = device_get_ivars(pcib); 6556 if (dinfo->cfg.pcie.pcie_location != 0 && 6557 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) 6558 return (pcib); 6559 6560 dev = pcib; 6561 } 6562 } 6563 6564 /* 6565 * Wait for pending transactions to complete on a PCI-express function. 6566 * 6567 * The maximum delay is specified in milliseconds in max_delay. Note 6568 * that this function may sleep. 6569 * 6570 * Returns true if the function is idle and false if the timeout is 6571 * exceeded. If dev is not a PCI-express function, this returns true. 6572 */ 6573 bool 6574 pcie_wait_for_pending_transactions(device_t dev, u_int max_delay) 6575 { 6576 struct pci_devinfo *dinfo = device_get_ivars(dev); 6577 uint16_t sta; 6578 int cap; 6579 6580 cap = dinfo->cfg.pcie.pcie_location; 6581 if (cap == 0) 6582 return (true); 6583 6584 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6585 while (sta & PCIEM_STA_TRANSACTION_PND) { 6586 if (max_delay == 0) 6587 return (false); 6588 6589 /* Poll once every 100 milliseconds up to the timeout. */ 6590 if (max_delay > 100) { 6591 pause_sbt("pcietp", 100 * SBT_1MS, 0, C_HARDCLOCK); 6592 max_delay -= 100; 6593 } else { 6594 pause_sbt("pcietp", max_delay * SBT_1MS, 0, 6595 C_HARDCLOCK); 6596 max_delay = 0; 6597 } 6598 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6599 } 6600 6601 return (true); 6602 } 6603 6604 /* 6605 * Determine the maximum Completion Timeout in microseconds. 6606 * 6607 * For non-PCI-express functions this returns 0. 6608 */ 6609 int 6610 pcie_get_max_completion_timeout(device_t dev) 6611 { 6612 struct pci_devinfo *dinfo = device_get_ivars(dev); 6613 int cap; 6614 6615 cap = dinfo->cfg.pcie.pcie_location; 6616 if (cap == 0) 6617 return (0); 6618 6619 /* 6620 * Functions using the 1.x spec use the default timeout range of 6621 * 50 microseconds to 50 milliseconds. Functions that do not 6622 * support programmable timeouts also use this range. 6623 */ 6624 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 || 6625 (pci_read_config(dev, cap + PCIER_DEVICE_CAP2, 4) & 6626 PCIEM_CAP2_COMP_TIMO_RANGES) == 0) 6627 return (50 * 1000); 6628 6629 switch (pci_read_config(dev, cap + PCIER_DEVICE_CTL2, 2) & 6630 PCIEM_CTL2_COMP_TIMO_VAL) { 6631 case PCIEM_CTL2_COMP_TIMO_100US: 6632 return (100); 6633 case PCIEM_CTL2_COMP_TIMO_10MS: 6634 return (10 * 1000); 6635 case PCIEM_CTL2_COMP_TIMO_55MS: 6636 return (55 * 1000); 6637 case PCIEM_CTL2_COMP_TIMO_210MS: 6638 return (210 * 1000); 6639 case PCIEM_CTL2_COMP_TIMO_900MS: 6640 return (900 * 1000); 6641 case PCIEM_CTL2_COMP_TIMO_3500MS: 6642 return (3500 * 1000); 6643 case PCIEM_CTL2_COMP_TIMO_13S: 6644 return (13 * 1000 * 1000); 6645 case PCIEM_CTL2_COMP_TIMO_64S: 6646 return (64 * 1000 * 1000); 6647 default: 6648 return (50 * 1000); 6649 } 6650 } 6651 6652 void 6653 pcie_apei_error(device_t dev, int sev, uint8_t *aerp) 6654 { 6655 struct pci_devinfo *dinfo = device_get_ivars(dev); 6656 const char *s; 6657 int aer; 6658 uint32_t r, r1; 6659 uint16_t rs; 6660 6661 if (sev == PCIEM_STA_CORRECTABLE_ERROR) 6662 s = "Correctable"; 6663 else if (sev == PCIEM_STA_NON_FATAL_ERROR) 6664 s = "Uncorrectable (Non-Fatal)"; 6665 else 6666 s = "Uncorrectable (Fatal)"; 6667 device_printf(dev, "%s PCIe error reported by APEI\n", s); 6668 if (aerp) { 6669 if (sev == PCIEM_STA_CORRECTABLE_ERROR) { 6670 r = le32dec(aerp + PCIR_AER_COR_STATUS); 6671 r1 = le32dec(aerp + PCIR_AER_COR_MASK); 6672 } else { 6673 r = le32dec(aerp + PCIR_AER_UC_STATUS); 6674 r1 = le32dec(aerp + PCIR_AER_UC_MASK); 6675 } 6676 device_printf(dev, "status 0x%08x mask 0x%08x", r, r1); 6677 if (sev != PCIEM_STA_CORRECTABLE_ERROR) { 6678 r = le32dec(aerp + PCIR_AER_UC_SEVERITY); 6679 rs = le16dec(aerp + PCIR_AER_CAP_CONTROL); 6680 printf(" severity 0x%08x first %d\n", 6681 r, rs & 0x1f); 6682 } else 6683 printf("\n"); 6684 } 6685 6686 /* As kind of recovery just report and clear the error statuses. */ 6687 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6688 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6689 if (r != 0) { 6690 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6691 device_printf(dev, "Clearing UC AER errors 0x%08x\n", r); 6692 } 6693 6694 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6695 if (r != 0) { 6696 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6697 device_printf(dev, "Clearing COR AER errors 0x%08x\n", r); 6698 } 6699 } 6700 if (dinfo->cfg.pcie.pcie_location != 0) { 6701 rs = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6702 PCIER_DEVICE_STA, 2); 6703 if ((rs & (PCIEM_STA_CORRECTABLE_ERROR | 6704 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6705 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6706 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6707 PCIER_DEVICE_STA, rs, 2); 6708 device_printf(dev, "Clearing PCIe errors 0x%04x\n", rs); 6709 } 6710 } 6711 } 6712 6713 /* 6714 * Perform a Function Level Reset (FLR) on a device. 6715 * 6716 * This function first waits for any pending transactions to complete 6717 * within the timeout specified by max_delay. If transactions are 6718 * still pending, the function will return false without attempting a 6719 * reset. 6720 * 6721 * If dev is not a PCI-express function or does not support FLR, this 6722 * function returns false. 6723 * 6724 * Note that no registers are saved or restored. The caller is 6725 * responsible for saving and restoring any registers including 6726 * PCI-standard registers via pci_save_state() and 6727 * pci_restore_state(). 6728 */ 6729 bool 6730 pcie_flr(device_t dev, u_int max_delay, bool force) 6731 { 6732 struct pci_devinfo *dinfo = device_get_ivars(dev); 6733 uint16_t cmd, ctl; 6734 int compl_delay; 6735 int cap; 6736 6737 cap = dinfo->cfg.pcie.pcie_location; 6738 if (cap == 0) 6739 return (false); 6740 6741 if (!(pci_read_config(dev, cap + PCIER_DEVICE_CAP, 4) & PCIEM_CAP_FLR)) 6742 return (false); 6743 6744 /* 6745 * Disable busmastering to prevent generation of new 6746 * transactions while waiting for the device to go idle. If 6747 * the idle timeout fails, the command register is restored 6748 * which will re-enable busmastering. 6749 */ 6750 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 6751 pci_write_config(dev, PCIR_COMMAND, cmd & ~(PCIM_CMD_BUSMASTEREN), 2); 6752 if (!pcie_wait_for_pending_transactions(dev, max_delay)) { 6753 if (!force) { 6754 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 6755 return (false); 6756 } 6757 pci_printf(&dinfo->cfg, 6758 "Resetting with transactions pending after %d ms\n", 6759 max_delay); 6760 6761 /* 6762 * Extend the post-FLR delay to cover the maximum 6763 * Completion Timeout delay of anything in flight 6764 * during the FLR delay. Enforce a minimum delay of 6765 * at least 10ms. 6766 */ 6767 compl_delay = pcie_get_max_completion_timeout(dev) / 1000; 6768 if (compl_delay < 10) 6769 compl_delay = 10; 6770 } else 6771 compl_delay = 0; 6772 6773 /* Initiate the reset. */ 6774 ctl = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 6775 pci_write_config(dev, cap + PCIER_DEVICE_CTL, ctl | 6776 PCIEM_CTL_INITIATE_FLR, 2); 6777 6778 /* Wait for 100ms. */ 6779 pause_sbt("pcieflr", (100 + compl_delay) * SBT_1MS, 0, C_HARDCLOCK); 6780 6781 if (pci_read_config(dev, cap + PCIER_DEVICE_STA, 2) & 6782 PCIEM_STA_TRANSACTION_PND) 6783 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n"); 6784 return (true); 6785 } 6786 6787 /* 6788 * Attempt a power-management reset by cycling the device in/out of D3 6789 * state. PCI spec says we can only go into D3 state from D0 state. 6790 * Transition from D[12] into D0 before going to D3 state. 6791 */ 6792 int 6793 pci_power_reset(device_t dev) 6794 { 6795 int ps; 6796 6797 ps = pci_get_powerstate(dev); 6798 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6799 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6800 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6801 pci_set_powerstate(dev, ps); 6802 return (0); 6803 } 6804 6805 /* 6806 * Try link drop and retrain of the downstream port of upstream 6807 * switch, for PCIe. According to the PCIe 3.0 spec 6.6.1, this must 6808 * cause Conventional Hot reset of the device in the slot. 6809 * Alternative, for PCIe, could be the secondary bus reset initiatied 6810 * on the upstream switch PCIR_BRIDGECTL_1, bit 6. 6811 */ 6812 int 6813 pcie_link_reset(device_t port, int pcie_location) 6814 { 6815 uint16_t v; 6816 6817 v = pci_read_config(port, pcie_location + PCIER_LINK_CTL, 2); 6818 v |= PCIEM_LINK_CTL_LINK_DIS; 6819 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6820 pause_sbt("pcier1", mstosbt(20), 0, 0); 6821 v &= ~PCIEM_LINK_CTL_LINK_DIS; 6822 v |= PCIEM_LINK_CTL_RETRAIN_LINK; 6823 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6824 pause_sbt("pcier2", mstosbt(100), 0, 0); /* 100 ms */ 6825 v = pci_read_config(port, pcie_location + PCIER_LINK_STA, 2); 6826 return ((v & PCIEM_LINK_STA_TRAINING) != 0 ? ETIMEDOUT : 0); 6827 } 6828 6829 static int 6830 pci_reset_post(device_t dev, device_t child) 6831 { 6832 6833 if (dev == device_get_parent(child)) 6834 pci_restore_state(child); 6835 return (0); 6836 } 6837 6838 static int 6839 pci_reset_prepare(device_t dev, device_t child) 6840 { 6841 6842 if (dev == device_get_parent(child)) 6843 pci_save_state(child); 6844 return (0); 6845 } 6846 6847 static int 6848 pci_reset_child(device_t dev, device_t child, int flags) 6849 { 6850 int error; 6851 6852 if (dev == NULL || device_get_parent(child) != dev) 6853 return (0); 6854 if ((flags & DEVF_RESET_DETACH) != 0) { 6855 error = device_get_state(child) == DS_ATTACHED ? 6856 device_detach(child) : 0; 6857 } else { 6858 error = BUS_SUSPEND_CHILD(dev, child); 6859 } 6860 if (error == 0) { 6861 if (!pcie_flr(child, 1000, false)) { 6862 error = BUS_RESET_PREPARE(dev, child); 6863 if (error == 0) 6864 pci_power_reset(child); 6865 BUS_RESET_POST(dev, child); 6866 } 6867 if ((flags & DEVF_RESET_DETACH) != 0) 6868 device_probe_and_attach(child); 6869 else 6870 BUS_RESUME_CHILD(dev, child); 6871 } 6872 return (error); 6873 } 6874 6875 const struct pci_device_table * 6876 pci_match_device(device_t child, const struct pci_device_table *id, size_t nelt) 6877 { 6878 bool match; 6879 uint16_t vendor, device, subvendor, subdevice, class, subclass, revid; 6880 6881 vendor = pci_get_vendor(child); 6882 device = pci_get_device(child); 6883 subvendor = pci_get_subvendor(child); 6884 subdevice = pci_get_subdevice(child); 6885 class = pci_get_class(child); 6886 subclass = pci_get_subclass(child); 6887 revid = pci_get_revid(child); 6888 while (nelt-- > 0) { 6889 match = true; 6890 if (id->match_flag_vendor) 6891 match &= vendor == id->vendor; 6892 if (id->match_flag_device) 6893 match &= device == id->device; 6894 if (id->match_flag_subvendor) 6895 match &= subvendor == id->subvendor; 6896 if (id->match_flag_subdevice) 6897 match &= subdevice == id->subdevice; 6898 if (id->match_flag_class) 6899 match &= class == id->class_id; 6900 if (id->match_flag_subclass) 6901 match &= subclass == id->subclass; 6902 if (id->match_flag_revid) 6903 match &= revid == id->revid; 6904 if (match) 6905 return (id); 6906 id++; 6907 } 6908 return (NULL); 6909 } 6910 6911 static void 6912 pci_print_faulted_dev_name(const struct pci_devinfo *dinfo) 6913 { 6914 const char *dev_name; 6915 device_t dev; 6916 6917 dev = dinfo->cfg.dev; 6918 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus, 6919 dinfo->cfg.slot, dinfo->cfg.func); 6920 dev_name = device_get_name(dev); 6921 if (dev_name != NULL) 6922 printf(" (%s%d)", dev_name, device_get_unit(dev)); 6923 } 6924 6925 void 6926 pci_print_faulted_dev(void) 6927 { 6928 struct pci_devinfo *dinfo; 6929 device_t dev; 6930 int aer, i; 6931 uint32_t r1, r2; 6932 uint16_t status; 6933 6934 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6935 dev = dinfo->cfg.dev; 6936 status = pci_read_config(dev, PCIR_STATUS, 2); 6937 status &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6938 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6939 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6940 if (status != 0) { 6941 pci_print_faulted_dev_name(dinfo); 6942 printf(" error 0x%04x\n", status); 6943 } 6944 if (dinfo->cfg.pcie.pcie_location != 0) { 6945 status = pci_read_config(dev, 6946 dinfo->cfg.pcie.pcie_location + 6947 PCIER_DEVICE_STA, 2); 6948 if ((status & (PCIEM_STA_CORRECTABLE_ERROR | 6949 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6950 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6951 pci_print_faulted_dev_name(dinfo); 6952 printf(" PCIe DEVCTL 0x%04x DEVSTA 0x%04x\n", 6953 pci_read_config(dev, 6954 dinfo->cfg.pcie.pcie_location + 6955 PCIER_DEVICE_CTL, 2), 6956 status); 6957 } 6958 } 6959 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6960 r1 = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6961 r2 = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6962 if (r1 != 0 || r2 != 0) { 6963 pci_print_faulted_dev_name(dinfo); 6964 printf(" AER UC 0x%08x Mask 0x%08x Svr 0x%08x\n" 6965 " COR 0x%08x Mask 0x%08x Ctl 0x%08x\n", 6966 r1, pci_read_config(dev, aer + 6967 PCIR_AER_UC_MASK, 4), 6968 pci_read_config(dev, aer + 6969 PCIR_AER_UC_SEVERITY, 4), 6970 r2, pci_read_config(dev, aer + 6971 PCIR_AER_COR_MASK, 4), 6972 pci_read_config(dev, aer + 6973 PCIR_AER_CAP_CONTROL, 4)); 6974 for (i = 0; i < 4; i++) { 6975 r1 = pci_read_config(dev, aer + 6976 PCIR_AER_HEADER_LOG + i * 4, 4); 6977 printf(" HL%d: 0x%08x\n", i, r1); 6978 } 6979 } 6980 } 6981 } 6982 } 6983 6984 #ifdef DDB 6985 DB_SHOW_COMMAND_FLAGS(pcierr, pci_print_faulted_dev_db, DB_CMD_MEMSAFE) 6986 { 6987 6988 pci_print_faulted_dev(); 6989 } 6990 6991 static void 6992 db_clear_pcie_errors(const struct pci_devinfo *dinfo) 6993 { 6994 device_t dev; 6995 int aer; 6996 uint32_t r; 6997 6998 dev = dinfo->cfg.dev; 6999 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 7000 PCIER_DEVICE_STA, 2); 7001 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 7002 PCIER_DEVICE_STA, r, 2); 7003 7004 if (pci_find_extcap(dev, PCIZ_AER, &aer) != 0) 7005 return; 7006 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 7007 if (r != 0) 7008 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 7009 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 7010 if (r != 0) 7011 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 7012 } 7013 7014 DB_COMMAND_FLAGS(pci_clearerr, db_pci_clearerr, DB_CMD_MEMSAFE) 7015 { 7016 struct pci_devinfo *dinfo; 7017 device_t dev; 7018 uint16_t status, status1; 7019 7020 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 7021 dev = dinfo->cfg.dev; 7022 status1 = status = pci_read_config(dev, PCIR_STATUS, 2); 7023 status1 &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 7024 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 7025 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 7026 if (status1 != 0) { 7027 status &= ~status1; 7028 pci_write_config(dev, PCIR_STATUS, status, 2); 7029 } 7030 if (dinfo->cfg.pcie.pcie_location != 0) 7031 db_clear_pcie_errors(dinfo); 7032 } 7033 } 7034 #endif 7035