1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/linker.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/sysctl.h> 44 #include <sys/types.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 55 #include <sys/pciio.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pci_private.h> 59 60 #include "pcib_if.h" 61 #include "pci_if.h" 62 63 #if (defined(__i386__) && !defined(PC98)) || defined(__amd64__) || \ 64 defined (__ia64__) 65 #include <contrib/dev/acpica/acpi.h> 66 #include "acpi_if.h" 67 #else 68 #define ACPI_PWR_FOR_SLEEP(x, y, z) 69 #endif 70 71 static uint32_t pci_mapbase(unsigned mapreg); 72 static int pci_maptype(unsigned mapreg); 73 static int pci_mapsize(unsigned testval); 74 static int pci_maprange(unsigned mapreg); 75 static void pci_fixancient(pcicfgregs *cfg); 76 77 static int pci_porten(device_t pcib, int b, int s, int f); 78 static int pci_memen(device_t pcib, int b, int s, int f); 79 static int pci_add_map(device_t pcib, device_t bus, device_t dev, 80 int b, int s, int f, int reg, 81 struct resource_list *rl); 82 static void pci_add_resources(device_t pcib, device_t bus, 83 device_t dev); 84 static int pci_probe(device_t dev); 85 static int pci_attach(device_t dev); 86 static void pci_load_vendor_data(void); 87 static int pci_describe_parse_line(char **ptr, int *vendor, 88 int *device, char **desc); 89 static char *pci_describe_device(device_t dev); 90 static int pci_modevent(module_t mod, int what, void *arg); 91 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 92 pcicfgregs *cfg); 93 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 94 95 static device_method_t pci_methods[] = { 96 /* Device interface */ 97 DEVMETHOD(device_probe, pci_probe), 98 DEVMETHOD(device_attach, pci_attach), 99 DEVMETHOD(device_shutdown, bus_generic_shutdown), 100 DEVMETHOD(device_suspend, pci_suspend), 101 DEVMETHOD(device_resume, pci_resume), 102 103 /* Bus interface */ 104 DEVMETHOD(bus_print_child, pci_print_child), 105 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 106 DEVMETHOD(bus_read_ivar, pci_read_ivar), 107 DEVMETHOD(bus_write_ivar, pci_write_ivar), 108 DEVMETHOD(bus_driver_added, pci_driver_added), 109 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 110 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 111 112 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 113 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 114 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 115 DEVMETHOD(bus_delete_resource, pci_delete_resource), 116 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 117 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 118 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 119 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 120 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 121 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 122 123 /* PCI interface */ 124 DEVMETHOD(pci_read_config, pci_read_config_method), 125 DEVMETHOD(pci_write_config, pci_write_config_method), 126 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 127 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 128 DEVMETHOD(pci_enable_io, pci_enable_io_method), 129 DEVMETHOD(pci_disable_io, pci_disable_io_method), 130 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 131 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 132 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 133 134 { 0, 0 } 135 }; 136 137 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 138 139 devclass_t pci_devclass; 140 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 141 MODULE_VERSION(pci, 1); 142 143 static char *pci_vendordata; 144 static size_t pci_vendordata_size; 145 146 147 struct pci_quirk { 148 uint32_t devid; /* Vendor/device of the card */ 149 int type; 150 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 151 int arg1; 152 int arg2; 153 }; 154 155 struct pci_quirk pci_quirks[] = { 156 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 157 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 158 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 159 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 160 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 161 162 { 0 } 163 }; 164 165 /* map register information */ 166 #define PCI_MAPMEM 0x01 /* memory map */ 167 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 168 #define PCI_MAPPORT 0x04 /* port map */ 169 170 struct devlist pci_devq; 171 uint32_t pci_generation; 172 uint32_t pci_numdevs = 0; 173 174 /* sysctl vars */ 175 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 176 177 static int pci_enable_io_modes = 1; 178 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 179 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 180 &pci_enable_io_modes, 1, 181 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 182 enable these bits correctly. We'd like to do this all the time, but there\n\ 183 are some peripherals that this causes problems with."); 184 185 static int pci_do_powerstate = 1; 186 TUNABLE_INT("hw.pci.do_powerstate", &pci_do_powerstate); 187 SYSCTL_INT(_hw_pci, OID_AUTO, do_powerstate, CTLFLAG_RW, 188 &pci_do_powerstate, 1, 189 "Power down devices into D3 state when no driver attaches to them.\n\ 190 Otherwise, leave the device in D0 state when no driver attaches."); 191 192 /* Find a device_t by bus/slot/function */ 193 194 device_t 195 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 196 { 197 struct pci_devinfo *dinfo; 198 199 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 200 if ((dinfo->cfg.bus == bus) && 201 (dinfo->cfg.slot == slot) && 202 (dinfo->cfg.func == func)) { 203 return (dinfo->cfg.dev); 204 } 205 } 206 207 return (NULL); 208 } 209 210 /* Find a device_t by vendor/device ID */ 211 212 device_t 213 pci_find_device(uint16_t vendor, uint16_t device) 214 { 215 struct pci_devinfo *dinfo; 216 217 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 218 if ((dinfo->cfg.vendor == vendor) && 219 (dinfo->cfg.device == device)) { 220 return (dinfo->cfg.dev); 221 } 222 } 223 224 return (NULL); 225 } 226 227 /* return base address of memory or port map */ 228 229 static uint32_t 230 pci_mapbase(unsigned mapreg) 231 { 232 int mask = 0x03; 233 if ((mapreg & 0x01) == 0) 234 mask = 0x0f; 235 return (mapreg & ~mask); 236 } 237 238 /* return map type of memory or port map */ 239 240 static int 241 pci_maptype(unsigned mapreg) 242 { 243 static uint8_t maptype[0x10] = { 244 PCI_MAPMEM, PCI_MAPPORT, 245 PCI_MAPMEM, 0, 246 PCI_MAPMEM, PCI_MAPPORT, 247 0, 0, 248 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 249 PCI_MAPMEM|PCI_MAPMEMP, 0, 250 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 251 0, 0, 252 }; 253 254 return maptype[mapreg & 0x0f]; 255 } 256 257 /* return log2 of map size decoded for memory or port map */ 258 259 static int 260 pci_mapsize(unsigned testval) 261 { 262 int ln2size; 263 264 testval = pci_mapbase(testval); 265 ln2size = 0; 266 if (testval != 0) { 267 while ((testval & 1) == 0) 268 { 269 ln2size++; 270 testval >>= 1; 271 } 272 } 273 return (ln2size); 274 } 275 276 /* return log2 of address range supported by map register */ 277 278 static int 279 pci_maprange(unsigned mapreg) 280 { 281 int ln2range = 0; 282 switch (mapreg & 0x07) { 283 case 0x00: 284 case 0x01: 285 case 0x05: 286 ln2range = 32; 287 break; 288 case 0x02: 289 ln2range = 20; 290 break; 291 case 0x04: 292 ln2range = 64; 293 break; 294 } 295 return (ln2range); 296 } 297 298 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 299 300 static void 301 pci_fixancient(pcicfgregs *cfg) 302 { 303 if (cfg->hdrtype != 0) 304 return; 305 306 /* PCI to PCI bridges use header type 1 */ 307 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 308 cfg->hdrtype = 1; 309 } 310 311 /* extract header type specific config data */ 312 313 static void 314 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 315 { 316 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 317 switch (cfg->hdrtype) { 318 case 0: 319 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 320 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 321 cfg->nummaps = PCI_MAXMAPS_0; 322 break; 323 case 1: 324 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 325 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 326 cfg->nummaps = PCI_MAXMAPS_1; 327 break; 328 case 2: 329 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 330 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 331 cfg->nummaps = PCI_MAXMAPS_2; 332 break; 333 } 334 #undef REG 335 } 336 337 /* read configuration header into pcicfgregs structure */ 338 339 struct pci_devinfo * 340 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 341 { 342 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 343 pcicfgregs *cfg = NULL; 344 struct pci_devinfo *devlist_entry; 345 struct devlist *devlist_head; 346 347 devlist_head = &pci_devq; 348 349 devlist_entry = NULL; 350 351 if (REG(PCIR_DEVVENDOR, 4) != -1) { 352 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 353 if (devlist_entry == NULL) 354 return (NULL); 355 356 cfg = &devlist_entry->cfg; 357 358 cfg->bus = b; 359 cfg->slot = s; 360 cfg->func = f; 361 cfg->vendor = REG(PCIR_VENDOR, 2); 362 cfg->device = REG(PCIR_DEVICE, 2); 363 cfg->cmdreg = REG(PCIR_COMMAND, 2); 364 cfg->statreg = REG(PCIR_STATUS, 2); 365 cfg->baseclass = REG(PCIR_CLASS, 1); 366 cfg->subclass = REG(PCIR_SUBCLASS, 1); 367 cfg->progif = REG(PCIR_PROGIF, 1); 368 cfg->revid = REG(PCIR_REVID, 1); 369 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 370 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 371 cfg->lattimer = REG(PCIR_LATTIMER, 1); 372 cfg->intpin = REG(PCIR_INTPIN, 1); 373 cfg->intline = REG(PCIR_INTLINE, 1); 374 375 cfg->mingnt = REG(PCIR_MINGNT, 1); 376 cfg->maxlat = REG(PCIR_MAXLAT, 1); 377 378 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 379 cfg->hdrtype &= ~PCIM_MFDEV; 380 381 pci_fixancient(cfg); 382 pci_hdrtypedata(pcib, b, s, f, cfg); 383 384 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 385 pci_read_extcap(pcib, cfg); 386 387 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 388 389 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 390 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 391 devlist_entry->conf.pc_sel.pc_func = cfg->func; 392 devlist_entry->conf.pc_hdr = cfg->hdrtype; 393 394 devlist_entry->conf.pc_subvendor = cfg->subvendor; 395 devlist_entry->conf.pc_subdevice = cfg->subdevice; 396 devlist_entry->conf.pc_vendor = cfg->vendor; 397 devlist_entry->conf.pc_device = cfg->device; 398 399 devlist_entry->conf.pc_class = cfg->baseclass; 400 devlist_entry->conf.pc_subclass = cfg->subclass; 401 devlist_entry->conf.pc_progif = cfg->progif; 402 devlist_entry->conf.pc_revid = cfg->revid; 403 404 pci_numdevs++; 405 pci_generation++; 406 } 407 return (devlist_entry); 408 #undef REG 409 } 410 411 static void 412 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 413 { 414 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 415 int ptr, nextptr, ptrptr; 416 417 switch (cfg->hdrtype & PCIM_HDRTYPE) { 418 case 0: 419 ptrptr = PCIR_CAP_PTR; 420 break; 421 case 2: 422 ptrptr = 0x14; 423 break; 424 default: 425 return; /* no extended capabilities support */ 426 } 427 nextptr = REG(ptrptr, 1); /* sanity check? */ 428 429 /* 430 * Read capability entries. 431 */ 432 while (nextptr != 0) { 433 /* Sanity check */ 434 if (nextptr > 255) { 435 printf("illegal PCI extended capability offset %d\n", 436 nextptr); 437 return; 438 } 439 /* Find the next entry */ 440 ptr = nextptr; 441 nextptr = REG(ptr + 1, 1); 442 443 /* Process this entry */ 444 switch (REG(ptr, 1)) { 445 case PCIY_PMG: /* PCI power management */ 446 if (cfg->pp.pp_cap == 0) { 447 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 448 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 449 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 450 if ((nextptr - ptr) > PCIR_POWER_DATA) 451 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 452 } 453 break; 454 case PCIY_MSI: /* PCI MSI */ 455 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 456 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 457 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 458 else 459 cfg->msi.msi_data = PCIR_MSI_DATA; 460 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 461 PCIM_MSICTRL_MMC_MASK)>>1); 462 default: 463 break; 464 } 465 } 466 #undef REG 467 } 468 469 /* free pcicfgregs structure and all depending data structures */ 470 471 int 472 pci_freecfg(struct pci_devinfo *dinfo) 473 { 474 struct devlist *devlist_head; 475 476 devlist_head = &pci_devq; 477 478 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 479 free(dinfo, M_DEVBUF); 480 481 /* increment the generation count */ 482 pci_generation++; 483 484 /* we're losing one device */ 485 pci_numdevs--; 486 return (0); 487 } 488 489 /* 490 * PCI power manangement 491 */ 492 int 493 pci_set_powerstate_method(device_t dev, device_t child, int state) 494 { 495 struct pci_devinfo *dinfo = device_get_ivars(child); 496 pcicfgregs *cfg = &dinfo->cfg; 497 uint16_t status; 498 int result, oldstate, highest, delay; 499 500 if (cfg->pp.pp_cap == 0) 501 return (EOPNOTSUPP); 502 503 /* 504 * Optimize a no state change request away. While it would be OK to 505 * write to the hardware in theory, some devices have shown odd 506 * behavior when going from D3 -> D3. 507 */ 508 oldstate = pci_get_powerstate(child); 509 if (oldstate == state) 510 return (0); 511 512 /* 513 * The PCI power management specification states that after a state 514 * transition between PCI power states, system software must 515 * guarantee a minimal delay before the function accesses the device. 516 * Compute the worst case delay that we need to guarantee before we 517 * access the device. Many devices will be responsive much more 518 * quickly than this delay, but there are some that don't respond 519 * instantly to state changes. Transitions to/from D3 state require 520 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 521 * is done below with DELAY rather than a sleeper function because 522 * this function can be called from contexts where we cannot sleep. 523 */ 524 highest = (oldstate > state) ? oldstate : state; 525 if (highest == PCI_POWERSTATE_D3) 526 delay = 10000; 527 else if (highest == PCI_POWERSTATE_D2) 528 delay = 200; 529 else 530 delay = 0; 531 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 532 & ~PCIM_PSTAT_DMASK; 533 result = 0; 534 switch (state) { 535 case PCI_POWERSTATE_D0: 536 status |= PCIM_PSTAT_D0; 537 break; 538 case PCI_POWERSTATE_D1: 539 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 540 return (EOPNOTSUPP); 541 status |= PCIM_PSTAT_D1; 542 break; 543 case PCI_POWERSTATE_D2: 544 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 545 return (EOPNOTSUPP); 546 status |= PCIM_PSTAT_D2; 547 break; 548 case PCI_POWERSTATE_D3: 549 status |= PCIM_PSTAT_D3; 550 break; 551 default: 552 return (EINVAL); 553 } 554 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 555 if (delay) 556 DELAY(delay); 557 return (0); 558 } 559 560 int 561 pci_get_powerstate_method(device_t dev, device_t child) 562 { 563 struct pci_devinfo *dinfo = device_get_ivars(child); 564 pcicfgregs *cfg = &dinfo->cfg; 565 uint16_t status; 566 int result; 567 568 if (cfg->pp.pp_cap != 0) { 569 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 570 switch (status & PCIM_PSTAT_DMASK) { 571 case PCIM_PSTAT_D0: 572 result = PCI_POWERSTATE_D0; 573 break; 574 case PCIM_PSTAT_D1: 575 result = PCI_POWERSTATE_D1; 576 break; 577 case PCIM_PSTAT_D2: 578 result = PCI_POWERSTATE_D2; 579 break; 580 case PCIM_PSTAT_D3: 581 result = PCI_POWERSTATE_D3; 582 break; 583 default: 584 result = PCI_POWERSTATE_UNKNOWN; 585 break; 586 } 587 } else { 588 /* No support, device is always at D0 */ 589 result = PCI_POWERSTATE_D0; 590 } 591 return (result); 592 } 593 594 /* 595 * Some convenience functions for PCI device drivers. 596 */ 597 598 static __inline void 599 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 600 { 601 uint16_t command; 602 603 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 604 command |= bit; 605 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 606 } 607 608 static __inline void 609 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 610 { 611 uint16_t command; 612 613 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 614 command &= ~bit; 615 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 616 } 617 618 int 619 pci_enable_busmaster_method(device_t dev, device_t child) 620 { 621 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 622 return (0); 623 } 624 625 int 626 pci_disable_busmaster_method(device_t dev, device_t child) 627 { 628 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 629 return (0); 630 } 631 632 int 633 pci_enable_io_method(device_t dev, device_t child, int space) 634 { 635 uint16_t command; 636 uint16_t bit; 637 char *error; 638 639 bit = 0; 640 error = NULL; 641 642 switch(space) { 643 case SYS_RES_IOPORT: 644 bit = PCIM_CMD_PORTEN; 645 error = "port"; 646 break; 647 case SYS_RES_MEMORY: 648 bit = PCIM_CMD_MEMEN; 649 error = "memory"; 650 break; 651 default: 652 return (EINVAL); 653 } 654 pci_set_command_bit(dev, child, bit); 655 /* Some devices seem to need a brief stall here, what do to? */ 656 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 657 if (command & bit) 658 return (0); 659 device_printf(child, "failed to enable %s mapping!\n", error); 660 return (ENXIO); 661 } 662 663 int 664 pci_disable_io_method(device_t dev, device_t child, int space) 665 { 666 uint16_t command; 667 uint16_t bit; 668 char *error; 669 670 bit = 0; 671 error = NULL; 672 673 switch(space) { 674 case SYS_RES_IOPORT: 675 bit = PCIM_CMD_PORTEN; 676 error = "port"; 677 break; 678 case SYS_RES_MEMORY: 679 bit = PCIM_CMD_MEMEN; 680 error = "memory"; 681 break; 682 default: 683 return (EINVAL); 684 } 685 pci_clear_command_bit(dev, child, bit); 686 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 687 if (command & bit) { 688 device_printf(child, "failed to disable %s mapping!\n", error); 689 return (ENXIO); 690 } 691 return (0); 692 } 693 694 /* 695 * New style pci driver. Parent device is either a pci-host-bridge or a 696 * pci-pci-bridge. Both kinds are represented by instances of pcib. 697 */ 698 699 void 700 pci_print_verbose(struct pci_devinfo *dinfo) 701 { 702 if (bootverbose) { 703 pcicfgregs *cfg = &dinfo->cfg; 704 705 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 706 cfg->vendor, cfg->device, cfg->revid); 707 printf("\tbus=%d, slot=%d, func=%d\n", 708 cfg->bus, cfg->slot, cfg->func); 709 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 710 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 711 cfg->mfdev); 712 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 713 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 714 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 715 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 716 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 717 if (cfg->intpin > 0) 718 printf("\tintpin=%c, irq=%d\n", 719 cfg->intpin +'a' -1, cfg->intline); 720 if (cfg->pp.pp_cap) { 721 uint16_t status; 722 723 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 724 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 725 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 726 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 727 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 728 status & PCIM_PSTAT_DMASK); 729 } 730 if (cfg->msi.msi_data) { 731 int ctrl; 732 733 ctrl = cfg->msi.msi_ctrl; 734 printf("\tMSI supports %d message%s%s%s\n", 735 cfg->msi.msi_msgnum, 736 (cfg->msi.msi_msgnum == 1) ? "" : "s", 737 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 738 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 739 } 740 } 741 } 742 743 static int 744 pci_porten(device_t pcib, int b, int s, int f) 745 { 746 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 747 & PCIM_CMD_PORTEN) != 0; 748 } 749 750 static int 751 pci_memen(device_t pcib, int b, int s, int f) 752 { 753 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 754 & PCIM_CMD_MEMEN) != 0; 755 } 756 757 /* 758 * Add a resource based on a pci map register. Return 1 if the map 759 * register is a 32bit map register or 2 if it is a 64bit register. 760 */ 761 static int 762 pci_add_map(device_t pcib, device_t bus, device_t dev, 763 int b, int s, int f, int reg, struct resource_list *rl) 764 { 765 uint32_t map; 766 uint64_t base; 767 uint64_t start, end, count; 768 uint8_t ln2size; 769 uint8_t ln2range; 770 uint32_t testval; 771 uint16_t cmd; 772 int type; 773 774 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 775 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 776 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 777 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 778 779 if (pci_maptype(map) & PCI_MAPMEM) 780 type = SYS_RES_MEMORY; 781 else 782 type = SYS_RES_IOPORT; 783 ln2size = pci_mapsize(testval); 784 ln2range = pci_maprange(testval); 785 base = pci_mapbase(map); 786 787 /* 788 * For I/O registers, if bottom bit is set, and the next bit up 789 * isn't clear, we know we have a BAR that doesn't conform to the 790 * spec, so ignore it. Also, sanity check the size of the data 791 * areas to the type of memory involved. Memory must be at least 792 * 32 bytes in size, while I/O ranges must be at least 4. 793 */ 794 if ((testval & 0x1) == 0x1 && 795 (testval & 0x2) != 0) 796 return (1); 797 if ((type == SYS_RES_MEMORY && ln2size < 5) || 798 (type == SYS_RES_IOPORT && ln2size < 2)) 799 return (1); 800 801 if (ln2range == 64) 802 /* Read the other half of a 64bit map register */ 803 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 804 805 if (bootverbose) { 806 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 807 reg, pci_maptype(map), ln2range, 808 (unsigned int) base, ln2size); 809 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 810 printf(", port disabled\n"); 811 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 812 printf(", memory disabled\n"); 813 else 814 printf(", enabled\n"); 815 } 816 817 /* 818 * This code theoretically does the right thing, but has 819 * undesirable side effects in some cases where peripherals 820 * respond oddly to having these bits enabled. Let the user 821 * be able to turn them off (since pci_enable_io_modes is 1 by 822 * default). 823 */ 824 if (pci_enable_io_modes) { 825 /* Turn on resources that have been left off by a lazy BIOS */ 826 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 827 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 828 cmd |= PCIM_CMD_PORTEN; 829 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 830 } 831 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 832 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 833 cmd |= PCIM_CMD_MEMEN; 834 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 835 } 836 } else { 837 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 838 return (1); 839 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 840 return (1); 841 } 842 /* 843 * If base is 0, then we have problems. It is best to ignore 844 * such entires for the moment. These will be allocated later if 845 * the driver specifically requests them. 846 */ 847 if (base == 0) 848 return 1; 849 850 start = base; 851 end = base + (1 << ln2size) - 1; 852 count = 1 << ln2size; 853 resource_list_add(rl, type, reg, start, end, count); 854 855 /* 856 * Not quite sure what to do on failure of allocating the resource 857 * since I can postulate several right answers. 858 */ 859 resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 0); 860 return ((ln2range == 64) ? 2 : 1); 861 } 862 863 /* 864 * For ATA devices we need to decide early what addressing mode to use. 865 * Legacy demands that the primary and secondary ATA ports sits on the 866 * same addresses that old ISA hardware did. This dictates that we use 867 * those addresses and ignore the BAR's if we cannot set PCI native 868 * addressing mode. 869 */ 870 static void 871 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 872 int s, int f, struct resource_list *rl) 873 { 874 int rid, type, progif; 875 #if 0 876 /* if this device supports PCI native addressing use it */ 877 progif = pci_read_config(dev, PCIR_PROGIF, 1); 878 if ((progif & 0x8a) == 0x8a) { 879 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 880 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 881 printf("Trying ATA native PCI addressing mode\n"); 882 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 883 } 884 } 885 #endif 886 progif = pci_read_config(dev, PCIR_PROGIF, 1); 887 type = SYS_RES_IOPORT; 888 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 889 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl); 890 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl); 891 } 892 else { 893 rid = PCIR_BAR(0); 894 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 895 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,8,0); 896 rid = PCIR_BAR(1); 897 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 898 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,1,0); 899 } 900 if (progif & PCIP_STORAGE_IDE_MODESEC) { 901 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl); 902 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl); 903 } 904 else { 905 rid = PCIR_BAR(2); 906 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 907 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,8,0); 908 rid = PCIR_BAR(3); 909 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 910 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,1,0); 911 } 912 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl); 913 } 914 915 static void 916 pci_add_resources(device_t pcib, device_t bus, device_t dev) 917 { 918 struct pci_devinfo *dinfo = device_get_ivars(dev); 919 pcicfgregs *cfg = &dinfo->cfg; 920 struct resource_list *rl = &dinfo->resources; 921 struct pci_quirk *q; 922 int b, i, irq, f, s; 923 924 b = cfg->bus; 925 s = cfg->slot; 926 f = cfg->func; 927 928 /* ATA devices needs special map treatment */ 929 if ((pci_get_class(dev) == PCIC_STORAGE) && 930 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 931 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 932 pci_ata_maps(pcib, bus, dev, b, s, f, rl); 933 else 934 for (i = 0; i < cfg->nummaps;) 935 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 936 rl); 937 938 for (q = &pci_quirks[0]; q->devid; q++) { 939 if (q->devid == ((cfg->device << 16) | cfg->vendor) 940 && q->type == PCI_QUIRK_MAP_REG) 941 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl); 942 } 943 944 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 945 #if defined(__ia64__) || defined(__i386__) || defined(__amd64__) || \ 946 defined(__arm__) || defined(__alpha__) 947 /* 948 * Try to re-route interrupts. Sometimes the BIOS or 949 * firmware may leave bogus values in these registers. 950 * If the re-route fails, then just stick with what we 951 * have. 952 */ 953 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 954 if (PCI_INTERRUPT_VALID(irq)) { 955 pci_write_config(dev, PCIR_INTLINE, irq, 1); 956 cfg->intline = irq; 957 } else 958 #endif 959 irq = cfg->intline; 960 resource_list_add(rl, SYS_RES_IRQ, 0, irq, irq, 1); 961 } 962 } 963 964 void 965 pci_add_children(device_t dev, int busno, size_t dinfo_size) 966 { 967 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 968 device_t pcib = device_get_parent(dev); 969 struct pci_devinfo *dinfo; 970 int maxslots; 971 int s, f, pcifunchigh; 972 uint8_t hdrtype; 973 974 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 975 ("dinfo_size too small")); 976 maxslots = PCIB_MAXSLOTS(pcib); 977 for (s = 0; s <= maxslots; s++) { 978 pcifunchigh = 0; 979 f = 0; 980 hdrtype = REG(PCIR_HDRTYPE, 1); 981 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 982 continue; 983 if (hdrtype & PCIM_MFDEV) 984 pcifunchigh = PCI_FUNCMAX; 985 for (f = 0; f <= pcifunchigh; f++) { 986 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 987 if (dinfo != NULL) { 988 pci_add_child(dev, dinfo); 989 } 990 } 991 } 992 #undef REG 993 } 994 995 void 996 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 997 { 998 device_t pcib; 999 1000 pcib = device_get_parent(bus); 1001 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1002 device_set_ivars(dinfo->cfg.dev, dinfo); 1003 resource_list_init(&dinfo->resources); 1004 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 1005 pci_cfg_restore(dinfo->cfg.dev, dinfo); 1006 pci_add_resources(pcib, bus, dinfo->cfg.dev); 1007 pci_print_verbose(dinfo); 1008 } 1009 1010 static int 1011 pci_probe(device_t dev) 1012 { 1013 1014 device_set_desc(dev, "PCI bus"); 1015 1016 /* Allow other subclasses to override this driver. */ 1017 return (-1000); 1018 } 1019 1020 static int 1021 pci_attach(device_t dev) 1022 { 1023 int busno; 1024 1025 /* 1026 * Since there can be multiple independantly numbered PCI 1027 * busses on some large alpha systems, we can't use the unit 1028 * number to decide what bus we are probing. We ask the parent 1029 * pcib what our bus number is. 1030 */ 1031 busno = pcib_get_bus(dev); 1032 if (bootverbose) 1033 device_printf(dev, "physical bus=%d\n", busno); 1034 1035 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1036 1037 return (bus_generic_attach(dev)); 1038 } 1039 1040 int 1041 pci_suspend(device_t dev) 1042 { 1043 int dstate, error, i, numdevs; 1044 device_t acpi_dev, child, *devlist; 1045 struct pci_devinfo *dinfo; 1046 1047 /* 1048 * Save the PCI configuration space for each child and set the 1049 * device in the appropriate power state for this sleep state. 1050 */ 1051 acpi_dev = NULL; 1052 if (pci_do_powerstate) 1053 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1054 device_get_children(dev, &devlist, &numdevs); 1055 for (i = 0; i < numdevs; i++) { 1056 child = devlist[i]; 1057 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1058 pci_cfg_save(child, dinfo, 0); 1059 } 1060 1061 /* Suspend devices before potentially powering them down. */ 1062 error = bus_generic_suspend(dev); 1063 if (error) { 1064 free(devlist, M_TEMP); 1065 return (error); 1066 } 1067 1068 /* 1069 * Always set the device to D3. If ACPI suggests a different 1070 * power state, use it instead. If ACPI is not present, the 1071 * firmware is responsible for managing device power. Skip 1072 * children who aren't attached since they are powered down 1073 * separately. Only manage type 0 devices for now. 1074 */ 1075 for (i = 0; acpi_dev && i < numdevs; i++) { 1076 child = devlist[i]; 1077 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1078 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 1079 dstate = PCI_POWERSTATE_D3; 1080 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 1081 pci_set_powerstate(child, dstate); 1082 } 1083 } 1084 free(devlist, M_TEMP); 1085 return (0); 1086 } 1087 1088 int 1089 pci_resume(device_t dev) 1090 { 1091 int i, numdevs; 1092 device_t acpi_dev, child, *devlist; 1093 struct pci_devinfo *dinfo; 1094 1095 /* 1096 * Set each child to D0 and restore its PCI configuration space. 1097 */ 1098 acpi_dev = NULL; 1099 if (pci_do_powerstate) 1100 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1101 device_get_children(dev, &devlist, &numdevs); 1102 for (i = 0; i < numdevs; i++) { 1103 /* 1104 * Notify ACPI we're going to D0 but ignore the result. If 1105 * ACPI is not present, the firmware is responsible for 1106 * managing device power. Only manage type 0 devices for now. 1107 */ 1108 child = devlist[i]; 1109 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1110 if (acpi_dev && device_is_attached(child) && 1111 dinfo->cfg.hdrtype == 0) { 1112 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 1113 pci_set_powerstate(child, PCI_POWERSTATE_D0); 1114 } 1115 1116 /* Now the device is powered up, restore its config space. */ 1117 pci_cfg_restore(child, dinfo); 1118 } 1119 free(devlist, M_TEMP); 1120 return (bus_generic_resume(dev)); 1121 } 1122 1123 static void 1124 pci_load_vendor_data(void) 1125 { 1126 caddr_t vendordata, info; 1127 1128 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1129 info = preload_search_info(vendordata, MODINFO_ADDR); 1130 pci_vendordata = *(char **)info; 1131 info = preload_search_info(vendordata, MODINFO_SIZE); 1132 pci_vendordata_size = *(size_t *)info; 1133 /* terminate the database */ 1134 pci_vendordata[pci_vendordata_size] = '\n'; 1135 } 1136 } 1137 1138 void 1139 pci_driver_added(device_t dev, driver_t *driver) 1140 { 1141 int numdevs; 1142 device_t *devlist; 1143 device_t child; 1144 struct pci_devinfo *dinfo; 1145 int i; 1146 1147 if (bootverbose) 1148 device_printf(dev, "driver added\n"); 1149 DEVICE_IDENTIFY(driver, dev); 1150 device_get_children(dev, &devlist, &numdevs); 1151 for (i = 0; i < numdevs; i++) { 1152 child = devlist[i]; 1153 if (device_get_state(child) != DS_NOTPRESENT) 1154 continue; 1155 dinfo = device_get_ivars(child); 1156 pci_print_verbose(dinfo); 1157 if (bootverbose) 1158 printf("pci%d:%d:%d: reprobing on driver added\n", 1159 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1160 pci_cfg_restore(child, dinfo); 1161 if (device_probe_and_attach(child) != 0) 1162 pci_cfg_save(child, dinfo, 1); 1163 } 1164 free(devlist, M_TEMP); 1165 } 1166 1167 int 1168 pci_print_child(device_t dev, device_t child) 1169 { 1170 struct pci_devinfo *dinfo; 1171 struct resource_list *rl; 1172 int retval = 0; 1173 1174 dinfo = device_get_ivars(child); 1175 rl = &dinfo->resources; 1176 1177 retval += bus_print_child_header(dev, child); 1178 1179 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1180 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1181 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1182 if (device_get_flags(dev)) 1183 retval += printf(" flags %#x", device_get_flags(dev)); 1184 1185 retval += printf(" at device %d.%d", pci_get_slot(child), 1186 pci_get_function(child)); 1187 1188 retval += bus_print_child_footer(dev, child); 1189 1190 return (retval); 1191 } 1192 1193 static struct 1194 { 1195 int class; 1196 int subclass; 1197 char *desc; 1198 } pci_nomatch_tab[] = { 1199 {PCIC_OLD, -1, "old"}, 1200 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1201 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1202 {PCIC_STORAGE, -1, "mass storage"}, 1203 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1204 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1205 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1206 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1207 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1208 {PCIC_NETWORK, -1, "network"}, 1209 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1210 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1211 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1212 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1213 {PCIC_DISPLAY, -1, "display"}, 1214 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1215 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1216 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1217 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1218 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1219 {PCIC_MEMORY, -1, "memory"}, 1220 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1221 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1222 {PCIC_BRIDGE, -1, "bridge"}, 1223 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1224 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1225 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1226 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1227 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1228 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1229 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1230 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1231 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 1232 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1233 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1234 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1235 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1236 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1237 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1238 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1239 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1240 {PCIC_INPUTDEV, -1, "input device"}, 1241 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1242 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1243 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1244 {PCIC_DOCKING, -1, "docking station"}, 1245 {PCIC_PROCESSOR, -1, "processor"}, 1246 {PCIC_SERIALBUS, -1, "serial bus"}, 1247 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1248 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1249 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1250 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1251 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1252 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1253 {0, 0, NULL} 1254 }; 1255 1256 void 1257 pci_probe_nomatch(device_t dev, device_t child) 1258 { 1259 int i; 1260 char *cp, *scp, *device; 1261 1262 /* 1263 * Look for a listing for this device in a loaded device database. 1264 */ 1265 if ((device = pci_describe_device(child)) != NULL) { 1266 device_printf(dev, "<%s>", device); 1267 free(device, M_DEVBUF); 1268 } else { 1269 /* 1270 * Scan the class/subclass descriptions for a general 1271 * description. 1272 */ 1273 cp = "unknown"; 1274 scp = NULL; 1275 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1276 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1277 if (pci_nomatch_tab[i].subclass == -1) { 1278 cp = pci_nomatch_tab[i].desc; 1279 } else if (pci_nomatch_tab[i].subclass == 1280 pci_get_subclass(child)) { 1281 scp = pci_nomatch_tab[i].desc; 1282 } 1283 } 1284 } 1285 device_printf(dev, "<%s%s%s>", 1286 cp ? cp : "", 1287 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1288 scp ? scp : ""); 1289 } 1290 printf(" at device %d.%d (no driver attached)\n", 1291 pci_get_slot(child), pci_get_function(child)); 1292 if (pci_do_powerstate) 1293 pci_cfg_save(child, 1294 (struct pci_devinfo *) device_get_ivars(child), 1); 1295 return; 1296 } 1297 1298 /* 1299 * Parse the PCI device database, if loaded, and return a pointer to a 1300 * description of the device. 1301 * 1302 * The database is flat text formatted as follows: 1303 * 1304 * Any line not in a valid format is ignored. 1305 * Lines are terminated with newline '\n' characters. 1306 * 1307 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1308 * the vendor name. 1309 * 1310 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1311 * - devices cannot be listed without a corresponding VENDOR line. 1312 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1313 * another TAB, then the device name. 1314 */ 1315 1316 /* 1317 * Assuming (ptr) points to the beginning of a line in the database, 1318 * return the vendor or device and description of the next entry. 1319 * The value of (vendor) or (device) inappropriate for the entry type 1320 * is set to -1. Returns nonzero at the end of the database. 1321 * 1322 * Note that this is slightly unrobust in the face of corrupt data; 1323 * we attempt to safeguard against this by spamming the end of the 1324 * database with a newline when we initialise. 1325 */ 1326 static int 1327 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1328 { 1329 char *cp = *ptr; 1330 int left; 1331 1332 *device = -1; 1333 *vendor = -1; 1334 **desc = '\0'; 1335 for (;;) { 1336 left = pci_vendordata_size - (cp - pci_vendordata); 1337 if (left <= 0) { 1338 *ptr = cp; 1339 return(1); 1340 } 1341 1342 /* vendor entry? */ 1343 if (*cp != '\t' && 1344 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1345 break; 1346 /* device entry? */ 1347 if (*cp == '\t' && 1348 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1349 break; 1350 1351 /* skip to next line */ 1352 while (*cp != '\n' && left > 0) { 1353 cp++; 1354 left--; 1355 } 1356 if (*cp == '\n') { 1357 cp++; 1358 left--; 1359 } 1360 } 1361 /* skip to next line */ 1362 while (*cp != '\n' && left > 0) { 1363 cp++; 1364 left--; 1365 } 1366 if (*cp == '\n' && left > 0) 1367 cp++; 1368 *ptr = cp; 1369 return(0); 1370 } 1371 1372 static char * 1373 pci_describe_device(device_t dev) 1374 { 1375 int vendor, device; 1376 char *desc, *vp, *dp, *line; 1377 1378 desc = vp = dp = NULL; 1379 1380 /* 1381 * If we have no vendor data, we can't do anything. 1382 */ 1383 if (pci_vendordata == NULL) 1384 goto out; 1385 1386 /* 1387 * Scan the vendor data looking for this device 1388 */ 1389 line = pci_vendordata; 1390 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1391 goto out; 1392 for (;;) { 1393 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1394 goto out; 1395 if (vendor == pci_get_vendor(dev)) 1396 break; 1397 } 1398 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1399 goto out; 1400 for (;;) { 1401 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1402 *dp = 0; 1403 break; 1404 } 1405 if (vendor != -1) { 1406 *dp = 0; 1407 break; 1408 } 1409 if (device == pci_get_device(dev)) 1410 break; 1411 } 1412 if (dp[0] == '\0') 1413 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1414 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1415 NULL) 1416 sprintf(desc, "%s, %s", vp, dp); 1417 out: 1418 if (vp != NULL) 1419 free(vp, M_DEVBUF); 1420 if (dp != NULL) 1421 free(dp, M_DEVBUF); 1422 return(desc); 1423 } 1424 1425 int 1426 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1427 { 1428 struct pci_devinfo *dinfo; 1429 pcicfgregs *cfg; 1430 1431 dinfo = device_get_ivars(child); 1432 cfg = &dinfo->cfg; 1433 1434 switch (which) { 1435 case PCI_IVAR_ETHADDR: 1436 /* 1437 * The generic accessor doesn't deal with failure, so 1438 * we set the return value, then return an error. 1439 */ 1440 *((uint8_t **) result) = NULL; 1441 return (EINVAL); 1442 case PCI_IVAR_SUBVENDOR: 1443 *result = cfg->subvendor; 1444 break; 1445 case PCI_IVAR_SUBDEVICE: 1446 *result = cfg->subdevice; 1447 break; 1448 case PCI_IVAR_VENDOR: 1449 *result = cfg->vendor; 1450 break; 1451 case PCI_IVAR_DEVICE: 1452 *result = cfg->device; 1453 break; 1454 case PCI_IVAR_DEVID: 1455 *result = (cfg->device << 16) | cfg->vendor; 1456 break; 1457 case PCI_IVAR_CLASS: 1458 *result = cfg->baseclass; 1459 break; 1460 case PCI_IVAR_SUBCLASS: 1461 *result = cfg->subclass; 1462 break; 1463 case PCI_IVAR_PROGIF: 1464 *result = cfg->progif; 1465 break; 1466 case PCI_IVAR_REVID: 1467 *result = cfg->revid; 1468 break; 1469 case PCI_IVAR_INTPIN: 1470 *result = cfg->intpin; 1471 break; 1472 case PCI_IVAR_IRQ: 1473 *result = cfg->intline; 1474 break; 1475 case PCI_IVAR_BUS: 1476 *result = cfg->bus; 1477 break; 1478 case PCI_IVAR_SLOT: 1479 *result = cfg->slot; 1480 break; 1481 case PCI_IVAR_FUNCTION: 1482 *result = cfg->func; 1483 break; 1484 default: 1485 return (ENOENT); 1486 } 1487 return (0); 1488 } 1489 1490 int 1491 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1492 { 1493 struct pci_devinfo *dinfo; 1494 1495 dinfo = device_get_ivars(child); 1496 1497 switch (which) { 1498 case PCI_IVAR_INTPIN: 1499 dinfo->cfg.intpin = value; 1500 return (0); 1501 case PCI_IVAR_ETHADDR: 1502 case PCI_IVAR_SUBVENDOR: 1503 case PCI_IVAR_SUBDEVICE: 1504 case PCI_IVAR_VENDOR: 1505 case PCI_IVAR_DEVICE: 1506 case PCI_IVAR_DEVID: 1507 case PCI_IVAR_CLASS: 1508 case PCI_IVAR_SUBCLASS: 1509 case PCI_IVAR_PROGIF: 1510 case PCI_IVAR_REVID: 1511 case PCI_IVAR_IRQ: 1512 case PCI_IVAR_BUS: 1513 case PCI_IVAR_SLOT: 1514 case PCI_IVAR_FUNCTION: 1515 return (EINVAL); /* disallow for now */ 1516 1517 default: 1518 return (ENOENT); 1519 } 1520 } 1521 1522 1523 #include "opt_ddb.h" 1524 #ifdef DDB 1525 #include <ddb/ddb.h> 1526 #include <sys/cons.h> 1527 1528 /* 1529 * List resources based on pci map registers, used for within ddb 1530 */ 1531 1532 DB_SHOW_COMMAND(pciregs, db_pci_dump) 1533 { 1534 struct pci_devinfo *dinfo; 1535 struct devlist *devlist_head; 1536 struct pci_conf *p; 1537 const char *name; 1538 int i, error, none_count, quit; 1539 1540 none_count = 0; 1541 /* get the head of the device queue */ 1542 devlist_head = &pci_devq; 1543 1544 /* 1545 * Go through the list of devices and print out devices 1546 */ 1547 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 1548 for (error = 0, i = 0, quit = 0, 1549 dinfo = STAILQ_FIRST(devlist_head); 1550 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1551 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1552 1553 /* Populate pd_name and pd_unit */ 1554 name = NULL; 1555 if (dinfo->cfg.dev) 1556 name = device_get_name(dinfo->cfg.dev); 1557 1558 p = &dinfo->conf; 1559 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1560 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1561 (name && *name) ? name : "none", 1562 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1563 none_count++, 1564 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1565 p->pc_sel.pc_func, (p->pc_class << 16) | 1566 (p->pc_subclass << 8) | p->pc_progif, 1567 (p->pc_subdevice << 16) | p->pc_subvendor, 1568 (p->pc_device << 16) | p->pc_vendor, 1569 p->pc_revid, p->pc_hdr); 1570 } 1571 } 1572 #endif /* DDB */ 1573 1574 static struct resource * 1575 pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1576 u_long start, u_long end, u_long count, u_int flags) 1577 { 1578 struct pci_devinfo *dinfo = device_get_ivars(child); 1579 struct resource_list *rl = &dinfo->resources; 1580 struct resource_list_entry *rle; 1581 struct resource *res; 1582 uint32_t map, testval; 1583 int mapsize; 1584 1585 /* 1586 * Weed out the bogons, and figure out how large the BAR/map 1587 * is. Bars that read back 0 here are bogus and unimplemented. 1588 * Note: atapci in legacy mode are special and handled elsewhere 1589 * in the code. If you have a atapci device in legacy mode and 1590 * it fails here, that other code is broken. 1591 */ 1592 res = NULL; 1593 map = pci_read_config(child, *rid, 4); 1594 pci_write_config(child, *rid, 0xffffffff, 4); 1595 testval = pci_read_config(child, *rid, 4); 1596 if (testval == 0) 1597 return (NULL); 1598 if (pci_maptype(testval) & PCI_MAPMEM) { 1599 if (type != SYS_RES_MEMORY) { 1600 device_printf(child, 1601 "failed: rid %#x is memory, requested %d\n", 1602 *rid, type); 1603 goto out; 1604 } 1605 } else { 1606 if (type != SYS_RES_IOPORT) { 1607 device_printf(child, 1608 "failed: rid %#x is ioport, requested %d\n", 1609 *rid, type); 1610 goto out; 1611 } 1612 } 1613 /* 1614 * For real BARs, we need to override the size that 1615 * the driver requests, because that's what the BAR 1616 * actually uses and we would otherwise have a 1617 * situation where we might allocate the excess to 1618 * another driver, which won't work. 1619 */ 1620 mapsize = pci_mapsize(testval); 1621 count = 1 << mapsize; 1622 if (RF_ALIGNMENT(flags) < mapsize) 1623 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1624 1625 /* 1626 * Allocate enough resource, and then write back the 1627 * appropriate bar for that resource. 1628 */ 1629 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1630 start, end, count, flags); 1631 if (res == NULL) { 1632 device_printf(child, "%#lx bytes of rid %#x res %d failed.\n", 1633 count, *rid, type); 1634 goto out; 1635 } 1636 resource_list_add(rl, type, *rid, start, end, count); 1637 rle = resource_list_find(rl, type, *rid); 1638 if (rle == NULL) 1639 panic("pci_alloc_map: unexpectedly can't find resource."); 1640 rle->res = res; 1641 if (bootverbose) 1642 device_printf(child, 1643 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1644 count, *rid, type, rman_get_start(res)); 1645 map = rman_get_start(res); 1646 out:; 1647 pci_write_config(child, *rid, map, 4); 1648 return (res); 1649 } 1650 1651 1652 struct resource * 1653 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1654 u_long start, u_long end, u_long count, u_int flags) 1655 { 1656 struct pci_devinfo *dinfo = device_get_ivars(child); 1657 struct resource_list *rl = &dinfo->resources; 1658 struct resource_list_entry *rle; 1659 pcicfgregs *cfg = &dinfo->cfg; 1660 1661 /* 1662 * Perform lazy resource allocation 1663 */ 1664 if (device_get_parent(child) == dev) { 1665 switch (type) { 1666 case SYS_RES_IRQ: 1667 /* 1668 * If the child device doesn't have an 1669 * interrupt routed and is deserving of an 1670 * interrupt, try to assign it one. 1671 */ 1672 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1673 (cfg->intpin != 0)) { 1674 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1675 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1676 pci_write_config(child, PCIR_INTLINE, 1677 cfg->intline, 1); 1678 resource_list_add(rl, SYS_RES_IRQ, 0, 1679 cfg->intline, cfg->intline, 1); 1680 } 1681 } 1682 break; 1683 case SYS_RES_IOPORT: 1684 case SYS_RES_MEMORY: 1685 if (*rid < PCIR_BAR(cfg->nummaps)) { 1686 /* 1687 * Enable the I/O mode. We should 1688 * also be assigning resources too 1689 * when none are present. The 1690 * resource_list_alloc kind of sorta does 1691 * this... 1692 */ 1693 if (PCI_ENABLE_IO(dev, child, type)) 1694 return (NULL); 1695 } 1696 rle = resource_list_find(rl, type, *rid); 1697 if (rle == NULL) 1698 return (pci_alloc_map(dev, child, type, rid, 1699 start, end, count, flags)); 1700 break; 1701 } 1702 /* 1703 * If we've already allocated the resource, then 1704 * return it now. But first we may need to activate 1705 * it, since we don't allocate the resource as active 1706 * above. Normally this would be done down in the 1707 * nexus, but since we short-circuit that path we have 1708 * to do its job here. Not sure if we should free the 1709 * resource if it fails to activate. 1710 */ 1711 rle = resource_list_find(rl, type, *rid); 1712 if (rle != NULL && rle->res != NULL) { 1713 if (bootverbose) 1714 device_printf(child, 1715 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 1716 rman_get_size(rle->res), *rid, type, 1717 rman_get_start(rle->res)); 1718 if ((flags & RF_ACTIVE) && 1719 bus_generic_activate_resource(dev, child, type, 1720 *rid, rle->res) != 0) 1721 return NULL; 1722 return (rle->res); 1723 } 1724 } 1725 return (resource_list_alloc(rl, dev, child, type, rid, 1726 start, end, count, flags)); 1727 } 1728 1729 void 1730 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1731 { 1732 struct pci_devinfo *dinfo; 1733 struct resource_list *rl; 1734 struct resource_list_entry *rle; 1735 1736 if (device_get_parent(child) != dev) 1737 return; 1738 1739 dinfo = device_get_ivars(child); 1740 rl = &dinfo->resources; 1741 rle = resource_list_find(rl, type, rid); 1742 if (rle) { 1743 if (rle->res) { 1744 if (rman_get_device(rle->res) != dev || 1745 rman_get_flags(rle->res) & RF_ACTIVE) { 1746 device_printf(dev, "delete_resource: " 1747 "Resource still owned by child, oops. " 1748 "(type=%d, rid=%d, addr=%lx)\n", 1749 rle->type, rle->rid, 1750 rman_get_start(rle->res)); 1751 return; 1752 } 1753 bus_release_resource(dev, type, rid, rle->res); 1754 } 1755 resource_list_delete(rl, type, rid); 1756 } 1757 /* 1758 * Why do we turn off the PCI configuration BAR when we delete a 1759 * resource? -- imp 1760 */ 1761 pci_write_config(child, rid, 0, 4); 1762 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1763 } 1764 1765 struct resource_list * 1766 pci_get_resource_list (device_t dev, device_t child) 1767 { 1768 struct pci_devinfo *dinfo = device_get_ivars(child); 1769 1770 return (&dinfo->resources); 1771 } 1772 1773 uint32_t 1774 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1775 { 1776 struct pci_devinfo *dinfo = device_get_ivars(child); 1777 pcicfgregs *cfg = &dinfo->cfg; 1778 1779 return (PCIB_READ_CONFIG(device_get_parent(dev), 1780 cfg->bus, cfg->slot, cfg->func, reg, width)); 1781 } 1782 1783 void 1784 pci_write_config_method(device_t dev, device_t child, int reg, 1785 uint32_t val, int width) 1786 { 1787 struct pci_devinfo *dinfo = device_get_ivars(child); 1788 pcicfgregs *cfg = &dinfo->cfg; 1789 1790 PCIB_WRITE_CONFIG(device_get_parent(dev), 1791 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1792 } 1793 1794 int 1795 pci_child_location_str_method(device_t dev, device_t child, char *buf, 1796 size_t buflen) 1797 { 1798 1799 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1800 pci_get_function(child)); 1801 return (0); 1802 } 1803 1804 int 1805 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1806 size_t buflen) 1807 { 1808 struct pci_devinfo *dinfo; 1809 pcicfgregs *cfg; 1810 1811 dinfo = device_get_ivars(child); 1812 cfg = &dinfo->cfg; 1813 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1814 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1815 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1816 cfg->progif); 1817 return (0); 1818 } 1819 1820 int 1821 pci_assign_interrupt_method(device_t dev, device_t child) 1822 { 1823 struct pci_devinfo *dinfo = device_get_ivars(child); 1824 pcicfgregs *cfg = &dinfo->cfg; 1825 1826 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1827 cfg->intpin)); 1828 } 1829 1830 static int 1831 pci_modevent(module_t mod, int what, void *arg) 1832 { 1833 static struct cdev *pci_cdev; 1834 1835 switch (what) { 1836 case MOD_LOAD: 1837 STAILQ_INIT(&pci_devq); 1838 pci_generation = 0; 1839 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1840 "pci"); 1841 pci_load_vendor_data(); 1842 break; 1843 1844 case MOD_UNLOAD: 1845 destroy_dev(pci_cdev); 1846 break; 1847 } 1848 1849 return (0); 1850 } 1851 1852 void 1853 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 1854 { 1855 int i; 1856 1857 /* 1858 * Only do header type 0 devices. Type 1 devices are bridges, 1859 * which we know need special treatment. Type 2 devices are 1860 * cardbus bridges which also require special treatment. 1861 * Other types are unknown, and we err on the side of safety 1862 * by ignoring them. 1863 */ 1864 if (dinfo->cfg.hdrtype != 0) 1865 return; 1866 1867 /* 1868 * Restore the device to full power mode. We must do this 1869 * before we restore the registers because moving from D3 to 1870 * D0 will cause the chip's BARs and some other registers to 1871 * be reset to some unknown power on reset values. Cut down 1872 * the noise on boot by doing nothing if we are already in 1873 * state D0. 1874 */ 1875 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1876 if (bootverbose) 1877 printf( 1878 "pci%d:%d:%d: Transition from D%d to D0\n", 1879 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 1880 pci_get_powerstate(dev)); 1881 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1882 } 1883 for (i = 0; i < dinfo->cfg.nummaps; i++) 1884 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 1885 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 1886 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 1887 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 1888 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 1889 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 1890 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 1891 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 1892 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 1893 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 1894 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 1895 } 1896 1897 void 1898 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 1899 { 1900 int i; 1901 uint32_t cls; 1902 int ps; 1903 1904 /* 1905 * Only do header type 0 devices. Type 1 devices are bridges, which 1906 * we know need special treatment. Type 2 devices are cardbus bridges 1907 * which also require special treatment. Other types are unknown, and 1908 * we err on the side of safety by ignoring them. Powering down 1909 * bridges should not be undertaken lightly. 1910 */ 1911 if (dinfo->cfg.hdrtype != 0) 1912 return; 1913 for (i = 0; i < dinfo->cfg.nummaps; i++) 1914 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1915 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 1916 1917 /* 1918 * Some drivers apparently write to these registers w/o updating our 1919 * cached copy. No harm happens if we update the copy, so do so here 1920 * so we can restore them. The COMMAND register is modified by the 1921 * bus w/o updating the cache. This should represent the normally 1922 * writable portion of the 'defined' part of type 0 headers. In 1923 * theory we also need to save/restore the PCI capability structures 1924 * we know about, but apart from power we don't know any that are 1925 * writable. 1926 */ 1927 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1928 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1929 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 1930 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 1931 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 1932 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 1933 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 1934 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 1935 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 1936 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1937 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1938 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 1939 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 1940 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 1941 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 1942 1943 /* 1944 * don't set the state for display devices, base peripherals and 1945 * memory devices since bad things happen when they are powered down. 1946 * We should (a) have drivers that can easily detach and (b) use 1947 * generic drivers for these devices so that some device actually 1948 * attaches. We need to make sure that when we implement (a) we don't 1949 * power the device down on a reattach. 1950 */ 1951 cls = pci_get_class(dev); 1952 if (setstate && cls != PCIC_DISPLAY && cls != PCIC_MEMORY && 1953 cls != PCIC_BASEPERIPH) { 1954 /* 1955 * PCI spec says we can only go into D3 state from D0 state. 1956 * Transition from D[12] into D0 before going to D3 state. 1957 */ 1958 ps = pci_get_powerstate(dev); 1959 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) { 1960 if (bootverbose) 1961 printf( 1962 "pci%d:%d:%d: Transition from D%d to D0\n", 1963 dinfo->cfg.bus, dinfo->cfg.slot, 1964 dinfo->cfg.func, ps); 1965 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1966 } 1967 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) { 1968 if (bootverbose) 1969 printf( 1970 "pci%d:%d:%d: Transition from D0 to D3\n", 1971 dinfo->cfg.bus, dinfo->cfg.slot, 1972 dinfo->cfg.func); 1973 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 1974 } 1975 } 1976 } 1977