1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 5 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000, BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice unmodified, this list of conditions, and the following 14 * disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "opt_acpi.h" 35 #include "opt_bus.h" 36 37 #include <sys/param.h> 38 #include <sys/conf.h> 39 #include <sys/endian.h> 40 #include <sys/eventhandler.h> 41 #include <sys/fcntl.h> 42 #include <sys/kernel.h> 43 #include <sys/limits.h> 44 #include <sys/linker.h> 45 #include <sys/malloc.h> 46 #include <sys/module.h> 47 #include <sys/queue.h> 48 #include <sys/sysctl.h> 49 #include <sys/systm.h> 50 51 #include <vm/vm.h> 52 #include <vm/pmap.h> 53 #include <vm/vm_extern.h> 54 55 #include <sys/bus.h> 56 #include <machine/bus.h> 57 #include <sys/rman.h> 58 #include <machine/resource.h> 59 #include <machine/stdarg.h> 60 61 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 62 #include <machine/intr_machdep.h> 63 #endif 64 65 #include <sys/pciio.h> 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pci_private.h> 69 70 #ifdef PCI_IOV 71 #include <sys/nv.h> 72 #include <dev/pci/pci_iov_private.h> 73 #endif 74 75 #include <dev/usb/controller/xhcireg.h> 76 #include <dev/usb/controller/ehcireg.h> 77 #include <dev/usb/controller/ohcireg.h> 78 #include <dev/usb/controller/uhcireg.h> 79 80 #include "pcib_if.h" 81 #include "pci_if.h" 82 83 #define PCIR_IS_BIOS(cfg, reg) \ 84 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ 85 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) 86 87 static int pci_has_quirk(uint32_t devid, int quirk); 88 static pci_addr_t pci_mapbase(uint64_t mapreg); 89 static const char *pci_maptype(uint64_t mapreg); 90 static int pci_maprange(uint64_t mapreg); 91 static pci_addr_t pci_rombase(uint64_t mapreg); 92 static int pci_romsize(uint64_t testval); 93 static void pci_fixancient(pcicfgregs *cfg); 94 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...); 95 96 static int pci_porten(device_t dev); 97 static int pci_memen(device_t dev); 98 static void pci_assign_interrupt(device_t bus, device_t dev, 99 int force_route); 100 static int pci_add_map(device_t bus, device_t dev, int reg, 101 struct resource_list *rl, int force, int prefetch); 102 static int pci_probe(device_t dev); 103 static void pci_load_vendor_data(void); 104 static int pci_describe_parse_line(char **ptr, int *vendor, 105 int *device, char **desc); 106 static char *pci_describe_device(device_t dev); 107 static int pci_modevent(module_t mod, int what, void *arg); 108 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 109 pcicfgregs *cfg); 110 static void pci_read_cap(device_t pcib, pcicfgregs *cfg); 111 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 112 int reg, uint32_t *data); 113 #if 0 114 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 115 int reg, uint32_t data); 116 #endif 117 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 118 static void pci_mask_msix(device_t dev, u_int index); 119 static void pci_unmask_msix(device_t dev, u_int index); 120 static int pci_msi_blacklisted(void); 121 static int pci_msix_blacklisted(void); 122 static void pci_resume_msi(device_t dev); 123 static void pci_resume_msix(device_t dev); 124 static int pci_remap_intr_method(device_t bus, device_t dev, 125 u_int irq); 126 static void pci_hint_device_unit(device_t acdev, device_t child, 127 const char *name, int *unitp); 128 static int pci_reset_post(device_t dev, device_t child); 129 static int pci_reset_prepare(device_t dev, device_t child); 130 static int pci_reset_child(device_t dev, device_t child, 131 int flags); 132 133 static int pci_get_id_method(device_t dev, device_t child, 134 enum pci_id_type type, uintptr_t *rid); 135 136 static struct pci_devinfo * pci_fill_devinfo(device_t pcib, device_t bus, int d, 137 int b, int s, int f, uint16_t vid, uint16_t did); 138 139 static device_method_t pci_methods[] = { 140 /* Device interface */ 141 DEVMETHOD(device_probe, pci_probe), 142 DEVMETHOD(device_attach, pci_attach), 143 DEVMETHOD(device_detach, pci_detach), 144 DEVMETHOD(device_shutdown, bus_generic_shutdown), 145 DEVMETHOD(device_suspend, bus_generic_suspend), 146 DEVMETHOD(device_resume, pci_resume), 147 148 /* Bus interface */ 149 DEVMETHOD(bus_print_child, pci_print_child), 150 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 151 DEVMETHOD(bus_read_ivar, pci_read_ivar), 152 DEVMETHOD(bus_write_ivar, pci_write_ivar), 153 DEVMETHOD(bus_driver_added, pci_driver_added), 154 DEVMETHOD(bus_setup_intr, pci_setup_intr), 155 DEVMETHOD(bus_teardown_intr, pci_teardown_intr), 156 DEVMETHOD(bus_reset_prepare, pci_reset_prepare), 157 DEVMETHOD(bus_reset_post, pci_reset_post), 158 DEVMETHOD(bus_reset_child, pci_reset_child), 159 160 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag), 161 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 162 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 163 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 164 DEVMETHOD(bus_delete_resource, pci_delete_resource), 165 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 166 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 167 DEVMETHOD(bus_release_resource, pci_release_resource), 168 DEVMETHOD(bus_activate_resource, pci_activate_resource), 169 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource), 170 DEVMETHOD(bus_child_deleted, pci_child_deleted), 171 DEVMETHOD(bus_child_detached, pci_child_detached), 172 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 173 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 174 DEVMETHOD(bus_hint_device_unit, pci_hint_device_unit), 175 DEVMETHOD(bus_remap_intr, pci_remap_intr_method), 176 DEVMETHOD(bus_suspend_child, pci_suspend_child), 177 DEVMETHOD(bus_resume_child, pci_resume_child), 178 DEVMETHOD(bus_rescan, pci_rescan_method), 179 180 /* PCI interface */ 181 DEVMETHOD(pci_read_config, pci_read_config_method), 182 DEVMETHOD(pci_write_config, pci_write_config_method), 183 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 184 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 185 DEVMETHOD(pci_enable_io, pci_enable_io_method), 186 DEVMETHOD(pci_disable_io, pci_disable_io_method), 187 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 188 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 189 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 190 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 191 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 192 DEVMETHOD(pci_find_cap, pci_find_cap_method), 193 DEVMETHOD(pci_find_next_cap, pci_find_next_cap_method), 194 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 195 DEVMETHOD(pci_find_next_extcap, pci_find_next_extcap_method), 196 DEVMETHOD(pci_find_htcap, pci_find_htcap_method), 197 DEVMETHOD(pci_find_next_htcap, pci_find_next_htcap_method), 198 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 199 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), 200 DEVMETHOD(pci_enable_msi, pci_enable_msi_method), 201 DEVMETHOD(pci_enable_msix, pci_enable_msix_method), 202 DEVMETHOD(pci_disable_msi, pci_disable_msi_method), 203 DEVMETHOD(pci_remap_msix, pci_remap_msix_method), 204 DEVMETHOD(pci_release_msi, pci_release_msi_method), 205 DEVMETHOD(pci_msi_count, pci_msi_count_method), 206 DEVMETHOD(pci_msix_count, pci_msix_count_method), 207 DEVMETHOD(pci_msix_pba_bar, pci_msix_pba_bar_method), 208 DEVMETHOD(pci_msix_table_bar, pci_msix_table_bar_method), 209 DEVMETHOD(pci_get_id, pci_get_id_method), 210 DEVMETHOD(pci_alloc_devinfo, pci_alloc_devinfo_method), 211 DEVMETHOD(pci_child_added, pci_child_added_method), 212 #ifdef PCI_IOV 213 DEVMETHOD(pci_iov_attach, pci_iov_attach_method), 214 DEVMETHOD(pci_iov_detach, pci_iov_detach_method), 215 DEVMETHOD(pci_create_iov_child, pci_create_iov_child_method), 216 #endif 217 218 DEVMETHOD_END 219 }; 220 221 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc)); 222 223 static devclass_t pci_devclass; 224 EARLY_DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL, 225 BUS_PASS_BUS); 226 MODULE_VERSION(pci, 1); 227 228 static char *pci_vendordata; 229 static size_t pci_vendordata_size; 230 231 struct pci_quirk { 232 uint32_t devid; /* Vendor/device of the card */ 233 int type; 234 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 235 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */ 236 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */ 237 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */ 238 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */ 239 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */ 240 #define PCI_QUIRK_REALLOC_BAR 7 /* Can't allocate memory at the default address */ 241 int arg1; 242 int arg2; 243 }; 244 245 static const struct pci_quirk pci_quirks[] = { 246 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */ 247 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 248 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 249 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 250 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 251 252 /* 253 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge 254 * or the CMIC-SL (AKA ServerWorks GC_LE). 255 */ 256 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 257 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 258 259 /* 260 * MSI doesn't work on earlier Intel chipsets including 261 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855. 262 */ 263 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 264 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 265 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 266 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 267 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 268 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 269 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 270 271 /* 272 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX 273 * bridge. 274 */ 275 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 276 277 /* 278 * Some virtualization environments emulate an older chipset 279 * but support MSI just fine. QEMU uses the Intel 82440. 280 */ 281 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 }, 282 283 /* 284 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus 285 * controller depending on SoftPciRst register (PM_IO 0x55 [7]). 286 * It prevents us from attaching hpet(4) when the bit is unset. 287 * Note this quirk only affects SB600 revision A13 and earlier. 288 * For SB600 A21 and later, firmware must set the bit to hide it. 289 * For SB700 and later, it is unused and hardcoded to zero. 290 */ 291 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 }, 292 293 /* 294 * Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have 295 * a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit 296 * of the command register is set. 297 */ 298 { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 299 { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 300 { 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 301 { 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 302 { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 303 304 /* 305 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't 306 * issue MSI interrupts with PCIM_CMD_INTxDIS set either. 307 */ 308 { 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */ 309 { 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */ 310 { 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */ 311 { 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */ 312 { 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */ 313 { 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */ 314 315 /* 316 * HPE Gen 10 VGA has a memory range that can't be allocated in the 317 * expected place. 318 */ 319 { 0x98741002, PCI_QUIRK_REALLOC_BAR, 0, 0 }, 320 { 0 } 321 }; 322 323 /* map register information */ 324 #define PCI_MAPMEM 0x01 /* memory map */ 325 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 326 #define PCI_MAPPORT 0x04 /* port map */ 327 328 struct devlist pci_devq; 329 uint32_t pci_generation; 330 uint32_t pci_numdevs = 0; 331 static int pcie_chipset, pcix_chipset; 332 333 /* sysctl vars */ 334 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 335 "PCI bus tuning parameters"); 336 337 static int pci_enable_io_modes = 1; 338 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RWTUN, 339 &pci_enable_io_modes, 1, 340 "Enable I/O and memory bits in the config register. Some BIOSes do not" 341 " enable these bits correctly. We'd like to do this all the time, but" 342 " there are some peripherals that this causes problems with."); 343 344 static int pci_do_realloc_bars = 1; 345 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RWTUN, 346 &pci_do_realloc_bars, 0, 347 "Attempt to allocate a new range for any BARs whose original " 348 "firmware-assigned ranges fail to allocate during the initial device scan."); 349 350 static int pci_do_power_nodriver = 0; 351 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RWTUN, 352 &pci_do_power_nodriver, 0, 353 "Place a function into D3 state when no driver attaches to it. 0 means" 354 " disable. 1 means conservatively place devices into D3 state. 2 means" 355 " aggressively place devices into D3 state. 3 means put absolutely" 356 " everything in D3 state."); 357 358 int pci_do_power_resume = 1; 359 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RWTUN, 360 &pci_do_power_resume, 1, 361 "Transition from D3 -> D0 on resume."); 362 363 int pci_do_power_suspend = 1; 364 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RWTUN, 365 &pci_do_power_suspend, 1, 366 "Transition from D0 -> D3 on suspend."); 367 368 static int pci_do_msi = 1; 369 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RWTUN, &pci_do_msi, 1, 370 "Enable support for MSI interrupts"); 371 372 static int pci_do_msix = 1; 373 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RWTUN, &pci_do_msix, 1, 374 "Enable support for MSI-X interrupts"); 375 376 static int pci_msix_rewrite_table = 0; 377 SYSCTL_INT(_hw_pci, OID_AUTO, msix_rewrite_table, CTLFLAG_RWTUN, 378 &pci_msix_rewrite_table, 0, 379 "Rewrite entire MSI-X table when updating MSI-X entries"); 380 381 static int pci_honor_msi_blacklist = 1; 382 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RDTUN, 383 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X"); 384 385 #if defined(__i386__) || defined(__amd64__) 386 static int pci_usb_takeover = 1; 387 #else 388 static int pci_usb_takeover = 0; 389 #endif 390 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN, 391 &pci_usb_takeover, 1, 392 "Enable early takeover of USB controllers. Disable this if you depend on" 393 " BIOS emulation of USB devices, that is you use USB devices (like" 394 " keyboard or mouse) but do not load USB drivers"); 395 396 static int pci_clear_bars; 397 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0, 398 "Ignore firmware-assigned resources for BARs."); 399 400 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 401 static int pci_clear_buses; 402 SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0, 403 "Ignore firmware-assigned bus numbers."); 404 #endif 405 406 static int pci_enable_ari = 1; 407 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari, 408 0, "Enable support for PCIe Alternative RID Interpretation"); 409 410 int pci_enable_aspm = 1; 411 SYSCTL_INT(_hw_pci, OID_AUTO, enable_aspm, CTLFLAG_RDTUN, &pci_enable_aspm, 412 0, "Enable support for PCIe Active State Power Management"); 413 414 static int pci_clear_aer_on_attach = 0; 415 SYSCTL_INT(_hw_pci, OID_AUTO, clear_aer_on_attach, CTLFLAG_RWTUN, 416 &pci_clear_aer_on_attach, 0, 417 "Clear port and device AER state on driver attach"); 418 419 static int 420 pci_has_quirk(uint32_t devid, int quirk) 421 { 422 const struct pci_quirk *q; 423 424 for (q = &pci_quirks[0]; q->devid; q++) { 425 if (q->devid == devid && q->type == quirk) 426 return (1); 427 } 428 return (0); 429 } 430 431 /* Find a device_t by bus/slot/function in domain 0 */ 432 433 device_t 434 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 435 { 436 437 return (pci_find_dbsf(0, bus, slot, func)); 438 } 439 440 /* Find a device_t by domain/bus/slot/function */ 441 442 device_t 443 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func) 444 { 445 struct pci_devinfo *dinfo = NULL; 446 447 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 448 if ((dinfo->cfg.domain == domain) && 449 (dinfo->cfg.bus == bus) && 450 (dinfo->cfg.slot == slot) && 451 (dinfo->cfg.func == func)) { 452 break; 453 } 454 } 455 456 return (dinfo != NULL ? dinfo->cfg.dev : NULL); 457 } 458 459 /* Find a device_t by vendor/device ID */ 460 461 device_t 462 pci_find_device(uint16_t vendor, uint16_t device) 463 { 464 struct pci_devinfo *dinfo; 465 466 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 467 if ((dinfo->cfg.vendor == vendor) && 468 (dinfo->cfg.device == device)) { 469 return (dinfo->cfg.dev); 470 } 471 } 472 473 return (NULL); 474 } 475 476 device_t 477 pci_find_class(uint8_t class, uint8_t subclass) 478 { 479 struct pci_devinfo *dinfo; 480 481 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 482 if (dinfo->cfg.baseclass == class && 483 dinfo->cfg.subclass == subclass) { 484 return (dinfo->cfg.dev); 485 } 486 } 487 488 return (NULL); 489 } 490 491 static int 492 pci_printf(pcicfgregs *cfg, const char *fmt, ...) 493 { 494 va_list ap; 495 int retval; 496 497 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, 498 cfg->func); 499 va_start(ap, fmt); 500 retval += vprintf(fmt, ap); 501 va_end(ap); 502 return (retval); 503 } 504 505 /* return base address of memory or port map */ 506 507 static pci_addr_t 508 pci_mapbase(uint64_t mapreg) 509 { 510 511 if (PCI_BAR_MEM(mapreg)) 512 return (mapreg & PCIM_BAR_MEM_BASE); 513 else 514 return (mapreg & PCIM_BAR_IO_BASE); 515 } 516 517 /* return map type of memory or port map */ 518 519 static const char * 520 pci_maptype(uint64_t mapreg) 521 { 522 523 if (PCI_BAR_IO(mapreg)) 524 return ("I/O Port"); 525 if (mapreg & PCIM_BAR_MEM_PREFETCH) 526 return ("Prefetchable Memory"); 527 return ("Memory"); 528 } 529 530 /* return log2 of map size decoded for memory or port map */ 531 532 int 533 pci_mapsize(uint64_t testval) 534 { 535 int ln2size; 536 537 testval = pci_mapbase(testval); 538 ln2size = 0; 539 if (testval != 0) { 540 while ((testval & 1) == 0) 541 { 542 ln2size++; 543 testval >>= 1; 544 } 545 } 546 return (ln2size); 547 } 548 549 /* return base address of device ROM */ 550 551 static pci_addr_t 552 pci_rombase(uint64_t mapreg) 553 { 554 555 return (mapreg & PCIM_BIOS_ADDR_MASK); 556 } 557 558 /* return log2 of map size decided for device ROM */ 559 560 static int 561 pci_romsize(uint64_t testval) 562 { 563 int ln2size; 564 565 testval = pci_rombase(testval); 566 ln2size = 0; 567 if (testval != 0) { 568 while ((testval & 1) == 0) 569 { 570 ln2size++; 571 testval >>= 1; 572 } 573 } 574 return (ln2size); 575 } 576 577 /* return log2 of address range supported by map register */ 578 579 static int 580 pci_maprange(uint64_t mapreg) 581 { 582 int ln2range = 0; 583 584 if (PCI_BAR_IO(mapreg)) 585 ln2range = 32; 586 else 587 switch (mapreg & PCIM_BAR_MEM_TYPE) { 588 case PCIM_BAR_MEM_32: 589 ln2range = 32; 590 break; 591 case PCIM_BAR_MEM_1MB: 592 ln2range = 20; 593 break; 594 case PCIM_BAR_MEM_64: 595 ln2range = 64; 596 break; 597 } 598 return (ln2range); 599 } 600 601 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 602 603 static void 604 pci_fixancient(pcicfgregs *cfg) 605 { 606 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 607 return; 608 609 /* PCI to PCI bridges use header type 1 */ 610 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 611 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; 612 } 613 614 /* extract header type specific config data */ 615 616 static void 617 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 618 { 619 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 620 switch (cfg->hdrtype & PCIM_HDRTYPE) { 621 case PCIM_HDRTYPE_NORMAL: 622 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 623 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 624 cfg->mingnt = REG(PCIR_MINGNT, 1); 625 cfg->maxlat = REG(PCIR_MAXLAT, 1); 626 cfg->nummaps = PCI_MAXMAPS_0; 627 break; 628 case PCIM_HDRTYPE_BRIDGE: 629 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1); 630 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1); 631 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1); 632 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1); 633 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2); 634 cfg->nummaps = PCI_MAXMAPS_1; 635 break; 636 case PCIM_HDRTYPE_CARDBUS: 637 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1); 638 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1); 639 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1); 640 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1); 641 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2); 642 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 643 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 644 cfg->nummaps = PCI_MAXMAPS_2; 645 break; 646 } 647 #undef REG 648 } 649 650 /* read configuration header into pcicfgregs structure */ 651 struct pci_devinfo * 652 pci_read_device(device_t pcib, device_t bus, int d, int b, int s, int f) 653 { 654 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 655 uint16_t vid, did; 656 657 vid = REG(PCIR_VENDOR, 2); 658 did = REG(PCIR_DEVICE, 2); 659 if (vid != 0xffff) 660 return (pci_fill_devinfo(pcib, bus, d, b, s, f, vid, did)); 661 662 return (NULL); 663 } 664 665 struct pci_devinfo * 666 pci_alloc_devinfo_method(device_t dev) 667 { 668 669 return (malloc(sizeof(struct pci_devinfo), M_DEVBUF, 670 M_WAITOK | M_ZERO)); 671 } 672 673 static struct pci_devinfo * 674 pci_fill_devinfo(device_t pcib, device_t bus, int d, int b, int s, int f, 675 uint16_t vid, uint16_t did) 676 { 677 struct pci_devinfo *devlist_entry; 678 pcicfgregs *cfg; 679 680 devlist_entry = PCI_ALLOC_DEVINFO(bus); 681 682 cfg = &devlist_entry->cfg; 683 684 cfg->domain = d; 685 cfg->bus = b; 686 cfg->slot = s; 687 cfg->func = f; 688 cfg->vendor = vid; 689 cfg->device = did; 690 cfg->cmdreg = REG(PCIR_COMMAND, 2); 691 cfg->statreg = REG(PCIR_STATUS, 2); 692 cfg->baseclass = REG(PCIR_CLASS, 1); 693 cfg->subclass = REG(PCIR_SUBCLASS, 1); 694 cfg->progif = REG(PCIR_PROGIF, 1); 695 cfg->revid = REG(PCIR_REVID, 1); 696 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 697 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 698 cfg->lattimer = REG(PCIR_LATTIMER, 1); 699 cfg->intpin = REG(PCIR_INTPIN, 1); 700 cfg->intline = REG(PCIR_INTLINE, 1); 701 702 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 703 cfg->hdrtype &= ~PCIM_MFDEV; 704 STAILQ_INIT(&cfg->maps); 705 706 cfg->iov = NULL; 707 708 pci_fixancient(cfg); 709 pci_hdrtypedata(pcib, b, s, f, cfg); 710 711 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 712 pci_read_cap(pcib, cfg); 713 714 STAILQ_INSERT_TAIL(&pci_devq, devlist_entry, pci_links); 715 716 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; 717 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 718 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 719 devlist_entry->conf.pc_sel.pc_func = cfg->func; 720 devlist_entry->conf.pc_hdr = cfg->hdrtype; 721 722 devlist_entry->conf.pc_subvendor = cfg->subvendor; 723 devlist_entry->conf.pc_subdevice = cfg->subdevice; 724 devlist_entry->conf.pc_vendor = cfg->vendor; 725 devlist_entry->conf.pc_device = cfg->device; 726 727 devlist_entry->conf.pc_class = cfg->baseclass; 728 devlist_entry->conf.pc_subclass = cfg->subclass; 729 devlist_entry->conf.pc_progif = cfg->progif; 730 devlist_entry->conf.pc_revid = cfg->revid; 731 732 pci_numdevs++; 733 pci_generation++; 734 735 return (devlist_entry); 736 } 737 #undef REG 738 739 static void 740 pci_ea_fill_info(device_t pcib, pcicfgregs *cfg) 741 { 742 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \ 743 cfg->ea.ea_location + (n), w) 744 int num_ent; 745 int ptr; 746 int a, b; 747 uint32_t val; 748 int ent_size; 749 uint32_t dw[4]; 750 uint64_t base, max_offset; 751 struct pci_ea_entry *eae; 752 753 if (cfg->ea.ea_location == 0) 754 return; 755 756 STAILQ_INIT(&cfg->ea.ea_entries); 757 758 /* Determine the number of entries */ 759 num_ent = REG(PCIR_EA_NUM_ENT, 2); 760 num_ent &= PCIM_EA_NUM_ENT_MASK; 761 762 /* Find the first entry to care of */ 763 ptr = PCIR_EA_FIRST_ENT; 764 765 /* Skip DWORD 2 for type 1 functions */ 766 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) 767 ptr += 4; 768 769 for (a = 0; a < num_ent; a++) { 770 eae = malloc(sizeof(*eae), M_DEVBUF, M_WAITOK | M_ZERO); 771 eae->eae_cfg_offset = cfg->ea.ea_location + ptr; 772 773 /* Read a number of dwords in the entry */ 774 val = REG(ptr, 4); 775 ptr += 4; 776 ent_size = (val & PCIM_EA_ES); 777 778 for (b = 0; b < ent_size; b++) { 779 dw[b] = REG(ptr, 4); 780 ptr += 4; 781 } 782 783 eae->eae_flags = val; 784 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 785 786 base = dw[0] & PCIM_EA_FIELD_MASK; 787 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 788 b = 2; 789 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 790 base |= (uint64_t)dw[b] << 32UL; 791 b++; 792 } 793 if (((dw[1] & PCIM_EA_IS_64) != 0) 794 && (b < ent_size)) { 795 max_offset |= (uint64_t)dw[b] << 32UL; 796 b++; 797 } 798 799 eae->eae_base = base; 800 eae->eae_max_offset = max_offset; 801 802 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link); 803 804 if (bootverbose) { 805 printf("PCI(EA) dev %04x:%04x, bei %d, flags #%x, base #%jx, max_offset #%jx\n", 806 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags, 807 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset); 808 } 809 } 810 } 811 #undef REG 812 813 static void 814 pci_read_cap(device_t pcib, pcicfgregs *cfg) 815 { 816 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 817 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 818 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 819 uint64_t addr; 820 #endif 821 uint32_t val; 822 int ptr, nextptr, ptrptr; 823 824 switch (cfg->hdrtype & PCIM_HDRTYPE) { 825 case PCIM_HDRTYPE_NORMAL: 826 case PCIM_HDRTYPE_BRIDGE: 827 ptrptr = PCIR_CAP_PTR; 828 break; 829 case PCIM_HDRTYPE_CARDBUS: 830 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 831 break; 832 default: 833 return; /* no extended capabilities support */ 834 } 835 nextptr = REG(ptrptr, 1); /* sanity check? */ 836 837 /* 838 * Read capability entries. 839 */ 840 while (nextptr != 0) { 841 /* Sanity check */ 842 if (nextptr > 255) { 843 printf("illegal PCI extended capability offset %d\n", 844 nextptr); 845 return; 846 } 847 /* Find the next entry */ 848 ptr = nextptr; 849 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 850 851 /* Process this entry */ 852 switch (REG(ptr + PCICAP_ID, 1)) { 853 case PCIY_PMG: /* PCI power management */ 854 if (cfg->pp.pp_cap == 0) { 855 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 856 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 857 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE; 858 if ((nextptr - ptr) > PCIR_POWER_DATA) 859 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 860 } 861 break; 862 case PCIY_HT: /* HyperTransport */ 863 /* Determine HT-specific capability type. */ 864 val = REG(ptr + PCIR_HT_COMMAND, 2); 865 866 if ((val & 0xe000) == PCIM_HTCAP_SLAVE) 867 cfg->ht.ht_slave = ptr; 868 869 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 870 switch (val & PCIM_HTCMD_CAP_MASK) { 871 case PCIM_HTCAP_MSI_MAPPING: 872 if (!(val & PCIM_HTCMD_MSI_FIXED)) { 873 /* Sanity check the mapping window. */ 874 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 875 4); 876 addr <<= 32; 877 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 878 4); 879 if (addr != MSI_INTEL_ADDR_BASE) 880 device_printf(pcib, 881 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", 882 cfg->domain, cfg->bus, 883 cfg->slot, cfg->func, 884 (long long)addr); 885 } else 886 addr = MSI_INTEL_ADDR_BASE; 887 888 cfg->ht.ht_msimap = ptr; 889 cfg->ht.ht_msictrl = val; 890 cfg->ht.ht_msiaddr = addr; 891 break; 892 } 893 #endif 894 break; 895 case PCIY_MSI: /* PCI MSI */ 896 cfg->msi.msi_location = ptr; 897 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 898 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 899 PCIM_MSICTRL_MMC_MASK)>>1); 900 break; 901 case PCIY_MSIX: /* PCI MSI-X */ 902 cfg->msix.msix_location = ptr; 903 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 904 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl & 905 PCIM_MSIXCTRL_TABLE_SIZE) + 1; 906 val = REG(ptr + PCIR_MSIX_TABLE, 4); 907 cfg->msix.msix_table_bar = PCIR_BAR(val & 908 PCIM_MSIX_BIR_MASK); 909 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 910 val = REG(ptr + PCIR_MSIX_PBA, 4); 911 cfg->msix.msix_pba_bar = PCIR_BAR(val & 912 PCIM_MSIX_BIR_MASK); 913 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 914 break; 915 case PCIY_VPD: /* PCI Vital Product Data */ 916 cfg->vpd.vpd_reg = ptr; 917 break; 918 case PCIY_SUBVENDOR: 919 /* Should always be true. */ 920 if ((cfg->hdrtype & PCIM_HDRTYPE) == 921 PCIM_HDRTYPE_BRIDGE) { 922 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4); 923 cfg->subvendor = val & 0xffff; 924 cfg->subdevice = val >> 16; 925 } 926 break; 927 case PCIY_PCIX: /* PCI-X */ 928 /* 929 * Assume we have a PCI-X chipset if we have 930 * at least one PCI-PCI bridge with a PCI-X 931 * capability. Note that some systems with 932 * PCI-express or HT chipsets might match on 933 * this check as well. 934 */ 935 if ((cfg->hdrtype & PCIM_HDRTYPE) == 936 PCIM_HDRTYPE_BRIDGE) 937 pcix_chipset = 1; 938 cfg->pcix.pcix_location = ptr; 939 break; 940 case PCIY_EXPRESS: /* PCI-express */ 941 /* 942 * Assume we have a PCI-express chipset if we have 943 * at least one PCI-express device. 944 */ 945 pcie_chipset = 1; 946 cfg->pcie.pcie_location = ptr; 947 val = REG(ptr + PCIER_FLAGS, 2); 948 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; 949 break; 950 case PCIY_EA: /* Enhanced Allocation */ 951 cfg->ea.ea_location = ptr; 952 pci_ea_fill_info(pcib, cfg); 953 break; 954 default: 955 break; 956 } 957 } 958 959 #if defined(__powerpc__) 960 /* 961 * Enable the MSI mapping window for all HyperTransport 962 * slaves. PCI-PCI bridges have their windows enabled via 963 * PCIB_MAP_MSI(). 964 */ 965 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && 966 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { 967 device_printf(pcib, 968 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n", 969 cfg->domain, cfg->bus, cfg->slot, cfg->func); 970 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 971 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, 972 2); 973 } 974 #endif 975 /* REG and WREG use carry through to next functions */ 976 } 977 978 /* 979 * PCI Vital Product Data 980 */ 981 982 #define PCI_VPD_TIMEOUT 1000000 983 984 static int 985 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data) 986 { 987 int count = PCI_VPD_TIMEOUT; 988 989 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 990 991 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); 992 993 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { 994 if (--count < 0) 995 return (ENXIO); 996 DELAY(1); /* limit looping */ 997 } 998 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); 999 1000 return (0); 1001 } 1002 1003 #if 0 1004 static int 1005 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 1006 { 1007 int count = PCI_VPD_TIMEOUT; 1008 1009 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1010 1011 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4); 1012 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2); 1013 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) { 1014 if (--count < 0) 1015 return (ENXIO); 1016 DELAY(1); /* limit looping */ 1017 } 1018 1019 return (0); 1020 } 1021 #endif 1022 1023 #undef PCI_VPD_TIMEOUT 1024 1025 struct vpd_readstate { 1026 device_t pcib; 1027 pcicfgregs *cfg; 1028 uint32_t val; 1029 int bytesinval; 1030 int off; 1031 uint8_t cksum; 1032 }; 1033 1034 static int 1035 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data) 1036 { 1037 uint32_t reg; 1038 uint8_t byte; 1039 1040 if (vrs->bytesinval == 0) { 1041 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) 1042 return (ENXIO); 1043 vrs->val = le32toh(reg); 1044 vrs->off += 4; 1045 byte = vrs->val & 0xff; 1046 vrs->bytesinval = 3; 1047 } else { 1048 vrs->val = vrs->val >> 8; 1049 byte = vrs->val & 0xff; 1050 vrs->bytesinval--; 1051 } 1052 1053 vrs->cksum += byte; 1054 *data = byte; 1055 return (0); 1056 } 1057 1058 static void 1059 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 1060 { 1061 struct vpd_readstate vrs; 1062 int state; 1063 int name; 1064 int remain; 1065 int i; 1066 int alloc, off; /* alloc/off for RO/W arrays */ 1067 int cksumvalid; 1068 int dflen; 1069 uint8_t byte; 1070 uint8_t byte2; 1071 1072 /* init vpd reader */ 1073 vrs.bytesinval = 0; 1074 vrs.off = 0; 1075 vrs.pcib = pcib; 1076 vrs.cfg = cfg; 1077 vrs.cksum = 0; 1078 1079 state = 0; 1080 name = remain = i = 0; /* shut up stupid gcc */ 1081 alloc = off = 0; /* shut up stupid gcc */ 1082 dflen = 0; /* shut up stupid gcc */ 1083 cksumvalid = -1; 1084 while (state >= 0) { 1085 if (vpd_nextbyte(&vrs, &byte)) { 1086 state = -2; 1087 break; 1088 } 1089 #if 0 1090 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \ 1091 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val, 1092 vrs.off, vrs.bytesinval, byte, state, remain, name, i); 1093 #endif 1094 switch (state) { 1095 case 0: /* item name */ 1096 if (byte & 0x80) { 1097 if (vpd_nextbyte(&vrs, &byte2)) { 1098 state = -2; 1099 break; 1100 } 1101 remain = byte2; 1102 if (vpd_nextbyte(&vrs, &byte2)) { 1103 state = -2; 1104 break; 1105 } 1106 remain |= byte2 << 8; 1107 name = byte & 0x7f; 1108 } else { 1109 remain = byte & 0x7; 1110 name = (byte >> 3) & 0xf; 1111 } 1112 if (vrs.off + remain - vrs.bytesinval > 0x8000) { 1113 pci_printf(cfg, 1114 "VPD data overflow, remain %#x\n", remain); 1115 state = -1; 1116 break; 1117 } 1118 switch (name) { 1119 case 0x2: /* String */ 1120 cfg->vpd.vpd_ident = malloc(remain + 1, 1121 M_DEVBUF, M_WAITOK); 1122 i = 0; 1123 state = 1; 1124 break; 1125 case 0xf: /* End */ 1126 state = -1; 1127 break; 1128 case 0x10: /* VPD-R */ 1129 alloc = 8; 1130 off = 0; 1131 cfg->vpd.vpd_ros = malloc(alloc * 1132 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF, 1133 M_WAITOK | M_ZERO); 1134 state = 2; 1135 break; 1136 case 0x11: /* VPD-W */ 1137 alloc = 8; 1138 off = 0; 1139 cfg->vpd.vpd_w = malloc(alloc * 1140 sizeof(*cfg->vpd.vpd_w), M_DEVBUF, 1141 M_WAITOK | M_ZERO); 1142 state = 5; 1143 break; 1144 default: /* Invalid data, abort */ 1145 state = -1; 1146 break; 1147 } 1148 break; 1149 1150 case 1: /* Identifier String */ 1151 cfg->vpd.vpd_ident[i++] = byte; 1152 remain--; 1153 if (remain == 0) { 1154 cfg->vpd.vpd_ident[i] = '\0'; 1155 state = 0; 1156 } 1157 break; 1158 1159 case 2: /* VPD-R Keyword Header */ 1160 if (off == alloc) { 1161 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1162 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros), 1163 M_DEVBUF, M_WAITOK | M_ZERO); 1164 } 1165 cfg->vpd.vpd_ros[off].keyword[0] = byte; 1166 if (vpd_nextbyte(&vrs, &byte2)) { 1167 state = -2; 1168 break; 1169 } 1170 cfg->vpd.vpd_ros[off].keyword[1] = byte2; 1171 if (vpd_nextbyte(&vrs, &byte2)) { 1172 state = -2; 1173 break; 1174 } 1175 cfg->vpd.vpd_ros[off].len = dflen = byte2; 1176 if (dflen == 0 && 1177 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV", 1178 2) == 0) { 1179 /* 1180 * if this happens, we can't trust the rest 1181 * of the VPD. 1182 */ 1183 pci_printf(cfg, "bad keyword length: %d\n", 1184 dflen); 1185 cksumvalid = 0; 1186 state = -1; 1187 break; 1188 } else if (dflen == 0) { 1189 cfg->vpd.vpd_ros[off].value = malloc(1 * 1190 sizeof(*cfg->vpd.vpd_ros[off].value), 1191 M_DEVBUF, M_WAITOK); 1192 cfg->vpd.vpd_ros[off].value[0] = '\x00'; 1193 } else 1194 cfg->vpd.vpd_ros[off].value = malloc( 1195 (dflen + 1) * 1196 sizeof(*cfg->vpd.vpd_ros[off].value), 1197 M_DEVBUF, M_WAITOK); 1198 remain -= 3; 1199 i = 0; 1200 /* keep in sync w/ state 3's transistions */ 1201 if (dflen == 0 && remain == 0) 1202 state = 0; 1203 else if (dflen == 0) 1204 state = 2; 1205 else 1206 state = 3; 1207 break; 1208 1209 case 3: /* VPD-R Keyword Value */ 1210 cfg->vpd.vpd_ros[off].value[i++] = byte; 1211 if (strncmp(cfg->vpd.vpd_ros[off].keyword, 1212 "RV", 2) == 0 && cksumvalid == -1) { 1213 if (vrs.cksum == 0) 1214 cksumvalid = 1; 1215 else { 1216 if (bootverbose) 1217 pci_printf(cfg, 1218 "bad VPD cksum, remain %hhu\n", 1219 vrs.cksum); 1220 cksumvalid = 0; 1221 state = -1; 1222 break; 1223 } 1224 } 1225 dflen--; 1226 remain--; 1227 /* keep in sync w/ state 2's transistions */ 1228 if (dflen == 0) 1229 cfg->vpd.vpd_ros[off++].value[i++] = '\0'; 1230 if (dflen == 0 && remain == 0) { 1231 cfg->vpd.vpd_rocnt = off; 1232 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1233 off * sizeof(*cfg->vpd.vpd_ros), 1234 M_DEVBUF, M_WAITOK | M_ZERO); 1235 state = 0; 1236 } else if (dflen == 0) 1237 state = 2; 1238 break; 1239 1240 case 4: 1241 remain--; 1242 if (remain == 0) 1243 state = 0; 1244 break; 1245 1246 case 5: /* VPD-W Keyword Header */ 1247 if (off == alloc) { 1248 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1249 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w), 1250 M_DEVBUF, M_WAITOK | M_ZERO); 1251 } 1252 cfg->vpd.vpd_w[off].keyword[0] = byte; 1253 if (vpd_nextbyte(&vrs, &byte2)) { 1254 state = -2; 1255 break; 1256 } 1257 cfg->vpd.vpd_w[off].keyword[1] = byte2; 1258 if (vpd_nextbyte(&vrs, &byte2)) { 1259 state = -2; 1260 break; 1261 } 1262 cfg->vpd.vpd_w[off].len = dflen = byte2; 1263 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval; 1264 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) * 1265 sizeof(*cfg->vpd.vpd_w[off].value), 1266 M_DEVBUF, M_WAITOK); 1267 remain -= 3; 1268 i = 0; 1269 /* keep in sync w/ state 6's transistions */ 1270 if (dflen == 0 && remain == 0) 1271 state = 0; 1272 else if (dflen == 0) 1273 state = 5; 1274 else 1275 state = 6; 1276 break; 1277 1278 case 6: /* VPD-W Keyword Value */ 1279 cfg->vpd.vpd_w[off].value[i++] = byte; 1280 dflen--; 1281 remain--; 1282 /* keep in sync w/ state 5's transistions */ 1283 if (dflen == 0) 1284 cfg->vpd.vpd_w[off++].value[i++] = '\0'; 1285 if (dflen == 0 && remain == 0) { 1286 cfg->vpd.vpd_wcnt = off; 1287 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1288 off * sizeof(*cfg->vpd.vpd_w), 1289 M_DEVBUF, M_WAITOK | M_ZERO); 1290 state = 0; 1291 } else if (dflen == 0) 1292 state = 5; 1293 break; 1294 1295 default: 1296 pci_printf(cfg, "invalid state: %d\n", state); 1297 state = -1; 1298 break; 1299 } 1300 } 1301 1302 if (cksumvalid == 0 || state < -1) { 1303 /* read-only data bad, clean up */ 1304 if (cfg->vpd.vpd_ros != NULL) { 1305 for (off = 0; cfg->vpd.vpd_ros[off].value; off++) 1306 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF); 1307 free(cfg->vpd.vpd_ros, M_DEVBUF); 1308 cfg->vpd.vpd_ros = NULL; 1309 } 1310 } 1311 if (state < -1) { 1312 /* I/O error, clean up */ 1313 pci_printf(cfg, "failed to read VPD data.\n"); 1314 if (cfg->vpd.vpd_ident != NULL) { 1315 free(cfg->vpd.vpd_ident, M_DEVBUF); 1316 cfg->vpd.vpd_ident = NULL; 1317 } 1318 if (cfg->vpd.vpd_w != NULL) { 1319 for (off = 0; cfg->vpd.vpd_w[off].value; off++) 1320 free(cfg->vpd.vpd_w[off].value, M_DEVBUF); 1321 free(cfg->vpd.vpd_w, M_DEVBUF); 1322 cfg->vpd.vpd_w = NULL; 1323 } 1324 } 1325 cfg->vpd.vpd_cached = 1; 1326 #undef REG 1327 #undef WREG 1328 } 1329 1330 int 1331 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 1332 { 1333 struct pci_devinfo *dinfo = device_get_ivars(child); 1334 pcicfgregs *cfg = &dinfo->cfg; 1335 1336 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1337 pci_read_vpd(device_get_parent(dev), cfg); 1338 1339 *identptr = cfg->vpd.vpd_ident; 1340 1341 if (*identptr == NULL) 1342 return (ENXIO); 1343 1344 return (0); 1345 } 1346 1347 int 1348 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 1349 const char **vptr) 1350 { 1351 struct pci_devinfo *dinfo = device_get_ivars(child); 1352 pcicfgregs *cfg = &dinfo->cfg; 1353 int i; 1354 1355 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1356 pci_read_vpd(device_get_parent(dev), cfg); 1357 1358 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 1359 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 1360 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { 1361 *vptr = cfg->vpd.vpd_ros[i].value; 1362 return (0); 1363 } 1364 1365 *vptr = NULL; 1366 return (ENXIO); 1367 } 1368 1369 struct pcicfg_vpd * 1370 pci_fetch_vpd_list(device_t dev) 1371 { 1372 struct pci_devinfo *dinfo = device_get_ivars(dev); 1373 pcicfgregs *cfg = &dinfo->cfg; 1374 1375 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1376 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg); 1377 return (&cfg->vpd); 1378 } 1379 1380 /* 1381 * Find the requested HyperTransport capability and return the offset 1382 * in configuration space via the pointer provided. The function 1383 * returns 0 on success and an error code otherwise. 1384 */ 1385 int 1386 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg) 1387 { 1388 int ptr, error; 1389 uint16_t val; 1390 1391 error = pci_find_cap(child, PCIY_HT, &ptr); 1392 if (error) 1393 return (error); 1394 1395 /* 1396 * Traverse the capabilities list checking each HT capability 1397 * to see if it matches the requested HT capability. 1398 */ 1399 for (;;) { 1400 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1401 if (capability == PCIM_HTCAP_SLAVE || 1402 capability == PCIM_HTCAP_HOST) 1403 val &= 0xe000; 1404 else 1405 val &= PCIM_HTCMD_CAP_MASK; 1406 if (val == capability) { 1407 if (capreg != NULL) 1408 *capreg = ptr; 1409 return (0); 1410 } 1411 1412 /* Skip to the next HT capability. */ 1413 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1414 break; 1415 } 1416 1417 return (ENOENT); 1418 } 1419 1420 /* 1421 * Find the next requested HyperTransport capability after start and return 1422 * the offset in configuration space via the pointer provided. The function 1423 * returns 0 on success and an error code otherwise. 1424 */ 1425 int 1426 pci_find_next_htcap_method(device_t dev, device_t child, int capability, 1427 int start, int *capreg) 1428 { 1429 int ptr; 1430 uint16_t val; 1431 1432 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == PCIY_HT, 1433 ("start capability is not HyperTransport capability")); 1434 ptr = start; 1435 1436 /* 1437 * Traverse the capabilities list checking each HT capability 1438 * to see if it matches the requested HT capability. 1439 */ 1440 for (;;) { 1441 /* Skip to the next HT capability. */ 1442 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1443 break; 1444 1445 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1446 if (capability == PCIM_HTCAP_SLAVE || 1447 capability == PCIM_HTCAP_HOST) 1448 val &= 0xe000; 1449 else 1450 val &= PCIM_HTCMD_CAP_MASK; 1451 if (val == capability) { 1452 if (capreg != NULL) 1453 *capreg = ptr; 1454 return (0); 1455 } 1456 } 1457 1458 return (ENOENT); 1459 } 1460 1461 /* 1462 * Find the requested capability and return the offset in 1463 * configuration space via the pointer provided. The function returns 1464 * 0 on success and an error code otherwise. 1465 */ 1466 int 1467 pci_find_cap_method(device_t dev, device_t child, int capability, 1468 int *capreg) 1469 { 1470 struct pci_devinfo *dinfo = device_get_ivars(child); 1471 pcicfgregs *cfg = &dinfo->cfg; 1472 uint32_t status; 1473 uint8_t ptr; 1474 1475 /* 1476 * Check the CAP_LIST bit of the PCI status register first. 1477 */ 1478 status = pci_read_config(child, PCIR_STATUS, 2); 1479 if (!(status & PCIM_STATUS_CAPPRESENT)) 1480 return (ENXIO); 1481 1482 /* 1483 * Determine the start pointer of the capabilities list. 1484 */ 1485 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1486 case PCIM_HDRTYPE_NORMAL: 1487 case PCIM_HDRTYPE_BRIDGE: 1488 ptr = PCIR_CAP_PTR; 1489 break; 1490 case PCIM_HDRTYPE_CARDBUS: 1491 ptr = PCIR_CAP_PTR_2; 1492 break; 1493 default: 1494 /* XXX: panic? */ 1495 return (ENXIO); /* no extended capabilities support */ 1496 } 1497 ptr = pci_read_config(child, ptr, 1); 1498 1499 /* 1500 * Traverse the capabilities list. 1501 */ 1502 while (ptr != 0) { 1503 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1504 if (capreg != NULL) 1505 *capreg = ptr; 1506 return (0); 1507 } 1508 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1509 } 1510 1511 return (ENOENT); 1512 } 1513 1514 /* 1515 * Find the next requested capability after start and return the offset in 1516 * configuration space via the pointer provided. The function returns 1517 * 0 on success and an error code otherwise. 1518 */ 1519 int 1520 pci_find_next_cap_method(device_t dev, device_t child, int capability, 1521 int start, int *capreg) 1522 { 1523 uint8_t ptr; 1524 1525 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == capability, 1526 ("start capability is not expected capability")); 1527 1528 ptr = pci_read_config(child, start + PCICAP_NEXTPTR, 1); 1529 while (ptr != 0) { 1530 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1531 if (capreg != NULL) 1532 *capreg = ptr; 1533 return (0); 1534 } 1535 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1536 } 1537 1538 return (ENOENT); 1539 } 1540 1541 /* 1542 * Find the requested extended capability and return the offset in 1543 * configuration space via the pointer provided. The function returns 1544 * 0 on success and an error code otherwise. 1545 */ 1546 int 1547 pci_find_extcap_method(device_t dev, device_t child, int capability, 1548 int *capreg) 1549 { 1550 struct pci_devinfo *dinfo = device_get_ivars(child); 1551 pcicfgregs *cfg = &dinfo->cfg; 1552 uint32_t ecap; 1553 uint16_t ptr; 1554 1555 /* Only supported for PCI-express devices. */ 1556 if (cfg->pcie.pcie_location == 0) 1557 return (ENXIO); 1558 1559 ptr = PCIR_EXTCAP; 1560 ecap = pci_read_config(child, ptr, 4); 1561 if (ecap == 0xffffffff || ecap == 0) 1562 return (ENOENT); 1563 for (;;) { 1564 if (PCI_EXTCAP_ID(ecap) == capability) { 1565 if (capreg != NULL) 1566 *capreg = ptr; 1567 return (0); 1568 } 1569 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1570 if (ptr == 0) 1571 break; 1572 ecap = pci_read_config(child, ptr, 4); 1573 } 1574 1575 return (ENOENT); 1576 } 1577 1578 /* 1579 * Find the next requested extended capability after start and return the 1580 * offset in configuration space via the pointer provided. The function 1581 * returns 0 on success and an error code otherwise. 1582 */ 1583 int 1584 pci_find_next_extcap_method(device_t dev, device_t child, int capability, 1585 int start, int *capreg) 1586 { 1587 struct pci_devinfo *dinfo = device_get_ivars(child); 1588 pcicfgregs *cfg = &dinfo->cfg; 1589 uint32_t ecap; 1590 uint16_t ptr; 1591 1592 /* Only supported for PCI-express devices. */ 1593 if (cfg->pcie.pcie_location == 0) 1594 return (ENXIO); 1595 1596 ecap = pci_read_config(child, start, 4); 1597 KASSERT(PCI_EXTCAP_ID(ecap) == capability, 1598 ("start extended capability is not expected capability")); 1599 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1600 while (ptr != 0) { 1601 ecap = pci_read_config(child, ptr, 4); 1602 if (PCI_EXTCAP_ID(ecap) == capability) { 1603 if (capreg != NULL) 1604 *capreg = ptr; 1605 return (0); 1606 } 1607 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1608 } 1609 1610 return (ENOENT); 1611 } 1612 1613 /* 1614 * Support for MSI-X message interrupts. 1615 */ 1616 static void 1617 pci_write_msix_entry(device_t dev, u_int index, uint64_t address, uint32_t data) 1618 { 1619 struct pci_devinfo *dinfo = device_get_ivars(dev); 1620 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1621 uint32_t offset; 1622 1623 KASSERT(msix->msix_table_len > index, ("bogus index")); 1624 offset = msix->msix_table_offset + index * 16; 1625 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); 1626 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); 1627 bus_write_4(msix->msix_table_res, offset + 8, data); 1628 } 1629 1630 void 1631 pci_enable_msix_method(device_t dev, device_t child, u_int index, 1632 uint64_t address, uint32_t data) 1633 { 1634 1635 if (pci_msix_rewrite_table) { 1636 struct pci_devinfo *dinfo = device_get_ivars(child); 1637 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1638 1639 /* 1640 * Some VM hosts require MSIX to be disabled in the 1641 * control register before updating the MSIX table 1642 * entries are allowed. It is not enough to only 1643 * disable MSIX while updating a single entry. MSIX 1644 * must be disabled while updating all entries in the 1645 * table. 1646 */ 1647 pci_write_config(child, 1648 msix->msix_location + PCIR_MSIX_CTRL, 1649 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2); 1650 pci_resume_msix(child); 1651 } else 1652 pci_write_msix_entry(child, index, address, data); 1653 1654 /* Enable MSI -> HT mapping. */ 1655 pci_ht_map_msi(child, address); 1656 } 1657 1658 void 1659 pci_mask_msix(device_t dev, u_int index) 1660 { 1661 struct pci_devinfo *dinfo = device_get_ivars(dev); 1662 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1663 uint32_t offset, val; 1664 1665 KASSERT(msix->msix_msgnum > index, ("bogus index")); 1666 offset = msix->msix_table_offset + index * 16 + 12; 1667 val = bus_read_4(msix->msix_table_res, offset); 1668 val |= PCIM_MSIX_VCTRL_MASK; 1669 1670 /* 1671 * Some devices (e.g. Samsung PM961) do not support reads of this 1672 * register, so always write the new value. 1673 */ 1674 bus_write_4(msix->msix_table_res, offset, val); 1675 } 1676 1677 void 1678 pci_unmask_msix(device_t dev, u_int index) 1679 { 1680 struct pci_devinfo *dinfo = device_get_ivars(dev); 1681 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1682 uint32_t offset, val; 1683 1684 KASSERT(msix->msix_table_len > index, ("bogus index")); 1685 offset = msix->msix_table_offset + index * 16 + 12; 1686 val = bus_read_4(msix->msix_table_res, offset); 1687 val &= ~PCIM_MSIX_VCTRL_MASK; 1688 1689 /* 1690 * Some devices (e.g. Samsung PM961) do not support reads of this 1691 * register, so always write the new value. 1692 */ 1693 bus_write_4(msix->msix_table_res, offset, val); 1694 } 1695 1696 int 1697 pci_pending_msix(device_t dev, u_int index) 1698 { 1699 struct pci_devinfo *dinfo = device_get_ivars(dev); 1700 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1701 uint32_t offset, bit; 1702 1703 KASSERT(msix->msix_table_len > index, ("bogus index")); 1704 offset = msix->msix_pba_offset + (index / 32) * 4; 1705 bit = 1 << index % 32; 1706 return (bus_read_4(msix->msix_pba_res, offset) & bit); 1707 } 1708 1709 /* 1710 * Restore MSI-X registers and table during resume. If MSI-X is 1711 * enabled then walk the virtual table to restore the actual MSI-X 1712 * table. 1713 */ 1714 static void 1715 pci_resume_msix(device_t dev) 1716 { 1717 struct pci_devinfo *dinfo = device_get_ivars(dev); 1718 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1719 struct msix_table_entry *mte; 1720 struct msix_vector *mv; 1721 int i; 1722 1723 if (msix->msix_alloc > 0) { 1724 /* First, mask all vectors. */ 1725 for (i = 0; i < msix->msix_msgnum; i++) 1726 pci_mask_msix(dev, i); 1727 1728 /* Second, program any messages with at least one handler. */ 1729 for (i = 0; i < msix->msix_table_len; i++) { 1730 mte = &msix->msix_table[i]; 1731 if (mte->mte_vector == 0 || mte->mte_handlers == 0) 1732 continue; 1733 mv = &msix->msix_vectors[mte->mte_vector - 1]; 1734 pci_write_msix_entry(dev, i, mv->mv_address, 1735 mv->mv_data); 1736 pci_unmask_msix(dev, i); 1737 } 1738 } 1739 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, 1740 msix->msix_ctrl, 2); 1741 } 1742 1743 /* 1744 * Attempt to allocate *count MSI-X messages. The actual number allocated is 1745 * returned in *count. After this function returns, each message will be 1746 * available to the driver as SYS_RES_IRQ resources starting at rid 1. 1747 */ 1748 int 1749 pci_alloc_msix_method(device_t dev, device_t child, int *count) 1750 { 1751 struct pci_devinfo *dinfo = device_get_ivars(child); 1752 pcicfgregs *cfg = &dinfo->cfg; 1753 struct resource_list_entry *rle; 1754 int actual, error, i, irq, max; 1755 1756 /* Don't let count == 0 get us into trouble. */ 1757 if (*count == 0) 1758 return (EINVAL); 1759 1760 /* If rid 0 is allocated, then fail. */ 1761 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1762 if (rle != NULL && rle->res != NULL) 1763 return (ENXIO); 1764 1765 /* Already have allocated messages? */ 1766 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1767 return (ENXIO); 1768 1769 /* If MSI-X is blacklisted for this system, fail. */ 1770 if (pci_msix_blacklisted()) 1771 return (ENXIO); 1772 1773 /* MSI-X capability present? */ 1774 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1775 return (ENODEV); 1776 1777 /* Make sure the appropriate BARs are mapped. */ 1778 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1779 cfg->msix.msix_table_bar); 1780 if (rle == NULL || rle->res == NULL || 1781 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1782 return (ENXIO); 1783 cfg->msix.msix_table_res = rle->res; 1784 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1785 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1786 cfg->msix.msix_pba_bar); 1787 if (rle == NULL || rle->res == NULL || 1788 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1789 return (ENXIO); 1790 } 1791 cfg->msix.msix_pba_res = rle->res; 1792 1793 if (bootverbose) 1794 device_printf(child, 1795 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1796 *count, cfg->msix.msix_msgnum); 1797 max = min(*count, cfg->msix.msix_msgnum); 1798 for (i = 0; i < max; i++) { 1799 /* Allocate a message. */ 1800 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq); 1801 if (error) { 1802 if (i == 0) 1803 return (error); 1804 break; 1805 } 1806 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1807 irq, 1); 1808 } 1809 actual = i; 1810 1811 if (bootverbose) { 1812 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1813 if (actual == 1) 1814 device_printf(child, "using IRQ %ju for MSI-X\n", 1815 rle->start); 1816 else { 1817 int run; 1818 1819 /* 1820 * Be fancy and try to print contiguous runs of 1821 * IRQ values as ranges. 'irq' is the previous IRQ. 1822 * 'run' is true if we are in a range. 1823 */ 1824 device_printf(child, "using IRQs %ju", rle->start); 1825 irq = rle->start; 1826 run = 0; 1827 for (i = 1; i < actual; i++) { 1828 rle = resource_list_find(&dinfo->resources, 1829 SYS_RES_IRQ, i + 1); 1830 1831 /* Still in a run? */ 1832 if (rle->start == irq + 1) { 1833 run = 1; 1834 irq++; 1835 continue; 1836 } 1837 1838 /* Finish previous range. */ 1839 if (run) { 1840 printf("-%d", irq); 1841 run = 0; 1842 } 1843 1844 /* Start new range. */ 1845 printf(",%ju", rle->start); 1846 irq = rle->start; 1847 } 1848 1849 /* Unfinished range? */ 1850 if (run) 1851 printf("-%d", irq); 1852 printf(" for MSI-X\n"); 1853 } 1854 } 1855 1856 /* Mask all vectors. */ 1857 for (i = 0; i < cfg->msix.msix_msgnum; i++) 1858 pci_mask_msix(child, i); 1859 1860 /* Allocate and initialize vector data and virtual table. */ 1861 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual, 1862 M_DEVBUF, M_WAITOK | M_ZERO); 1863 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual, 1864 M_DEVBUF, M_WAITOK | M_ZERO); 1865 for (i = 0; i < actual; i++) { 1866 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1867 cfg->msix.msix_vectors[i].mv_irq = rle->start; 1868 cfg->msix.msix_table[i].mte_vector = i + 1; 1869 } 1870 1871 /* Update control register to enable MSI-X. */ 1872 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1873 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1874 cfg->msix.msix_ctrl, 2); 1875 1876 /* Update counts of alloc'd messages. */ 1877 cfg->msix.msix_alloc = actual; 1878 cfg->msix.msix_table_len = actual; 1879 *count = actual; 1880 return (0); 1881 } 1882 1883 /* 1884 * By default, pci_alloc_msix() will assign the allocated IRQ 1885 * resources consecutively to the first N messages in the MSI-X table. 1886 * However, device drivers may want to use different layouts if they 1887 * either receive fewer messages than they asked for, or they wish to 1888 * populate the MSI-X table sparsely. This method allows the driver 1889 * to specify what layout it wants. It must be called after a 1890 * successful pci_alloc_msix() but before any of the associated 1891 * SYS_RES_IRQ resources are allocated via bus_alloc_resource(). 1892 * 1893 * The 'vectors' array contains 'count' message vectors. The array 1894 * maps directly to the MSI-X table in that index 0 in the array 1895 * specifies the vector for the first message in the MSI-X table, etc. 1896 * The vector value in each array index can either be 0 to indicate 1897 * that no vector should be assigned to a message slot, or it can be a 1898 * number from 1 to N (where N is the count returned from a 1899 * succcessful call to pci_alloc_msix()) to indicate which message 1900 * vector (IRQ) to be used for the corresponding message. 1901 * 1902 * On successful return, each message with a non-zero vector will have 1903 * an associated SYS_RES_IRQ whose rid is equal to the array index + 1904 * 1. Additionally, if any of the IRQs allocated via the previous 1905 * call to pci_alloc_msix() are not used in the mapping, those IRQs 1906 * will be freed back to the system automatically. 1907 * 1908 * For example, suppose a driver has a MSI-X table with 6 messages and 1909 * asks for 6 messages, but pci_alloc_msix() only returns a count of 1910 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and 1911 * C. After the call to pci_alloc_msix(), the device will be setup to 1912 * have an MSI-X table of ABC--- (where - means no vector assigned). 1913 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 }, 1914 * then the MSI-X table will look like A-AB-B, and the 'C' vector will 1915 * be freed back to the system. This device will also have valid 1916 * SYS_RES_IRQ rids of 1, 3, 4, and 6. 1917 * 1918 * In any case, the SYS_RES_IRQ rid X will always map to the message 1919 * at MSI-X table index X - 1 and will only be valid if a vector is 1920 * assigned to that table entry. 1921 */ 1922 int 1923 pci_remap_msix_method(device_t dev, device_t child, int count, 1924 const u_int *vectors) 1925 { 1926 struct pci_devinfo *dinfo = device_get_ivars(child); 1927 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1928 struct resource_list_entry *rle; 1929 int i, irq, j, *used; 1930 1931 /* 1932 * Have to have at least one message in the table but the 1933 * table can't be bigger than the actual MSI-X table in the 1934 * device. 1935 */ 1936 if (count == 0 || count > msix->msix_msgnum) 1937 return (EINVAL); 1938 1939 /* Sanity check the vectors. */ 1940 for (i = 0; i < count; i++) 1941 if (vectors[i] > msix->msix_alloc) 1942 return (EINVAL); 1943 1944 /* 1945 * Make sure there aren't any holes in the vectors to be used. 1946 * It's a big pain to support it, and it doesn't really make 1947 * sense anyway. Also, at least one vector must be used. 1948 */ 1949 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK | 1950 M_ZERO); 1951 for (i = 0; i < count; i++) 1952 if (vectors[i] != 0) 1953 used[vectors[i] - 1] = 1; 1954 for (i = 0; i < msix->msix_alloc - 1; i++) 1955 if (used[i] == 0 && used[i + 1] == 1) { 1956 free(used, M_DEVBUF); 1957 return (EINVAL); 1958 } 1959 if (used[0] != 1) { 1960 free(used, M_DEVBUF); 1961 return (EINVAL); 1962 } 1963 1964 /* Make sure none of the resources are allocated. */ 1965 for (i = 0; i < msix->msix_table_len; i++) { 1966 if (msix->msix_table[i].mte_vector == 0) 1967 continue; 1968 if (msix->msix_table[i].mte_handlers > 0) { 1969 free(used, M_DEVBUF); 1970 return (EBUSY); 1971 } 1972 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1973 KASSERT(rle != NULL, ("missing resource")); 1974 if (rle->res != NULL) { 1975 free(used, M_DEVBUF); 1976 return (EBUSY); 1977 } 1978 } 1979 1980 /* Free the existing resource list entries. */ 1981 for (i = 0; i < msix->msix_table_len; i++) { 1982 if (msix->msix_table[i].mte_vector == 0) 1983 continue; 1984 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1985 } 1986 1987 /* 1988 * Build the new virtual table keeping track of which vectors are 1989 * used. 1990 */ 1991 free(msix->msix_table, M_DEVBUF); 1992 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count, 1993 M_DEVBUF, M_WAITOK | M_ZERO); 1994 for (i = 0; i < count; i++) 1995 msix->msix_table[i].mte_vector = vectors[i]; 1996 msix->msix_table_len = count; 1997 1998 /* Free any unused IRQs and resize the vectors array if necessary. */ 1999 j = msix->msix_alloc - 1; 2000 if (used[j] == 0) { 2001 struct msix_vector *vec; 2002 2003 while (used[j] == 0) { 2004 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2005 msix->msix_vectors[j].mv_irq); 2006 j--; 2007 } 2008 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF, 2009 M_WAITOK); 2010 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * 2011 (j + 1)); 2012 free(msix->msix_vectors, M_DEVBUF); 2013 msix->msix_vectors = vec; 2014 msix->msix_alloc = j + 1; 2015 } 2016 free(used, M_DEVBUF); 2017 2018 /* Map the IRQs onto the rids. */ 2019 for (i = 0; i < count; i++) { 2020 if (vectors[i] == 0) 2021 continue; 2022 irq = msix->msix_vectors[vectors[i] - 1].mv_irq; 2023 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 2024 irq, 1); 2025 } 2026 2027 if (bootverbose) { 2028 device_printf(child, "Remapped MSI-X IRQs as: "); 2029 for (i = 0; i < count; i++) { 2030 if (i != 0) 2031 printf(", "); 2032 if (vectors[i] == 0) 2033 printf("---"); 2034 else 2035 printf("%d", 2036 msix->msix_vectors[vectors[i] - 1].mv_irq); 2037 } 2038 printf("\n"); 2039 } 2040 2041 return (0); 2042 } 2043 2044 static int 2045 pci_release_msix(device_t dev, device_t child) 2046 { 2047 struct pci_devinfo *dinfo = device_get_ivars(child); 2048 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2049 struct resource_list_entry *rle; 2050 int i; 2051 2052 /* Do we have any messages to release? */ 2053 if (msix->msix_alloc == 0) 2054 return (ENODEV); 2055 2056 /* Make sure none of the resources are allocated. */ 2057 for (i = 0; i < msix->msix_table_len; i++) { 2058 if (msix->msix_table[i].mte_vector == 0) 2059 continue; 2060 if (msix->msix_table[i].mte_handlers > 0) 2061 return (EBUSY); 2062 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2063 KASSERT(rle != NULL, ("missing resource")); 2064 if (rle->res != NULL) 2065 return (EBUSY); 2066 } 2067 2068 /* Update control register to disable MSI-X. */ 2069 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 2070 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, 2071 msix->msix_ctrl, 2); 2072 2073 /* Free the resource list entries. */ 2074 for (i = 0; i < msix->msix_table_len; i++) { 2075 if (msix->msix_table[i].mte_vector == 0) 2076 continue; 2077 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2078 } 2079 free(msix->msix_table, M_DEVBUF); 2080 msix->msix_table_len = 0; 2081 2082 /* Release the IRQs. */ 2083 for (i = 0; i < msix->msix_alloc; i++) 2084 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2085 msix->msix_vectors[i].mv_irq); 2086 free(msix->msix_vectors, M_DEVBUF); 2087 msix->msix_alloc = 0; 2088 return (0); 2089 } 2090 2091 /* 2092 * Return the max supported MSI-X messages this device supports. 2093 * Basically, assuming the MD code can alloc messages, this function 2094 * should return the maximum value that pci_alloc_msix() can return. 2095 * Thus, it is subject to the tunables, etc. 2096 */ 2097 int 2098 pci_msix_count_method(device_t dev, device_t child) 2099 { 2100 struct pci_devinfo *dinfo = device_get_ivars(child); 2101 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2102 2103 if (pci_do_msix && msix->msix_location != 0) 2104 return (msix->msix_msgnum); 2105 return (0); 2106 } 2107 2108 int 2109 pci_msix_pba_bar_method(device_t dev, device_t child) 2110 { 2111 struct pci_devinfo *dinfo = device_get_ivars(child); 2112 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2113 2114 if (pci_do_msix && msix->msix_location != 0) 2115 return (msix->msix_pba_bar); 2116 return (-1); 2117 } 2118 2119 int 2120 pci_msix_table_bar_method(device_t dev, device_t child) 2121 { 2122 struct pci_devinfo *dinfo = device_get_ivars(child); 2123 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2124 2125 if (pci_do_msix && msix->msix_location != 0) 2126 return (msix->msix_table_bar); 2127 return (-1); 2128 } 2129 2130 /* 2131 * HyperTransport MSI mapping control 2132 */ 2133 void 2134 pci_ht_map_msi(device_t dev, uint64_t addr) 2135 { 2136 struct pci_devinfo *dinfo = device_get_ivars(dev); 2137 struct pcicfg_ht *ht = &dinfo->cfg.ht; 2138 2139 if (!ht->ht_msimap) 2140 return; 2141 2142 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && 2143 ht->ht_msiaddr >> 20 == addr >> 20) { 2144 /* Enable MSI -> HT mapping. */ 2145 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 2146 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2147 ht->ht_msictrl, 2); 2148 } 2149 2150 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { 2151 /* Disable MSI -> HT mapping. */ 2152 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; 2153 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2154 ht->ht_msictrl, 2); 2155 } 2156 } 2157 2158 int 2159 pci_get_max_payload(device_t dev) 2160 { 2161 struct pci_devinfo *dinfo = device_get_ivars(dev); 2162 int cap; 2163 uint16_t val; 2164 2165 cap = dinfo->cfg.pcie.pcie_location; 2166 if (cap == 0) 2167 return (0); 2168 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2169 val &= PCIEM_CTL_MAX_PAYLOAD; 2170 val >>= 5; 2171 return (1 << (val + 7)); 2172 } 2173 2174 int 2175 pci_get_max_read_req(device_t dev) 2176 { 2177 struct pci_devinfo *dinfo = device_get_ivars(dev); 2178 int cap; 2179 uint16_t val; 2180 2181 cap = dinfo->cfg.pcie.pcie_location; 2182 if (cap == 0) 2183 return (0); 2184 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2185 val &= PCIEM_CTL_MAX_READ_REQUEST; 2186 val >>= 12; 2187 return (1 << (val + 7)); 2188 } 2189 2190 int 2191 pci_set_max_read_req(device_t dev, int size) 2192 { 2193 struct pci_devinfo *dinfo = device_get_ivars(dev); 2194 int cap; 2195 uint16_t val; 2196 2197 cap = dinfo->cfg.pcie.pcie_location; 2198 if (cap == 0) 2199 return (0); 2200 if (size < 128) 2201 size = 128; 2202 if (size > 4096) 2203 size = 4096; 2204 size = (1 << (fls(size) - 1)); 2205 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2206 val &= ~PCIEM_CTL_MAX_READ_REQUEST; 2207 val |= (fls(size) - 8) << 12; 2208 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2); 2209 return (size); 2210 } 2211 2212 uint32_t 2213 pcie_read_config(device_t dev, int reg, int width) 2214 { 2215 struct pci_devinfo *dinfo = device_get_ivars(dev); 2216 int cap; 2217 2218 cap = dinfo->cfg.pcie.pcie_location; 2219 if (cap == 0) { 2220 if (width == 2) 2221 return (0xffff); 2222 return (0xffffffff); 2223 } 2224 2225 return (pci_read_config(dev, cap + reg, width)); 2226 } 2227 2228 void 2229 pcie_write_config(device_t dev, int reg, uint32_t value, int width) 2230 { 2231 struct pci_devinfo *dinfo = device_get_ivars(dev); 2232 int cap; 2233 2234 cap = dinfo->cfg.pcie.pcie_location; 2235 if (cap == 0) 2236 return; 2237 pci_write_config(dev, cap + reg, value, width); 2238 } 2239 2240 /* 2241 * Adjusts a PCI-e capability register by clearing the bits in mask 2242 * and setting the bits in (value & mask). Bits not set in mask are 2243 * not adjusted. 2244 * 2245 * Returns the old value on success or all ones on failure. 2246 */ 2247 uint32_t 2248 pcie_adjust_config(device_t dev, int reg, uint32_t mask, uint32_t value, 2249 int width) 2250 { 2251 struct pci_devinfo *dinfo = device_get_ivars(dev); 2252 uint32_t old, new; 2253 int cap; 2254 2255 cap = dinfo->cfg.pcie.pcie_location; 2256 if (cap == 0) { 2257 if (width == 2) 2258 return (0xffff); 2259 return (0xffffffff); 2260 } 2261 2262 old = pci_read_config(dev, cap + reg, width); 2263 new = old & ~mask; 2264 new |= (value & mask); 2265 pci_write_config(dev, cap + reg, new, width); 2266 return (old); 2267 } 2268 2269 /* 2270 * Support for MSI message signalled interrupts. 2271 */ 2272 void 2273 pci_enable_msi_method(device_t dev, device_t child, uint64_t address, 2274 uint16_t data) 2275 { 2276 struct pci_devinfo *dinfo = device_get_ivars(child); 2277 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2278 2279 /* Write data and address values. */ 2280 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, 2281 address & 0xffffffff, 4); 2282 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2283 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, 2284 address >> 32, 4); 2285 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, 2286 data, 2); 2287 } else 2288 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, 2289 2); 2290 2291 /* Enable MSI in the control register. */ 2292 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 2293 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2294 msi->msi_ctrl, 2); 2295 2296 /* Enable MSI -> HT mapping. */ 2297 pci_ht_map_msi(child, address); 2298 } 2299 2300 void 2301 pci_disable_msi_method(device_t dev, device_t child) 2302 { 2303 struct pci_devinfo *dinfo = device_get_ivars(child); 2304 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2305 2306 /* Disable MSI -> HT mapping. */ 2307 pci_ht_map_msi(child, 0); 2308 2309 /* Disable MSI in the control register. */ 2310 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; 2311 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2312 msi->msi_ctrl, 2); 2313 } 2314 2315 /* 2316 * Restore MSI registers during resume. If MSI is enabled then 2317 * restore the data and address registers in addition to the control 2318 * register. 2319 */ 2320 static void 2321 pci_resume_msi(device_t dev) 2322 { 2323 struct pci_devinfo *dinfo = device_get_ivars(dev); 2324 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2325 uint64_t address; 2326 uint16_t data; 2327 2328 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 2329 address = msi->msi_addr; 2330 data = msi->msi_data; 2331 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 2332 address & 0xffffffff, 4); 2333 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2334 pci_write_config(dev, msi->msi_location + 2335 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 2336 pci_write_config(dev, msi->msi_location + 2337 PCIR_MSI_DATA_64BIT, data, 2); 2338 } else 2339 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, 2340 data, 2); 2341 } 2342 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 2343 2); 2344 } 2345 2346 static int 2347 pci_remap_intr_method(device_t bus, device_t dev, u_int irq) 2348 { 2349 struct pci_devinfo *dinfo = device_get_ivars(dev); 2350 pcicfgregs *cfg = &dinfo->cfg; 2351 struct resource_list_entry *rle; 2352 struct msix_table_entry *mte; 2353 struct msix_vector *mv; 2354 uint64_t addr; 2355 uint32_t data; 2356 int error, i, j; 2357 2358 /* 2359 * Handle MSI first. We try to find this IRQ among our list 2360 * of MSI IRQs. If we find it, we request updated address and 2361 * data registers and apply the results. 2362 */ 2363 if (cfg->msi.msi_alloc > 0) { 2364 /* If we don't have any active handlers, nothing to do. */ 2365 if (cfg->msi.msi_handlers == 0) 2366 return (0); 2367 for (i = 0; i < cfg->msi.msi_alloc; i++) { 2368 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 2369 i + 1); 2370 if (rle->start == irq) { 2371 error = PCIB_MAP_MSI(device_get_parent(bus), 2372 dev, irq, &addr, &data); 2373 if (error) 2374 return (error); 2375 pci_disable_msi(dev); 2376 dinfo->cfg.msi.msi_addr = addr; 2377 dinfo->cfg.msi.msi_data = data; 2378 pci_enable_msi(dev, addr, data); 2379 return (0); 2380 } 2381 } 2382 return (ENOENT); 2383 } 2384 2385 /* 2386 * For MSI-X, we check to see if we have this IRQ. If we do, 2387 * we request the updated mapping info. If that works, we go 2388 * through all the slots that use this IRQ and update them. 2389 */ 2390 if (cfg->msix.msix_alloc > 0) { 2391 for (i = 0; i < cfg->msix.msix_alloc; i++) { 2392 mv = &cfg->msix.msix_vectors[i]; 2393 if (mv->mv_irq == irq) { 2394 error = PCIB_MAP_MSI(device_get_parent(bus), 2395 dev, irq, &addr, &data); 2396 if (error) 2397 return (error); 2398 mv->mv_address = addr; 2399 mv->mv_data = data; 2400 for (j = 0; j < cfg->msix.msix_table_len; j++) { 2401 mte = &cfg->msix.msix_table[j]; 2402 if (mte->mte_vector != i + 1) 2403 continue; 2404 if (mte->mte_handlers == 0) 2405 continue; 2406 pci_mask_msix(dev, j); 2407 pci_enable_msix(dev, j, addr, data); 2408 pci_unmask_msix(dev, j); 2409 } 2410 } 2411 } 2412 return (ENOENT); 2413 } 2414 2415 return (ENOENT); 2416 } 2417 2418 /* 2419 * Returns true if the specified device is blacklisted because MSI 2420 * doesn't work. 2421 */ 2422 int 2423 pci_msi_device_blacklisted(device_t dev) 2424 { 2425 2426 if (!pci_honor_msi_blacklist) 2427 return (0); 2428 2429 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI)); 2430 } 2431 2432 /* 2433 * Determine if MSI is blacklisted globally on this system. Currently, 2434 * we just check for blacklisted chipsets as represented by the 2435 * host-PCI bridge at device 0:0:0. In the future, it may become 2436 * necessary to check other system attributes, such as the kenv values 2437 * that give the motherboard manufacturer and model number. 2438 */ 2439 static int 2440 pci_msi_blacklisted(void) 2441 { 2442 device_t dev; 2443 2444 if (!pci_honor_msi_blacklist) 2445 return (0); 2446 2447 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ 2448 if (!(pcie_chipset || pcix_chipset)) { 2449 if (vm_guest != VM_GUEST_NO) { 2450 /* 2451 * Whitelist older chipsets in virtual 2452 * machines known to support MSI. 2453 */ 2454 dev = pci_find_bsf(0, 0, 0); 2455 if (dev != NULL) 2456 return (!pci_has_quirk(pci_get_devid(dev), 2457 PCI_QUIRK_ENABLE_MSI_VM)); 2458 } 2459 return (1); 2460 } 2461 2462 dev = pci_find_bsf(0, 0, 0); 2463 if (dev != NULL) 2464 return (pci_msi_device_blacklisted(dev)); 2465 return (0); 2466 } 2467 2468 /* 2469 * Returns true if the specified device is blacklisted because MSI-X 2470 * doesn't work. Note that this assumes that if MSI doesn't work, 2471 * MSI-X doesn't either. 2472 */ 2473 int 2474 pci_msix_device_blacklisted(device_t dev) 2475 { 2476 2477 if (!pci_honor_msi_blacklist) 2478 return (0); 2479 2480 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX)) 2481 return (1); 2482 2483 return (pci_msi_device_blacklisted(dev)); 2484 } 2485 2486 /* 2487 * Determine if MSI-X is blacklisted globally on this system. If MSI 2488 * is blacklisted, assume that MSI-X is as well. Check for additional 2489 * chipsets where MSI works but MSI-X does not. 2490 */ 2491 static int 2492 pci_msix_blacklisted(void) 2493 { 2494 device_t dev; 2495 2496 if (!pci_honor_msi_blacklist) 2497 return (0); 2498 2499 dev = pci_find_bsf(0, 0, 0); 2500 if (dev != NULL && pci_has_quirk(pci_get_devid(dev), 2501 PCI_QUIRK_DISABLE_MSIX)) 2502 return (1); 2503 2504 return (pci_msi_blacklisted()); 2505 } 2506 2507 /* 2508 * Attempt to allocate *count MSI messages. The actual number allocated is 2509 * returned in *count. After this function returns, each message will be 2510 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 2511 */ 2512 int 2513 pci_alloc_msi_method(device_t dev, device_t child, int *count) 2514 { 2515 struct pci_devinfo *dinfo = device_get_ivars(child); 2516 pcicfgregs *cfg = &dinfo->cfg; 2517 struct resource_list_entry *rle; 2518 int actual, error, i, irqs[32]; 2519 uint16_t ctrl; 2520 2521 /* Don't let count == 0 get us into trouble. */ 2522 if (*count == 0) 2523 return (EINVAL); 2524 2525 /* If rid 0 is allocated, then fail. */ 2526 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 2527 if (rle != NULL && rle->res != NULL) 2528 return (ENXIO); 2529 2530 /* Already have allocated messages? */ 2531 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 2532 return (ENXIO); 2533 2534 /* If MSI is blacklisted for this system, fail. */ 2535 if (pci_msi_blacklisted()) 2536 return (ENXIO); 2537 2538 /* MSI capability present? */ 2539 if (cfg->msi.msi_location == 0 || !pci_do_msi) 2540 return (ENODEV); 2541 2542 if (bootverbose) 2543 device_printf(child, 2544 "attempting to allocate %d MSI vectors (%d supported)\n", 2545 *count, cfg->msi.msi_msgnum); 2546 2547 /* Don't ask for more than the device supports. */ 2548 actual = min(*count, cfg->msi.msi_msgnum); 2549 2550 /* Don't ask for more than 32 messages. */ 2551 actual = min(actual, 32); 2552 2553 /* MSI requires power of 2 number of messages. */ 2554 if (!powerof2(actual)) 2555 return (EINVAL); 2556 2557 for (;;) { 2558 /* Try to allocate N messages. */ 2559 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 2560 actual, irqs); 2561 if (error == 0) 2562 break; 2563 if (actual == 1) 2564 return (error); 2565 2566 /* Try N / 2. */ 2567 actual >>= 1; 2568 } 2569 2570 /* 2571 * We now have N actual messages mapped onto SYS_RES_IRQ 2572 * resources in the irqs[] array, so add new resources 2573 * starting at rid 1. 2574 */ 2575 for (i = 0; i < actual; i++) 2576 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 2577 irqs[i], irqs[i], 1); 2578 2579 if (bootverbose) { 2580 if (actual == 1) 2581 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 2582 else { 2583 int run; 2584 2585 /* 2586 * Be fancy and try to print contiguous runs 2587 * of IRQ values as ranges. 'run' is true if 2588 * we are in a range. 2589 */ 2590 device_printf(child, "using IRQs %d", irqs[0]); 2591 run = 0; 2592 for (i = 1; i < actual; i++) { 2593 /* Still in a run? */ 2594 if (irqs[i] == irqs[i - 1] + 1) { 2595 run = 1; 2596 continue; 2597 } 2598 2599 /* Finish previous range. */ 2600 if (run) { 2601 printf("-%d", irqs[i - 1]); 2602 run = 0; 2603 } 2604 2605 /* Start new range. */ 2606 printf(",%d", irqs[i]); 2607 } 2608 2609 /* Unfinished range? */ 2610 if (run) 2611 printf("-%d", irqs[actual - 1]); 2612 printf(" for MSI\n"); 2613 } 2614 } 2615 2616 /* Update control register with actual count. */ 2617 ctrl = cfg->msi.msi_ctrl; 2618 ctrl &= ~PCIM_MSICTRL_MME_MASK; 2619 ctrl |= (ffs(actual) - 1) << 4; 2620 cfg->msi.msi_ctrl = ctrl; 2621 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 2622 2623 /* Update counts of alloc'd messages. */ 2624 cfg->msi.msi_alloc = actual; 2625 cfg->msi.msi_handlers = 0; 2626 *count = actual; 2627 return (0); 2628 } 2629 2630 /* Release the MSI messages associated with this device. */ 2631 int 2632 pci_release_msi_method(device_t dev, device_t child) 2633 { 2634 struct pci_devinfo *dinfo = device_get_ivars(child); 2635 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2636 struct resource_list_entry *rle; 2637 int error, i, irqs[32]; 2638 2639 /* Try MSI-X first. */ 2640 error = pci_release_msix(dev, child); 2641 if (error != ENODEV) 2642 return (error); 2643 2644 /* Do we have any messages to release? */ 2645 if (msi->msi_alloc == 0) 2646 return (ENODEV); 2647 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); 2648 2649 /* Make sure none of the resources are allocated. */ 2650 if (msi->msi_handlers > 0) 2651 return (EBUSY); 2652 for (i = 0; i < msi->msi_alloc; i++) { 2653 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2654 KASSERT(rle != NULL, ("missing MSI resource")); 2655 if (rle->res != NULL) 2656 return (EBUSY); 2657 irqs[i] = rle->start; 2658 } 2659 2660 /* Update control register with 0 count. */ 2661 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), 2662 ("%s: MSI still enabled", __func__)); 2663 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; 2664 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2665 msi->msi_ctrl, 2); 2666 2667 /* Release the messages. */ 2668 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); 2669 for (i = 0; i < msi->msi_alloc; i++) 2670 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2671 2672 /* Update alloc count. */ 2673 msi->msi_alloc = 0; 2674 msi->msi_addr = 0; 2675 msi->msi_data = 0; 2676 return (0); 2677 } 2678 2679 /* 2680 * Return the max supported MSI messages this device supports. 2681 * Basically, assuming the MD code can alloc messages, this function 2682 * should return the maximum value that pci_alloc_msi() can return. 2683 * Thus, it is subject to the tunables, etc. 2684 */ 2685 int 2686 pci_msi_count_method(device_t dev, device_t child) 2687 { 2688 struct pci_devinfo *dinfo = device_get_ivars(child); 2689 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2690 2691 if (pci_do_msi && msi->msi_location != 0) 2692 return (msi->msi_msgnum); 2693 return (0); 2694 } 2695 2696 /* free pcicfgregs structure and all depending data structures */ 2697 2698 int 2699 pci_freecfg(struct pci_devinfo *dinfo) 2700 { 2701 struct devlist *devlist_head; 2702 struct pci_map *pm, *next; 2703 int i; 2704 2705 devlist_head = &pci_devq; 2706 2707 if (dinfo->cfg.vpd.vpd_reg) { 2708 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF); 2709 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++) 2710 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF); 2711 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF); 2712 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++) 2713 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF); 2714 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF); 2715 } 2716 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { 2717 free(pm, M_DEVBUF); 2718 } 2719 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 2720 free(dinfo, M_DEVBUF); 2721 2722 /* increment the generation count */ 2723 pci_generation++; 2724 2725 /* we're losing one device */ 2726 pci_numdevs--; 2727 return (0); 2728 } 2729 2730 /* 2731 * PCI power manangement 2732 */ 2733 int 2734 pci_set_powerstate_method(device_t dev, device_t child, int state) 2735 { 2736 struct pci_devinfo *dinfo = device_get_ivars(child); 2737 pcicfgregs *cfg = &dinfo->cfg; 2738 uint16_t status; 2739 int oldstate, highest, delay; 2740 2741 if (cfg->pp.pp_cap == 0) 2742 return (EOPNOTSUPP); 2743 2744 /* 2745 * Optimize a no state change request away. While it would be OK to 2746 * write to the hardware in theory, some devices have shown odd 2747 * behavior when going from D3 -> D3. 2748 */ 2749 oldstate = pci_get_powerstate(child); 2750 if (oldstate == state) 2751 return (0); 2752 2753 /* 2754 * The PCI power management specification states that after a state 2755 * transition between PCI power states, system software must 2756 * guarantee a minimal delay before the function accesses the device. 2757 * Compute the worst case delay that we need to guarantee before we 2758 * access the device. Many devices will be responsive much more 2759 * quickly than this delay, but there are some that don't respond 2760 * instantly to state changes. Transitions to/from D3 state require 2761 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 2762 * is done below with DELAY rather than a sleeper function because 2763 * this function can be called from contexts where we cannot sleep. 2764 */ 2765 highest = (oldstate > state) ? oldstate : state; 2766 if (highest == PCI_POWERSTATE_D3) 2767 delay = 10000; 2768 else if (highest == PCI_POWERSTATE_D2) 2769 delay = 200; 2770 else 2771 delay = 0; 2772 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 2773 & ~PCIM_PSTAT_DMASK; 2774 switch (state) { 2775 case PCI_POWERSTATE_D0: 2776 status |= PCIM_PSTAT_D0; 2777 break; 2778 case PCI_POWERSTATE_D1: 2779 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 2780 return (EOPNOTSUPP); 2781 status |= PCIM_PSTAT_D1; 2782 break; 2783 case PCI_POWERSTATE_D2: 2784 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 2785 return (EOPNOTSUPP); 2786 status |= PCIM_PSTAT_D2; 2787 break; 2788 case PCI_POWERSTATE_D3: 2789 status |= PCIM_PSTAT_D3; 2790 break; 2791 default: 2792 return (EINVAL); 2793 } 2794 2795 if (bootverbose) 2796 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate, 2797 state); 2798 2799 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 2800 if (delay) 2801 DELAY(delay); 2802 return (0); 2803 } 2804 2805 int 2806 pci_get_powerstate_method(device_t dev, device_t child) 2807 { 2808 struct pci_devinfo *dinfo = device_get_ivars(child); 2809 pcicfgregs *cfg = &dinfo->cfg; 2810 uint16_t status; 2811 int result; 2812 2813 if (cfg->pp.pp_cap != 0) { 2814 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 2815 switch (status & PCIM_PSTAT_DMASK) { 2816 case PCIM_PSTAT_D0: 2817 result = PCI_POWERSTATE_D0; 2818 break; 2819 case PCIM_PSTAT_D1: 2820 result = PCI_POWERSTATE_D1; 2821 break; 2822 case PCIM_PSTAT_D2: 2823 result = PCI_POWERSTATE_D2; 2824 break; 2825 case PCIM_PSTAT_D3: 2826 result = PCI_POWERSTATE_D3; 2827 break; 2828 default: 2829 result = PCI_POWERSTATE_UNKNOWN; 2830 break; 2831 } 2832 } else { 2833 /* No support, device is always at D0 */ 2834 result = PCI_POWERSTATE_D0; 2835 } 2836 return (result); 2837 } 2838 2839 /* 2840 * Some convenience functions for PCI device drivers. 2841 */ 2842 2843 static __inline void 2844 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 2845 { 2846 uint16_t command; 2847 2848 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2849 command |= bit; 2850 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2851 } 2852 2853 static __inline void 2854 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 2855 { 2856 uint16_t command; 2857 2858 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2859 command &= ~bit; 2860 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2861 } 2862 2863 int 2864 pci_enable_busmaster_method(device_t dev, device_t child) 2865 { 2866 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2867 return (0); 2868 } 2869 2870 int 2871 pci_disable_busmaster_method(device_t dev, device_t child) 2872 { 2873 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2874 return (0); 2875 } 2876 2877 int 2878 pci_enable_io_method(device_t dev, device_t child, int space) 2879 { 2880 uint16_t bit; 2881 2882 switch(space) { 2883 case SYS_RES_IOPORT: 2884 bit = PCIM_CMD_PORTEN; 2885 break; 2886 case SYS_RES_MEMORY: 2887 bit = PCIM_CMD_MEMEN; 2888 break; 2889 default: 2890 return (EINVAL); 2891 } 2892 pci_set_command_bit(dev, child, bit); 2893 return (0); 2894 } 2895 2896 int 2897 pci_disable_io_method(device_t dev, device_t child, int space) 2898 { 2899 uint16_t bit; 2900 2901 switch(space) { 2902 case SYS_RES_IOPORT: 2903 bit = PCIM_CMD_PORTEN; 2904 break; 2905 case SYS_RES_MEMORY: 2906 bit = PCIM_CMD_MEMEN; 2907 break; 2908 default: 2909 return (EINVAL); 2910 } 2911 pci_clear_command_bit(dev, child, bit); 2912 return (0); 2913 } 2914 2915 /* 2916 * New style pci driver. Parent device is either a pci-host-bridge or a 2917 * pci-pci-bridge. Both kinds are represented by instances of pcib. 2918 */ 2919 2920 void 2921 pci_print_verbose(struct pci_devinfo *dinfo) 2922 { 2923 2924 if (bootverbose) { 2925 pcicfgregs *cfg = &dinfo->cfg; 2926 2927 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 2928 cfg->vendor, cfg->device, cfg->revid); 2929 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n", 2930 cfg->domain, cfg->bus, cfg->slot, cfg->func); 2931 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 2932 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 2933 cfg->mfdev); 2934 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 2935 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 2936 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 2937 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 2938 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 2939 if (cfg->intpin > 0) 2940 printf("\tintpin=%c, irq=%d\n", 2941 cfg->intpin +'a' -1, cfg->intline); 2942 if (cfg->pp.pp_cap) { 2943 uint16_t status; 2944 2945 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 2946 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 2947 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 2948 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 2949 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 2950 status & PCIM_PSTAT_DMASK); 2951 } 2952 if (cfg->msi.msi_location) { 2953 int ctrl; 2954 2955 ctrl = cfg->msi.msi_ctrl; 2956 printf("\tMSI supports %d message%s%s%s\n", 2957 cfg->msi.msi_msgnum, 2958 (cfg->msi.msi_msgnum == 1) ? "" : "s", 2959 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 2960 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 2961 } 2962 if (cfg->msix.msix_location) { 2963 printf("\tMSI-X supports %d message%s ", 2964 cfg->msix.msix_msgnum, 2965 (cfg->msix.msix_msgnum == 1) ? "" : "s"); 2966 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 2967 printf("in map 0x%x\n", 2968 cfg->msix.msix_table_bar); 2969 else 2970 printf("in maps 0x%x and 0x%x\n", 2971 cfg->msix.msix_table_bar, 2972 cfg->msix.msix_pba_bar); 2973 } 2974 } 2975 } 2976 2977 static int 2978 pci_porten(device_t dev) 2979 { 2980 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0; 2981 } 2982 2983 static int 2984 pci_memen(device_t dev) 2985 { 2986 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0; 2987 } 2988 2989 void 2990 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, 2991 int *bar64) 2992 { 2993 struct pci_devinfo *dinfo; 2994 pci_addr_t map, testval; 2995 int ln2range; 2996 uint16_t cmd; 2997 2998 /* 2999 * The device ROM BAR is special. It is always a 32-bit 3000 * memory BAR. Bit 0 is special and should not be set when 3001 * sizing the BAR. 3002 */ 3003 dinfo = device_get_ivars(dev); 3004 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { 3005 map = pci_read_config(dev, reg, 4); 3006 pci_write_config(dev, reg, 0xfffffffe, 4); 3007 testval = pci_read_config(dev, reg, 4); 3008 pci_write_config(dev, reg, map, 4); 3009 *mapp = map; 3010 *testvalp = testval; 3011 if (bar64 != NULL) 3012 *bar64 = 0; 3013 return; 3014 } 3015 3016 map = pci_read_config(dev, reg, 4); 3017 ln2range = pci_maprange(map); 3018 if (ln2range == 64) 3019 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3020 3021 /* 3022 * Disable decoding via the command register before 3023 * determining the BAR's length since we will be placing it in 3024 * a weird state. 3025 */ 3026 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3027 pci_write_config(dev, PCIR_COMMAND, 3028 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 3029 3030 /* 3031 * Determine the BAR's length by writing all 1's. The bottom 3032 * log_2(size) bits of the BAR will stick as 0 when we read 3033 * the value back. 3034 * 3035 * NB: according to the PCI Local Bus Specification, rev. 3.0: 3036 * "Software writes 0FFFFFFFFh to both registers, reads them back, 3037 * and combines the result into a 64-bit value." (section 6.2.5.1) 3038 * 3039 * Writes to both registers must be performed before attempting to 3040 * read back the size value. 3041 */ 3042 testval = 0; 3043 pci_write_config(dev, reg, 0xffffffff, 4); 3044 if (ln2range == 64) { 3045 pci_write_config(dev, reg + 4, 0xffffffff, 4); 3046 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3047 } 3048 testval |= pci_read_config(dev, reg, 4); 3049 3050 /* 3051 * Restore the original value of the BAR. We may have reprogrammed 3052 * the BAR of the low-level console device and when booting verbose, 3053 * we need the console device addressable. 3054 */ 3055 pci_write_config(dev, reg, map, 4); 3056 if (ln2range == 64) 3057 pci_write_config(dev, reg + 4, map >> 32, 4); 3058 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3059 3060 *mapp = map; 3061 *testvalp = testval; 3062 if (bar64 != NULL) 3063 *bar64 = (ln2range == 64); 3064 } 3065 3066 static void 3067 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base) 3068 { 3069 struct pci_devinfo *dinfo; 3070 int ln2range; 3071 3072 /* The device ROM BAR is always a 32-bit memory BAR. */ 3073 dinfo = device_get_ivars(dev); 3074 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3075 ln2range = 32; 3076 else 3077 ln2range = pci_maprange(pm->pm_value); 3078 pci_write_config(dev, pm->pm_reg, base, 4); 3079 if (ln2range == 64) 3080 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); 3081 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); 3082 if (ln2range == 64) 3083 pm->pm_value |= (pci_addr_t)pci_read_config(dev, 3084 pm->pm_reg + 4, 4) << 32; 3085 } 3086 3087 struct pci_map * 3088 pci_find_bar(device_t dev, int reg) 3089 { 3090 struct pci_devinfo *dinfo; 3091 struct pci_map *pm; 3092 3093 dinfo = device_get_ivars(dev); 3094 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3095 if (pm->pm_reg == reg) 3096 return (pm); 3097 } 3098 return (NULL); 3099 } 3100 3101 int 3102 pci_bar_enabled(device_t dev, struct pci_map *pm) 3103 { 3104 struct pci_devinfo *dinfo; 3105 uint16_t cmd; 3106 3107 dinfo = device_get_ivars(dev); 3108 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && 3109 !(pm->pm_value & PCIM_BIOS_ENABLE)) 3110 return (0); 3111 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3112 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) 3113 return ((cmd & PCIM_CMD_MEMEN) != 0); 3114 else 3115 return ((cmd & PCIM_CMD_PORTEN) != 0); 3116 } 3117 3118 struct pci_map * 3119 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size) 3120 { 3121 struct pci_devinfo *dinfo; 3122 struct pci_map *pm, *prev; 3123 3124 dinfo = device_get_ivars(dev); 3125 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO); 3126 pm->pm_reg = reg; 3127 pm->pm_value = value; 3128 pm->pm_size = size; 3129 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { 3130 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", 3131 reg)); 3132 if (STAILQ_NEXT(prev, pm_link) == NULL || 3133 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) 3134 break; 3135 } 3136 if (prev != NULL) 3137 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); 3138 else 3139 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); 3140 return (pm); 3141 } 3142 3143 static void 3144 pci_restore_bars(device_t dev) 3145 { 3146 struct pci_devinfo *dinfo; 3147 struct pci_map *pm; 3148 int ln2range; 3149 3150 dinfo = device_get_ivars(dev); 3151 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3152 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3153 ln2range = 32; 3154 else 3155 ln2range = pci_maprange(pm->pm_value); 3156 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); 3157 if (ln2range == 64) 3158 pci_write_config(dev, pm->pm_reg + 4, 3159 pm->pm_value >> 32, 4); 3160 } 3161 } 3162 3163 /* 3164 * Add a resource based on a pci map register. Return 1 if the map 3165 * register is a 32bit map register or 2 if it is a 64bit register. 3166 */ 3167 static int 3168 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, 3169 int force, int prefetch) 3170 { 3171 struct pci_map *pm; 3172 pci_addr_t base, map, testval; 3173 pci_addr_t start, end, count; 3174 int barlen, basezero, flags, maprange, mapsize, type; 3175 uint16_t cmd; 3176 struct resource *res; 3177 3178 /* 3179 * The BAR may already exist if the device is a CardBus card 3180 * whose CIS is stored in this BAR. 3181 */ 3182 pm = pci_find_bar(dev, reg); 3183 if (pm != NULL) { 3184 maprange = pci_maprange(pm->pm_value); 3185 barlen = maprange == 64 ? 2 : 1; 3186 return (barlen); 3187 } 3188 3189 pci_read_bar(dev, reg, &map, &testval, NULL); 3190 if (PCI_BAR_MEM(map)) { 3191 type = SYS_RES_MEMORY; 3192 if (map & PCIM_BAR_MEM_PREFETCH) 3193 prefetch = 1; 3194 } else 3195 type = SYS_RES_IOPORT; 3196 mapsize = pci_mapsize(testval); 3197 base = pci_mapbase(map); 3198 #ifdef __PCI_BAR_ZERO_VALID 3199 basezero = 0; 3200 #else 3201 basezero = base == 0; 3202 #endif 3203 maprange = pci_maprange(map); 3204 barlen = maprange == 64 ? 2 : 1; 3205 3206 /* 3207 * For I/O registers, if bottom bit is set, and the next bit up 3208 * isn't clear, we know we have a BAR that doesn't conform to the 3209 * spec, so ignore it. Also, sanity check the size of the data 3210 * areas to the type of memory involved. Memory must be at least 3211 * 16 bytes in size, while I/O ranges must be at least 4. 3212 */ 3213 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0) 3214 return (barlen); 3215 if ((type == SYS_RES_MEMORY && mapsize < 4) || 3216 (type == SYS_RES_IOPORT && mapsize < 2)) 3217 return (barlen); 3218 3219 /* Save a record of this BAR. */ 3220 pm = pci_add_bar(dev, reg, map, mapsize); 3221 if (bootverbose) { 3222 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d", 3223 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize); 3224 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3225 printf(", port disabled\n"); 3226 else if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3227 printf(", memory disabled\n"); 3228 else 3229 printf(", enabled\n"); 3230 } 3231 3232 /* 3233 * If base is 0, then we have problems if this architecture does 3234 * not allow that. It is best to ignore such entries for the 3235 * moment. These will be allocated later if the driver specifically 3236 * requests them. However, some removable buses look better when 3237 * all resources are allocated, so allow '0' to be overriden. 3238 * 3239 * Similarly treat maps whose values is the same as the test value 3240 * read back. These maps have had all f's written to them by the 3241 * BIOS in an attempt to disable the resources. 3242 */ 3243 if (!force && (basezero || map == testval)) 3244 return (barlen); 3245 if ((u_long)base != base) { 3246 device_printf(bus, 3247 "pci%d:%d:%d:%d bar %#x too many address bits", 3248 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev), 3249 pci_get_function(dev), reg); 3250 return (barlen); 3251 } 3252 3253 /* 3254 * This code theoretically does the right thing, but has 3255 * undesirable side effects in some cases where peripherals 3256 * respond oddly to having these bits enabled. Let the user 3257 * be able to turn them off (since pci_enable_io_modes is 1 by 3258 * default). 3259 */ 3260 if (pci_enable_io_modes) { 3261 /* Turn on resources that have been left off by a lazy BIOS */ 3262 if (type == SYS_RES_IOPORT && !pci_porten(dev)) { 3263 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3264 cmd |= PCIM_CMD_PORTEN; 3265 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3266 } 3267 if (type == SYS_RES_MEMORY && !pci_memen(dev)) { 3268 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3269 cmd |= PCIM_CMD_MEMEN; 3270 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3271 } 3272 } else { 3273 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3274 return (barlen); 3275 if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3276 return (barlen); 3277 } 3278 3279 count = (pci_addr_t)1 << mapsize; 3280 flags = RF_ALIGNMENT_LOG2(mapsize); 3281 if (prefetch) 3282 flags |= RF_PREFETCHABLE; 3283 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) { 3284 start = 0; /* Let the parent decide. */ 3285 end = ~0; 3286 } else { 3287 start = base; 3288 end = base + count - 1; 3289 } 3290 resource_list_add(rl, type, reg, start, end, count); 3291 3292 /* 3293 * Try to allocate the resource for this BAR from our parent 3294 * so that this resource range is already reserved. The 3295 * driver for this device will later inherit this resource in 3296 * pci_alloc_resource(). 3297 */ 3298 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count, 3299 flags); 3300 if ((pci_do_realloc_bars 3301 || pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_REALLOC_BAR)) 3302 && res == NULL && (start != 0 || end != ~0)) { 3303 /* 3304 * If the allocation fails, try to allocate a resource for 3305 * this BAR using any available range. The firmware felt 3306 * it was important enough to assign a resource, so don't 3307 * disable decoding if we can help it. 3308 */ 3309 resource_list_delete(rl, type, reg); 3310 resource_list_add(rl, type, reg, 0, ~0, count); 3311 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0, 3312 count, flags); 3313 } 3314 if (res == NULL) { 3315 /* 3316 * If the allocation fails, delete the resource list entry 3317 * and disable decoding for this device. 3318 * 3319 * If the driver requests this resource in the future, 3320 * pci_reserve_map() will try to allocate a fresh 3321 * resource range. 3322 */ 3323 resource_list_delete(rl, type, reg); 3324 pci_disable_io(dev, type); 3325 if (bootverbose) 3326 device_printf(bus, 3327 "pci%d:%d:%d:%d bar %#x failed to allocate\n", 3328 pci_get_domain(dev), pci_get_bus(dev), 3329 pci_get_slot(dev), pci_get_function(dev), reg); 3330 } else { 3331 start = rman_get_start(res); 3332 pci_write_bar(dev, pm, start); 3333 } 3334 return (barlen); 3335 } 3336 3337 /* 3338 * For ATA devices we need to decide early what addressing mode to use. 3339 * Legacy demands that the primary and secondary ATA ports sits on the 3340 * same addresses that old ISA hardware did. This dictates that we use 3341 * those addresses and ignore the BAR's if we cannot set PCI native 3342 * addressing mode. 3343 */ 3344 static void 3345 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, 3346 uint32_t prefetchmask) 3347 { 3348 int rid, type, progif; 3349 #if 0 3350 /* if this device supports PCI native addressing use it */ 3351 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3352 if ((progif & 0x8a) == 0x8a) { 3353 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 3354 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 3355 printf("Trying ATA native PCI addressing mode\n"); 3356 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 3357 } 3358 } 3359 #endif 3360 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3361 type = SYS_RES_IOPORT; 3362 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 3363 pci_add_map(bus, dev, PCIR_BAR(0), rl, force, 3364 prefetchmask & (1 << 0)); 3365 pci_add_map(bus, dev, PCIR_BAR(1), rl, force, 3366 prefetchmask & (1 << 1)); 3367 } else { 3368 rid = PCIR_BAR(0); 3369 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 3370 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0, 3371 0x1f7, 8, 0); 3372 rid = PCIR_BAR(1); 3373 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 3374 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6, 3375 0x3f6, 1, 0); 3376 } 3377 if (progif & PCIP_STORAGE_IDE_MODESEC) { 3378 pci_add_map(bus, dev, PCIR_BAR(2), rl, force, 3379 prefetchmask & (1 << 2)); 3380 pci_add_map(bus, dev, PCIR_BAR(3), rl, force, 3381 prefetchmask & (1 << 3)); 3382 } else { 3383 rid = PCIR_BAR(2); 3384 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 3385 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170, 3386 0x177, 8, 0); 3387 rid = PCIR_BAR(3); 3388 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 3389 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376, 3390 0x376, 1, 0); 3391 } 3392 pci_add_map(bus, dev, PCIR_BAR(4), rl, force, 3393 prefetchmask & (1 << 4)); 3394 pci_add_map(bus, dev, PCIR_BAR(5), rl, force, 3395 prefetchmask & (1 << 5)); 3396 } 3397 3398 static void 3399 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 3400 { 3401 struct pci_devinfo *dinfo = device_get_ivars(dev); 3402 pcicfgregs *cfg = &dinfo->cfg; 3403 char tunable_name[64]; 3404 int irq; 3405 3406 /* Has to have an intpin to have an interrupt. */ 3407 if (cfg->intpin == 0) 3408 return; 3409 3410 /* Let the user override the IRQ with a tunable. */ 3411 irq = PCI_INVALID_IRQ; 3412 snprintf(tunable_name, sizeof(tunable_name), 3413 "hw.pci%d.%d.%d.INT%c.irq", 3414 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 3415 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 3416 irq = PCI_INVALID_IRQ; 3417 3418 /* 3419 * If we didn't get an IRQ via the tunable, then we either use the 3420 * IRQ value in the intline register or we ask the bus to route an 3421 * interrupt for us. If force_route is true, then we only use the 3422 * value in the intline register if the bus was unable to assign an 3423 * IRQ. 3424 */ 3425 if (!PCI_INTERRUPT_VALID(irq)) { 3426 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 3427 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 3428 if (!PCI_INTERRUPT_VALID(irq)) 3429 irq = cfg->intline; 3430 } 3431 3432 /* If after all that we don't have an IRQ, just bail. */ 3433 if (!PCI_INTERRUPT_VALID(irq)) 3434 return; 3435 3436 /* Update the config register if it changed. */ 3437 if (irq != cfg->intline) { 3438 cfg->intline = irq; 3439 pci_write_config(dev, PCIR_INTLINE, irq, 1); 3440 } 3441 3442 /* Add this IRQ as rid 0 interrupt resource. */ 3443 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 3444 } 3445 3446 /* Perform early OHCI takeover from SMM. */ 3447 static void 3448 ohci_early_takeover(device_t self) 3449 { 3450 struct resource *res; 3451 uint32_t ctl; 3452 int rid; 3453 int i; 3454 3455 rid = PCIR_BAR(0); 3456 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3457 if (res == NULL) 3458 return; 3459 3460 ctl = bus_read_4(res, OHCI_CONTROL); 3461 if (ctl & OHCI_IR) { 3462 if (bootverbose) 3463 printf("ohci early: " 3464 "SMM active, request owner change\n"); 3465 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR); 3466 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 3467 DELAY(1000); 3468 ctl = bus_read_4(res, OHCI_CONTROL); 3469 } 3470 if (ctl & OHCI_IR) { 3471 if (bootverbose) 3472 printf("ohci early: " 3473 "SMM does not respond, resetting\n"); 3474 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET); 3475 } 3476 /* Disable interrupts */ 3477 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 3478 } 3479 3480 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3481 } 3482 3483 /* Perform early UHCI takeover from SMM. */ 3484 static void 3485 uhci_early_takeover(device_t self) 3486 { 3487 struct resource *res; 3488 int rid; 3489 3490 /* 3491 * Set the PIRQD enable bit and switch off all the others. We don't 3492 * want legacy support to interfere with us XXX Does this also mean 3493 * that the BIOS won't touch the keyboard anymore if it is connected 3494 * to the ports of the root hub? 3495 */ 3496 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2); 3497 3498 /* Disable interrupts */ 3499 rid = PCI_UHCI_BASE_REG; 3500 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE); 3501 if (res != NULL) { 3502 bus_write_2(res, UHCI_INTR, 0); 3503 bus_release_resource(self, SYS_RES_IOPORT, rid, res); 3504 } 3505 } 3506 3507 /* Perform early EHCI takeover from SMM. */ 3508 static void 3509 ehci_early_takeover(device_t self) 3510 { 3511 struct resource *res; 3512 uint32_t cparams; 3513 uint32_t eec; 3514 uint8_t eecp; 3515 uint8_t bios_sem; 3516 uint8_t offs; 3517 int rid; 3518 int i; 3519 3520 rid = PCIR_BAR(0); 3521 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3522 if (res == NULL) 3523 return; 3524 3525 cparams = bus_read_4(res, EHCI_HCCPARAMS); 3526 3527 /* Synchronise with the BIOS if it owns the controller. */ 3528 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0; 3529 eecp = EHCI_EECP_NEXT(eec)) { 3530 eec = pci_read_config(self, eecp, 4); 3531 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) { 3532 continue; 3533 } 3534 bios_sem = pci_read_config(self, eecp + 3535 EHCI_LEGSUP_BIOS_SEM, 1); 3536 if (bios_sem == 0) { 3537 continue; 3538 } 3539 if (bootverbose) 3540 printf("ehci early: " 3541 "SMM active, request owner change\n"); 3542 3543 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1); 3544 3545 for (i = 0; (i < 100) && (bios_sem != 0); i++) { 3546 DELAY(1000); 3547 bios_sem = pci_read_config(self, eecp + 3548 EHCI_LEGSUP_BIOS_SEM, 1); 3549 } 3550 3551 if (bios_sem != 0) { 3552 if (bootverbose) 3553 printf("ehci early: " 3554 "SMM does not respond\n"); 3555 } 3556 /* Disable interrupts */ 3557 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION)); 3558 bus_write_4(res, offs + EHCI_USBINTR, 0); 3559 } 3560 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3561 } 3562 3563 /* Perform early XHCI takeover from SMM. */ 3564 static void 3565 xhci_early_takeover(device_t self) 3566 { 3567 struct resource *res; 3568 uint32_t cparams; 3569 uint32_t eec; 3570 uint8_t eecp; 3571 uint8_t bios_sem; 3572 uint8_t offs; 3573 int rid; 3574 int i; 3575 3576 rid = PCIR_BAR(0); 3577 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3578 if (res == NULL) 3579 return; 3580 3581 cparams = bus_read_4(res, XHCI_HCSPARAMS0); 3582 3583 eec = -1; 3584 3585 /* Synchronise with the BIOS if it owns the controller. */ 3586 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 3587 eecp += XHCI_XECP_NEXT(eec) << 2) { 3588 eec = bus_read_4(res, eecp); 3589 3590 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 3591 continue; 3592 3593 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM); 3594 if (bios_sem == 0) 3595 continue; 3596 3597 if (bootverbose) 3598 printf("xhci early: " 3599 "SMM active, request owner change\n"); 3600 3601 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1); 3602 3603 /* wait a maximum of 5 second */ 3604 3605 for (i = 0; (i < 5000) && (bios_sem != 0); i++) { 3606 DELAY(1000); 3607 bios_sem = bus_read_1(res, eecp + 3608 XHCI_XECP_BIOS_SEM); 3609 } 3610 3611 if (bios_sem != 0) { 3612 if (bootverbose) 3613 printf("xhci early: " 3614 "SMM does not respond\n"); 3615 } 3616 3617 /* Disable interrupts */ 3618 offs = bus_read_1(res, XHCI_CAPLENGTH); 3619 bus_write_4(res, offs + XHCI_USBCMD, 0); 3620 bus_read_4(res, offs + XHCI_USBSTS); 3621 } 3622 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3623 } 3624 3625 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 3626 static void 3627 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg, 3628 struct resource_list *rl) 3629 { 3630 struct resource *res; 3631 char *cp; 3632 rman_res_t start, end, count; 3633 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus; 3634 3635 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3636 case PCIM_HDRTYPE_BRIDGE: 3637 sec_reg = PCIR_SECBUS_1; 3638 sub_reg = PCIR_SUBBUS_1; 3639 break; 3640 case PCIM_HDRTYPE_CARDBUS: 3641 sec_reg = PCIR_SECBUS_2; 3642 sub_reg = PCIR_SUBBUS_2; 3643 break; 3644 default: 3645 return; 3646 } 3647 3648 /* 3649 * If the existing bus range is valid, attempt to reserve it 3650 * from our parent. If this fails for any reason, clear the 3651 * secbus and subbus registers. 3652 * 3653 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus? 3654 * This would at least preserve the existing sec_bus if it is 3655 * valid. 3656 */ 3657 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1); 3658 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1); 3659 3660 /* Quirk handling. */ 3661 switch (pci_get_devid(dev)) { 3662 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 3663 sup_bus = pci_read_config(dev, 0x41, 1); 3664 if (sup_bus != 0xff) { 3665 sec_bus = sup_bus + 1; 3666 sub_bus = sup_bus + 1; 3667 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1); 3668 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3669 } 3670 break; 3671 3672 case 0x00dd10de: 3673 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 3674 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 3675 break; 3676 if (strncmp(cp, "Compal", 6) != 0) { 3677 freeenv(cp); 3678 break; 3679 } 3680 freeenv(cp); 3681 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 3682 break; 3683 if (strncmp(cp, "08A0", 4) != 0) { 3684 freeenv(cp); 3685 break; 3686 } 3687 freeenv(cp); 3688 if (sub_bus < 0xa) { 3689 sub_bus = 0xa; 3690 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3691 } 3692 break; 3693 } 3694 3695 if (bootverbose) 3696 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus); 3697 if (sec_bus > 0 && sub_bus >= sec_bus) { 3698 start = sec_bus; 3699 end = sub_bus; 3700 count = end - start + 1; 3701 3702 resource_list_add(rl, PCI_RES_BUS, 0, 0, ~0, count); 3703 3704 /* 3705 * If requested, clear secondary bus registers in 3706 * bridge devices to force a complete renumbering 3707 * rather than reserving the existing range. However, 3708 * preserve the existing size. 3709 */ 3710 if (pci_clear_buses) 3711 goto clear; 3712 3713 rid = 0; 3714 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid, 3715 start, end, count, 0); 3716 if (res != NULL) 3717 return; 3718 3719 if (bootverbose) 3720 device_printf(bus, 3721 "pci%d:%d:%d:%d secbus failed to allocate\n", 3722 pci_get_domain(dev), pci_get_bus(dev), 3723 pci_get_slot(dev), pci_get_function(dev)); 3724 } 3725 3726 clear: 3727 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1); 3728 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1); 3729 } 3730 3731 static struct resource * 3732 pci_alloc_secbus(device_t dev, device_t child, int *rid, rman_res_t start, 3733 rman_res_t end, rman_res_t count, u_int flags) 3734 { 3735 struct pci_devinfo *dinfo; 3736 pcicfgregs *cfg; 3737 struct resource_list *rl; 3738 struct resource *res; 3739 int sec_reg, sub_reg; 3740 3741 dinfo = device_get_ivars(child); 3742 cfg = &dinfo->cfg; 3743 rl = &dinfo->resources; 3744 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3745 case PCIM_HDRTYPE_BRIDGE: 3746 sec_reg = PCIR_SECBUS_1; 3747 sub_reg = PCIR_SUBBUS_1; 3748 break; 3749 case PCIM_HDRTYPE_CARDBUS: 3750 sec_reg = PCIR_SECBUS_2; 3751 sub_reg = PCIR_SUBBUS_2; 3752 break; 3753 default: 3754 return (NULL); 3755 } 3756 3757 if (*rid != 0) 3758 return (NULL); 3759 3760 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL) 3761 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count); 3762 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) { 3763 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid, 3764 start, end, count, flags & ~RF_ACTIVE); 3765 if (res == NULL) { 3766 resource_list_delete(rl, PCI_RES_BUS, *rid); 3767 device_printf(child, "allocating %ju bus%s failed\n", 3768 count, count == 1 ? "" : "es"); 3769 return (NULL); 3770 } 3771 if (bootverbose) 3772 device_printf(child, 3773 "Lazy allocation of %ju bus%s at %ju\n", count, 3774 count == 1 ? "" : "es", rman_get_start(res)); 3775 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1); 3776 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1); 3777 } 3778 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start, 3779 end, count, flags)); 3780 } 3781 #endif 3782 3783 static int 3784 pci_ea_bei_to_rid(device_t dev, int bei) 3785 { 3786 #ifdef PCI_IOV 3787 struct pci_devinfo *dinfo; 3788 int iov_pos; 3789 struct pcicfg_iov *iov; 3790 3791 dinfo = device_get_ivars(dev); 3792 iov = dinfo->cfg.iov; 3793 if (iov != NULL) 3794 iov_pos = iov->iov_pos; 3795 else 3796 iov_pos = 0; 3797 #endif 3798 3799 /* Check if matches BAR */ 3800 if ((bei >= PCIM_EA_BEI_BAR_0) && 3801 (bei <= PCIM_EA_BEI_BAR_5)) 3802 return (PCIR_BAR(bei)); 3803 3804 /* Check ROM */ 3805 if (bei == PCIM_EA_BEI_ROM) 3806 return (PCIR_BIOS); 3807 3808 #ifdef PCI_IOV 3809 /* Check if matches VF_BAR */ 3810 if ((iov != NULL) && (bei >= PCIM_EA_BEI_VF_BAR_0) && 3811 (bei <= PCIM_EA_BEI_VF_BAR_5)) 3812 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) + 3813 iov_pos); 3814 #endif 3815 3816 return (-1); 3817 } 3818 3819 int 3820 pci_ea_is_enabled(device_t dev, int rid) 3821 { 3822 struct pci_ea_entry *ea; 3823 struct pci_devinfo *dinfo; 3824 3825 dinfo = device_get_ivars(dev); 3826 3827 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3828 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid) 3829 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0); 3830 } 3831 3832 return (0); 3833 } 3834 3835 void 3836 pci_add_resources_ea(device_t bus, device_t dev, int alloc_iov) 3837 { 3838 struct pci_ea_entry *ea; 3839 struct pci_devinfo *dinfo; 3840 pci_addr_t start, end, count; 3841 struct resource_list *rl; 3842 int type, flags, rid; 3843 struct resource *res; 3844 uint32_t tmp; 3845 #ifdef PCI_IOV 3846 struct pcicfg_iov *iov; 3847 #endif 3848 3849 dinfo = device_get_ivars(dev); 3850 rl = &dinfo->resources; 3851 flags = 0; 3852 3853 #ifdef PCI_IOV 3854 iov = dinfo->cfg.iov; 3855 #endif 3856 3857 if (dinfo->cfg.ea.ea_location == 0) 3858 return; 3859 3860 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3861 /* 3862 * TODO: Ignore EA-BAR if is not enabled. 3863 * Currently the EA implementation supports 3864 * only situation, where EA structure contains 3865 * predefined entries. In case they are not enabled 3866 * leave them unallocated and proceed with 3867 * a legacy-BAR mechanism. 3868 */ 3869 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0) 3870 continue; 3871 3872 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) { 3873 case PCIM_EA_P_MEM_PREFETCH: 3874 case PCIM_EA_P_VF_MEM_PREFETCH: 3875 flags = RF_PREFETCHABLE; 3876 /* FALLTHROUGH */ 3877 case PCIM_EA_P_VF_MEM: 3878 case PCIM_EA_P_MEM: 3879 type = SYS_RES_MEMORY; 3880 break; 3881 case PCIM_EA_P_IO: 3882 type = SYS_RES_IOPORT; 3883 break; 3884 default: 3885 continue; 3886 } 3887 3888 if (alloc_iov != 0) { 3889 #ifdef PCI_IOV 3890 /* Allocating IOV, confirm BEI matches */ 3891 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) || 3892 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5)) 3893 continue; 3894 #else 3895 continue; 3896 #endif 3897 } else { 3898 /* Allocating BAR, confirm BEI matches */ 3899 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) || 3900 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) && 3901 (ea->eae_bei != PCIM_EA_BEI_ROM)) 3902 continue; 3903 } 3904 3905 rid = pci_ea_bei_to_rid(dev, ea->eae_bei); 3906 if (rid < 0) 3907 continue; 3908 3909 /* Skip resources already allocated by EA */ 3910 if ((resource_list_find(rl, SYS_RES_MEMORY, rid) != NULL) || 3911 (resource_list_find(rl, SYS_RES_IOPORT, rid) != NULL)) 3912 continue; 3913 3914 start = ea->eae_base; 3915 count = ea->eae_max_offset + 1; 3916 #ifdef PCI_IOV 3917 if (iov != NULL) 3918 count = count * iov->iov_num_vfs; 3919 #endif 3920 end = start + count - 1; 3921 if (count == 0) 3922 continue; 3923 3924 resource_list_add(rl, type, rid, start, end, count); 3925 res = resource_list_reserve(rl, bus, dev, type, &rid, start, end, count, 3926 flags); 3927 if (res == NULL) { 3928 resource_list_delete(rl, type, rid); 3929 3930 /* 3931 * Failed to allocate using EA, disable entry. 3932 * Another attempt to allocation will be performed 3933 * further, but this time using legacy BAR registers 3934 */ 3935 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4); 3936 tmp &= ~PCIM_EA_ENABLE; 3937 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4); 3938 3939 /* 3940 * Disabling entry might fail in case it is hardwired. 3941 * Read flags again to match current status. 3942 */ 3943 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4); 3944 3945 continue; 3946 } 3947 3948 /* As per specification, fill BAR with zeros */ 3949 pci_write_config(dev, rid, 0, 4); 3950 } 3951 } 3952 3953 void 3954 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 3955 { 3956 struct pci_devinfo *dinfo; 3957 pcicfgregs *cfg; 3958 struct resource_list *rl; 3959 const struct pci_quirk *q; 3960 uint32_t devid; 3961 int i; 3962 3963 dinfo = device_get_ivars(dev); 3964 cfg = &dinfo->cfg; 3965 rl = &dinfo->resources; 3966 devid = (cfg->device << 16) | cfg->vendor; 3967 3968 /* Allocate resources using Enhanced Allocation */ 3969 pci_add_resources_ea(bus, dev, 0); 3970 3971 /* ATA devices needs special map treatment */ 3972 if ((pci_get_class(dev) == PCIC_STORAGE) && 3973 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 3974 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 3975 (!pci_read_config(dev, PCIR_BAR(0), 4) && 3976 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 3977 pci_ata_maps(bus, dev, rl, force, prefetchmask); 3978 else 3979 for (i = 0; i < cfg->nummaps;) { 3980 /* Skip resources already managed by EA */ 3981 if ((resource_list_find(rl, SYS_RES_MEMORY, PCIR_BAR(i)) != NULL) || 3982 (resource_list_find(rl, SYS_RES_IOPORT, PCIR_BAR(i)) != NULL) || 3983 pci_ea_is_enabled(dev, PCIR_BAR(i))) { 3984 i++; 3985 continue; 3986 } 3987 3988 /* 3989 * Skip quirked resources. 3990 */ 3991 for (q = &pci_quirks[0]; q->devid != 0; q++) 3992 if (q->devid == devid && 3993 q->type == PCI_QUIRK_UNMAP_REG && 3994 q->arg1 == PCIR_BAR(i)) 3995 break; 3996 if (q->devid != 0) { 3997 i++; 3998 continue; 3999 } 4000 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force, 4001 prefetchmask & (1 << i)); 4002 } 4003 4004 /* 4005 * Add additional, quirked resources. 4006 */ 4007 for (q = &pci_quirks[0]; q->devid != 0; q++) 4008 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) 4009 pci_add_map(bus, dev, q->arg1, rl, force, 0); 4010 4011 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 4012 #ifdef __PCI_REROUTE_INTERRUPT 4013 /* 4014 * Try to re-route interrupts. Sometimes the BIOS or 4015 * firmware may leave bogus values in these registers. 4016 * If the re-route fails, then just stick with what we 4017 * have. 4018 */ 4019 pci_assign_interrupt(bus, dev, 1); 4020 #else 4021 pci_assign_interrupt(bus, dev, 0); 4022 #endif 4023 } 4024 4025 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS && 4026 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) { 4027 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI) 4028 xhci_early_takeover(dev); 4029 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI) 4030 ehci_early_takeover(dev); 4031 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI) 4032 ohci_early_takeover(dev); 4033 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI) 4034 uhci_early_takeover(dev); 4035 } 4036 4037 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 4038 /* 4039 * Reserve resources for secondary bus ranges behind bridge 4040 * devices. 4041 */ 4042 pci_reserve_secbus(bus, dev, cfg, rl); 4043 #endif 4044 } 4045 4046 static struct pci_devinfo * 4047 pci_identify_function(device_t pcib, device_t dev, int domain, int busno, 4048 int slot, int func) 4049 { 4050 struct pci_devinfo *dinfo; 4051 4052 dinfo = pci_read_device(pcib, dev, domain, busno, slot, func); 4053 if (dinfo != NULL) 4054 pci_add_child(dev, dinfo); 4055 4056 return (dinfo); 4057 } 4058 4059 void 4060 pci_add_children(device_t dev, int domain, int busno) 4061 { 4062 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4063 device_t pcib = device_get_parent(dev); 4064 struct pci_devinfo *dinfo; 4065 int maxslots; 4066 int s, f, pcifunchigh; 4067 uint8_t hdrtype; 4068 int first_func; 4069 4070 /* 4071 * Try to detect a device at slot 0, function 0. If it exists, try to 4072 * enable ARI. We must enable ARI before detecting the rest of the 4073 * functions on this bus as ARI changes the set of slots and functions 4074 * that are legal on this bus. 4075 */ 4076 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0); 4077 if (dinfo != NULL && pci_enable_ari) 4078 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); 4079 4080 /* 4081 * Start looking for new devices on slot 0 at function 1 because we 4082 * just identified the device at slot 0, function 0. 4083 */ 4084 first_func = 1; 4085 4086 maxslots = PCIB_MAXSLOTS(pcib); 4087 for (s = 0; s <= maxslots; s++, first_func = 0) { 4088 pcifunchigh = 0; 4089 f = 0; 4090 DELAY(1); 4091 hdrtype = REG(PCIR_HDRTYPE, 1); 4092 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4093 continue; 4094 if (hdrtype & PCIM_MFDEV) 4095 pcifunchigh = PCIB_MAXFUNCS(pcib); 4096 for (f = first_func; f <= pcifunchigh; f++) 4097 pci_identify_function(pcib, dev, domain, busno, s, f); 4098 } 4099 #undef REG 4100 } 4101 4102 int 4103 pci_rescan_method(device_t dev) 4104 { 4105 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4106 device_t pcib = device_get_parent(dev); 4107 device_t child, *devlist, *unchanged; 4108 int devcount, error, i, j, maxslots, oldcount; 4109 int busno, domain, s, f, pcifunchigh; 4110 uint8_t hdrtype; 4111 4112 /* No need to check for ARI on a rescan. */ 4113 error = device_get_children(dev, &devlist, &devcount); 4114 if (error) 4115 return (error); 4116 if (devcount != 0) { 4117 unchanged = malloc(devcount * sizeof(device_t), M_TEMP, 4118 M_NOWAIT | M_ZERO); 4119 if (unchanged == NULL) { 4120 free(devlist, M_TEMP); 4121 return (ENOMEM); 4122 } 4123 } else 4124 unchanged = NULL; 4125 4126 domain = pcib_get_domain(dev); 4127 busno = pcib_get_bus(dev); 4128 maxslots = PCIB_MAXSLOTS(pcib); 4129 for (s = 0; s <= maxslots; s++) { 4130 /* If function 0 is not present, skip to the next slot. */ 4131 f = 0; 4132 if (REG(PCIR_VENDOR, 2) == 0xffff) 4133 continue; 4134 pcifunchigh = 0; 4135 hdrtype = REG(PCIR_HDRTYPE, 1); 4136 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4137 continue; 4138 if (hdrtype & PCIM_MFDEV) 4139 pcifunchigh = PCIB_MAXFUNCS(pcib); 4140 for (f = 0; f <= pcifunchigh; f++) { 4141 if (REG(PCIR_VENDOR, 2) == 0xffff) 4142 continue; 4143 4144 /* 4145 * Found a valid function. Check if a 4146 * device_t for this device already exists. 4147 */ 4148 for (i = 0; i < devcount; i++) { 4149 child = devlist[i]; 4150 if (child == NULL) 4151 continue; 4152 if (pci_get_slot(child) == s && 4153 pci_get_function(child) == f) { 4154 unchanged[i] = child; 4155 goto next_func; 4156 } 4157 } 4158 4159 pci_identify_function(pcib, dev, domain, busno, s, f); 4160 next_func:; 4161 } 4162 } 4163 4164 /* Remove devices that are no longer present. */ 4165 for (i = 0; i < devcount; i++) { 4166 if (unchanged[i] != NULL) 4167 continue; 4168 device_delete_child(dev, devlist[i]); 4169 } 4170 4171 free(devlist, M_TEMP); 4172 oldcount = devcount; 4173 4174 /* Try to attach the devices just added. */ 4175 error = device_get_children(dev, &devlist, &devcount); 4176 if (error) { 4177 free(unchanged, M_TEMP); 4178 return (error); 4179 } 4180 4181 for (i = 0; i < devcount; i++) { 4182 for (j = 0; j < oldcount; j++) { 4183 if (devlist[i] == unchanged[j]) 4184 goto next_device; 4185 } 4186 4187 device_probe_and_attach(devlist[i]); 4188 next_device:; 4189 } 4190 4191 free(unchanged, M_TEMP); 4192 free(devlist, M_TEMP); 4193 return (0); 4194 #undef REG 4195 } 4196 4197 #ifdef PCI_IOV 4198 device_t 4199 pci_add_iov_child(device_t bus, device_t pf, uint16_t rid, uint16_t vid, 4200 uint16_t did) 4201 { 4202 struct pci_devinfo *vf_dinfo; 4203 device_t pcib; 4204 int busno, slot, func; 4205 4206 pcib = device_get_parent(bus); 4207 4208 PCIB_DECODE_RID(pcib, rid, &busno, &slot, &func); 4209 4210 vf_dinfo = pci_fill_devinfo(pcib, bus, pci_get_domain(pcib), busno, 4211 slot, func, vid, did); 4212 4213 vf_dinfo->cfg.flags |= PCICFG_VF; 4214 pci_add_child(bus, vf_dinfo); 4215 4216 return (vf_dinfo->cfg.dev); 4217 } 4218 4219 device_t 4220 pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid, 4221 uint16_t vid, uint16_t did) 4222 { 4223 4224 return (pci_add_iov_child(bus, pf, rid, vid, did)); 4225 } 4226 #endif 4227 4228 static void 4229 pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo) 4230 { 4231 int aer; 4232 uint32_t r; 4233 uint16_t r2; 4234 4235 if (dinfo->cfg.pcie.pcie_location != 0 && 4236 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) { 4237 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4238 PCIER_ROOT_CTL, 2); 4239 r2 &= ~(PCIEM_ROOT_CTL_SERR_CORR | 4240 PCIEM_ROOT_CTL_SERR_NONFATAL | PCIEM_ROOT_CTL_SERR_FATAL); 4241 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4242 PCIER_ROOT_CTL, r2, 2); 4243 } 4244 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 4245 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 4246 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 4247 if (r != 0 && bootverbose) { 4248 pci_printf(&dinfo->cfg, 4249 "clearing AER UC 0x%08x -> 0x%08x\n", 4250 r, pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4251 4)); 4252 } 4253 4254 r = pci_read_config(dev, aer + PCIR_AER_UC_MASK, 4); 4255 r &= ~(PCIM_AER_UC_TRAINING_ERROR | 4256 PCIM_AER_UC_DL_PROTOCOL_ERROR | 4257 PCIM_AER_UC_SURPRISE_LINK_DOWN | 4258 PCIM_AER_UC_POISONED_TLP | 4259 PCIM_AER_UC_FC_PROTOCOL_ERROR | 4260 PCIM_AER_UC_COMPLETION_TIMEOUT | 4261 PCIM_AER_UC_COMPLETER_ABORT | 4262 PCIM_AER_UC_UNEXPECTED_COMPLETION | 4263 PCIM_AER_UC_RECEIVER_OVERFLOW | 4264 PCIM_AER_UC_MALFORMED_TLP | 4265 PCIM_AER_UC_ECRC_ERROR | 4266 PCIM_AER_UC_UNSUPPORTED_REQUEST | 4267 PCIM_AER_UC_ACS_VIOLATION | 4268 PCIM_AER_UC_INTERNAL_ERROR | 4269 PCIM_AER_UC_MC_BLOCKED_TLP | 4270 PCIM_AER_UC_ATOMIC_EGRESS_BLK | 4271 PCIM_AER_UC_TLP_PREFIX_BLOCKED); 4272 pci_write_config(dev, aer + PCIR_AER_UC_MASK, r, 4); 4273 4274 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 4275 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 4276 if (r != 0 && bootverbose) { 4277 pci_printf(&dinfo->cfg, 4278 "clearing AER COR 0x%08x -> 0x%08x\n", 4279 r, pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4280 4)); 4281 } 4282 4283 r = pci_read_config(dev, aer + PCIR_AER_COR_MASK, 4); 4284 r &= ~(PCIM_AER_COR_RECEIVER_ERROR | 4285 PCIM_AER_COR_BAD_TLP | 4286 PCIM_AER_COR_BAD_DLLP | 4287 PCIM_AER_COR_REPLAY_ROLLOVER | 4288 PCIM_AER_COR_REPLAY_TIMEOUT | 4289 PCIM_AER_COR_ADVISORY_NF_ERROR | 4290 PCIM_AER_COR_INTERNAL_ERROR | 4291 PCIM_AER_COR_HEADER_LOG_OVFLOW); 4292 pci_write_config(dev, aer + PCIR_AER_COR_MASK, r, 4); 4293 4294 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4295 PCIER_DEVICE_CTL, 2); 4296 r |= PCIEM_CTL_COR_ENABLE | PCIEM_CTL_NFER_ENABLE | 4297 PCIEM_CTL_FER_ENABLE | PCIEM_CTL_URR_ENABLE; 4298 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4299 PCIER_DEVICE_CTL, r, 2); 4300 } 4301 } 4302 4303 void 4304 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 4305 { 4306 device_t dev; 4307 4308 dinfo->cfg.dev = dev = device_add_child(bus, NULL, -1); 4309 device_set_ivars(dev, dinfo); 4310 resource_list_init(&dinfo->resources); 4311 pci_cfg_save(dev, dinfo, 0); 4312 pci_cfg_restore(dev, dinfo); 4313 pci_print_verbose(dinfo); 4314 pci_add_resources(bus, dev, 0, 0); 4315 pci_child_added(dinfo->cfg.dev); 4316 4317 if (pci_clear_aer_on_attach) 4318 pci_add_child_clear_aer(dev, dinfo); 4319 4320 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev); 4321 } 4322 4323 void 4324 pci_child_added_method(device_t dev, device_t child) 4325 { 4326 4327 } 4328 4329 static int 4330 pci_probe(device_t dev) 4331 { 4332 4333 device_set_desc(dev, "PCI bus"); 4334 4335 /* Allow other subclasses to override this driver. */ 4336 return (BUS_PROBE_GENERIC); 4337 } 4338 4339 int 4340 pci_attach_common(device_t dev) 4341 { 4342 struct pci_softc *sc; 4343 int busno, domain; 4344 #ifdef PCI_RES_BUS 4345 int rid; 4346 #endif 4347 4348 sc = device_get_softc(dev); 4349 domain = pcib_get_domain(dev); 4350 busno = pcib_get_bus(dev); 4351 #ifdef PCI_RES_BUS 4352 rid = 0; 4353 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, 4354 1, 0); 4355 if (sc->sc_bus == NULL) { 4356 device_printf(dev, "failed to allocate bus number\n"); 4357 return (ENXIO); 4358 } 4359 #endif 4360 if (bootverbose) 4361 device_printf(dev, "domain=%d, physical bus=%d\n", 4362 domain, busno); 4363 sc->sc_dma_tag = bus_get_dma_tag(dev); 4364 return (0); 4365 } 4366 4367 int 4368 pci_attach(device_t dev) 4369 { 4370 int busno, domain, error; 4371 4372 error = pci_attach_common(dev); 4373 if (error) 4374 return (error); 4375 4376 /* 4377 * Since there can be multiple independently numbered PCI 4378 * buses on systems with multiple PCI domains, we can't use 4379 * the unit number to decide which bus we are probing. We ask 4380 * the parent pcib what our domain and bus numbers are. 4381 */ 4382 domain = pcib_get_domain(dev); 4383 busno = pcib_get_bus(dev); 4384 pci_add_children(dev, domain, busno); 4385 return (bus_generic_attach(dev)); 4386 } 4387 4388 int 4389 pci_detach(device_t dev) 4390 { 4391 #ifdef PCI_RES_BUS 4392 struct pci_softc *sc; 4393 #endif 4394 int error; 4395 4396 error = bus_generic_detach(dev); 4397 if (error) 4398 return (error); 4399 #ifdef PCI_RES_BUS 4400 sc = device_get_softc(dev); 4401 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus); 4402 if (error) 4403 return (error); 4404 #endif 4405 return (device_delete_children(dev)); 4406 } 4407 4408 static void 4409 pci_hint_device_unit(device_t dev, device_t child, const char *name, int *unitp) 4410 { 4411 int line, unit; 4412 const char *at; 4413 char me1[24], me2[32]; 4414 uint8_t b, s, f; 4415 uint32_t d; 4416 4417 d = pci_get_domain(child); 4418 b = pci_get_bus(child); 4419 s = pci_get_slot(child); 4420 f = pci_get_function(child); 4421 snprintf(me1, sizeof(me1), "pci%u:%u:%u", b, s, f); 4422 snprintf(me2, sizeof(me2), "pci%u:%u:%u:%u", d, b, s, f); 4423 line = 0; 4424 while (resource_find_dev(&line, name, &unit, "at", NULL) == 0) { 4425 resource_string_value(name, unit, "at", &at); 4426 if (strcmp(at, me1) != 0 && strcmp(at, me2) != 0) 4427 continue; /* No match, try next candidate */ 4428 *unitp = unit; 4429 return; 4430 } 4431 } 4432 4433 static void 4434 pci_set_power_child(device_t dev, device_t child, int state) 4435 { 4436 device_t pcib; 4437 int dstate; 4438 4439 /* 4440 * Set the device to the given state. If the firmware suggests 4441 * a different power state, use it instead. If power management 4442 * is not present, the firmware is responsible for managing 4443 * device power. Skip children who aren't attached since they 4444 * are handled separately. 4445 */ 4446 pcib = device_get_parent(dev); 4447 dstate = state; 4448 if (device_is_attached(child) && 4449 PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0) 4450 pci_set_powerstate(child, dstate); 4451 } 4452 4453 int 4454 pci_suspend_child(device_t dev, device_t child) 4455 { 4456 struct pci_devinfo *dinfo; 4457 struct resource_list_entry *rle; 4458 int error; 4459 4460 dinfo = device_get_ivars(child); 4461 4462 /* 4463 * Save the PCI configuration space for the child and set the 4464 * device in the appropriate power state for this sleep state. 4465 */ 4466 pci_cfg_save(child, dinfo, 0); 4467 4468 /* Suspend devices before potentially powering them down. */ 4469 error = bus_generic_suspend_child(dev, child); 4470 4471 if (error) 4472 return (error); 4473 4474 if (pci_do_power_suspend) { 4475 /* 4476 * Make sure this device's interrupt handler is not invoked 4477 * in the case the device uses a shared interrupt that can 4478 * be raised by some other device. 4479 * This is applicable only to regular (legacy) PCI interrupts 4480 * as MSI/MSI-X interrupts are never shared. 4481 */ 4482 rle = resource_list_find(&dinfo->resources, 4483 SYS_RES_IRQ, 0); 4484 if (rle != NULL && rle->res != NULL) 4485 (void)bus_suspend_intr(child, rle->res); 4486 pci_set_power_child(dev, child, PCI_POWERSTATE_D3); 4487 } 4488 4489 return (0); 4490 } 4491 4492 int 4493 pci_resume_child(device_t dev, device_t child) 4494 { 4495 struct pci_devinfo *dinfo; 4496 struct resource_list_entry *rle; 4497 4498 if (pci_do_power_resume) 4499 pci_set_power_child(dev, child, PCI_POWERSTATE_D0); 4500 4501 dinfo = device_get_ivars(child); 4502 pci_cfg_restore(child, dinfo); 4503 if (!device_is_attached(child)) 4504 pci_cfg_save(child, dinfo, 1); 4505 4506 bus_generic_resume_child(dev, child); 4507 4508 /* 4509 * Allow interrupts only after fully resuming the driver and hardware. 4510 */ 4511 if (pci_do_power_suspend) { 4512 /* See pci_suspend_child for details. */ 4513 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 4514 if (rle != NULL && rle->res != NULL) 4515 (void)bus_resume_intr(child, rle->res); 4516 } 4517 4518 return (0); 4519 } 4520 4521 int 4522 pci_resume(device_t dev) 4523 { 4524 device_t child, *devlist; 4525 int error, i, numdevs; 4526 4527 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 4528 return (error); 4529 4530 /* 4531 * Resume critical devices first, then everything else later. 4532 */ 4533 for (i = 0; i < numdevs; i++) { 4534 child = devlist[i]; 4535 switch (pci_get_class(child)) { 4536 case PCIC_DISPLAY: 4537 case PCIC_MEMORY: 4538 case PCIC_BRIDGE: 4539 case PCIC_BASEPERIPH: 4540 BUS_RESUME_CHILD(dev, child); 4541 break; 4542 } 4543 } 4544 for (i = 0; i < numdevs; i++) { 4545 child = devlist[i]; 4546 switch (pci_get_class(child)) { 4547 case PCIC_DISPLAY: 4548 case PCIC_MEMORY: 4549 case PCIC_BRIDGE: 4550 case PCIC_BASEPERIPH: 4551 break; 4552 default: 4553 BUS_RESUME_CHILD(dev, child); 4554 } 4555 } 4556 free(devlist, M_TEMP); 4557 return (0); 4558 } 4559 4560 static void 4561 pci_load_vendor_data(void) 4562 { 4563 caddr_t data; 4564 void *ptr; 4565 size_t sz; 4566 4567 data = preload_search_by_type("pci_vendor_data"); 4568 if (data != NULL) { 4569 ptr = preload_fetch_addr(data); 4570 sz = preload_fetch_size(data); 4571 if (ptr != NULL && sz != 0) { 4572 pci_vendordata = ptr; 4573 pci_vendordata_size = sz; 4574 /* terminate the database */ 4575 pci_vendordata[pci_vendordata_size] = '\n'; 4576 } 4577 } 4578 } 4579 4580 void 4581 pci_driver_added(device_t dev, driver_t *driver) 4582 { 4583 int numdevs; 4584 device_t *devlist; 4585 device_t child; 4586 struct pci_devinfo *dinfo; 4587 int i; 4588 4589 if (bootverbose) 4590 device_printf(dev, "driver added\n"); 4591 DEVICE_IDENTIFY(driver, dev); 4592 if (device_get_children(dev, &devlist, &numdevs) != 0) 4593 return; 4594 for (i = 0; i < numdevs; i++) { 4595 child = devlist[i]; 4596 if (device_get_state(child) != DS_NOTPRESENT) 4597 continue; 4598 dinfo = device_get_ivars(child); 4599 pci_print_verbose(dinfo); 4600 if (bootverbose) 4601 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); 4602 pci_cfg_restore(child, dinfo); 4603 if (device_probe_and_attach(child) != 0) 4604 pci_child_detached(dev, child); 4605 } 4606 free(devlist, M_TEMP); 4607 } 4608 4609 int 4610 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, 4611 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep) 4612 { 4613 struct pci_devinfo *dinfo; 4614 struct msix_table_entry *mte; 4615 struct msix_vector *mv; 4616 uint64_t addr; 4617 uint32_t data; 4618 void *cookie; 4619 int error, rid; 4620 4621 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr, 4622 arg, &cookie); 4623 if (error) 4624 return (error); 4625 4626 /* If this is not a direct child, just bail out. */ 4627 if (device_get_parent(child) != dev) { 4628 *cookiep = cookie; 4629 return(0); 4630 } 4631 4632 rid = rman_get_rid(irq); 4633 if (rid == 0) { 4634 /* Make sure that INTx is enabled */ 4635 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4636 } else { 4637 /* 4638 * Check to see if the interrupt is MSI or MSI-X. 4639 * Ask our parent to map the MSI and give 4640 * us the address and data register values. 4641 * If we fail for some reason, teardown the 4642 * interrupt handler. 4643 */ 4644 dinfo = device_get_ivars(child); 4645 if (dinfo->cfg.msi.msi_alloc > 0) { 4646 if (dinfo->cfg.msi.msi_addr == 0) { 4647 KASSERT(dinfo->cfg.msi.msi_handlers == 0, 4648 ("MSI has handlers, but vectors not mapped")); 4649 error = PCIB_MAP_MSI(device_get_parent(dev), 4650 child, rman_get_start(irq), &addr, &data); 4651 if (error) 4652 goto bad; 4653 dinfo->cfg.msi.msi_addr = addr; 4654 dinfo->cfg.msi.msi_data = data; 4655 } 4656 if (dinfo->cfg.msi.msi_handlers == 0) 4657 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, 4658 dinfo->cfg.msi.msi_data); 4659 dinfo->cfg.msi.msi_handlers++; 4660 } else { 4661 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4662 ("No MSI or MSI-X interrupts allocated")); 4663 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4664 ("MSI-X index too high")); 4665 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4666 KASSERT(mte->mte_vector != 0, ("no message vector")); 4667 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; 4668 KASSERT(mv->mv_irq == rman_get_start(irq), 4669 ("IRQ mismatch")); 4670 if (mv->mv_address == 0) { 4671 KASSERT(mte->mte_handlers == 0, 4672 ("MSI-X table entry has handlers, but vector not mapped")); 4673 error = PCIB_MAP_MSI(device_get_parent(dev), 4674 child, rman_get_start(irq), &addr, &data); 4675 if (error) 4676 goto bad; 4677 mv->mv_address = addr; 4678 mv->mv_data = data; 4679 } 4680 4681 /* 4682 * The MSIX table entry must be made valid by 4683 * incrementing the mte_handlers before 4684 * calling pci_enable_msix() and 4685 * pci_resume_msix(). Else the MSIX rewrite 4686 * table quirk will not work as expected. 4687 */ 4688 mte->mte_handlers++; 4689 if (mte->mte_handlers == 1) { 4690 pci_enable_msix(child, rid - 1, mv->mv_address, 4691 mv->mv_data); 4692 pci_unmask_msix(child, rid - 1); 4693 } 4694 } 4695 4696 /* 4697 * Make sure that INTx is disabled if we are using MSI/MSI-X, 4698 * unless the device is affected by PCI_QUIRK_MSI_INTX_BUG, 4699 * in which case we "enable" INTx so MSI/MSI-X actually works. 4700 */ 4701 if (!pci_has_quirk(pci_get_devid(child), 4702 PCI_QUIRK_MSI_INTX_BUG)) 4703 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4704 else 4705 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4706 bad: 4707 if (error) { 4708 (void)bus_generic_teardown_intr(dev, child, irq, 4709 cookie); 4710 return (error); 4711 } 4712 } 4713 *cookiep = cookie; 4714 return (0); 4715 } 4716 4717 int 4718 pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 4719 void *cookie) 4720 { 4721 struct msix_table_entry *mte; 4722 struct resource_list_entry *rle; 4723 struct pci_devinfo *dinfo; 4724 int error, rid; 4725 4726 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE)) 4727 return (EINVAL); 4728 4729 /* If this isn't a direct child, just bail out */ 4730 if (device_get_parent(child) != dev) 4731 return(bus_generic_teardown_intr(dev, child, irq, cookie)); 4732 4733 rid = rman_get_rid(irq); 4734 if (rid == 0) { 4735 /* Mask INTx */ 4736 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4737 } else { 4738 /* 4739 * Check to see if the interrupt is MSI or MSI-X. If so, 4740 * decrement the appropriate handlers count and mask the 4741 * MSI-X message, or disable MSI messages if the count 4742 * drops to 0. 4743 */ 4744 dinfo = device_get_ivars(child); 4745 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); 4746 if (rle->res != irq) 4747 return (EINVAL); 4748 if (dinfo->cfg.msi.msi_alloc > 0) { 4749 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, 4750 ("MSI-X index too high")); 4751 if (dinfo->cfg.msi.msi_handlers == 0) 4752 return (EINVAL); 4753 dinfo->cfg.msi.msi_handlers--; 4754 if (dinfo->cfg.msi.msi_handlers == 0) 4755 pci_disable_msi(child); 4756 } else { 4757 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4758 ("No MSI or MSI-X interrupts allocated")); 4759 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4760 ("MSI-X index too high")); 4761 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4762 if (mte->mte_handlers == 0) 4763 return (EINVAL); 4764 mte->mte_handlers--; 4765 if (mte->mte_handlers == 0) 4766 pci_mask_msix(child, rid - 1); 4767 } 4768 } 4769 error = bus_generic_teardown_intr(dev, child, irq, cookie); 4770 if (rid > 0) 4771 KASSERT(error == 0, 4772 ("%s: generic teardown failed for MSI/MSI-X", __func__)); 4773 return (error); 4774 } 4775 4776 int 4777 pci_print_child(device_t dev, device_t child) 4778 { 4779 struct pci_devinfo *dinfo; 4780 struct resource_list *rl; 4781 int retval = 0; 4782 4783 dinfo = device_get_ivars(child); 4784 rl = &dinfo->resources; 4785 4786 retval += bus_print_child_header(dev, child); 4787 4788 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#jx"); 4789 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 4790 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 4791 if (device_get_flags(dev)) 4792 retval += printf(" flags %#x", device_get_flags(dev)); 4793 4794 retval += printf(" at device %d.%d", pci_get_slot(child), 4795 pci_get_function(child)); 4796 4797 retval += bus_print_child_domain(dev, child); 4798 retval += bus_print_child_footer(dev, child); 4799 4800 return (retval); 4801 } 4802 4803 static const struct 4804 { 4805 int class; 4806 int subclass; 4807 int report; /* 0 = bootverbose, 1 = always */ 4808 const char *desc; 4809 } pci_nomatch_tab[] = { 4810 {PCIC_OLD, -1, 1, "old"}, 4811 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"}, 4812 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"}, 4813 {PCIC_STORAGE, -1, 1, "mass storage"}, 4814 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"}, 4815 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"}, 4816 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"}, 4817 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"}, 4818 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"}, 4819 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"}, 4820 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"}, 4821 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"}, 4822 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"}, 4823 {PCIC_NETWORK, -1, 1, "network"}, 4824 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"}, 4825 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"}, 4826 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"}, 4827 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"}, 4828 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"}, 4829 {PCIC_DISPLAY, -1, 1, "display"}, 4830 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"}, 4831 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"}, 4832 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"}, 4833 {PCIC_MULTIMEDIA, -1, 1, "multimedia"}, 4834 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"}, 4835 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"}, 4836 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"}, 4837 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"}, 4838 {PCIC_MEMORY, -1, 1, "memory"}, 4839 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"}, 4840 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"}, 4841 {PCIC_BRIDGE, -1, 1, "bridge"}, 4842 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"}, 4843 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"}, 4844 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"}, 4845 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"}, 4846 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"}, 4847 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"}, 4848 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"}, 4849 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"}, 4850 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"}, 4851 {PCIC_SIMPLECOMM, -1, 1, "simple comms"}, 4852 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */ 4853 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"}, 4854 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"}, 4855 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"}, 4856 {PCIC_BASEPERIPH, -1, 0, "base peripheral"}, 4857 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"}, 4858 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"}, 4859 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"}, 4860 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"}, 4861 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"}, 4862 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"}, 4863 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"}, 4864 {PCIC_INPUTDEV, -1, 1, "input device"}, 4865 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"}, 4866 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"}, 4867 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"}, 4868 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"}, 4869 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"}, 4870 {PCIC_DOCKING, -1, 1, "docking station"}, 4871 {PCIC_PROCESSOR, -1, 1, "processor"}, 4872 {PCIC_SERIALBUS, -1, 1, "serial bus"}, 4873 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"}, 4874 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"}, 4875 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"}, 4876 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"}, 4877 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"}, 4878 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"}, 4879 {PCIC_WIRELESS, -1, 1, "wireless controller"}, 4880 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"}, 4881 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"}, 4882 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"}, 4883 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"}, 4884 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"}, 4885 {PCIC_SATCOM, -1, 1, "satellite communication"}, 4886 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"}, 4887 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"}, 4888 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"}, 4889 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"}, 4890 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"}, 4891 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"}, 4892 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"}, 4893 {PCIC_DASP, -1, 0, "dasp"}, 4894 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"}, 4895 {PCIC_DASP, PCIS_DASP_PERFCNTRS, 1, "performance counters"}, 4896 {PCIC_DASP, PCIS_DASP_COMM_SYNC, 1, "communication synchronizer"}, 4897 {PCIC_DASP, PCIS_DASP_MGMT_CARD, 1, "signal processing management"}, 4898 {0, 0, 0, NULL} 4899 }; 4900 4901 void 4902 pci_probe_nomatch(device_t dev, device_t child) 4903 { 4904 int i, report; 4905 const char *cp, *scp; 4906 char *device; 4907 4908 /* 4909 * Look for a listing for this device in a loaded device database. 4910 */ 4911 report = 1; 4912 if ((device = pci_describe_device(child)) != NULL) { 4913 device_printf(dev, "<%s>", device); 4914 free(device, M_DEVBUF); 4915 } else { 4916 /* 4917 * Scan the class/subclass descriptions for a general 4918 * description. 4919 */ 4920 cp = "unknown"; 4921 scp = NULL; 4922 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 4923 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 4924 if (pci_nomatch_tab[i].subclass == -1) { 4925 cp = pci_nomatch_tab[i].desc; 4926 report = pci_nomatch_tab[i].report; 4927 } else if (pci_nomatch_tab[i].subclass == 4928 pci_get_subclass(child)) { 4929 scp = pci_nomatch_tab[i].desc; 4930 report = pci_nomatch_tab[i].report; 4931 } 4932 } 4933 } 4934 if (report || bootverbose) { 4935 device_printf(dev, "<%s%s%s>", 4936 cp ? cp : "", 4937 ((cp != NULL) && (scp != NULL)) ? ", " : "", 4938 scp ? scp : ""); 4939 } 4940 } 4941 if (report || bootverbose) { 4942 printf(" at device %d.%d (no driver attached)\n", 4943 pci_get_slot(child), pci_get_function(child)); 4944 } 4945 pci_cfg_save(child, device_get_ivars(child), 1); 4946 } 4947 4948 void 4949 pci_child_detached(device_t dev, device_t child) 4950 { 4951 struct pci_devinfo *dinfo; 4952 struct resource_list *rl; 4953 4954 dinfo = device_get_ivars(child); 4955 rl = &dinfo->resources; 4956 4957 /* 4958 * Have to deallocate IRQs before releasing any MSI messages and 4959 * have to release MSI messages before deallocating any memory 4960 * BARs. 4961 */ 4962 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0) 4963 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); 4964 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { 4965 pci_printf(&dinfo->cfg, "Device leaked MSI vectors\n"); 4966 (void)pci_release_msi(child); 4967 } 4968 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0) 4969 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); 4970 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0) 4971 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); 4972 #ifdef PCI_RES_BUS 4973 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0) 4974 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); 4975 #endif 4976 4977 pci_cfg_save(child, dinfo, 1); 4978 } 4979 4980 /* 4981 * Parse the PCI device database, if loaded, and return a pointer to a 4982 * description of the device. 4983 * 4984 * The database is flat text formatted as follows: 4985 * 4986 * Any line not in a valid format is ignored. 4987 * Lines are terminated with newline '\n' characters. 4988 * 4989 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 4990 * the vendor name. 4991 * 4992 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 4993 * - devices cannot be listed without a corresponding VENDOR line. 4994 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 4995 * another TAB, then the device name. 4996 */ 4997 4998 /* 4999 * Assuming (ptr) points to the beginning of a line in the database, 5000 * return the vendor or device and description of the next entry. 5001 * The value of (vendor) or (device) inappropriate for the entry type 5002 * is set to -1. Returns nonzero at the end of the database. 5003 * 5004 * Note that this is slightly unrobust in the face of corrupt data; 5005 * we attempt to safeguard against this by spamming the end of the 5006 * database with a newline when we initialise. 5007 */ 5008 static int 5009 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 5010 { 5011 char *cp = *ptr; 5012 int left; 5013 5014 *device = -1; 5015 *vendor = -1; 5016 **desc = '\0'; 5017 for (;;) { 5018 left = pci_vendordata_size - (cp - pci_vendordata); 5019 if (left <= 0) { 5020 *ptr = cp; 5021 return(1); 5022 } 5023 5024 /* vendor entry? */ 5025 if (*cp != '\t' && 5026 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 5027 break; 5028 /* device entry? */ 5029 if (*cp == '\t' && 5030 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 5031 break; 5032 5033 /* skip to next line */ 5034 while (*cp != '\n' && left > 0) { 5035 cp++; 5036 left--; 5037 } 5038 if (*cp == '\n') { 5039 cp++; 5040 left--; 5041 } 5042 } 5043 /* skip to next line */ 5044 while (*cp != '\n' && left > 0) { 5045 cp++; 5046 left--; 5047 } 5048 if (*cp == '\n' && left > 0) 5049 cp++; 5050 *ptr = cp; 5051 return(0); 5052 } 5053 5054 static char * 5055 pci_describe_device(device_t dev) 5056 { 5057 int vendor, device; 5058 char *desc, *vp, *dp, *line; 5059 5060 desc = vp = dp = NULL; 5061 5062 /* 5063 * If we have no vendor data, we can't do anything. 5064 */ 5065 if (pci_vendordata == NULL) 5066 goto out; 5067 5068 /* 5069 * Scan the vendor data looking for this device 5070 */ 5071 line = pci_vendordata; 5072 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5073 goto out; 5074 for (;;) { 5075 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 5076 goto out; 5077 if (vendor == pci_get_vendor(dev)) 5078 break; 5079 } 5080 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5081 goto out; 5082 for (;;) { 5083 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 5084 *dp = 0; 5085 break; 5086 } 5087 if (vendor != -1) { 5088 *dp = 0; 5089 break; 5090 } 5091 if (device == pci_get_device(dev)) 5092 break; 5093 } 5094 if (dp[0] == '\0') 5095 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 5096 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 5097 NULL) 5098 sprintf(desc, "%s, %s", vp, dp); 5099 out: 5100 if (vp != NULL) 5101 free(vp, M_DEVBUF); 5102 if (dp != NULL) 5103 free(dp, M_DEVBUF); 5104 return(desc); 5105 } 5106 5107 int 5108 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 5109 { 5110 struct pci_devinfo *dinfo; 5111 pcicfgregs *cfg; 5112 5113 dinfo = device_get_ivars(child); 5114 cfg = &dinfo->cfg; 5115 5116 switch (which) { 5117 case PCI_IVAR_ETHADDR: 5118 /* 5119 * The generic accessor doesn't deal with failure, so 5120 * we set the return value, then return an error. 5121 */ 5122 *((uint8_t **) result) = NULL; 5123 return (EINVAL); 5124 case PCI_IVAR_SUBVENDOR: 5125 *result = cfg->subvendor; 5126 break; 5127 case PCI_IVAR_SUBDEVICE: 5128 *result = cfg->subdevice; 5129 break; 5130 case PCI_IVAR_VENDOR: 5131 *result = cfg->vendor; 5132 break; 5133 case PCI_IVAR_DEVICE: 5134 *result = cfg->device; 5135 break; 5136 case PCI_IVAR_DEVID: 5137 *result = (cfg->device << 16) | cfg->vendor; 5138 break; 5139 case PCI_IVAR_CLASS: 5140 *result = cfg->baseclass; 5141 break; 5142 case PCI_IVAR_SUBCLASS: 5143 *result = cfg->subclass; 5144 break; 5145 case PCI_IVAR_PROGIF: 5146 *result = cfg->progif; 5147 break; 5148 case PCI_IVAR_REVID: 5149 *result = cfg->revid; 5150 break; 5151 case PCI_IVAR_INTPIN: 5152 *result = cfg->intpin; 5153 break; 5154 case PCI_IVAR_IRQ: 5155 *result = cfg->intline; 5156 break; 5157 case PCI_IVAR_DOMAIN: 5158 *result = cfg->domain; 5159 break; 5160 case PCI_IVAR_BUS: 5161 *result = cfg->bus; 5162 break; 5163 case PCI_IVAR_SLOT: 5164 *result = cfg->slot; 5165 break; 5166 case PCI_IVAR_FUNCTION: 5167 *result = cfg->func; 5168 break; 5169 case PCI_IVAR_CMDREG: 5170 *result = cfg->cmdreg; 5171 break; 5172 case PCI_IVAR_CACHELNSZ: 5173 *result = cfg->cachelnsz; 5174 break; 5175 case PCI_IVAR_MINGNT: 5176 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5177 *result = -1; 5178 return (EINVAL); 5179 } 5180 *result = cfg->mingnt; 5181 break; 5182 case PCI_IVAR_MAXLAT: 5183 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5184 *result = -1; 5185 return (EINVAL); 5186 } 5187 *result = cfg->maxlat; 5188 break; 5189 case PCI_IVAR_LATTIMER: 5190 *result = cfg->lattimer; 5191 break; 5192 default: 5193 return (ENOENT); 5194 } 5195 return (0); 5196 } 5197 5198 int 5199 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 5200 { 5201 struct pci_devinfo *dinfo; 5202 5203 dinfo = device_get_ivars(child); 5204 5205 switch (which) { 5206 case PCI_IVAR_INTPIN: 5207 dinfo->cfg.intpin = value; 5208 return (0); 5209 case PCI_IVAR_ETHADDR: 5210 case PCI_IVAR_SUBVENDOR: 5211 case PCI_IVAR_SUBDEVICE: 5212 case PCI_IVAR_VENDOR: 5213 case PCI_IVAR_DEVICE: 5214 case PCI_IVAR_DEVID: 5215 case PCI_IVAR_CLASS: 5216 case PCI_IVAR_SUBCLASS: 5217 case PCI_IVAR_PROGIF: 5218 case PCI_IVAR_REVID: 5219 case PCI_IVAR_IRQ: 5220 case PCI_IVAR_DOMAIN: 5221 case PCI_IVAR_BUS: 5222 case PCI_IVAR_SLOT: 5223 case PCI_IVAR_FUNCTION: 5224 return (EINVAL); /* disallow for now */ 5225 5226 default: 5227 return (ENOENT); 5228 } 5229 } 5230 5231 #include "opt_ddb.h" 5232 #ifdef DDB 5233 #include <ddb/ddb.h> 5234 #include <sys/cons.h> 5235 5236 /* 5237 * List resources based on pci map registers, used for within ddb 5238 */ 5239 5240 DB_SHOW_COMMAND(pciregs, db_pci_dump) 5241 { 5242 struct pci_devinfo *dinfo; 5243 struct devlist *devlist_head; 5244 struct pci_conf *p; 5245 const char *name; 5246 int i, error, none_count; 5247 5248 none_count = 0; 5249 /* get the head of the device queue */ 5250 devlist_head = &pci_devq; 5251 5252 /* 5253 * Go through the list of devices and print out devices 5254 */ 5255 for (error = 0, i = 0, 5256 dinfo = STAILQ_FIRST(devlist_head); 5257 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 5258 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 5259 /* Populate pd_name and pd_unit */ 5260 name = NULL; 5261 if (dinfo->cfg.dev) 5262 name = device_get_name(dinfo->cfg.dev); 5263 5264 p = &dinfo->conf; 5265 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x " 5266 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 5267 (name && *name) ? name : "none", 5268 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 5269 none_count++, 5270 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, 5271 p->pc_sel.pc_func, (p->pc_class << 16) | 5272 (p->pc_subclass << 8) | p->pc_progif, 5273 (p->pc_subdevice << 16) | p->pc_subvendor, 5274 (p->pc_device << 16) | p->pc_vendor, 5275 p->pc_revid, p->pc_hdr); 5276 } 5277 } 5278 #endif /* DDB */ 5279 5280 static struct resource * 5281 pci_reserve_map(device_t dev, device_t child, int type, int *rid, 5282 rman_res_t start, rman_res_t end, rman_res_t count, u_int num, 5283 u_int flags) 5284 { 5285 struct pci_devinfo *dinfo = device_get_ivars(child); 5286 struct resource_list *rl = &dinfo->resources; 5287 struct resource *res; 5288 struct pci_map *pm; 5289 uint16_t cmd; 5290 pci_addr_t map, testval; 5291 int mapsize; 5292 5293 res = NULL; 5294 5295 /* If rid is managed by EA, ignore it */ 5296 if (pci_ea_is_enabled(child, *rid)) 5297 goto out; 5298 5299 pm = pci_find_bar(child, *rid); 5300 if (pm != NULL) { 5301 /* This is a BAR that we failed to allocate earlier. */ 5302 mapsize = pm->pm_size; 5303 map = pm->pm_value; 5304 } else { 5305 /* 5306 * Weed out the bogons, and figure out how large the 5307 * BAR/map is. BARs that read back 0 here are bogus 5308 * and unimplemented. Note: atapci in legacy mode are 5309 * special and handled elsewhere in the code. If you 5310 * have a atapci device in legacy mode and it fails 5311 * here, that other code is broken. 5312 */ 5313 pci_read_bar(child, *rid, &map, &testval, NULL); 5314 5315 /* 5316 * Determine the size of the BAR and ignore BARs with a size 5317 * of 0. Device ROM BARs use a different mask value. 5318 */ 5319 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) 5320 mapsize = pci_romsize(testval); 5321 else 5322 mapsize = pci_mapsize(testval); 5323 if (mapsize == 0) 5324 goto out; 5325 pm = pci_add_bar(child, *rid, map, mapsize); 5326 } 5327 5328 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { 5329 if (type != SYS_RES_MEMORY) { 5330 if (bootverbose) 5331 device_printf(dev, 5332 "child %s requested type %d for rid %#x," 5333 " but the BAR says it is an memio\n", 5334 device_get_nameunit(child), type, *rid); 5335 goto out; 5336 } 5337 } else { 5338 if (type != SYS_RES_IOPORT) { 5339 if (bootverbose) 5340 device_printf(dev, 5341 "child %s requested type %d for rid %#x," 5342 " but the BAR says it is an ioport\n", 5343 device_get_nameunit(child), type, *rid); 5344 goto out; 5345 } 5346 } 5347 5348 /* 5349 * For real BARs, we need to override the size that 5350 * the driver requests, because that's what the BAR 5351 * actually uses and we would otherwise have a 5352 * situation where we might allocate the excess to 5353 * another driver, which won't work. 5354 */ 5355 count = ((pci_addr_t)1 << mapsize) * num; 5356 if (RF_ALIGNMENT(flags) < mapsize) 5357 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 5358 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH)) 5359 flags |= RF_PREFETCHABLE; 5360 5361 /* 5362 * Allocate enough resource, and then write back the 5363 * appropriate BAR for that resource. 5364 */ 5365 resource_list_add(rl, type, *rid, start, end, count); 5366 res = resource_list_reserve(rl, dev, child, type, rid, start, end, 5367 count, flags & ~RF_ACTIVE); 5368 if (res == NULL) { 5369 resource_list_delete(rl, type, *rid); 5370 device_printf(child, 5371 "%#jx bytes of rid %#x res %d failed (%#jx, %#jx).\n", 5372 count, *rid, type, start, end); 5373 goto out; 5374 } 5375 if (bootverbose) 5376 device_printf(child, 5377 "Lazy allocation of %#jx bytes rid %#x type %d at %#jx\n", 5378 count, *rid, type, rman_get_start(res)); 5379 5380 /* Disable decoding via the CMD register before updating the BAR */ 5381 cmd = pci_read_config(child, PCIR_COMMAND, 2); 5382 pci_write_config(child, PCIR_COMMAND, 5383 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 5384 5385 map = rman_get_start(res); 5386 pci_write_bar(child, pm, map); 5387 5388 /* Restore the original value of the CMD register */ 5389 pci_write_config(child, PCIR_COMMAND, cmd, 2); 5390 out: 5391 return (res); 5392 } 5393 5394 struct resource * 5395 pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid, 5396 rman_res_t start, rman_res_t end, rman_res_t count, u_long num, 5397 u_int flags) 5398 { 5399 struct pci_devinfo *dinfo; 5400 struct resource_list *rl; 5401 struct resource_list_entry *rle; 5402 struct resource *res; 5403 pcicfgregs *cfg; 5404 5405 /* 5406 * Perform lazy resource allocation 5407 */ 5408 dinfo = device_get_ivars(child); 5409 rl = &dinfo->resources; 5410 cfg = &dinfo->cfg; 5411 switch (type) { 5412 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 5413 case PCI_RES_BUS: 5414 return (pci_alloc_secbus(dev, child, rid, start, end, count, 5415 flags)); 5416 #endif 5417 case SYS_RES_IRQ: 5418 /* 5419 * Can't alloc legacy interrupt once MSI messages have 5420 * been allocated. 5421 */ 5422 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 5423 cfg->msix.msix_alloc > 0)) 5424 return (NULL); 5425 5426 /* 5427 * If the child device doesn't have an interrupt 5428 * routed and is deserving of an interrupt, try to 5429 * assign it one. 5430 */ 5431 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 5432 (cfg->intpin != 0)) 5433 pci_assign_interrupt(dev, child, 0); 5434 break; 5435 case SYS_RES_IOPORT: 5436 case SYS_RES_MEMORY: 5437 #ifdef NEW_PCIB 5438 /* 5439 * PCI-PCI bridge I/O window resources are not BARs. 5440 * For those allocations just pass the request up the 5441 * tree. 5442 */ 5443 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { 5444 switch (*rid) { 5445 case PCIR_IOBASEL_1: 5446 case PCIR_MEMBASE_1: 5447 case PCIR_PMBASEL_1: 5448 /* 5449 * XXX: Should we bother creating a resource 5450 * list entry? 5451 */ 5452 return (bus_generic_alloc_resource(dev, child, 5453 type, rid, start, end, count, flags)); 5454 } 5455 } 5456 #endif 5457 /* Reserve resources for this BAR if needed. */ 5458 rle = resource_list_find(rl, type, *rid); 5459 if (rle == NULL) { 5460 res = pci_reserve_map(dev, child, type, rid, start, end, 5461 count, num, flags); 5462 if (res == NULL) 5463 return (NULL); 5464 } 5465 } 5466 return (resource_list_alloc(rl, dev, child, type, rid, 5467 start, end, count, flags)); 5468 } 5469 5470 struct resource * 5471 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 5472 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 5473 { 5474 #ifdef PCI_IOV 5475 struct pci_devinfo *dinfo; 5476 #endif 5477 5478 if (device_get_parent(child) != dev) 5479 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 5480 type, rid, start, end, count, flags)); 5481 5482 #ifdef PCI_IOV 5483 dinfo = device_get_ivars(child); 5484 if (dinfo->cfg.flags & PCICFG_VF) { 5485 switch (type) { 5486 /* VFs can't have I/O BARs. */ 5487 case SYS_RES_IOPORT: 5488 return (NULL); 5489 case SYS_RES_MEMORY: 5490 return (pci_vf_alloc_mem_resource(dev, child, rid, 5491 start, end, count, flags)); 5492 } 5493 5494 /* Fall through for other types of resource allocations. */ 5495 } 5496 #endif 5497 5498 return (pci_alloc_multi_resource(dev, child, type, rid, start, end, 5499 count, 1, flags)); 5500 } 5501 5502 int 5503 pci_release_resource(device_t dev, device_t child, int type, int rid, 5504 struct resource *r) 5505 { 5506 struct pci_devinfo *dinfo; 5507 struct resource_list *rl; 5508 pcicfgregs *cfg; 5509 5510 if (device_get_parent(child) != dev) 5511 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 5512 type, rid, r)); 5513 5514 dinfo = device_get_ivars(child); 5515 cfg = &dinfo->cfg; 5516 5517 #ifdef PCI_IOV 5518 if (dinfo->cfg.flags & PCICFG_VF) { 5519 switch (type) { 5520 /* VFs can't have I/O BARs. */ 5521 case SYS_RES_IOPORT: 5522 return (EDOOFUS); 5523 case SYS_RES_MEMORY: 5524 return (pci_vf_release_mem_resource(dev, child, rid, 5525 r)); 5526 } 5527 5528 /* Fall through for other types of resource allocations. */ 5529 } 5530 #endif 5531 5532 #ifdef NEW_PCIB 5533 /* 5534 * PCI-PCI bridge I/O window resources are not BARs. For 5535 * those allocations just pass the request up the tree. 5536 */ 5537 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && 5538 (type == SYS_RES_IOPORT || type == SYS_RES_MEMORY)) { 5539 switch (rid) { 5540 case PCIR_IOBASEL_1: 5541 case PCIR_MEMBASE_1: 5542 case PCIR_PMBASEL_1: 5543 return (bus_generic_release_resource(dev, child, type, 5544 rid, r)); 5545 } 5546 } 5547 #endif 5548 5549 rl = &dinfo->resources; 5550 return (resource_list_release(rl, dev, child, type, rid, r)); 5551 } 5552 5553 int 5554 pci_activate_resource(device_t dev, device_t child, int type, int rid, 5555 struct resource *r) 5556 { 5557 struct pci_devinfo *dinfo; 5558 int error; 5559 5560 error = bus_generic_activate_resource(dev, child, type, rid, r); 5561 if (error) 5562 return (error); 5563 5564 /* Enable decoding in the command register when activating BARs. */ 5565 if (device_get_parent(child) == dev) { 5566 /* Device ROMs need their decoding explicitly enabled. */ 5567 dinfo = device_get_ivars(child); 5568 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5569 pci_write_bar(child, pci_find_bar(child, rid), 5570 rman_get_start(r) | PCIM_BIOS_ENABLE); 5571 switch (type) { 5572 case SYS_RES_IOPORT: 5573 case SYS_RES_MEMORY: 5574 error = PCI_ENABLE_IO(dev, child, type); 5575 break; 5576 } 5577 } 5578 return (error); 5579 } 5580 5581 int 5582 pci_deactivate_resource(device_t dev, device_t child, int type, 5583 int rid, struct resource *r) 5584 { 5585 struct pci_devinfo *dinfo; 5586 int error; 5587 5588 error = bus_generic_deactivate_resource(dev, child, type, rid, r); 5589 if (error) 5590 return (error); 5591 5592 /* Disable decoding for device ROMs. */ 5593 if (device_get_parent(child) == dev) { 5594 dinfo = device_get_ivars(child); 5595 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5596 pci_write_bar(child, pci_find_bar(child, rid), 5597 rman_get_start(r)); 5598 } 5599 return (0); 5600 } 5601 5602 void 5603 pci_child_deleted(device_t dev, device_t child) 5604 { 5605 struct resource_list_entry *rle; 5606 struct resource_list *rl; 5607 struct pci_devinfo *dinfo; 5608 5609 dinfo = device_get_ivars(child); 5610 rl = &dinfo->resources; 5611 5612 EVENTHANDLER_INVOKE(pci_delete_device, child); 5613 5614 /* Turn off access to resources we're about to free */ 5615 if (bus_child_present(child) != 0) { 5616 pci_write_config(child, PCIR_COMMAND, pci_read_config(child, 5617 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2); 5618 5619 pci_disable_busmaster(child); 5620 } 5621 5622 /* Free all allocated resources */ 5623 STAILQ_FOREACH(rle, rl, link) { 5624 if (rle->res) { 5625 if (rman_get_flags(rle->res) & RF_ACTIVE || 5626 resource_list_busy(rl, rle->type, rle->rid)) { 5627 pci_printf(&dinfo->cfg, 5628 "Resource still owned, oops. " 5629 "(type=%d, rid=%d, addr=%lx)\n", 5630 rle->type, rle->rid, 5631 rman_get_start(rle->res)); 5632 bus_release_resource(child, rle->type, rle->rid, 5633 rle->res); 5634 } 5635 resource_list_unreserve(rl, dev, child, rle->type, 5636 rle->rid); 5637 } 5638 } 5639 resource_list_free(rl); 5640 5641 pci_freecfg(dinfo); 5642 } 5643 5644 void 5645 pci_delete_resource(device_t dev, device_t child, int type, int rid) 5646 { 5647 struct pci_devinfo *dinfo; 5648 struct resource_list *rl; 5649 struct resource_list_entry *rle; 5650 5651 if (device_get_parent(child) != dev) 5652 return; 5653 5654 dinfo = device_get_ivars(child); 5655 rl = &dinfo->resources; 5656 rle = resource_list_find(rl, type, rid); 5657 if (rle == NULL) 5658 return; 5659 5660 if (rle->res) { 5661 if (rman_get_flags(rle->res) & RF_ACTIVE || 5662 resource_list_busy(rl, type, rid)) { 5663 device_printf(dev, "delete_resource: " 5664 "Resource still owned by child, oops. " 5665 "(type=%d, rid=%d, addr=%jx)\n", 5666 type, rid, rman_get_start(rle->res)); 5667 return; 5668 } 5669 resource_list_unreserve(rl, dev, child, type, rid); 5670 } 5671 resource_list_delete(rl, type, rid); 5672 } 5673 5674 struct resource_list * 5675 pci_get_resource_list (device_t dev, device_t child) 5676 { 5677 struct pci_devinfo *dinfo = device_get_ivars(child); 5678 5679 return (&dinfo->resources); 5680 } 5681 5682 #ifdef ACPI_DMAR 5683 bus_dma_tag_t acpi_iommu_get_dma_tag(device_t dev, device_t child); 5684 bus_dma_tag_t 5685 pci_get_dma_tag(device_t bus, device_t dev) 5686 { 5687 bus_dma_tag_t tag; 5688 struct pci_softc *sc; 5689 5690 if (device_get_parent(dev) == bus) { 5691 /* try iommu and return if it works */ 5692 tag = acpi_iommu_get_dma_tag(bus, dev); 5693 } else 5694 tag = NULL; 5695 if (tag == NULL) { 5696 sc = device_get_softc(bus); 5697 tag = sc->sc_dma_tag; 5698 } 5699 return (tag); 5700 } 5701 #else 5702 bus_dma_tag_t 5703 pci_get_dma_tag(device_t bus, device_t dev) 5704 { 5705 struct pci_softc *sc = device_get_softc(bus); 5706 5707 return (sc->sc_dma_tag); 5708 } 5709 #endif 5710 5711 uint32_t 5712 pci_read_config_method(device_t dev, device_t child, int reg, int width) 5713 { 5714 struct pci_devinfo *dinfo = device_get_ivars(child); 5715 pcicfgregs *cfg = &dinfo->cfg; 5716 5717 #ifdef PCI_IOV 5718 /* 5719 * SR-IOV VFs don't implement the VID or DID registers, so we have to 5720 * emulate them here. 5721 */ 5722 if (cfg->flags & PCICFG_VF) { 5723 if (reg == PCIR_VENDOR) { 5724 switch (width) { 5725 case 4: 5726 return (cfg->device << 16 | cfg->vendor); 5727 case 2: 5728 return (cfg->vendor); 5729 case 1: 5730 return (cfg->vendor & 0xff); 5731 default: 5732 return (0xffffffff); 5733 } 5734 } else if (reg == PCIR_DEVICE) { 5735 switch (width) { 5736 /* Note that an unaligned 4-byte read is an error. */ 5737 case 2: 5738 return (cfg->device); 5739 case 1: 5740 return (cfg->device & 0xff); 5741 default: 5742 return (0xffffffff); 5743 } 5744 } 5745 } 5746 #endif 5747 5748 return (PCIB_READ_CONFIG(device_get_parent(dev), 5749 cfg->bus, cfg->slot, cfg->func, reg, width)); 5750 } 5751 5752 void 5753 pci_write_config_method(device_t dev, device_t child, int reg, 5754 uint32_t val, int width) 5755 { 5756 struct pci_devinfo *dinfo = device_get_ivars(child); 5757 pcicfgregs *cfg = &dinfo->cfg; 5758 5759 PCIB_WRITE_CONFIG(device_get_parent(dev), 5760 cfg->bus, cfg->slot, cfg->func, reg, val, width); 5761 } 5762 5763 int 5764 pci_child_location_str_method(device_t dev, device_t child, char *buf, 5765 size_t buflen) 5766 { 5767 5768 snprintf(buf, buflen, "slot=%d function=%d dbsf=pci%d:%d:%d:%d", 5769 pci_get_slot(child), pci_get_function(child), pci_get_domain(child), 5770 pci_get_bus(child), pci_get_slot(child), pci_get_function(child)); 5771 return (0); 5772 } 5773 5774 int 5775 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 5776 size_t buflen) 5777 { 5778 struct pci_devinfo *dinfo; 5779 pcicfgregs *cfg; 5780 5781 dinfo = device_get_ivars(child); 5782 cfg = &dinfo->cfg; 5783 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 5784 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 5785 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 5786 cfg->progif); 5787 return (0); 5788 } 5789 5790 int 5791 pci_assign_interrupt_method(device_t dev, device_t child) 5792 { 5793 struct pci_devinfo *dinfo = device_get_ivars(child); 5794 pcicfgregs *cfg = &dinfo->cfg; 5795 5796 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 5797 cfg->intpin)); 5798 } 5799 5800 static void 5801 pci_lookup(void *arg, const char *name, device_t *dev) 5802 { 5803 long val; 5804 char *end; 5805 int domain, bus, slot, func; 5806 5807 if (*dev != NULL) 5808 return; 5809 5810 /* 5811 * Accept pciconf-style selectors of either pciD:B:S:F or 5812 * pciB:S:F. In the latter case, the domain is assumed to 5813 * be zero. 5814 */ 5815 if (strncmp(name, "pci", 3) != 0) 5816 return; 5817 val = strtol(name + 3, &end, 10); 5818 if (val < 0 || val > INT_MAX || *end != ':') 5819 return; 5820 domain = val; 5821 val = strtol(end + 1, &end, 10); 5822 if (val < 0 || val > INT_MAX || *end != ':') 5823 return; 5824 bus = val; 5825 val = strtol(end + 1, &end, 10); 5826 if (val < 0 || val > INT_MAX) 5827 return; 5828 slot = val; 5829 if (*end == ':') { 5830 val = strtol(end + 1, &end, 10); 5831 if (val < 0 || val > INT_MAX || *end != '\0') 5832 return; 5833 func = val; 5834 } else if (*end == '\0') { 5835 func = slot; 5836 slot = bus; 5837 bus = domain; 5838 domain = 0; 5839 } else 5840 return; 5841 5842 if (domain > PCI_DOMAINMAX || bus > PCI_BUSMAX || slot > PCI_SLOTMAX || 5843 func > PCIE_ARI_FUNCMAX || (slot != 0 && func > PCI_FUNCMAX)) 5844 return; 5845 5846 *dev = pci_find_dbsf(domain, bus, slot, func); 5847 } 5848 5849 static int 5850 pci_modevent(module_t mod, int what, void *arg) 5851 { 5852 static struct cdev *pci_cdev; 5853 static eventhandler_tag tag; 5854 5855 switch (what) { 5856 case MOD_LOAD: 5857 STAILQ_INIT(&pci_devq); 5858 pci_generation = 0; 5859 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 5860 "pci"); 5861 pci_load_vendor_data(); 5862 tag = EVENTHANDLER_REGISTER(dev_lookup, pci_lookup, NULL, 5863 1000); 5864 break; 5865 5866 case MOD_UNLOAD: 5867 if (tag != NULL) 5868 EVENTHANDLER_DEREGISTER(dev_lookup, tag); 5869 destroy_dev(pci_cdev); 5870 break; 5871 } 5872 5873 return (0); 5874 } 5875 5876 static void 5877 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo) 5878 { 5879 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2) 5880 struct pcicfg_pcie *cfg; 5881 int version, pos; 5882 5883 cfg = &dinfo->cfg.pcie; 5884 pos = cfg->pcie_location; 5885 5886 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 5887 5888 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); 5889 5890 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5891 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 5892 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 5893 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); 5894 5895 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5896 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 5897 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 5898 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); 5899 5900 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5901 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 5902 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); 5903 5904 if (version > 1) { 5905 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); 5906 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); 5907 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); 5908 } 5909 #undef WREG 5910 } 5911 5912 static void 5913 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo) 5914 { 5915 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 5916 dinfo->cfg.pcix.pcix_command, 2); 5917 } 5918 5919 void 5920 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 5921 { 5922 5923 /* 5924 * Restore the device to full power mode. We must do this 5925 * before we restore the registers because moving from D3 to 5926 * D0 will cause the chip's BARs and some other registers to 5927 * be reset to some unknown power on reset values. Cut down 5928 * the noise on boot by doing nothing if we are already in 5929 * state D0. 5930 */ 5931 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) 5932 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 5933 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 5934 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 5935 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 5936 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 5937 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 5938 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 5939 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 5940 case PCIM_HDRTYPE_NORMAL: 5941 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 5942 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 5943 break; 5944 case PCIM_HDRTYPE_BRIDGE: 5945 pci_write_config(dev, PCIR_SECLAT_1, 5946 dinfo->cfg.bridge.br_seclat, 1); 5947 pci_write_config(dev, PCIR_SUBBUS_1, 5948 dinfo->cfg.bridge.br_subbus, 1); 5949 pci_write_config(dev, PCIR_SECBUS_1, 5950 dinfo->cfg.bridge.br_secbus, 1); 5951 pci_write_config(dev, PCIR_PRIBUS_1, 5952 dinfo->cfg.bridge.br_pribus, 1); 5953 pci_write_config(dev, PCIR_BRIDGECTL_1, 5954 dinfo->cfg.bridge.br_control, 2); 5955 break; 5956 case PCIM_HDRTYPE_CARDBUS: 5957 pci_write_config(dev, PCIR_SECLAT_2, 5958 dinfo->cfg.bridge.br_seclat, 1); 5959 pci_write_config(dev, PCIR_SUBBUS_2, 5960 dinfo->cfg.bridge.br_subbus, 1); 5961 pci_write_config(dev, PCIR_SECBUS_2, 5962 dinfo->cfg.bridge.br_secbus, 1); 5963 pci_write_config(dev, PCIR_PRIBUS_2, 5964 dinfo->cfg.bridge.br_pribus, 1); 5965 pci_write_config(dev, PCIR_BRIDGECTL_2, 5966 dinfo->cfg.bridge.br_control, 2); 5967 break; 5968 } 5969 pci_restore_bars(dev); 5970 5971 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE) 5972 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 5973 5974 /* 5975 * Restore extended capabilities for PCI-Express and PCI-X 5976 */ 5977 if (dinfo->cfg.pcie.pcie_location != 0) 5978 pci_cfg_restore_pcie(dev, dinfo); 5979 if (dinfo->cfg.pcix.pcix_location != 0) 5980 pci_cfg_restore_pcix(dev, dinfo); 5981 5982 /* Restore MSI and MSI-X configurations if they are present. */ 5983 if (dinfo->cfg.msi.msi_location != 0) 5984 pci_resume_msi(dev); 5985 if (dinfo->cfg.msix.msix_location != 0) 5986 pci_resume_msix(dev); 5987 5988 #ifdef PCI_IOV 5989 if (dinfo->cfg.iov != NULL) 5990 pci_iov_cfg_restore(dev, dinfo); 5991 #endif 5992 } 5993 5994 static void 5995 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo) 5996 { 5997 #define RREG(n) pci_read_config(dev, pos + (n), 2) 5998 struct pcicfg_pcie *cfg; 5999 int version, pos; 6000 6001 cfg = &dinfo->cfg.pcie; 6002 pos = cfg->pcie_location; 6003 6004 cfg->pcie_flags = RREG(PCIER_FLAGS); 6005 6006 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6007 6008 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); 6009 6010 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6011 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6012 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6013 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); 6014 6015 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6016 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6017 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6018 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); 6019 6020 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6021 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6022 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); 6023 6024 if (version > 1) { 6025 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); 6026 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); 6027 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); 6028 } 6029 #undef RREG 6030 } 6031 6032 static void 6033 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo) 6034 { 6035 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, 6036 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); 6037 } 6038 6039 void 6040 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 6041 { 6042 uint32_t cls; 6043 int ps; 6044 6045 /* 6046 * Some drivers apparently write to these registers w/o updating our 6047 * cached copy. No harm happens if we update the copy, so do so here 6048 * so we can restore them. The COMMAND register is modified by the 6049 * bus w/o updating the cache. This should represent the normally 6050 * writable portion of the 'defined' part of type 0/1/2 headers. 6051 */ 6052 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 6053 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 6054 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 6055 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 6056 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 6057 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 6058 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 6059 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 6060 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 6061 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 6062 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 6063 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6064 case PCIM_HDRTYPE_NORMAL: 6065 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 6066 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 6067 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 6068 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 6069 break; 6070 case PCIM_HDRTYPE_BRIDGE: 6071 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6072 PCIR_SECLAT_1, 1); 6073 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6074 PCIR_SUBBUS_1, 1); 6075 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6076 PCIR_SECBUS_1, 1); 6077 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6078 PCIR_PRIBUS_1, 1); 6079 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6080 PCIR_BRIDGECTL_1, 2); 6081 break; 6082 case PCIM_HDRTYPE_CARDBUS: 6083 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6084 PCIR_SECLAT_2, 1); 6085 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6086 PCIR_SUBBUS_2, 1); 6087 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6088 PCIR_SECBUS_2, 1); 6089 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6090 PCIR_PRIBUS_2, 1); 6091 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6092 PCIR_BRIDGECTL_2, 2); 6093 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2); 6094 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2); 6095 break; 6096 } 6097 6098 if (dinfo->cfg.pcie.pcie_location != 0) 6099 pci_cfg_save_pcie(dev, dinfo); 6100 6101 if (dinfo->cfg.pcix.pcix_location != 0) 6102 pci_cfg_save_pcix(dev, dinfo); 6103 6104 #ifdef PCI_IOV 6105 if (dinfo->cfg.iov != NULL) 6106 pci_iov_cfg_save(dev, dinfo); 6107 #endif 6108 6109 /* 6110 * don't set the state for display devices, base peripherals and 6111 * memory devices since bad things happen when they are powered down. 6112 * We should (a) have drivers that can easily detach and (b) use 6113 * generic drivers for these devices so that some device actually 6114 * attaches. We need to make sure that when we implement (a) we don't 6115 * power the device down on a reattach. 6116 */ 6117 cls = pci_get_class(dev); 6118 if (!setstate) 6119 return; 6120 switch (pci_do_power_nodriver) 6121 { 6122 case 0: /* NO powerdown at all */ 6123 return; 6124 case 1: /* Conservative about what to power down */ 6125 if (cls == PCIC_STORAGE) 6126 return; 6127 /*FALLTHROUGH*/ 6128 case 2: /* Aggressive about what to power down */ 6129 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 6130 cls == PCIC_BASEPERIPH) 6131 return; 6132 /*FALLTHROUGH*/ 6133 case 3: /* Power down everything */ 6134 break; 6135 } 6136 /* 6137 * PCI spec says we can only go into D3 state from D0 state. 6138 * Transition from D[12] into D0 before going to D3 state. 6139 */ 6140 ps = pci_get_powerstate(dev); 6141 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6142 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6143 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 6144 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6145 } 6146 6147 /* Wrapper APIs suitable for device driver use. */ 6148 void 6149 pci_save_state(device_t dev) 6150 { 6151 struct pci_devinfo *dinfo; 6152 6153 dinfo = device_get_ivars(dev); 6154 pci_cfg_save(dev, dinfo, 0); 6155 } 6156 6157 void 6158 pci_restore_state(device_t dev) 6159 { 6160 struct pci_devinfo *dinfo; 6161 6162 dinfo = device_get_ivars(dev); 6163 pci_cfg_restore(dev, dinfo); 6164 } 6165 6166 static int 6167 pci_get_id_method(device_t dev, device_t child, enum pci_id_type type, 6168 uintptr_t *id) 6169 { 6170 6171 return (PCIB_GET_ID(device_get_parent(dev), child, type, id)); 6172 } 6173 6174 /* Find the upstream port of a given PCI device in a root complex. */ 6175 device_t 6176 pci_find_pcie_root_port(device_t dev) 6177 { 6178 struct pci_devinfo *dinfo; 6179 devclass_t pci_class; 6180 device_t pcib, bus; 6181 6182 pci_class = devclass_find("pci"); 6183 KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class, 6184 ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); 6185 6186 /* 6187 * Walk the bridge hierarchy until we find a PCI-e root 6188 * port or a non-PCI device. 6189 */ 6190 for (;;) { 6191 bus = device_get_parent(dev); 6192 KASSERT(bus != NULL, ("%s: null parent of %s", __func__, 6193 device_get_nameunit(dev))); 6194 6195 pcib = device_get_parent(bus); 6196 KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__, 6197 device_get_nameunit(bus))); 6198 6199 /* 6200 * pcib's parent must be a PCI bus for this to be a 6201 * PCI-PCI bridge. 6202 */ 6203 if (device_get_devclass(device_get_parent(pcib)) != pci_class) 6204 return (NULL); 6205 6206 dinfo = device_get_ivars(pcib); 6207 if (dinfo->cfg.pcie.pcie_location != 0 && 6208 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) 6209 return (pcib); 6210 6211 dev = pcib; 6212 } 6213 } 6214 6215 /* 6216 * Wait for pending transactions to complete on a PCI-express function. 6217 * 6218 * The maximum delay is specified in milliseconds in max_delay. Note 6219 * that this function may sleep. 6220 * 6221 * Returns true if the function is idle and false if the timeout is 6222 * exceeded. If dev is not a PCI-express function, this returns true. 6223 */ 6224 bool 6225 pcie_wait_for_pending_transactions(device_t dev, u_int max_delay) 6226 { 6227 struct pci_devinfo *dinfo = device_get_ivars(dev); 6228 uint16_t sta; 6229 int cap; 6230 6231 cap = dinfo->cfg.pcie.pcie_location; 6232 if (cap == 0) 6233 return (true); 6234 6235 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6236 while (sta & PCIEM_STA_TRANSACTION_PND) { 6237 if (max_delay == 0) 6238 return (false); 6239 6240 /* Poll once every 100 milliseconds up to the timeout. */ 6241 if (max_delay > 100) { 6242 pause_sbt("pcietp", 100 * SBT_1MS, 0, C_HARDCLOCK); 6243 max_delay -= 100; 6244 } else { 6245 pause_sbt("pcietp", max_delay * SBT_1MS, 0, 6246 C_HARDCLOCK); 6247 max_delay = 0; 6248 } 6249 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6250 } 6251 6252 return (true); 6253 } 6254 6255 /* 6256 * Determine the maximum Completion Timeout in microseconds. 6257 * 6258 * For non-PCI-express functions this returns 0. 6259 */ 6260 int 6261 pcie_get_max_completion_timeout(device_t dev) 6262 { 6263 struct pci_devinfo *dinfo = device_get_ivars(dev); 6264 int cap; 6265 6266 cap = dinfo->cfg.pcie.pcie_location; 6267 if (cap == 0) 6268 return (0); 6269 6270 /* 6271 * Functions using the 1.x spec use the default timeout range of 6272 * 50 microseconds to 50 milliseconds. Functions that do not 6273 * support programmable timeouts also use this range. 6274 */ 6275 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 || 6276 (pci_read_config(dev, cap + PCIER_DEVICE_CAP2, 4) & 6277 PCIEM_CAP2_COMP_TIMO_RANGES) == 0) 6278 return (50 * 1000); 6279 6280 switch (pci_read_config(dev, cap + PCIER_DEVICE_CTL2, 2) & 6281 PCIEM_CTL2_COMP_TIMO_VAL) { 6282 case PCIEM_CTL2_COMP_TIMO_100US: 6283 return (100); 6284 case PCIEM_CTL2_COMP_TIMO_10MS: 6285 return (10 * 1000); 6286 case PCIEM_CTL2_COMP_TIMO_55MS: 6287 return (55 * 1000); 6288 case PCIEM_CTL2_COMP_TIMO_210MS: 6289 return (210 * 1000); 6290 case PCIEM_CTL2_COMP_TIMO_900MS: 6291 return (900 * 1000); 6292 case PCIEM_CTL2_COMP_TIMO_3500MS: 6293 return (3500 * 1000); 6294 case PCIEM_CTL2_COMP_TIMO_13S: 6295 return (13 * 1000 * 1000); 6296 case PCIEM_CTL2_COMP_TIMO_64S: 6297 return (64 * 1000 * 1000); 6298 default: 6299 return (50 * 1000); 6300 } 6301 } 6302 6303 void 6304 pcie_apei_error(device_t dev, int sev, uint8_t *aerp) 6305 { 6306 struct pci_devinfo *dinfo = device_get_ivars(dev); 6307 const char *s; 6308 int aer; 6309 uint32_t r, r1; 6310 uint16_t rs; 6311 6312 if (sev == PCIEM_STA_CORRECTABLE_ERROR) 6313 s = "Correctable"; 6314 else if (sev == PCIEM_STA_NON_FATAL_ERROR) 6315 s = "Uncorrectable (Non-Fatal)"; 6316 else 6317 s = "Uncorrectable (Fatal)"; 6318 device_printf(dev, "%s PCIe error reported by APEI\n", s); 6319 if (aerp) { 6320 if (sev == PCIEM_STA_CORRECTABLE_ERROR) { 6321 r = le32dec(aerp + PCIR_AER_COR_STATUS); 6322 r1 = le32dec(aerp + PCIR_AER_COR_MASK); 6323 } else { 6324 r = le32dec(aerp + PCIR_AER_UC_STATUS); 6325 r1 = le32dec(aerp + PCIR_AER_UC_MASK); 6326 } 6327 device_printf(dev, "status 0x%08x mask 0x%08x", r, r1); 6328 if (sev != PCIEM_STA_CORRECTABLE_ERROR) { 6329 r = le32dec(aerp + PCIR_AER_UC_SEVERITY); 6330 rs = le16dec(aerp + PCIR_AER_CAP_CONTROL); 6331 printf(" severity 0x%08x first %d\n", 6332 r, rs & 0x1f); 6333 } else 6334 printf("\n"); 6335 } 6336 6337 /* As kind of recovery just report and clear the error statuses. */ 6338 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6339 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6340 if (r != 0) { 6341 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6342 device_printf(dev, "Clearing UC AER errors 0x%08x\n", r); 6343 } 6344 6345 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6346 if (r != 0) { 6347 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6348 device_printf(dev, "Clearing COR AER errors 0x%08x\n", r); 6349 } 6350 } 6351 if (dinfo->cfg.pcie.pcie_location != 0) { 6352 rs = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6353 PCIER_DEVICE_STA, 2); 6354 if ((rs & (PCIEM_STA_CORRECTABLE_ERROR | 6355 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6356 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6357 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6358 PCIER_DEVICE_STA, rs, 2); 6359 device_printf(dev, "Clearing PCIe errors 0x%04x\n", rs); 6360 } 6361 } 6362 } 6363 6364 /* 6365 * Perform a Function Level Reset (FLR) on a device. 6366 * 6367 * This function first waits for any pending transactions to complete 6368 * within the timeout specified by max_delay. If transactions are 6369 * still pending, the function will return false without attempting a 6370 * reset. 6371 * 6372 * If dev is not a PCI-express function or does not support FLR, this 6373 * function returns false. 6374 * 6375 * Note that no registers are saved or restored. The caller is 6376 * responsible for saving and restoring any registers including 6377 * PCI-standard registers via pci_save_state() and 6378 * pci_restore_state(). 6379 */ 6380 bool 6381 pcie_flr(device_t dev, u_int max_delay, bool force) 6382 { 6383 struct pci_devinfo *dinfo = device_get_ivars(dev); 6384 uint16_t cmd, ctl; 6385 int compl_delay; 6386 int cap; 6387 6388 cap = dinfo->cfg.pcie.pcie_location; 6389 if (cap == 0) 6390 return (false); 6391 6392 if (!(pci_read_config(dev, cap + PCIER_DEVICE_CAP, 4) & PCIEM_CAP_FLR)) 6393 return (false); 6394 6395 /* 6396 * Disable busmastering to prevent generation of new 6397 * transactions while waiting for the device to go idle. If 6398 * the idle timeout fails, the command register is restored 6399 * which will re-enable busmastering. 6400 */ 6401 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 6402 pci_write_config(dev, PCIR_COMMAND, cmd & ~(PCIM_CMD_BUSMASTEREN), 2); 6403 if (!pcie_wait_for_pending_transactions(dev, max_delay)) { 6404 if (!force) { 6405 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 6406 return (false); 6407 } 6408 pci_printf(&dinfo->cfg, 6409 "Resetting with transactions pending after %d ms\n", 6410 max_delay); 6411 6412 /* 6413 * Extend the post-FLR delay to cover the maximum 6414 * Completion Timeout delay of anything in flight 6415 * during the FLR delay. Enforce a minimum delay of 6416 * at least 10ms. 6417 */ 6418 compl_delay = pcie_get_max_completion_timeout(dev) / 1000; 6419 if (compl_delay < 10) 6420 compl_delay = 10; 6421 } else 6422 compl_delay = 0; 6423 6424 /* Initiate the reset. */ 6425 ctl = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 6426 pci_write_config(dev, cap + PCIER_DEVICE_CTL, ctl | 6427 PCIEM_CTL_INITIATE_FLR, 2); 6428 6429 /* Wait for 100ms. */ 6430 pause_sbt("pcieflr", (100 + compl_delay) * SBT_1MS, 0, C_HARDCLOCK); 6431 6432 if (pci_read_config(dev, cap + PCIER_DEVICE_STA, 2) & 6433 PCIEM_STA_TRANSACTION_PND) 6434 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n"); 6435 return (true); 6436 } 6437 6438 /* 6439 * Attempt a power-management reset by cycling the device in/out of D3 6440 * state. PCI spec says we can only go into D3 state from D0 state. 6441 * Transition from D[12] into D0 before going to D3 state. 6442 */ 6443 int 6444 pci_power_reset(device_t dev) 6445 { 6446 int ps; 6447 6448 ps = pci_get_powerstate(dev); 6449 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6450 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6451 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6452 pci_set_powerstate(dev, ps); 6453 return (0); 6454 } 6455 6456 /* 6457 * Try link drop and retrain of the downstream port of upstream 6458 * switch, for PCIe. According to the PCIe 3.0 spec 6.6.1, this must 6459 * cause Conventional Hot reset of the device in the slot. 6460 * Alternative, for PCIe, could be the secondary bus reset initiatied 6461 * on the upstream switch PCIR_BRIDGECTL_1, bit 6. 6462 */ 6463 int 6464 pcie_link_reset(device_t port, int pcie_location) 6465 { 6466 uint16_t v; 6467 6468 v = pci_read_config(port, pcie_location + PCIER_LINK_CTL, 2); 6469 v |= PCIEM_LINK_CTL_LINK_DIS; 6470 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6471 pause_sbt("pcier1", mstosbt(20), 0, 0); 6472 v &= ~PCIEM_LINK_CTL_LINK_DIS; 6473 v |= PCIEM_LINK_CTL_RETRAIN_LINK; 6474 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6475 pause_sbt("pcier2", mstosbt(100), 0, 0); /* 100 ms */ 6476 v = pci_read_config(port, pcie_location + PCIER_LINK_STA, 2); 6477 return ((v & PCIEM_LINK_STA_TRAINING) != 0 ? ETIMEDOUT : 0); 6478 } 6479 6480 static int 6481 pci_reset_post(device_t dev, device_t child) 6482 { 6483 6484 if (dev == device_get_parent(child)) 6485 pci_restore_state(child); 6486 return (0); 6487 } 6488 6489 static int 6490 pci_reset_prepare(device_t dev, device_t child) 6491 { 6492 6493 if (dev == device_get_parent(child)) 6494 pci_save_state(child); 6495 return (0); 6496 } 6497 6498 static int 6499 pci_reset_child(device_t dev, device_t child, int flags) 6500 { 6501 int error; 6502 6503 if (dev == NULL || device_get_parent(child) != dev) 6504 return (0); 6505 if ((flags & DEVF_RESET_DETACH) != 0) { 6506 error = device_get_state(child) == DS_ATTACHED ? 6507 device_detach(child) : 0; 6508 } else { 6509 error = BUS_SUSPEND_CHILD(dev, child); 6510 } 6511 if (error == 0) { 6512 if (!pcie_flr(child, 1000, false)) { 6513 error = BUS_RESET_PREPARE(dev, child); 6514 if (error == 0) 6515 pci_power_reset(child); 6516 BUS_RESET_POST(dev, child); 6517 } 6518 if ((flags & DEVF_RESET_DETACH) != 0) 6519 device_probe_and_attach(child); 6520 else 6521 BUS_RESUME_CHILD(dev, child); 6522 } 6523 return (error); 6524 } 6525 6526 const struct pci_device_table * 6527 pci_match_device(device_t child, const struct pci_device_table *id, size_t nelt) 6528 { 6529 bool match; 6530 uint16_t vendor, device, subvendor, subdevice, class, subclass, revid; 6531 6532 vendor = pci_get_vendor(child); 6533 device = pci_get_device(child); 6534 subvendor = pci_get_subvendor(child); 6535 subdevice = pci_get_subdevice(child); 6536 class = pci_get_class(child); 6537 subclass = pci_get_subclass(child); 6538 revid = pci_get_revid(child); 6539 while (nelt-- > 0) { 6540 match = true; 6541 if (id->match_flag_vendor) 6542 match &= vendor == id->vendor; 6543 if (id->match_flag_device) 6544 match &= device == id->device; 6545 if (id->match_flag_subvendor) 6546 match &= subvendor == id->subvendor; 6547 if (id->match_flag_subdevice) 6548 match &= subdevice == id->subdevice; 6549 if (id->match_flag_class) 6550 match &= class == id->class_id; 6551 if (id->match_flag_subclass) 6552 match &= subclass == id->subclass; 6553 if (id->match_flag_revid) 6554 match &= revid == id->revid; 6555 if (match) 6556 return (id); 6557 id++; 6558 } 6559 return (NULL); 6560 } 6561 6562 static void 6563 pci_print_faulted_dev_name(const struct pci_devinfo *dinfo) 6564 { 6565 const char *dev_name; 6566 device_t dev; 6567 6568 dev = dinfo->cfg.dev; 6569 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus, 6570 dinfo->cfg.slot, dinfo->cfg.func); 6571 dev_name = device_get_name(dev); 6572 if (dev_name != NULL) 6573 printf(" (%s%d)", dev_name, device_get_unit(dev)); 6574 } 6575 6576 void 6577 pci_print_faulted_dev(void) 6578 { 6579 struct pci_devinfo *dinfo; 6580 device_t dev; 6581 int aer, i; 6582 uint32_t r1, r2; 6583 uint16_t status; 6584 6585 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6586 dev = dinfo->cfg.dev; 6587 status = pci_read_config(dev, PCIR_STATUS, 2); 6588 status &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6589 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6590 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6591 if (status != 0) { 6592 pci_print_faulted_dev_name(dinfo); 6593 printf(" error 0x%04x\n", status); 6594 } 6595 if (dinfo->cfg.pcie.pcie_location != 0) { 6596 status = pci_read_config(dev, 6597 dinfo->cfg.pcie.pcie_location + 6598 PCIER_DEVICE_STA, 2); 6599 if ((status & (PCIEM_STA_CORRECTABLE_ERROR | 6600 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6601 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6602 pci_print_faulted_dev_name(dinfo); 6603 printf(" PCIe DEVCTL 0x%04x DEVSTA 0x%04x\n", 6604 pci_read_config(dev, 6605 dinfo->cfg.pcie.pcie_location + 6606 PCIER_DEVICE_CTL, 2), 6607 status); 6608 } 6609 } 6610 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6611 r1 = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6612 r2 = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6613 if (r1 != 0 || r2 != 0) { 6614 pci_print_faulted_dev_name(dinfo); 6615 printf(" AER UC 0x%08x Mask 0x%08x Svr 0x%08x\n" 6616 " COR 0x%08x Mask 0x%08x Ctl 0x%08x\n", 6617 r1, pci_read_config(dev, aer + 6618 PCIR_AER_UC_MASK, 4), 6619 pci_read_config(dev, aer + 6620 PCIR_AER_UC_SEVERITY, 4), 6621 r2, pci_read_config(dev, aer + 6622 PCIR_AER_COR_MASK, 4), 6623 pci_read_config(dev, aer + 6624 PCIR_AER_CAP_CONTROL, 4)); 6625 for (i = 0; i < 4; i++) { 6626 r1 = pci_read_config(dev, aer + 6627 PCIR_AER_HEADER_LOG + i * 4, 4); 6628 printf(" HL%d: 0x%08x\n", i, r1); 6629 } 6630 } 6631 } 6632 } 6633 } 6634 6635 #ifdef DDB 6636 DB_SHOW_COMMAND(pcierr, pci_print_faulted_dev_db) 6637 { 6638 6639 pci_print_faulted_dev(); 6640 } 6641 6642 static void 6643 db_clear_pcie_errors(const struct pci_devinfo *dinfo) 6644 { 6645 device_t dev; 6646 int aer; 6647 uint32_t r; 6648 6649 dev = dinfo->cfg.dev; 6650 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6651 PCIER_DEVICE_STA, 2); 6652 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6653 PCIER_DEVICE_STA, r, 2); 6654 6655 if (pci_find_extcap(dev, PCIZ_AER, &aer) != 0) 6656 return; 6657 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6658 if (r != 0) 6659 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6660 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6661 if (r != 0) 6662 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6663 } 6664 6665 DB_COMMAND(pci_clearerr, db_pci_clearerr) 6666 { 6667 struct pci_devinfo *dinfo; 6668 device_t dev; 6669 uint16_t status, status1; 6670 6671 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6672 dev = dinfo->cfg.dev; 6673 status1 = status = pci_read_config(dev, PCIR_STATUS, 2); 6674 status1 &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6675 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6676 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6677 if (status1 != 0) { 6678 status &= ~status1; 6679 pci_write_config(dev, PCIR_STATUS, status, 2); 6680 } 6681 if (dinfo->cfg.pcie.pcie_location != 0) 6682 db_clear_pcie_errors(dinfo); 6683 } 6684 } 6685 #endif 6686