1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 5 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000, BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice unmodified, this list of conditions, and the following 14 * disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "opt_acpi.h" 35 #include "opt_iommu.h" 36 #include "opt_bus.h" 37 38 #include <sys/param.h> 39 #include <sys/conf.h> 40 #include <sys/endian.h> 41 #include <sys/eventhandler.h> 42 #include <sys/fcntl.h> 43 #include <sys/kernel.h> 44 #include <sys/limits.h> 45 #include <sys/linker.h> 46 #include <sys/malloc.h> 47 #include <sys/module.h> 48 #include <sys/queue.h> 49 #include <sys/sysctl.h> 50 #include <sys/systm.h> 51 #include <sys/taskqueue.h> 52 #include <sys/tree.h> 53 54 #include <vm/vm.h> 55 #include <vm/pmap.h> 56 #include <vm/vm_extern.h> 57 58 #include <sys/bus.h> 59 #include <machine/bus.h> 60 #include <sys/rman.h> 61 #include <machine/resource.h> 62 #include <machine/stdarg.h> 63 64 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 65 #include <machine/intr_machdep.h> 66 #endif 67 68 #include <sys/pciio.h> 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 #include <dev/pci/pci_private.h> 72 73 #ifdef PCI_IOV 74 #include <sys/nv.h> 75 #include <dev/pci/pci_iov_private.h> 76 #endif 77 78 #include <dev/usb/controller/xhcireg.h> 79 #include <dev/usb/controller/ehcireg.h> 80 #include <dev/usb/controller/ohcireg.h> 81 #include <dev/usb/controller/uhcireg.h> 82 83 #include <dev/iommu/iommu.h> 84 85 #include "pcib_if.h" 86 #include "pci_if.h" 87 88 #define PCIR_IS_BIOS(cfg, reg) \ 89 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ 90 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) 91 92 static int pci_has_quirk(uint32_t devid, int quirk); 93 static pci_addr_t pci_mapbase(uint64_t mapreg); 94 static const char *pci_maptype(uint64_t mapreg); 95 static int pci_maprange(uint64_t mapreg); 96 static pci_addr_t pci_rombase(uint64_t mapreg); 97 static int pci_romsize(uint64_t testval); 98 static void pci_fixancient(pcicfgregs *cfg); 99 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...); 100 101 static int pci_porten(device_t dev); 102 static int pci_memen(device_t dev); 103 static void pci_assign_interrupt(device_t bus, device_t dev, 104 int force_route); 105 static int pci_add_map(device_t bus, device_t dev, int reg, 106 struct resource_list *rl, int force, int prefetch); 107 static int pci_probe(device_t dev); 108 static void pci_load_vendor_data(void); 109 static int pci_describe_parse_line(char **ptr, int *vendor, 110 int *device, char **desc); 111 static char *pci_describe_device(device_t dev); 112 static int pci_modevent(module_t mod, int what, void *arg); 113 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 114 pcicfgregs *cfg); 115 static void pci_read_cap(device_t pcib, pcicfgregs *cfg); 116 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 117 int reg, uint32_t *data); 118 #if 0 119 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 120 int reg, uint32_t data); 121 #endif 122 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 123 static void pci_mask_msix(device_t dev, u_int index); 124 static void pci_unmask_msix(device_t dev, u_int index); 125 static int pci_msi_blacklisted(void); 126 static int pci_msix_blacklisted(void); 127 static void pci_resume_msi(device_t dev); 128 static void pci_resume_msix(device_t dev); 129 static int pci_remap_intr_method(device_t bus, device_t dev, 130 u_int irq); 131 static void pci_hint_device_unit(device_t acdev, device_t child, 132 const char *name, int *unitp); 133 static int pci_reset_post(device_t dev, device_t child); 134 static int pci_reset_prepare(device_t dev, device_t child); 135 static int pci_reset_child(device_t dev, device_t child, 136 int flags); 137 138 static int pci_get_id_method(device_t dev, device_t child, 139 enum pci_id_type type, uintptr_t *rid); 140 141 static struct pci_devinfo * pci_fill_devinfo(device_t pcib, device_t bus, int d, 142 int b, int s, int f, uint16_t vid, uint16_t did); 143 144 static device_method_t pci_methods[] = { 145 /* Device interface */ 146 DEVMETHOD(device_probe, pci_probe), 147 DEVMETHOD(device_attach, pci_attach), 148 DEVMETHOD(device_detach, pci_detach), 149 DEVMETHOD(device_shutdown, bus_generic_shutdown), 150 DEVMETHOD(device_suspend, bus_generic_suspend), 151 DEVMETHOD(device_resume, pci_resume), 152 153 /* Bus interface */ 154 DEVMETHOD(bus_print_child, pci_print_child), 155 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 156 DEVMETHOD(bus_read_ivar, pci_read_ivar), 157 DEVMETHOD(bus_write_ivar, pci_write_ivar), 158 DEVMETHOD(bus_driver_added, pci_driver_added), 159 DEVMETHOD(bus_setup_intr, pci_setup_intr), 160 DEVMETHOD(bus_teardown_intr, pci_teardown_intr), 161 DEVMETHOD(bus_reset_prepare, pci_reset_prepare), 162 DEVMETHOD(bus_reset_post, pci_reset_post), 163 DEVMETHOD(bus_reset_child, pci_reset_child), 164 165 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag), 166 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 167 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 168 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 169 DEVMETHOD(bus_delete_resource, pci_delete_resource), 170 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 171 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 172 DEVMETHOD(bus_release_resource, pci_release_resource), 173 DEVMETHOD(bus_activate_resource, pci_activate_resource), 174 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource), 175 DEVMETHOD(bus_child_deleted, pci_child_deleted), 176 DEVMETHOD(bus_child_detached, pci_child_detached), 177 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 178 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 179 DEVMETHOD(bus_hint_device_unit, pci_hint_device_unit), 180 DEVMETHOD(bus_remap_intr, pci_remap_intr_method), 181 DEVMETHOD(bus_suspend_child, pci_suspend_child), 182 DEVMETHOD(bus_resume_child, pci_resume_child), 183 DEVMETHOD(bus_rescan, pci_rescan_method), 184 185 /* PCI interface */ 186 DEVMETHOD(pci_read_config, pci_read_config_method), 187 DEVMETHOD(pci_write_config, pci_write_config_method), 188 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 189 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 190 DEVMETHOD(pci_enable_io, pci_enable_io_method), 191 DEVMETHOD(pci_disable_io, pci_disable_io_method), 192 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 193 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 194 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 195 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 196 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 197 DEVMETHOD(pci_find_cap, pci_find_cap_method), 198 DEVMETHOD(pci_find_next_cap, pci_find_next_cap_method), 199 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 200 DEVMETHOD(pci_find_next_extcap, pci_find_next_extcap_method), 201 DEVMETHOD(pci_find_htcap, pci_find_htcap_method), 202 DEVMETHOD(pci_find_next_htcap, pci_find_next_htcap_method), 203 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 204 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), 205 DEVMETHOD(pci_enable_msi, pci_enable_msi_method), 206 DEVMETHOD(pci_enable_msix, pci_enable_msix_method), 207 DEVMETHOD(pci_disable_msi, pci_disable_msi_method), 208 DEVMETHOD(pci_remap_msix, pci_remap_msix_method), 209 DEVMETHOD(pci_release_msi, pci_release_msi_method), 210 DEVMETHOD(pci_msi_count, pci_msi_count_method), 211 DEVMETHOD(pci_msix_count, pci_msix_count_method), 212 DEVMETHOD(pci_msix_pba_bar, pci_msix_pba_bar_method), 213 DEVMETHOD(pci_msix_table_bar, pci_msix_table_bar_method), 214 DEVMETHOD(pci_get_id, pci_get_id_method), 215 DEVMETHOD(pci_alloc_devinfo, pci_alloc_devinfo_method), 216 DEVMETHOD(pci_child_added, pci_child_added_method), 217 #ifdef PCI_IOV 218 DEVMETHOD(pci_iov_attach, pci_iov_attach_method), 219 DEVMETHOD(pci_iov_detach, pci_iov_detach_method), 220 DEVMETHOD(pci_create_iov_child, pci_create_iov_child_method), 221 #endif 222 223 DEVMETHOD_END 224 }; 225 226 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc)); 227 228 static devclass_t pci_devclass; 229 EARLY_DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL, 230 BUS_PASS_BUS); 231 MODULE_VERSION(pci, 1); 232 233 static char *pci_vendordata; 234 static size_t pci_vendordata_size; 235 236 struct pci_quirk { 237 uint32_t devid; /* Vendor/device of the card */ 238 int type; 239 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 240 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */ 241 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */ 242 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */ 243 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */ 244 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */ 245 #define PCI_QUIRK_REALLOC_BAR 7 /* Can't allocate memory at the default address */ 246 int arg1; 247 int arg2; 248 }; 249 250 static const struct pci_quirk pci_quirks[] = { 251 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */ 252 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 253 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 254 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 255 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 256 257 /* 258 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge 259 * or the CMIC-SL (AKA ServerWorks GC_LE). 260 */ 261 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 262 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 263 264 /* 265 * MSI doesn't work on earlier Intel chipsets including 266 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855. 267 */ 268 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 269 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 270 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 271 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 272 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 273 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 274 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 275 276 /* 277 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX 278 * bridge. 279 */ 280 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 281 282 /* 283 * Some virtualization environments emulate an older chipset 284 * but support MSI just fine. QEMU uses the Intel 82440. 285 */ 286 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 }, 287 288 /* 289 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus 290 * controller depending on SoftPciRst register (PM_IO 0x55 [7]). 291 * It prevents us from attaching hpet(4) when the bit is unset. 292 * Note this quirk only affects SB600 revision A13 and earlier. 293 * For SB600 A21 and later, firmware must set the bit to hide it. 294 * For SB700 and later, it is unused and hardcoded to zero. 295 */ 296 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 }, 297 298 /* 299 * Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have 300 * a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit 301 * of the command register is set. 302 */ 303 { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 304 { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 305 { 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 306 { 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 307 { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 308 309 /* 310 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't 311 * issue MSI interrupts with PCIM_CMD_INTxDIS set either. 312 */ 313 { 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */ 314 { 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */ 315 { 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */ 316 { 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */ 317 { 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */ 318 { 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */ 319 320 /* 321 * HPE Gen 10 VGA has a memory range that can't be allocated in the 322 * expected place. 323 */ 324 { 0x98741002, PCI_QUIRK_REALLOC_BAR, 0, 0 }, 325 { 0 } 326 }; 327 328 /* map register information */ 329 #define PCI_MAPMEM 0x01 /* memory map */ 330 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 331 #define PCI_MAPPORT 0x04 /* port map */ 332 333 struct devlist pci_devq; 334 uint32_t pci_generation; 335 uint32_t pci_numdevs = 0; 336 static int pcie_chipset, pcix_chipset; 337 338 /* sysctl vars */ 339 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 340 "PCI bus tuning parameters"); 341 342 static int pci_enable_io_modes = 1; 343 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RWTUN, 344 &pci_enable_io_modes, 1, 345 "Enable I/O and memory bits in the config register. Some BIOSes do not" 346 " enable these bits correctly. We'd like to do this all the time, but" 347 " there are some peripherals that this causes problems with."); 348 349 static int pci_do_realloc_bars = 1; 350 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RWTUN, 351 &pci_do_realloc_bars, 0, 352 "Attempt to allocate a new range for any BARs whose original " 353 "firmware-assigned ranges fail to allocate during the initial device scan."); 354 355 static int pci_do_power_nodriver = 0; 356 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RWTUN, 357 &pci_do_power_nodriver, 0, 358 "Place a function into D3 state when no driver attaches to it. 0 means" 359 " disable. 1 means conservatively place devices into D3 state. 2 means" 360 " aggressively place devices into D3 state. 3 means put absolutely" 361 " everything in D3 state."); 362 363 int pci_do_power_resume = 1; 364 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RWTUN, 365 &pci_do_power_resume, 1, 366 "Transition from D3 -> D0 on resume."); 367 368 int pci_do_power_suspend = 1; 369 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RWTUN, 370 &pci_do_power_suspend, 1, 371 "Transition from D0 -> D3 on suspend."); 372 373 static int pci_do_msi = 1; 374 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RWTUN, &pci_do_msi, 1, 375 "Enable support for MSI interrupts"); 376 377 static int pci_do_msix = 1; 378 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RWTUN, &pci_do_msix, 1, 379 "Enable support for MSI-X interrupts"); 380 381 static int pci_msix_rewrite_table = 0; 382 SYSCTL_INT(_hw_pci, OID_AUTO, msix_rewrite_table, CTLFLAG_RWTUN, 383 &pci_msix_rewrite_table, 0, 384 "Rewrite entire MSI-X table when updating MSI-X entries"); 385 386 static int pci_honor_msi_blacklist = 1; 387 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RDTUN, 388 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X"); 389 390 #if defined(__i386__) || defined(__amd64__) 391 static int pci_usb_takeover = 1; 392 #else 393 static int pci_usb_takeover = 0; 394 #endif 395 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN, 396 &pci_usb_takeover, 1, 397 "Enable early takeover of USB controllers. Disable this if you depend on" 398 " BIOS emulation of USB devices, that is you use USB devices (like" 399 " keyboard or mouse) but do not load USB drivers"); 400 401 static int pci_clear_bars; 402 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0, 403 "Ignore firmware-assigned resources for BARs."); 404 405 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 406 static int pci_clear_buses; 407 SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0, 408 "Ignore firmware-assigned bus numbers."); 409 #endif 410 411 static int pci_enable_ari = 1; 412 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari, 413 0, "Enable support for PCIe Alternative RID Interpretation"); 414 415 int pci_enable_aspm = 1; 416 SYSCTL_INT(_hw_pci, OID_AUTO, enable_aspm, CTLFLAG_RDTUN, &pci_enable_aspm, 417 0, "Enable support for PCIe Active State Power Management"); 418 419 static int pci_clear_aer_on_attach = 0; 420 SYSCTL_INT(_hw_pci, OID_AUTO, clear_aer_on_attach, CTLFLAG_RWTUN, 421 &pci_clear_aer_on_attach, 0, 422 "Clear port and device AER state on driver attach"); 423 424 static int 425 pci_has_quirk(uint32_t devid, int quirk) 426 { 427 const struct pci_quirk *q; 428 429 for (q = &pci_quirks[0]; q->devid; q++) { 430 if (q->devid == devid && q->type == quirk) 431 return (1); 432 } 433 return (0); 434 } 435 436 /* Find a device_t by bus/slot/function in domain 0 */ 437 438 device_t 439 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 440 { 441 442 return (pci_find_dbsf(0, bus, slot, func)); 443 } 444 445 /* Find a device_t by domain/bus/slot/function */ 446 447 device_t 448 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func) 449 { 450 struct pci_devinfo *dinfo = NULL; 451 452 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 453 if ((dinfo->cfg.domain == domain) && 454 (dinfo->cfg.bus == bus) && 455 (dinfo->cfg.slot == slot) && 456 (dinfo->cfg.func == func)) { 457 break; 458 } 459 } 460 461 return (dinfo != NULL ? dinfo->cfg.dev : NULL); 462 } 463 464 /* Find a device_t by vendor/device ID */ 465 466 device_t 467 pci_find_device(uint16_t vendor, uint16_t device) 468 { 469 struct pci_devinfo *dinfo; 470 471 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 472 if ((dinfo->cfg.vendor == vendor) && 473 (dinfo->cfg.device == device)) { 474 return (dinfo->cfg.dev); 475 } 476 } 477 478 return (NULL); 479 } 480 481 device_t 482 pci_find_class(uint8_t class, uint8_t subclass) 483 { 484 struct pci_devinfo *dinfo; 485 486 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 487 if (dinfo->cfg.baseclass == class && 488 dinfo->cfg.subclass == subclass) { 489 return (dinfo->cfg.dev); 490 } 491 } 492 493 return (NULL); 494 } 495 496 device_t 497 pci_find_class_from(uint8_t class, uint8_t subclass, device_t from) 498 { 499 struct pci_devinfo *dinfo; 500 bool found = false; 501 502 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 503 if (from != NULL && found == false) { 504 if (from != dinfo->cfg.dev) 505 continue; 506 found = true; 507 continue; 508 } 509 if (dinfo->cfg.baseclass == class && 510 dinfo->cfg.subclass == subclass) { 511 return (dinfo->cfg.dev); 512 } 513 } 514 515 return (NULL); 516 } 517 518 static int 519 pci_printf(pcicfgregs *cfg, const char *fmt, ...) 520 { 521 va_list ap; 522 int retval; 523 524 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, 525 cfg->func); 526 va_start(ap, fmt); 527 retval += vprintf(fmt, ap); 528 va_end(ap); 529 return (retval); 530 } 531 532 /* return base address of memory or port map */ 533 534 static pci_addr_t 535 pci_mapbase(uint64_t mapreg) 536 { 537 538 if (PCI_BAR_MEM(mapreg)) 539 return (mapreg & PCIM_BAR_MEM_BASE); 540 else 541 return (mapreg & PCIM_BAR_IO_BASE); 542 } 543 544 /* return map type of memory or port map */ 545 546 static const char * 547 pci_maptype(uint64_t mapreg) 548 { 549 550 if (PCI_BAR_IO(mapreg)) 551 return ("I/O Port"); 552 if (mapreg & PCIM_BAR_MEM_PREFETCH) 553 return ("Prefetchable Memory"); 554 return ("Memory"); 555 } 556 557 /* return log2 of map size decoded for memory or port map */ 558 559 int 560 pci_mapsize(uint64_t testval) 561 { 562 int ln2size; 563 564 testval = pci_mapbase(testval); 565 ln2size = 0; 566 if (testval != 0) { 567 while ((testval & 1) == 0) 568 { 569 ln2size++; 570 testval >>= 1; 571 } 572 } 573 return (ln2size); 574 } 575 576 /* return base address of device ROM */ 577 578 static pci_addr_t 579 pci_rombase(uint64_t mapreg) 580 { 581 582 return (mapreg & PCIM_BIOS_ADDR_MASK); 583 } 584 585 /* return log2 of map size decided for device ROM */ 586 587 static int 588 pci_romsize(uint64_t testval) 589 { 590 int ln2size; 591 592 testval = pci_rombase(testval); 593 ln2size = 0; 594 if (testval != 0) { 595 while ((testval & 1) == 0) 596 { 597 ln2size++; 598 testval >>= 1; 599 } 600 } 601 return (ln2size); 602 } 603 604 /* return log2 of address range supported by map register */ 605 606 static int 607 pci_maprange(uint64_t mapreg) 608 { 609 int ln2range = 0; 610 611 if (PCI_BAR_IO(mapreg)) 612 ln2range = 32; 613 else 614 switch (mapreg & PCIM_BAR_MEM_TYPE) { 615 case PCIM_BAR_MEM_32: 616 ln2range = 32; 617 break; 618 case PCIM_BAR_MEM_1MB: 619 ln2range = 20; 620 break; 621 case PCIM_BAR_MEM_64: 622 ln2range = 64; 623 break; 624 } 625 return (ln2range); 626 } 627 628 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 629 630 static void 631 pci_fixancient(pcicfgregs *cfg) 632 { 633 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 634 return; 635 636 /* PCI to PCI bridges use header type 1 */ 637 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 638 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; 639 } 640 641 /* extract header type specific config data */ 642 643 static void 644 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 645 { 646 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 647 switch (cfg->hdrtype & PCIM_HDRTYPE) { 648 case PCIM_HDRTYPE_NORMAL: 649 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 650 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 651 cfg->mingnt = REG(PCIR_MINGNT, 1); 652 cfg->maxlat = REG(PCIR_MAXLAT, 1); 653 cfg->nummaps = PCI_MAXMAPS_0; 654 break; 655 case PCIM_HDRTYPE_BRIDGE: 656 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1); 657 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1); 658 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1); 659 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1); 660 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2); 661 cfg->nummaps = PCI_MAXMAPS_1; 662 break; 663 case PCIM_HDRTYPE_CARDBUS: 664 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1); 665 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1); 666 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1); 667 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1); 668 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2); 669 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 670 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 671 cfg->nummaps = PCI_MAXMAPS_2; 672 break; 673 } 674 #undef REG 675 } 676 677 /* read configuration header into pcicfgregs structure */ 678 struct pci_devinfo * 679 pci_read_device(device_t pcib, device_t bus, int d, int b, int s, int f) 680 { 681 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 682 uint16_t vid, did; 683 684 vid = REG(PCIR_VENDOR, 2); 685 did = REG(PCIR_DEVICE, 2); 686 if (vid != 0xffff) 687 return (pci_fill_devinfo(pcib, bus, d, b, s, f, vid, did)); 688 689 return (NULL); 690 } 691 692 struct pci_devinfo * 693 pci_alloc_devinfo_method(device_t dev) 694 { 695 696 return (malloc(sizeof(struct pci_devinfo), M_DEVBUF, 697 M_WAITOK | M_ZERO)); 698 } 699 700 static struct pci_devinfo * 701 pci_fill_devinfo(device_t pcib, device_t bus, int d, int b, int s, int f, 702 uint16_t vid, uint16_t did) 703 { 704 struct pci_devinfo *devlist_entry; 705 pcicfgregs *cfg; 706 707 devlist_entry = PCI_ALLOC_DEVINFO(bus); 708 709 cfg = &devlist_entry->cfg; 710 711 cfg->domain = d; 712 cfg->bus = b; 713 cfg->slot = s; 714 cfg->func = f; 715 cfg->vendor = vid; 716 cfg->device = did; 717 cfg->cmdreg = REG(PCIR_COMMAND, 2); 718 cfg->statreg = REG(PCIR_STATUS, 2); 719 cfg->baseclass = REG(PCIR_CLASS, 1); 720 cfg->subclass = REG(PCIR_SUBCLASS, 1); 721 cfg->progif = REG(PCIR_PROGIF, 1); 722 cfg->revid = REG(PCIR_REVID, 1); 723 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 724 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 725 cfg->lattimer = REG(PCIR_LATTIMER, 1); 726 cfg->intpin = REG(PCIR_INTPIN, 1); 727 cfg->intline = REG(PCIR_INTLINE, 1); 728 729 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 730 cfg->hdrtype &= ~PCIM_MFDEV; 731 STAILQ_INIT(&cfg->maps); 732 733 cfg->iov = NULL; 734 735 pci_fixancient(cfg); 736 pci_hdrtypedata(pcib, b, s, f, cfg); 737 738 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 739 pci_read_cap(pcib, cfg); 740 741 STAILQ_INSERT_TAIL(&pci_devq, devlist_entry, pci_links); 742 743 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; 744 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 745 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 746 devlist_entry->conf.pc_sel.pc_func = cfg->func; 747 devlist_entry->conf.pc_hdr = cfg->hdrtype; 748 749 devlist_entry->conf.pc_subvendor = cfg->subvendor; 750 devlist_entry->conf.pc_subdevice = cfg->subdevice; 751 devlist_entry->conf.pc_vendor = cfg->vendor; 752 devlist_entry->conf.pc_device = cfg->device; 753 754 devlist_entry->conf.pc_class = cfg->baseclass; 755 devlist_entry->conf.pc_subclass = cfg->subclass; 756 devlist_entry->conf.pc_progif = cfg->progif; 757 devlist_entry->conf.pc_revid = cfg->revid; 758 759 pci_numdevs++; 760 pci_generation++; 761 762 return (devlist_entry); 763 } 764 #undef REG 765 766 static void 767 pci_ea_fill_info(device_t pcib, pcicfgregs *cfg) 768 { 769 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \ 770 cfg->ea.ea_location + (n), w) 771 int num_ent; 772 int ptr; 773 int a, b; 774 uint32_t val; 775 int ent_size; 776 uint32_t dw[4]; 777 uint64_t base, max_offset; 778 struct pci_ea_entry *eae; 779 780 if (cfg->ea.ea_location == 0) 781 return; 782 783 STAILQ_INIT(&cfg->ea.ea_entries); 784 785 /* Determine the number of entries */ 786 num_ent = REG(PCIR_EA_NUM_ENT, 2); 787 num_ent &= PCIM_EA_NUM_ENT_MASK; 788 789 /* Find the first entry to care of */ 790 ptr = PCIR_EA_FIRST_ENT; 791 792 /* Skip DWORD 2 for type 1 functions */ 793 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) 794 ptr += 4; 795 796 for (a = 0; a < num_ent; a++) { 797 eae = malloc(sizeof(*eae), M_DEVBUF, M_WAITOK | M_ZERO); 798 eae->eae_cfg_offset = cfg->ea.ea_location + ptr; 799 800 /* Read a number of dwords in the entry */ 801 val = REG(ptr, 4); 802 ptr += 4; 803 ent_size = (val & PCIM_EA_ES); 804 805 for (b = 0; b < ent_size; b++) { 806 dw[b] = REG(ptr, 4); 807 ptr += 4; 808 } 809 810 eae->eae_flags = val; 811 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 812 813 base = dw[0] & PCIM_EA_FIELD_MASK; 814 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 815 b = 2; 816 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 817 base |= (uint64_t)dw[b] << 32UL; 818 b++; 819 } 820 if (((dw[1] & PCIM_EA_IS_64) != 0) 821 && (b < ent_size)) { 822 max_offset |= (uint64_t)dw[b] << 32UL; 823 b++; 824 } 825 826 eae->eae_base = base; 827 eae->eae_max_offset = max_offset; 828 829 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link); 830 831 if (bootverbose) { 832 printf("PCI(EA) dev %04x:%04x, bei %d, flags #%x, base #%jx, max_offset #%jx\n", 833 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags, 834 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset); 835 } 836 } 837 } 838 #undef REG 839 840 static void 841 pci_read_cap(device_t pcib, pcicfgregs *cfg) 842 { 843 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 844 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 845 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 846 uint64_t addr; 847 #endif 848 uint32_t val; 849 int ptr, nextptr, ptrptr; 850 851 switch (cfg->hdrtype & PCIM_HDRTYPE) { 852 case PCIM_HDRTYPE_NORMAL: 853 case PCIM_HDRTYPE_BRIDGE: 854 ptrptr = PCIR_CAP_PTR; 855 break; 856 case PCIM_HDRTYPE_CARDBUS: 857 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 858 break; 859 default: 860 return; /* no extended capabilities support */ 861 } 862 nextptr = REG(ptrptr, 1); /* sanity check? */ 863 864 /* 865 * Read capability entries. 866 */ 867 while (nextptr != 0) { 868 /* Sanity check */ 869 if (nextptr > 255) { 870 printf("illegal PCI extended capability offset %d\n", 871 nextptr); 872 return; 873 } 874 /* Find the next entry */ 875 ptr = nextptr; 876 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 877 878 /* Process this entry */ 879 switch (REG(ptr + PCICAP_ID, 1)) { 880 case PCIY_PMG: /* PCI power management */ 881 if (cfg->pp.pp_cap == 0) { 882 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 883 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 884 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE; 885 if ((nextptr - ptr) > PCIR_POWER_DATA) 886 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 887 } 888 break; 889 case PCIY_HT: /* HyperTransport */ 890 /* Determine HT-specific capability type. */ 891 val = REG(ptr + PCIR_HT_COMMAND, 2); 892 893 if ((val & 0xe000) == PCIM_HTCAP_SLAVE) 894 cfg->ht.ht_slave = ptr; 895 896 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 897 switch (val & PCIM_HTCMD_CAP_MASK) { 898 case PCIM_HTCAP_MSI_MAPPING: 899 if (!(val & PCIM_HTCMD_MSI_FIXED)) { 900 /* Sanity check the mapping window. */ 901 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 902 4); 903 addr <<= 32; 904 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 905 4); 906 if (addr != MSI_INTEL_ADDR_BASE) 907 device_printf(pcib, 908 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", 909 cfg->domain, cfg->bus, 910 cfg->slot, cfg->func, 911 (long long)addr); 912 } else 913 addr = MSI_INTEL_ADDR_BASE; 914 915 cfg->ht.ht_msimap = ptr; 916 cfg->ht.ht_msictrl = val; 917 cfg->ht.ht_msiaddr = addr; 918 break; 919 } 920 #endif 921 break; 922 case PCIY_MSI: /* PCI MSI */ 923 cfg->msi.msi_location = ptr; 924 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 925 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 926 PCIM_MSICTRL_MMC_MASK)>>1); 927 break; 928 case PCIY_MSIX: /* PCI MSI-X */ 929 cfg->msix.msix_location = ptr; 930 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 931 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl & 932 PCIM_MSIXCTRL_TABLE_SIZE) + 1; 933 val = REG(ptr + PCIR_MSIX_TABLE, 4); 934 cfg->msix.msix_table_bar = PCIR_BAR(val & 935 PCIM_MSIX_BIR_MASK); 936 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 937 val = REG(ptr + PCIR_MSIX_PBA, 4); 938 cfg->msix.msix_pba_bar = PCIR_BAR(val & 939 PCIM_MSIX_BIR_MASK); 940 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 941 break; 942 case PCIY_VPD: /* PCI Vital Product Data */ 943 cfg->vpd.vpd_reg = ptr; 944 break; 945 case PCIY_SUBVENDOR: 946 /* Should always be true. */ 947 if ((cfg->hdrtype & PCIM_HDRTYPE) == 948 PCIM_HDRTYPE_BRIDGE) { 949 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4); 950 cfg->subvendor = val & 0xffff; 951 cfg->subdevice = val >> 16; 952 } 953 break; 954 case PCIY_PCIX: /* PCI-X */ 955 /* 956 * Assume we have a PCI-X chipset if we have 957 * at least one PCI-PCI bridge with a PCI-X 958 * capability. Note that some systems with 959 * PCI-express or HT chipsets might match on 960 * this check as well. 961 */ 962 if ((cfg->hdrtype & PCIM_HDRTYPE) == 963 PCIM_HDRTYPE_BRIDGE) 964 pcix_chipset = 1; 965 cfg->pcix.pcix_location = ptr; 966 break; 967 case PCIY_EXPRESS: /* PCI-express */ 968 /* 969 * Assume we have a PCI-express chipset if we have 970 * at least one PCI-express device. 971 */ 972 pcie_chipset = 1; 973 cfg->pcie.pcie_location = ptr; 974 val = REG(ptr + PCIER_FLAGS, 2); 975 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; 976 break; 977 case PCIY_EA: /* Enhanced Allocation */ 978 cfg->ea.ea_location = ptr; 979 pci_ea_fill_info(pcib, cfg); 980 break; 981 default: 982 break; 983 } 984 } 985 986 #if defined(__powerpc__) 987 /* 988 * Enable the MSI mapping window for all HyperTransport 989 * slaves. PCI-PCI bridges have their windows enabled via 990 * PCIB_MAP_MSI(). 991 */ 992 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && 993 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { 994 device_printf(pcib, 995 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n", 996 cfg->domain, cfg->bus, cfg->slot, cfg->func); 997 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 998 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, 999 2); 1000 } 1001 #endif 1002 /* REG and WREG use carry through to next functions */ 1003 } 1004 1005 /* 1006 * PCI Vital Product Data 1007 */ 1008 1009 #define PCI_VPD_TIMEOUT 1000000 1010 1011 static int 1012 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data) 1013 { 1014 int count = PCI_VPD_TIMEOUT; 1015 1016 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1017 1018 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); 1019 1020 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { 1021 if (--count < 0) 1022 return (ENXIO); 1023 DELAY(1); /* limit looping */ 1024 } 1025 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); 1026 1027 return (0); 1028 } 1029 1030 #if 0 1031 static int 1032 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 1033 { 1034 int count = PCI_VPD_TIMEOUT; 1035 1036 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1037 1038 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4); 1039 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2); 1040 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) { 1041 if (--count < 0) 1042 return (ENXIO); 1043 DELAY(1); /* limit looping */ 1044 } 1045 1046 return (0); 1047 } 1048 #endif 1049 1050 #undef PCI_VPD_TIMEOUT 1051 1052 struct vpd_readstate { 1053 device_t pcib; 1054 pcicfgregs *cfg; 1055 uint32_t val; 1056 int bytesinval; 1057 int off; 1058 uint8_t cksum; 1059 }; 1060 1061 static int 1062 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data) 1063 { 1064 uint32_t reg; 1065 uint8_t byte; 1066 1067 if (vrs->bytesinval == 0) { 1068 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) 1069 return (ENXIO); 1070 vrs->val = le32toh(reg); 1071 vrs->off += 4; 1072 byte = vrs->val & 0xff; 1073 vrs->bytesinval = 3; 1074 } else { 1075 vrs->val = vrs->val >> 8; 1076 byte = vrs->val & 0xff; 1077 vrs->bytesinval--; 1078 } 1079 1080 vrs->cksum += byte; 1081 *data = byte; 1082 return (0); 1083 } 1084 1085 static void 1086 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 1087 { 1088 struct vpd_readstate vrs; 1089 int state; 1090 int name; 1091 int remain; 1092 int i; 1093 int alloc, off; /* alloc/off for RO/W arrays */ 1094 int cksumvalid; 1095 int dflen; 1096 uint8_t byte; 1097 uint8_t byte2; 1098 1099 /* init vpd reader */ 1100 vrs.bytesinval = 0; 1101 vrs.off = 0; 1102 vrs.pcib = pcib; 1103 vrs.cfg = cfg; 1104 vrs.cksum = 0; 1105 1106 state = 0; 1107 name = remain = i = 0; /* shut up stupid gcc */ 1108 alloc = off = 0; /* shut up stupid gcc */ 1109 dflen = 0; /* shut up stupid gcc */ 1110 cksumvalid = -1; 1111 while (state >= 0) { 1112 if (vpd_nextbyte(&vrs, &byte)) { 1113 state = -2; 1114 break; 1115 } 1116 #if 0 1117 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \ 1118 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val, 1119 vrs.off, vrs.bytesinval, byte, state, remain, name, i); 1120 #endif 1121 switch (state) { 1122 case 0: /* item name */ 1123 if (byte & 0x80) { 1124 if (vpd_nextbyte(&vrs, &byte2)) { 1125 state = -2; 1126 break; 1127 } 1128 remain = byte2; 1129 if (vpd_nextbyte(&vrs, &byte2)) { 1130 state = -2; 1131 break; 1132 } 1133 remain |= byte2 << 8; 1134 name = byte & 0x7f; 1135 } else { 1136 remain = byte & 0x7; 1137 name = (byte >> 3) & 0xf; 1138 } 1139 if (vrs.off + remain - vrs.bytesinval > 0x8000) { 1140 pci_printf(cfg, 1141 "VPD data overflow, remain %#x\n", remain); 1142 state = -1; 1143 break; 1144 } 1145 switch (name) { 1146 case 0x2: /* String */ 1147 cfg->vpd.vpd_ident = malloc(remain + 1, 1148 M_DEVBUF, M_WAITOK); 1149 i = 0; 1150 state = 1; 1151 break; 1152 case 0xf: /* End */ 1153 state = -1; 1154 break; 1155 case 0x10: /* VPD-R */ 1156 alloc = 8; 1157 off = 0; 1158 cfg->vpd.vpd_ros = malloc(alloc * 1159 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF, 1160 M_WAITOK | M_ZERO); 1161 state = 2; 1162 break; 1163 case 0x11: /* VPD-W */ 1164 alloc = 8; 1165 off = 0; 1166 cfg->vpd.vpd_w = malloc(alloc * 1167 sizeof(*cfg->vpd.vpd_w), M_DEVBUF, 1168 M_WAITOK | M_ZERO); 1169 state = 5; 1170 break; 1171 default: /* Invalid data, abort */ 1172 state = -1; 1173 break; 1174 } 1175 break; 1176 1177 case 1: /* Identifier String */ 1178 cfg->vpd.vpd_ident[i++] = byte; 1179 remain--; 1180 if (remain == 0) { 1181 cfg->vpd.vpd_ident[i] = '\0'; 1182 state = 0; 1183 } 1184 break; 1185 1186 case 2: /* VPD-R Keyword Header */ 1187 if (off == alloc) { 1188 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1189 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros), 1190 M_DEVBUF, M_WAITOK | M_ZERO); 1191 } 1192 cfg->vpd.vpd_ros[off].keyword[0] = byte; 1193 if (vpd_nextbyte(&vrs, &byte2)) { 1194 state = -2; 1195 break; 1196 } 1197 cfg->vpd.vpd_ros[off].keyword[1] = byte2; 1198 if (vpd_nextbyte(&vrs, &byte2)) { 1199 state = -2; 1200 break; 1201 } 1202 cfg->vpd.vpd_ros[off].len = dflen = byte2; 1203 if (dflen == 0 && 1204 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV", 1205 2) == 0) { 1206 /* 1207 * if this happens, we can't trust the rest 1208 * of the VPD. 1209 */ 1210 pci_printf(cfg, "bad keyword length: %d\n", 1211 dflen); 1212 cksumvalid = 0; 1213 state = -1; 1214 break; 1215 } else if (dflen == 0) { 1216 cfg->vpd.vpd_ros[off].value = malloc(1 * 1217 sizeof(*cfg->vpd.vpd_ros[off].value), 1218 M_DEVBUF, M_WAITOK); 1219 cfg->vpd.vpd_ros[off].value[0] = '\x00'; 1220 } else 1221 cfg->vpd.vpd_ros[off].value = malloc( 1222 (dflen + 1) * 1223 sizeof(*cfg->vpd.vpd_ros[off].value), 1224 M_DEVBUF, M_WAITOK); 1225 remain -= 3; 1226 i = 0; 1227 /* keep in sync w/ state 3's transistions */ 1228 if (dflen == 0 && remain == 0) 1229 state = 0; 1230 else if (dflen == 0) 1231 state = 2; 1232 else 1233 state = 3; 1234 break; 1235 1236 case 3: /* VPD-R Keyword Value */ 1237 cfg->vpd.vpd_ros[off].value[i++] = byte; 1238 if (strncmp(cfg->vpd.vpd_ros[off].keyword, 1239 "RV", 2) == 0 && cksumvalid == -1) { 1240 if (vrs.cksum == 0) 1241 cksumvalid = 1; 1242 else { 1243 if (bootverbose) 1244 pci_printf(cfg, 1245 "bad VPD cksum, remain %hhu\n", 1246 vrs.cksum); 1247 cksumvalid = 0; 1248 state = -1; 1249 break; 1250 } 1251 } 1252 dflen--; 1253 remain--; 1254 /* keep in sync w/ state 2's transistions */ 1255 if (dflen == 0) 1256 cfg->vpd.vpd_ros[off++].value[i++] = '\0'; 1257 if (dflen == 0 && remain == 0) { 1258 cfg->vpd.vpd_rocnt = off; 1259 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1260 off * sizeof(*cfg->vpd.vpd_ros), 1261 M_DEVBUF, M_WAITOK | M_ZERO); 1262 state = 0; 1263 } else if (dflen == 0) 1264 state = 2; 1265 break; 1266 1267 case 4: 1268 remain--; 1269 if (remain == 0) 1270 state = 0; 1271 break; 1272 1273 case 5: /* VPD-W Keyword Header */ 1274 if (off == alloc) { 1275 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1276 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w), 1277 M_DEVBUF, M_WAITOK | M_ZERO); 1278 } 1279 cfg->vpd.vpd_w[off].keyword[0] = byte; 1280 if (vpd_nextbyte(&vrs, &byte2)) { 1281 state = -2; 1282 break; 1283 } 1284 cfg->vpd.vpd_w[off].keyword[1] = byte2; 1285 if (vpd_nextbyte(&vrs, &byte2)) { 1286 state = -2; 1287 break; 1288 } 1289 cfg->vpd.vpd_w[off].len = dflen = byte2; 1290 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval; 1291 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) * 1292 sizeof(*cfg->vpd.vpd_w[off].value), 1293 M_DEVBUF, M_WAITOK); 1294 remain -= 3; 1295 i = 0; 1296 /* keep in sync w/ state 6's transistions */ 1297 if (dflen == 0 && remain == 0) 1298 state = 0; 1299 else if (dflen == 0) 1300 state = 5; 1301 else 1302 state = 6; 1303 break; 1304 1305 case 6: /* VPD-W Keyword Value */ 1306 cfg->vpd.vpd_w[off].value[i++] = byte; 1307 dflen--; 1308 remain--; 1309 /* keep in sync w/ state 5's transistions */ 1310 if (dflen == 0) 1311 cfg->vpd.vpd_w[off++].value[i++] = '\0'; 1312 if (dflen == 0 && remain == 0) { 1313 cfg->vpd.vpd_wcnt = off; 1314 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1315 off * sizeof(*cfg->vpd.vpd_w), 1316 M_DEVBUF, M_WAITOK | M_ZERO); 1317 state = 0; 1318 } else if (dflen == 0) 1319 state = 5; 1320 break; 1321 1322 default: 1323 pci_printf(cfg, "invalid state: %d\n", state); 1324 state = -1; 1325 break; 1326 } 1327 } 1328 1329 if (cksumvalid == 0 || state < -1) { 1330 /* read-only data bad, clean up */ 1331 if (cfg->vpd.vpd_ros != NULL) { 1332 for (off = 0; cfg->vpd.vpd_ros[off].value; off++) 1333 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF); 1334 free(cfg->vpd.vpd_ros, M_DEVBUF); 1335 cfg->vpd.vpd_ros = NULL; 1336 } 1337 } 1338 if (state < -1) { 1339 /* I/O error, clean up */ 1340 pci_printf(cfg, "failed to read VPD data.\n"); 1341 if (cfg->vpd.vpd_ident != NULL) { 1342 free(cfg->vpd.vpd_ident, M_DEVBUF); 1343 cfg->vpd.vpd_ident = NULL; 1344 } 1345 if (cfg->vpd.vpd_w != NULL) { 1346 for (off = 0; cfg->vpd.vpd_w[off].value; off++) 1347 free(cfg->vpd.vpd_w[off].value, M_DEVBUF); 1348 free(cfg->vpd.vpd_w, M_DEVBUF); 1349 cfg->vpd.vpd_w = NULL; 1350 } 1351 } 1352 cfg->vpd.vpd_cached = 1; 1353 #undef REG 1354 #undef WREG 1355 } 1356 1357 int 1358 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 1359 { 1360 struct pci_devinfo *dinfo = device_get_ivars(child); 1361 pcicfgregs *cfg = &dinfo->cfg; 1362 1363 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1364 pci_read_vpd(device_get_parent(dev), cfg); 1365 1366 *identptr = cfg->vpd.vpd_ident; 1367 1368 if (*identptr == NULL) 1369 return (ENXIO); 1370 1371 return (0); 1372 } 1373 1374 int 1375 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 1376 const char **vptr) 1377 { 1378 struct pci_devinfo *dinfo = device_get_ivars(child); 1379 pcicfgregs *cfg = &dinfo->cfg; 1380 int i; 1381 1382 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1383 pci_read_vpd(device_get_parent(dev), cfg); 1384 1385 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 1386 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 1387 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { 1388 *vptr = cfg->vpd.vpd_ros[i].value; 1389 return (0); 1390 } 1391 1392 *vptr = NULL; 1393 return (ENXIO); 1394 } 1395 1396 struct pcicfg_vpd * 1397 pci_fetch_vpd_list(device_t dev) 1398 { 1399 struct pci_devinfo *dinfo = device_get_ivars(dev); 1400 pcicfgregs *cfg = &dinfo->cfg; 1401 1402 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1403 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg); 1404 return (&cfg->vpd); 1405 } 1406 1407 /* 1408 * Find the requested HyperTransport capability and return the offset 1409 * in configuration space via the pointer provided. The function 1410 * returns 0 on success and an error code otherwise. 1411 */ 1412 int 1413 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg) 1414 { 1415 int ptr, error; 1416 uint16_t val; 1417 1418 error = pci_find_cap(child, PCIY_HT, &ptr); 1419 if (error) 1420 return (error); 1421 1422 /* 1423 * Traverse the capabilities list checking each HT capability 1424 * to see if it matches the requested HT capability. 1425 */ 1426 for (;;) { 1427 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1428 if (capability == PCIM_HTCAP_SLAVE || 1429 capability == PCIM_HTCAP_HOST) 1430 val &= 0xe000; 1431 else 1432 val &= PCIM_HTCMD_CAP_MASK; 1433 if (val == capability) { 1434 if (capreg != NULL) 1435 *capreg = ptr; 1436 return (0); 1437 } 1438 1439 /* Skip to the next HT capability. */ 1440 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1441 break; 1442 } 1443 1444 return (ENOENT); 1445 } 1446 1447 /* 1448 * Find the next requested HyperTransport capability after start and return 1449 * the offset in configuration space via the pointer provided. The function 1450 * returns 0 on success and an error code otherwise. 1451 */ 1452 int 1453 pci_find_next_htcap_method(device_t dev, device_t child, int capability, 1454 int start, int *capreg) 1455 { 1456 int ptr; 1457 uint16_t val; 1458 1459 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == PCIY_HT, 1460 ("start capability is not HyperTransport capability")); 1461 ptr = start; 1462 1463 /* 1464 * Traverse the capabilities list checking each HT capability 1465 * to see if it matches the requested HT capability. 1466 */ 1467 for (;;) { 1468 /* Skip to the next HT capability. */ 1469 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1470 break; 1471 1472 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1473 if (capability == PCIM_HTCAP_SLAVE || 1474 capability == PCIM_HTCAP_HOST) 1475 val &= 0xe000; 1476 else 1477 val &= PCIM_HTCMD_CAP_MASK; 1478 if (val == capability) { 1479 if (capreg != NULL) 1480 *capreg = ptr; 1481 return (0); 1482 } 1483 } 1484 1485 return (ENOENT); 1486 } 1487 1488 /* 1489 * Find the requested capability and return the offset in 1490 * configuration space via the pointer provided. The function returns 1491 * 0 on success and an error code otherwise. 1492 */ 1493 int 1494 pci_find_cap_method(device_t dev, device_t child, int capability, 1495 int *capreg) 1496 { 1497 struct pci_devinfo *dinfo = device_get_ivars(child); 1498 pcicfgregs *cfg = &dinfo->cfg; 1499 uint32_t status; 1500 uint8_t ptr; 1501 1502 /* 1503 * Check the CAP_LIST bit of the PCI status register first. 1504 */ 1505 status = pci_read_config(child, PCIR_STATUS, 2); 1506 if (!(status & PCIM_STATUS_CAPPRESENT)) 1507 return (ENXIO); 1508 1509 /* 1510 * Determine the start pointer of the capabilities list. 1511 */ 1512 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1513 case PCIM_HDRTYPE_NORMAL: 1514 case PCIM_HDRTYPE_BRIDGE: 1515 ptr = PCIR_CAP_PTR; 1516 break; 1517 case PCIM_HDRTYPE_CARDBUS: 1518 ptr = PCIR_CAP_PTR_2; 1519 break; 1520 default: 1521 /* XXX: panic? */ 1522 return (ENXIO); /* no extended capabilities support */ 1523 } 1524 ptr = pci_read_config(child, ptr, 1); 1525 1526 /* 1527 * Traverse the capabilities list. 1528 */ 1529 while (ptr != 0) { 1530 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1531 if (capreg != NULL) 1532 *capreg = ptr; 1533 return (0); 1534 } 1535 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1536 } 1537 1538 return (ENOENT); 1539 } 1540 1541 /* 1542 * Find the next requested capability after start and return the offset in 1543 * configuration space via the pointer provided. The function returns 1544 * 0 on success and an error code otherwise. 1545 */ 1546 int 1547 pci_find_next_cap_method(device_t dev, device_t child, int capability, 1548 int start, int *capreg) 1549 { 1550 uint8_t ptr; 1551 1552 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == capability, 1553 ("start capability is not expected capability")); 1554 1555 ptr = pci_read_config(child, start + PCICAP_NEXTPTR, 1); 1556 while (ptr != 0) { 1557 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1558 if (capreg != NULL) 1559 *capreg = ptr; 1560 return (0); 1561 } 1562 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1563 } 1564 1565 return (ENOENT); 1566 } 1567 1568 /* 1569 * Find the requested extended capability and return the offset in 1570 * configuration space via the pointer provided. The function returns 1571 * 0 on success and an error code otherwise. 1572 */ 1573 int 1574 pci_find_extcap_method(device_t dev, device_t child, int capability, 1575 int *capreg) 1576 { 1577 struct pci_devinfo *dinfo = device_get_ivars(child); 1578 pcicfgregs *cfg = &dinfo->cfg; 1579 uint32_t ecap; 1580 uint16_t ptr; 1581 1582 /* Only supported for PCI-express devices. */ 1583 if (cfg->pcie.pcie_location == 0) 1584 return (ENXIO); 1585 1586 ptr = PCIR_EXTCAP; 1587 ecap = pci_read_config(child, ptr, 4); 1588 if (ecap == 0xffffffff || ecap == 0) 1589 return (ENOENT); 1590 for (;;) { 1591 if (PCI_EXTCAP_ID(ecap) == capability) { 1592 if (capreg != NULL) 1593 *capreg = ptr; 1594 return (0); 1595 } 1596 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1597 if (ptr == 0) 1598 break; 1599 ecap = pci_read_config(child, ptr, 4); 1600 } 1601 1602 return (ENOENT); 1603 } 1604 1605 /* 1606 * Find the next requested extended capability after start and return the 1607 * offset in configuration space via the pointer provided. The function 1608 * returns 0 on success and an error code otherwise. 1609 */ 1610 int 1611 pci_find_next_extcap_method(device_t dev, device_t child, int capability, 1612 int start, int *capreg) 1613 { 1614 struct pci_devinfo *dinfo = device_get_ivars(child); 1615 pcicfgregs *cfg = &dinfo->cfg; 1616 uint32_t ecap; 1617 uint16_t ptr; 1618 1619 /* Only supported for PCI-express devices. */ 1620 if (cfg->pcie.pcie_location == 0) 1621 return (ENXIO); 1622 1623 ecap = pci_read_config(child, start, 4); 1624 KASSERT(PCI_EXTCAP_ID(ecap) == capability, 1625 ("start extended capability is not expected capability")); 1626 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1627 while (ptr != 0) { 1628 ecap = pci_read_config(child, ptr, 4); 1629 if (PCI_EXTCAP_ID(ecap) == capability) { 1630 if (capreg != NULL) 1631 *capreg = ptr; 1632 return (0); 1633 } 1634 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1635 } 1636 1637 return (ENOENT); 1638 } 1639 1640 /* 1641 * Support for MSI-X message interrupts. 1642 */ 1643 static void 1644 pci_write_msix_entry(device_t dev, u_int index, uint64_t address, uint32_t data) 1645 { 1646 struct pci_devinfo *dinfo = device_get_ivars(dev); 1647 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1648 uint32_t offset; 1649 1650 KASSERT(msix->msix_table_len > index, ("bogus index")); 1651 offset = msix->msix_table_offset + index * 16; 1652 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); 1653 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); 1654 bus_write_4(msix->msix_table_res, offset + 8, data); 1655 } 1656 1657 void 1658 pci_enable_msix_method(device_t dev, device_t child, u_int index, 1659 uint64_t address, uint32_t data) 1660 { 1661 1662 if (pci_msix_rewrite_table) { 1663 struct pci_devinfo *dinfo = device_get_ivars(child); 1664 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1665 1666 /* 1667 * Some VM hosts require MSIX to be disabled in the 1668 * control register before updating the MSIX table 1669 * entries are allowed. It is not enough to only 1670 * disable MSIX while updating a single entry. MSIX 1671 * must be disabled while updating all entries in the 1672 * table. 1673 */ 1674 pci_write_config(child, 1675 msix->msix_location + PCIR_MSIX_CTRL, 1676 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2); 1677 pci_resume_msix(child); 1678 } else 1679 pci_write_msix_entry(child, index, address, data); 1680 1681 /* Enable MSI -> HT mapping. */ 1682 pci_ht_map_msi(child, address); 1683 } 1684 1685 void 1686 pci_mask_msix(device_t dev, u_int index) 1687 { 1688 struct pci_devinfo *dinfo = device_get_ivars(dev); 1689 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1690 uint32_t offset, val; 1691 1692 KASSERT(msix->msix_msgnum > index, ("bogus index")); 1693 offset = msix->msix_table_offset + index * 16 + 12; 1694 val = bus_read_4(msix->msix_table_res, offset); 1695 val |= PCIM_MSIX_VCTRL_MASK; 1696 1697 /* 1698 * Some devices (e.g. Samsung PM961) do not support reads of this 1699 * register, so always write the new value. 1700 */ 1701 bus_write_4(msix->msix_table_res, offset, val); 1702 } 1703 1704 void 1705 pci_unmask_msix(device_t dev, u_int index) 1706 { 1707 struct pci_devinfo *dinfo = device_get_ivars(dev); 1708 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1709 uint32_t offset, val; 1710 1711 KASSERT(msix->msix_table_len > index, ("bogus index")); 1712 offset = msix->msix_table_offset + index * 16 + 12; 1713 val = bus_read_4(msix->msix_table_res, offset); 1714 val &= ~PCIM_MSIX_VCTRL_MASK; 1715 1716 /* 1717 * Some devices (e.g. Samsung PM961) do not support reads of this 1718 * register, so always write the new value. 1719 */ 1720 bus_write_4(msix->msix_table_res, offset, val); 1721 } 1722 1723 int 1724 pci_pending_msix(device_t dev, u_int index) 1725 { 1726 struct pci_devinfo *dinfo = device_get_ivars(dev); 1727 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1728 uint32_t offset, bit; 1729 1730 KASSERT(msix->msix_table_len > index, ("bogus index")); 1731 offset = msix->msix_pba_offset + (index / 32) * 4; 1732 bit = 1 << index % 32; 1733 return (bus_read_4(msix->msix_pba_res, offset) & bit); 1734 } 1735 1736 /* 1737 * Restore MSI-X registers and table during resume. If MSI-X is 1738 * enabled then walk the virtual table to restore the actual MSI-X 1739 * table. 1740 */ 1741 static void 1742 pci_resume_msix(device_t dev) 1743 { 1744 struct pci_devinfo *dinfo = device_get_ivars(dev); 1745 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1746 struct msix_table_entry *mte; 1747 struct msix_vector *mv; 1748 int i; 1749 1750 if (msix->msix_alloc > 0) { 1751 /* First, mask all vectors. */ 1752 for (i = 0; i < msix->msix_msgnum; i++) 1753 pci_mask_msix(dev, i); 1754 1755 /* Second, program any messages with at least one handler. */ 1756 for (i = 0; i < msix->msix_table_len; i++) { 1757 mte = &msix->msix_table[i]; 1758 if (mte->mte_vector == 0 || mte->mte_handlers == 0) 1759 continue; 1760 mv = &msix->msix_vectors[mte->mte_vector - 1]; 1761 pci_write_msix_entry(dev, i, mv->mv_address, 1762 mv->mv_data); 1763 pci_unmask_msix(dev, i); 1764 } 1765 } 1766 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, 1767 msix->msix_ctrl, 2); 1768 } 1769 1770 /* 1771 * Attempt to allocate *count MSI-X messages. The actual number allocated is 1772 * returned in *count. After this function returns, each message will be 1773 * available to the driver as SYS_RES_IRQ resources starting at rid 1. 1774 */ 1775 int 1776 pci_alloc_msix_method(device_t dev, device_t child, int *count) 1777 { 1778 struct pci_devinfo *dinfo = device_get_ivars(child); 1779 pcicfgregs *cfg = &dinfo->cfg; 1780 struct resource_list_entry *rle; 1781 int actual, error, i, irq, max; 1782 1783 /* Don't let count == 0 get us into trouble. */ 1784 if (*count == 0) 1785 return (EINVAL); 1786 1787 /* If rid 0 is allocated, then fail. */ 1788 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1789 if (rle != NULL && rle->res != NULL) 1790 return (ENXIO); 1791 1792 /* Already have allocated messages? */ 1793 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1794 return (ENXIO); 1795 1796 /* If MSI-X is blacklisted for this system, fail. */ 1797 if (pci_msix_blacklisted()) 1798 return (ENXIO); 1799 1800 /* MSI-X capability present? */ 1801 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1802 return (ENODEV); 1803 1804 /* Make sure the appropriate BARs are mapped. */ 1805 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1806 cfg->msix.msix_table_bar); 1807 if (rle == NULL || rle->res == NULL || 1808 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1809 return (ENXIO); 1810 cfg->msix.msix_table_res = rle->res; 1811 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1812 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1813 cfg->msix.msix_pba_bar); 1814 if (rle == NULL || rle->res == NULL || 1815 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1816 return (ENXIO); 1817 } 1818 cfg->msix.msix_pba_res = rle->res; 1819 1820 if (bootverbose) 1821 device_printf(child, 1822 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1823 *count, cfg->msix.msix_msgnum); 1824 max = min(*count, cfg->msix.msix_msgnum); 1825 for (i = 0; i < max; i++) { 1826 /* Allocate a message. */ 1827 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq); 1828 if (error) { 1829 if (i == 0) 1830 return (error); 1831 break; 1832 } 1833 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1834 irq, 1); 1835 } 1836 actual = i; 1837 1838 if (bootverbose) { 1839 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1840 if (actual == 1) 1841 device_printf(child, "using IRQ %ju for MSI-X\n", 1842 rle->start); 1843 else { 1844 int run; 1845 1846 /* 1847 * Be fancy and try to print contiguous runs of 1848 * IRQ values as ranges. 'irq' is the previous IRQ. 1849 * 'run' is true if we are in a range. 1850 */ 1851 device_printf(child, "using IRQs %ju", rle->start); 1852 irq = rle->start; 1853 run = 0; 1854 for (i = 1; i < actual; i++) { 1855 rle = resource_list_find(&dinfo->resources, 1856 SYS_RES_IRQ, i + 1); 1857 1858 /* Still in a run? */ 1859 if (rle->start == irq + 1) { 1860 run = 1; 1861 irq++; 1862 continue; 1863 } 1864 1865 /* Finish previous range. */ 1866 if (run) { 1867 printf("-%d", irq); 1868 run = 0; 1869 } 1870 1871 /* Start new range. */ 1872 printf(",%ju", rle->start); 1873 irq = rle->start; 1874 } 1875 1876 /* Unfinished range? */ 1877 if (run) 1878 printf("-%d", irq); 1879 printf(" for MSI-X\n"); 1880 } 1881 } 1882 1883 /* Mask all vectors. */ 1884 for (i = 0; i < cfg->msix.msix_msgnum; i++) 1885 pci_mask_msix(child, i); 1886 1887 /* Allocate and initialize vector data and virtual table. */ 1888 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual, 1889 M_DEVBUF, M_WAITOK | M_ZERO); 1890 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual, 1891 M_DEVBUF, M_WAITOK | M_ZERO); 1892 for (i = 0; i < actual; i++) { 1893 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1894 cfg->msix.msix_vectors[i].mv_irq = rle->start; 1895 cfg->msix.msix_table[i].mte_vector = i + 1; 1896 } 1897 1898 /* Update control register to enable MSI-X. */ 1899 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1900 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1901 cfg->msix.msix_ctrl, 2); 1902 1903 /* Update counts of alloc'd messages. */ 1904 cfg->msix.msix_alloc = actual; 1905 cfg->msix.msix_table_len = actual; 1906 *count = actual; 1907 return (0); 1908 } 1909 1910 /* 1911 * By default, pci_alloc_msix() will assign the allocated IRQ 1912 * resources consecutively to the first N messages in the MSI-X table. 1913 * However, device drivers may want to use different layouts if they 1914 * either receive fewer messages than they asked for, or they wish to 1915 * populate the MSI-X table sparsely. This method allows the driver 1916 * to specify what layout it wants. It must be called after a 1917 * successful pci_alloc_msix() but before any of the associated 1918 * SYS_RES_IRQ resources are allocated via bus_alloc_resource(). 1919 * 1920 * The 'vectors' array contains 'count' message vectors. The array 1921 * maps directly to the MSI-X table in that index 0 in the array 1922 * specifies the vector for the first message in the MSI-X table, etc. 1923 * The vector value in each array index can either be 0 to indicate 1924 * that no vector should be assigned to a message slot, or it can be a 1925 * number from 1 to N (where N is the count returned from a 1926 * succcessful call to pci_alloc_msix()) to indicate which message 1927 * vector (IRQ) to be used for the corresponding message. 1928 * 1929 * On successful return, each message with a non-zero vector will have 1930 * an associated SYS_RES_IRQ whose rid is equal to the array index + 1931 * 1. Additionally, if any of the IRQs allocated via the previous 1932 * call to pci_alloc_msix() are not used in the mapping, those IRQs 1933 * will be freed back to the system automatically. 1934 * 1935 * For example, suppose a driver has a MSI-X table with 6 messages and 1936 * asks for 6 messages, but pci_alloc_msix() only returns a count of 1937 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and 1938 * C. After the call to pci_alloc_msix(), the device will be setup to 1939 * have an MSI-X table of ABC--- (where - means no vector assigned). 1940 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 }, 1941 * then the MSI-X table will look like A-AB-B, and the 'C' vector will 1942 * be freed back to the system. This device will also have valid 1943 * SYS_RES_IRQ rids of 1, 3, 4, and 6. 1944 * 1945 * In any case, the SYS_RES_IRQ rid X will always map to the message 1946 * at MSI-X table index X - 1 and will only be valid if a vector is 1947 * assigned to that table entry. 1948 */ 1949 int 1950 pci_remap_msix_method(device_t dev, device_t child, int count, 1951 const u_int *vectors) 1952 { 1953 struct pci_devinfo *dinfo = device_get_ivars(child); 1954 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1955 struct resource_list_entry *rle; 1956 int i, irq, j, *used; 1957 1958 /* 1959 * Have to have at least one message in the table but the 1960 * table can't be bigger than the actual MSI-X table in the 1961 * device. 1962 */ 1963 if (count == 0 || count > msix->msix_msgnum) 1964 return (EINVAL); 1965 1966 /* Sanity check the vectors. */ 1967 for (i = 0; i < count; i++) 1968 if (vectors[i] > msix->msix_alloc) 1969 return (EINVAL); 1970 1971 /* 1972 * Make sure there aren't any holes in the vectors to be used. 1973 * It's a big pain to support it, and it doesn't really make 1974 * sense anyway. Also, at least one vector must be used. 1975 */ 1976 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK | 1977 M_ZERO); 1978 for (i = 0; i < count; i++) 1979 if (vectors[i] != 0) 1980 used[vectors[i] - 1] = 1; 1981 for (i = 0; i < msix->msix_alloc - 1; i++) 1982 if (used[i] == 0 && used[i + 1] == 1) { 1983 free(used, M_DEVBUF); 1984 return (EINVAL); 1985 } 1986 if (used[0] != 1) { 1987 free(used, M_DEVBUF); 1988 return (EINVAL); 1989 } 1990 1991 /* Make sure none of the resources are allocated. */ 1992 for (i = 0; i < msix->msix_table_len; i++) { 1993 if (msix->msix_table[i].mte_vector == 0) 1994 continue; 1995 if (msix->msix_table[i].mte_handlers > 0) { 1996 free(used, M_DEVBUF); 1997 return (EBUSY); 1998 } 1999 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2000 KASSERT(rle != NULL, ("missing resource")); 2001 if (rle->res != NULL) { 2002 free(used, M_DEVBUF); 2003 return (EBUSY); 2004 } 2005 } 2006 2007 /* Free the existing resource list entries. */ 2008 for (i = 0; i < msix->msix_table_len; i++) { 2009 if (msix->msix_table[i].mte_vector == 0) 2010 continue; 2011 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2012 } 2013 2014 /* 2015 * Build the new virtual table keeping track of which vectors are 2016 * used. 2017 */ 2018 free(msix->msix_table, M_DEVBUF); 2019 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count, 2020 M_DEVBUF, M_WAITOK | M_ZERO); 2021 for (i = 0; i < count; i++) 2022 msix->msix_table[i].mte_vector = vectors[i]; 2023 msix->msix_table_len = count; 2024 2025 /* Free any unused IRQs and resize the vectors array if necessary. */ 2026 j = msix->msix_alloc - 1; 2027 if (used[j] == 0) { 2028 struct msix_vector *vec; 2029 2030 while (used[j] == 0) { 2031 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2032 msix->msix_vectors[j].mv_irq); 2033 j--; 2034 } 2035 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF, 2036 M_WAITOK); 2037 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * 2038 (j + 1)); 2039 free(msix->msix_vectors, M_DEVBUF); 2040 msix->msix_vectors = vec; 2041 msix->msix_alloc = j + 1; 2042 } 2043 free(used, M_DEVBUF); 2044 2045 /* Map the IRQs onto the rids. */ 2046 for (i = 0; i < count; i++) { 2047 if (vectors[i] == 0) 2048 continue; 2049 irq = msix->msix_vectors[vectors[i] - 1].mv_irq; 2050 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 2051 irq, 1); 2052 } 2053 2054 if (bootverbose) { 2055 device_printf(child, "Remapped MSI-X IRQs as: "); 2056 for (i = 0; i < count; i++) { 2057 if (i != 0) 2058 printf(", "); 2059 if (vectors[i] == 0) 2060 printf("---"); 2061 else 2062 printf("%d", 2063 msix->msix_vectors[vectors[i] - 1].mv_irq); 2064 } 2065 printf("\n"); 2066 } 2067 2068 return (0); 2069 } 2070 2071 static int 2072 pci_release_msix(device_t dev, device_t child) 2073 { 2074 struct pci_devinfo *dinfo = device_get_ivars(child); 2075 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2076 struct resource_list_entry *rle; 2077 int i; 2078 2079 /* Do we have any messages to release? */ 2080 if (msix->msix_alloc == 0) 2081 return (ENODEV); 2082 2083 /* Make sure none of the resources are allocated. */ 2084 for (i = 0; i < msix->msix_table_len; i++) { 2085 if (msix->msix_table[i].mte_vector == 0) 2086 continue; 2087 if (msix->msix_table[i].mte_handlers > 0) 2088 return (EBUSY); 2089 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2090 KASSERT(rle != NULL, ("missing resource")); 2091 if (rle->res != NULL) 2092 return (EBUSY); 2093 } 2094 2095 /* Update control register to disable MSI-X. */ 2096 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 2097 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, 2098 msix->msix_ctrl, 2); 2099 2100 /* Free the resource list entries. */ 2101 for (i = 0; i < msix->msix_table_len; i++) { 2102 if (msix->msix_table[i].mte_vector == 0) 2103 continue; 2104 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2105 } 2106 free(msix->msix_table, M_DEVBUF); 2107 msix->msix_table_len = 0; 2108 2109 /* Release the IRQs. */ 2110 for (i = 0; i < msix->msix_alloc; i++) 2111 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2112 msix->msix_vectors[i].mv_irq); 2113 free(msix->msix_vectors, M_DEVBUF); 2114 msix->msix_alloc = 0; 2115 return (0); 2116 } 2117 2118 /* 2119 * Return the max supported MSI-X messages this device supports. 2120 * Basically, assuming the MD code can alloc messages, this function 2121 * should return the maximum value that pci_alloc_msix() can return. 2122 * Thus, it is subject to the tunables, etc. 2123 */ 2124 int 2125 pci_msix_count_method(device_t dev, device_t child) 2126 { 2127 struct pci_devinfo *dinfo = device_get_ivars(child); 2128 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2129 2130 if (pci_do_msix && msix->msix_location != 0) 2131 return (msix->msix_msgnum); 2132 return (0); 2133 } 2134 2135 int 2136 pci_msix_pba_bar_method(device_t dev, device_t child) 2137 { 2138 struct pci_devinfo *dinfo = device_get_ivars(child); 2139 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2140 2141 if (pci_do_msix && msix->msix_location != 0) 2142 return (msix->msix_pba_bar); 2143 return (-1); 2144 } 2145 2146 int 2147 pci_msix_table_bar_method(device_t dev, device_t child) 2148 { 2149 struct pci_devinfo *dinfo = device_get_ivars(child); 2150 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2151 2152 if (pci_do_msix && msix->msix_location != 0) 2153 return (msix->msix_table_bar); 2154 return (-1); 2155 } 2156 2157 /* 2158 * HyperTransport MSI mapping control 2159 */ 2160 void 2161 pci_ht_map_msi(device_t dev, uint64_t addr) 2162 { 2163 struct pci_devinfo *dinfo = device_get_ivars(dev); 2164 struct pcicfg_ht *ht = &dinfo->cfg.ht; 2165 2166 if (!ht->ht_msimap) 2167 return; 2168 2169 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && 2170 ht->ht_msiaddr >> 20 == addr >> 20) { 2171 /* Enable MSI -> HT mapping. */ 2172 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 2173 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2174 ht->ht_msictrl, 2); 2175 } 2176 2177 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { 2178 /* Disable MSI -> HT mapping. */ 2179 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; 2180 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2181 ht->ht_msictrl, 2); 2182 } 2183 } 2184 2185 int 2186 pci_get_max_payload(device_t dev) 2187 { 2188 struct pci_devinfo *dinfo = device_get_ivars(dev); 2189 int cap; 2190 uint16_t val; 2191 2192 cap = dinfo->cfg.pcie.pcie_location; 2193 if (cap == 0) 2194 return (0); 2195 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2196 val &= PCIEM_CTL_MAX_PAYLOAD; 2197 val >>= 5; 2198 return (1 << (val + 7)); 2199 } 2200 2201 int 2202 pci_get_max_read_req(device_t dev) 2203 { 2204 struct pci_devinfo *dinfo = device_get_ivars(dev); 2205 int cap; 2206 uint16_t val; 2207 2208 cap = dinfo->cfg.pcie.pcie_location; 2209 if (cap == 0) 2210 return (0); 2211 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2212 val &= PCIEM_CTL_MAX_READ_REQUEST; 2213 val >>= 12; 2214 return (1 << (val + 7)); 2215 } 2216 2217 int 2218 pci_set_max_read_req(device_t dev, int size) 2219 { 2220 struct pci_devinfo *dinfo = device_get_ivars(dev); 2221 int cap; 2222 uint16_t val; 2223 2224 cap = dinfo->cfg.pcie.pcie_location; 2225 if (cap == 0) 2226 return (0); 2227 if (size < 128) 2228 size = 128; 2229 if (size > 4096) 2230 size = 4096; 2231 size = (1 << (fls(size) - 1)); 2232 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2233 val &= ~PCIEM_CTL_MAX_READ_REQUEST; 2234 val |= (fls(size) - 8) << 12; 2235 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2); 2236 return (size); 2237 } 2238 2239 uint32_t 2240 pcie_read_config(device_t dev, int reg, int width) 2241 { 2242 struct pci_devinfo *dinfo = device_get_ivars(dev); 2243 int cap; 2244 2245 cap = dinfo->cfg.pcie.pcie_location; 2246 if (cap == 0) { 2247 if (width == 2) 2248 return (0xffff); 2249 return (0xffffffff); 2250 } 2251 2252 return (pci_read_config(dev, cap + reg, width)); 2253 } 2254 2255 void 2256 pcie_write_config(device_t dev, int reg, uint32_t value, int width) 2257 { 2258 struct pci_devinfo *dinfo = device_get_ivars(dev); 2259 int cap; 2260 2261 cap = dinfo->cfg.pcie.pcie_location; 2262 if (cap == 0) 2263 return; 2264 pci_write_config(dev, cap + reg, value, width); 2265 } 2266 2267 /* 2268 * Adjusts a PCI-e capability register by clearing the bits in mask 2269 * and setting the bits in (value & mask). Bits not set in mask are 2270 * not adjusted. 2271 * 2272 * Returns the old value on success or all ones on failure. 2273 */ 2274 uint32_t 2275 pcie_adjust_config(device_t dev, int reg, uint32_t mask, uint32_t value, 2276 int width) 2277 { 2278 struct pci_devinfo *dinfo = device_get_ivars(dev); 2279 uint32_t old, new; 2280 int cap; 2281 2282 cap = dinfo->cfg.pcie.pcie_location; 2283 if (cap == 0) { 2284 if (width == 2) 2285 return (0xffff); 2286 return (0xffffffff); 2287 } 2288 2289 old = pci_read_config(dev, cap + reg, width); 2290 new = old & ~mask; 2291 new |= (value & mask); 2292 pci_write_config(dev, cap + reg, new, width); 2293 return (old); 2294 } 2295 2296 /* 2297 * Support for MSI message signalled interrupts. 2298 */ 2299 void 2300 pci_enable_msi_method(device_t dev, device_t child, uint64_t address, 2301 uint16_t data) 2302 { 2303 struct pci_devinfo *dinfo = device_get_ivars(child); 2304 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2305 2306 /* Write data and address values. */ 2307 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, 2308 address & 0xffffffff, 4); 2309 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2310 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, 2311 address >> 32, 4); 2312 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, 2313 data, 2); 2314 } else 2315 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, 2316 2); 2317 2318 /* Enable MSI in the control register. */ 2319 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 2320 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2321 msi->msi_ctrl, 2); 2322 2323 /* Enable MSI -> HT mapping. */ 2324 pci_ht_map_msi(child, address); 2325 } 2326 2327 void 2328 pci_disable_msi_method(device_t dev, device_t child) 2329 { 2330 struct pci_devinfo *dinfo = device_get_ivars(child); 2331 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2332 2333 /* Disable MSI -> HT mapping. */ 2334 pci_ht_map_msi(child, 0); 2335 2336 /* Disable MSI in the control register. */ 2337 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; 2338 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2339 msi->msi_ctrl, 2); 2340 } 2341 2342 /* 2343 * Restore MSI registers during resume. If MSI is enabled then 2344 * restore the data and address registers in addition to the control 2345 * register. 2346 */ 2347 static void 2348 pci_resume_msi(device_t dev) 2349 { 2350 struct pci_devinfo *dinfo = device_get_ivars(dev); 2351 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2352 uint64_t address; 2353 uint16_t data; 2354 2355 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 2356 address = msi->msi_addr; 2357 data = msi->msi_data; 2358 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 2359 address & 0xffffffff, 4); 2360 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2361 pci_write_config(dev, msi->msi_location + 2362 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 2363 pci_write_config(dev, msi->msi_location + 2364 PCIR_MSI_DATA_64BIT, data, 2); 2365 } else 2366 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, 2367 data, 2); 2368 } 2369 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 2370 2); 2371 } 2372 2373 static int 2374 pci_remap_intr_method(device_t bus, device_t dev, u_int irq) 2375 { 2376 struct pci_devinfo *dinfo = device_get_ivars(dev); 2377 pcicfgregs *cfg = &dinfo->cfg; 2378 struct resource_list_entry *rle; 2379 struct msix_table_entry *mte; 2380 struct msix_vector *mv; 2381 uint64_t addr; 2382 uint32_t data; 2383 int error, i, j; 2384 2385 /* 2386 * Handle MSI first. We try to find this IRQ among our list 2387 * of MSI IRQs. If we find it, we request updated address and 2388 * data registers and apply the results. 2389 */ 2390 if (cfg->msi.msi_alloc > 0) { 2391 /* If we don't have any active handlers, nothing to do. */ 2392 if (cfg->msi.msi_handlers == 0) 2393 return (0); 2394 for (i = 0; i < cfg->msi.msi_alloc; i++) { 2395 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 2396 i + 1); 2397 if (rle->start == irq) { 2398 error = PCIB_MAP_MSI(device_get_parent(bus), 2399 dev, irq, &addr, &data); 2400 if (error) 2401 return (error); 2402 pci_disable_msi(dev); 2403 dinfo->cfg.msi.msi_addr = addr; 2404 dinfo->cfg.msi.msi_data = data; 2405 pci_enable_msi(dev, addr, data); 2406 return (0); 2407 } 2408 } 2409 return (ENOENT); 2410 } 2411 2412 /* 2413 * For MSI-X, we check to see if we have this IRQ. If we do, 2414 * we request the updated mapping info. If that works, we go 2415 * through all the slots that use this IRQ and update them. 2416 */ 2417 if (cfg->msix.msix_alloc > 0) { 2418 for (i = 0; i < cfg->msix.msix_alloc; i++) { 2419 mv = &cfg->msix.msix_vectors[i]; 2420 if (mv->mv_irq == irq) { 2421 error = PCIB_MAP_MSI(device_get_parent(bus), 2422 dev, irq, &addr, &data); 2423 if (error) 2424 return (error); 2425 mv->mv_address = addr; 2426 mv->mv_data = data; 2427 for (j = 0; j < cfg->msix.msix_table_len; j++) { 2428 mte = &cfg->msix.msix_table[j]; 2429 if (mte->mte_vector != i + 1) 2430 continue; 2431 if (mte->mte_handlers == 0) 2432 continue; 2433 pci_mask_msix(dev, j); 2434 pci_enable_msix(dev, j, addr, data); 2435 pci_unmask_msix(dev, j); 2436 } 2437 } 2438 } 2439 return (ENOENT); 2440 } 2441 2442 return (ENOENT); 2443 } 2444 2445 /* 2446 * Returns true if the specified device is blacklisted because MSI 2447 * doesn't work. 2448 */ 2449 int 2450 pci_msi_device_blacklisted(device_t dev) 2451 { 2452 2453 if (!pci_honor_msi_blacklist) 2454 return (0); 2455 2456 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI)); 2457 } 2458 2459 /* 2460 * Determine if MSI is blacklisted globally on this system. Currently, 2461 * we just check for blacklisted chipsets as represented by the 2462 * host-PCI bridge at device 0:0:0. In the future, it may become 2463 * necessary to check other system attributes, such as the kenv values 2464 * that give the motherboard manufacturer and model number. 2465 */ 2466 static int 2467 pci_msi_blacklisted(void) 2468 { 2469 device_t dev; 2470 2471 if (!pci_honor_msi_blacklist) 2472 return (0); 2473 2474 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ 2475 if (!(pcie_chipset || pcix_chipset)) { 2476 if (vm_guest != VM_GUEST_NO) { 2477 /* 2478 * Whitelist older chipsets in virtual 2479 * machines known to support MSI. 2480 */ 2481 dev = pci_find_bsf(0, 0, 0); 2482 if (dev != NULL) 2483 return (!pci_has_quirk(pci_get_devid(dev), 2484 PCI_QUIRK_ENABLE_MSI_VM)); 2485 } 2486 return (1); 2487 } 2488 2489 dev = pci_find_bsf(0, 0, 0); 2490 if (dev != NULL) 2491 return (pci_msi_device_blacklisted(dev)); 2492 return (0); 2493 } 2494 2495 /* 2496 * Returns true if the specified device is blacklisted because MSI-X 2497 * doesn't work. Note that this assumes that if MSI doesn't work, 2498 * MSI-X doesn't either. 2499 */ 2500 int 2501 pci_msix_device_blacklisted(device_t dev) 2502 { 2503 2504 if (!pci_honor_msi_blacklist) 2505 return (0); 2506 2507 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX)) 2508 return (1); 2509 2510 return (pci_msi_device_blacklisted(dev)); 2511 } 2512 2513 /* 2514 * Determine if MSI-X is blacklisted globally on this system. If MSI 2515 * is blacklisted, assume that MSI-X is as well. Check for additional 2516 * chipsets where MSI works but MSI-X does not. 2517 */ 2518 static int 2519 pci_msix_blacklisted(void) 2520 { 2521 device_t dev; 2522 2523 if (!pci_honor_msi_blacklist) 2524 return (0); 2525 2526 dev = pci_find_bsf(0, 0, 0); 2527 if (dev != NULL && pci_has_quirk(pci_get_devid(dev), 2528 PCI_QUIRK_DISABLE_MSIX)) 2529 return (1); 2530 2531 return (pci_msi_blacklisted()); 2532 } 2533 2534 /* 2535 * Attempt to allocate *count MSI messages. The actual number allocated is 2536 * returned in *count. After this function returns, each message will be 2537 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 2538 */ 2539 int 2540 pci_alloc_msi_method(device_t dev, device_t child, int *count) 2541 { 2542 struct pci_devinfo *dinfo = device_get_ivars(child); 2543 pcicfgregs *cfg = &dinfo->cfg; 2544 struct resource_list_entry *rle; 2545 int actual, error, i, irqs[32]; 2546 uint16_t ctrl; 2547 2548 /* Don't let count == 0 get us into trouble. */ 2549 if (*count == 0) 2550 return (EINVAL); 2551 2552 /* If rid 0 is allocated, then fail. */ 2553 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 2554 if (rle != NULL && rle->res != NULL) 2555 return (ENXIO); 2556 2557 /* Already have allocated messages? */ 2558 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 2559 return (ENXIO); 2560 2561 /* If MSI is blacklisted for this system, fail. */ 2562 if (pci_msi_blacklisted()) 2563 return (ENXIO); 2564 2565 /* MSI capability present? */ 2566 if (cfg->msi.msi_location == 0 || !pci_do_msi) 2567 return (ENODEV); 2568 2569 if (bootverbose) 2570 device_printf(child, 2571 "attempting to allocate %d MSI vectors (%d supported)\n", 2572 *count, cfg->msi.msi_msgnum); 2573 2574 /* Don't ask for more than the device supports. */ 2575 actual = min(*count, cfg->msi.msi_msgnum); 2576 2577 /* Don't ask for more than 32 messages. */ 2578 actual = min(actual, 32); 2579 2580 /* MSI requires power of 2 number of messages. */ 2581 if (!powerof2(actual)) 2582 return (EINVAL); 2583 2584 for (;;) { 2585 /* Try to allocate N messages. */ 2586 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 2587 actual, irqs); 2588 if (error == 0) 2589 break; 2590 if (actual == 1) 2591 return (error); 2592 2593 /* Try N / 2. */ 2594 actual >>= 1; 2595 } 2596 2597 /* 2598 * We now have N actual messages mapped onto SYS_RES_IRQ 2599 * resources in the irqs[] array, so add new resources 2600 * starting at rid 1. 2601 */ 2602 for (i = 0; i < actual; i++) 2603 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 2604 irqs[i], irqs[i], 1); 2605 2606 if (bootverbose) { 2607 if (actual == 1) 2608 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 2609 else { 2610 int run; 2611 2612 /* 2613 * Be fancy and try to print contiguous runs 2614 * of IRQ values as ranges. 'run' is true if 2615 * we are in a range. 2616 */ 2617 device_printf(child, "using IRQs %d", irqs[0]); 2618 run = 0; 2619 for (i = 1; i < actual; i++) { 2620 /* Still in a run? */ 2621 if (irqs[i] == irqs[i - 1] + 1) { 2622 run = 1; 2623 continue; 2624 } 2625 2626 /* Finish previous range. */ 2627 if (run) { 2628 printf("-%d", irqs[i - 1]); 2629 run = 0; 2630 } 2631 2632 /* Start new range. */ 2633 printf(",%d", irqs[i]); 2634 } 2635 2636 /* Unfinished range? */ 2637 if (run) 2638 printf("-%d", irqs[actual - 1]); 2639 printf(" for MSI\n"); 2640 } 2641 } 2642 2643 /* Update control register with actual count. */ 2644 ctrl = cfg->msi.msi_ctrl; 2645 ctrl &= ~PCIM_MSICTRL_MME_MASK; 2646 ctrl |= (ffs(actual) - 1) << 4; 2647 cfg->msi.msi_ctrl = ctrl; 2648 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 2649 2650 /* Update counts of alloc'd messages. */ 2651 cfg->msi.msi_alloc = actual; 2652 cfg->msi.msi_handlers = 0; 2653 *count = actual; 2654 return (0); 2655 } 2656 2657 /* Release the MSI messages associated with this device. */ 2658 int 2659 pci_release_msi_method(device_t dev, device_t child) 2660 { 2661 struct pci_devinfo *dinfo = device_get_ivars(child); 2662 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2663 struct resource_list_entry *rle; 2664 int error, i, irqs[32]; 2665 2666 /* Try MSI-X first. */ 2667 error = pci_release_msix(dev, child); 2668 if (error != ENODEV) 2669 return (error); 2670 2671 /* Do we have any messages to release? */ 2672 if (msi->msi_alloc == 0) 2673 return (ENODEV); 2674 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); 2675 2676 /* Make sure none of the resources are allocated. */ 2677 if (msi->msi_handlers > 0) 2678 return (EBUSY); 2679 for (i = 0; i < msi->msi_alloc; i++) { 2680 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2681 KASSERT(rle != NULL, ("missing MSI resource")); 2682 if (rle->res != NULL) 2683 return (EBUSY); 2684 irqs[i] = rle->start; 2685 } 2686 2687 /* Update control register with 0 count. */ 2688 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), 2689 ("%s: MSI still enabled", __func__)); 2690 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; 2691 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2692 msi->msi_ctrl, 2); 2693 2694 /* Release the messages. */ 2695 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); 2696 for (i = 0; i < msi->msi_alloc; i++) 2697 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2698 2699 /* Update alloc count. */ 2700 msi->msi_alloc = 0; 2701 msi->msi_addr = 0; 2702 msi->msi_data = 0; 2703 return (0); 2704 } 2705 2706 /* 2707 * Return the max supported MSI messages this device supports. 2708 * Basically, assuming the MD code can alloc messages, this function 2709 * should return the maximum value that pci_alloc_msi() can return. 2710 * Thus, it is subject to the tunables, etc. 2711 */ 2712 int 2713 pci_msi_count_method(device_t dev, device_t child) 2714 { 2715 struct pci_devinfo *dinfo = device_get_ivars(child); 2716 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2717 2718 if (pci_do_msi && msi->msi_location != 0) 2719 return (msi->msi_msgnum); 2720 return (0); 2721 } 2722 2723 /* free pcicfgregs structure and all depending data structures */ 2724 2725 int 2726 pci_freecfg(struct pci_devinfo *dinfo) 2727 { 2728 struct devlist *devlist_head; 2729 struct pci_map *pm, *next; 2730 int i; 2731 2732 devlist_head = &pci_devq; 2733 2734 if (dinfo->cfg.vpd.vpd_reg) { 2735 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF); 2736 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++) 2737 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF); 2738 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF); 2739 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++) 2740 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF); 2741 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF); 2742 } 2743 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { 2744 free(pm, M_DEVBUF); 2745 } 2746 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 2747 free(dinfo, M_DEVBUF); 2748 2749 /* increment the generation count */ 2750 pci_generation++; 2751 2752 /* we're losing one device */ 2753 pci_numdevs--; 2754 return (0); 2755 } 2756 2757 /* 2758 * PCI power manangement 2759 */ 2760 int 2761 pci_set_powerstate_method(device_t dev, device_t child, int state) 2762 { 2763 struct pci_devinfo *dinfo = device_get_ivars(child); 2764 pcicfgregs *cfg = &dinfo->cfg; 2765 uint16_t status; 2766 int oldstate, highest, delay; 2767 2768 if (cfg->pp.pp_cap == 0) 2769 return (EOPNOTSUPP); 2770 2771 /* 2772 * Optimize a no state change request away. While it would be OK to 2773 * write to the hardware in theory, some devices have shown odd 2774 * behavior when going from D3 -> D3. 2775 */ 2776 oldstate = pci_get_powerstate(child); 2777 if (oldstate == state) 2778 return (0); 2779 2780 /* 2781 * The PCI power management specification states that after a state 2782 * transition between PCI power states, system software must 2783 * guarantee a minimal delay before the function accesses the device. 2784 * Compute the worst case delay that we need to guarantee before we 2785 * access the device. Many devices will be responsive much more 2786 * quickly than this delay, but there are some that don't respond 2787 * instantly to state changes. Transitions to/from D3 state require 2788 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 2789 * is done below with DELAY rather than a sleeper function because 2790 * this function can be called from contexts where we cannot sleep. 2791 */ 2792 highest = (oldstate > state) ? oldstate : state; 2793 if (highest == PCI_POWERSTATE_D3) 2794 delay = 10000; 2795 else if (highest == PCI_POWERSTATE_D2) 2796 delay = 200; 2797 else 2798 delay = 0; 2799 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 2800 & ~PCIM_PSTAT_DMASK; 2801 switch (state) { 2802 case PCI_POWERSTATE_D0: 2803 status |= PCIM_PSTAT_D0; 2804 break; 2805 case PCI_POWERSTATE_D1: 2806 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 2807 return (EOPNOTSUPP); 2808 status |= PCIM_PSTAT_D1; 2809 break; 2810 case PCI_POWERSTATE_D2: 2811 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 2812 return (EOPNOTSUPP); 2813 status |= PCIM_PSTAT_D2; 2814 break; 2815 case PCI_POWERSTATE_D3: 2816 status |= PCIM_PSTAT_D3; 2817 break; 2818 default: 2819 return (EINVAL); 2820 } 2821 2822 if (bootverbose) 2823 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate, 2824 state); 2825 2826 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 2827 if (delay) 2828 DELAY(delay); 2829 return (0); 2830 } 2831 2832 int 2833 pci_get_powerstate_method(device_t dev, device_t child) 2834 { 2835 struct pci_devinfo *dinfo = device_get_ivars(child); 2836 pcicfgregs *cfg = &dinfo->cfg; 2837 uint16_t status; 2838 int result; 2839 2840 if (cfg->pp.pp_cap != 0) { 2841 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 2842 switch (status & PCIM_PSTAT_DMASK) { 2843 case PCIM_PSTAT_D0: 2844 result = PCI_POWERSTATE_D0; 2845 break; 2846 case PCIM_PSTAT_D1: 2847 result = PCI_POWERSTATE_D1; 2848 break; 2849 case PCIM_PSTAT_D2: 2850 result = PCI_POWERSTATE_D2; 2851 break; 2852 case PCIM_PSTAT_D3: 2853 result = PCI_POWERSTATE_D3; 2854 break; 2855 default: 2856 result = PCI_POWERSTATE_UNKNOWN; 2857 break; 2858 } 2859 } else { 2860 /* No support, device is always at D0 */ 2861 result = PCI_POWERSTATE_D0; 2862 } 2863 return (result); 2864 } 2865 2866 /* 2867 * Some convenience functions for PCI device drivers. 2868 */ 2869 2870 static __inline void 2871 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 2872 { 2873 uint16_t command; 2874 2875 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2876 command |= bit; 2877 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2878 } 2879 2880 static __inline void 2881 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 2882 { 2883 uint16_t command; 2884 2885 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2886 command &= ~bit; 2887 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2888 } 2889 2890 int 2891 pci_enable_busmaster_method(device_t dev, device_t child) 2892 { 2893 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2894 return (0); 2895 } 2896 2897 int 2898 pci_disable_busmaster_method(device_t dev, device_t child) 2899 { 2900 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2901 return (0); 2902 } 2903 2904 int 2905 pci_enable_io_method(device_t dev, device_t child, int space) 2906 { 2907 uint16_t bit; 2908 2909 switch(space) { 2910 case SYS_RES_IOPORT: 2911 bit = PCIM_CMD_PORTEN; 2912 break; 2913 case SYS_RES_MEMORY: 2914 bit = PCIM_CMD_MEMEN; 2915 break; 2916 default: 2917 return (EINVAL); 2918 } 2919 pci_set_command_bit(dev, child, bit); 2920 return (0); 2921 } 2922 2923 int 2924 pci_disable_io_method(device_t dev, device_t child, int space) 2925 { 2926 uint16_t bit; 2927 2928 switch(space) { 2929 case SYS_RES_IOPORT: 2930 bit = PCIM_CMD_PORTEN; 2931 break; 2932 case SYS_RES_MEMORY: 2933 bit = PCIM_CMD_MEMEN; 2934 break; 2935 default: 2936 return (EINVAL); 2937 } 2938 pci_clear_command_bit(dev, child, bit); 2939 return (0); 2940 } 2941 2942 /* 2943 * New style pci driver. Parent device is either a pci-host-bridge or a 2944 * pci-pci-bridge. Both kinds are represented by instances of pcib. 2945 */ 2946 2947 void 2948 pci_print_verbose(struct pci_devinfo *dinfo) 2949 { 2950 2951 if (bootverbose) { 2952 pcicfgregs *cfg = &dinfo->cfg; 2953 2954 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 2955 cfg->vendor, cfg->device, cfg->revid); 2956 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n", 2957 cfg->domain, cfg->bus, cfg->slot, cfg->func); 2958 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 2959 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 2960 cfg->mfdev); 2961 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 2962 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 2963 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 2964 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 2965 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 2966 if (cfg->intpin > 0) 2967 printf("\tintpin=%c, irq=%d\n", 2968 cfg->intpin +'a' -1, cfg->intline); 2969 if (cfg->pp.pp_cap) { 2970 uint16_t status; 2971 2972 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 2973 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 2974 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 2975 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 2976 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 2977 status & PCIM_PSTAT_DMASK); 2978 } 2979 if (cfg->msi.msi_location) { 2980 int ctrl; 2981 2982 ctrl = cfg->msi.msi_ctrl; 2983 printf("\tMSI supports %d message%s%s%s\n", 2984 cfg->msi.msi_msgnum, 2985 (cfg->msi.msi_msgnum == 1) ? "" : "s", 2986 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 2987 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 2988 } 2989 if (cfg->msix.msix_location) { 2990 printf("\tMSI-X supports %d message%s ", 2991 cfg->msix.msix_msgnum, 2992 (cfg->msix.msix_msgnum == 1) ? "" : "s"); 2993 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 2994 printf("in map 0x%x\n", 2995 cfg->msix.msix_table_bar); 2996 else 2997 printf("in maps 0x%x and 0x%x\n", 2998 cfg->msix.msix_table_bar, 2999 cfg->msix.msix_pba_bar); 3000 } 3001 } 3002 } 3003 3004 static int 3005 pci_porten(device_t dev) 3006 { 3007 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0; 3008 } 3009 3010 static int 3011 pci_memen(device_t dev) 3012 { 3013 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0; 3014 } 3015 3016 void 3017 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, 3018 int *bar64) 3019 { 3020 struct pci_devinfo *dinfo; 3021 pci_addr_t map, testval; 3022 int ln2range; 3023 uint16_t cmd; 3024 3025 /* 3026 * The device ROM BAR is special. It is always a 32-bit 3027 * memory BAR. Bit 0 is special and should not be set when 3028 * sizing the BAR. 3029 */ 3030 dinfo = device_get_ivars(dev); 3031 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { 3032 map = pci_read_config(dev, reg, 4); 3033 pci_write_config(dev, reg, 0xfffffffe, 4); 3034 testval = pci_read_config(dev, reg, 4); 3035 pci_write_config(dev, reg, map, 4); 3036 *mapp = map; 3037 *testvalp = testval; 3038 if (bar64 != NULL) 3039 *bar64 = 0; 3040 return; 3041 } 3042 3043 map = pci_read_config(dev, reg, 4); 3044 ln2range = pci_maprange(map); 3045 if (ln2range == 64) 3046 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3047 3048 /* 3049 * Disable decoding via the command register before 3050 * determining the BAR's length since we will be placing it in 3051 * a weird state. 3052 */ 3053 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3054 pci_write_config(dev, PCIR_COMMAND, 3055 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 3056 3057 /* 3058 * Determine the BAR's length by writing all 1's. The bottom 3059 * log_2(size) bits of the BAR will stick as 0 when we read 3060 * the value back. 3061 * 3062 * NB: according to the PCI Local Bus Specification, rev. 3.0: 3063 * "Software writes 0FFFFFFFFh to both registers, reads them back, 3064 * and combines the result into a 64-bit value." (section 6.2.5.1) 3065 * 3066 * Writes to both registers must be performed before attempting to 3067 * read back the size value. 3068 */ 3069 testval = 0; 3070 pci_write_config(dev, reg, 0xffffffff, 4); 3071 if (ln2range == 64) { 3072 pci_write_config(dev, reg + 4, 0xffffffff, 4); 3073 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3074 } 3075 testval |= pci_read_config(dev, reg, 4); 3076 3077 /* 3078 * Restore the original value of the BAR. We may have reprogrammed 3079 * the BAR of the low-level console device and when booting verbose, 3080 * we need the console device addressable. 3081 */ 3082 pci_write_config(dev, reg, map, 4); 3083 if (ln2range == 64) 3084 pci_write_config(dev, reg + 4, map >> 32, 4); 3085 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3086 3087 *mapp = map; 3088 *testvalp = testval; 3089 if (bar64 != NULL) 3090 *bar64 = (ln2range == 64); 3091 } 3092 3093 static void 3094 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base) 3095 { 3096 struct pci_devinfo *dinfo; 3097 int ln2range; 3098 3099 /* The device ROM BAR is always a 32-bit memory BAR. */ 3100 dinfo = device_get_ivars(dev); 3101 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3102 ln2range = 32; 3103 else 3104 ln2range = pci_maprange(pm->pm_value); 3105 pci_write_config(dev, pm->pm_reg, base, 4); 3106 if (ln2range == 64) 3107 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); 3108 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); 3109 if (ln2range == 64) 3110 pm->pm_value |= (pci_addr_t)pci_read_config(dev, 3111 pm->pm_reg + 4, 4) << 32; 3112 } 3113 3114 struct pci_map * 3115 pci_find_bar(device_t dev, int reg) 3116 { 3117 struct pci_devinfo *dinfo; 3118 struct pci_map *pm; 3119 3120 dinfo = device_get_ivars(dev); 3121 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3122 if (pm->pm_reg == reg) 3123 return (pm); 3124 } 3125 return (NULL); 3126 } 3127 3128 int 3129 pci_bar_enabled(device_t dev, struct pci_map *pm) 3130 { 3131 struct pci_devinfo *dinfo; 3132 uint16_t cmd; 3133 3134 dinfo = device_get_ivars(dev); 3135 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && 3136 !(pm->pm_value & PCIM_BIOS_ENABLE)) 3137 return (0); 3138 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3139 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) 3140 return ((cmd & PCIM_CMD_MEMEN) != 0); 3141 else 3142 return ((cmd & PCIM_CMD_PORTEN) != 0); 3143 } 3144 3145 struct pci_map * 3146 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size) 3147 { 3148 struct pci_devinfo *dinfo; 3149 struct pci_map *pm, *prev; 3150 3151 dinfo = device_get_ivars(dev); 3152 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO); 3153 pm->pm_reg = reg; 3154 pm->pm_value = value; 3155 pm->pm_size = size; 3156 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { 3157 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", 3158 reg)); 3159 if (STAILQ_NEXT(prev, pm_link) == NULL || 3160 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) 3161 break; 3162 } 3163 if (prev != NULL) 3164 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); 3165 else 3166 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); 3167 return (pm); 3168 } 3169 3170 static void 3171 pci_restore_bars(device_t dev) 3172 { 3173 struct pci_devinfo *dinfo; 3174 struct pci_map *pm; 3175 int ln2range; 3176 3177 dinfo = device_get_ivars(dev); 3178 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3179 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3180 ln2range = 32; 3181 else 3182 ln2range = pci_maprange(pm->pm_value); 3183 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); 3184 if (ln2range == 64) 3185 pci_write_config(dev, pm->pm_reg + 4, 3186 pm->pm_value >> 32, 4); 3187 } 3188 } 3189 3190 /* 3191 * Add a resource based on a pci map register. Return 1 if the map 3192 * register is a 32bit map register or 2 if it is a 64bit register. 3193 */ 3194 static int 3195 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, 3196 int force, int prefetch) 3197 { 3198 struct pci_map *pm; 3199 pci_addr_t base, map, testval; 3200 pci_addr_t start, end, count; 3201 int barlen, basezero, flags, maprange, mapsize, type; 3202 uint16_t cmd; 3203 struct resource *res; 3204 3205 /* 3206 * The BAR may already exist if the device is a CardBus card 3207 * whose CIS is stored in this BAR. 3208 */ 3209 pm = pci_find_bar(dev, reg); 3210 if (pm != NULL) { 3211 maprange = pci_maprange(pm->pm_value); 3212 barlen = maprange == 64 ? 2 : 1; 3213 return (barlen); 3214 } 3215 3216 pci_read_bar(dev, reg, &map, &testval, NULL); 3217 if (PCI_BAR_MEM(map)) { 3218 type = SYS_RES_MEMORY; 3219 if (map & PCIM_BAR_MEM_PREFETCH) 3220 prefetch = 1; 3221 } else 3222 type = SYS_RES_IOPORT; 3223 mapsize = pci_mapsize(testval); 3224 base = pci_mapbase(map); 3225 #ifdef __PCI_BAR_ZERO_VALID 3226 basezero = 0; 3227 #else 3228 basezero = base == 0; 3229 #endif 3230 maprange = pci_maprange(map); 3231 barlen = maprange == 64 ? 2 : 1; 3232 3233 /* 3234 * For I/O registers, if bottom bit is set, and the next bit up 3235 * isn't clear, we know we have a BAR that doesn't conform to the 3236 * spec, so ignore it. Also, sanity check the size of the data 3237 * areas to the type of memory involved. Memory must be at least 3238 * 16 bytes in size, while I/O ranges must be at least 4. 3239 */ 3240 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0) 3241 return (barlen); 3242 if ((type == SYS_RES_MEMORY && mapsize < 4) || 3243 (type == SYS_RES_IOPORT && mapsize < 2)) 3244 return (barlen); 3245 3246 /* Save a record of this BAR. */ 3247 pm = pci_add_bar(dev, reg, map, mapsize); 3248 if (bootverbose) { 3249 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d", 3250 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize); 3251 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3252 printf(", port disabled\n"); 3253 else if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3254 printf(", memory disabled\n"); 3255 else 3256 printf(", enabled\n"); 3257 } 3258 3259 /* 3260 * If base is 0, then we have problems if this architecture does 3261 * not allow that. It is best to ignore such entries for the 3262 * moment. These will be allocated later if the driver specifically 3263 * requests them. However, some removable buses look better when 3264 * all resources are allocated, so allow '0' to be overriden. 3265 * 3266 * Similarly treat maps whose values is the same as the test value 3267 * read back. These maps have had all f's written to them by the 3268 * BIOS in an attempt to disable the resources. 3269 */ 3270 if (!force && (basezero || map == testval)) 3271 return (barlen); 3272 if ((u_long)base != base) { 3273 device_printf(bus, 3274 "pci%d:%d:%d:%d bar %#x too many address bits", 3275 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev), 3276 pci_get_function(dev), reg); 3277 return (barlen); 3278 } 3279 3280 /* 3281 * This code theoretically does the right thing, but has 3282 * undesirable side effects in some cases where peripherals 3283 * respond oddly to having these bits enabled. Let the user 3284 * be able to turn them off (since pci_enable_io_modes is 1 by 3285 * default). 3286 */ 3287 if (pci_enable_io_modes) { 3288 /* Turn on resources that have been left off by a lazy BIOS */ 3289 if (type == SYS_RES_IOPORT && !pci_porten(dev)) { 3290 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3291 cmd |= PCIM_CMD_PORTEN; 3292 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3293 } 3294 if (type == SYS_RES_MEMORY && !pci_memen(dev)) { 3295 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3296 cmd |= PCIM_CMD_MEMEN; 3297 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3298 } 3299 } else { 3300 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3301 return (barlen); 3302 if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3303 return (barlen); 3304 } 3305 3306 count = (pci_addr_t)1 << mapsize; 3307 flags = RF_ALIGNMENT_LOG2(mapsize); 3308 if (prefetch) 3309 flags |= RF_PREFETCHABLE; 3310 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) { 3311 start = 0; /* Let the parent decide. */ 3312 end = ~0; 3313 } else { 3314 start = base; 3315 end = base + count - 1; 3316 } 3317 resource_list_add(rl, type, reg, start, end, count); 3318 3319 /* 3320 * Try to allocate the resource for this BAR from our parent 3321 * so that this resource range is already reserved. The 3322 * driver for this device will later inherit this resource in 3323 * pci_alloc_resource(). 3324 */ 3325 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count, 3326 flags); 3327 if ((pci_do_realloc_bars 3328 || pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_REALLOC_BAR)) 3329 && res == NULL && (start != 0 || end != ~0)) { 3330 /* 3331 * If the allocation fails, try to allocate a resource for 3332 * this BAR using any available range. The firmware felt 3333 * it was important enough to assign a resource, so don't 3334 * disable decoding if we can help it. 3335 */ 3336 resource_list_delete(rl, type, reg); 3337 resource_list_add(rl, type, reg, 0, ~0, count); 3338 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0, 3339 count, flags); 3340 } 3341 if (res == NULL) { 3342 /* 3343 * If the allocation fails, delete the resource list entry 3344 * and disable decoding for this device. 3345 * 3346 * If the driver requests this resource in the future, 3347 * pci_reserve_map() will try to allocate a fresh 3348 * resource range. 3349 */ 3350 resource_list_delete(rl, type, reg); 3351 pci_disable_io(dev, type); 3352 if (bootverbose) 3353 device_printf(bus, 3354 "pci%d:%d:%d:%d bar %#x failed to allocate\n", 3355 pci_get_domain(dev), pci_get_bus(dev), 3356 pci_get_slot(dev), pci_get_function(dev), reg); 3357 } else { 3358 start = rman_get_start(res); 3359 pci_write_bar(dev, pm, start); 3360 } 3361 return (barlen); 3362 } 3363 3364 /* 3365 * For ATA devices we need to decide early what addressing mode to use. 3366 * Legacy demands that the primary and secondary ATA ports sits on the 3367 * same addresses that old ISA hardware did. This dictates that we use 3368 * those addresses and ignore the BAR's if we cannot set PCI native 3369 * addressing mode. 3370 */ 3371 static void 3372 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, 3373 uint32_t prefetchmask) 3374 { 3375 int rid, type, progif; 3376 #if 0 3377 /* if this device supports PCI native addressing use it */ 3378 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3379 if ((progif & 0x8a) == 0x8a) { 3380 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 3381 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 3382 printf("Trying ATA native PCI addressing mode\n"); 3383 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 3384 } 3385 } 3386 #endif 3387 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3388 type = SYS_RES_IOPORT; 3389 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 3390 pci_add_map(bus, dev, PCIR_BAR(0), rl, force, 3391 prefetchmask & (1 << 0)); 3392 pci_add_map(bus, dev, PCIR_BAR(1), rl, force, 3393 prefetchmask & (1 << 1)); 3394 } else { 3395 rid = PCIR_BAR(0); 3396 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 3397 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0, 3398 0x1f7, 8, 0); 3399 rid = PCIR_BAR(1); 3400 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 3401 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6, 3402 0x3f6, 1, 0); 3403 } 3404 if (progif & PCIP_STORAGE_IDE_MODESEC) { 3405 pci_add_map(bus, dev, PCIR_BAR(2), rl, force, 3406 prefetchmask & (1 << 2)); 3407 pci_add_map(bus, dev, PCIR_BAR(3), rl, force, 3408 prefetchmask & (1 << 3)); 3409 } else { 3410 rid = PCIR_BAR(2); 3411 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 3412 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170, 3413 0x177, 8, 0); 3414 rid = PCIR_BAR(3); 3415 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 3416 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376, 3417 0x376, 1, 0); 3418 } 3419 pci_add_map(bus, dev, PCIR_BAR(4), rl, force, 3420 prefetchmask & (1 << 4)); 3421 pci_add_map(bus, dev, PCIR_BAR(5), rl, force, 3422 prefetchmask & (1 << 5)); 3423 } 3424 3425 static void 3426 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 3427 { 3428 struct pci_devinfo *dinfo = device_get_ivars(dev); 3429 pcicfgregs *cfg = &dinfo->cfg; 3430 char tunable_name[64]; 3431 int irq; 3432 3433 /* Has to have an intpin to have an interrupt. */ 3434 if (cfg->intpin == 0) 3435 return; 3436 3437 /* Let the user override the IRQ with a tunable. */ 3438 irq = PCI_INVALID_IRQ; 3439 snprintf(tunable_name, sizeof(tunable_name), 3440 "hw.pci%d.%d.%d.INT%c.irq", 3441 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 3442 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 3443 irq = PCI_INVALID_IRQ; 3444 3445 /* 3446 * If we didn't get an IRQ via the tunable, then we either use the 3447 * IRQ value in the intline register or we ask the bus to route an 3448 * interrupt for us. If force_route is true, then we only use the 3449 * value in the intline register if the bus was unable to assign an 3450 * IRQ. 3451 */ 3452 if (!PCI_INTERRUPT_VALID(irq)) { 3453 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 3454 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 3455 if (!PCI_INTERRUPT_VALID(irq)) 3456 irq = cfg->intline; 3457 } 3458 3459 /* If after all that we don't have an IRQ, just bail. */ 3460 if (!PCI_INTERRUPT_VALID(irq)) 3461 return; 3462 3463 /* Update the config register if it changed. */ 3464 if (irq != cfg->intline) { 3465 cfg->intline = irq; 3466 pci_write_config(dev, PCIR_INTLINE, irq, 1); 3467 } 3468 3469 /* Add this IRQ as rid 0 interrupt resource. */ 3470 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 3471 } 3472 3473 /* Perform early OHCI takeover from SMM. */ 3474 static void 3475 ohci_early_takeover(device_t self) 3476 { 3477 struct resource *res; 3478 uint32_t ctl; 3479 int rid; 3480 int i; 3481 3482 rid = PCIR_BAR(0); 3483 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3484 if (res == NULL) 3485 return; 3486 3487 ctl = bus_read_4(res, OHCI_CONTROL); 3488 if (ctl & OHCI_IR) { 3489 if (bootverbose) 3490 printf("ohci early: " 3491 "SMM active, request owner change\n"); 3492 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR); 3493 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 3494 DELAY(1000); 3495 ctl = bus_read_4(res, OHCI_CONTROL); 3496 } 3497 if (ctl & OHCI_IR) { 3498 if (bootverbose) 3499 printf("ohci early: " 3500 "SMM does not respond, resetting\n"); 3501 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET); 3502 } 3503 /* Disable interrupts */ 3504 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 3505 } 3506 3507 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3508 } 3509 3510 /* Perform early UHCI takeover from SMM. */ 3511 static void 3512 uhci_early_takeover(device_t self) 3513 { 3514 struct resource *res; 3515 int rid; 3516 3517 /* 3518 * Set the PIRQD enable bit and switch off all the others. We don't 3519 * want legacy support to interfere with us XXX Does this also mean 3520 * that the BIOS won't touch the keyboard anymore if it is connected 3521 * to the ports of the root hub? 3522 */ 3523 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2); 3524 3525 /* Disable interrupts */ 3526 rid = PCI_UHCI_BASE_REG; 3527 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE); 3528 if (res != NULL) { 3529 bus_write_2(res, UHCI_INTR, 0); 3530 bus_release_resource(self, SYS_RES_IOPORT, rid, res); 3531 } 3532 } 3533 3534 /* Perform early EHCI takeover from SMM. */ 3535 static void 3536 ehci_early_takeover(device_t self) 3537 { 3538 struct resource *res; 3539 uint32_t cparams; 3540 uint32_t eec; 3541 uint8_t eecp; 3542 uint8_t bios_sem; 3543 uint8_t offs; 3544 int rid; 3545 int i; 3546 3547 rid = PCIR_BAR(0); 3548 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3549 if (res == NULL) 3550 return; 3551 3552 cparams = bus_read_4(res, EHCI_HCCPARAMS); 3553 3554 /* Synchronise with the BIOS if it owns the controller. */ 3555 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0; 3556 eecp = EHCI_EECP_NEXT(eec)) { 3557 eec = pci_read_config(self, eecp, 4); 3558 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) { 3559 continue; 3560 } 3561 bios_sem = pci_read_config(self, eecp + 3562 EHCI_LEGSUP_BIOS_SEM, 1); 3563 if (bios_sem == 0) { 3564 continue; 3565 } 3566 if (bootverbose) 3567 printf("ehci early: " 3568 "SMM active, request owner change\n"); 3569 3570 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1); 3571 3572 for (i = 0; (i < 100) && (bios_sem != 0); i++) { 3573 DELAY(1000); 3574 bios_sem = pci_read_config(self, eecp + 3575 EHCI_LEGSUP_BIOS_SEM, 1); 3576 } 3577 3578 if (bios_sem != 0) { 3579 if (bootverbose) 3580 printf("ehci early: " 3581 "SMM does not respond\n"); 3582 } 3583 /* Disable interrupts */ 3584 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION)); 3585 bus_write_4(res, offs + EHCI_USBINTR, 0); 3586 } 3587 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3588 } 3589 3590 /* Perform early XHCI takeover from SMM. */ 3591 static void 3592 xhci_early_takeover(device_t self) 3593 { 3594 struct resource *res; 3595 uint32_t cparams; 3596 uint32_t eec; 3597 uint8_t eecp; 3598 uint8_t bios_sem; 3599 uint8_t offs; 3600 int rid; 3601 int i; 3602 3603 rid = PCIR_BAR(0); 3604 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3605 if (res == NULL) 3606 return; 3607 3608 cparams = bus_read_4(res, XHCI_HCSPARAMS0); 3609 3610 eec = -1; 3611 3612 /* Synchronise with the BIOS if it owns the controller. */ 3613 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 3614 eecp += XHCI_XECP_NEXT(eec) << 2) { 3615 eec = bus_read_4(res, eecp); 3616 3617 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 3618 continue; 3619 3620 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM); 3621 if (bios_sem == 0) 3622 continue; 3623 3624 if (bootverbose) 3625 printf("xhci early: " 3626 "SMM active, request owner change\n"); 3627 3628 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1); 3629 3630 /* wait a maximum of 5 second */ 3631 3632 for (i = 0; (i < 5000) && (bios_sem != 0); i++) { 3633 DELAY(1000); 3634 bios_sem = bus_read_1(res, eecp + 3635 XHCI_XECP_BIOS_SEM); 3636 } 3637 3638 if (bios_sem != 0) { 3639 if (bootverbose) 3640 printf("xhci early: " 3641 "SMM does not respond\n"); 3642 } 3643 3644 /* Disable interrupts */ 3645 offs = bus_read_1(res, XHCI_CAPLENGTH); 3646 bus_write_4(res, offs + XHCI_USBCMD, 0); 3647 bus_read_4(res, offs + XHCI_USBSTS); 3648 } 3649 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3650 } 3651 3652 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 3653 static void 3654 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg, 3655 struct resource_list *rl) 3656 { 3657 struct resource *res; 3658 char *cp; 3659 rman_res_t start, end, count; 3660 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus; 3661 3662 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3663 case PCIM_HDRTYPE_BRIDGE: 3664 sec_reg = PCIR_SECBUS_1; 3665 sub_reg = PCIR_SUBBUS_1; 3666 break; 3667 case PCIM_HDRTYPE_CARDBUS: 3668 sec_reg = PCIR_SECBUS_2; 3669 sub_reg = PCIR_SUBBUS_2; 3670 break; 3671 default: 3672 return; 3673 } 3674 3675 /* 3676 * If the existing bus range is valid, attempt to reserve it 3677 * from our parent. If this fails for any reason, clear the 3678 * secbus and subbus registers. 3679 * 3680 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus? 3681 * This would at least preserve the existing sec_bus if it is 3682 * valid. 3683 */ 3684 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1); 3685 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1); 3686 3687 /* Quirk handling. */ 3688 switch (pci_get_devid(dev)) { 3689 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 3690 sup_bus = pci_read_config(dev, 0x41, 1); 3691 if (sup_bus != 0xff) { 3692 sec_bus = sup_bus + 1; 3693 sub_bus = sup_bus + 1; 3694 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1); 3695 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3696 } 3697 break; 3698 3699 case 0x00dd10de: 3700 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 3701 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 3702 break; 3703 if (strncmp(cp, "Compal", 6) != 0) { 3704 freeenv(cp); 3705 break; 3706 } 3707 freeenv(cp); 3708 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 3709 break; 3710 if (strncmp(cp, "08A0", 4) != 0) { 3711 freeenv(cp); 3712 break; 3713 } 3714 freeenv(cp); 3715 if (sub_bus < 0xa) { 3716 sub_bus = 0xa; 3717 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3718 } 3719 break; 3720 } 3721 3722 if (bootverbose) 3723 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus); 3724 if (sec_bus > 0 && sub_bus >= sec_bus) { 3725 start = sec_bus; 3726 end = sub_bus; 3727 count = end - start + 1; 3728 3729 resource_list_add(rl, PCI_RES_BUS, 0, 0, ~0, count); 3730 3731 /* 3732 * If requested, clear secondary bus registers in 3733 * bridge devices to force a complete renumbering 3734 * rather than reserving the existing range. However, 3735 * preserve the existing size. 3736 */ 3737 if (pci_clear_buses) 3738 goto clear; 3739 3740 rid = 0; 3741 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid, 3742 start, end, count, 0); 3743 if (res != NULL) 3744 return; 3745 3746 if (bootverbose) 3747 device_printf(bus, 3748 "pci%d:%d:%d:%d secbus failed to allocate\n", 3749 pci_get_domain(dev), pci_get_bus(dev), 3750 pci_get_slot(dev), pci_get_function(dev)); 3751 } 3752 3753 clear: 3754 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1); 3755 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1); 3756 } 3757 3758 static struct resource * 3759 pci_alloc_secbus(device_t dev, device_t child, int *rid, rman_res_t start, 3760 rman_res_t end, rman_res_t count, u_int flags) 3761 { 3762 struct pci_devinfo *dinfo; 3763 pcicfgregs *cfg; 3764 struct resource_list *rl; 3765 struct resource *res; 3766 int sec_reg, sub_reg; 3767 3768 dinfo = device_get_ivars(child); 3769 cfg = &dinfo->cfg; 3770 rl = &dinfo->resources; 3771 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3772 case PCIM_HDRTYPE_BRIDGE: 3773 sec_reg = PCIR_SECBUS_1; 3774 sub_reg = PCIR_SUBBUS_1; 3775 break; 3776 case PCIM_HDRTYPE_CARDBUS: 3777 sec_reg = PCIR_SECBUS_2; 3778 sub_reg = PCIR_SUBBUS_2; 3779 break; 3780 default: 3781 return (NULL); 3782 } 3783 3784 if (*rid != 0) 3785 return (NULL); 3786 3787 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL) 3788 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count); 3789 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) { 3790 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid, 3791 start, end, count, flags & ~RF_ACTIVE); 3792 if (res == NULL) { 3793 resource_list_delete(rl, PCI_RES_BUS, *rid); 3794 device_printf(child, "allocating %ju bus%s failed\n", 3795 count, count == 1 ? "" : "es"); 3796 return (NULL); 3797 } 3798 if (bootverbose) 3799 device_printf(child, 3800 "Lazy allocation of %ju bus%s at %ju\n", count, 3801 count == 1 ? "" : "es", rman_get_start(res)); 3802 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1); 3803 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1); 3804 } 3805 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start, 3806 end, count, flags)); 3807 } 3808 #endif 3809 3810 static int 3811 pci_ea_bei_to_rid(device_t dev, int bei) 3812 { 3813 #ifdef PCI_IOV 3814 struct pci_devinfo *dinfo; 3815 int iov_pos; 3816 struct pcicfg_iov *iov; 3817 3818 dinfo = device_get_ivars(dev); 3819 iov = dinfo->cfg.iov; 3820 if (iov != NULL) 3821 iov_pos = iov->iov_pos; 3822 else 3823 iov_pos = 0; 3824 #endif 3825 3826 /* Check if matches BAR */ 3827 if ((bei >= PCIM_EA_BEI_BAR_0) && 3828 (bei <= PCIM_EA_BEI_BAR_5)) 3829 return (PCIR_BAR(bei)); 3830 3831 /* Check ROM */ 3832 if (bei == PCIM_EA_BEI_ROM) 3833 return (PCIR_BIOS); 3834 3835 #ifdef PCI_IOV 3836 /* Check if matches VF_BAR */ 3837 if ((iov != NULL) && (bei >= PCIM_EA_BEI_VF_BAR_0) && 3838 (bei <= PCIM_EA_BEI_VF_BAR_5)) 3839 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) + 3840 iov_pos); 3841 #endif 3842 3843 return (-1); 3844 } 3845 3846 int 3847 pci_ea_is_enabled(device_t dev, int rid) 3848 { 3849 struct pci_ea_entry *ea; 3850 struct pci_devinfo *dinfo; 3851 3852 dinfo = device_get_ivars(dev); 3853 3854 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3855 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid) 3856 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0); 3857 } 3858 3859 return (0); 3860 } 3861 3862 void 3863 pci_add_resources_ea(device_t bus, device_t dev, int alloc_iov) 3864 { 3865 struct pci_ea_entry *ea; 3866 struct pci_devinfo *dinfo; 3867 pci_addr_t start, end, count; 3868 struct resource_list *rl; 3869 int type, flags, rid; 3870 struct resource *res; 3871 uint32_t tmp; 3872 #ifdef PCI_IOV 3873 struct pcicfg_iov *iov; 3874 #endif 3875 3876 dinfo = device_get_ivars(dev); 3877 rl = &dinfo->resources; 3878 flags = 0; 3879 3880 #ifdef PCI_IOV 3881 iov = dinfo->cfg.iov; 3882 #endif 3883 3884 if (dinfo->cfg.ea.ea_location == 0) 3885 return; 3886 3887 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3888 /* 3889 * TODO: Ignore EA-BAR if is not enabled. 3890 * Currently the EA implementation supports 3891 * only situation, where EA structure contains 3892 * predefined entries. In case they are not enabled 3893 * leave them unallocated and proceed with 3894 * a legacy-BAR mechanism. 3895 */ 3896 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0) 3897 continue; 3898 3899 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) { 3900 case PCIM_EA_P_MEM_PREFETCH: 3901 case PCIM_EA_P_VF_MEM_PREFETCH: 3902 flags = RF_PREFETCHABLE; 3903 /* FALLTHROUGH */ 3904 case PCIM_EA_P_VF_MEM: 3905 case PCIM_EA_P_MEM: 3906 type = SYS_RES_MEMORY; 3907 break; 3908 case PCIM_EA_P_IO: 3909 type = SYS_RES_IOPORT; 3910 break; 3911 default: 3912 continue; 3913 } 3914 3915 if (alloc_iov != 0) { 3916 #ifdef PCI_IOV 3917 /* Allocating IOV, confirm BEI matches */ 3918 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) || 3919 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5)) 3920 continue; 3921 #else 3922 continue; 3923 #endif 3924 } else { 3925 /* Allocating BAR, confirm BEI matches */ 3926 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) || 3927 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) && 3928 (ea->eae_bei != PCIM_EA_BEI_ROM)) 3929 continue; 3930 } 3931 3932 rid = pci_ea_bei_to_rid(dev, ea->eae_bei); 3933 if (rid < 0) 3934 continue; 3935 3936 /* Skip resources already allocated by EA */ 3937 if ((resource_list_find(rl, SYS_RES_MEMORY, rid) != NULL) || 3938 (resource_list_find(rl, SYS_RES_IOPORT, rid) != NULL)) 3939 continue; 3940 3941 start = ea->eae_base; 3942 count = ea->eae_max_offset + 1; 3943 #ifdef PCI_IOV 3944 if (iov != NULL) 3945 count = count * iov->iov_num_vfs; 3946 #endif 3947 end = start + count - 1; 3948 if (count == 0) 3949 continue; 3950 3951 resource_list_add(rl, type, rid, start, end, count); 3952 res = resource_list_reserve(rl, bus, dev, type, &rid, start, end, count, 3953 flags); 3954 if (res == NULL) { 3955 resource_list_delete(rl, type, rid); 3956 3957 /* 3958 * Failed to allocate using EA, disable entry. 3959 * Another attempt to allocation will be performed 3960 * further, but this time using legacy BAR registers 3961 */ 3962 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4); 3963 tmp &= ~PCIM_EA_ENABLE; 3964 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4); 3965 3966 /* 3967 * Disabling entry might fail in case it is hardwired. 3968 * Read flags again to match current status. 3969 */ 3970 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4); 3971 3972 continue; 3973 } 3974 3975 /* As per specification, fill BAR with zeros */ 3976 pci_write_config(dev, rid, 0, 4); 3977 } 3978 } 3979 3980 void 3981 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 3982 { 3983 struct pci_devinfo *dinfo; 3984 pcicfgregs *cfg; 3985 struct resource_list *rl; 3986 const struct pci_quirk *q; 3987 uint32_t devid; 3988 int i; 3989 3990 dinfo = device_get_ivars(dev); 3991 cfg = &dinfo->cfg; 3992 rl = &dinfo->resources; 3993 devid = (cfg->device << 16) | cfg->vendor; 3994 3995 /* Allocate resources using Enhanced Allocation */ 3996 pci_add_resources_ea(bus, dev, 0); 3997 3998 /* ATA devices needs special map treatment */ 3999 if ((pci_get_class(dev) == PCIC_STORAGE) && 4000 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 4001 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 4002 (!pci_read_config(dev, PCIR_BAR(0), 4) && 4003 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 4004 pci_ata_maps(bus, dev, rl, force, prefetchmask); 4005 else 4006 for (i = 0; i < cfg->nummaps;) { 4007 /* Skip resources already managed by EA */ 4008 if ((resource_list_find(rl, SYS_RES_MEMORY, PCIR_BAR(i)) != NULL) || 4009 (resource_list_find(rl, SYS_RES_IOPORT, PCIR_BAR(i)) != NULL) || 4010 pci_ea_is_enabled(dev, PCIR_BAR(i))) { 4011 i++; 4012 continue; 4013 } 4014 4015 /* 4016 * Skip quirked resources. 4017 */ 4018 for (q = &pci_quirks[0]; q->devid != 0; q++) 4019 if (q->devid == devid && 4020 q->type == PCI_QUIRK_UNMAP_REG && 4021 q->arg1 == PCIR_BAR(i)) 4022 break; 4023 if (q->devid != 0) { 4024 i++; 4025 continue; 4026 } 4027 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force, 4028 prefetchmask & (1 << i)); 4029 } 4030 4031 /* 4032 * Add additional, quirked resources. 4033 */ 4034 for (q = &pci_quirks[0]; q->devid != 0; q++) 4035 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) 4036 pci_add_map(bus, dev, q->arg1, rl, force, 0); 4037 4038 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 4039 #ifdef __PCI_REROUTE_INTERRUPT 4040 /* 4041 * Try to re-route interrupts. Sometimes the BIOS or 4042 * firmware may leave bogus values in these registers. 4043 * If the re-route fails, then just stick with what we 4044 * have. 4045 */ 4046 pci_assign_interrupt(bus, dev, 1); 4047 #else 4048 pci_assign_interrupt(bus, dev, 0); 4049 #endif 4050 } 4051 4052 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS && 4053 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) { 4054 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI) 4055 xhci_early_takeover(dev); 4056 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI) 4057 ehci_early_takeover(dev); 4058 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI) 4059 ohci_early_takeover(dev); 4060 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI) 4061 uhci_early_takeover(dev); 4062 } 4063 4064 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 4065 /* 4066 * Reserve resources for secondary bus ranges behind bridge 4067 * devices. 4068 */ 4069 pci_reserve_secbus(bus, dev, cfg, rl); 4070 #endif 4071 } 4072 4073 static struct pci_devinfo * 4074 pci_identify_function(device_t pcib, device_t dev, int domain, int busno, 4075 int slot, int func) 4076 { 4077 struct pci_devinfo *dinfo; 4078 4079 dinfo = pci_read_device(pcib, dev, domain, busno, slot, func); 4080 if (dinfo != NULL) 4081 pci_add_child(dev, dinfo); 4082 4083 return (dinfo); 4084 } 4085 4086 void 4087 pci_add_children(device_t dev, int domain, int busno) 4088 { 4089 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4090 device_t pcib = device_get_parent(dev); 4091 struct pci_devinfo *dinfo; 4092 int maxslots; 4093 int s, f, pcifunchigh; 4094 uint8_t hdrtype; 4095 int first_func; 4096 4097 /* 4098 * Try to detect a device at slot 0, function 0. If it exists, try to 4099 * enable ARI. We must enable ARI before detecting the rest of the 4100 * functions on this bus as ARI changes the set of slots and functions 4101 * that are legal on this bus. 4102 */ 4103 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0); 4104 if (dinfo != NULL && pci_enable_ari) 4105 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); 4106 4107 /* 4108 * Start looking for new devices on slot 0 at function 1 because we 4109 * just identified the device at slot 0, function 0. 4110 */ 4111 first_func = 1; 4112 4113 maxslots = PCIB_MAXSLOTS(pcib); 4114 for (s = 0; s <= maxslots; s++, first_func = 0) { 4115 pcifunchigh = 0; 4116 f = 0; 4117 DELAY(1); 4118 hdrtype = REG(PCIR_HDRTYPE, 1); 4119 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4120 continue; 4121 if (hdrtype & PCIM_MFDEV) 4122 pcifunchigh = PCIB_MAXFUNCS(pcib); 4123 for (f = first_func; f <= pcifunchigh; f++) 4124 pci_identify_function(pcib, dev, domain, busno, s, f); 4125 } 4126 #undef REG 4127 } 4128 4129 int 4130 pci_rescan_method(device_t dev) 4131 { 4132 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4133 device_t pcib = device_get_parent(dev); 4134 device_t child, *devlist, *unchanged; 4135 int devcount, error, i, j, maxslots, oldcount; 4136 int busno, domain, s, f, pcifunchigh; 4137 uint8_t hdrtype; 4138 4139 /* No need to check for ARI on a rescan. */ 4140 error = device_get_children(dev, &devlist, &devcount); 4141 if (error) 4142 return (error); 4143 if (devcount != 0) { 4144 unchanged = malloc(devcount * sizeof(device_t), M_TEMP, 4145 M_NOWAIT | M_ZERO); 4146 if (unchanged == NULL) { 4147 free(devlist, M_TEMP); 4148 return (ENOMEM); 4149 } 4150 } else 4151 unchanged = NULL; 4152 4153 domain = pcib_get_domain(dev); 4154 busno = pcib_get_bus(dev); 4155 maxslots = PCIB_MAXSLOTS(pcib); 4156 for (s = 0; s <= maxslots; s++) { 4157 /* If function 0 is not present, skip to the next slot. */ 4158 f = 0; 4159 if (REG(PCIR_VENDOR, 2) == 0xffff) 4160 continue; 4161 pcifunchigh = 0; 4162 hdrtype = REG(PCIR_HDRTYPE, 1); 4163 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4164 continue; 4165 if (hdrtype & PCIM_MFDEV) 4166 pcifunchigh = PCIB_MAXFUNCS(pcib); 4167 for (f = 0; f <= pcifunchigh; f++) { 4168 if (REG(PCIR_VENDOR, 2) == 0xffff) 4169 continue; 4170 4171 /* 4172 * Found a valid function. Check if a 4173 * device_t for this device already exists. 4174 */ 4175 for (i = 0; i < devcount; i++) { 4176 child = devlist[i]; 4177 if (child == NULL) 4178 continue; 4179 if (pci_get_slot(child) == s && 4180 pci_get_function(child) == f) { 4181 unchanged[i] = child; 4182 goto next_func; 4183 } 4184 } 4185 4186 pci_identify_function(pcib, dev, domain, busno, s, f); 4187 next_func:; 4188 } 4189 } 4190 4191 /* Remove devices that are no longer present. */ 4192 for (i = 0; i < devcount; i++) { 4193 if (unchanged[i] != NULL) 4194 continue; 4195 device_delete_child(dev, devlist[i]); 4196 } 4197 4198 free(devlist, M_TEMP); 4199 oldcount = devcount; 4200 4201 /* Try to attach the devices just added. */ 4202 error = device_get_children(dev, &devlist, &devcount); 4203 if (error) { 4204 free(unchanged, M_TEMP); 4205 return (error); 4206 } 4207 4208 for (i = 0; i < devcount; i++) { 4209 for (j = 0; j < oldcount; j++) { 4210 if (devlist[i] == unchanged[j]) 4211 goto next_device; 4212 } 4213 4214 device_probe_and_attach(devlist[i]); 4215 next_device:; 4216 } 4217 4218 free(unchanged, M_TEMP); 4219 free(devlist, M_TEMP); 4220 return (0); 4221 #undef REG 4222 } 4223 4224 #ifdef PCI_IOV 4225 device_t 4226 pci_add_iov_child(device_t bus, device_t pf, uint16_t rid, uint16_t vid, 4227 uint16_t did) 4228 { 4229 struct pci_devinfo *vf_dinfo; 4230 device_t pcib; 4231 int busno, slot, func; 4232 4233 pcib = device_get_parent(bus); 4234 4235 PCIB_DECODE_RID(pcib, rid, &busno, &slot, &func); 4236 4237 vf_dinfo = pci_fill_devinfo(pcib, bus, pci_get_domain(pcib), busno, 4238 slot, func, vid, did); 4239 4240 vf_dinfo->cfg.flags |= PCICFG_VF; 4241 pci_add_child(bus, vf_dinfo); 4242 4243 return (vf_dinfo->cfg.dev); 4244 } 4245 4246 device_t 4247 pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid, 4248 uint16_t vid, uint16_t did) 4249 { 4250 4251 return (pci_add_iov_child(bus, pf, rid, vid, did)); 4252 } 4253 #endif 4254 4255 static void 4256 pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo) 4257 { 4258 int aer; 4259 uint32_t r; 4260 uint16_t r2; 4261 4262 if (dinfo->cfg.pcie.pcie_location != 0 && 4263 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) { 4264 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4265 PCIER_ROOT_CTL, 2); 4266 r2 &= ~(PCIEM_ROOT_CTL_SERR_CORR | 4267 PCIEM_ROOT_CTL_SERR_NONFATAL | PCIEM_ROOT_CTL_SERR_FATAL); 4268 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4269 PCIER_ROOT_CTL, r2, 2); 4270 } 4271 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 4272 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 4273 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 4274 if (r != 0 && bootverbose) { 4275 pci_printf(&dinfo->cfg, 4276 "clearing AER UC 0x%08x -> 0x%08x\n", 4277 r, pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4278 4)); 4279 } 4280 4281 r = pci_read_config(dev, aer + PCIR_AER_UC_MASK, 4); 4282 r &= ~(PCIM_AER_UC_TRAINING_ERROR | 4283 PCIM_AER_UC_DL_PROTOCOL_ERROR | 4284 PCIM_AER_UC_SURPRISE_LINK_DOWN | 4285 PCIM_AER_UC_POISONED_TLP | 4286 PCIM_AER_UC_FC_PROTOCOL_ERROR | 4287 PCIM_AER_UC_COMPLETION_TIMEOUT | 4288 PCIM_AER_UC_COMPLETER_ABORT | 4289 PCIM_AER_UC_UNEXPECTED_COMPLETION | 4290 PCIM_AER_UC_RECEIVER_OVERFLOW | 4291 PCIM_AER_UC_MALFORMED_TLP | 4292 PCIM_AER_UC_ECRC_ERROR | 4293 PCIM_AER_UC_UNSUPPORTED_REQUEST | 4294 PCIM_AER_UC_ACS_VIOLATION | 4295 PCIM_AER_UC_INTERNAL_ERROR | 4296 PCIM_AER_UC_MC_BLOCKED_TLP | 4297 PCIM_AER_UC_ATOMIC_EGRESS_BLK | 4298 PCIM_AER_UC_TLP_PREFIX_BLOCKED); 4299 pci_write_config(dev, aer + PCIR_AER_UC_MASK, r, 4); 4300 4301 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 4302 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 4303 if (r != 0 && bootverbose) { 4304 pci_printf(&dinfo->cfg, 4305 "clearing AER COR 0x%08x -> 0x%08x\n", 4306 r, pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4307 4)); 4308 } 4309 4310 r = pci_read_config(dev, aer + PCIR_AER_COR_MASK, 4); 4311 r &= ~(PCIM_AER_COR_RECEIVER_ERROR | 4312 PCIM_AER_COR_BAD_TLP | 4313 PCIM_AER_COR_BAD_DLLP | 4314 PCIM_AER_COR_REPLAY_ROLLOVER | 4315 PCIM_AER_COR_REPLAY_TIMEOUT | 4316 PCIM_AER_COR_ADVISORY_NF_ERROR | 4317 PCIM_AER_COR_INTERNAL_ERROR | 4318 PCIM_AER_COR_HEADER_LOG_OVFLOW); 4319 pci_write_config(dev, aer + PCIR_AER_COR_MASK, r, 4); 4320 4321 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4322 PCIER_DEVICE_CTL, 2); 4323 r |= PCIEM_CTL_COR_ENABLE | PCIEM_CTL_NFER_ENABLE | 4324 PCIEM_CTL_FER_ENABLE | PCIEM_CTL_URR_ENABLE; 4325 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4326 PCIER_DEVICE_CTL, r, 2); 4327 } 4328 } 4329 4330 void 4331 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 4332 { 4333 device_t dev; 4334 4335 dinfo->cfg.dev = dev = device_add_child(bus, NULL, -1); 4336 device_set_ivars(dev, dinfo); 4337 resource_list_init(&dinfo->resources); 4338 pci_cfg_save(dev, dinfo, 0); 4339 pci_cfg_restore(dev, dinfo); 4340 pci_print_verbose(dinfo); 4341 pci_add_resources(bus, dev, 0, 0); 4342 pci_child_added(dinfo->cfg.dev); 4343 4344 if (pci_clear_aer_on_attach) 4345 pci_add_child_clear_aer(dev, dinfo); 4346 4347 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev); 4348 } 4349 4350 void 4351 pci_child_added_method(device_t dev, device_t child) 4352 { 4353 4354 } 4355 4356 static int 4357 pci_probe(device_t dev) 4358 { 4359 4360 device_set_desc(dev, "PCI bus"); 4361 4362 /* Allow other subclasses to override this driver. */ 4363 return (BUS_PROBE_GENERIC); 4364 } 4365 4366 int 4367 pci_attach_common(device_t dev) 4368 { 4369 struct pci_softc *sc; 4370 int busno, domain; 4371 #ifdef PCI_RES_BUS 4372 int rid; 4373 #endif 4374 4375 sc = device_get_softc(dev); 4376 domain = pcib_get_domain(dev); 4377 busno = pcib_get_bus(dev); 4378 #ifdef PCI_RES_BUS 4379 rid = 0; 4380 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, 4381 1, 0); 4382 if (sc->sc_bus == NULL) { 4383 device_printf(dev, "failed to allocate bus number\n"); 4384 return (ENXIO); 4385 } 4386 #endif 4387 if (bootverbose) 4388 device_printf(dev, "domain=%d, physical bus=%d\n", 4389 domain, busno); 4390 sc->sc_dma_tag = bus_get_dma_tag(dev); 4391 return (0); 4392 } 4393 4394 int 4395 pci_attach(device_t dev) 4396 { 4397 int busno, domain, error; 4398 4399 error = pci_attach_common(dev); 4400 if (error) 4401 return (error); 4402 4403 /* 4404 * Since there can be multiple independently numbered PCI 4405 * buses on systems with multiple PCI domains, we can't use 4406 * the unit number to decide which bus we are probing. We ask 4407 * the parent pcib what our domain and bus numbers are. 4408 */ 4409 domain = pcib_get_domain(dev); 4410 busno = pcib_get_bus(dev); 4411 pci_add_children(dev, domain, busno); 4412 return (bus_generic_attach(dev)); 4413 } 4414 4415 int 4416 pci_detach(device_t dev) 4417 { 4418 #ifdef PCI_RES_BUS 4419 struct pci_softc *sc; 4420 #endif 4421 int error; 4422 4423 error = bus_generic_detach(dev); 4424 if (error) 4425 return (error); 4426 #ifdef PCI_RES_BUS 4427 sc = device_get_softc(dev); 4428 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus); 4429 if (error) 4430 return (error); 4431 #endif 4432 return (device_delete_children(dev)); 4433 } 4434 4435 static void 4436 pci_hint_device_unit(device_t dev, device_t child, const char *name, int *unitp) 4437 { 4438 int line, unit; 4439 const char *at; 4440 char me1[24], me2[32]; 4441 uint8_t b, s, f; 4442 uint32_t d; 4443 4444 d = pci_get_domain(child); 4445 b = pci_get_bus(child); 4446 s = pci_get_slot(child); 4447 f = pci_get_function(child); 4448 snprintf(me1, sizeof(me1), "pci%u:%u:%u", b, s, f); 4449 snprintf(me2, sizeof(me2), "pci%u:%u:%u:%u", d, b, s, f); 4450 line = 0; 4451 while (resource_find_dev(&line, name, &unit, "at", NULL) == 0) { 4452 resource_string_value(name, unit, "at", &at); 4453 if (strcmp(at, me1) != 0 && strcmp(at, me2) != 0) 4454 continue; /* No match, try next candidate */ 4455 *unitp = unit; 4456 return; 4457 } 4458 } 4459 4460 static void 4461 pci_set_power_child(device_t dev, device_t child, int state) 4462 { 4463 device_t pcib; 4464 int dstate; 4465 4466 /* 4467 * Set the device to the given state. If the firmware suggests 4468 * a different power state, use it instead. If power management 4469 * is not present, the firmware is responsible for managing 4470 * device power. Skip children who aren't attached since they 4471 * are handled separately. 4472 */ 4473 pcib = device_get_parent(dev); 4474 dstate = state; 4475 if (device_is_attached(child) && 4476 PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0) 4477 pci_set_powerstate(child, dstate); 4478 } 4479 4480 int 4481 pci_suspend_child(device_t dev, device_t child) 4482 { 4483 struct pci_devinfo *dinfo; 4484 struct resource_list_entry *rle; 4485 int error; 4486 4487 dinfo = device_get_ivars(child); 4488 4489 /* 4490 * Save the PCI configuration space for the child and set the 4491 * device in the appropriate power state for this sleep state. 4492 */ 4493 pci_cfg_save(child, dinfo, 0); 4494 4495 /* Suspend devices before potentially powering them down. */ 4496 error = bus_generic_suspend_child(dev, child); 4497 4498 if (error) 4499 return (error); 4500 4501 if (pci_do_power_suspend) { 4502 /* 4503 * Make sure this device's interrupt handler is not invoked 4504 * in the case the device uses a shared interrupt that can 4505 * be raised by some other device. 4506 * This is applicable only to regular (legacy) PCI interrupts 4507 * as MSI/MSI-X interrupts are never shared. 4508 */ 4509 rle = resource_list_find(&dinfo->resources, 4510 SYS_RES_IRQ, 0); 4511 if (rle != NULL && rle->res != NULL) 4512 (void)bus_suspend_intr(child, rle->res); 4513 pci_set_power_child(dev, child, PCI_POWERSTATE_D3); 4514 } 4515 4516 return (0); 4517 } 4518 4519 int 4520 pci_resume_child(device_t dev, device_t child) 4521 { 4522 struct pci_devinfo *dinfo; 4523 struct resource_list_entry *rle; 4524 4525 if (pci_do_power_resume) 4526 pci_set_power_child(dev, child, PCI_POWERSTATE_D0); 4527 4528 dinfo = device_get_ivars(child); 4529 pci_cfg_restore(child, dinfo); 4530 if (!device_is_attached(child)) 4531 pci_cfg_save(child, dinfo, 1); 4532 4533 bus_generic_resume_child(dev, child); 4534 4535 /* 4536 * Allow interrupts only after fully resuming the driver and hardware. 4537 */ 4538 if (pci_do_power_suspend) { 4539 /* See pci_suspend_child for details. */ 4540 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 4541 if (rle != NULL && rle->res != NULL) 4542 (void)bus_resume_intr(child, rle->res); 4543 } 4544 4545 return (0); 4546 } 4547 4548 int 4549 pci_resume(device_t dev) 4550 { 4551 device_t child, *devlist; 4552 int error, i, numdevs; 4553 4554 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 4555 return (error); 4556 4557 /* 4558 * Resume critical devices first, then everything else later. 4559 */ 4560 for (i = 0; i < numdevs; i++) { 4561 child = devlist[i]; 4562 switch (pci_get_class(child)) { 4563 case PCIC_DISPLAY: 4564 case PCIC_MEMORY: 4565 case PCIC_BRIDGE: 4566 case PCIC_BASEPERIPH: 4567 BUS_RESUME_CHILD(dev, child); 4568 break; 4569 } 4570 } 4571 for (i = 0; i < numdevs; i++) { 4572 child = devlist[i]; 4573 switch (pci_get_class(child)) { 4574 case PCIC_DISPLAY: 4575 case PCIC_MEMORY: 4576 case PCIC_BRIDGE: 4577 case PCIC_BASEPERIPH: 4578 break; 4579 default: 4580 BUS_RESUME_CHILD(dev, child); 4581 } 4582 } 4583 free(devlist, M_TEMP); 4584 return (0); 4585 } 4586 4587 static void 4588 pci_load_vendor_data(void) 4589 { 4590 caddr_t data; 4591 void *ptr; 4592 size_t sz; 4593 4594 data = preload_search_by_type("pci_vendor_data"); 4595 if (data != NULL) { 4596 ptr = preload_fetch_addr(data); 4597 sz = preload_fetch_size(data); 4598 if (ptr != NULL && sz != 0) { 4599 pci_vendordata = ptr; 4600 pci_vendordata_size = sz; 4601 /* terminate the database */ 4602 pci_vendordata[pci_vendordata_size] = '\n'; 4603 } 4604 } 4605 } 4606 4607 void 4608 pci_driver_added(device_t dev, driver_t *driver) 4609 { 4610 int numdevs; 4611 device_t *devlist; 4612 device_t child; 4613 struct pci_devinfo *dinfo; 4614 int i; 4615 4616 if (bootverbose) 4617 device_printf(dev, "driver added\n"); 4618 DEVICE_IDENTIFY(driver, dev); 4619 if (device_get_children(dev, &devlist, &numdevs) != 0) 4620 return; 4621 for (i = 0; i < numdevs; i++) { 4622 child = devlist[i]; 4623 if (device_get_state(child) != DS_NOTPRESENT) 4624 continue; 4625 dinfo = device_get_ivars(child); 4626 pci_print_verbose(dinfo); 4627 if (bootverbose) 4628 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); 4629 pci_cfg_restore(child, dinfo); 4630 if (device_probe_and_attach(child) != 0) 4631 pci_child_detached(dev, child); 4632 } 4633 free(devlist, M_TEMP); 4634 } 4635 4636 int 4637 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, 4638 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep) 4639 { 4640 struct pci_devinfo *dinfo; 4641 struct msix_table_entry *mte; 4642 struct msix_vector *mv; 4643 uint64_t addr; 4644 uint32_t data; 4645 void *cookie; 4646 int error, rid; 4647 4648 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr, 4649 arg, &cookie); 4650 if (error) 4651 return (error); 4652 4653 /* If this is not a direct child, just bail out. */ 4654 if (device_get_parent(child) != dev) { 4655 *cookiep = cookie; 4656 return(0); 4657 } 4658 4659 rid = rman_get_rid(irq); 4660 if (rid == 0) { 4661 /* Make sure that INTx is enabled */ 4662 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4663 } else { 4664 /* 4665 * Check to see if the interrupt is MSI or MSI-X. 4666 * Ask our parent to map the MSI and give 4667 * us the address and data register values. 4668 * If we fail for some reason, teardown the 4669 * interrupt handler. 4670 */ 4671 dinfo = device_get_ivars(child); 4672 if (dinfo->cfg.msi.msi_alloc > 0) { 4673 if (dinfo->cfg.msi.msi_addr == 0) { 4674 KASSERT(dinfo->cfg.msi.msi_handlers == 0, 4675 ("MSI has handlers, but vectors not mapped")); 4676 error = PCIB_MAP_MSI(device_get_parent(dev), 4677 child, rman_get_start(irq), &addr, &data); 4678 if (error) 4679 goto bad; 4680 dinfo->cfg.msi.msi_addr = addr; 4681 dinfo->cfg.msi.msi_data = data; 4682 } 4683 if (dinfo->cfg.msi.msi_handlers == 0) 4684 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, 4685 dinfo->cfg.msi.msi_data); 4686 dinfo->cfg.msi.msi_handlers++; 4687 } else { 4688 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4689 ("No MSI or MSI-X interrupts allocated")); 4690 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4691 ("MSI-X index too high")); 4692 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4693 KASSERT(mte->mte_vector != 0, ("no message vector")); 4694 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; 4695 KASSERT(mv->mv_irq == rman_get_start(irq), 4696 ("IRQ mismatch")); 4697 if (mv->mv_address == 0) { 4698 KASSERT(mte->mte_handlers == 0, 4699 ("MSI-X table entry has handlers, but vector not mapped")); 4700 error = PCIB_MAP_MSI(device_get_parent(dev), 4701 child, rman_get_start(irq), &addr, &data); 4702 if (error) 4703 goto bad; 4704 mv->mv_address = addr; 4705 mv->mv_data = data; 4706 } 4707 4708 /* 4709 * The MSIX table entry must be made valid by 4710 * incrementing the mte_handlers before 4711 * calling pci_enable_msix() and 4712 * pci_resume_msix(). Else the MSIX rewrite 4713 * table quirk will not work as expected. 4714 */ 4715 mte->mte_handlers++; 4716 if (mte->mte_handlers == 1) { 4717 pci_enable_msix(child, rid - 1, mv->mv_address, 4718 mv->mv_data); 4719 pci_unmask_msix(child, rid - 1); 4720 } 4721 } 4722 4723 /* 4724 * Make sure that INTx is disabled if we are using MSI/MSI-X, 4725 * unless the device is affected by PCI_QUIRK_MSI_INTX_BUG, 4726 * in which case we "enable" INTx so MSI/MSI-X actually works. 4727 */ 4728 if (!pci_has_quirk(pci_get_devid(child), 4729 PCI_QUIRK_MSI_INTX_BUG)) 4730 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4731 else 4732 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4733 bad: 4734 if (error) { 4735 (void)bus_generic_teardown_intr(dev, child, irq, 4736 cookie); 4737 return (error); 4738 } 4739 } 4740 *cookiep = cookie; 4741 return (0); 4742 } 4743 4744 int 4745 pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 4746 void *cookie) 4747 { 4748 struct msix_table_entry *mte; 4749 struct resource_list_entry *rle; 4750 struct pci_devinfo *dinfo; 4751 int error, rid; 4752 4753 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE)) 4754 return (EINVAL); 4755 4756 /* If this isn't a direct child, just bail out */ 4757 if (device_get_parent(child) != dev) 4758 return(bus_generic_teardown_intr(dev, child, irq, cookie)); 4759 4760 rid = rman_get_rid(irq); 4761 if (rid == 0) { 4762 /* Mask INTx */ 4763 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4764 } else { 4765 /* 4766 * Check to see if the interrupt is MSI or MSI-X. If so, 4767 * decrement the appropriate handlers count and mask the 4768 * MSI-X message, or disable MSI messages if the count 4769 * drops to 0. 4770 */ 4771 dinfo = device_get_ivars(child); 4772 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); 4773 if (rle->res != irq) 4774 return (EINVAL); 4775 if (dinfo->cfg.msi.msi_alloc > 0) { 4776 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, 4777 ("MSI-X index too high")); 4778 if (dinfo->cfg.msi.msi_handlers == 0) 4779 return (EINVAL); 4780 dinfo->cfg.msi.msi_handlers--; 4781 if (dinfo->cfg.msi.msi_handlers == 0) 4782 pci_disable_msi(child); 4783 } else { 4784 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4785 ("No MSI or MSI-X interrupts allocated")); 4786 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4787 ("MSI-X index too high")); 4788 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4789 if (mte->mte_handlers == 0) 4790 return (EINVAL); 4791 mte->mte_handlers--; 4792 if (mte->mte_handlers == 0) 4793 pci_mask_msix(child, rid - 1); 4794 } 4795 } 4796 error = bus_generic_teardown_intr(dev, child, irq, cookie); 4797 if (rid > 0) 4798 KASSERT(error == 0, 4799 ("%s: generic teardown failed for MSI/MSI-X", __func__)); 4800 return (error); 4801 } 4802 4803 int 4804 pci_print_child(device_t dev, device_t child) 4805 { 4806 struct pci_devinfo *dinfo; 4807 struct resource_list *rl; 4808 int retval = 0; 4809 4810 dinfo = device_get_ivars(child); 4811 rl = &dinfo->resources; 4812 4813 retval += bus_print_child_header(dev, child); 4814 4815 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#jx"); 4816 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 4817 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 4818 if (device_get_flags(dev)) 4819 retval += printf(" flags %#x", device_get_flags(dev)); 4820 4821 retval += printf(" at device %d.%d", pci_get_slot(child), 4822 pci_get_function(child)); 4823 4824 retval += bus_print_child_domain(dev, child); 4825 retval += bus_print_child_footer(dev, child); 4826 4827 return (retval); 4828 } 4829 4830 static const struct 4831 { 4832 int class; 4833 int subclass; 4834 int report; /* 0 = bootverbose, 1 = always */ 4835 const char *desc; 4836 } pci_nomatch_tab[] = { 4837 {PCIC_OLD, -1, 1, "old"}, 4838 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"}, 4839 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"}, 4840 {PCIC_STORAGE, -1, 1, "mass storage"}, 4841 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"}, 4842 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"}, 4843 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"}, 4844 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"}, 4845 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"}, 4846 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"}, 4847 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"}, 4848 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"}, 4849 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"}, 4850 {PCIC_NETWORK, -1, 1, "network"}, 4851 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"}, 4852 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"}, 4853 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"}, 4854 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"}, 4855 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"}, 4856 {PCIC_DISPLAY, -1, 1, "display"}, 4857 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"}, 4858 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"}, 4859 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"}, 4860 {PCIC_MULTIMEDIA, -1, 1, "multimedia"}, 4861 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"}, 4862 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"}, 4863 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"}, 4864 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"}, 4865 {PCIC_MEMORY, -1, 1, "memory"}, 4866 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"}, 4867 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"}, 4868 {PCIC_BRIDGE, -1, 1, "bridge"}, 4869 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"}, 4870 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"}, 4871 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"}, 4872 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"}, 4873 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"}, 4874 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"}, 4875 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"}, 4876 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"}, 4877 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"}, 4878 {PCIC_SIMPLECOMM, -1, 1, "simple comms"}, 4879 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */ 4880 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"}, 4881 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"}, 4882 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"}, 4883 {PCIC_BASEPERIPH, -1, 0, "base peripheral"}, 4884 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"}, 4885 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"}, 4886 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"}, 4887 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"}, 4888 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"}, 4889 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"}, 4890 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"}, 4891 {PCIC_INPUTDEV, -1, 1, "input device"}, 4892 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"}, 4893 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"}, 4894 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"}, 4895 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"}, 4896 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"}, 4897 {PCIC_DOCKING, -1, 1, "docking station"}, 4898 {PCIC_PROCESSOR, -1, 1, "processor"}, 4899 {PCIC_SERIALBUS, -1, 1, "serial bus"}, 4900 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"}, 4901 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"}, 4902 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"}, 4903 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"}, 4904 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"}, 4905 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"}, 4906 {PCIC_WIRELESS, -1, 1, "wireless controller"}, 4907 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"}, 4908 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"}, 4909 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"}, 4910 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"}, 4911 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"}, 4912 {PCIC_SATCOM, -1, 1, "satellite communication"}, 4913 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"}, 4914 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"}, 4915 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"}, 4916 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"}, 4917 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"}, 4918 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"}, 4919 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"}, 4920 {PCIC_DASP, -1, 0, "dasp"}, 4921 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"}, 4922 {PCIC_DASP, PCIS_DASP_PERFCNTRS, 1, "performance counters"}, 4923 {PCIC_DASP, PCIS_DASP_COMM_SYNC, 1, "communication synchronizer"}, 4924 {PCIC_DASP, PCIS_DASP_MGMT_CARD, 1, "signal processing management"}, 4925 {0, 0, 0, NULL} 4926 }; 4927 4928 void 4929 pci_probe_nomatch(device_t dev, device_t child) 4930 { 4931 int i, report; 4932 const char *cp, *scp; 4933 char *device; 4934 4935 /* 4936 * Look for a listing for this device in a loaded device database. 4937 */ 4938 report = 1; 4939 if ((device = pci_describe_device(child)) != NULL) { 4940 device_printf(dev, "<%s>", device); 4941 free(device, M_DEVBUF); 4942 } else { 4943 /* 4944 * Scan the class/subclass descriptions for a general 4945 * description. 4946 */ 4947 cp = "unknown"; 4948 scp = NULL; 4949 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 4950 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 4951 if (pci_nomatch_tab[i].subclass == -1) { 4952 cp = pci_nomatch_tab[i].desc; 4953 report = pci_nomatch_tab[i].report; 4954 } else if (pci_nomatch_tab[i].subclass == 4955 pci_get_subclass(child)) { 4956 scp = pci_nomatch_tab[i].desc; 4957 report = pci_nomatch_tab[i].report; 4958 } 4959 } 4960 } 4961 if (report || bootverbose) { 4962 device_printf(dev, "<%s%s%s>", 4963 cp ? cp : "", 4964 ((cp != NULL) && (scp != NULL)) ? ", " : "", 4965 scp ? scp : ""); 4966 } 4967 } 4968 if (report || bootverbose) { 4969 printf(" at device %d.%d (no driver attached)\n", 4970 pci_get_slot(child), pci_get_function(child)); 4971 } 4972 pci_cfg_save(child, device_get_ivars(child), 1); 4973 } 4974 4975 void 4976 pci_child_detached(device_t dev, device_t child) 4977 { 4978 struct pci_devinfo *dinfo; 4979 struct resource_list *rl; 4980 4981 dinfo = device_get_ivars(child); 4982 rl = &dinfo->resources; 4983 4984 /* 4985 * Have to deallocate IRQs before releasing any MSI messages and 4986 * have to release MSI messages before deallocating any memory 4987 * BARs. 4988 */ 4989 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0) 4990 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); 4991 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { 4992 pci_printf(&dinfo->cfg, "Device leaked MSI vectors\n"); 4993 (void)pci_release_msi(child); 4994 } 4995 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0) 4996 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); 4997 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0) 4998 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); 4999 #ifdef PCI_RES_BUS 5000 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0) 5001 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); 5002 #endif 5003 5004 pci_cfg_save(child, dinfo, 1); 5005 } 5006 5007 /* 5008 * Parse the PCI device database, if loaded, and return a pointer to a 5009 * description of the device. 5010 * 5011 * The database is flat text formatted as follows: 5012 * 5013 * Any line not in a valid format is ignored. 5014 * Lines are terminated with newline '\n' characters. 5015 * 5016 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 5017 * the vendor name. 5018 * 5019 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 5020 * - devices cannot be listed without a corresponding VENDOR line. 5021 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 5022 * another TAB, then the device name. 5023 */ 5024 5025 /* 5026 * Assuming (ptr) points to the beginning of a line in the database, 5027 * return the vendor or device and description of the next entry. 5028 * The value of (vendor) or (device) inappropriate for the entry type 5029 * is set to -1. Returns nonzero at the end of the database. 5030 * 5031 * Note that this is slightly unrobust in the face of corrupt data; 5032 * we attempt to safeguard against this by spamming the end of the 5033 * database with a newline when we initialise. 5034 */ 5035 static int 5036 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 5037 { 5038 char *cp = *ptr; 5039 int left; 5040 5041 *device = -1; 5042 *vendor = -1; 5043 **desc = '\0'; 5044 for (;;) { 5045 left = pci_vendordata_size - (cp - pci_vendordata); 5046 if (left <= 0) { 5047 *ptr = cp; 5048 return(1); 5049 } 5050 5051 /* vendor entry? */ 5052 if (*cp != '\t' && 5053 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 5054 break; 5055 /* device entry? */ 5056 if (*cp == '\t' && 5057 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 5058 break; 5059 5060 /* skip to next line */ 5061 while (*cp != '\n' && left > 0) { 5062 cp++; 5063 left--; 5064 } 5065 if (*cp == '\n') { 5066 cp++; 5067 left--; 5068 } 5069 } 5070 /* skip to next line */ 5071 while (*cp != '\n' && left > 0) { 5072 cp++; 5073 left--; 5074 } 5075 if (*cp == '\n' && left > 0) 5076 cp++; 5077 *ptr = cp; 5078 return(0); 5079 } 5080 5081 static char * 5082 pci_describe_device(device_t dev) 5083 { 5084 int vendor, device; 5085 char *desc, *vp, *dp, *line; 5086 5087 desc = vp = dp = NULL; 5088 5089 /* 5090 * If we have no vendor data, we can't do anything. 5091 */ 5092 if (pci_vendordata == NULL) 5093 goto out; 5094 5095 /* 5096 * Scan the vendor data looking for this device 5097 */ 5098 line = pci_vendordata; 5099 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5100 goto out; 5101 for (;;) { 5102 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 5103 goto out; 5104 if (vendor == pci_get_vendor(dev)) 5105 break; 5106 } 5107 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5108 goto out; 5109 for (;;) { 5110 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 5111 *dp = 0; 5112 break; 5113 } 5114 if (vendor != -1) { 5115 *dp = 0; 5116 break; 5117 } 5118 if (device == pci_get_device(dev)) 5119 break; 5120 } 5121 if (dp[0] == '\0') 5122 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 5123 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 5124 NULL) 5125 sprintf(desc, "%s, %s", vp, dp); 5126 out: 5127 if (vp != NULL) 5128 free(vp, M_DEVBUF); 5129 if (dp != NULL) 5130 free(dp, M_DEVBUF); 5131 return(desc); 5132 } 5133 5134 int 5135 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 5136 { 5137 struct pci_devinfo *dinfo; 5138 pcicfgregs *cfg; 5139 5140 dinfo = device_get_ivars(child); 5141 cfg = &dinfo->cfg; 5142 5143 switch (which) { 5144 case PCI_IVAR_ETHADDR: 5145 /* 5146 * The generic accessor doesn't deal with failure, so 5147 * we set the return value, then return an error. 5148 */ 5149 *((uint8_t **) result) = NULL; 5150 return (EINVAL); 5151 case PCI_IVAR_SUBVENDOR: 5152 *result = cfg->subvendor; 5153 break; 5154 case PCI_IVAR_SUBDEVICE: 5155 *result = cfg->subdevice; 5156 break; 5157 case PCI_IVAR_VENDOR: 5158 *result = cfg->vendor; 5159 break; 5160 case PCI_IVAR_DEVICE: 5161 *result = cfg->device; 5162 break; 5163 case PCI_IVAR_DEVID: 5164 *result = (cfg->device << 16) | cfg->vendor; 5165 break; 5166 case PCI_IVAR_CLASS: 5167 *result = cfg->baseclass; 5168 break; 5169 case PCI_IVAR_SUBCLASS: 5170 *result = cfg->subclass; 5171 break; 5172 case PCI_IVAR_PROGIF: 5173 *result = cfg->progif; 5174 break; 5175 case PCI_IVAR_REVID: 5176 *result = cfg->revid; 5177 break; 5178 case PCI_IVAR_INTPIN: 5179 *result = cfg->intpin; 5180 break; 5181 case PCI_IVAR_IRQ: 5182 *result = cfg->intline; 5183 break; 5184 case PCI_IVAR_DOMAIN: 5185 *result = cfg->domain; 5186 break; 5187 case PCI_IVAR_BUS: 5188 *result = cfg->bus; 5189 break; 5190 case PCI_IVAR_SLOT: 5191 *result = cfg->slot; 5192 break; 5193 case PCI_IVAR_FUNCTION: 5194 *result = cfg->func; 5195 break; 5196 case PCI_IVAR_CMDREG: 5197 *result = cfg->cmdreg; 5198 break; 5199 case PCI_IVAR_CACHELNSZ: 5200 *result = cfg->cachelnsz; 5201 break; 5202 case PCI_IVAR_MINGNT: 5203 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5204 *result = -1; 5205 return (EINVAL); 5206 } 5207 *result = cfg->mingnt; 5208 break; 5209 case PCI_IVAR_MAXLAT: 5210 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5211 *result = -1; 5212 return (EINVAL); 5213 } 5214 *result = cfg->maxlat; 5215 break; 5216 case PCI_IVAR_LATTIMER: 5217 *result = cfg->lattimer; 5218 break; 5219 default: 5220 return (ENOENT); 5221 } 5222 return (0); 5223 } 5224 5225 int 5226 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 5227 { 5228 struct pci_devinfo *dinfo; 5229 5230 dinfo = device_get_ivars(child); 5231 5232 switch (which) { 5233 case PCI_IVAR_INTPIN: 5234 dinfo->cfg.intpin = value; 5235 return (0); 5236 case PCI_IVAR_ETHADDR: 5237 case PCI_IVAR_SUBVENDOR: 5238 case PCI_IVAR_SUBDEVICE: 5239 case PCI_IVAR_VENDOR: 5240 case PCI_IVAR_DEVICE: 5241 case PCI_IVAR_DEVID: 5242 case PCI_IVAR_CLASS: 5243 case PCI_IVAR_SUBCLASS: 5244 case PCI_IVAR_PROGIF: 5245 case PCI_IVAR_REVID: 5246 case PCI_IVAR_IRQ: 5247 case PCI_IVAR_DOMAIN: 5248 case PCI_IVAR_BUS: 5249 case PCI_IVAR_SLOT: 5250 case PCI_IVAR_FUNCTION: 5251 return (EINVAL); /* disallow for now */ 5252 5253 default: 5254 return (ENOENT); 5255 } 5256 } 5257 5258 #include "opt_ddb.h" 5259 #ifdef DDB 5260 #include <ddb/ddb.h> 5261 #include <sys/cons.h> 5262 5263 /* 5264 * List resources based on pci map registers, used for within ddb 5265 */ 5266 5267 DB_SHOW_COMMAND(pciregs, db_pci_dump) 5268 { 5269 struct pci_devinfo *dinfo; 5270 struct devlist *devlist_head; 5271 struct pci_conf *p; 5272 const char *name; 5273 int i, error, none_count; 5274 5275 none_count = 0; 5276 /* get the head of the device queue */ 5277 devlist_head = &pci_devq; 5278 5279 /* 5280 * Go through the list of devices and print out devices 5281 */ 5282 for (error = 0, i = 0, 5283 dinfo = STAILQ_FIRST(devlist_head); 5284 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 5285 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 5286 /* Populate pd_name and pd_unit */ 5287 name = NULL; 5288 if (dinfo->cfg.dev) 5289 name = device_get_name(dinfo->cfg.dev); 5290 5291 p = &dinfo->conf; 5292 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x " 5293 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 5294 (name && *name) ? name : "none", 5295 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 5296 none_count++, 5297 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, 5298 p->pc_sel.pc_func, (p->pc_class << 16) | 5299 (p->pc_subclass << 8) | p->pc_progif, 5300 (p->pc_subdevice << 16) | p->pc_subvendor, 5301 (p->pc_device << 16) | p->pc_vendor, 5302 p->pc_revid, p->pc_hdr); 5303 } 5304 } 5305 #endif /* DDB */ 5306 5307 static struct resource * 5308 pci_reserve_map(device_t dev, device_t child, int type, int *rid, 5309 rman_res_t start, rman_res_t end, rman_res_t count, u_int num, 5310 u_int flags) 5311 { 5312 struct pci_devinfo *dinfo = device_get_ivars(child); 5313 struct resource_list *rl = &dinfo->resources; 5314 struct resource *res; 5315 struct pci_map *pm; 5316 uint16_t cmd; 5317 pci_addr_t map, testval; 5318 int mapsize; 5319 5320 res = NULL; 5321 5322 /* If rid is managed by EA, ignore it */ 5323 if (pci_ea_is_enabled(child, *rid)) 5324 goto out; 5325 5326 pm = pci_find_bar(child, *rid); 5327 if (pm != NULL) { 5328 /* This is a BAR that we failed to allocate earlier. */ 5329 mapsize = pm->pm_size; 5330 map = pm->pm_value; 5331 } else { 5332 /* 5333 * Weed out the bogons, and figure out how large the 5334 * BAR/map is. BARs that read back 0 here are bogus 5335 * and unimplemented. Note: atapci in legacy mode are 5336 * special and handled elsewhere in the code. If you 5337 * have a atapci device in legacy mode and it fails 5338 * here, that other code is broken. 5339 */ 5340 pci_read_bar(child, *rid, &map, &testval, NULL); 5341 5342 /* 5343 * Determine the size of the BAR and ignore BARs with a size 5344 * of 0. Device ROM BARs use a different mask value. 5345 */ 5346 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) 5347 mapsize = pci_romsize(testval); 5348 else 5349 mapsize = pci_mapsize(testval); 5350 if (mapsize == 0) 5351 goto out; 5352 pm = pci_add_bar(child, *rid, map, mapsize); 5353 } 5354 5355 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { 5356 if (type != SYS_RES_MEMORY) { 5357 if (bootverbose) 5358 device_printf(dev, 5359 "child %s requested type %d for rid %#x," 5360 " but the BAR says it is an memio\n", 5361 device_get_nameunit(child), type, *rid); 5362 goto out; 5363 } 5364 } else { 5365 if (type != SYS_RES_IOPORT) { 5366 if (bootverbose) 5367 device_printf(dev, 5368 "child %s requested type %d for rid %#x," 5369 " but the BAR says it is an ioport\n", 5370 device_get_nameunit(child), type, *rid); 5371 goto out; 5372 } 5373 } 5374 5375 /* 5376 * For real BARs, we need to override the size that 5377 * the driver requests, because that's what the BAR 5378 * actually uses and we would otherwise have a 5379 * situation where we might allocate the excess to 5380 * another driver, which won't work. 5381 */ 5382 count = ((pci_addr_t)1 << mapsize) * num; 5383 if (RF_ALIGNMENT(flags) < mapsize) 5384 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 5385 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH)) 5386 flags |= RF_PREFETCHABLE; 5387 5388 /* 5389 * Allocate enough resource, and then write back the 5390 * appropriate BAR for that resource. 5391 */ 5392 resource_list_add(rl, type, *rid, start, end, count); 5393 res = resource_list_reserve(rl, dev, child, type, rid, start, end, 5394 count, flags & ~RF_ACTIVE); 5395 if (res == NULL) { 5396 resource_list_delete(rl, type, *rid); 5397 device_printf(child, 5398 "%#jx bytes of rid %#x res %d failed (%#jx, %#jx).\n", 5399 count, *rid, type, start, end); 5400 goto out; 5401 } 5402 if (bootverbose) 5403 device_printf(child, 5404 "Lazy allocation of %#jx bytes rid %#x type %d at %#jx\n", 5405 count, *rid, type, rman_get_start(res)); 5406 5407 /* Disable decoding via the CMD register before updating the BAR */ 5408 cmd = pci_read_config(child, PCIR_COMMAND, 2); 5409 pci_write_config(child, PCIR_COMMAND, 5410 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 5411 5412 map = rman_get_start(res); 5413 pci_write_bar(child, pm, map); 5414 5415 /* Restore the original value of the CMD register */ 5416 pci_write_config(child, PCIR_COMMAND, cmd, 2); 5417 out: 5418 return (res); 5419 } 5420 5421 struct resource * 5422 pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid, 5423 rman_res_t start, rman_res_t end, rman_res_t count, u_long num, 5424 u_int flags) 5425 { 5426 struct pci_devinfo *dinfo; 5427 struct resource_list *rl; 5428 struct resource_list_entry *rle; 5429 struct resource *res; 5430 pcicfgregs *cfg; 5431 5432 /* 5433 * Perform lazy resource allocation 5434 */ 5435 dinfo = device_get_ivars(child); 5436 rl = &dinfo->resources; 5437 cfg = &dinfo->cfg; 5438 switch (type) { 5439 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 5440 case PCI_RES_BUS: 5441 return (pci_alloc_secbus(dev, child, rid, start, end, count, 5442 flags)); 5443 #endif 5444 case SYS_RES_IRQ: 5445 /* 5446 * Can't alloc legacy interrupt once MSI messages have 5447 * been allocated. 5448 */ 5449 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 5450 cfg->msix.msix_alloc > 0)) 5451 return (NULL); 5452 5453 /* 5454 * If the child device doesn't have an interrupt 5455 * routed and is deserving of an interrupt, try to 5456 * assign it one. 5457 */ 5458 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 5459 (cfg->intpin != 0)) 5460 pci_assign_interrupt(dev, child, 0); 5461 break; 5462 case SYS_RES_IOPORT: 5463 case SYS_RES_MEMORY: 5464 #ifdef NEW_PCIB 5465 /* 5466 * PCI-PCI bridge I/O window resources are not BARs. 5467 * For those allocations just pass the request up the 5468 * tree. 5469 */ 5470 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { 5471 switch (*rid) { 5472 case PCIR_IOBASEL_1: 5473 case PCIR_MEMBASE_1: 5474 case PCIR_PMBASEL_1: 5475 /* 5476 * XXX: Should we bother creating a resource 5477 * list entry? 5478 */ 5479 return (bus_generic_alloc_resource(dev, child, 5480 type, rid, start, end, count, flags)); 5481 } 5482 } 5483 #endif 5484 /* Reserve resources for this BAR if needed. */ 5485 rle = resource_list_find(rl, type, *rid); 5486 if (rle == NULL) { 5487 res = pci_reserve_map(dev, child, type, rid, start, end, 5488 count, num, flags); 5489 if (res == NULL) 5490 return (NULL); 5491 } 5492 } 5493 return (resource_list_alloc(rl, dev, child, type, rid, 5494 start, end, count, flags)); 5495 } 5496 5497 struct resource * 5498 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 5499 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 5500 { 5501 #ifdef PCI_IOV 5502 struct pci_devinfo *dinfo; 5503 #endif 5504 5505 if (device_get_parent(child) != dev) 5506 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 5507 type, rid, start, end, count, flags)); 5508 5509 #ifdef PCI_IOV 5510 dinfo = device_get_ivars(child); 5511 if (dinfo->cfg.flags & PCICFG_VF) { 5512 switch (type) { 5513 /* VFs can't have I/O BARs. */ 5514 case SYS_RES_IOPORT: 5515 return (NULL); 5516 case SYS_RES_MEMORY: 5517 return (pci_vf_alloc_mem_resource(dev, child, rid, 5518 start, end, count, flags)); 5519 } 5520 5521 /* Fall through for other types of resource allocations. */ 5522 } 5523 #endif 5524 5525 return (pci_alloc_multi_resource(dev, child, type, rid, start, end, 5526 count, 1, flags)); 5527 } 5528 5529 int 5530 pci_release_resource(device_t dev, device_t child, int type, int rid, 5531 struct resource *r) 5532 { 5533 struct pci_devinfo *dinfo; 5534 struct resource_list *rl; 5535 pcicfgregs *cfg; 5536 5537 if (device_get_parent(child) != dev) 5538 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 5539 type, rid, r)); 5540 5541 dinfo = device_get_ivars(child); 5542 cfg = &dinfo->cfg; 5543 5544 #ifdef PCI_IOV 5545 if (dinfo->cfg.flags & PCICFG_VF) { 5546 switch (type) { 5547 /* VFs can't have I/O BARs. */ 5548 case SYS_RES_IOPORT: 5549 return (EDOOFUS); 5550 case SYS_RES_MEMORY: 5551 return (pci_vf_release_mem_resource(dev, child, rid, 5552 r)); 5553 } 5554 5555 /* Fall through for other types of resource allocations. */ 5556 } 5557 #endif 5558 5559 #ifdef NEW_PCIB 5560 /* 5561 * PCI-PCI bridge I/O window resources are not BARs. For 5562 * those allocations just pass the request up the tree. 5563 */ 5564 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && 5565 (type == SYS_RES_IOPORT || type == SYS_RES_MEMORY)) { 5566 switch (rid) { 5567 case PCIR_IOBASEL_1: 5568 case PCIR_MEMBASE_1: 5569 case PCIR_PMBASEL_1: 5570 return (bus_generic_release_resource(dev, child, type, 5571 rid, r)); 5572 } 5573 } 5574 #endif 5575 5576 rl = &dinfo->resources; 5577 return (resource_list_release(rl, dev, child, type, rid, r)); 5578 } 5579 5580 int 5581 pci_activate_resource(device_t dev, device_t child, int type, int rid, 5582 struct resource *r) 5583 { 5584 struct pci_devinfo *dinfo; 5585 int error; 5586 5587 error = bus_generic_activate_resource(dev, child, type, rid, r); 5588 if (error) 5589 return (error); 5590 5591 /* Enable decoding in the command register when activating BARs. */ 5592 if (device_get_parent(child) == dev) { 5593 /* Device ROMs need their decoding explicitly enabled. */ 5594 dinfo = device_get_ivars(child); 5595 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5596 pci_write_bar(child, pci_find_bar(child, rid), 5597 rman_get_start(r) | PCIM_BIOS_ENABLE); 5598 switch (type) { 5599 case SYS_RES_IOPORT: 5600 case SYS_RES_MEMORY: 5601 error = PCI_ENABLE_IO(dev, child, type); 5602 break; 5603 } 5604 } 5605 return (error); 5606 } 5607 5608 int 5609 pci_deactivate_resource(device_t dev, device_t child, int type, 5610 int rid, struct resource *r) 5611 { 5612 struct pci_devinfo *dinfo; 5613 int error; 5614 5615 error = bus_generic_deactivate_resource(dev, child, type, rid, r); 5616 if (error) 5617 return (error); 5618 5619 /* Disable decoding for device ROMs. */ 5620 if (device_get_parent(child) == dev) { 5621 dinfo = device_get_ivars(child); 5622 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5623 pci_write_bar(child, pci_find_bar(child, rid), 5624 rman_get_start(r)); 5625 } 5626 return (0); 5627 } 5628 5629 void 5630 pci_child_deleted(device_t dev, device_t child) 5631 { 5632 struct resource_list_entry *rle; 5633 struct resource_list *rl; 5634 struct pci_devinfo *dinfo; 5635 5636 dinfo = device_get_ivars(child); 5637 rl = &dinfo->resources; 5638 5639 EVENTHANDLER_INVOKE(pci_delete_device, child); 5640 5641 /* Turn off access to resources we're about to free */ 5642 if (bus_child_present(child) != 0) { 5643 pci_write_config(child, PCIR_COMMAND, pci_read_config(child, 5644 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2); 5645 5646 pci_disable_busmaster(child); 5647 } 5648 5649 /* Free all allocated resources */ 5650 STAILQ_FOREACH(rle, rl, link) { 5651 if (rle->res) { 5652 if (rman_get_flags(rle->res) & RF_ACTIVE || 5653 resource_list_busy(rl, rle->type, rle->rid)) { 5654 pci_printf(&dinfo->cfg, 5655 "Resource still owned, oops. " 5656 "(type=%d, rid=%d, addr=%lx)\n", 5657 rle->type, rle->rid, 5658 rman_get_start(rle->res)); 5659 bus_release_resource(child, rle->type, rle->rid, 5660 rle->res); 5661 } 5662 resource_list_unreserve(rl, dev, child, rle->type, 5663 rle->rid); 5664 } 5665 } 5666 resource_list_free(rl); 5667 5668 pci_freecfg(dinfo); 5669 } 5670 5671 void 5672 pci_delete_resource(device_t dev, device_t child, int type, int rid) 5673 { 5674 struct pci_devinfo *dinfo; 5675 struct resource_list *rl; 5676 struct resource_list_entry *rle; 5677 5678 if (device_get_parent(child) != dev) 5679 return; 5680 5681 dinfo = device_get_ivars(child); 5682 rl = &dinfo->resources; 5683 rle = resource_list_find(rl, type, rid); 5684 if (rle == NULL) 5685 return; 5686 5687 if (rle->res) { 5688 if (rman_get_flags(rle->res) & RF_ACTIVE || 5689 resource_list_busy(rl, type, rid)) { 5690 device_printf(dev, "delete_resource: " 5691 "Resource still owned by child, oops. " 5692 "(type=%d, rid=%d, addr=%jx)\n", 5693 type, rid, rman_get_start(rle->res)); 5694 return; 5695 } 5696 resource_list_unreserve(rl, dev, child, type, rid); 5697 } 5698 resource_list_delete(rl, type, rid); 5699 } 5700 5701 struct resource_list * 5702 pci_get_resource_list (device_t dev, device_t child) 5703 { 5704 struct pci_devinfo *dinfo = device_get_ivars(child); 5705 5706 return (&dinfo->resources); 5707 } 5708 5709 #ifdef IOMMU 5710 bus_dma_tag_t 5711 pci_get_dma_tag(device_t bus, device_t dev) 5712 { 5713 bus_dma_tag_t tag; 5714 struct pci_softc *sc; 5715 5716 if (device_get_parent(dev) == bus) { 5717 /* try iommu and return if it works */ 5718 tag = iommu_get_dma_tag(bus, dev); 5719 } else 5720 tag = NULL; 5721 if (tag == NULL) { 5722 sc = device_get_softc(bus); 5723 tag = sc->sc_dma_tag; 5724 } 5725 return (tag); 5726 } 5727 #else 5728 bus_dma_tag_t 5729 pci_get_dma_tag(device_t bus, device_t dev) 5730 { 5731 struct pci_softc *sc = device_get_softc(bus); 5732 5733 return (sc->sc_dma_tag); 5734 } 5735 #endif 5736 5737 uint32_t 5738 pci_read_config_method(device_t dev, device_t child, int reg, int width) 5739 { 5740 struct pci_devinfo *dinfo = device_get_ivars(child); 5741 pcicfgregs *cfg = &dinfo->cfg; 5742 5743 #ifdef PCI_IOV 5744 /* 5745 * SR-IOV VFs don't implement the VID or DID registers, so we have to 5746 * emulate them here. 5747 */ 5748 if (cfg->flags & PCICFG_VF) { 5749 if (reg == PCIR_VENDOR) { 5750 switch (width) { 5751 case 4: 5752 return (cfg->device << 16 | cfg->vendor); 5753 case 2: 5754 return (cfg->vendor); 5755 case 1: 5756 return (cfg->vendor & 0xff); 5757 default: 5758 return (0xffffffff); 5759 } 5760 } else if (reg == PCIR_DEVICE) { 5761 switch (width) { 5762 /* Note that an unaligned 4-byte read is an error. */ 5763 case 2: 5764 return (cfg->device); 5765 case 1: 5766 return (cfg->device & 0xff); 5767 default: 5768 return (0xffffffff); 5769 } 5770 } 5771 } 5772 #endif 5773 5774 return (PCIB_READ_CONFIG(device_get_parent(dev), 5775 cfg->bus, cfg->slot, cfg->func, reg, width)); 5776 } 5777 5778 void 5779 pci_write_config_method(device_t dev, device_t child, int reg, 5780 uint32_t val, int width) 5781 { 5782 struct pci_devinfo *dinfo = device_get_ivars(child); 5783 pcicfgregs *cfg = &dinfo->cfg; 5784 5785 PCIB_WRITE_CONFIG(device_get_parent(dev), 5786 cfg->bus, cfg->slot, cfg->func, reg, val, width); 5787 } 5788 5789 int 5790 pci_child_location_str_method(device_t dev, device_t child, char *buf, 5791 size_t buflen) 5792 { 5793 5794 snprintf(buf, buflen, "slot=%d function=%d dbsf=pci%d:%d:%d:%d", 5795 pci_get_slot(child), pci_get_function(child), pci_get_domain(child), 5796 pci_get_bus(child), pci_get_slot(child), pci_get_function(child)); 5797 return (0); 5798 } 5799 5800 int 5801 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 5802 size_t buflen) 5803 { 5804 struct pci_devinfo *dinfo; 5805 pcicfgregs *cfg; 5806 5807 dinfo = device_get_ivars(child); 5808 cfg = &dinfo->cfg; 5809 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 5810 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 5811 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 5812 cfg->progif); 5813 return (0); 5814 } 5815 5816 int 5817 pci_assign_interrupt_method(device_t dev, device_t child) 5818 { 5819 struct pci_devinfo *dinfo = device_get_ivars(child); 5820 pcicfgregs *cfg = &dinfo->cfg; 5821 5822 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 5823 cfg->intpin)); 5824 } 5825 5826 static void 5827 pci_lookup(void *arg, const char *name, device_t *dev) 5828 { 5829 long val; 5830 char *end; 5831 int domain, bus, slot, func; 5832 5833 if (*dev != NULL) 5834 return; 5835 5836 /* 5837 * Accept pciconf-style selectors of either pciD:B:S:F or 5838 * pciB:S:F. In the latter case, the domain is assumed to 5839 * be zero. 5840 */ 5841 if (strncmp(name, "pci", 3) != 0) 5842 return; 5843 val = strtol(name + 3, &end, 10); 5844 if (val < 0 || val > INT_MAX || *end != ':') 5845 return; 5846 domain = val; 5847 val = strtol(end + 1, &end, 10); 5848 if (val < 0 || val > INT_MAX || *end != ':') 5849 return; 5850 bus = val; 5851 val = strtol(end + 1, &end, 10); 5852 if (val < 0 || val > INT_MAX) 5853 return; 5854 slot = val; 5855 if (*end == ':') { 5856 val = strtol(end + 1, &end, 10); 5857 if (val < 0 || val > INT_MAX || *end != '\0') 5858 return; 5859 func = val; 5860 } else if (*end == '\0') { 5861 func = slot; 5862 slot = bus; 5863 bus = domain; 5864 domain = 0; 5865 } else 5866 return; 5867 5868 if (domain > PCI_DOMAINMAX || bus > PCI_BUSMAX || slot > PCI_SLOTMAX || 5869 func > PCIE_ARI_FUNCMAX || (slot != 0 && func > PCI_FUNCMAX)) 5870 return; 5871 5872 *dev = pci_find_dbsf(domain, bus, slot, func); 5873 } 5874 5875 static int 5876 pci_modevent(module_t mod, int what, void *arg) 5877 { 5878 static struct cdev *pci_cdev; 5879 static eventhandler_tag tag; 5880 5881 switch (what) { 5882 case MOD_LOAD: 5883 STAILQ_INIT(&pci_devq); 5884 pci_generation = 0; 5885 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 5886 "pci"); 5887 pci_load_vendor_data(); 5888 tag = EVENTHANDLER_REGISTER(dev_lookup, pci_lookup, NULL, 5889 1000); 5890 break; 5891 5892 case MOD_UNLOAD: 5893 if (tag != NULL) 5894 EVENTHANDLER_DEREGISTER(dev_lookup, tag); 5895 destroy_dev(pci_cdev); 5896 break; 5897 } 5898 5899 return (0); 5900 } 5901 5902 static void 5903 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo) 5904 { 5905 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2) 5906 struct pcicfg_pcie *cfg; 5907 int version, pos; 5908 5909 cfg = &dinfo->cfg.pcie; 5910 pos = cfg->pcie_location; 5911 5912 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 5913 5914 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); 5915 5916 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5917 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 5918 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 5919 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); 5920 5921 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5922 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 5923 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 5924 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); 5925 5926 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 5927 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 5928 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); 5929 5930 if (version > 1) { 5931 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); 5932 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); 5933 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); 5934 } 5935 #undef WREG 5936 } 5937 5938 static void 5939 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo) 5940 { 5941 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 5942 dinfo->cfg.pcix.pcix_command, 2); 5943 } 5944 5945 void 5946 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 5947 { 5948 5949 /* 5950 * Restore the device to full power mode. We must do this 5951 * before we restore the registers because moving from D3 to 5952 * D0 will cause the chip's BARs and some other registers to 5953 * be reset to some unknown power on reset values. Cut down 5954 * the noise on boot by doing nothing if we are already in 5955 * state D0. 5956 */ 5957 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) 5958 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 5959 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 5960 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 5961 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 5962 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 5963 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 5964 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 5965 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 5966 case PCIM_HDRTYPE_NORMAL: 5967 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 5968 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 5969 break; 5970 case PCIM_HDRTYPE_BRIDGE: 5971 pci_write_config(dev, PCIR_SECLAT_1, 5972 dinfo->cfg.bridge.br_seclat, 1); 5973 pci_write_config(dev, PCIR_SUBBUS_1, 5974 dinfo->cfg.bridge.br_subbus, 1); 5975 pci_write_config(dev, PCIR_SECBUS_1, 5976 dinfo->cfg.bridge.br_secbus, 1); 5977 pci_write_config(dev, PCIR_PRIBUS_1, 5978 dinfo->cfg.bridge.br_pribus, 1); 5979 pci_write_config(dev, PCIR_BRIDGECTL_1, 5980 dinfo->cfg.bridge.br_control, 2); 5981 break; 5982 case PCIM_HDRTYPE_CARDBUS: 5983 pci_write_config(dev, PCIR_SECLAT_2, 5984 dinfo->cfg.bridge.br_seclat, 1); 5985 pci_write_config(dev, PCIR_SUBBUS_2, 5986 dinfo->cfg.bridge.br_subbus, 1); 5987 pci_write_config(dev, PCIR_SECBUS_2, 5988 dinfo->cfg.bridge.br_secbus, 1); 5989 pci_write_config(dev, PCIR_PRIBUS_2, 5990 dinfo->cfg.bridge.br_pribus, 1); 5991 pci_write_config(dev, PCIR_BRIDGECTL_2, 5992 dinfo->cfg.bridge.br_control, 2); 5993 break; 5994 } 5995 pci_restore_bars(dev); 5996 5997 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE) 5998 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 5999 6000 /* 6001 * Restore extended capabilities for PCI-Express and PCI-X 6002 */ 6003 if (dinfo->cfg.pcie.pcie_location != 0) 6004 pci_cfg_restore_pcie(dev, dinfo); 6005 if (dinfo->cfg.pcix.pcix_location != 0) 6006 pci_cfg_restore_pcix(dev, dinfo); 6007 6008 /* Restore MSI and MSI-X configurations if they are present. */ 6009 if (dinfo->cfg.msi.msi_location != 0) 6010 pci_resume_msi(dev); 6011 if (dinfo->cfg.msix.msix_location != 0) 6012 pci_resume_msix(dev); 6013 6014 #ifdef PCI_IOV 6015 if (dinfo->cfg.iov != NULL) 6016 pci_iov_cfg_restore(dev, dinfo); 6017 #endif 6018 } 6019 6020 static void 6021 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo) 6022 { 6023 #define RREG(n) pci_read_config(dev, pos + (n), 2) 6024 struct pcicfg_pcie *cfg; 6025 int version, pos; 6026 6027 cfg = &dinfo->cfg.pcie; 6028 pos = cfg->pcie_location; 6029 6030 cfg->pcie_flags = RREG(PCIER_FLAGS); 6031 6032 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6033 6034 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); 6035 6036 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6037 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6038 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6039 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); 6040 6041 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6042 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6043 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6044 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); 6045 6046 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6047 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6048 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); 6049 6050 if (version > 1) { 6051 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); 6052 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); 6053 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); 6054 } 6055 #undef RREG 6056 } 6057 6058 static void 6059 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo) 6060 { 6061 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, 6062 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); 6063 } 6064 6065 void 6066 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 6067 { 6068 uint32_t cls; 6069 int ps; 6070 6071 /* 6072 * Some drivers apparently write to these registers w/o updating our 6073 * cached copy. No harm happens if we update the copy, so do so here 6074 * so we can restore them. The COMMAND register is modified by the 6075 * bus w/o updating the cache. This should represent the normally 6076 * writable portion of the 'defined' part of type 0/1/2 headers. 6077 */ 6078 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 6079 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 6080 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 6081 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 6082 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 6083 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 6084 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 6085 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 6086 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 6087 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 6088 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 6089 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6090 case PCIM_HDRTYPE_NORMAL: 6091 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 6092 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 6093 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 6094 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 6095 break; 6096 case PCIM_HDRTYPE_BRIDGE: 6097 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6098 PCIR_SECLAT_1, 1); 6099 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6100 PCIR_SUBBUS_1, 1); 6101 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6102 PCIR_SECBUS_1, 1); 6103 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6104 PCIR_PRIBUS_1, 1); 6105 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6106 PCIR_BRIDGECTL_1, 2); 6107 break; 6108 case PCIM_HDRTYPE_CARDBUS: 6109 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6110 PCIR_SECLAT_2, 1); 6111 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6112 PCIR_SUBBUS_2, 1); 6113 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6114 PCIR_SECBUS_2, 1); 6115 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6116 PCIR_PRIBUS_2, 1); 6117 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6118 PCIR_BRIDGECTL_2, 2); 6119 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2); 6120 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2); 6121 break; 6122 } 6123 6124 if (dinfo->cfg.pcie.pcie_location != 0) 6125 pci_cfg_save_pcie(dev, dinfo); 6126 6127 if (dinfo->cfg.pcix.pcix_location != 0) 6128 pci_cfg_save_pcix(dev, dinfo); 6129 6130 #ifdef PCI_IOV 6131 if (dinfo->cfg.iov != NULL) 6132 pci_iov_cfg_save(dev, dinfo); 6133 #endif 6134 6135 /* 6136 * don't set the state for display devices, base peripherals and 6137 * memory devices since bad things happen when they are powered down. 6138 * We should (a) have drivers that can easily detach and (b) use 6139 * generic drivers for these devices so that some device actually 6140 * attaches. We need to make sure that when we implement (a) we don't 6141 * power the device down on a reattach. 6142 */ 6143 cls = pci_get_class(dev); 6144 if (!setstate) 6145 return; 6146 switch (pci_do_power_nodriver) 6147 { 6148 case 0: /* NO powerdown at all */ 6149 return; 6150 case 1: /* Conservative about what to power down */ 6151 if (cls == PCIC_STORAGE) 6152 return; 6153 /*FALLTHROUGH*/ 6154 case 2: /* Aggressive about what to power down */ 6155 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 6156 cls == PCIC_BASEPERIPH) 6157 return; 6158 /*FALLTHROUGH*/ 6159 case 3: /* Power down everything */ 6160 break; 6161 } 6162 /* 6163 * PCI spec says we can only go into D3 state from D0 state. 6164 * Transition from D[12] into D0 before going to D3 state. 6165 */ 6166 ps = pci_get_powerstate(dev); 6167 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6168 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6169 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 6170 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6171 } 6172 6173 /* Wrapper APIs suitable for device driver use. */ 6174 void 6175 pci_save_state(device_t dev) 6176 { 6177 struct pci_devinfo *dinfo; 6178 6179 dinfo = device_get_ivars(dev); 6180 pci_cfg_save(dev, dinfo, 0); 6181 } 6182 6183 void 6184 pci_restore_state(device_t dev) 6185 { 6186 struct pci_devinfo *dinfo; 6187 6188 dinfo = device_get_ivars(dev); 6189 pci_cfg_restore(dev, dinfo); 6190 } 6191 6192 static int 6193 pci_get_id_method(device_t dev, device_t child, enum pci_id_type type, 6194 uintptr_t *id) 6195 { 6196 6197 return (PCIB_GET_ID(device_get_parent(dev), child, type, id)); 6198 } 6199 6200 /* Find the upstream port of a given PCI device in a root complex. */ 6201 device_t 6202 pci_find_pcie_root_port(device_t dev) 6203 { 6204 struct pci_devinfo *dinfo; 6205 devclass_t pci_class; 6206 device_t pcib, bus; 6207 6208 pci_class = devclass_find("pci"); 6209 KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class, 6210 ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); 6211 6212 /* 6213 * Walk the bridge hierarchy until we find a PCI-e root 6214 * port or a non-PCI device. 6215 */ 6216 for (;;) { 6217 bus = device_get_parent(dev); 6218 KASSERT(bus != NULL, ("%s: null parent of %s", __func__, 6219 device_get_nameunit(dev))); 6220 6221 pcib = device_get_parent(bus); 6222 KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__, 6223 device_get_nameunit(bus))); 6224 6225 /* 6226 * pcib's parent must be a PCI bus for this to be a 6227 * PCI-PCI bridge. 6228 */ 6229 if (device_get_devclass(device_get_parent(pcib)) != pci_class) 6230 return (NULL); 6231 6232 dinfo = device_get_ivars(pcib); 6233 if (dinfo->cfg.pcie.pcie_location != 0 && 6234 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) 6235 return (pcib); 6236 6237 dev = pcib; 6238 } 6239 } 6240 6241 /* 6242 * Wait for pending transactions to complete on a PCI-express function. 6243 * 6244 * The maximum delay is specified in milliseconds in max_delay. Note 6245 * that this function may sleep. 6246 * 6247 * Returns true if the function is idle and false if the timeout is 6248 * exceeded. If dev is not a PCI-express function, this returns true. 6249 */ 6250 bool 6251 pcie_wait_for_pending_transactions(device_t dev, u_int max_delay) 6252 { 6253 struct pci_devinfo *dinfo = device_get_ivars(dev); 6254 uint16_t sta; 6255 int cap; 6256 6257 cap = dinfo->cfg.pcie.pcie_location; 6258 if (cap == 0) 6259 return (true); 6260 6261 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6262 while (sta & PCIEM_STA_TRANSACTION_PND) { 6263 if (max_delay == 0) 6264 return (false); 6265 6266 /* Poll once every 100 milliseconds up to the timeout. */ 6267 if (max_delay > 100) { 6268 pause_sbt("pcietp", 100 * SBT_1MS, 0, C_HARDCLOCK); 6269 max_delay -= 100; 6270 } else { 6271 pause_sbt("pcietp", max_delay * SBT_1MS, 0, 6272 C_HARDCLOCK); 6273 max_delay = 0; 6274 } 6275 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6276 } 6277 6278 return (true); 6279 } 6280 6281 /* 6282 * Determine the maximum Completion Timeout in microseconds. 6283 * 6284 * For non-PCI-express functions this returns 0. 6285 */ 6286 int 6287 pcie_get_max_completion_timeout(device_t dev) 6288 { 6289 struct pci_devinfo *dinfo = device_get_ivars(dev); 6290 int cap; 6291 6292 cap = dinfo->cfg.pcie.pcie_location; 6293 if (cap == 0) 6294 return (0); 6295 6296 /* 6297 * Functions using the 1.x spec use the default timeout range of 6298 * 50 microseconds to 50 milliseconds. Functions that do not 6299 * support programmable timeouts also use this range. 6300 */ 6301 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 || 6302 (pci_read_config(dev, cap + PCIER_DEVICE_CAP2, 4) & 6303 PCIEM_CAP2_COMP_TIMO_RANGES) == 0) 6304 return (50 * 1000); 6305 6306 switch (pci_read_config(dev, cap + PCIER_DEVICE_CTL2, 2) & 6307 PCIEM_CTL2_COMP_TIMO_VAL) { 6308 case PCIEM_CTL2_COMP_TIMO_100US: 6309 return (100); 6310 case PCIEM_CTL2_COMP_TIMO_10MS: 6311 return (10 * 1000); 6312 case PCIEM_CTL2_COMP_TIMO_55MS: 6313 return (55 * 1000); 6314 case PCIEM_CTL2_COMP_TIMO_210MS: 6315 return (210 * 1000); 6316 case PCIEM_CTL2_COMP_TIMO_900MS: 6317 return (900 * 1000); 6318 case PCIEM_CTL2_COMP_TIMO_3500MS: 6319 return (3500 * 1000); 6320 case PCIEM_CTL2_COMP_TIMO_13S: 6321 return (13 * 1000 * 1000); 6322 case PCIEM_CTL2_COMP_TIMO_64S: 6323 return (64 * 1000 * 1000); 6324 default: 6325 return (50 * 1000); 6326 } 6327 } 6328 6329 void 6330 pcie_apei_error(device_t dev, int sev, uint8_t *aerp) 6331 { 6332 struct pci_devinfo *dinfo = device_get_ivars(dev); 6333 const char *s; 6334 int aer; 6335 uint32_t r, r1; 6336 uint16_t rs; 6337 6338 if (sev == PCIEM_STA_CORRECTABLE_ERROR) 6339 s = "Correctable"; 6340 else if (sev == PCIEM_STA_NON_FATAL_ERROR) 6341 s = "Uncorrectable (Non-Fatal)"; 6342 else 6343 s = "Uncorrectable (Fatal)"; 6344 device_printf(dev, "%s PCIe error reported by APEI\n", s); 6345 if (aerp) { 6346 if (sev == PCIEM_STA_CORRECTABLE_ERROR) { 6347 r = le32dec(aerp + PCIR_AER_COR_STATUS); 6348 r1 = le32dec(aerp + PCIR_AER_COR_MASK); 6349 } else { 6350 r = le32dec(aerp + PCIR_AER_UC_STATUS); 6351 r1 = le32dec(aerp + PCIR_AER_UC_MASK); 6352 } 6353 device_printf(dev, "status 0x%08x mask 0x%08x", r, r1); 6354 if (sev != PCIEM_STA_CORRECTABLE_ERROR) { 6355 r = le32dec(aerp + PCIR_AER_UC_SEVERITY); 6356 rs = le16dec(aerp + PCIR_AER_CAP_CONTROL); 6357 printf(" severity 0x%08x first %d\n", 6358 r, rs & 0x1f); 6359 } else 6360 printf("\n"); 6361 } 6362 6363 /* As kind of recovery just report and clear the error statuses. */ 6364 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6365 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6366 if (r != 0) { 6367 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6368 device_printf(dev, "Clearing UC AER errors 0x%08x\n", r); 6369 } 6370 6371 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6372 if (r != 0) { 6373 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6374 device_printf(dev, "Clearing COR AER errors 0x%08x\n", r); 6375 } 6376 } 6377 if (dinfo->cfg.pcie.pcie_location != 0) { 6378 rs = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6379 PCIER_DEVICE_STA, 2); 6380 if ((rs & (PCIEM_STA_CORRECTABLE_ERROR | 6381 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6382 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6383 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6384 PCIER_DEVICE_STA, rs, 2); 6385 device_printf(dev, "Clearing PCIe errors 0x%04x\n", rs); 6386 } 6387 } 6388 } 6389 6390 /* 6391 * Perform a Function Level Reset (FLR) on a device. 6392 * 6393 * This function first waits for any pending transactions to complete 6394 * within the timeout specified by max_delay. If transactions are 6395 * still pending, the function will return false without attempting a 6396 * reset. 6397 * 6398 * If dev is not a PCI-express function or does not support FLR, this 6399 * function returns false. 6400 * 6401 * Note that no registers are saved or restored. The caller is 6402 * responsible for saving and restoring any registers including 6403 * PCI-standard registers via pci_save_state() and 6404 * pci_restore_state(). 6405 */ 6406 bool 6407 pcie_flr(device_t dev, u_int max_delay, bool force) 6408 { 6409 struct pci_devinfo *dinfo = device_get_ivars(dev); 6410 uint16_t cmd, ctl; 6411 int compl_delay; 6412 int cap; 6413 6414 cap = dinfo->cfg.pcie.pcie_location; 6415 if (cap == 0) 6416 return (false); 6417 6418 if (!(pci_read_config(dev, cap + PCIER_DEVICE_CAP, 4) & PCIEM_CAP_FLR)) 6419 return (false); 6420 6421 /* 6422 * Disable busmastering to prevent generation of new 6423 * transactions while waiting for the device to go idle. If 6424 * the idle timeout fails, the command register is restored 6425 * which will re-enable busmastering. 6426 */ 6427 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 6428 pci_write_config(dev, PCIR_COMMAND, cmd & ~(PCIM_CMD_BUSMASTEREN), 2); 6429 if (!pcie_wait_for_pending_transactions(dev, max_delay)) { 6430 if (!force) { 6431 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 6432 return (false); 6433 } 6434 pci_printf(&dinfo->cfg, 6435 "Resetting with transactions pending after %d ms\n", 6436 max_delay); 6437 6438 /* 6439 * Extend the post-FLR delay to cover the maximum 6440 * Completion Timeout delay of anything in flight 6441 * during the FLR delay. Enforce a minimum delay of 6442 * at least 10ms. 6443 */ 6444 compl_delay = pcie_get_max_completion_timeout(dev) / 1000; 6445 if (compl_delay < 10) 6446 compl_delay = 10; 6447 } else 6448 compl_delay = 0; 6449 6450 /* Initiate the reset. */ 6451 ctl = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 6452 pci_write_config(dev, cap + PCIER_DEVICE_CTL, ctl | 6453 PCIEM_CTL_INITIATE_FLR, 2); 6454 6455 /* Wait for 100ms. */ 6456 pause_sbt("pcieflr", (100 + compl_delay) * SBT_1MS, 0, C_HARDCLOCK); 6457 6458 if (pci_read_config(dev, cap + PCIER_DEVICE_STA, 2) & 6459 PCIEM_STA_TRANSACTION_PND) 6460 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n"); 6461 return (true); 6462 } 6463 6464 /* 6465 * Attempt a power-management reset by cycling the device in/out of D3 6466 * state. PCI spec says we can only go into D3 state from D0 state. 6467 * Transition from D[12] into D0 before going to D3 state. 6468 */ 6469 int 6470 pci_power_reset(device_t dev) 6471 { 6472 int ps; 6473 6474 ps = pci_get_powerstate(dev); 6475 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6476 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6477 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6478 pci_set_powerstate(dev, ps); 6479 return (0); 6480 } 6481 6482 /* 6483 * Try link drop and retrain of the downstream port of upstream 6484 * switch, for PCIe. According to the PCIe 3.0 spec 6.6.1, this must 6485 * cause Conventional Hot reset of the device in the slot. 6486 * Alternative, for PCIe, could be the secondary bus reset initiatied 6487 * on the upstream switch PCIR_BRIDGECTL_1, bit 6. 6488 */ 6489 int 6490 pcie_link_reset(device_t port, int pcie_location) 6491 { 6492 uint16_t v; 6493 6494 v = pci_read_config(port, pcie_location + PCIER_LINK_CTL, 2); 6495 v |= PCIEM_LINK_CTL_LINK_DIS; 6496 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6497 pause_sbt("pcier1", mstosbt(20), 0, 0); 6498 v &= ~PCIEM_LINK_CTL_LINK_DIS; 6499 v |= PCIEM_LINK_CTL_RETRAIN_LINK; 6500 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6501 pause_sbt("pcier2", mstosbt(100), 0, 0); /* 100 ms */ 6502 v = pci_read_config(port, pcie_location + PCIER_LINK_STA, 2); 6503 return ((v & PCIEM_LINK_STA_TRAINING) != 0 ? ETIMEDOUT : 0); 6504 } 6505 6506 static int 6507 pci_reset_post(device_t dev, device_t child) 6508 { 6509 6510 if (dev == device_get_parent(child)) 6511 pci_restore_state(child); 6512 return (0); 6513 } 6514 6515 static int 6516 pci_reset_prepare(device_t dev, device_t child) 6517 { 6518 6519 if (dev == device_get_parent(child)) 6520 pci_save_state(child); 6521 return (0); 6522 } 6523 6524 static int 6525 pci_reset_child(device_t dev, device_t child, int flags) 6526 { 6527 int error; 6528 6529 if (dev == NULL || device_get_parent(child) != dev) 6530 return (0); 6531 if ((flags & DEVF_RESET_DETACH) != 0) { 6532 error = device_get_state(child) == DS_ATTACHED ? 6533 device_detach(child) : 0; 6534 } else { 6535 error = BUS_SUSPEND_CHILD(dev, child); 6536 } 6537 if (error == 0) { 6538 if (!pcie_flr(child, 1000, false)) { 6539 error = BUS_RESET_PREPARE(dev, child); 6540 if (error == 0) 6541 pci_power_reset(child); 6542 BUS_RESET_POST(dev, child); 6543 } 6544 if ((flags & DEVF_RESET_DETACH) != 0) 6545 device_probe_and_attach(child); 6546 else 6547 BUS_RESUME_CHILD(dev, child); 6548 } 6549 return (error); 6550 } 6551 6552 const struct pci_device_table * 6553 pci_match_device(device_t child, const struct pci_device_table *id, size_t nelt) 6554 { 6555 bool match; 6556 uint16_t vendor, device, subvendor, subdevice, class, subclass, revid; 6557 6558 vendor = pci_get_vendor(child); 6559 device = pci_get_device(child); 6560 subvendor = pci_get_subvendor(child); 6561 subdevice = pci_get_subdevice(child); 6562 class = pci_get_class(child); 6563 subclass = pci_get_subclass(child); 6564 revid = pci_get_revid(child); 6565 while (nelt-- > 0) { 6566 match = true; 6567 if (id->match_flag_vendor) 6568 match &= vendor == id->vendor; 6569 if (id->match_flag_device) 6570 match &= device == id->device; 6571 if (id->match_flag_subvendor) 6572 match &= subvendor == id->subvendor; 6573 if (id->match_flag_subdevice) 6574 match &= subdevice == id->subdevice; 6575 if (id->match_flag_class) 6576 match &= class == id->class_id; 6577 if (id->match_flag_subclass) 6578 match &= subclass == id->subclass; 6579 if (id->match_flag_revid) 6580 match &= revid == id->revid; 6581 if (match) 6582 return (id); 6583 id++; 6584 } 6585 return (NULL); 6586 } 6587 6588 static void 6589 pci_print_faulted_dev_name(const struct pci_devinfo *dinfo) 6590 { 6591 const char *dev_name; 6592 device_t dev; 6593 6594 dev = dinfo->cfg.dev; 6595 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus, 6596 dinfo->cfg.slot, dinfo->cfg.func); 6597 dev_name = device_get_name(dev); 6598 if (dev_name != NULL) 6599 printf(" (%s%d)", dev_name, device_get_unit(dev)); 6600 } 6601 6602 void 6603 pci_print_faulted_dev(void) 6604 { 6605 struct pci_devinfo *dinfo; 6606 device_t dev; 6607 int aer, i; 6608 uint32_t r1, r2; 6609 uint16_t status; 6610 6611 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6612 dev = dinfo->cfg.dev; 6613 status = pci_read_config(dev, PCIR_STATUS, 2); 6614 status &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6615 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6616 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6617 if (status != 0) { 6618 pci_print_faulted_dev_name(dinfo); 6619 printf(" error 0x%04x\n", status); 6620 } 6621 if (dinfo->cfg.pcie.pcie_location != 0) { 6622 status = pci_read_config(dev, 6623 dinfo->cfg.pcie.pcie_location + 6624 PCIER_DEVICE_STA, 2); 6625 if ((status & (PCIEM_STA_CORRECTABLE_ERROR | 6626 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6627 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6628 pci_print_faulted_dev_name(dinfo); 6629 printf(" PCIe DEVCTL 0x%04x DEVSTA 0x%04x\n", 6630 pci_read_config(dev, 6631 dinfo->cfg.pcie.pcie_location + 6632 PCIER_DEVICE_CTL, 2), 6633 status); 6634 } 6635 } 6636 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6637 r1 = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6638 r2 = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6639 if (r1 != 0 || r2 != 0) { 6640 pci_print_faulted_dev_name(dinfo); 6641 printf(" AER UC 0x%08x Mask 0x%08x Svr 0x%08x\n" 6642 " COR 0x%08x Mask 0x%08x Ctl 0x%08x\n", 6643 r1, pci_read_config(dev, aer + 6644 PCIR_AER_UC_MASK, 4), 6645 pci_read_config(dev, aer + 6646 PCIR_AER_UC_SEVERITY, 4), 6647 r2, pci_read_config(dev, aer + 6648 PCIR_AER_COR_MASK, 4), 6649 pci_read_config(dev, aer + 6650 PCIR_AER_CAP_CONTROL, 4)); 6651 for (i = 0; i < 4; i++) { 6652 r1 = pci_read_config(dev, aer + 6653 PCIR_AER_HEADER_LOG + i * 4, 4); 6654 printf(" HL%d: 0x%08x\n", i, r1); 6655 } 6656 } 6657 } 6658 } 6659 } 6660 6661 #ifdef DDB 6662 DB_SHOW_COMMAND(pcierr, pci_print_faulted_dev_db) 6663 { 6664 6665 pci_print_faulted_dev(); 6666 } 6667 6668 static void 6669 db_clear_pcie_errors(const struct pci_devinfo *dinfo) 6670 { 6671 device_t dev; 6672 int aer; 6673 uint32_t r; 6674 6675 dev = dinfo->cfg.dev; 6676 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6677 PCIER_DEVICE_STA, 2); 6678 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6679 PCIER_DEVICE_STA, r, 2); 6680 6681 if (pci_find_extcap(dev, PCIZ_AER, &aer) != 0) 6682 return; 6683 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6684 if (r != 0) 6685 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6686 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6687 if (r != 0) 6688 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6689 } 6690 6691 DB_COMMAND(pci_clearerr, db_pci_clearerr) 6692 { 6693 struct pci_devinfo *dinfo; 6694 device_t dev; 6695 uint16_t status, status1; 6696 6697 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6698 dev = dinfo->cfg.dev; 6699 status1 = status = pci_read_config(dev, PCIR_STATUS, 2); 6700 status1 &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6701 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6702 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6703 if (status1 != 0) { 6704 status &= ~status1; 6705 pci_write_config(dev, PCIR_STATUS, status, 2); 6706 } 6707 if (dinfo->cfg.pcie.pcie_location != 0) 6708 db_clear_pcie_errors(dinfo); 6709 } 6710 } 6711 #endif 6712