1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 * 30 */ 31 32 #include "opt_bus.h" 33 #include "opt_pci.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/linker.h> 40 #include <sys/fcntl.h> 41 #include <sys/conf.h> 42 #include <sys/kernel.h> 43 #include <sys/queue.h> 44 #include <sys/types.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 55 #include <sys/pciio.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pci_private.h> 59 60 #include "pcib_if.h" 61 #include "pci_if.h" 62 63 static u_int32_t pci_mapbase(unsigned mapreg); 64 static int pci_maptype(unsigned mapreg); 65 static int pci_mapsize(unsigned testval); 66 static int pci_maprange(unsigned mapreg); 67 static void pci_fixancient(pcicfgregs *cfg); 68 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 69 pcicfgregs *cfg); 70 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 71 72 static int pci_porten(device_t pcib, int b, int s, int f); 73 static int pci_memen(device_t pcib, int b, int s, int f); 74 static int pci_add_map(device_t pcib, int b, int s, int f, int reg, 75 struct resource_list *rl); 76 static void pci_add_resources(device_t pcib, int b, int s, int f, 77 device_t dev); 78 static void pci_add_children(device_t dev, int busno); 79 static int pci_probe(device_t dev); 80 static int pci_describe_parse_line(char **ptr, int *vendor, 81 int *device, char **desc); 82 static char *pci_describe_device(device_t dev); 83 static int pci_modevent(module_t mod, int what, void *arg); 84 85 static device_method_t pci_methods[] = { 86 /* Device interface */ 87 DEVMETHOD(device_probe, pci_probe), 88 DEVMETHOD(device_attach, bus_generic_attach), 89 DEVMETHOD(device_shutdown, bus_generic_shutdown), 90 DEVMETHOD(device_suspend, bus_generic_suspend), 91 DEVMETHOD(device_resume, bus_generic_resume), 92 93 /* Bus interface */ 94 DEVMETHOD(bus_print_child, pci_print_child), 95 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 96 DEVMETHOD(bus_read_ivar, pci_read_ivar), 97 DEVMETHOD(bus_write_ivar, pci_write_ivar), 98 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 99 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 100 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 101 102 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 103 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 104 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 105 DEVMETHOD(bus_delete_resource, pci_delete_resource), 106 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 107 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 108 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 109 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 110 111 /* PCI interface */ 112 DEVMETHOD(pci_read_config, pci_read_config_method), 113 DEVMETHOD(pci_write_config, pci_write_config_method), 114 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 115 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 116 DEVMETHOD(pci_enable_io, pci_enable_io_method), 117 DEVMETHOD(pci_disable_io, pci_disable_io_method), 118 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 119 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 120 121 { 0, 0 } 122 }; 123 124 static driver_t pci_driver = { 125 "pci", 126 pci_methods, 127 0, /* no softc */ 128 }; 129 130 static devclass_t pci_devclass; 131 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 132 DRIVER_MODULE(pci, acpi_pcib, pci_driver, pci_devclass, pci_modevent, 0); 133 134 static char *pci_vendordata; 135 static size_t pci_vendordata_size; 136 137 138 struct pci_quirk { 139 u_int32_t devid; /* Vendor/device of the card */ 140 int type; 141 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 142 int arg1; 143 int arg2; 144 }; 145 146 struct pci_quirk pci_quirks[] = { 147 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 148 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 149 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 150 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 151 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 152 153 { 0 } 154 }; 155 156 /* map register information */ 157 #define PCI_MAPMEM 0x01 /* memory map */ 158 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 159 #define PCI_MAPPORT 0x04 /* port map */ 160 161 struct devlist pci_devq; 162 u_int32_t pci_generation; 163 u_int32_t pci_numdevs = 0; 164 165 /* Find a device_t by bus/slot/function */ 166 167 device_t 168 pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func) 169 { 170 struct pci_devinfo *dinfo; 171 172 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 173 if ((dinfo->cfg.bus == bus) && 174 (dinfo->cfg.slot == slot) && 175 (dinfo->cfg.func == func)) { 176 return (dinfo->cfg.dev); 177 } 178 } 179 180 return (NULL); 181 } 182 183 /* Find a device_t by vendor/device ID */ 184 185 device_t 186 pci_find_device (u_int16_t vendor, u_int16_t device) 187 { 188 struct pci_devinfo *dinfo; 189 190 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 191 if ((dinfo->cfg.vendor == vendor) && 192 (dinfo->cfg.device == device)) { 193 return (dinfo->cfg.dev); 194 } 195 } 196 197 return (NULL); 198 } 199 200 /* return base address of memory or port map */ 201 202 static u_int32_t 203 pci_mapbase(unsigned mapreg) 204 { 205 int mask = 0x03; 206 if ((mapreg & 0x01) == 0) 207 mask = 0x0f; 208 return (mapreg & ~mask); 209 } 210 211 /* return map type of memory or port map */ 212 213 static int 214 pci_maptype(unsigned mapreg) 215 { 216 static u_int8_t maptype[0x10] = { 217 PCI_MAPMEM, PCI_MAPPORT, 218 PCI_MAPMEM, 0, 219 PCI_MAPMEM, PCI_MAPPORT, 220 0, 0, 221 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 222 PCI_MAPMEM|PCI_MAPMEMP, 0, 223 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 224 0, 0, 225 }; 226 227 return maptype[mapreg & 0x0f]; 228 } 229 230 /* return log2 of map size decoded for memory or port map */ 231 232 static int 233 pci_mapsize(unsigned testval) 234 { 235 int ln2size; 236 237 testval = pci_mapbase(testval); 238 ln2size = 0; 239 if (testval != 0) { 240 while ((testval & 1) == 0) 241 { 242 ln2size++; 243 testval >>= 1; 244 } 245 } 246 return (ln2size); 247 } 248 249 /* return log2 of address range supported by map register */ 250 251 static int 252 pci_maprange(unsigned mapreg) 253 { 254 int ln2range = 0; 255 switch (mapreg & 0x07) { 256 case 0x00: 257 case 0x01: 258 case 0x05: 259 ln2range = 32; 260 break; 261 case 0x02: 262 ln2range = 20; 263 break; 264 case 0x04: 265 ln2range = 64; 266 break; 267 } 268 return (ln2range); 269 } 270 271 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 272 273 static void 274 pci_fixancient(pcicfgregs *cfg) 275 { 276 if (cfg->hdrtype != 0) 277 return; 278 279 /* PCI to PCI bridges use header type 1 */ 280 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 281 cfg->hdrtype = 1; 282 } 283 284 /* extract header type specific config data */ 285 286 static void 287 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 288 { 289 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 290 switch (cfg->hdrtype) { 291 case 0: 292 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 293 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 294 cfg->nummaps = PCI_MAXMAPS_0; 295 break; 296 case 1: 297 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 298 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 299 cfg->nummaps = PCI_MAXMAPS_1; 300 break; 301 case 2: 302 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 303 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 304 cfg->nummaps = PCI_MAXMAPS_2; 305 break; 306 } 307 #undef REG 308 } 309 310 /* read configuration header into pcicfgregs structure */ 311 312 struct pci_devinfo * 313 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 314 { 315 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 316 pcicfgregs *cfg = NULL; 317 struct pci_devinfo *devlist_entry; 318 struct devlist *devlist_head; 319 320 devlist_head = &pci_devq; 321 322 devlist_entry = NULL; 323 324 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 325 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 326 if (devlist_entry == NULL) 327 return (NULL); 328 329 cfg = &devlist_entry->cfg; 330 331 cfg->bus = b; 332 cfg->slot = s; 333 cfg->func = f; 334 cfg->vendor = REG(PCIR_VENDOR, 2); 335 cfg->device = REG(PCIR_DEVICE, 2); 336 cfg->cmdreg = REG(PCIR_COMMAND, 2); 337 cfg->statreg = REG(PCIR_STATUS, 2); 338 cfg->baseclass = REG(PCIR_CLASS, 1); 339 cfg->subclass = REG(PCIR_SUBCLASS, 1); 340 cfg->progif = REG(PCIR_PROGIF, 1); 341 cfg->revid = REG(PCIR_REVID, 1); 342 cfg->hdrtype = REG(PCIR_HEADERTYPE, 1); 343 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 344 cfg->lattimer = REG(PCIR_LATTIMER, 1); 345 cfg->intpin = REG(PCIR_INTPIN, 1); 346 cfg->intline = REG(PCIR_INTLINE, 1); 347 348 cfg->mingnt = REG(PCIR_MINGNT, 1); 349 cfg->maxlat = REG(PCIR_MAXLAT, 1); 350 351 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 352 cfg->hdrtype &= ~PCIM_MFDEV; 353 354 pci_fixancient(cfg); 355 pci_hdrtypedata(pcib, b, s, f, cfg); 356 357 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 358 pci_read_extcap(pcib, cfg); 359 360 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 361 362 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 363 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 364 devlist_entry->conf.pc_sel.pc_func = cfg->func; 365 devlist_entry->conf.pc_hdr = cfg->hdrtype; 366 367 devlist_entry->conf.pc_subvendor = cfg->subvendor; 368 devlist_entry->conf.pc_subdevice = cfg->subdevice; 369 devlist_entry->conf.pc_vendor = cfg->vendor; 370 devlist_entry->conf.pc_device = cfg->device; 371 372 devlist_entry->conf.pc_class = cfg->baseclass; 373 devlist_entry->conf.pc_subclass = cfg->subclass; 374 devlist_entry->conf.pc_progif = cfg->progif; 375 devlist_entry->conf.pc_revid = cfg->revid; 376 377 pci_numdevs++; 378 pci_generation++; 379 } 380 return (devlist_entry); 381 #undef REG 382 } 383 384 static void 385 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 386 { 387 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 388 int ptr, nextptr, ptrptr; 389 390 switch (cfg->hdrtype) { 391 case 0: 392 ptrptr = 0x34; 393 break; 394 case 2: 395 ptrptr = 0x14; 396 break; 397 default: 398 return; /* no extended capabilities support */ 399 } 400 nextptr = REG(ptrptr, 1); /* sanity check? */ 401 402 /* 403 * Read capability entries. 404 */ 405 while (nextptr != 0) { 406 /* Sanity check */ 407 if (nextptr > 255) { 408 printf("illegal PCI extended capability offset %d\n", 409 nextptr); 410 return; 411 } 412 /* Find the next entry */ 413 ptr = nextptr; 414 nextptr = REG(ptr + 1, 1); 415 416 /* Process this entry */ 417 switch (REG(ptr, 1)) { 418 case 0x01: /* PCI power management */ 419 if (cfg->pp_cap == 0) { 420 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 421 cfg->pp_status = ptr + PCIR_POWER_STATUS; 422 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 423 if ((nextptr - ptr) > PCIR_POWER_DATA) 424 cfg->pp_data = ptr + PCIR_POWER_DATA; 425 } 426 break; 427 default: 428 break; 429 } 430 } 431 #undef REG 432 } 433 434 /* free pcicfgregs structure and all depending data structures */ 435 436 int 437 pci_freecfg(struct pci_devinfo *dinfo) 438 { 439 struct devlist *devlist_head; 440 441 devlist_head = &pci_devq; 442 443 /* XXX this hasn't been tested */ 444 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 445 free(dinfo, M_DEVBUF); 446 447 /* increment the generation count */ 448 pci_generation++; 449 450 /* we're losing one device */ 451 pci_numdevs--; 452 return (0); 453 } 454 455 /* 456 * PCI power manangement 457 */ 458 int 459 pci_set_powerstate_method(device_t dev, device_t child, int state) 460 { 461 struct pci_devinfo *dinfo = device_get_ivars(child); 462 pcicfgregs *cfg = &dinfo->cfg; 463 u_int16_t status; 464 int result; 465 466 if (cfg->pp_cap != 0) { 467 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK; 468 result = 0; 469 switch (state) { 470 case PCI_POWERSTATE_D0: 471 status |= PCIM_PSTAT_D0; 472 break; 473 case PCI_POWERSTATE_D1: 474 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) { 475 status |= PCIM_PSTAT_D1; 476 } else { 477 result = EOPNOTSUPP; 478 } 479 break; 480 case PCI_POWERSTATE_D2: 481 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) { 482 status |= PCIM_PSTAT_D2; 483 } else { 484 result = EOPNOTSUPP; 485 } 486 break; 487 case PCI_POWERSTATE_D3: 488 status |= PCIM_PSTAT_D3; 489 break; 490 default: 491 result = EINVAL; 492 } 493 if (result == 0) 494 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2); 495 } else { 496 result = ENXIO; 497 } 498 return(result); 499 } 500 501 int 502 pci_get_powerstate_method(device_t dev, device_t child) 503 { 504 struct pci_devinfo *dinfo = device_get_ivars(child); 505 pcicfgregs *cfg = &dinfo->cfg; 506 u_int16_t status; 507 int result; 508 509 if (cfg->pp_cap != 0) { 510 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2); 511 switch (status & PCIM_PSTAT_DMASK) { 512 case PCIM_PSTAT_D0: 513 result = PCI_POWERSTATE_D0; 514 break; 515 case PCIM_PSTAT_D1: 516 result = PCI_POWERSTATE_D1; 517 break; 518 case PCIM_PSTAT_D2: 519 result = PCI_POWERSTATE_D2; 520 break; 521 case PCIM_PSTAT_D3: 522 result = PCI_POWERSTATE_D3; 523 break; 524 default: 525 result = PCI_POWERSTATE_UNKNOWN; 526 break; 527 } 528 } else { 529 /* No support, device is always at D0 */ 530 result = PCI_POWERSTATE_D0; 531 } 532 return(result); 533 } 534 535 /* 536 * Some convenience functions for PCI device drivers. 537 */ 538 539 static __inline void 540 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit) 541 { 542 u_int16_t command; 543 544 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 545 command |= bit; 546 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 547 } 548 549 static __inline void 550 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit) 551 { 552 u_int16_t command; 553 554 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 555 command &= ~bit; 556 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 557 } 558 559 void 560 pci_enable_busmaster_method(device_t dev, device_t child) 561 { 562 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 563 } 564 565 void 566 pci_disable_busmaster_method(device_t dev, device_t child) 567 { 568 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 569 } 570 571 void 572 pci_enable_io_method(device_t dev, device_t child, int space) 573 { 574 switch(space) { 575 case SYS_RES_IOPORT: 576 pci_set_command_bit(dev, child, PCIM_CMD_PORTEN); 577 break; 578 case SYS_RES_MEMORY: 579 pci_set_command_bit(dev, child, PCIM_CMD_MEMEN); 580 break; 581 } 582 } 583 584 void 585 pci_disable_io_method(device_t dev, device_t child, int space) 586 { 587 switch(space) { 588 case SYS_RES_IOPORT: 589 pci_clear_command_bit(dev, child, PCIM_CMD_PORTEN); 590 break; 591 case SYS_RES_MEMORY: 592 pci_clear_command_bit(dev, child, PCIM_CMD_MEMEN); 593 break; 594 } 595 } 596 597 /* 598 * New style pci driver. Parent device is either a pci-host-bridge or a 599 * pci-pci-bridge. Both kinds are represented by instances of pcib. 600 */ 601 602 void 603 pci_print_verbose(struct pci_devinfo *dinfo) 604 { 605 if (bootverbose) { 606 pcicfgregs *cfg = &dinfo->cfg; 607 608 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 609 cfg->vendor, cfg->device, cfg->revid); 610 printf("\tbus=%d, slot=%d, func=%d\n", 611 cfg->bus, cfg->slot, cfg->func); 612 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 613 cfg->baseclass, cfg->subclass, cfg->progif, 614 cfg->hdrtype, cfg->mfdev); 615 #ifdef PCI_DEBUG 616 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 617 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 618 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 619 cfg->lattimer, cfg->lattimer * 30, 620 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 621 #endif /* PCI_DEBUG */ 622 if (cfg->intpin > 0) 623 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 624 if (cfg->pp_cap) { 625 u_int16_t status; 626 627 status = pci_read_config(cfg->dev, cfg->pp_status, 2); 628 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 629 cfg->pp_cap & PCIM_PCAP_SPEC, 630 cfg->pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 631 cfg->pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 632 status & PCIM_PSTAT_DMASK); 633 } 634 } 635 } 636 637 static int 638 pci_porten(device_t pcib, int b, int s, int f) 639 { 640 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 641 & PCIM_CMD_PORTEN) != 0; 642 } 643 644 static int 645 pci_memen(device_t pcib, int b, int s, int f) 646 { 647 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 648 & PCIM_CMD_MEMEN) != 0; 649 } 650 651 /* 652 * Add a resource based on a pci map register. Return 1 if the map 653 * register is a 32bit map register or 2 if it is a 64bit register. 654 */ 655 static int 656 pci_add_map(device_t pcib, int b, int s, int f, int reg, 657 struct resource_list *rl) 658 { 659 u_int32_t map; 660 u_int64_t base; 661 u_int8_t ln2size; 662 u_int8_t ln2range; 663 u_int32_t testval; 664 #ifdef PCI_ENABLE_IO_MODES 665 u_int16_t cmd; 666 #endif 667 int type; 668 669 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 670 671 if (map == 0 || map == 0xffffffff) 672 return 1; /* skip invalid entry */ 673 674 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 675 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 676 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 677 678 base = pci_mapbase(map); 679 if (pci_maptype(map) & PCI_MAPMEM) 680 type = SYS_RES_MEMORY; 681 else 682 type = SYS_RES_IOPORT; 683 ln2size = pci_mapsize(testval); 684 ln2range = pci_maprange(testval); 685 if (ln2range == 64) { 686 /* Read the other half of a 64bit map register */ 687 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 688 } 689 690 if (bootverbose) { 691 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 692 reg, pci_maptype(map), ln2range, 693 (unsigned int) base, ln2size); 694 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 695 printf(", port disabled\n"); 696 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 697 printf(", memory disabled\n"); 698 else 699 printf(", enabled\n"); 700 } 701 702 /* 703 * This code theoretically does the right thing, but has 704 * undesirable side effects in some cases where 705 * peripherals respond oddly to having these bits 706 * enabled. Leave them alone by default. 707 */ 708 #ifdef PCI_ENABLE_IO_MODES 709 /* Turn on resources that have been left off by a lazy BIOS */ 710 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 711 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 712 cmd |= PCIM_CMD_PORTEN; 713 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 714 } 715 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 716 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 717 cmd |= PCIM_CMD_MEMEN; 718 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 719 } 720 #else 721 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 722 return 1; 723 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 724 return 1; 725 #endif 726 727 resource_list_add(rl, type, reg, 728 base, base + (1 << ln2size) - 1, 729 (1 << ln2size)); 730 731 return (ln2range == 64) ? 2 : 1; 732 } 733 734 static void 735 pci_add_resources(device_t pcib, int b, int s, int f, device_t dev) 736 { 737 struct pci_devinfo *dinfo = device_get_ivars(dev); 738 pcicfgregs *cfg = &dinfo->cfg; 739 struct resource_list *rl = &dinfo->resources; 740 struct pci_quirk *q; 741 int i; 742 743 for (i = 0; i < cfg->nummaps;) { 744 i += pci_add_map(pcib, b, s, f, PCIR_MAPS + i*4, rl); 745 } 746 747 for (q = &pci_quirks[0]; q->devid; q++) { 748 if (q->devid == ((cfg->device << 16) | cfg->vendor) 749 && q->type == PCI_QUIRK_MAP_REG) 750 pci_add_map(pcib, b, s, f, q->arg1, rl); 751 } 752 753 if (cfg->intpin > 0 && cfg->intline != 255) { 754 #ifdef __ia64__ 755 /* 756 * Re-route interrupts on ia64 so that we can get the 757 * I/O SAPIC interrupt numbers (the BIOS leaves legacy 758 * PIC interrupt numbers in the intline registers). 759 */ 760 cfg->intline = PCIB_ROUTE_INTERRUPT(pcib, 761 dev, 762 cfg->intpin); 763 #endif 764 resource_list_add(rl, SYS_RES_IRQ, 0, 765 cfg->intline, cfg->intline, 1); 766 } 767 } 768 769 static void 770 pci_add_children(device_t dev, int busno) 771 { 772 device_t pcib = device_get_parent(dev); 773 int maxslots; 774 int s, f; 775 776 maxslots = PCIB_MAXSLOTS(pcib); 777 778 for (s = 0; s <= maxslots; s++) { 779 int pcifunchigh = 0; 780 for (f = 0; f <= pcifunchigh; f++) { 781 struct pci_devinfo *dinfo = pci_read_device(pcib, 782 busno, s, f, sizeof(struct pci_devinfo)); 783 if (dinfo != NULL) { 784 if (dinfo->cfg.mfdev) 785 pcifunchigh = PCI_FUNCMAX; 786 787 dinfo->cfg.dev = device_add_child(dev, NULL, -1); 788 device_set_ivars(dinfo->cfg.dev, dinfo); 789 pci_add_resources(pcib, busno, s, f, 790 dinfo->cfg.dev); 791 pci_print_verbose(dinfo); 792 } 793 } 794 } 795 } 796 797 static int 798 pci_probe(device_t dev) 799 { 800 static int once, busno; 801 caddr_t vendordata, info; 802 803 device_set_desc(dev, "PCI bus"); 804 805 if (bootverbose) 806 device_printf(dev, "physical bus=%d\n", pcib_get_bus(dev)); 807 808 /* 809 * Since there can be multiple independantly numbered PCI 810 * busses on some large alpha systems, we can't use the unit 811 * number to decide what bus we are probing. We ask the parent 812 * pcib what our bus number is. 813 */ 814 busno = pcib_get_bus(dev); 815 if (busno < 0) 816 return ENXIO; 817 pci_add_children(dev, busno); 818 819 if (!once) { 820 make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, "pci"); 821 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 822 info = preload_search_info(vendordata, MODINFO_ADDR); 823 pci_vendordata = *(char **)info; 824 info = preload_search_info(vendordata, MODINFO_SIZE); 825 pci_vendordata_size = *(size_t *)info; 826 /* terminate the database */ 827 pci_vendordata[pci_vendordata_size] = '\n'; 828 } 829 once++; 830 } 831 832 return 0; 833 } 834 835 int 836 pci_print_child(device_t dev, device_t child) 837 { 838 struct pci_devinfo *dinfo; 839 struct resource_list *rl; 840 pcicfgregs *cfg; 841 int retval = 0; 842 843 dinfo = device_get_ivars(child); 844 cfg = &dinfo->cfg; 845 rl = &dinfo->resources; 846 847 retval += bus_print_child_header(dev, child); 848 849 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 850 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 851 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 852 if (device_get_flags(dev)) 853 retval += printf(" flags %#x", device_get_flags(dev)); 854 855 retval += printf(" at device %d.%d", pci_get_slot(child), 856 pci_get_function(child)); 857 858 retval += bus_print_child_footer(dev, child); 859 860 return (retval); 861 } 862 863 static struct 864 { 865 int class; 866 int subclass; 867 char *desc; 868 } pci_nomatch_tab[] = { 869 {PCIC_OLD, -1, "old"}, 870 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 871 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 872 {PCIC_STORAGE, -1, "mass storage"}, 873 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 874 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 875 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 876 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 877 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 878 {PCIC_NETWORK, -1, "network"}, 879 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 880 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 881 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 882 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 883 {PCIC_DISPLAY, -1, "display"}, 884 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 885 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 886 {PCIC_MULTIMEDIA, -1, "multimedia"}, 887 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 888 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 889 {PCIC_MEMORY, -1, "memory"}, 890 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 891 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 892 {PCIC_BRIDGE, -1, "bridge"}, 893 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 894 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 895 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 896 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 897 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 898 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 899 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 900 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 901 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 902 {PCIC_SIMPLECOMM, -1, "simple comms"}, 903 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 904 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 905 {PCIC_BASEPERIPH, -1, "base peripheral"}, 906 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 907 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 908 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 909 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 910 {PCIC_INPUTDEV, -1, "input device"}, 911 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 912 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 913 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 914 {PCIC_DOCKING, -1, "docking station"}, 915 {PCIC_PROCESSOR, -1, "processor"}, 916 {PCIC_SERIALBUS, -1, "serial bus"}, 917 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 918 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 919 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 920 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 921 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 922 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 923 {0, 0, NULL} 924 }; 925 926 void 927 pci_probe_nomatch(device_t dev, device_t child) 928 { 929 int i; 930 char *cp, *scp, *device; 931 932 /* 933 * Look for a listing for this device in a loaded device database. 934 */ 935 if ((device = pci_describe_device(child)) != NULL) { 936 device_printf(dev, "<%s>", device); 937 free(device, M_DEVBUF); 938 } else { 939 /* 940 * Scan the class/subclass descriptions for a general description. 941 */ 942 cp = "unknown"; 943 scp = NULL; 944 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 945 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 946 if (pci_nomatch_tab[i].subclass == -1) { 947 cp = pci_nomatch_tab[i].desc; 948 } else if (pci_nomatch_tab[i].subclass == pci_get_subclass(child)) { 949 scp = pci_nomatch_tab[i].desc; 950 } 951 } 952 } 953 device_printf(dev, "<%s%s%s>", 954 cp ? : "", 955 ((cp != NULL) && (scp != NULL)) ? ", " : "", 956 scp ? : ""); 957 } 958 printf(" at device %d.%d (no driver attached)\n", 959 pci_get_slot(child), 960 pci_get_function(child)); 961 return; 962 } 963 964 /* 965 * Parse the PCI device database, if loaded, and return a pointer to a 966 * description of the device. 967 * 968 * The database is flat text formatted as follows: 969 * 970 * Any line not in a valid format is ignored. 971 * Lines are terminated with newline '\n' characters. 972 * 973 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 974 * the vendor name. 975 * 976 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 977 * - devices cannot be listed without a corresponding VENDOR line. 978 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 979 * another TAB, then the device name. 980 */ 981 982 /* 983 * Assuming (ptr) points to the beginning of a line in the database, 984 * return the vendor or device and description of the next entry. 985 * The value of (vendor) or (device) inappropriate for the entry type 986 * is set to -1. Returns nonzero at the end of the database. 987 * 988 * Note that this is slightly unrobust in the face of corrupt data; 989 * we attempt to safeguard against this by spamming the end of the 990 * database with a newline when we initialise. 991 */ 992 static int 993 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 994 { 995 char *cp = *ptr; 996 int left; 997 998 *device = -1; 999 *vendor = -1; 1000 **desc = '\0'; 1001 for (;;) { 1002 left = pci_vendordata_size - (cp - pci_vendordata); 1003 if (left <= 0) { 1004 *ptr = cp; 1005 return(1); 1006 } 1007 1008 /* vendor entry? */ 1009 if (*cp != '\t' && sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1010 break; 1011 /* device entry? */ 1012 if (*cp == '\t' && sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1013 break; 1014 1015 /* skip to next line */ 1016 while (*cp != '\n' && left > 0) { 1017 cp++; 1018 left--; 1019 } 1020 if (*cp == '\n') { 1021 cp++; 1022 left--; 1023 } 1024 } 1025 /* skip to next line */ 1026 while (*cp != '\n' && left > 0) { 1027 cp++; 1028 left--; 1029 } 1030 if (*cp == '\n' && left > 0) 1031 cp++; 1032 *ptr = cp; 1033 return(0); 1034 } 1035 1036 static char * 1037 pci_describe_device(device_t dev) 1038 { 1039 int vendor, device; 1040 char *desc, *vp, *dp, *line; 1041 1042 desc = vp = dp = NULL; 1043 1044 /* 1045 * If we have no vendor data, we can't do anything. 1046 */ 1047 if (pci_vendordata == NULL) 1048 goto out; 1049 1050 /* 1051 * Scan the vendor data looking for this device 1052 */ 1053 line = pci_vendordata; 1054 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1055 goto out; 1056 for (;;) { 1057 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1058 goto out; 1059 if (vendor == pci_get_vendor(dev)) 1060 break; 1061 } 1062 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1063 goto out; 1064 for (;;) { 1065 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1066 *dp = 0; 1067 break; 1068 } 1069 if (vendor != -1) { 1070 *dp = 0; 1071 break; 1072 } 1073 if (device == pci_get_device(dev)) 1074 break; 1075 } 1076 if (dp[0] == '\0') 1077 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1078 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != NULL) 1079 sprintf(desc, "%s, %s", vp, dp); 1080 out: 1081 if (vp != NULL) 1082 free(vp, M_DEVBUF); 1083 if (dp != NULL) 1084 free(dp, M_DEVBUF); 1085 return(desc); 1086 } 1087 1088 int 1089 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1090 { 1091 struct pci_devinfo *dinfo; 1092 pcicfgregs *cfg; 1093 1094 dinfo = device_get_ivars(child); 1095 cfg = &dinfo->cfg; 1096 1097 switch (which) { 1098 case PCI_IVAR_SUBVENDOR: 1099 *result = cfg->subvendor; 1100 break; 1101 case PCI_IVAR_SUBDEVICE: 1102 *result = cfg->subdevice; 1103 break; 1104 case PCI_IVAR_VENDOR: 1105 *result = cfg->vendor; 1106 break; 1107 case PCI_IVAR_DEVICE: 1108 *result = cfg->device; 1109 break; 1110 case PCI_IVAR_DEVID: 1111 *result = (cfg->device << 16) | cfg->vendor; 1112 break; 1113 case PCI_IVAR_CLASS: 1114 *result = cfg->baseclass; 1115 break; 1116 case PCI_IVAR_SUBCLASS: 1117 *result = cfg->subclass; 1118 break; 1119 case PCI_IVAR_PROGIF: 1120 *result = cfg->progif; 1121 break; 1122 case PCI_IVAR_REVID: 1123 *result = cfg->revid; 1124 break; 1125 case PCI_IVAR_INTPIN: 1126 *result = cfg->intpin; 1127 break; 1128 case PCI_IVAR_IRQ: 1129 *result = cfg->intline; 1130 break; 1131 case PCI_IVAR_BUS: 1132 *result = cfg->bus; 1133 break; 1134 case PCI_IVAR_SLOT: 1135 *result = cfg->slot; 1136 break; 1137 case PCI_IVAR_FUNCTION: 1138 *result = cfg->func; 1139 break; 1140 default: 1141 return ENOENT; 1142 } 1143 return 0; 1144 } 1145 1146 int 1147 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1148 { 1149 struct pci_devinfo *dinfo; 1150 pcicfgregs *cfg; 1151 1152 dinfo = device_get_ivars(child); 1153 cfg = &dinfo->cfg; 1154 1155 switch (which) { 1156 case PCI_IVAR_SUBVENDOR: 1157 case PCI_IVAR_SUBDEVICE: 1158 case PCI_IVAR_VENDOR: 1159 case PCI_IVAR_DEVICE: 1160 case PCI_IVAR_DEVID: 1161 case PCI_IVAR_CLASS: 1162 case PCI_IVAR_SUBCLASS: 1163 case PCI_IVAR_PROGIF: 1164 case PCI_IVAR_REVID: 1165 case PCI_IVAR_INTPIN: 1166 case PCI_IVAR_IRQ: 1167 case PCI_IVAR_BUS: 1168 case PCI_IVAR_SLOT: 1169 case PCI_IVAR_FUNCTION: 1170 return EINVAL; /* disallow for now */ 1171 1172 default: 1173 return ENOENT; 1174 } 1175 return 0; 1176 } 1177 1178 struct resource * 1179 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1180 u_long start, u_long end, u_long count, u_int flags) 1181 { 1182 struct pci_devinfo *dinfo = device_get_ivars(child); 1183 struct resource_list *rl = &dinfo->resources; 1184 pcicfgregs *cfg = &dinfo->cfg; 1185 1186 /* 1187 * Perform lazy resource allocation 1188 * 1189 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY 1190 */ 1191 if (device_get_parent(child) == dev) { 1192 /* 1193 * If device doesn't have an interrupt routed, and is deserving of 1194 * an interrupt, try to assign it one. 1195 */ 1196 if ((type == SYS_RES_IRQ) && (cfg->intline == 255 || cfg->intline == 0) && (cfg->intpin != 0)) { 1197 cfg->intline = PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1198 cfg->intpin); 1199 if (cfg->intline != 255) { 1200 pci_write_config(child, PCIR_INTLINE, cfg->intline, 1); 1201 resource_list_add(rl, SYS_RES_IRQ, 0, 1202 cfg->intline, cfg->intline, 1); 1203 } 1204 } 1205 } 1206 1207 return resource_list_alloc(rl, dev, child, type, rid, 1208 start, end, count, flags); 1209 } 1210 1211 void 1212 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1213 { 1214 struct pci_devinfo *dinfo; 1215 struct resource_list *rl; 1216 struct resource_list_entry *rle; 1217 1218 if (device_get_parent(child) != dev) 1219 return; 1220 1221 dinfo = device_get_ivars(child); 1222 rl = &dinfo->resources; 1223 rle = resource_list_find(rl, type, rid); 1224 if (rle) { 1225 if (rle->res) { 1226 if (rle->res->r_dev != dev || 1227 rman_get_flags(rle->res) & RF_ACTIVE) { 1228 device_printf(dev, "delete_resource: " 1229 "Resource still owned by child, oops. " 1230 "(type=%d, rid=%d, addr=%lx)\n", 1231 rle->type, rle->rid, 1232 rman_get_start(rle->res)); 1233 return; 1234 } 1235 bus_release_resource(dev, type, rid, rle->res); 1236 } 1237 resource_list_delete(rl, type, rid); 1238 } 1239 /* I don't understand the next line */ 1240 pci_write_config(child, rid, 0, 4); 1241 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1242 } 1243 1244 struct resource_list * 1245 pci_get_resource_list (device_t dev, device_t child) 1246 { 1247 struct pci_devinfo * dinfo = device_get_ivars(child); 1248 struct resource_list * rl = &dinfo->resources; 1249 1250 if (!rl) 1251 return (NULL); 1252 1253 return (rl); 1254 } 1255 1256 u_int32_t 1257 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1258 { 1259 struct pci_devinfo *dinfo = device_get_ivars(child); 1260 pcicfgregs *cfg = &dinfo->cfg; 1261 1262 return PCIB_READ_CONFIG(device_get_parent(dev), 1263 cfg->bus, cfg->slot, cfg->func, 1264 reg, width); 1265 } 1266 1267 void 1268 pci_write_config_method(device_t dev, device_t child, int reg, 1269 u_int32_t val, int width) 1270 { 1271 struct pci_devinfo *dinfo = device_get_ivars(child); 1272 pcicfgregs *cfg = &dinfo->cfg; 1273 1274 PCIB_WRITE_CONFIG(device_get_parent(dev), 1275 cfg->bus, cfg->slot, cfg->func, 1276 reg, val, width); 1277 } 1278 1279 static int 1280 pci_modevent(module_t mod, int what, void *arg) 1281 { 1282 switch (what) { 1283 case MOD_LOAD: 1284 STAILQ_INIT(&pci_devq); 1285 pci_generation = 0; 1286 break; 1287 1288 case MOD_UNLOAD: 1289 break; 1290 } 1291 1292 return 0; 1293 } 1294