1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 * 30 */ 31 32 #include "opt_bus.h" 33 #include "opt_pci.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/linker.h> 40 #include <sys/fcntl.h> 41 #include <sys/conf.h> 42 #include <sys/kernel.h> 43 #include <sys/queue.h> 44 #include <sys/types.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 55 #include <sys/pciio.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pci_private.h> 59 60 #include "pcib_if.h" 61 #include "pci_if.h" 62 63 static u_int32_t pci_mapbase(unsigned mapreg); 64 static int pci_maptype(unsigned mapreg); 65 static int pci_mapsize(unsigned testval); 66 static int pci_maprange(unsigned mapreg); 67 static void pci_fixancient(pcicfgregs *cfg); 68 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 69 pcicfgregs *cfg); 70 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 71 72 static int pci_porten(device_t pcib, int b, int s, int f); 73 static int pci_memen(device_t pcib, int b, int s, int f); 74 static int pci_add_map(device_t pcib, int b, int s, int f, int reg, 75 struct resource_list *rl); 76 static void pci_add_resources(device_t pcib, int b, int s, int f, 77 device_t dev); 78 static void pci_add_children(device_t dev, int busno); 79 static int pci_probe(device_t dev); 80 static int pci_describe_parse_line(char **ptr, int *vendor, 81 int *device, char **desc); 82 static char *pci_describe_device(device_t dev); 83 static int pci_modevent(module_t mod, int what, void *arg); 84 85 static device_method_t pci_methods[] = { 86 /* Device interface */ 87 DEVMETHOD(device_probe, pci_probe), 88 DEVMETHOD(device_attach, bus_generic_attach), 89 DEVMETHOD(device_shutdown, bus_generic_shutdown), 90 DEVMETHOD(device_suspend, bus_generic_suspend), 91 DEVMETHOD(device_resume, bus_generic_resume), 92 93 /* Bus interface */ 94 DEVMETHOD(bus_print_child, pci_print_child), 95 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 96 DEVMETHOD(bus_read_ivar, pci_read_ivar), 97 DEVMETHOD(bus_write_ivar, pci_write_ivar), 98 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 99 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 100 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 101 102 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 103 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 104 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 105 DEVMETHOD(bus_delete_resource, pci_delete_resource), 106 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 107 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 108 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 109 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 110 111 /* PCI interface */ 112 DEVMETHOD(pci_read_config, pci_read_config_method), 113 DEVMETHOD(pci_write_config, pci_write_config_method), 114 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 115 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 116 DEVMETHOD(pci_enable_io, pci_enable_io_method), 117 DEVMETHOD(pci_disable_io, pci_disable_io_method), 118 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 119 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 120 121 { 0, 0 } 122 }; 123 124 static driver_t pci_driver = { 125 "pci", 126 pci_methods, 127 0, /* no softc */ 128 }; 129 130 static devclass_t pci_devclass; 131 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 132 DRIVER_MODULE(pci, acpi_pcib, pci_driver, pci_devclass, pci_modevent, 0); 133 MODULE_VERSION(pci, 1); 134 135 static char *pci_vendordata; 136 static size_t pci_vendordata_size; 137 138 139 struct pci_quirk { 140 u_int32_t devid; /* Vendor/device of the card */ 141 int type; 142 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 143 int arg1; 144 int arg2; 145 }; 146 147 struct pci_quirk pci_quirks[] = { 148 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 149 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 150 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 151 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 152 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 153 154 { 0 } 155 }; 156 157 /* map register information */ 158 #define PCI_MAPMEM 0x01 /* memory map */ 159 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 160 #define PCI_MAPPORT 0x04 /* port map */ 161 162 struct devlist pci_devq; 163 u_int32_t pci_generation; 164 u_int32_t pci_numdevs = 0; 165 166 /* Find a device_t by bus/slot/function */ 167 168 device_t 169 pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func) 170 { 171 struct pci_devinfo *dinfo; 172 173 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 174 if ((dinfo->cfg.bus == bus) && 175 (dinfo->cfg.slot == slot) && 176 (dinfo->cfg.func == func)) { 177 return (dinfo->cfg.dev); 178 } 179 } 180 181 return (NULL); 182 } 183 184 /* Find a device_t by vendor/device ID */ 185 186 device_t 187 pci_find_device (u_int16_t vendor, u_int16_t device) 188 { 189 struct pci_devinfo *dinfo; 190 191 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 192 if ((dinfo->cfg.vendor == vendor) && 193 (dinfo->cfg.device == device)) { 194 return (dinfo->cfg.dev); 195 } 196 } 197 198 return (NULL); 199 } 200 201 /* return base address of memory or port map */ 202 203 static u_int32_t 204 pci_mapbase(unsigned mapreg) 205 { 206 int mask = 0x03; 207 if ((mapreg & 0x01) == 0) 208 mask = 0x0f; 209 return (mapreg & ~mask); 210 } 211 212 /* return map type of memory or port map */ 213 214 static int 215 pci_maptype(unsigned mapreg) 216 { 217 static u_int8_t maptype[0x10] = { 218 PCI_MAPMEM, PCI_MAPPORT, 219 PCI_MAPMEM, 0, 220 PCI_MAPMEM, PCI_MAPPORT, 221 0, 0, 222 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 223 PCI_MAPMEM|PCI_MAPMEMP, 0, 224 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 225 0, 0, 226 }; 227 228 return maptype[mapreg & 0x0f]; 229 } 230 231 /* return log2 of map size decoded for memory or port map */ 232 233 static int 234 pci_mapsize(unsigned testval) 235 { 236 int ln2size; 237 238 testval = pci_mapbase(testval); 239 ln2size = 0; 240 if (testval != 0) { 241 while ((testval & 1) == 0) 242 { 243 ln2size++; 244 testval >>= 1; 245 } 246 } 247 return (ln2size); 248 } 249 250 /* return log2 of address range supported by map register */ 251 252 static int 253 pci_maprange(unsigned mapreg) 254 { 255 int ln2range = 0; 256 switch (mapreg & 0x07) { 257 case 0x00: 258 case 0x01: 259 case 0x05: 260 ln2range = 32; 261 break; 262 case 0x02: 263 ln2range = 20; 264 break; 265 case 0x04: 266 ln2range = 64; 267 break; 268 } 269 return (ln2range); 270 } 271 272 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 273 274 static void 275 pci_fixancient(pcicfgregs *cfg) 276 { 277 if (cfg->hdrtype != 0) 278 return; 279 280 /* PCI to PCI bridges use header type 1 */ 281 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 282 cfg->hdrtype = 1; 283 } 284 285 /* extract header type specific config data */ 286 287 static void 288 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 289 { 290 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 291 switch (cfg->hdrtype) { 292 case 0: 293 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 294 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 295 cfg->nummaps = PCI_MAXMAPS_0; 296 break; 297 case 1: 298 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 299 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 300 cfg->nummaps = PCI_MAXMAPS_1; 301 break; 302 case 2: 303 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 304 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 305 cfg->nummaps = PCI_MAXMAPS_2; 306 break; 307 } 308 #undef REG 309 } 310 311 /* read configuration header into pcicfgregs structure */ 312 313 struct pci_devinfo * 314 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 315 { 316 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 317 pcicfgregs *cfg = NULL; 318 struct pci_devinfo *devlist_entry; 319 struct devlist *devlist_head; 320 321 devlist_head = &pci_devq; 322 323 devlist_entry = NULL; 324 325 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 326 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 327 if (devlist_entry == NULL) 328 return (NULL); 329 330 cfg = &devlist_entry->cfg; 331 332 cfg->bus = b; 333 cfg->slot = s; 334 cfg->func = f; 335 cfg->vendor = REG(PCIR_VENDOR, 2); 336 cfg->device = REG(PCIR_DEVICE, 2); 337 cfg->cmdreg = REG(PCIR_COMMAND, 2); 338 cfg->statreg = REG(PCIR_STATUS, 2); 339 cfg->baseclass = REG(PCIR_CLASS, 1); 340 cfg->subclass = REG(PCIR_SUBCLASS, 1); 341 cfg->progif = REG(PCIR_PROGIF, 1); 342 cfg->revid = REG(PCIR_REVID, 1); 343 cfg->hdrtype = REG(PCIR_HEADERTYPE, 1); 344 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 345 cfg->lattimer = REG(PCIR_LATTIMER, 1); 346 cfg->intpin = REG(PCIR_INTPIN, 1); 347 cfg->intline = REG(PCIR_INTLINE, 1); 348 349 cfg->mingnt = REG(PCIR_MINGNT, 1); 350 cfg->maxlat = REG(PCIR_MAXLAT, 1); 351 352 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 353 cfg->hdrtype &= ~PCIM_MFDEV; 354 355 pci_fixancient(cfg); 356 pci_hdrtypedata(pcib, b, s, f, cfg); 357 358 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 359 pci_read_extcap(pcib, cfg); 360 361 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 362 363 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 364 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 365 devlist_entry->conf.pc_sel.pc_func = cfg->func; 366 devlist_entry->conf.pc_hdr = cfg->hdrtype; 367 368 devlist_entry->conf.pc_subvendor = cfg->subvendor; 369 devlist_entry->conf.pc_subdevice = cfg->subdevice; 370 devlist_entry->conf.pc_vendor = cfg->vendor; 371 devlist_entry->conf.pc_device = cfg->device; 372 373 devlist_entry->conf.pc_class = cfg->baseclass; 374 devlist_entry->conf.pc_subclass = cfg->subclass; 375 devlist_entry->conf.pc_progif = cfg->progif; 376 devlist_entry->conf.pc_revid = cfg->revid; 377 378 pci_numdevs++; 379 pci_generation++; 380 } 381 return (devlist_entry); 382 #undef REG 383 } 384 385 static void 386 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 387 { 388 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 389 int ptr, nextptr, ptrptr; 390 391 switch (cfg->hdrtype) { 392 case 0: 393 ptrptr = 0x34; 394 break; 395 case 2: 396 ptrptr = 0x14; 397 break; 398 default: 399 return; /* no extended capabilities support */ 400 } 401 nextptr = REG(ptrptr, 1); /* sanity check? */ 402 403 /* 404 * Read capability entries. 405 */ 406 while (nextptr != 0) { 407 /* Sanity check */ 408 if (nextptr > 255) { 409 printf("illegal PCI extended capability offset %d\n", 410 nextptr); 411 return; 412 } 413 /* Find the next entry */ 414 ptr = nextptr; 415 nextptr = REG(ptr + 1, 1); 416 417 /* Process this entry */ 418 switch (REG(ptr, 1)) { 419 case 0x01: /* PCI power management */ 420 if (cfg->pp_cap == 0) { 421 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 422 cfg->pp_status = ptr + PCIR_POWER_STATUS; 423 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 424 if ((nextptr - ptr) > PCIR_POWER_DATA) 425 cfg->pp_data = ptr + PCIR_POWER_DATA; 426 } 427 break; 428 default: 429 break; 430 } 431 } 432 #undef REG 433 } 434 435 /* free pcicfgregs structure and all depending data structures */ 436 437 int 438 pci_freecfg(struct pci_devinfo *dinfo) 439 { 440 struct devlist *devlist_head; 441 442 devlist_head = &pci_devq; 443 444 /* XXX this hasn't been tested */ 445 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 446 free(dinfo, M_DEVBUF); 447 448 /* increment the generation count */ 449 pci_generation++; 450 451 /* we're losing one device */ 452 pci_numdevs--; 453 return (0); 454 } 455 456 /* 457 * PCI power manangement 458 */ 459 int 460 pci_set_powerstate_method(device_t dev, device_t child, int state) 461 { 462 struct pci_devinfo *dinfo = device_get_ivars(child); 463 pcicfgregs *cfg = &dinfo->cfg; 464 u_int16_t status; 465 int result; 466 467 if (cfg->pp_cap != 0) { 468 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK; 469 result = 0; 470 switch (state) { 471 case PCI_POWERSTATE_D0: 472 status |= PCIM_PSTAT_D0; 473 break; 474 case PCI_POWERSTATE_D1: 475 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) { 476 status |= PCIM_PSTAT_D1; 477 } else { 478 result = EOPNOTSUPP; 479 } 480 break; 481 case PCI_POWERSTATE_D2: 482 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) { 483 status |= PCIM_PSTAT_D2; 484 } else { 485 result = EOPNOTSUPP; 486 } 487 break; 488 case PCI_POWERSTATE_D3: 489 status |= PCIM_PSTAT_D3; 490 break; 491 default: 492 result = EINVAL; 493 } 494 if (result == 0) 495 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2); 496 } else { 497 result = ENXIO; 498 } 499 return(result); 500 } 501 502 int 503 pci_get_powerstate_method(device_t dev, device_t child) 504 { 505 struct pci_devinfo *dinfo = device_get_ivars(child); 506 pcicfgregs *cfg = &dinfo->cfg; 507 u_int16_t status; 508 int result; 509 510 if (cfg->pp_cap != 0) { 511 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2); 512 switch (status & PCIM_PSTAT_DMASK) { 513 case PCIM_PSTAT_D0: 514 result = PCI_POWERSTATE_D0; 515 break; 516 case PCIM_PSTAT_D1: 517 result = PCI_POWERSTATE_D1; 518 break; 519 case PCIM_PSTAT_D2: 520 result = PCI_POWERSTATE_D2; 521 break; 522 case PCIM_PSTAT_D3: 523 result = PCI_POWERSTATE_D3; 524 break; 525 default: 526 result = PCI_POWERSTATE_UNKNOWN; 527 break; 528 } 529 } else { 530 /* No support, device is always at D0 */ 531 result = PCI_POWERSTATE_D0; 532 } 533 return(result); 534 } 535 536 /* 537 * Some convenience functions for PCI device drivers. 538 */ 539 540 static __inline void 541 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit) 542 { 543 u_int16_t command; 544 545 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 546 command |= bit; 547 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 548 } 549 550 static __inline void 551 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit) 552 { 553 u_int16_t command; 554 555 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 556 command &= ~bit; 557 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 558 } 559 560 void 561 pci_enable_busmaster_method(device_t dev, device_t child) 562 { 563 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 564 } 565 566 void 567 pci_disable_busmaster_method(device_t dev, device_t child) 568 { 569 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 570 } 571 572 void 573 pci_enable_io_method(device_t dev, device_t child, int space) 574 { 575 switch(space) { 576 case SYS_RES_IOPORT: 577 pci_set_command_bit(dev, child, PCIM_CMD_PORTEN); 578 break; 579 case SYS_RES_MEMORY: 580 pci_set_command_bit(dev, child, PCIM_CMD_MEMEN); 581 break; 582 } 583 } 584 585 void 586 pci_disable_io_method(device_t dev, device_t child, int space) 587 { 588 switch(space) { 589 case SYS_RES_IOPORT: 590 pci_clear_command_bit(dev, child, PCIM_CMD_PORTEN); 591 break; 592 case SYS_RES_MEMORY: 593 pci_clear_command_bit(dev, child, PCIM_CMD_MEMEN); 594 break; 595 } 596 } 597 598 /* 599 * New style pci driver. Parent device is either a pci-host-bridge or a 600 * pci-pci-bridge. Both kinds are represented by instances of pcib. 601 */ 602 603 void 604 pci_print_verbose(struct pci_devinfo *dinfo) 605 { 606 if (bootverbose) { 607 pcicfgregs *cfg = &dinfo->cfg; 608 609 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 610 cfg->vendor, cfg->device, cfg->revid); 611 printf("\tbus=%d, slot=%d, func=%d\n", 612 cfg->bus, cfg->slot, cfg->func); 613 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 614 cfg->baseclass, cfg->subclass, cfg->progif, 615 cfg->hdrtype, cfg->mfdev); 616 #ifdef PCI_DEBUG 617 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 618 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 619 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 620 cfg->lattimer, cfg->lattimer * 30, 621 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 622 #endif /* PCI_DEBUG */ 623 if (cfg->intpin > 0) 624 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 625 if (cfg->pp_cap) { 626 u_int16_t status; 627 628 status = pci_read_config(cfg->dev, cfg->pp_status, 2); 629 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 630 cfg->pp_cap & PCIM_PCAP_SPEC, 631 cfg->pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 632 cfg->pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 633 status & PCIM_PSTAT_DMASK); 634 } 635 } 636 } 637 638 static int 639 pci_porten(device_t pcib, int b, int s, int f) 640 { 641 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 642 & PCIM_CMD_PORTEN) != 0; 643 } 644 645 static int 646 pci_memen(device_t pcib, int b, int s, int f) 647 { 648 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 649 & PCIM_CMD_MEMEN) != 0; 650 } 651 652 /* 653 * Add a resource based on a pci map register. Return 1 if the map 654 * register is a 32bit map register or 2 if it is a 64bit register. 655 */ 656 static int 657 pci_add_map(device_t pcib, int b, int s, int f, int reg, 658 struct resource_list *rl) 659 { 660 u_int32_t map; 661 u_int64_t base; 662 u_int8_t ln2size; 663 u_int8_t ln2range; 664 u_int32_t testval; 665 #ifdef PCI_ENABLE_IO_MODES 666 u_int16_t cmd; 667 #endif 668 int type; 669 670 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 671 672 if (map == 0 || map == 0xffffffff) 673 return 1; /* skip invalid entry */ 674 675 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 676 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 677 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 678 679 base = pci_mapbase(map); 680 if (pci_maptype(map) & PCI_MAPMEM) 681 type = SYS_RES_MEMORY; 682 else 683 type = SYS_RES_IOPORT; 684 ln2size = pci_mapsize(testval); 685 ln2range = pci_maprange(testval); 686 if (ln2range == 64) { 687 /* Read the other half of a 64bit map register */ 688 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 689 } 690 691 if (bootverbose) { 692 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 693 reg, pci_maptype(map), ln2range, 694 (unsigned int) base, ln2size); 695 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 696 printf(", port disabled\n"); 697 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 698 printf(", memory disabled\n"); 699 else 700 printf(", enabled\n"); 701 } 702 703 /* 704 * This code theoretically does the right thing, but has 705 * undesirable side effects in some cases where 706 * peripherals respond oddly to having these bits 707 * enabled. Leave them alone by default. 708 */ 709 #ifdef PCI_ENABLE_IO_MODES 710 /* Turn on resources that have been left off by a lazy BIOS */ 711 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 712 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 713 cmd |= PCIM_CMD_PORTEN; 714 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 715 } 716 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 717 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 718 cmd |= PCIM_CMD_MEMEN; 719 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 720 } 721 #else 722 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 723 return 1; 724 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 725 return 1; 726 #endif 727 728 resource_list_add(rl, type, reg, 729 base, base + (1 << ln2size) - 1, 730 (1 << ln2size)); 731 732 return (ln2range == 64) ? 2 : 1; 733 } 734 735 static void 736 pci_add_resources(device_t pcib, int b, int s, int f, device_t dev) 737 { 738 struct pci_devinfo *dinfo = device_get_ivars(dev); 739 pcicfgregs *cfg = &dinfo->cfg; 740 struct resource_list *rl = &dinfo->resources; 741 struct pci_quirk *q; 742 int i; 743 744 for (i = 0; i < cfg->nummaps;) { 745 i += pci_add_map(pcib, b, s, f, PCIR_MAPS + i*4, rl); 746 } 747 748 for (q = &pci_quirks[0]; q->devid; q++) { 749 if (q->devid == ((cfg->device << 16) | cfg->vendor) 750 && q->type == PCI_QUIRK_MAP_REG) 751 pci_add_map(pcib, b, s, f, q->arg1, rl); 752 } 753 754 if (cfg->intpin > 0 && cfg->intline != 255 755 #ifdef __i386__ 756 && cfg->intline != 0 757 #endif 758 ) { 759 #ifdef __ia64__ 760 /* 761 * Re-route interrupts on ia64 so that we can get the 762 * I/O SAPIC interrupt numbers (the BIOS leaves legacy 763 * PIC interrupt numbers in the intline registers). 764 */ 765 cfg->intline = PCIB_ROUTE_INTERRUPT(pcib, 766 dev, 767 cfg->intpin); 768 #endif 769 resource_list_add(rl, SYS_RES_IRQ, 0, 770 cfg->intline, cfg->intline, 1); 771 } 772 } 773 774 static void 775 pci_add_children(device_t dev, int busno) 776 { 777 device_t pcib = device_get_parent(dev); 778 int maxslots; 779 int s, f; 780 781 maxslots = PCIB_MAXSLOTS(pcib); 782 783 for (s = 0; s <= maxslots; s++) { 784 int pcifunchigh = 0; 785 for (f = 0; f <= pcifunchigh; f++) { 786 struct pci_devinfo *dinfo = pci_read_device(pcib, 787 busno, s, f, sizeof(struct pci_devinfo)); 788 if (dinfo != NULL) { 789 if (dinfo->cfg.mfdev) 790 pcifunchigh = PCI_FUNCMAX; 791 792 dinfo->cfg.dev = device_add_child(dev, NULL, -1); 793 device_set_ivars(dinfo->cfg.dev, dinfo); 794 pci_add_resources(pcib, busno, s, f, 795 dinfo->cfg.dev); 796 pci_print_verbose(dinfo); 797 } 798 } 799 } 800 } 801 802 static int 803 pci_probe(device_t dev) 804 { 805 static int once, busno; 806 caddr_t vendordata, info; 807 808 device_set_desc(dev, "PCI bus"); 809 810 if (bootverbose) 811 device_printf(dev, "physical bus=%d\n", pcib_get_bus(dev)); 812 813 /* 814 * Since there can be multiple independantly numbered PCI 815 * busses on some large alpha systems, we can't use the unit 816 * number to decide what bus we are probing. We ask the parent 817 * pcib what our bus number is. 818 */ 819 busno = pcib_get_bus(dev); 820 if (busno < 0) 821 return ENXIO; 822 pci_add_children(dev, busno); 823 824 if (!once) { 825 make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, "pci"); 826 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 827 info = preload_search_info(vendordata, MODINFO_ADDR); 828 pci_vendordata = *(char **)info; 829 info = preload_search_info(vendordata, MODINFO_SIZE); 830 pci_vendordata_size = *(size_t *)info; 831 /* terminate the database */ 832 pci_vendordata[pci_vendordata_size] = '\n'; 833 } 834 once++; 835 } 836 837 return 0; 838 } 839 840 int 841 pci_print_child(device_t dev, device_t child) 842 { 843 struct pci_devinfo *dinfo; 844 struct resource_list *rl; 845 pcicfgregs *cfg; 846 int retval = 0; 847 848 dinfo = device_get_ivars(child); 849 cfg = &dinfo->cfg; 850 rl = &dinfo->resources; 851 852 retval += bus_print_child_header(dev, child); 853 854 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 855 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 856 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 857 if (device_get_flags(dev)) 858 retval += printf(" flags %#x", device_get_flags(dev)); 859 860 retval += printf(" at device %d.%d", pci_get_slot(child), 861 pci_get_function(child)); 862 863 retval += bus_print_child_footer(dev, child); 864 865 return (retval); 866 } 867 868 static struct 869 { 870 int class; 871 int subclass; 872 char *desc; 873 } pci_nomatch_tab[] = { 874 {PCIC_OLD, -1, "old"}, 875 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 876 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 877 {PCIC_STORAGE, -1, "mass storage"}, 878 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 879 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 880 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 881 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 882 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 883 {PCIC_NETWORK, -1, "network"}, 884 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 885 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 886 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 887 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 888 {PCIC_DISPLAY, -1, "display"}, 889 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 890 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 891 {PCIC_MULTIMEDIA, -1, "multimedia"}, 892 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 893 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 894 {PCIC_MEMORY, -1, "memory"}, 895 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 896 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 897 {PCIC_BRIDGE, -1, "bridge"}, 898 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 899 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 900 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 901 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 902 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 903 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 904 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 905 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 906 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 907 {PCIC_SIMPLECOMM, -1, "simple comms"}, 908 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 909 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 910 {PCIC_BASEPERIPH, -1, "base peripheral"}, 911 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 912 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 913 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 914 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 915 {PCIC_INPUTDEV, -1, "input device"}, 916 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 917 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 918 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 919 {PCIC_DOCKING, -1, "docking station"}, 920 {PCIC_PROCESSOR, -1, "processor"}, 921 {PCIC_SERIALBUS, -1, "serial bus"}, 922 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 923 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 924 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 925 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 926 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 927 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 928 {0, 0, NULL} 929 }; 930 931 void 932 pci_probe_nomatch(device_t dev, device_t child) 933 { 934 int i; 935 char *cp, *scp, *device; 936 937 /* 938 * Look for a listing for this device in a loaded device database. 939 */ 940 if ((device = pci_describe_device(child)) != NULL) { 941 device_printf(dev, "<%s>", device); 942 free(device, M_DEVBUF); 943 } else { 944 /* 945 * Scan the class/subclass descriptions for a general description. 946 */ 947 cp = "unknown"; 948 scp = NULL; 949 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 950 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 951 if (pci_nomatch_tab[i].subclass == -1) { 952 cp = pci_nomatch_tab[i].desc; 953 } else if (pci_nomatch_tab[i].subclass == pci_get_subclass(child)) { 954 scp = pci_nomatch_tab[i].desc; 955 } 956 } 957 } 958 device_printf(dev, "<%s%s%s>", 959 cp ? : "", 960 ((cp != NULL) && (scp != NULL)) ? ", " : "", 961 scp ? : ""); 962 } 963 printf(" at device %d.%d (no driver attached)\n", 964 pci_get_slot(child), 965 pci_get_function(child)); 966 return; 967 } 968 969 /* 970 * Parse the PCI device database, if loaded, and return a pointer to a 971 * description of the device. 972 * 973 * The database is flat text formatted as follows: 974 * 975 * Any line not in a valid format is ignored. 976 * Lines are terminated with newline '\n' characters. 977 * 978 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 979 * the vendor name. 980 * 981 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 982 * - devices cannot be listed without a corresponding VENDOR line. 983 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 984 * another TAB, then the device name. 985 */ 986 987 /* 988 * Assuming (ptr) points to the beginning of a line in the database, 989 * return the vendor or device and description of the next entry. 990 * The value of (vendor) or (device) inappropriate for the entry type 991 * is set to -1. Returns nonzero at the end of the database. 992 * 993 * Note that this is slightly unrobust in the face of corrupt data; 994 * we attempt to safeguard against this by spamming the end of the 995 * database with a newline when we initialise. 996 */ 997 static int 998 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 999 { 1000 char *cp = *ptr; 1001 int left; 1002 1003 *device = -1; 1004 *vendor = -1; 1005 **desc = '\0'; 1006 for (;;) { 1007 left = pci_vendordata_size - (cp - pci_vendordata); 1008 if (left <= 0) { 1009 *ptr = cp; 1010 return(1); 1011 } 1012 1013 /* vendor entry? */ 1014 if (*cp != '\t' && sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1015 break; 1016 /* device entry? */ 1017 if (*cp == '\t' && sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1018 break; 1019 1020 /* skip to next line */ 1021 while (*cp != '\n' && left > 0) { 1022 cp++; 1023 left--; 1024 } 1025 if (*cp == '\n') { 1026 cp++; 1027 left--; 1028 } 1029 } 1030 /* skip to next line */ 1031 while (*cp != '\n' && left > 0) { 1032 cp++; 1033 left--; 1034 } 1035 if (*cp == '\n' && left > 0) 1036 cp++; 1037 *ptr = cp; 1038 return(0); 1039 } 1040 1041 static char * 1042 pci_describe_device(device_t dev) 1043 { 1044 int vendor, device; 1045 char *desc, *vp, *dp, *line; 1046 1047 desc = vp = dp = NULL; 1048 1049 /* 1050 * If we have no vendor data, we can't do anything. 1051 */ 1052 if (pci_vendordata == NULL) 1053 goto out; 1054 1055 /* 1056 * Scan the vendor data looking for this device 1057 */ 1058 line = pci_vendordata; 1059 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1060 goto out; 1061 for (;;) { 1062 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1063 goto out; 1064 if (vendor == pci_get_vendor(dev)) 1065 break; 1066 } 1067 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1068 goto out; 1069 for (;;) { 1070 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1071 *dp = 0; 1072 break; 1073 } 1074 if (vendor != -1) { 1075 *dp = 0; 1076 break; 1077 } 1078 if (device == pci_get_device(dev)) 1079 break; 1080 } 1081 if (dp[0] == '\0') 1082 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1083 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != NULL) 1084 sprintf(desc, "%s, %s", vp, dp); 1085 out: 1086 if (vp != NULL) 1087 free(vp, M_DEVBUF); 1088 if (dp != NULL) 1089 free(dp, M_DEVBUF); 1090 return(desc); 1091 } 1092 1093 int 1094 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1095 { 1096 struct pci_devinfo *dinfo; 1097 pcicfgregs *cfg; 1098 1099 dinfo = device_get_ivars(child); 1100 cfg = &dinfo->cfg; 1101 1102 switch (which) { 1103 case PCI_IVAR_SUBVENDOR: 1104 *result = cfg->subvendor; 1105 break; 1106 case PCI_IVAR_SUBDEVICE: 1107 *result = cfg->subdevice; 1108 break; 1109 case PCI_IVAR_VENDOR: 1110 *result = cfg->vendor; 1111 break; 1112 case PCI_IVAR_DEVICE: 1113 *result = cfg->device; 1114 break; 1115 case PCI_IVAR_DEVID: 1116 *result = (cfg->device << 16) | cfg->vendor; 1117 break; 1118 case PCI_IVAR_CLASS: 1119 *result = cfg->baseclass; 1120 break; 1121 case PCI_IVAR_SUBCLASS: 1122 *result = cfg->subclass; 1123 break; 1124 case PCI_IVAR_PROGIF: 1125 *result = cfg->progif; 1126 break; 1127 case PCI_IVAR_REVID: 1128 *result = cfg->revid; 1129 break; 1130 case PCI_IVAR_INTPIN: 1131 *result = cfg->intpin; 1132 break; 1133 case PCI_IVAR_IRQ: 1134 *result = cfg->intline; 1135 break; 1136 case PCI_IVAR_BUS: 1137 *result = cfg->bus; 1138 break; 1139 case PCI_IVAR_SLOT: 1140 *result = cfg->slot; 1141 break; 1142 case PCI_IVAR_FUNCTION: 1143 *result = cfg->func; 1144 break; 1145 default: 1146 return ENOENT; 1147 } 1148 return 0; 1149 } 1150 1151 int 1152 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1153 { 1154 struct pci_devinfo *dinfo; 1155 pcicfgregs *cfg; 1156 1157 dinfo = device_get_ivars(child); 1158 cfg = &dinfo->cfg; 1159 1160 switch (which) { 1161 case PCI_IVAR_SUBVENDOR: 1162 case PCI_IVAR_SUBDEVICE: 1163 case PCI_IVAR_VENDOR: 1164 case PCI_IVAR_DEVICE: 1165 case PCI_IVAR_DEVID: 1166 case PCI_IVAR_CLASS: 1167 case PCI_IVAR_SUBCLASS: 1168 case PCI_IVAR_PROGIF: 1169 case PCI_IVAR_REVID: 1170 case PCI_IVAR_INTPIN: 1171 case PCI_IVAR_IRQ: 1172 case PCI_IVAR_BUS: 1173 case PCI_IVAR_SLOT: 1174 case PCI_IVAR_FUNCTION: 1175 return EINVAL; /* disallow for now */ 1176 1177 default: 1178 return ENOENT; 1179 } 1180 return 0; 1181 } 1182 1183 struct resource * 1184 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1185 u_long start, u_long end, u_long count, u_int flags) 1186 { 1187 struct pci_devinfo *dinfo = device_get_ivars(child); 1188 struct resource_list *rl = &dinfo->resources; 1189 pcicfgregs *cfg = &dinfo->cfg; 1190 1191 /* 1192 * Perform lazy resource allocation 1193 * 1194 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY 1195 */ 1196 if (device_get_parent(child) == dev) { 1197 /* 1198 * If device doesn't have an interrupt routed, and is deserving of 1199 * an interrupt, try to assign it one. 1200 */ 1201 if ((type == SYS_RES_IRQ) && (cfg->intline == 255 || cfg->intline == 0) && (cfg->intpin != 0)) { 1202 cfg->intline = PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1203 cfg->intpin); 1204 if (cfg->intline != 255) { 1205 pci_write_config(child, PCIR_INTLINE, cfg->intline, 1); 1206 resource_list_add(rl, SYS_RES_IRQ, 0, 1207 cfg->intline, cfg->intline, 1); 1208 } 1209 } 1210 } 1211 1212 return resource_list_alloc(rl, dev, child, type, rid, 1213 start, end, count, flags); 1214 } 1215 1216 void 1217 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1218 { 1219 struct pci_devinfo *dinfo; 1220 struct resource_list *rl; 1221 struct resource_list_entry *rle; 1222 1223 if (device_get_parent(child) != dev) 1224 return; 1225 1226 dinfo = device_get_ivars(child); 1227 rl = &dinfo->resources; 1228 rle = resource_list_find(rl, type, rid); 1229 if (rle) { 1230 if (rle->res) { 1231 if (rle->res->r_dev != dev || 1232 rman_get_flags(rle->res) & RF_ACTIVE) { 1233 device_printf(dev, "delete_resource: " 1234 "Resource still owned by child, oops. " 1235 "(type=%d, rid=%d, addr=%lx)\n", 1236 rle->type, rle->rid, 1237 rman_get_start(rle->res)); 1238 return; 1239 } 1240 bus_release_resource(dev, type, rid, rle->res); 1241 } 1242 resource_list_delete(rl, type, rid); 1243 } 1244 /* I don't understand the next line */ 1245 pci_write_config(child, rid, 0, 4); 1246 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1247 } 1248 1249 struct resource_list * 1250 pci_get_resource_list (device_t dev, device_t child) 1251 { 1252 struct pci_devinfo * dinfo = device_get_ivars(child); 1253 struct resource_list * rl = &dinfo->resources; 1254 1255 if (!rl) 1256 return (NULL); 1257 1258 return (rl); 1259 } 1260 1261 u_int32_t 1262 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1263 { 1264 struct pci_devinfo *dinfo = device_get_ivars(child); 1265 pcicfgregs *cfg = &dinfo->cfg; 1266 1267 return PCIB_READ_CONFIG(device_get_parent(dev), 1268 cfg->bus, cfg->slot, cfg->func, 1269 reg, width); 1270 } 1271 1272 void 1273 pci_write_config_method(device_t dev, device_t child, int reg, 1274 u_int32_t val, int width) 1275 { 1276 struct pci_devinfo *dinfo = device_get_ivars(child); 1277 pcicfgregs *cfg = &dinfo->cfg; 1278 1279 PCIB_WRITE_CONFIG(device_get_parent(dev), 1280 cfg->bus, cfg->slot, cfg->func, 1281 reg, val, width); 1282 } 1283 1284 static int 1285 pci_modevent(module_t mod, int what, void *arg) 1286 { 1287 switch (what) { 1288 case MOD_LOAD: 1289 STAILQ_INIT(&pci_devq); 1290 pci_generation = 0; 1291 break; 1292 1293 case MOD_UNLOAD: 1294 break; 1295 } 1296 1297 return 0; 1298 } 1299