1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/linker.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/sysctl.h> 44 #include <sys/types.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 55 #include <sys/pciio.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pci_private.h> 59 60 #include "pcib_if.h" 61 #include "pci_if.h" 62 63 #if (defined(__i386__) && !defined(PC98)) || defined(__amd64__) || \ 64 defined (__ia64__) 65 #include <contrib/dev/acpica/acpi.h> 66 #include "acpi_if.h" 67 #else 68 #define ACPI_PWR_FOR_SLEEP(x, y, z) 69 #endif 70 71 static uint32_t pci_mapbase(unsigned mapreg); 72 static int pci_maptype(unsigned mapreg); 73 static int pci_mapsize(unsigned testval); 74 static int pci_maprange(unsigned mapreg); 75 static void pci_fixancient(pcicfgregs *cfg); 76 77 static int pci_porten(device_t pcib, int b, int s, int f); 78 static int pci_memen(device_t pcib, int b, int s, int f); 79 static void pci_assign_interrupt(device_t bus, device_t dev, 80 int force_route); 81 static int pci_add_map(device_t pcib, device_t bus, device_t dev, 82 int b, int s, int f, int reg, 83 struct resource_list *rl); 84 static void pci_add_resources(device_t pcib, device_t bus, 85 device_t dev); 86 static int pci_probe(device_t dev); 87 static int pci_attach(device_t dev); 88 static void pci_load_vendor_data(void); 89 static int pci_describe_parse_line(char **ptr, int *vendor, 90 int *device, char **desc); 91 static char *pci_describe_device(device_t dev); 92 static int pci_modevent(module_t mod, int what, void *arg); 93 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 94 pcicfgregs *cfg); 95 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 96 97 static device_method_t pci_methods[] = { 98 /* Device interface */ 99 DEVMETHOD(device_probe, pci_probe), 100 DEVMETHOD(device_attach, pci_attach), 101 DEVMETHOD(device_detach, bus_generic_detach), 102 DEVMETHOD(device_shutdown, bus_generic_shutdown), 103 DEVMETHOD(device_suspend, pci_suspend), 104 DEVMETHOD(device_resume, pci_resume), 105 106 /* Bus interface */ 107 DEVMETHOD(bus_print_child, pci_print_child), 108 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 109 DEVMETHOD(bus_read_ivar, pci_read_ivar), 110 DEVMETHOD(bus_write_ivar, pci_write_ivar), 111 DEVMETHOD(bus_driver_added, pci_driver_added), 112 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 113 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 114 115 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 116 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 117 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 118 DEVMETHOD(bus_delete_resource, pci_delete_resource), 119 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 120 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 121 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 122 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 123 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 124 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 125 126 /* PCI interface */ 127 DEVMETHOD(pci_read_config, pci_read_config_method), 128 DEVMETHOD(pci_write_config, pci_write_config_method), 129 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 130 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 131 DEVMETHOD(pci_enable_io, pci_enable_io_method), 132 DEVMETHOD(pci_disable_io, pci_disable_io_method), 133 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 134 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 135 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 136 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 137 138 { 0, 0 } 139 }; 140 141 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 142 143 devclass_t pci_devclass; 144 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 145 MODULE_VERSION(pci, 1); 146 147 static char *pci_vendordata; 148 static size_t pci_vendordata_size; 149 150 151 struct pci_quirk { 152 uint32_t devid; /* Vendor/device of the card */ 153 int type; 154 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 155 int arg1; 156 int arg2; 157 }; 158 159 struct pci_quirk pci_quirks[] = { 160 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 161 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 162 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 163 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 164 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 165 166 { 0 } 167 }; 168 169 /* map register information */ 170 #define PCI_MAPMEM 0x01 /* memory map */ 171 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 172 #define PCI_MAPPORT 0x04 /* port map */ 173 174 struct devlist pci_devq; 175 uint32_t pci_generation; 176 uint32_t pci_numdevs = 0; 177 178 /* sysctl vars */ 179 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 180 181 static int pci_enable_io_modes = 1; 182 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 183 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 184 &pci_enable_io_modes, 1, 185 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 186 enable these bits correctly. We'd like to do this all the time, but there\n\ 187 are some peripherals that this causes problems with."); 188 189 static int pci_do_power_nodriver = 0; 190 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver); 191 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW, 192 &pci_do_power_nodriver, 0, 193 "Place a function into D3 state when no driver attaches to it. 0 means\n\ 194 disable. 1 means conservatively place devices into D3 state. 2 means\n\ 195 agressively place devices into D3 state. 3 means put absolutely everything\n\ 196 in D3 state."); 197 198 static int pci_do_power_resume = 1; 199 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume); 200 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW, 201 &pci_do_power_resume, 1, 202 "Transition from D3 -> D0 on resume."); 203 204 /* Find a device_t by bus/slot/function */ 205 206 device_t 207 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 208 { 209 struct pci_devinfo *dinfo; 210 211 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 212 if ((dinfo->cfg.bus == bus) && 213 (dinfo->cfg.slot == slot) && 214 (dinfo->cfg.func == func)) { 215 return (dinfo->cfg.dev); 216 } 217 } 218 219 return (NULL); 220 } 221 222 /* Find a device_t by vendor/device ID */ 223 224 device_t 225 pci_find_device(uint16_t vendor, uint16_t device) 226 { 227 struct pci_devinfo *dinfo; 228 229 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 230 if ((dinfo->cfg.vendor == vendor) && 231 (dinfo->cfg.device == device)) { 232 return (dinfo->cfg.dev); 233 } 234 } 235 236 return (NULL); 237 } 238 239 /* return base address of memory or port map */ 240 241 static uint32_t 242 pci_mapbase(unsigned mapreg) 243 { 244 int mask = 0x03; 245 if ((mapreg & 0x01) == 0) 246 mask = 0x0f; 247 return (mapreg & ~mask); 248 } 249 250 /* return map type of memory or port map */ 251 252 static int 253 pci_maptype(unsigned mapreg) 254 { 255 static uint8_t maptype[0x10] = { 256 PCI_MAPMEM, PCI_MAPPORT, 257 PCI_MAPMEM, 0, 258 PCI_MAPMEM, PCI_MAPPORT, 259 0, 0, 260 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 261 PCI_MAPMEM|PCI_MAPMEMP, 0, 262 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 263 0, 0, 264 }; 265 266 return maptype[mapreg & 0x0f]; 267 } 268 269 /* return log2 of map size decoded for memory or port map */ 270 271 static int 272 pci_mapsize(unsigned testval) 273 { 274 int ln2size; 275 276 testval = pci_mapbase(testval); 277 ln2size = 0; 278 if (testval != 0) { 279 while ((testval & 1) == 0) 280 { 281 ln2size++; 282 testval >>= 1; 283 } 284 } 285 return (ln2size); 286 } 287 288 /* return log2 of address range supported by map register */ 289 290 static int 291 pci_maprange(unsigned mapreg) 292 { 293 int ln2range = 0; 294 switch (mapreg & 0x07) { 295 case 0x00: 296 case 0x01: 297 case 0x05: 298 ln2range = 32; 299 break; 300 case 0x02: 301 ln2range = 20; 302 break; 303 case 0x04: 304 ln2range = 64; 305 break; 306 } 307 return (ln2range); 308 } 309 310 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 311 312 static void 313 pci_fixancient(pcicfgregs *cfg) 314 { 315 if (cfg->hdrtype != 0) 316 return; 317 318 /* PCI to PCI bridges use header type 1 */ 319 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 320 cfg->hdrtype = 1; 321 } 322 323 /* extract header type specific config data */ 324 325 static void 326 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 327 { 328 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 329 switch (cfg->hdrtype) { 330 case 0: 331 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 332 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 333 cfg->nummaps = PCI_MAXMAPS_0; 334 break; 335 case 1: 336 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 337 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 338 cfg->nummaps = PCI_MAXMAPS_1; 339 break; 340 case 2: 341 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 342 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 343 cfg->nummaps = PCI_MAXMAPS_2; 344 break; 345 } 346 #undef REG 347 } 348 349 /* read configuration header into pcicfgregs structure */ 350 351 struct pci_devinfo * 352 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 353 { 354 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 355 pcicfgregs *cfg = NULL; 356 struct pci_devinfo *devlist_entry; 357 struct devlist *devlist_head; 358 359 devlist_head = &pci_devq; 360 361 devlist_entry = NULL; 362 363 if (REG(PCIR_DEVVENDOR, 4) != -1) { 364 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 365 if (devlist_entry == NULL) 366 return (NULL); 367 368 cfg = &devlist_entry->cfg; 369 370 cfg->bus = b; 371 cfg->slot = s; 372 cfg->func = f; 373 cfg->vendor = REG(PCIR_VENDOR, 2); 374 cfg->device = REG(PCIR_DEVICE, 2); 375 cfg->cmdreg = REG(PCIR_COMMAND, 2); 376 cfg->statreg = REG(PCIR_STATUS, 2); 377 cfg->baseclass = REG(PCIR_CLASS, 1); 378 cfg->subclass = REG(PCIR_SUBCLASS, 1); 379 cfg->progif = REG(PCIR_PROGIF, 1); 380 cfg->revid = REG(PCIR_REVID, 1); 381 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 382 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 383 cfg->lattimer = REG(PCIR_LATTIMER, 1); 384 cfg->intpin = REG(PCIR_INTPIN, 1); 385 cfg->intline = REG(PCIR_INTLINE, 1); 386 387 cfg->mingnt = REG(PCIR_MINGNT, 1); 388 cfg->maxlat = REG(PCIR_MAXLAT, 1); 389 390 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 391 cfg->hdrtype &= ~PCIM_MFDEV; 392 393 pci_fixancient(cfg); 394 pci_hdrtypedata(pcib, b, s, f, cfg); 395 396 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 397 pci_read_extcap(pcib, cfg); 398 399 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 400 401 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 402 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 403 devlist_entry->conf.pc_sel.pc_func = cfg->func; 404 devlist_entry->conf.pc_hdr = cfg->hdrtype; 405 406 devlist_entry->conf.pc_subvendor = cfg->subvendor; 407 devlist_entry->conf.pc_subdevice = cfg->subdevice; 408 devlist_entry->conf.pc_vendor = cfg->vendor; 409 devlist_entry->conf.pc_device = cfg->device; 410 411 devlist_entry->conf.pc_class = cfg->baseclass; 412 devlist_entry->conf.pc_subclass = cfg->subclass; 413 devlist_entry->conf.pc_progif = cfg->progif; 414 devlist_entry->conf.pc_revid = cfg->revid; 415 416 pci_numdevs++; 417 pci_generation++; 418 } 419 return (devlist_entry); 420 #undef REG 421 } 422 423 static void 424 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 425 { 426 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 427 int ptr, nextptr, ptrptr; 428 429 switch (cfg->hdrtype & PCIM_HDRTYPE) { 430 case 0: 431 ptrptr = PCIR_CAP_PTR; 432 break; 433 case 2: 434 ptrptr = PCIR_CAP_PTR_2; 435 break; 436 default: 437 return; /* no extended capabilities support */ 438 } 439 nextptr = REG(ptrptr, 1); /* sanity check? */ 440 441 /* 442 * Read capability entries. 443 */ 444 while (nextptr != 0) { 445 /* Sanity check */ 446 if (nextptr > 255) { 447 printf("illegal PCI extended capability offset %d\n", 448 nextptr); 449 return; 450 } 451 /* Find the next entry */ 452 ptr = nextptr; 453 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 454 455 /* Process this entry */ 456 switch (REG(ptr + PCICAP_ID, 1)) { 457 case PCIY_PMG: /* PCI power management */ 458 if (cfg->pp.pp_cap == 0) { 459 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 460 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 461 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 462 if ((nextptr - ptr) > PCIR_POWER_DATA) 463 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 464 } 465 break; 466 case PCIY_MSI: /* PCI MSI */ 467 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 468 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 469 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 470 else 471 cfg->msi.msi_data = PCIR_MSI_DATA; 472 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 473 PCIM_MSICTRL_MMC_MASK)>>1); 474 default: 475 break; 476 } 477 } 478 #undef REG 479 } 480 481 /* 482 * Return the offset in configuration space of the requested extended 483 * capability entry or 0 if the specified capability was not found. 484 */ 485 int 486 pci_find_extcap_method(device_t dev, device_t child, int capability, 487 int *capreg) 488 { 489 struct pci_devinfo *dinfo = device_get_ivars(child); 490 pcicfgregs *cfg = &dinfo->cfg; 491 u_int32_t status; 492 u_int8_t ptr; 493 494 /* 495 * Check the CAP_LIST bit of the PCI status register first. 496 */ 497 status = pci_read_config(child, PCIR_STATUS, 2); 498 if (!(status & PCIM_STATUS_CAPPRESENT)) 499 return (ENXIO); 500 501 /* 502 * Determine the start pointer of the capabilities list. 503 */ 504 switch (cfg->hdrtype & PCIM_HDRTYPE) { 505 case 0: 506 ptr = PCIR_CAP_PTR; 507 break; 508 case 2: 509 ptr = PCIR_CAP_PTR_2; 510 break; 511 default: 512 /* XXX: panic? */ 513 return (ENXIO); /* no extended capabilities support */ 514 } 515 ptr = pci_read_config(child, ptr, 1); 516 517 /* 518 * Traverse the capabilities list. 519 */ 520 while (ptr != 0) { 521 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 522 if (capreg != NULL) 523 *capreg = ptr; 524 return (0); 525 } 526 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 527 } 528 529 return (ENOENT); 530 } 531 532 /* free pcicfgregs structure and all depending data structures */ 533 534 int 535 pci_freecfg(struct pci_devinfo *dinfo) 536 { 537 struct devlist *devlist_head; 538 539 devlist_head = &pci_devq; 540 541 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 542 free(dinfo, M_DEVBUF); 543 544 /* increment the generation count */ 545 pci_generation++; 546 547 /* we're losing one device */ 548 pci_numdevs--; 549 return (0); 550 } 551 552 /* 553 * PCI power manangement 554 */ 555 int 556 pci_set_powerstate_method(device_t dev, device_t child, int state) 557 { 558 struct pci_devinfo *dinfo = device_get_ivars(child); 559 pcicfgregs *cfg = &dinfo->cfg; 560 uint16_t status; 561 int result, oldstate, highest, delay; 562 563 if (cfg->pp.pp_cap == 0) 564 return (EOPNOTSUPP); 565 566 /* 567 * Optimize a no state change request away. While it would be OK to 568 * write to the hardware in theory, some devices have shown odd 569 * behavior when going from D3 -> D3. 570 */ 571 oldstate = pci_get_powerstate(child); 572 if (oldstate == state) 573 return (0); 574 575 /* 576 * The PCI power management specification states that after a state 577 * transition between PCI power states, system software must 578 * guarantee a minimal delay before the function accesses the device. 579 * Compute the worst case delay that we need to guarantee before we 580 * access the device. Many devices will be responsive much more 581 * quickly than this delay, but there are some that don't respond 582 * instantly to state changes. Transitions to/from D3 state require 583 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 584 * is done below with DELAY rather than a sleeper function because 585 * this function can be called from contexts where we cannot sleep. 586 */ 587 highest = (oldstate > state) ? oldstate : state; 588 if (highest == PCI_POWERSTATE_D3) 589 delay = 10000; 590 else if (highest == PCI_POWERSTATE_D2) 591 delay = 200; 592 else 593 delay = 0; 594 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 595 & ~PCIM_PSTAT_DMASK; 596 result = 0; 597 switch (state) { 598 case PCI_POWERSTATE_D0: 599 status |= PCIM_PSTAT_D0; 600 break; 601 case PCI_POWERSTATE_D1: 602 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 603 return (EOPNOTSUPP); 604 status |= PCIM_PSTAT_D1; 605 break; 606 case PCI_POWERSTATE_D2: 607 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 608 return (EOPNOTSUPP); 609 status |= PCIM_PSTAT_D2; 610 break; 611 case PCI_POWERSTATE_D3: 612 status |= PCIM_PSTAT_D3; 613 break; 614 default: 615 return (EINVAL); 616 } 617 618 if (bootverbose) 619 printf( 620 "pci%d:%d:%d: Transition from D%d to D%d\n", 621 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 622 oldstate, state); 623 624 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 625 if (delay) 626 DELAY(delay); 627 return (0); 628 } 629 630 int 631 pci_get_powerstate_method(device_t dev, device_t child) 632 { 633 struct pci_devinfo *dinfo = device_get_ivars(child); 634 pcicfgregs *cfg = &dinfo->cfg; 635 uint16_t status; 636 int result; 637 638 if (cfg->pp.pp_cap != 0) { 639 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 640 switch (status & PCIM_PSTAT_DMASK) { 641 case PCIM_PSTAT_D0: 642 result = PCI_POWERSTATE_D0; 643 break; 644 case PCIM_PSTAT_D1: 645 result = PCI_POWERSTATE_D1; 646 break; 647 case PCIM_PSTAT_D2: 648 result = PCI_POWERSTATE_D2; 649 break; 650 case PCIM_PSTAT_D3: 651 result = PCI_POWERSTATE_D3; 652 break; 653 default: 654 result = PCI_POWERSTATE_UNKNOWN; 655 break; 656 } 657 } else { 658 /* No support, device is always at D0 */ 659 result = PCI_POWERSTATE_D0; 660 } 661 return (result); 662 } 663 664 /* 665 * Some convenience functions for PCI device drivers. 666 */ 667 668 static __inline void 669 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 670 { 671 uint16_t command; 672 673 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 674 command |= bit; 675 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 676 } 677 678 static __inline void 679 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 680 { 681 uint16_t command; 682 683 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 684 command &= ~bit; 685 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 686 } 687 688 int 689 pci_enable_busmaster_method(device_t dev, device_t child) 690 { 691 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 692 return (0); 693 } 694 695 int 696 pci_disable_busmaster_method(device_t dev, device_t child) 697 { 698 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 699 return (0); 700 } 701 702 int 703 pci_enable_io_method(device_t dev, device_t child, int space) 704 { 705 uint16_t command; 706 uint16_t bit; 707 char *error; 708 709 bit = 0; 710 error = NULL; 711 712 switch(space) { 713 case SYS_RES_IOPORT: 714 bit = PCIM_CMD_PORTEN; 715 error = "port"; 716 break; 717 case SYS_RES_MEMORY: 718 bit = PCIM_CMD_MEMEN; 719 error = "memory"; 720 break; 721 default: 722 return (EINVAL); 723 } 724 pci_set_command_bit(dev, child, bit); 725 /* Some devices seem to need a brief stall here, what do to? */ 726 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 727 if (command & bit) 728 return (0); 729 device_printf(child, "failed to enable %s mapping!\n", error); 730 return (ENXIO); 731 } 732 733 int 734 pci_disable_io_method(device_t dev, device_t child, int space) 735 { 736 uint16_t command; 737 uint16_t bit; 738 char *error; 739 740 bit = 0; 741 error = NULL; 742 743 switch(space) { 744 case SYS_RES_IOPORT: 745 bit = PCIM_CMD_PORTEN; 746 error = "port"; 747 break; 748 case SYS_RES_MEMORY: 749 bit = PCIM_CMD_MEMEN; 750 error = "memory"; 751 break; 752 default: 753 return (EINVAL); 754 } 755 pci_clear_command_bit(dev, child, bit); 756 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 757 if (command & bit) { 758 device_printf(child, "failed to disable %s mapping!\n", error); 759 return (ENXIO); 760 } 761 return (0); 762 } 763 764 /* 765 * New style pci driver. Parent device is either a pci-host-bridge or a 766 * pci-pci-bridge. Both kinds are represented by instances of pcib. 767 */ 768 769 void 770 pci_print_verbose(struct pci_devinfo *dinfo) 771 { 772 if (bootverbose) { 773 pcicfgregs *cfg = &dinfo->cfg; 774 775 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 776 cfg->vendor, cfg->device, cfg->revid); 777 printf("\tbus=%d, slot=%d, func=%d\n", 778 cfg->bus, cfg->slot, cfg->func); 779 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 780 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 781 cfg->mfdev); 782 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 783 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 784 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 785 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 786 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 787 if (cfg->intpin > 0) 788 printf("\tintpin=%c, irq=%d\n", 789 cfg->intpin +'a' -1, cfg->intline); 790 if (cfg->pp.pp_cap) { 791 uint16_t status; 792 793 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 794 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 795 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 796 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 797 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 798 status & PCIM_PSTAT_DMASK); 799 } 800 if (cfg->msi.msi_data) { 801 int ctrl; 802 803 ctrl = cfg->msi.msi_ctrl; 804 printf("\tMSI supports %d message%s%s%s\n", 805 cfg->msi.msi_msgnum, 806 (cfg->msi.msi_msgnum == 1) ? "" : "s", 807 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 808 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 809 } 810 } 811 } 812 813 static int 814 pci_porten(device_t pcib, int b, int s, int f) 815 { 816 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 817 & PCIM_CMD_PORTEN) != 0; 818 } 819 820 static int 821 pci_memen(device_t pcib, int b, int s, int f) 822 { 823 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 824 & PCIM_CMD_MEMEN) != 0; 825 } 826 827 /* 828 * Add a resource based on a pci map register. Return 1 if the map 829 * register is a 32bit map register or 2 if it is a 64bit register. 830 */ 831 static int 832 pci_add_map(device_t pcib, device_t bus, device_t dev, 833 int b, int s, int f, int reg, struct resource_list *rl) 834 { 835 uint32_t map; 836 uint64_t base; 837 uint64_t start, end, count; 838 uint8_t ln2size; 839 uint8_t ln2range; 840 uint32_t testval; 841 uint16_t cmd; 842 int type; 843 int barlen; 844 845 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 846 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 847 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 848 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 849 850 if (pci_maptype(map) & PCI_MAPMEM) 851 type = SYS_RES_MEMORY; 852 else 853 type = SYS_RES_IOPORT; 854 ln2size = pci_mapsize(testval); 855 ln2range = pci_maprange(testval); 856 base = pci_mapbase(map); 857 barlen = ln2range == 64 ? 2 : 1; 858 859 /* 860 * For I/O registers, if bottom bit is set, and the next bit up 861 * isn't clear, we know we have a BAR that doesn't conform to the 862 * spec, so ignore it. Also, sanity check the size of the data 863 * areas to the type of memory involved. Memory must be at least 864 * 32 bytes in size, while I/O ranges must be at least 4. 865 */ 866 if ((testval & 0x1) == 0x1 && 867 (testval & 0x2) != 0) 868 return (barlen); 869 if ((type == SYS_RES_MEMORY && ln2size < 5) || 870 (type == SYS_RES_IOPORT && ln2size < 2)) 871 return (barlen); 872 873 if (ln2range == 64) 874 /* Read the other half of a 64bit map register */ 875 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 876 877 if (bootverbose) { 878 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 879 reg, pci_maptype(map), ln2range, 880 (unsigned int) base, ln2size); 881 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 882 printf(", port disabled\n"); 883 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 884 printf(", memory disabled\n"); 885 else 886 printf(", enabled\n"); 887 } 888 889 /* 890 * If base is 0, then we have problems. It is best to ignore 891 * such entries for the moment. These will be allocated later if 892 * the driver specifically requests them. 893 * 894 * Similarly treat maps whose values is the same as the test value 895 * read back. These maps have had all f's written to them by the 896 * BIOS in an attempt to disable the resources. 897 */ 898 if (base == 0 || map == testval) 899 return (barlen); 900 901 /* 902 * This code theoretically does the right thing, but has 903 * undesirable side effects in some cases where peripherals 904 * respond oddly to having these bits enabled. Let the user 905 * be able to turn them off (since pci_enable_io_modes is 1 by 906 * default). 907 */ 908 if (pci_enable_io_modes) { 909 /* Turn on resources that have been left off by a lazy BIOS */ 910 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 911 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 912 cmd |= PCIM_CMD_PORTEN; 913 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 914 } 915 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 916 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 917 cmd |= PCIM_CMD_MEMEN; 918 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 919 } 920 } else { 921 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 922 return (barlen); 923 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 924 return (barlen); 925 } 926 927 start = base; 928 end = base + (1 << ln2size) - 1; 929 count = 1 << ln2size; 930 resource_list_add(rl, type, reg, start, end, count); 931 932 /* 933 * Not quite sure what to do on failure of allocating the resource 934 * since I can postulate several right answers. 935 */ 936 resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 0); 937 return (barlen); 938 } 939 940 /* 941 * For ATA devices we need to decide early what addressing mode to use. 942 * Legacy demands that the primary and secondary ATA ports sits on the 943 * same addresses that old ISA hardware did. This dictates that we use 944 * those addresses and ignore the BAR's if we cannot set PCI native 945 * addressing mode. 946 */ 947 static void 948 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 949 int s, int f, struct resource_list *rl) 950 { 951 int rid, type, progif; 952 #if 0 953 /* if this device supports PCI native addressing use it */ 954 progif = pci_read_config(dev, PCIR_PROGIF, 1); 955 if ((progif & 0x8a) == 0x8a) { 956 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 957 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 958 printf("Trying ATA native PCI addressing mode\n"); 959 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 960 } 961 } 962 #endif 963 progif = pci_read_config(dev, PCIR_PROGIF, 1); 964 type = SYS_RES_IOPORT; 965 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 966 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl); 967 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl); 968 } else { 969 rid = PCIR_BAR(0); 970 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 971 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,8,0); 972 rid = PCIR_BAR(1); 973 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 974 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,1,0); 975 } 976 if (progif & PCIP_STORAGE_IDE_MODESEC) { 977 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl); 978 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl); 979 } else { 980 rid = PCIR_BAR(2); 981 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 982 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,8,0); 983 rid = PCIR_BAR(3); 984 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 985 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,1,0); 986 } 987 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl); 988 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl); 989 } 990 991 static void 992 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 993 { 994 struct pci_devinfo *dinfo = device_get_ivars(dev); 995 pcicfgregs *cfg = &dinfo->cfg; 996 char tunable_name[64]; 997 int irq; 998 999 /* Has to have an intpin to have an interrupt. */ 1000 if (cfg->intpin == 0) 1001 return; 1002 1003 /* Let the user override the IRQ with a tunable. */ 1004 irq = PCI_INVALID_IRQ; 1005 snprintf(tunable_name, sizeof(tunable_name), "hw.pci%d.%d.INT%c.irq", 1006 cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 1007 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 1008 irq = PCI_INVALID_IRQ; 1009 1010 /* 1011 * If we didn't get an IRQ via the tunable, then we either use the 1012 * IRQ value in the intline register or we ask the bus to route an 1013 * interrupt for us. If force_route is true, then we only use the 1014 * value in the intline register if the bus was unable to assign an 1015 * IRQ. 1016 */ 1017 if (!PCI_INTERRUPT_VALID(irq)) { 1018 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 1019 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 1020 if (!PCI_INTERRUPT_VALID(irq)) 1021 irq = cfg->intline; 1022 } 1023 1024 /* If after all that we don't have an IRQ, just bail. */ 1025 if (!PCI_INTERRUPT_VALID(irq)) 1026 return; 1027 1028 /* Update the config register if it changed. */ 1029 if (irq != cfg->intline) { 1030 cfg->intline = irq; 1031 pci_write_config(dev, PCIR_INTLINE, irq, 1); 1032 } 1033 1034 /* Add this IRQ as rid 0 interrupt resource. */ 1035 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 1036 } 1037 1038 static void 1039 pci_add_resources(device_t pcib, device_t bus, device_t dev) 1040 { 1041 struct pci_devinfo *dinfo = device_get_ivars(dev); 1042 pcicfgregs *cfg = &dinfo->cfg; 1043 struct resource_list *rl = &dinfo->resources; 1044 struct pci_quirk *q; 1045 int b, i, f, s; 1046 1047 b = cfg->bus; 1048 s = cfg->slot; 1049 f = cfg->func; 1050 1051 /* ATA devices needs special map treatment */ 1052 if ((pci_get_class(dev) == PCIC_STORAGE) && 1053 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 1054 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 1055 pci_ata_maps(pcib, bus, dev, b, s, f, rl); 1056 else 1057 for (i = 0; i < cfg->nummaps;) 1058 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 1059 rl); 1060 1061 for (q = &pci_quirks[0]; q->devid; q++) { 1062 if (q->devid == ((cfg->device << 16) | cfg->vendor) 1063 && q->type == PCI_QUIRK_MAP_REG) 1064 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl); 1065 } 1066 1067 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 1068 #if defined(__ia64__) || defined(__i386__) || defined(__amd64__) || \ 1069 defined(__arm__) || defined(__alpha__) 1070 /* 1071 * Try to re-route interrupts. Sometimes the BIOS or 1072 * firmware may leave bogus values in these registers. 1073 * If the re-route fails, then just stick with what we 1074 * have. 1075 */ 1076 pci_assign_interrupt(bus, dev, 1); 1077 #else 1078 pci_assign_interrupt(bus, dev, 0); 1079 #endif 1080 } 1081 } 1082 1083 void 1084 pci_add_children(device_t dev, int busno, size_t dinfo_size) 1085 { 1086 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 1087 device_t pcib = device_get_parent(dev); 1088 struct pci_devinfo *dinfo; 1089 int maxslots; 1090 int s, f, pcifunchigh; 1091 uint8_t hdrtype; 1092 1093 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 1094 ("dinfo_size too small")); 1095 maxslots = PCIB_MAXSLOTS(pcib); 1096 for (s = 0; s <= maxslots; s++) { 1097 pcifunchigh = 0; 1098 f = 0; 1099 DELAY(1); 1100 hdrtype = REG(PCIR_HDRTYPE, 1); 1101 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 1102 continue; 1103 if (hdrtype & PCIM_MFDEV) 1104 pcifunchigh = PCI_FUNCMAX; 1105 for (f = 0; f <= pcifunchigh; f++) { 1106 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 1107 if (dinfo != NULL) { 1108 pci_add_child(dev, dinfo); 1109 } 1110 } 1111 } 1112 #undef REG 1113 } 1114 1115 void 1116 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1117 { 1118 device_t pcib; 1119 1120 pcib = device_get_parent(bus); 1121 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1122 device_set_ivars(dinfo->cfg.dev, dinfo); 1123 resource_list_init(&dinfo->resources); 1124 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 1125 pci_cfg_restore(dinfo->cfg.dev, dinfo); 1126 pci_print_verbose(dinfo); 1127 pci_add_resources(pcib, bus, dinfo->cfg.dev); 1128 } 1129 1130 static int 1131 pci_probe(device_t dev) 1132 { 1133 1134 device_set_desc(dev, "PCI bus"); 1135 1136 /* Allow other subclasses to override this driver. */ 1137 return (-1000); 1138 } 1139 1140 static int 1141 pci_attach(device_t dev) 1142 { 1143 int busno; 1144 1145 /* 1146 * Since there can be multiple independantly numbered PCI 1147 * busses on some large alpha systems, we can't use the unit 1148 * number to decide what bus we are probing. We ask the parent 1149 * pcib what our bus number is. 1150 */ 1151 busno = pcib_get_bus(dev); 1152 if (bootverbose) 1153 device_printf(dev, "physical bus=%d\n", busno); 1154 1155 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1156 1157 return (bus_generic_attach(dev)); 1158 } 1159 1160 int 1161 pci_suspend(device_t dev) 1162 { 1163 int dstate, error, i, numdevs; 1164 device_t acpi_dev, child, *devlist; 1165 struct pci_devinfo *dinfo; 1166 1167 /* 1168 * Save the PCI configuration space for each child and set the 1169 * device in the appropriate power state for this sleep state. 1170 */ 1171 acpi_dev = NULL; 1172 if (pci_do_power_resume) 1173 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1174 device_get_children(dev, &devlist, &numdevs); 1175 for (i = 0; i < numdevs; i++) { 1176 child = devlist[i]; 1177 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1178 pci_cfg_save(child, dinfo, 0); 1179 } 1180 1181 /* Suspend devices before potentially powering them down. */ 1182 error = bus_generic_suspend(dev); 1183 if (error) { 1184 free(devlist, M_TEMP); 1185 return (error); 1186 } 1187 1188 /* 1189 * Always set the device to D3. If ACPI suggests a different 1190 * power state, use it instead. If ACPI is not present, the 1191 * firmware is responsible for managing device power. Skip 1192 * children who aren't attached since they are powered down 1193 * separately. Only manage type 0 devices for now. 1194 */ 1195 for (i = 0; acpi_dev && i < numdevs; i++) { 1196 child = devlist[i]; 1197 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1198 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 1199 dstate = PCI_POWERSTATE_D3; 1200 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 1201 pci_set_powerstate(child, dstate); 1202 } 1203 } 1204 free(devlist, M_TEMP); 1205 return (0); 1206 } 1207 1208 int 1209 pci_resume(device_t dev) 1210 { 1211 int i, numdevs; 1212 device_t acpi_dev, child, *devlist; 1213 struct pci_devinfo *dinfo; 1214 1215 /* 1216 * Set each child to D0 and restore its PCI configuration space. 1217 */ 1218 acpi_dev = NULL; 1219 if (pci_do_power_resume) 1220 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1221 device_get_children(dev, &devlist, &numdevs); 1222 for (i = 0; i < numdevs; i++) { 1223 /* 1224 * Notify ACPI we're going to D0 but ignore the result. If 1225 * ACPI is not present, the firmware is responsible for 1226 * managing device power. Only manage type 0 devices for now. 1227 */ 1228 child = devlist[i]; 1229 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1230 if (acpi_dev && device_is_attached(child) && 1231 dinfo->cfg.hdrtype == 0) { 1232 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 1233 pci_set_powerstate(child, PCI_POWERSTATE_D0); 1234 } 1235 1236 /* Now the device is powered up, restore its config space. */ 1237 pci_cfg_restore(child, dinfo); 1238 } 1239 free(devlist, M_TEMP); 1240 return (bus_generic_resume(dev)); 1241 } 1242 1243 static void 1244 pci_load_vendor_data(void) 1245 { 1246 caddr_t vendordata, info; 1247 1248 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1249 info = preload_search_info(vendordata, MODINFO_ADDR); 1250 pci_vendordata = *(char **)info; 1251 info = preload_search_info(vendordata, MODINFO_SIZE); 1252 pci_vendordata_size = *(size_t *)info; 1253 /* terminate the database */ 1254 pci_vendordata[pci_vendordata_size] = '\n'; 1255 } 1256 } 1257 1258 void 1259 pci_driver_added(device_t dev, driver_t *driver) 1260 { 1261 int numdevs; 1262 device_t *devlist; 1263 device_t child; 1264 struct pci_devinfo *dinfo; 1265 int i; 1266 1267 if (bootverbose) 1268 device_printf(dev, "driver added\n"); 1269 DEVICE_IDENTIFY(driver, dev); 1270 device_get_children(dev, &devlist, &numdevs); 1271 for (i = 0; i < numdevs; i++) { 1272 child = devlist[i]; 1273 if (device_get_state(child) != DS_NOTPRESENT) 1274 continue; 1275 dinfo = device_get_ivars(child); 1276 pci_print_verbose(dinfo); 1277 if (bootverbose) 1278 printf("pci%d:%d:%d: reprobing on driver added\n", 1279 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1280 pci_cfg_restore(child, dinfo); 1281 if (device_probe_and_attach(child) != 0) 1282 pci_cfg_save(child, dinfo, 1); 1283 } 1284 free(devlist, M_TEMP); 1285 } 1286 1287 int 1288 pci_print_child(device_t dev, device_t child) 1289 { 1290 struct pci_devinfo *dinfo; 1291 struct resource_list *rl; 1292 int retval = 0; 1293 1294 dinfo = device_get_ivars(child); 1295 rl = &dinfo->resources; 1296 1297 retval += bus_print_child_header(dev, child); 1298 1299 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1300 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1301 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1302 if (device_get_flags(dev)) 1303 retval += printf(" flags %#x", device_get_flags(dev)); 1304 1305 retval += printf(" at device %d.%d", pci_get_slot(child), 1306 pci_get_function(child)); 1307 1308 retval += bus_print_child_footer(dev, child); 1309 1310 return (retval); 1311 } 1312 1313 static struct 1314 { 1315 int class; 1316 int subclass; 1317 char *desc; 1318 } pci_nomatch_tab[] = { 1319 {PCIC_OLD, -1, "old"}, 1320 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1321 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1322 {PCIC_STORAGE, -1, "mass storage"}, 1323 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1324 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1325 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1326 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1327 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1328 {PCIC_NETWORK, -1, "network"}, 1329 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1330 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1331 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1332 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1333 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"}, 1334 {PCIC_DISPLAY, -1, "display"}, 1335 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1336 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1337 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"}, 1338 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1339 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1340 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1341 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"}, 1342 {PCIC_MEMORY, -1, "memory"}, 1343 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1344 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1345 {PCIC_BRIDGE, -1, "bridge"}, 1346 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1347 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1348 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1349 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1350 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1351 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1352 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1353 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1354 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"}, 1355 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1356 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1357 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1358 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"}, 1359 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"}, 1360 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1361 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1362 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1363 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1364 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1365 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"}, 1366 {PCIC_INPUTDEV, -1, "input device"}, 1367 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1368 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1369 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1370 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"}, 1371 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"}, 1372 {PCIC_DOCKING, -1, "docking station"}, 1373 {PCIC_PROCESSOR, -1, "processor"}, 1374 {PCIC_SERIALBUS, -1, "serial bus"}, 1375 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1376 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1377 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1378 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1379 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1380 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1381 {PCIC_WIRELESS, -1, "wireless controller"}, 1382 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"}, 1383 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"}, 1384 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"}, 1385 {PCIC_INTELLIIO, -1, "intelligent I/O controller"}, 1386 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"}, 1387 {PCIC_SATCOM, -1, "satellite communication"}, 1388 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"}, 1389 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"}, 1390 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"}, 1391 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"}, 1392 {PCIC_CRYPTO, -1, "encrypt/decrypt"}, 1393 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"}, 1394 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "entertainment crypto"}, 1395 {PCIC_DASP, -1, "dasp"}, 1396 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"}, 1397 {0, 0, NULL} 1398 }; 1399 1400 void 1401 pci_probe_nomatch(device_t dev, device_t child) 1402 { 1403 int i; 1404 char *cp, *scp, *device; 1405 1406 /* 1407 * Look for a listing for this device in a loaded device database. 1408 */ 1409 if ((device = pci_describe_device(child)) != NULL) { 1410 device_printf(dev, "<%s>", device); 1411 free(device, M_DEVBUF); 1412 } else { 1413 /* 1414 * Scan the class/subclass descriptions for a general 1415 * description. 1416 */ 1417 cp = "unknown"; 1418 scp = NULL; 1419 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1420 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1421 if (pci_nomatch_tab[i].subclass == -1) { 1422 cp = pci_nomatch_tab[i].desc; 1423 } else if (pci_nomatch_tab[i].subclass == 1424 pci_get_subclass(child)) { 1425 scp = pci_nomatch_tab[i].desc; 1426 } 1427 } 1428 } 1429 device_printf(dev, "<%s%s%s>", 1430 cp ? cp : "", 1431 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1432 scp ? scp : ""); 1433 } 1434 printf(" at device %d.%d (no driver attached)\n", 1435 pci_get_slot(child), pci_get_function(child)); 1436 if (pci_do_power_nodriver) 1437 pci_cfg_save(child, 1438 (struct pci_devinfo *) device_get_ivars(child), 1); 1439 return; 1440 } 1441 1442 /* 1443 * Parse the PCI device database, if loaded, and return a pointer to a 1444 * description of the device. 1445 * 1446 * The database is flat text formatted as follows: 1447 * 1448 * Any line not in a valid format is ignored. 1449 * Lines are terminated with newline '\n' characters. 1450 * 1451 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1452 * the vendor name. 1453 * 1454 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1455 * - devices cannot be listed without a corresponding VENDOR line. 1456 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1457 * another TAB, then the device name. 1458 */ 1459 1460 /* 1461 * Assuming (ptr) points to the beginning of a line in the database, 1462 * return the vendor or device and description of the next entry. 1463 * The value of (vendor) or (device) inappropriate for the entry type 1464 * is set to -1. Returns nonzero at the end of the database. 1465 * 1466 * Note that this is slightly unrobust in the face of corrupt data; 1467 * we attempt to safeguard against this by spamming the end of the 1468 * database with a newline when we initialise. 1469 */ 1470 static int 1471 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1472 { 1473 char *cp = *ptr; 1474 int left; 1475 1476 *device = -1; 1477 *vendor = -1; 1478 **desc = '\0'; 1479 for (;;) { 1480 left = pci_vendordata_size - (cp - pci_vendordata); 1481 if (left <= 0) { 1482 *ptr = cp; 1483 return(1); 1484 } 1485 1486 /* vendor entry? */ 1487 if (*cp != '\t' && 1488 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1489 break; 1490 /* device entry? */ 1491 if (*cp == '\t' && 1492 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1493 break; 1494 1495 /* skip to next line */ 1496 while (*cp != '\n' && left > 0) { 1497 cp++; 1498 left--; 1499 } 1500 if (*cp == '\n') { 1501 cp++; 1502 left--; 1503 } 1504 } 1505 /* skip to next line */ 1506 while (*cp != '\n' && left > 0) { 1507 cp++; 1508 left--; 1509 } 1510 if (*cp == '\n' && left > 0) 1511 cp++; 1512 *ptr = cp; 1513 return(0); 1514 } 1515 1516 static char * 1517 pci_describe_device(device_t dev) 1518 { 1519 int vendor, device; 1520 char *desc, *vp, *dp, *line; 1521 1522 desc = vp = dp = NULL; 1523 1524 /* 1525 * If we have no vendor data, we can't do anything. 1526 */ 1527 if (pci_vendordata == NULL) 1528 goto out; 1529 1530 /* 1531 * Scan the vendor data looking for this device 1532 */ 1533 line = pci_vendordata; 1534 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1535 goto out; 1536 for (;;) { 1537 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1538 goto out; 1539 if (vendor == pci_get_vendor(dev)) 1540 break; 1541 } 1542 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1543 goto out; 1544 for (;;) { 1545 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1546 *dp = 0; 1547 break; 1548 } 1549 if (vendor != -1) { 1550 *dp = 0; 1551 break; 1552 } 1553 if (device == pci_get_device(dev)) 1554 break; 1555 } 1556 if (dp[0] == '\0') 1557 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1558 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1559 NULL) 1560 sprintf(desc, "%s, %s", vp, dp); 1561 out: 1562 if (vp != NULL) 1563 free(vp, M_DEVBUF); 1564 if (dp != NULL) 1565 free(dp, M_DEVBUF); 1566 return(desc); 1567 } 1568 1569 int 1570 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1571 { 1572 struct pci_devinfo *dinfo; 1573 pcicfgregs *cfg; 1574 1575 dinfo = device_get_ivars(child); 1576 cfg = &dinfo->cfg; 1577 1578 switch (which) { 1579 case PCI_IVAR_ETHADDR: 1580 /* 1581 * The generic accessor doesn't deal with failure, so 1582 * we set the return value, then return an error. 1583 */ 1584 *((uint8_t **) result) = NULL; 1585 return (EINVAL); 1586 case PCI_IVAR_SUBVENDOR: 1587 *result = cfg->subvendor; 1588 break; 1589 case PCI_IVAR_SUBDEVICE: 1590 *result = cfg->subdevice; 1591 break; 1592 case PCI_IVAR_VENDOR: 1593 *result = cfg->vendor; 1594 break; 1595 case PCI_IVAR_DEVICE: 1596 *result = cfg->device; 1597 break; 1598 case PCI_IVAR_DEVID: 1599 *result = (cfg->device << 16) | cfg->vendor; 1600 break; 1601 case PCI_IVAR_CLASS: 1602 *result = cfg->baseclass; 1603 break; 1604 case PCI_IVAR_SUBCLASS: 1605 *result = cfg->subclass; 1606 break; 1607 case PCI_IVAR_PROGIF: 1608 *result = cfg->progif; 1609 break; 1610 case PCI_IVAR_REVID: 1611 *result = cfg->revid; 1612 break; 1613 case PCI_IVAR_INTPIN: 1614 *result = cfg->intpin; 1615 break; 1616 case PCI_IVAR_IRQ: 1617 *result = cfg->intline; 1618 break; 1619 case PCI_IVAR_BUS: 1620 *result = cfg->bus; 1621 break; 1622 case PCI_IVAR_SLOT: 1623 *result = cfg->slot; 1624 break; 1625 case PCI_IVAR_FUNCTION: 1626 *result = cfg->func; 1627 break; 1628 case PCI_IVAR_CMDREG: 1629 *result = cfg->cmdreg; 1630 break; 1631 case PCI_IVAR_CACHELNSZ: 1632 *result = cfg->cachelnsz; 1633 break; 1634 case PCI_IVAR_MINGNT: 1635 *result = cfg->mingnt; 1636 break; 1637 case PCI_IVAR_MAXLAT: 1638 *result = cfg->maxlat; 1639 break; 1640 case PCI_IVAR_LATTIMER: 1641 *result = cfg->lattimer; 1642 break; 1643 default: 1644 return (ENOENT); 1645 } 1646 return (0); 1647 } 1648 1649 int 1650 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1651 { 1652 struct pci_devinfo *dinfo; 1653 1654 dinfo = device_get_ivars(child); 1655 1656 switch (which) { 1657 case PCI_IVAR_INTPIN: 1658 dinfo->cfg.intpin = value; 1659 return (0); 1660 case PCI_IVAR_ETHADDR: 1661 case PCI_IVAR_SUBVENDOR: 1662 case PCI_IVAR_SUBDEVICE: 1663 case PCI_IVAR_VENDOR: 1664 case PCI_IVAR_DEVICE: 1665 case PCI_IVAR_DEVID: 1666 case PCI_IVAR_CLASS: 1667 case PCI_IVAR_SUBCLASS: 1668 case PCI_IVAR_PROGIF: 1669 case PCI_IVAR_REVID: 1670 case PCI_IVAR_IRQ: 1671 case PCI_IVAR_BUS: 1672 case PCI_IVAR_SLOT: 1673 case PCI_IVAR_FUNCTION: 1674 return (EINVAL); /* disallow for now */ 1675 1676 default: 1677 return (ENOENT); 1678 } 1679 } 1680 1681 1682 #include "opt_ddb.h" 1683 #ifdef DDB 1684 #include <ddb/ddb.h> 1685 #include <sys/cons.h> 1686 1687 /* 1688 * List resources based on pci map registers, used for within ddb 1689 */ 1690 1691 DB_SHOW_COMMAND(pciregs, db_pci_dump) 1692 { 1693 struct pci_devinfo *dinfo; 1694 struct devlist *devlist_head; 1695 struct pci_conf *p; 1696 const char *name; 1697 int i, error, none_count, quit; 1698 1699 none_count = 0; 1700 /* get the head of the device queue */ 1701 devlist_head = &pci_devq; 1702 1703 /* 1704 * Go through the list of devices and print out devices 1705 */ 1706 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 1707 for (error = 0, i = 0, quit = 0, 1708 dinfo = STAILQ_FIRST(devlist_head); 1709 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1710 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1711 1712 /* Populate pd_name and pd_unit */ 1713 name = NULL; 1714 if (dinfo->cfg.dev) 1715 name = device_get_name(dinfo->cfg.dev); 1716 1717 p = &dinfo->conf; 1718 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1719 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1720 (name && *name) ? name : "none", 1721 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1722 none_count++, 1723 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1724 p->pc_sel.pc_func, (p->pc_class << 16) | 1725 (p->pc_subclass << 8) | p->pc_progif, 1726 (p->pc_subdevice << 16) | p->pc_subvendor, 1727 (p->pc_device << 16) | p->pc_vendor, 1728 p->pc_revid, p->pc_hdr); 1729 } 1730 } 1731 #endif /* DDB */ 1732 1733 static struct resource * 1734 pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1735 u_long start, u_long end, u_long count, u_int flags) 1736 { 1737 struct pci_devinfo *dinfo = device_get_ivars(child); 1738 struct resource_list *rl = &dinfo->resources; 1739 struct resource_list_entry *rle; 1740 struct resource *res; 1741 uint32_t map, testval; 1742 int mapsize; 1743 1744 /* 1745 * Weed out the bogons, and figure out how large the BAR/map 1746 * is. Bars that read back 0 here are bogus and unimplemented. 1747 * Note: atapci in legacy mode are special and handled elsewhere 1748 * in the code. If you have a atapci device in legacy mode and 1749 * it fails here, that other code is broken. 1750 */ 1751 res = NULL; 1752 map = pci_read_config(child, *rid, 4); 1753 pci_write_config(child, *rid, 0xffffffff, 4); 1754 testval = pci_read_config(child, *rid, 4); 1755 if (pci_mapbase(testval) == 0) 1756 goto out; 1757 if (pci_maptype(testval) & PCI_MAPMEM) { 1758 if (type != SYS_RES_MEMORY) { 1759 if (bootverbose) 1760 device_printf(dev, 1761 "child %s requested type %d for rid %#x," 1762 " but the BAR says it is an memio\n", 1763 device_get_nameunit(child), type, *rid); 1764 goto out; 1765 } 1766 } else { 1767 if (type != SYS_RES_IOPORT) { 1768 if (bootverbose) 1769 device_printf(dev, 1770 "child %s requested type %d for rid %#x," 1771 " but the BAR says it is an ioport\n", 1772 device_get_nameunit(child), type, *rid); 1773 goto out; 1774 } 1775 } 1776 /* 1777 * For real BARs, we need to override the size that 1778 * the driver requests, because that's what the BAR 1779 * actually uses and we would otherwise have a 1780 * situation where we might allocate the excess to 1781 * another driver, which won't work. 1782 */ 1783 mapsize = pci_mapsize(testval); 1784 count = 1 << mapsize; 1785 if (RF_ALIGNMENT(flags) < mapsize) 1786 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1787 1788 /* 1789 * Allocate enough resource, and then write back the 1790 * appropriate bar for that resource. 1791 */ 1792 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1793 start, end, count, flags); 1794 if (res == NULL) { 1795 device_printf(child, 1796 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n", 1797 count, *rid, type, start, end); 1798 goto out; 1799 } 1800 resource_list_add(rl, type, *rid, start, end, count); 1801 rle = resource_list_find(rl, type, *rid); 1802 if (rle == NULL) 1803 panic("pci_alloc_map: unexpectedly can't find resource."); 1804 rle->res = res; 1805 rle->start = rman_get_start(res); 1806 rle->end = rman_get_end(res); 1807 rle->count = count; 1808 if (bootverbose) 1809 device_printf(child, 1810 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1811 count, *rid, type, rman_get_start(res)); 1812 map = rman_get_start(res); 1813 out:; 1814 pci_write_config(child, *rid, map, 4); 1815 return (res); 1816 } 1817 1818 1819 struct resource * 1820 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1821 u_long start, u_long end, u_long count, u_int flags) 1822 { 1823 struct pci_devinfo *dinfo = device_get_ivars(child); 1824 struct resource_list *rl = &dinfo->resources; 1825 struct resource_list_entry *rle; 1826 pcicfgregs *cfg = &dinfo->cfg; 1827 1828 /* 1829 * Perform lazy resource allocation 1830 */ 1831 if (device_get_parent(child) == dev) { 1832 switch (type) { 1833 case SYS_RES_IRQ: 1834 /* 1835 * If the child device doesn't have an 1836 * interrupt routed and is deserving of an 1837 * interrupt, try to assign it one. 1838 */ 1839 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1840 (cfg->intpin != 0)) 1841 pci_assign_interrupt(dev, child, 0); 1842 break; 1843 case SYS_RES_IOPORT: 1844 case SYS_RES_MEMORY: 1845 if (*rid < PCIR_BAR(cfg->nummaps)) { 1846 /* 1847 * Enable the I/O mode. We should 1848 * also be assigning resources too 1849 * when none are present. The 1850 * resource_list_alloc kind of sorta does 1851 * this... 1852 */ 1853 if (PCI_ENABLE_IO(dev, child, type)) 1854 return (NULL); 1855 } 1856 rle = resource_list_find(rl, type, *rid); 1857 if (rle == NULL) 1858 return (pci_alloc_map(dev, child, type, rid, 1859 start, end, count, flags)); 1860 break; 1861 } 1862 /* 1863 * If we've already allocated the resource, then 1864 * return it now. But first we may need to activate 1865 * it, since we don't allocate the resource as active 1866 * above. Normally this would be done down in the 1867 * nexus, but since we short-circuit that path we have 1868 * to do its job here. Not sure if we should free the 1869 * resource if it fails to activate. 1870 */ 1871 rle = resource_list_find(rl, type, *rid); 1872 if (rle != NULL && rle->res != NULL) { 1873 if (bootverbose) 1874 device_printf(child, 1875 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 1876 rman_get_size(rle->res), *rid, type, 1877 rman_get_start(rle->res)); 1878 if ((flags & RF_ACTIVE) && 1879 bus_generic_activate_resource(dev, child, type, 1880 *rid, rle->res) != 0) 1881 return NULL; 1882 return (rle->res); 1883 } 1884 } 1885 return (resource_list_alloc(rl, dev, child, type, rid, 1886 start, end, count, flags)); 1887 } 1888 1889 void 1890 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1891 { 1892 struct pci_devinfo *dinfo; 1893 struct resource_list *rl; 1894 struct resource_list_entry *rle; 1895 1896 if (device_get_parent(child) != dev) 1897 return; 1898 1899 dinfo = device_get_ivars(child); 1900 rl = &dinfo->resources; 1901 rle = resource_list_find(rl, type, rid); 1902 if (rle) { 1903 if (rle->res) { 1904 if (rman_get_device(rle->res) != dev || 1905 rman_get_flags(rle->res) & RF_ACTIVE) { 1906 device_printf(dev, "delete_resource: " 1907 "Resource still owned by child, oops. " 1908 "(type=%d, rid=%d, addr=%lx)\n", 1909 rle->type, rle->rid, 1910 rman_get_start(rle->res)); 1911 return; 1912 } 1913 bus_release_resource(dev, type, rid, rle->res); 1914 } 1915 resource_list_delete(rl, type, rid); 1916 } 1917 /* 1918 * Why do we turn off the PCI configuration BAR when we delete a 1919 * resource? -- imp 1920 */ 1921 pci_write_config(child, rid, 0, 4); 1922 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1923 } 1924 1925 struct resource_list * 1926 pci_get_resource_list (device_t dev, device_t child) 1927 { 1928 struct pci_devinfo *dinfo = device_get_ivars(child); 1929 1930 return (&dinfo->resources); 1931 } 1932 1933 uint32_t 1934 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1935 { 1936 struct pci_devinfo *dinfo = device_get_ivars(child); 1937 pcicfgregs *cfg = &dinfo->cfg; 1938 1939 return (PCIB_READ_CONFIG(device_get_parent(dev), 1940 cfg->bus, cfg->slot, cfg->func, reg, width)); 1941 } 1942 1943 void 1944 pci_write_config_method(device_t dev, device_t child, int reg, 1945 uint32_t val, int width) 1946 { 1947 struct pci_devinfo *dinfo = device_get_ivars(child); 1948 pcicfgregs *cfg = &dinfo->cfg; 1949 1950 PCIB_WRITE_CONFIG(device_get_parent(dev), 1951 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1952 } 1953 1954 int 1955 pci_child_location_str_method(device_t dev, device_t child, char *buf, 1956 size_t buflen) 1957 { 1958 1959 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1960 pci_get_function(child)); 1961 return (0); 1962 } 1963 1964 int 1965 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1966 size_t buflen) 1967 { 1968 struct pci_devinfo *dinfo; 1969 pcicfgregs *cfg; 1970 1971 dinfo = device_get_ivars(child); 1972 cfg = &dinfo->cfg; 1973 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1974 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1975 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1976 cfg->progif); 1977 return (0); 1978 } 1979 1980 int 1981 pci_assign_interrupt_method(device_t dev, device_t child) 1982 { 1983 struct pci_devinfo *dinfo = device_get_ivars(child); 1984 pcicfgregs *cfg = &dinfo->cfg; 1985 1986 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1987 cfg->intpin)); 1988 } 1989 1990 static int 1991 pci_modevent(module_t mod, int what, void *arg) 1992 { 1993 static struct cdev *pci_cdev; 1994 1995 switch (what) { 1996 case MOD_LOAD: 1997 STAILQ_INIT(&pci_devq); 1998 pci_generation = 0; 1999 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 2000 "pci"); 2001 pci_load_vendor_data(); 2002 break; 2003 2004 case MOD_UNLOAD: 2005 destroy_dev(pci_cdev); 2006 break; 2007 } 2008 2009 return (0); 2010 } 2011 2012 void 2013 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 2014 { 2015 int i; 2016 2017 /* 2018 * Only do header type 0 devices. Type 1 devices are bridges, 2019 * which we know need special treatment. Type 2 devices are 2020 * cardbus bridges which also require special treatment. 2021 * Other types are unknown, and we err on the side of safety 2022 * by ignoring them. 2023 */ 2024 if (dinfo->cfg.hdrtype != 0) 2025 return; 2026 2027 /* 2028 * Restore the device to full power mode. We must do this 2029 * before we restore the registers because moving from D3 to 2030 * D0 will cause the chip's BARs and some other registers to 2031 * be reset to some unknown power on reset values. Cut down 2032 * the noise on boot by doing nothing if we are already in 2033 * state D0. 2034 */ 2035 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 2036 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2037 } 2038 for (i = 0; i < dinfo->cfg.nummaps; i++) 2039 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 2040 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 2041 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 2042 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 2043 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 2044 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 2045 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 2046 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 2047 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 2048 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 2049 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 2050 } 2051 2052 void 2053 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 2054 { 2055 int i; 2056 uint32_t cls; 2057 int ps; 2058 2059 /* 2060 * Only do header type 0 devices. Type 1 devices are bridges, which 2061 * we know need special treatment. Type 2 devices are cardbus bridges 2062 * which also require special treatment. Other types are unknown, and 2063 * we err on the side of safety by ignoring them. Powering down 2064 * bridges should not be undertaken lightly. 2065 */ 2066 if (dinfo->cfg.hdrtype != 0) 2067 return; 2068 for (i = 0; i < dinfo->cfg.nummaps; i++) 2069 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 2070 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 2071 2072 /* 2073 * Some drivers apparently write to these registers w/o updating our 2074 * cached copy. No harm happens if we update the copy, so do so here 2075 * so we can restore them. The COMMAND register is modified by the 2076 * bus w/o updating the cache. This should represent the normally 2077 * writable portion of the 'defined' part of type 0 headers. In 2078 * theory we also need to save/restore the PCI capability structures 2079 * we know about, but apart from power we don't know any that are 2080 * writable. 2081 */ 2082 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 2083 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 2084 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 2085 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 2086 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 2087 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 2088 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 2089 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 2090 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 2091 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2092 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2093 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 2094 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 2095 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 2096 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 2097 2098 /* 2099 * don't set the state for display devices, base peripherals and 2100 * memory devices since bad things happen when they are powered down. 2101 * We should (a) have drivers that can easily detach and (b) use 2102 * generic drivers for these devices so that some device actually 2103 * attaches. We need to make sure that when we implement (a) we don't 2104 * power the device down on a reattach. 2105 */ 2106 cls = pci_get_class(dev); 2107 if (!setstate) 2108 return; 2109 switch (pci_do_power_nodriver) 2110 { 2111 case 0: /* NO powerdown at all */ 2112 return; 2113 case 1: /* Conservative about what to power down */ 2114 if (cls == PCIC_STORAGE) 2115 return; 2116 /*FALLTHROUGH*/ 2117 case 2: /* Agressive about what to power down */ 2118 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 2119 cls == PCIC_BASEPERIPH) 2120 return; 2121 /*FALLTHROUGH*/ 2122 case 3: /* Power down everything */ 2123 break; 2124 } 2125 /* 2126 * PCI spec says we can only go into D3 state from D0 state. 2127 * Transition from D[12] into D0 before going to D3 state. 2128 */ 2129 ps = pci_get_powerstate(dev); 2130 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 2131 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2132 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 2133 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 2134 } 2135