1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/linker.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/sysctl.h> 44 #include <sys/types.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 55 #include <sys/pciio.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pci_private.h> 59 60 #include "pcib_if.h" 61 #include "pci_if.h" 62 63 #if (defined(__i386__) && !defined(PC98)) || defined(__amd64__) || \ 64 defined (__ia64__) 65 #include <contrib/dev/acpica/acpi.h> 66 #include <dev/acpica/acpivar.h> 67 #include "acpi_if.h" 68 #else 69 #define ACPI_PWR_FOR_SLEEP(x, y, z) 70 #endif 71 72 static uint32_t pci_mapbase(unsigned mapreg); 73 static int pci_maptype(unsigned mapreg); 74 static int pci_mapsize(unsigned testval); 75 static int pci_maprange(unsigned mapreg); 76 static void pci_fixancient(pcicfgregs *cfg); 77 78 static int pci_porten(device_t pcib, int b, int s, int f); 79 static int pci_memen(device_t pcib, int b, int s, int f); 80 static int pci_add_map(device_t pcib, device_t bus, device_t dev, 81 int b, int s, int f, int reg, 82 struct resource_list *rl); 83 static void pci_add_resources(device_t pcib, device_t bus, 84 device_t dev); 85 static int pci_probe(device_t dev); 86 static int pci_attach(device_t dev); 87 static void pci_load_vendor_data(void); 88 static int pci_describe_parse_line(char **ptr, int *vendor, 89 int *device, char **desc); 90 static char *pci_describe_device(device_t dev); 91 static int pci_modevent(module_t mod, int what, void *arg); 92 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 93 pcicfgregs *cfg); 94 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 95 static void pci_cfg_restore(device_t, struct pci_devinfo *); 96 static void pci_cfg_save(device_t, struct pci_devinfo *, int); 97 98 static device_method_t pci_methods[] = { 99 /* Device interface */ 100 DEVMETHOD(device_probe, pci_probe), 101 DEVMETHOD(device_attach, pci_attach), 102 DEVMETHOD(device_shutdown, bus_generic_shutdown), 103 DEVMETHOD(device_suspend, pci_suspend), 104 DEVMETHOD(device_resume, pci_resume), 105 106 /* Bus interface */ 107 DEVMETHOD(bus_print_child, pci_print_child), 108 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 109 DEVMETHOD(bus_read_ivar, pci_read_ivar), 110 DEVMETHOD(bus_write_ivar, pci_write_ivar), 111 DEVMETHOD(bus_driver_added, pci_driver_added), 112 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 113 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 114 115 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 116 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 117 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 118 DEVMETHOD(bus_delete_resource, pci_delete_resource), 119 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 120 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 121 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 122 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 123 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 124 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 125 126 /* PCI interface */ 127 DEVMETHOD(pci_read_config, pci_read_config_method), 128 DEVMETHOD(pci_write_config, pci_write_config_method), 129 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 130 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 131 DEVMETHOD(pci_enable_io, pci_enable_io_method), 132 DEVMETHOD(pci_disable_io, pci_disable_io_method), 133 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 134 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 135 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 136 137 { 0, 0 } 138 }; 139 140 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 141 142 devclass_t pci_devclass; 143 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 144 MODULE_VERSION(pci, 1); 145 146 static char *pci_vendordata; 147 static size_t pci_vendordata_size; 148 149 150 struct pci_quirk { 151 uint32_t devid; /* Vendor/device of the card */ 152 int type; 153 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 154 int arg1; 155 int arg2; 156 }; 157 158 struct pci_quirk pci_quirks[] = { 159 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 160 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 161 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 162 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 163 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 164 165 { 0 } 166 }; 167 168 /* map register information */ 169 #define PCI_MAPMEM 0x01 /* memory map */ 170 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 171 #define PCI_MAPPORT 0x04 /* port map */ 172 173 struct devlist pci_devq; 174 uint32_t pci_generation; 175 uint32_t pci_numdevs = 0; 176 177 /* sysctl vars */ 178 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 179 180 static int pci_enable_io_modes = 1; 181 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 182 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 183 &pci_enable_io_modes, 1, 184 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 185 enable these bits correctly. We'd like to do this all the time, but there\n\ 186 are some peripherals that this causes problems with."); 187 188 static int pci_do_powerstate = 1; 189 TUNABLE_INT("hw.pci.do_powerstate", &pci_do_powerstate); 190 SYSCTL_INT(_hw_pci, OID_AUTO, do_powerstate, CTLFLAG_RW, 191 &pci_do_powerstate, 1, 192 "Power down devices into D3 state when no driver attaches to them.\n\ 193 Otherwise, leave the device in D0 state when no driver attaches."); 194 195 /* Find a device_t by bus/slot/function */ 196 197 device_t 198 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 199 { 200 struct pci_devinfo *dinfo; 201 202 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 203 if ((dinfo->cfg.bus == bus) && 204 (dinfo->cfg.slot == slot) && 205 (dinfo->cfg.func == func)) { 206 return (dinfo->cfg.dev); 207 } 208 } 209 210 return (NULL); 211 } 212 213 /* Find a device_t by vendor/device ID */ 214 215 device_t 216 pci_find_device(uint16_t vendor, uint16_t device) 217 { 218 struct pci_devinfo *dinfo; 219 220 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 221 if ((dinfo->cfg.vendor == vendor) && 222 (dinfo->cfg.device == device)) { 223 return (dinfo->cfg.dev); 224 } 225 } 226 227 return (NULL); 228 } 229 230 /* return base address of memory or port map */ 231 232 static uint32_t 233 pci_mapbase(unsigned mapreg) 234 { 235 int mask = 0x03; 236 if ((mapreg & 0x01) == 0) 237 mask = 0x0f; 238 return (mapreg & ~mask); 239 } 240 241 /* return map type of memory or port map */ 242 243 static int 244 pci_maptype(unsigned mapreg) 245 { 246 static uint8_t maptype[0x10] = { 247 PCI_MAPMEM, PCI_MAPPORT, 248 PCI_MAPMEM, 0, 249 PCI_MAPMEM, PCI_MAPPORT, 250 0, 0, 251 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 252 PCI_MAPMEM|PCI_MAPMEMP, 0, 253 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 254 0, 0, 255 }; 256 257 return maptype[mapreg & 0x0f]; 258 } 259 260 /* return log2 of map size decoded for memory or port map */ 261 262 static int 263 pci_mapsize(unsigned testval) 264 { 265 int ln2size; 266 267 testval = pci_mapbase(testval); 268 ln2size = 0; 269 if (testval != 0) { 270 while ((testval & 1) == 0) 271 { 272 ln2size++; 273 testval >>= 1; 274 } 275 } 276 return (ln2size); 277 } 278 279 /* return log2 of address range supported by map register */ 280 281 static int 282 pci_maprange(unsigned mapreg) 283 { 284 int ln2range = 0; 285 switch (mapreg & 0x07) { 286 case 0x00: 287 case 0x01: 288 case 0x05: 289 ln2range = 32; 290 break; 291 case 0x02: 292 ln2range = 20; 293 break; 294 case 0x04: 295 ln2range = 64; 296 break; 297 } 298 return (ln2range); 299 } 300 301 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 302 303 static void 304 pci_fixancient(pcicfgregs *cfg) 305 { 306 if (cfg->hdrtype != 0) 307 return; 308 309 /* PCI to PCI bridges use header type 1 */ 310 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 311 cfg->hdrtype = 1; 312 } 313 314 /* extract header type specific config data */ 315 316 static void 317 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 318 { 319 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 320 switch (cfg->hdrtype) { 321 case 0: 322 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 323 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 324 cfg->nummaps = PCI_MAXMAPS_0; 325 break; 326 case 1: 327 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 328 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 329 cfg->nummaps = PCI_MAXMAPS_1; 330 break; 331 case 2: 332 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 333 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 334 cfg->nummaps = PCI_MAXMAPS_2; 335 break; 336 } 337 #undef REG 338 } 339 340 /* read configuration header into pcicfgregs structure */ 341 342 struct pci_devinfo * 343 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 344 { 345 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 346 pcicfgregs *cfg = NULL; 347 struct pci_devinfo *devlist_entry; 348 struct devlist *devlist_head; 349 350 devlist_head = &pci_devq; 351 352 devlist_entry = NULL; 353 354 if (REG(PCIR_DEVVENDOR, 4) != -1) { 355 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 356 if (devlist_entry == NULL) 357 return (NULL); 358 359 cfg = &devlist_entry->cfg; 360 361 cfg->bus = b; 362 cfg->slot = s; 363 cfg->func = f; 364 cfg->vendor = REG(PCIR_VENDOR, 2); 365 cfg->device = REG(PCIR_DEVICE, 2); 366 cfg->cmdreg = REG(PCIR_COMMAND, 2); 367 cfg->statreg = REG(PCIR_STATUS, 2); 368 cfg->baseclass = REG(PCIR_CLASS, 1); 369 cfg->subclass = REG(PCIR_SUBCLASS, 1); 370 cfg->progif = REG(PCIR_PROGIF, 1); 371 cfg->revid = REG(PCIR_REVID, 1); 372 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 373 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 374 cfg->lattimer = REG(PCIR_LATTIMER, 1); 375 cfg->intpin = REG(PCIR_INTPIN, 1); 376 cfg->intline = REG(PCIR_INTLINE, 1); 377 378 cfg->mingnt = REG(PCIR_MINGNT, 1); 379 cfg->maxlat = REG(PCIR_MAXLAT, 1); 380 381 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 382 cfg->hdrtype &= ~PCIM_MFDEV; 383 384 pci_fixancient(cfg); 385 pci_hdrtypedata(pcib, b, s, f, cfg); 386 387 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 388 pci_read_extcap(pcib, cfg); 389 390 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 391 392 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 393 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 394 devlist_entry->conf.pc_sel.pc_func = cfg->func; 395 devlist_entry->conf.pc_hdr = cfg->hdrtype; 396 397 devlist_entry->conf.pc_subvendor = cfg->subvendor; 398 devlist_entry->conf.pc_subdevice = cfg->subdevice; 399 devlist_entry->conf.pc_vendor = cfg->vendor; 400 devlist_entry->conf.pc_device = cfg->device; 401 402 devlist_entry->conf.pc_class = cfg->baseclass; 403 devlist_entry->conf.pc_subclass = cfg->subclass; 404 devlist_entry->conf.pc_progif = cfg->progif; 405 devlist_entry->conf.pc_revid = cfg->revid; 406 407 pci_numdevs++; 408 pci_generation++; 409 } 410 return (devlist_entry); 411 #undef REG 412 } 413 414 static void 415 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 416 { 417 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 418 int ptr, nextptr, ptrptr; 419 420 switch (cfg->hdrtype & PCIM_HDRTYPE) { 421 case 0: 422 ptrptr = PCIR_CAP_PTR; 423 break; 424 case 2: 425 ptrptr = 0x14; 426 break; 427 default: 428 return; /* no extended capabilities support */ 429 } 430 nextptr = REG(ptrptr, 1); /* sanity check? */ 431 432 /* 433 * Read capability entries. 434 */ 435 while (nextptr != 0) { 436 /* Sanity check */ 437 if (nextptr > 255) { 438 printf("illegal PCI extended capability offset %d\n", 439 nextptr); 440 return; 441 } 442 /* Find the next entry */ 443 ptr = nextptr; 444 nextptr = REG(ptr + 1, 1); 445 446 /* Process this entry */ 447 switch (REG(ptr, 1)) { 448 case PCIY_PMG: /* PCI power management */ 449 if (cfg->pp.pp_cap == 0) { 450 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 451 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 452 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 453 if ((nextptr - ptr) > PCIR_POWER_DATA) 454 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 455 } 456 break; 457 case PCIY_MSI: /* PCI MSI */ 458 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 459 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 460 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 461 else 462 cfg->msi.msi_data = PCIR_MSI_DATA; 463 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 464 PCIM_MSICTRL_MMC_MASK)>>1); 465 default: 466 break; 467 } 468 } 469 #undef REG 470 } 471 472 /* free pcicfgregs structure and all depending data structures */ 473 474 int 475 pci_freecfg(struct pci_devinfo *dinfo) 476 { 477 struct devlist *devlist_head; 478 479 devlist_head = &pci_devq; 480 481 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 482 free(dinfo, M_DEVBUF); 483 484 /* increment the generation count */ 485 pci_generation++; 486 487 /* we're losing one device */ 488 pci_numdevs--; 489 return (0); 490 } 491 492 /* 493 * PCI power manangement 494 */ 495 int 496 pci_set_powerstate_method(device_t dev, device_t child, int state) 497 { 498 struct pci_devinfo *dinfo = device_get_ivars(child); 499 pcicfgregs *cfg = &dinfo->cfg; 500 uint16_t status; 501 int result, oldstate, highest, delay; 502 503 if (cfg->pp.pp_cap == 0) 504 return (EOPNOTSUPP); 505 506 /* 507 * Optimize a no state change request away. While it would be OK to 508 * write to the hardware in theory, some devices have shown odd 509 * behavior when going from D3 -> D3. 510 */ 511 oldstate = pci_get_powerstate(child); 512 if (oldstate == state) 513 return (0); 514 515 /* 516 * The PCI power management specification states that after a state 517 * transition between PCI power states, system software must 518 * guarantee a minimal delay before the function accesses the device. 519 * Compute the worst case delay that we need to guarantee before we 520 * access the device. Many devices will be responsive much more 521 * quickly than this delay, but there are some that don't respond 522 * instantly to state changes. Transitions to/from D3 state require 523 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 524 * is done below with DELAY rather than a sleeper function because 525 * this function can be called from contexts where we cannot sleep. 526 */ 527 highest = (oldstate > state) ? oldstate : state; 528 if (highest == PCI_POWERSTATE_D3) 529 delay = 10000; 530 else if (highest == PCI_POWERSTATE_D2) 531 delay = 200; 532 else 533 delay = 0; 534 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 535 & ~PCIM_PSTAT_DMASK; 536 result = 0; 537 switch (state) { 538 case PCI_POWERSTATE_D0: 539 status |= PCIM_PSTAT_D0; 540 break; 541 case PCI_POWERSTATE_D1: 542 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 543 return (EOPNOTSUPP); 544 status |= PCIM_PSTAT_D1; 545 break; 546 case PCI_POWERSTATE_D2: 547 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 548 return (EOPNOTSUPP); 549 status |= PCIM_PSTAT_D2; 550 break; 551 case PCI_POWERSTATE_D3: 552 status |= PCIM_PSTAT_D3; 553 break; 554 default: 555 return (EINVAL); 556 } 557 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 558 if (delay) 559 DELAY(delay); 560 return (0); 561 } 562 563 int 564 pci_get_powerstate_method(device_t dev, device_t child) 565 { 566 struct pci_devinfo *dinfo = device_get_ivars(child); 567 pcicfgregs *cfg = &dinfo->cfg; 568 uint16_t status; 569 int result; 570 571 if (cfg->pp.pp_cap != 0) { 572 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 573 switch (status & PCIM_PSTAT_DMASK) { 574 case PCIM_PSTAT_D0: 575 result = PCI_POWERSTATE_D0; 576 break; 577 case PCIM_PSTAT_D1: 578 result = PCI_POWERSTATE_D1; 579 break; 580 case PCIM_PSTAT_D2: 581 result = PCI_POWERSTATE_D2; 582 break; 583 case PCIM_PSTAT_D3: 584 result = PCI_POWERSTATE_D3; 585 break; 586 default: 587 result = PCI_POWERSTATE_UNKNOWN; 588 break; 589 } 590 } else { 591 /* No support, device is always at D0 */ 592 result = PCI_POWERSTATE_D0; 593 } 594 return (result); 595 } 596 597 /* 598 * Some convenience functions for PCI device drivers. 599 */ 600 601 static __inline void 602 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 603 { 604 uint16_t command; 605 606 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 607 command |= bit; 608 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 609 } 610 611 static __inline void 612 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 613 { 614 uint16_t command; 615 616 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 617 command &= ~bit; 618 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 619 } 620 621 int 622 pci_enable_busmaster_method(device_t dev, device_t child) 623 { 624 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 625 return (0); 626 } 627 628 int 629 pci_disable_busmaster_method(device_t dev, device_t child) 630 { 631 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 632 return (0); 633 } 634 635 int 636 pci_enable_io_method(device_t dev, device_t child, int space) 637 { 638 uint16_t command; 639 uint16_t bit; 640 char *error; 641 642 bit = 0; 643 error = NULL; 644 645 switch(space) { 646 case SYS_RES_IOPORT: 647 bit = PCIM_CMD_PORTEN; 648 error = "port"; 649 break; 650 case SYS_RES_MEMORY: 651 bit = PCIM_CMD_MEMEN; 652 error = "memory"; 653 break; 654 default: 655 return (EINVAL); 656 } 657 pci_set_command_bit(dev, child, bit); 658 /* Some devices seem to need a brief stall here, what do to? */ 659 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 660 if (command & bit) 661 return (0); 662 device_printf(child, "failed to enable %s mapping!\n", error); 663 return (ENXIO); 664 } 665 666 int 667 pci_disable_io_method(device_t dev, device_t child, int space) 668 { 669 uint16_t command; 670 uint16_t bit; 671 char *error; 672 673 bit = 0; 674 error = NULL; 675 676 switch(space) { 677 case SYS_RES_IOPORT: 678 bit = PCIM_CMD_PORTEN; 679 error = "port"; 680 break; 681 case SYS_RES_MEMORY: 682 bit = PCIM_CMD_MEMEN; 683 error = "memory"; 684 break; 685 default: 686 return (EINVAL); 687 } 688 pci_clear_command_bit(dev, child, bit); 689 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 690 if (command & bit) { 691 device_printf(child, "failed to disable %s mapping!\n", error); 692 return (ENXIO); 693 } 694 return (0); 695 } 696 697 /* 698 * New style pci driver. Parent device is either a pci-host-bridge or a 699 * pci-pci-bridge. Both kinds are represented by instances of pcib. 700 */ 701 702 void 703 pci_print_verbose(struct pci_devinfo *dinfo) 704 { 705 if (bootverbose) { 706 pcicfgregs *cfg = &dinfo->cfg; 707 708 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 709 cfg->vendor, cfg->device, cfg->revid); 710 printf("\tbus=%d, slot=%d, func=%d\n", 711 cfg->bus, cfg->slot, cfg->func); 712 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 713 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 714 cfg->mfdev); 715 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 716 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 717 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 718 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 719 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 720 if (cfg->intpin > 0) 721 printf("\tintpin=%c, irq=%d\n", 722 cfg->intpin +'a' -1, cfg->intline); 723 if (cfg->pp.pp_cap) { 724 uint16_t status; 725 726 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 727 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 728 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 729 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 730 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 731 status & PCIM_PSTAT_DMASK); 732 } 733 if (cfg->msi.msi_data) { 734 int ctrl; 735 736 ctrl = cfg->msi.msi_ctrl; 737 printf("\tMSI supports %d message%s%s%s\n", 738 cfg->msi.msi_msgnum, 739 (cfg->msi.msi_msgnum == 1) ? "" : "s", 740 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 741 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 742 } 743 } 744 } 745 746 static int 747 pci_porten(device_t pcib, int b, int s, int f) 748 { 749 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 750 & PCIM_CMD_PORTEN) != 0; 751 } 752 753 static int 754 pci_memen(device_t pcib, int b, int s, int f) 755 { 756 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 757 & PCIM_CMD_MEMEN) != 0; 758 } 759 760 /* 761 * Add a resource based on a pci map register. Return 1 if the map 762 * register is a 32bit map register or 2 if it is a 64bit register. 763 */ 764 static int 765 pci_add_map(device_t pcib, device_t bus, device_t dev, 766 int b, int s, int f, int reg, struct resource_list *rl) 767 { 768 uint32_t map; 769 uint64_t base; 770 uint64_t start, end, count; 771 uint8_t ln2size; 772 uint8_t ln2range; 773 uint32_t testval; 774 uint16_t cmd; 775 int type; 776 777 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 778 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 779 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 780 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 781 782 if (pci_maptype(map) & PCI_MAPMEM) 783 type = SYS_RES_MEMORY; 784 else 785 type = SYS_RES_IOPORT; 786 ln2size = pci_mapsize(testval); 787 ln2range = pci_maprange(testval); 788 base = pci_mapbase(map); 789 790 /* 791 * For I/O registers, if bottom bit is set, and the next bit up 792 * isn't clear, we know we have a BAR that doesn't conform to the 793 * spec, so ignore it. Also, sanity check the size of the data 794 * areas to the type of memory involved. Memory must be at least 795 * 32 bytes in size, while I/O ranges must be at least 4. 796 */ 797 if ((testval & 0x1) == 0x1 && 798 (testval & 0x2) != 0) 799 return (1); 800 if ((type == SYS_RES_MEMORY && ln2size < 5) || 801 (type == SYS_RES_IOPORT && ln2size < 2)) 802 return (1); 803 804 if (ln2range == 64) 805 /* Read the other half of a 64bit map register */ 806 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 807 808 if (bootverbose) { 809 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 810 reg, pci_maptype(map), ln2range, 811 (unsigned int) base, ln2size); 812 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 813 printf(", port disabled\n"); 814 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 815 printf(", memory disabled\n"); 816 else 817 printf(", enabled\n"); 818 } 819 820 /* 821 * This code theoretically does the right thing, but has 822 * undesirable side effects in some cases where peripherals 823 * respond oddly to having these bits enabled. Let the user 824 * be able to turn them off (since pci_enable_io_modes is 1 by 825 * default). 826 */ 827 if (pci_enable_io_modes) { 828 /* Turn on resources that have been left off by a lazy BIOS */ 829 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 830 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 831 cmd |= PCIM_CMD_PORTEN; 832 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 833 } 834 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 835 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 836 cmd |= PCIM_CMD_MEMEN; 837 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 838 } 839 } else { 840 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 841 return (1); 842 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 843 return (1); 844 } 845 /* 846 * If base is 0, then we have problems. It is best to ignore 847 * such entires for the moment. These will be allocated later if 848 * the driver specifically requests them. 849 */ 850 if (base == 0) 851 return 1; 852 853 start = base; 854 end = base + (1 << ln2size) - 1; 855 count = 1 << ln2size; 856 resource_list_add(rl, type, reg, start, end, count); 857 858 /* 859 * Not quite sure what to do on failure of allocating the resource 860 * since I can postulate several right answers. 861 */ 862 resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 0); 863 return ((ln2range == 64) ? 2 : 1); 864 } 865 866 /* 867 * For ATA devices we need to decide early what addressing mode to use. 868 * Legacy demands that the primary and secondary ATA ports sits on the 869 * same addresses that old ISA hardware did. This dictates that we use 870 * those addresses and ignore the BAR's if we cannot set PCI native 871 * addressing mode. 872 */ 873 static void 874 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 875 int s, int f, struct resource_list *rl) 876 { 877 int rid, type, progif; 878 #if 0 879 /* if this device supports PCI native addressing use it */ 880 progif = pci_read_config(dev, PCIR_PROGIF, 1); 881 if ((progif & 0x8a) == 0x8a) { 882 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 883 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 884 printf("Trying ATA native PCI addressing mode\n"); 885 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 886 } 887 } 888 #endif 889 progif = pci_read_config(dev, PCIR_PROGIF, 1); 890 type = SYS_RES_IOPORT; 891 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 892 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl); 893 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl); 894 } 895 else { 896 rid = PCIR_BAR(0); 897 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 898 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,8,0); 899 rid = PCIR_BAR(1); 900 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 901 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,1,0); 902 } 903 if (progif & PCIP_STORAGE_IDE_MODESEC) { 904 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl); 905 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl); 906 } 907 else { 908 rid = PCIR_BAR(2); 909 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 910 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,8,0); 911 rid = PCIR_BAR(3); 912 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 913 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,1,0); 914 } 915 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl); 916 } 917 918 static void 919 pci_add_resources(device_t pcib, device_t bus, device_t dev) 920 { 921 struct pci_devinfo *dinfo = device_get_ivars(dev); 922 pcicfgregs *cfg = &dinfo->cfg; 923 struct resource_list *rl = &dinfo->resources; 924 struct pci_quirk *q; 925 int b, i, irq, f, s; 926 927 b = cfg->bus; 928 s = cfg->slot; 929 f = cfg->func; 930 931 /* ATA devices needs special map treatment */ 932 if ((pci_get_class(dev) == PCIC_STORAGE) && 933 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 934 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 935 pci_ata_maps(pcib, bus, dev, b, s, f, rl); 936 else 937 for (i = 0; i < cfg->nummaps;) 938 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 939 rl); 940 941 for (q = &pci_quirks[0]; q->devid; q++) { 942 if (q->devid == ((cfg->device << 16) | cfg->vendor) 943 && q->type == PCI_QUIRK_MAP_REG) 944 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl); 945 } 946 947 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 948 #if defined(__ia64__) || defined(__i386__) || defined(__amd64__) || \ 949 defined(__arm__) 950 /* 951 * Try to re-route interrupts. Sometimes the BIOS or 952 * firmware may leave bogus values in these registers. 953 * If the re-route fails, then just stick with what we 954 * have. 955 */ 956 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 957 if (PCI_INTERRUPT_VALID(irq)) { 958 pci_write_config(dev, PCIR_INTLINE, irq, 1); 959 cfg->intline = irq; 960 } else 961 #endif 962 irq = cfg->intline; 963 resource_list_add(rl, SYS_RES_IRQ, 0, irq, irq, 1); 964 } 965 } 966 967 void 968 pci_add_children(device_t dev, int busno, size_t dinfo_size) 969 { 970 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 971 device_t pcib = device_get_parent(dev); 972 struct pci_devinfo *dinfo; 973 int maxslots; 974 int s, f, pcifunchigh; 975 uint8_t hdrtype; 976 977 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 978 ("dinfo_size too small")); 979 maxslots = PCIB_MAXSLOTS(pcib); 980 for (s = 0; s <= maxslots; s++) { 981 pcifunchigh = 0; 982 f = 0; 983 hdrtype = REG(PCIR_HDRTYPE, 1); 984 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 985 continue; 986 if (hdrtype & PCIM_MFDEV) 987 pcifunchigh = PCI_FUNCMAX; 988 for (f = 0; f <= pcifunchigh; f++) { 989 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 990 if (dinfo != NULL) { 991 pci_add_child(dev, dinfo); 992 } 993 } 994 } 995 #undef REG 996 } 997 998 void 999 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1000 { 1001 device_t pcib; 1002 1003 pcib = device_get_parent(bus); 1004 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1005 device_set_ivars(dinfo->cfg.dev, dinfo); 1006 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 1007 pci_cfg_restore(dinfo->cfg.dev, dinfo); 1008 pci_add_resources(pcib, bus, dinfo->cfg.dev); 1009 pci_print_verbose(dinfo); 1010 } 1011 1012 static int 1013 pci_probe(device_t dev) 1014 { 1015 1016 device_set_desc(dev, "PCI bus"); 1017 1018 /* Allow other subclasses to override this driver. */ 1019 return (-1000); 1020 } 1021 1022 static int 1023 pci_attach(device_t dev) 1024 { 1025 int busno; 1026 1027 /* 1028 * Since there can be multiple independantly numbered PCI 1029 * busses on some large alpha systems, we can't use the unit 1030 * number to decide what bus we are probing. We ask the parent 1031 * pcib what our bus number is. 1032 */ 1033 busno = pcib_get_bus(dev); 1034 if (bootverbose) 1035 device_printf(dev, "physical bus=%d\n", busno); 1036 1037 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1038 1039 return (bus_generic_attach(dev)); 1040 } 1041 1042 int 1043 pci_suspend(device_t dev) 1044 { 1045 int dstate, error, i, numdevs; 1046 device_t acpi_dev, child, *devlist; 1047 struct pci_devinfo *dinfo; 1048 1049 /* 1050 * Save the PCI configuration space for each child and set the 1051 * device in the appropriate power state for this sleep state. 1052 */ 1053 acpi_dev = NULL; 1054 if (pci_do_powerstate) 1055 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1056 device_get_children(dev, &devlist, &numdevs); 1057 for (i = 0; i < numdevs; i++) { 1058 child = devlist[i]; 1059 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1060 pci_cfg_save(child, dinfo, 0); 1061 } 1062 1063 /* Suspend devices before potentially powering them down. */ 1064 error = bus_generic_suspend(dev); 1065 if (error) 1066 return (error); 1067 1068 /* 1069 * Always set the device to D3. If ACPI suggests a different 1070 * power state, use it instead. If ACPI is not present, the 1071 * firmware is responsible for managing device power. Skip 1072 * children who aren't attached since they are powered down 1073 * separately. Only manage type 0 devices for now. 1074 */ 1075 for (i = 0; acpi_dev && i < numdevs; i++) { 1076 child = devlist[i]; 1077 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1078 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 1079 dstate = PCI_POWERSTATE_D3; 1080 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 1081 pci_set_powerstate(child, dstate); 1082 } 1083 } 1084 free(devlist, M_TEMP); 1085 return (0); 1086 } 1087 1088 int 1089 pci_resume(device_t dev) 1090 { 1091 int i, numdevs; 1092 device_t acpi_dev, child, *devlist; 1093 struct pci_devinfo *dinfo; 1094 1095 /* 1096 * Set each child to D0 and restore its PCI configuration space. 1097 */ 1098 acpi_dev = NULL; 1099 if (pci_do_powerstate) 1100 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1101 device_get_children(dev, &devlist, &numdevs); 1102 for (i = 0; i < numdevs; i++) { 1103 /* 1104 * Notify ACPI we're going to D0 but ignore the result. If 1105 * ACPI is not present, the firmware is responsible for 1106 * managing device power. Only manage type 0 devices for now. 1107 */ 1108 child = devlist[i]; 1109 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1110 if (acpi_dev && device_is_attached(child) && 1111 dinfo->cfg.hdrtype == 0) { 1112 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 1113 pci_set_powerstate(child, PCI_POWERSTATE_D0); 1114 } 1115 1116 /* Now the device is powered up, restore its config space. */ 1117 pci_cfg_restore(child, dinfo); 1118 } 1119 free(devlist, M_TEMP); 1120 return (bus_generic_resume(dev)); 1121 } 1122 1123 static void 1124 pci_load_vendor_data(void) 1125 { 1126 caddr_t vendordata, info; 1127 1128 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1129 info = preload_search_info(vendordata, MODINFO_ADDR); 1130 pci_vendordata = *(char **)info; 1131 info = preload_search_info(vendordata, MODINFO_SIZE); 1132 pci_vendordata_size = *(size_t *)info; 1133 /* terminate the database */ 1134 pci_vendordata[pci_vendordata_size] = '\n'; 1135 } 1136 } 1137 1138 void 1139 pci_driver_added(device_t dev, driver_t *driver) 1140 { 1141 int numdevs; 1142 device_t *devlist; 1143 device_t child; 1144 struct pci_devinfo *dinfo; 1145 int i; 1146 1147 if (bootverbose) 1148 device_printf(dev, "driver added\n"); 1149 DEVICE_IDENTIFY(driver, dev); 1150 device_get_children(dev, &devlist, &numdevs); 1151 for (i = 0; i < numdevs; i++) { 1152 child = devlist[i]; 1153 if (device_get_state(child) != DS_NOTPRESENT) 1154 continue; 1155 dinfo = device_get_ivars(child); 1156 pci_print_verbose(dinfo); 1157 /*XXX???*/ /* resource_list_init(&dinfo->cfg.resources); */ 1158 if (bootverbose) 1159 printf("pci%d:%d:%d: reprobing on driver added\n", 1160 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1161 pci_cfg_restore(child, dinfo); 1162 if (device_probe_and_attach(child) != 0) 1163 pci_cfg_save(child, dinfo, 1); 1164 } 1165 free(devlist, M_TEMP); 1166 } 1167 1168 int 1169 pci_print_child(device_t dev, device_t child) 1170 { 1171 struct pci_devinfo *dinfo; 1172 struct resource_list *rl; 1173 int retval = 0; 1174 1175 dinfo = device_get_ivars(child); 1176 rl = &dinfo->resources; 1177 1178 retval += bus_print_child_header(dev, child); 1179 1180 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1181 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1182 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1183 if (device_get_flags(dev)) 1184 retval += printf(" flags %#x", device_get_flags(dev)); 1185 1186 retval += printf(" at device %d.%d", pci_get_slot(child), 1187 pci_get_function(child)); 1188 1189 retval += bus_print_child_footer(dev, child); 1190 1191 return (retval); 1192 } 1193 1194 static struct 1195 { 1196 int class; 1197 int subclass; 1198 char *desc; 1199 } pci_nomatch_tab[] = { 1200 {PCIC_OLD, -1, "old"}, 1201 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1202 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1203 {PCIC_STORAGE, -1, "mass storage"}, 1204 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1205 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1206 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1207 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1208 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1209 {PCIC_NETWORK, -1, "network"}, 1210 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1211 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1212 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1213 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1214 {PCIC_DISPLAY, -1, "display"}, 1215 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1216 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1217 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1218 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1219 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1220 {PCIC_MEMORY, -1, "memory"}, 1221 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1222 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1223 {PCIC_BRIDGE, -1, "bridge"}, 1224 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1225 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1226 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1227 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1228 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1229 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1230 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1231 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1232 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 1233 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1234 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1235 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1236 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1237 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1238 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1239 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1240 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1241 {PCIC_INPUTDEV, -1, "input device"}, 1242 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1243 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1244 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1245 {PCIC_DOCKING, -1, "docking station"}, 1246 {PCIC_PROCESSOR, -1, "processor"}, 1247 {PCIC_SERIALBUS, -1, "serial bus"}, 1248 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1249 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1250 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1251 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1252 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1253 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1254 {0, 0, NULL} 1255 }; 1256 1257 void 1258 pci_probe_nomatch(device_t dev, device_t child) 1259 { 1260 int i; 1261 char *cp, *scp, *device; 1262 1263 /* 1264 * Look for a listing for this device in a loaded device database. 1265 */ 1266 if ((device = pci_describe_device(child)) != NULL) { 1267 device_printf(dev, "<%s>", device); 1268 free(device, M_DEVBUF); 1269 } else { 1270 /* 1271 * Scan the class/subclass descriptions for a general 1272 * description. 1273 */ 1274 cp = "unknown"; 1275 scp = NULL; 1276 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1277 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1278 if (pci_nomatch_tab[i].subclass == -1) { 1279 cp = pci_nomatch_tab[i].desc; 1280 } else if (pci_nomatch_tab[i].subclass == 1281 pci_get_subclass(child)) { 1282 scp = pci_nomatch_tab[i].desc; 1283 } 1284 } 1285 } 1286 device_printf(dev, "<%s%s%s>", 1287 cp ? cp : "", 1288 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1289 scp ? scp : ""); 1290 } 1291 printf(" at device %d.%d (no driver attached)\n", 1292 pci_get_slot(child), pci_get_function(child)); 1293 if (pci_do_powerstate) 1294 pci_cfg_save(child, 1295 (struct pci_devinfo *) device_get_ivars(child), 1); 1296 return; 1297 } 1298 1299 /* 1300 * Parse the PCI device database, if loaded, and return a pointer to a 1301 * description of the device. 1302 * 1303 * The database is flat text formatted as follows: 1304 * 1305 * Any line not in a valid format is ignored. 1306 * Lines are terminated with newline '\n' characters. 1307 * 1308 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1309 * the vendor name. 1310 * 1311 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1312 * - devices cannot be listed without a corresponding VENDOR line. 1313 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1314 * another TAB, then the device name. 1315 */ 1316 1317 /* 1318 * Assuming (ptr) points to the beginning of a line in the database, 1319 * return the vendor or device and description of the next entry. 1320 * The value of (vendor) or (device) inappropriate for the entry type 1321 * is set to -1. Returns nonzero at the end of the database. 1322 * 1323 * Note that this is slightly unrobust in the face of corrupt data; 1324 * we attempt to safeguard against this by spamming the end of the 1325 * database with a newline when we initialise. 1326 */ 1327 static int 1328 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1329 { 1330 char *cp = *ptr; 1331 int left; 1332 1333 *device = -1; 1334 *vendor = -1; 1335 **desc = '\0'; 1336 for (;;) { 1337 left = pci_vendordata_size - (cp - pci_vendordata); 1338 if (left <= 0) { 1339 *ptr = cp; 1340 return(1); 1341 } 1342 1343 /* vendor entry? */ 1344 if (*cp != '\t' && 1345 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1346 break; 1347 /* device entry? */ 1348 if (*cp == '\t' && 1349 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1350 break; 1351 1352 /* skip to next line */ 1353 while (*cp != '\n' && left > 0) { 1354 cp++; 1355 left--; 1356 } 1357 if (*cp == '\n') { 1358 cp++; 1359 left--; 1360 } 1361 } 1362 /* skip to next line */ 1363 while (*cp != '\n' && left > 0) { 1364 cp++; 1365 left--; 1366 } 1367 if (*cp == '\n' && left > 0) 1368 cp++; 1369 *ptr = cp; 1370 return(0); 1371 } 1372 1373 static char * 1374 pci_describe_device(device_t dev) 1375 { 1376 int vendor, device; 1377 char *desc, *vp, *dp, *line; 1378 1379 desc = vp = dp = NULL; 1380 1381 /* 1382 * If we have no vendor data, we can't do anything. 1383 */ 1384 if (pci_vendordata == NULL) 1385 goto out; 1386 1387 /* 1388 * Scan the vendor data looking for this device 1389 */ 1390 line = pci_vendordata; 1391 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1392 goto out; 1393 for (;;) { 1394 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1395 goto out; 1396 if (vendor == pci_get_vendor(dev)) 1397 break; 1398 } 1399 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1400 goto out; 1401 for (;;) { 1402 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1403 *dp = 0; 1404 break; 1405 } 1406 if (vendor != -1) { 1407 *dp = 0; 1408 break; 1409 } 1410 if (device == pci_get_device(dev)) 1411 break; 1412 } 1413 if (dp[0] == '\0') 1414 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1415 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1416 NULL) 1417 sprintf(desc, "%s, %s", vp, dp); 1418 out: 1419 if (vp != NULL) 1420 free(vp, M_DEVBUF); 1421 if (dp != NULL) 1422 free(dp, M_DEVBUF); 1423 return(desc); 1424 } 1425 1426 int 1427 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1428 { 1429 struct pci_devinfo *dinfo; 1430 pcicfgregs *cfg; 1431 1432 dinfo = device_get_ivars(child); 1433 cfg = &dinfo->cfg; 1434 1435 switch (which) { 1436 case PCI_IVAR_ETHADDR: 1437 /* 1438 * The generic accessor doesn't deal with failure, so 1439 * we set the return value, then return an error. 1440 */ 1441 *((uint8_t **) result) = NULL; 1442 return (EINVAL); 1443 case PCI_IVAR_SUBVENDOR: 1444 *result = cfg->subvendor; 1445 break; 1446 case PCI_IVAR_SUBDEVICE: 1447 *result = cfg->subdevice; 1448 break; 1449 case PCI_IVAR_VENDOR: 1450 *result = cfg->vendor; 1451 break; 1452 case PCI_IVAR_DEVICE: 1453 *result = cfg->device; 1454 break; 1455 case PCI_IVAR_DEVID: 1456 *result = (cfg->device << 16) | cfg->vendor; 1457 break; 1458 case PCI_IVAR_CLASS: 1459 *result = cfg->baseclass; 1460 break; 1461 case PCI_IVAR_SUBCLASS: 1462 *result = cfg->subclass; 1463 break; 1464 case PCI_IVAR_PROGIF: 1465 *result = cfg->progif; 1466 break; 1467 case PCI_IVAR_REVID: 1468 *result = cfg->revid; 1469 break; 1470 case PCI_IVAR_INTPIN: 1471 *result = cfg->intpin; 1472 break; 1473 case PCI_IVAR_IRQ: 1474 *result = cfg->intline; 1475 break; 1476 case PCI_IVAR_BUS: 1477 *result = cfg->bus; 1478 break; 1479 case PCI_IVAR_SLOT: 1480 *result = cfg->slot; 1481 break; 1482 case PCI_IVAR_FUNCTION: 1483 *result = cfg->func; 1484 break; 1485 default: 1486 return (ENOENT); 1487 } 1488 return (0); 1489 } 1490 1491 int 1492 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1493 { 1494 struct pci_devinfo *dinfo; 1495 1496 dinfo = device_get_ivars(child); 1497 1498 switch (which) { 1499 case PCI_IVAR_INTPIN: 1500 dinfo->cfg.intpin = value; 1501 return (0); 1502 case PCI_IVAR_ETHADDR: 1503 case PCI_IVAR_SUBVENDOR: 1504 case PCI_IVAR_SUBDEVICE: 1505 case PCI_IVAR_VENDOR: 1506 case PCI_IVAR_DEVICE: 1507 case PCI_IVAR_DEVID: 1508 case PCI_IVAR_CLASS: 1509 case PCI_IVAR_SUBCLASS: 1510 case PCI_IVAR_PROGIF: 1511 case PCI_IVAR_REVID: 1512 case PCI_IVAR_IRQ: 1513 case PCI_IVAR_BUS: 1514 case PCI_IVAR_SLOT: 1515 case PCI_IVAR_FUNCTION: 1516 return (EINVAL); /* disallow for now */ 1517 1518 default: 1519 return (ENOENT); 1520 } 1521 } 1522 1523 1524 #include "opt_ddb.h" 1525 #ifdef DDB 1526 #include <ddb/ddb.h> 1527 #include <sys/cons.h> 1528 1529 /* 1530 * List resources based on pci map registers, used for within ddb 1531 */ 1532 1533 DB_SHOW_COMMAND(pciregs, db_pci_dump) 1534 { 1535 struct pci_devinfo *dinfo; 1536 struct devlist *devlist_head; 1537 struct pci_conf *p; 1538 const char *name; 1539 int i, error, none_count, quit; 1540 1541 none_count = 0; 1542 /* get the head of the device queue */ 1543 devlist_head = &pci_devq; 1544 1545 /* 1546 * Go through the list of devices and print out devices 1547 */ 1548 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 1549 for (error = 0, i = 0, quit = 0, 1550 dinfo = STAILQ_FIRST(devlist_head); 1551 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1552 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1553 1554 /* Populate pd_name and pd_unit */ 1555 name = NULL; 1556 if (dinfo->cfg.dev) 1557 name = device_get_name(dinfo->cfg.dev); 1558 1559 p = &dinfo->conf; 1560 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1561 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1562 (name && *name) ? name : "none", 1563 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1564 none_count++, 1565 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1566 p->pc_sel.pc_func, (p->pc_class << 16) | 1567 (p->pc_subclass << 8) | p->pc_progif, 1568 (p->pc_subdevice << 16) | p->pc_subvendor, 1569 (p->pc_device << 16) | p->pc_vendor, 1570 p->pc_revid, p->pc_hdr); 1571 } 1572 } 1573 #endif /* DDB */ 1574 1575 static struct resource * 1576 pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1577 u_long start, u_long end, u_long count, u_int flags) 1578 { 1579 struct pci_devinfo *dinfo = device_get_ivars(child); 1580 struct resource_list *rl = &dinfo->resources; 1581 struct resource_list_entry *rle; 1582 struct resource *res; 1583 uint32_t map, testval; 1584 int mapsize; 1585 1586 /* 1587 * Weed out the bogons, and figure out how large the BAR/map 1588 * is. Bars that read back 0 here are bogus and unimplemented. 1589 * Note: atapci in legacy mode are special and handled elsewhere 1590 * in the code. If you have a atapci device in legacy mode and 1591 * it fails here, that other code is broken. 1592 */ 1593 res = NULL; 1594 map = pci_read_config(child, *rid, 4); 1595 pci_write_config(child, *rid, 0xffffffff, 4); 1596 testval = pci_read_config(child, *rid, 4); 1597 if (testval == 0) 1598 return (NULL); 1599 if (pci_maptype(testval) & PCI_MAPMEM) { 1600 if (type != SYS_RES_MEMORY) { 1601 device_printf(child, 1602 "failed: rid %#x is memory, requested %d\n", 1603 *rid, type); 1604 goto out; 1605 } 1606 } else { 1607 if (type != SYS_RES_IOPORT) { 1608 device_printf(child, 1609 "failed: rid %#x is ioport, requested %d\n", 1610 *rid, type); 1611 goto out; 1612 } 1613 } 1614 /* 1615 * For real BARs, we need to override the size that 1616 * the driver requests, because that's what the BAR 1617 * actually uses and we would otherwise have a 1618 * situation where we might allocate the excess to 1619 * another driver, which won't work. 1620 */ 1621 mapsize = pci_mapsize(testval); 1622 count = 1 << mapsize; 1623 if (RF_ALIGNMENT(flags) < mapsize) 1624 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1625 1626 /* 1627 * Allocate enough resource, and then write back the 1628 * appropriate bar for that resource. 1629 */ 1630 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1631 start, end, count, flags); 1632 if (res == NULL) { 1633 device_printf(child, "%#lx bytes of rid %#x res %d failed.\n", 1634 count, *rid, type); 1635 goto out; 1636 } 1637 resource_list_add(rl, type, *rid, start, end, count); 1638 rle = resource_list_find(rl, type, *rid); 1639 if (rle == NULL) 1640 panic("pci_alloc_map: unexpectedly can't find resource."); 1641 rle->res = res; 1642 if (bootverbose) 1643 device_printf(child, 1644 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1645 count, *rid, type, rman_get_start(res)); 1646 map = rman_get_start(res); 1647 out:; 1648 pci_write_config(child, *rid, map, 4); 1649 return (res); 1650 } 1651 1652 1653 struct resource * 1654 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1655 u_long start, u_long end, u_long count, u_int flags) 1656 { 1657 struct pci_devinfo *dinfo = device_get_ivars(child); 1658 struct resource_list *rl = &dinfo->resources; 1659 struct resource_list_entry *rle; 1660 pcicfgregs *cfg = &dinfo->cfg; 1661 1662 /* 1663 * Perform lazy resource allocation 1664 */ 1665 if (device_get_parent(child) == dev) { 1666 switch (type) { 1667 case SYS_RES_IRQ: 1668 /* 1669 * If the child device doesn't have an 1670 * interrupt routed and is deserving of an 1671 * interrupt, try to assign it one. 1672 */ 1673 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1674 (cfg->intpin != 0)) { 1675 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1676 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1677 pci_write_config(child, PCIR_INTLINE, 1678 cfg->intline, 1); 1679 resource_list_add(rl, SYS_RES_IRQ, 0, 1680 cfg->intline, cfg->intline, 1); 1681 } 1682 } 1683 break; 1684 case SYS_RES_IOPORT: 1685 case SYS_RES_MEMORY: 1686 if (*rid < PCIR_BAR(cfg->nummaps)) { 1687 /* 1688 * Enable the I/O mode. We should 1689 * also be assigning resources too 1690 * when none are present. The 1691 * resource_list_alloc kind of sorta does 1692 * this... 1693 */ 1694 if (PCI_ENABLE_IO(dev, child, type)) 1695 return (NULL); 1696 } 1697 rle = resource_list_find(rl, type, *rid); 1698 if (rle == NULL) 1699 return (pci_alloc_map(dev, child, type, rid, 1700 start, end, count, flags)); 1701 break; 1702 } 1703 /* 1704 * If we've already allocated the resource, then 1705 * return it now. But first we may need to activate 1706 * it, since we don't allocate the resource as active 1707 * above. Normally this would be done down in the 1708 * nexus, but since we short-circuit that path we have 1709 * to do its job here. Not sure if we should free the 1710 * resource if it fails to activate. 1711 */ 1712 rle = resource_list_find(rl, type, *rid); 1713 if (rle != NULL && rle->res != NULL) { 1714 if (bootverbose) 1715 device_printf(child, 1716 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 1717 rman_get_size(rle->res), *rid, type, 1718 rman_get_start(rle->res)); 1719 if ((flags & RF_ACTIVE) && 1720 bus_generic_activate_resource(dev, child, type, 1721 *rid, rle->res) != 0) 1722 return NULL; 1723 return (rle->res); 1724 } 1725 } 1726 return (resource_list_alloc(rl, dev, child, type, rid, 1727 start, end, count, flags)); 1728 } 1729 1730 void 1731 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1732 { 1733 struct pci_devinfo *dinfo; 1734 struct resource_list *rl; 1735 struct resource_list_entry *rle; 1736 1737 if (device_get_parent(child) != dev) 1738 return; 1739 1740 dinfo = device_get_ivars(child); 1741 rl = &dinfo->resources; 1742 rle = resource_list_find(rl, type, rid); 1743 if (rle) { 1744 if (rle->res) { 1745 if (rman_get_device(rle->res) != dev || 1746 rman_get_flags(rle->res) & RF_ACTIVE) { 1747 device_printf(dev, "delete_resource: " 1748 "Resource still owned by child, oops. " 1749 "(type=%d, rid=%d, addr=%lx)\n", 1750 rle->type, rle->rid, 1751 rman_get_start(rle->res)); 1752 return; 1753 } 1754 bus_release_resource(dev, type, rid, rle->res); 1755 } 1756 resource_list_delete(rl, type, rid); 1757 } 1758 /* 1759 * Why do we turn off the PCI configuration BAR when we delete a 1760 * resource? -- imp 1761 */ 1762 pci_write_config(child, rid, 0, 4); 1763 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1764 } 1765 1766 struct resource_list * 1767 pci_get_resource_list (device_t dev, device_t child) 1768 { 1769 struct pci_devinfo *dinfo = device_get_ivars(child); 1770 1771 return (&dinfo->resources); 1772 } 1773 1774 uint32_t 1775 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1776 { 1777 struct pci_devinfo *dinfo = device_get_ivars(child); 1778 pcicfgregs *cfg = &dinfo->cfg; 1779 1780 return (PCIB_READ_CONFIG(device_get_parent(dev), 1781 cfg->bus, cfg->slot, cfg->func, reg, width)); 1782 } 1783 1784 void 1785 pci_write_config_method(device_t dev, device_t child, int reg, 1786 uint32_t val, int width) 1787 { 1788 struct pci_devinfo *dinfo = device_get_ivars(child); 1789 pcicfgregs *cfg = &dinfo->cfg; 1790 1791 PCIB_WRITE_CONFIG(device_get_parent(dev), 1792 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1793 } 1794 1795 int 1796 pci_child_location_str_method(device_t dev, device_t child, char *buf, 1797 size_t buflen) 1798 { 1799 struct pci_devinfo *dinfo; 1800 1801 dinfo = device_get_ivars(child); 1802 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1803 pci_get_function(child)); 1804 return (0); 1805 } 1806 1807 int 1808 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1809 size_t buflen) 1810 { 1811 struct pci_devinfo *dinfo; 1812 pcicfgregs *cfg; 1813 1814 dinfo = device_get_ivars(child); 1815 cfg = &dinfo->cfg; 1816 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1817 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1818 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1819 cfg->progif); 1820 return (0); 1821 } 1822 1823 int 1824 pci_assign_interrupt_method(device_t dev, device_t child) 1825 { 1826 struct pci_devinfo *dinfo = device_get_ivars(child); 1827 pcicfgregs *cfg = &dinfo->cfg; 1828 1829 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1830 cfg->intpin)); 1831 } 1832 1833 static int 1834 pci_modevent(module_t mod, int what, void *arg) 1835 { 1836 static struct cdev *pci_cdev; 1837 1838 switch (what) { 1839 case MOD_LOAD: 1840 STAILQ_INIT(&pci_devq); 1841 pci_generation = 0; 1842 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1843 "pci"); 1844 pci_load_vendor_data(); 1845 break; 1846 1847 case MOD_UNLOAD: 1848 destroy_dev(pci_cdev); 1849 break; 1850 } 1851 1852 return (0); 1853 } 1854 1855 static void 1856 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 1857 { 1858 int i; 1859 1860 /* 1861 * Only do header type 0 devices. Type 1 devices are bridges, 1862 * which we know need special treatment. Type 2 devices are 1863 * cardbus bridges which also require special treatment. 1864 * Other types are unknown, and we err on the side of safety 1865 * by ignoring them. 1866 */ 1867 if (dinfo->cfg.hdrtype != 0) 1868 return; 1869 1870 /* 1871 * Restore the device to full power mode. We must do this 1872 * before we restore the registers because moving from D3 to 1873 * D0 will cause the chip's BARs and some other registers to 1874 * be reset to some unknown power on reset values. Cut down 1875 * the noise on boot by doing nothing if we are already in 1876 * state D0. 1877 */ 1878 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1879 if (bootverbose) 1880 printf( 1881 "pci%d:%d:%d: Transition from D%d to D0\n", 1882 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 1883 pci_get_powerstate(dev)); 1884 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1885 } 1886 for (i = 0; i < dinfo->cfg.nummaps; i++) 1887 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 1888 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 1889 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 1890 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 1891 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 1892 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 1893 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 1894 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 1895 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 1896 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 1897 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 1898 } 1899 1900 static void 1901 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 1902 { 1903 int i; 1904 uint32_t cls; 1905 int ps; 1906 1907 /* 1908 * Only do header type 0 devices. Type 1 devices are bridges, which 1909 * we know need special treatment. Type 2 devices are cardbus bridges 1910 * which also require special treatment. Other types are unknown, and 1911 * we err on the side of safety by ignoring them. Powering down 1912 * bridges should not be undertaken lightly. 1913 */ 1914 if (dinfo->cfg.hdrtype != 0) 1915 return; 1916 for (i = 0; i < dinfo->cfg.nummaps; i++) 1917 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1918 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 1919 1920 /* 1921 * Some drivers apparently write to these registers w/o updating our 1922 * cahced copy. No harm happens if we update the copy, so do so here 1923 * so we can restore them. The COMMAND register is modified by the 1924 * bus w/o updating the cache. This should represent the normally 1925 * writable portion of the 'defined' part of type 0 headers. In 1926 * theory we also need to save/restore the PCI capability structures 1927 * we know about, but apart from power we don't know any that are 1928 * writable. 1929 */ 1930 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1931 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1932 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 1933 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 1934 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 1935 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 1936 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 1937 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 1938 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 1939 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1940 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1941 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 1942 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 1943 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 1944 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 1945 1946 /* 1947 * don't set the state for display devices, base peripherals and 1948 * memory devices since bad things happen when they are powered down. 1949 * We should (a) have drivers that can easily detach and (b) use 1950 * generic drivers for these devices so that some device actually 1951 * attaches. We need to make sure that when we implement (a) we don't 1952 * power the device down on a reattach. 1953 */ 1954 cls = pci_get_class(dev); 1955 if (setstate && cls != PCIC_DISPLAY && cls != PCIC_MEMORY && 1956 cls != PCIC_BASEPERIPH) { 1957 /* 1958 * PCI spec says we can only go into D3 state from D0 state. 1959 * Transition from D[12] into D0 before going to D3 state. 1960 */ 1961 ps = pci_get_powerstate(dev); 1962 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) { 1963 if (bootverbose) 1964 printf( 1965 "pci%d:%d:%d: Transition from D%d to D0\n", 1966 dinfo->cfg.bus, dinfo->cfg.slot, 1967 dinfo->cfg.func, ps); 1968 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1969 } 1970 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) { 1971 if (bootverbose) 1972 printf( 1973 "pci%d:%d:%d: Transition from D0 to D3\n", 1974 dinfo->cfg.bus, dinfo->cfg.slot, 1975 dinfo->cfg.func); 1976 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 1977 } 1978 } 1979 } 1980