1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/linker.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/sysctl.h> 44 #include <sys/types.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 55 #include <sys/pciio.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pci_private.h> 59 60 #include "pcib_if.h" 61 #include "pci_if.h" 62 63 #if (defined(__i386__) && !defined(PC98)) || defined(__amd64__) || \ 64 defined (__ia64__) 65 #include <contrib/dev/acpica/acpi.h> 66 #include "acpi_if.h" 67 #else 68 #define ACPI_PWR_FOR_SLEEP(x, y, z) 69 #endif 70 71 static uint32_t pci_mapbase(unsigned mapreg); 72 static int pci_maptype(unsigned mapreg); 73 static int pci_mapsize(unsigned testval); 74 static int pci_maprange(unsigned mapreg); 75 static void pci_fixancient(pcicfgregs *cfg); 76 77 static int pci_porten(device_t pcib, int b, int s, int f); 78 static int pci_memen(device_t pcib, int b, int s, int f); 79 static int pci_add_map(device_t pcib, device_t bus, device_t dev, 80 int b, int s, int f, int reg, 81 struct resource_list *rl); 82 static void pci_add_resources(device_t pcib, device_t bus, 83 device_t dev); 84 static int pci_probe(device_t dev); 85 static int pci_attach(device_t dev); 86 static void pci_load_vendor_data(void); 87 static int pci_describe_parse_line(char **ptr, int *vendor, 88 int *device, char **desc); 89 static char *pci_describe_device(device_t dev); 90 static int pci_modevent(module_t mod, int what, void *arg); 91 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 92 pcicfgregs *cfg); 93 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 94 95 static device_method_t pci_methods[] = { 96 /* Device interface */ 97 DEVMETHOD(device_probe, pci_probe), 98 DEVMETHOD(device_attach, pci_attach), 99 DEVMETHOD(device_detach, bus_generic_detach), 100 DEVMETHOD(device_shutdown, bus_generic_shutdown), 101 DEVMETHOD(device_suspend, pci_suspend), 102 DEVMETHOD(device_resume, pci_resume), 103 104 /* Bus interface */ 105 DEVMETHOD(bus_print_child, pci_print_child), 106 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 107 DEVMETHOD(bus_read_ivar, pci_read_ivar), 108 DEVMETHOD(bus_write_ivar, pci_write_ivar), 109 DEVMETHOD(bus_driver_added, pci_driver_added), 110 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 111 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 112 113 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 114 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 115 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 116 DEVMETHOD(bus_delete_resource, pci_delete_resource), 117 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 118 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 119 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 120 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 121 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 122 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 123 124 /* PCI interface */ 125 DEVMETHOD(pci_read_config, pci_read_config_method), 126 DEVMETHOD(pci_write_config, pci_write_config_method), 127 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 128 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 129 DEVMETHOD(pci_enable_io, pci_enable_io_method), 130 DEVMETHOD(pci_disable_io, pci_disable_io_method), 131 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 132 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 133 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 134 135 { 0, 0 } 136 }; 137 138 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 139 140 devclass_t pci_devclass; 141 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 142 MODULE_VERSION(pci, 1); 143 144 static char *pci_vendordata; 145 static size_t pci_vendordata_size; 146 147 148 struct pci_quirk { 149 uint32_t devid; /* Vendor/device of the card */ 150 int type; 151 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 152 int arg1; 153 int arg2; 154 }; 155 156 struct pci_quirk pci_quirks[] = { 157 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 158 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 159 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 160 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 161 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 162 163 { 0 } 164 }; 165 166 /* map register information */ 167 #define PCI_MAPMEM 0x01 /* memory map */ 168 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 169 #define PCI_MAPPORT 0x04 /* port map */ 170 171 struct devlist pci_devq; 172 uint32_t pci_generation; 173 uint32_t pci_numdevs = 0; 174 175 /* sysctl vars */ 176 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 177 178 static int pci_enable_io_modes = 1; 179 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 180 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 181 &pci_enable_io_modes, 1, 182 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 183 enable these bits correctly. We'd like to do this all the time, but there\n\ 184 are some peripherals that this causes problems with."); 185 186 static int pci_do_power_nodriver = 0; 187 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver); 188 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW, 189 &pci_do_power_nodriver, 0, 190 "Place a function into D3 state when no driver attaches to it. 0 means\n\ 191 disable. 1 means conservatively place devices into D3 state. 2 means\n\ 192 agressively place devices into D3 state. 3 means put absolutely everything\n\ 193 in D3 state."); 194 195 static int pci_do_power_resume = 1; 196 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume); 197 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW, 198 &pci_do_power_resume, 1, 199 "Transition from D3 -> D0 on resume."); 200 201 /* Find a device_t by bus/slot/function */ 202 203 device_t 204 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 205 { 206 struct pci_devinfo *dinfo; 207 208 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 209 if ((dinfo->cfg.bus == bus) && 210 (dinfo->cfg.slot == slot) && 211 (dinfo->cfg.func == func)) { 212 return (dinfo->cfg.dev); 213 } 214 } 215 216 return (NULL); 217 } 218 219 /* Find a device_t by vendor/device ID */ 220 221 device_t 222 pci_find_device(uint16_t vendor, uint16_t device) 223 { 224 struct pci_devinfo *dinfo; 225 226 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 227 if ((dinfo->cfg.vendor == vendor) && 228 (dinfo->cfg.device == device)) { 229 return (dinfo->cfg.dev); 230 } 231 } 232 233 return (NULL); 234 } 235 236 /* return base address of memory or port map */ 237 238 static uint32_t 239 pci_mapbase(unsigned mapreg) 240 { 241 int mask = 0x03; 242 if ((mapreg & 0x01) == 0) 243 mask = 0x0f; 244 return (mapreg & ~mask); 245 } 246 247 /* return map type of memory or port map */ 248 249 static int 250 pci_maptype(unsigned mapreg) 251 { 252 static uint8_t maptype[0x10] = { 253 PCI_MAPMEM, PCI_MAPPORT, 254 PCI_MAPMEM, 0, 255 PCI_MAPMEM, PCI_MAPPORT, 256 0, 0, 257 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 258 PCI_MAPMEM|PCI_MAPMEMP, 0, 259 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 260 0, 0, 261 }; 262 263 return maptype[mapreg & 0x0f]; 264 } 265 266 /* return log2 of map size decoded for memory or port map */ 267 268 static int 269 pci_mapsize(unsigned testval) 270 { 271 int ln2size; 272 273 testval = pci_mapbase(testval); 274 ln2size = 0; 275 if (testval != 0) { 276 while ((testval & 1) == 0) 277 { 278 ln2size++; 279 testval >>= 1; 280 } 281 } 282 return (ln2size); 283 } 284 285 /* return log2 of address range supported by map register */ 286 287 static int 288 pci_maprange(unsigned mapreg) 289 { 290 int ln2range = 0; 291 switch (mapreg & 0x07) { 292 case 0x00: 293 case 0x01: 294 case 0x05: 295 ln2range = 32; 296 break; 297 case 0x02: 298 ln2range = 20; 299 break; 300 case 0x04: 301 ln2range = 64; 302 break; 303 } 304 return (ln2range); 305 } 306 307 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 308 309 static void 310 pci_fixancient(pcicfgregs *cfg) 311 { 312 if (cfg->hdrtype != 0) 313 return; 314 315 /* PCI to PCI bridges use header type 1 */ 316 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 317 cfg->hdrtype = 1; 318 } 319 320 /* extract header type specific config data */ 321 322 static void 323 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 324 { 325 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 326 switch (cfg->hdrtype) { 327 case 0: 328 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 329 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 330 cfg->nummaps = PCI_MAXMAPS_0; 331 break; 332 case 1: 333 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 334 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 335 cfg->nummaps = PCI_MAXMAPS_1; 336 break; 337 case 2: 338 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 339 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 340 cfg->nummaps = PCI_MAXMAPS_2; 341 break; 342 } 343 #undef REG 344 } 345 346 /* read configuration header into pcicfgregs structure */ 347 348 struct pci_devinfo * 349 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 350 { 351 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 352 pcicfgregs *cfg = NULL; 353 struct pci_devinfo *devlist_entry; 354 struct devlist *devlist_head; 355 356 devlist_head = &pci_devq; 357 358 devlist_entry = NULL; 359 360 if (REG(PCIR_DEVVENDOR, 4) != -1) { 361 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 362 if (devlist_entry == NULL) 363 return (NULL); 364 365 cfg = &devlist_entry->cfg; 366 367 cfg->bus = b; 368 cfg->slot = s; 369 cfg->func = f; 370 cfg->vendor = REG(PCIR_VENDOR, 2); 371 cfg->device = REG(PCIR_DEVICE, 2); 372 cfg->cmdreg = REG(PCIR_COMMAND, 2); 373 cfg->statreg = REG(PCIR_STATUS, 2); 374 cfg->baseclass = REG(PCIR_CLASS, 1); 375 cfg->subclass = REG(PCIR_SUBCLASS, 1); 376 cfg->progif = REG(PCIR_PROGIF, 1); 377 cfg->revid = REG(PCIR_REVID, 1); 378 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 379 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 380 cfg->lattimer = REG(PCIR_LATTIMER, 1); 381 cfg->intpin = REG(PCIR_INTPIN, 1); 382 cfg->intline = REG(PCIR_INTLINE, 1); 383 384 cfg->mingnt = REG(PCIR_MINGNT, 1); 385 cfg->maxlat = REG(PCIR_MAXLAT, 1); 386 387 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 388 cfg->hdrtype &= ~PCIM_MFDEV; 389 390 pci_fixancient(cfg); 391 pci_hdrtypedata(pcib, b, s, f, cfg); 392 393 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 394 pci_read_extcap(pcib, cfg); 395 396 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 397 398 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 399 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 400 devlist_entry->conf.pc_sel.pc_func = cfg->func; 401 devlist_entry->conf.pc_hdr = cfg->hdrtype; 402 403 devlist_entry->conf.pc_subvendor = cfg->subvendor; 404 devlist_entry->conf.pc_subdevice = cfg->subdevice; 405 devlist_entry->conf.pc_vendor = cfg->vendor; 406 devlist_entry->conf.pc_device = cfg->device; 407 408 devlist_entry->conf.pc_class = cfg->baseclass; 409 devlist_entry->conf.pc_subclass = cfg->subclass; 410 devlist_entry->conf.pc_progif = cfg->progif; 411 devlist_entry->conf.pc_revid = cfg->revid; 412 413 pci_numdevs++; 414 pci_generation++; 415 } 416 return (devlist_entry); 417 #undef REG 418 } 419 420 static void 421 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 422 { 423 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 424 int ptr, nextptr, ptrptr; 425 426 switch (cfg->hdrtype & PCIM_HDRTYPE) { 427 case 0: 428 ptrptr = PCIR_CAP_PTR; 429 break; 430 case 2: 431 ptrptr = 0x14; 432 break; 433 default: 434 return; /* no extended capabilities support */ 435 } 436 nextptr = REG(ptrptr, 1); /* sanity check? */ 437 438 /* 439 * Read capability entries. 440 */ 441 while (nextptr != 0) { 442 /* Sanity check */ 443 if (nextptr > 255) { 444 printf("illegal PCI extended capability offset %d\n", 445 nextptr); 446 return; 447 } 448 /* Find the next entry */ 449 ptr = nextptr; 450 nextptr = REG(ptr + 1, 1); 451 452 /* Process this entry */ 453 switch (REG(ptr, 1)) { 454 case PCIY_PMG: /* PCI power management */ 455 if (cfg->pp.pp_cap == 0) { 456 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 457 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 458 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 459 if ((nextptr - ptr) > PCIR_POWER_DATA) 460 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 461 } 462 break; 463 case PCIY_MSI: /* PCI MSI */ 464 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 465 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 466 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 467 else 468 cfg->msi.msi_data = PCIR_MSI_DATA; 469 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 470 PCIM_MSICTRL_MMC_MASK)>>1); 471 default: 472 break; 473 } 474 } 475 #undef REG 476 } 477 478 /* free pcicfgregs structure and all depending data structures */ 479 480 int 481 pci_freecfg(struct pci_devinfo *dinfo) 482 { 483 struct devlist *devlist_head; 484 485 devlist_head = &pci_devq; 486 487 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 488 free(dinfo, M_DEVBUF); 489 490 /* increment the generation count */ 491 pci_generation++; 492 493 /* we're losing one device */ 494 pci_numdevs--; 495 return (0); 496 } 497 498 /* 499 * PCI power manangement 500 */ 501 int 502 pci_set_powerstate_method(device_t dev, device_t child, int state) 503 { 504 struct pci_devinfo *dinfo = device_get_ivars(child); 505 pcicfgregs *cfg = &dinfo->cfg; 506 uint16_t status; 507 int result, oldstate, highest, delay; 508 509 if (cfg->pp.pp_cap == 0) 510 return (EOPNOTSUPP); 511 512 /* 513 * Optimize a no state change request away. While it would be OK to 514 * write to the hardware in theory, some devices have shown odd 515 * behavior when going from D3 -> D3. 516 */ 517 oldstate = pci_get_powerstate(child); 518 if (oldstate == state) 519 return (0); 520 521 /* 522 * The PCI power management specification states that after a state 523 * transition between PCI power states, system software must 524 * guarantee a minimal delay before the function accesses the device. 525 * Compute the worst case delay that we need to guarantee before we 526 * access the device. Many devices will be responsive much more 527 * quickly than this delay, but there are some that don't respond 528 * instantly to state changes. Transitions to/from D3 state require 529 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 530 * is done below with DELAY rather than a sleeper function because 531 * this function can be called from contexts where we cannot sleep. 532 */ 533 highest = (oldstate > state) ? oldstate : state; 534 if (highest == PCI_POWERSTATE_D3) 535 delay = 10000; 536 else if (highest == PCI_POWERSTATE_D2) 537 delay = 200; 538 else 539 delay = 0; 540 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 541 & ~PCIM_PSTAT_DMASK; 542 result = 0; 543 switch (state) { 544 case PCI_POWERSTATE_D0: 545 status |= PCIM_PSTAT_D0; 546 break; 547 case PCI_POWERSTATE_D1: 548 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 549 return (EOPNOTSUPP); 550 status |= PCIM_PSTAT_D1; 551 break; 552 case PCI_POWERSTATE_D2: 553 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 554 return (EOPNOTSUPP); 555 status |= PCIM_PSTAT_D2; 556 break; 557 case PCI_POWERSTATE_D3: 558 status |= PCIM_PSTAT_D3; 559 break; 560 default: 561 return (EINVAL); 562 } 563 564 if (bootverbose) 565 printf( 566 "pci%d:%d:%d: Transition from D%d to D%d\n", 567 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 568 oldstate, state); 569 570 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 571 if (delay) 572 DELAY(delay); 573 return (0); 574 } 575 576 int 577 pci_get_powerstate_method(device_t dev, device_t child) 578 { 579 struct pci_devinfo *dinfo = device_get_ivars(child); 580 pcicfgregs *cfg = &dinfo->cfg; 581 uint16_t status; 582 int result; 583 584 if (cfg->pp.pp_cap != 0) { 585 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 586 switch (status & PCIM_PSTAT_DMASK) { 587 case PCIM_PSTAT_D0: 588 result = PCI_POWERSTATE_D0; 589 break; 590 case PCIM_PSTAT_D1: 591 result = PCI_POWERSTATE_D1; 592 break; 593 case PCIM_PSTAT_D2: 594 result = PCI_POWERSTATE_D2; 595 break; 596 case PCIM_PSTAT_D3: 597 result = PCI_POWERSTATE_D3; 598 break; 599 default: 600 result = PCI_POWERSTATE_UNKNOWN; 601 break; 602 } 603 } else { 604 /* No support, device is always at D0 */ 605 result = PCI_POWERSTATE_D0; 606 } 607 return (result); 608 } 609 610 /* 611 * Some convenience functions for PCI device drivers. 612 */ 613 614 static __inline void 615 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 616 { 617 uint16_t command; 618 619 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 620 command |= bit; 621 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 622 } 623 624 static __inline void 625 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 626 { 627 uint16_t command; 628 629 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 630 command &= ~bit; 631 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 632 } 633 634 int 635 pci_enable_busmaster_method(device_t dev, device_t child) 636 { 637 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 638 return (0); 639 } 640 641 int 642 pci_disable_busmaster_method(device_t dev, device_t child) 643 { 644 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 645 return (0); 646 } 647 648 int 649 pci_enable_io_method(device_t dev, device_t child, int space) 650 { 651 uint16_t command; 652 uint16_t bit; 653 char *error; 654 655 bit = 0; 656 error = NULL; 657 658 switch(space) { 659 case SYS_RES_IOPORT: 660 bit = PCIM_CMD_PORTEN; 661 error = "port"; 662 break; 663 case SYS_RES_MEMORY: 664 bit = PCIM_CMD_MEMEN; 665 error = "memory"; 666 break; 667 default: 668 return (EINVAL); 669 } 670 pci_set_command_bit(dev, child, bit); 671 /* Some devices seem to need a brief stall here, what do to? */ 672 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 673 if (command & bit) 674 return (0); 675 device_printf(child, "failed to enable %s mapping!\n", error); 676 return (ENXIO); 677 } 678 679 int 680 pci_disable_io_method(device_t dev, device_t child, int space) 681 { 682 uint16_t command; 683 uint16_t bit; 684 char *error; 685 686 bit = 0; 687 error = NULL; 688 689 switch(space) { 690 case SYS_RES_IOPORT: 691 bit = PCIM_CMD_PORTEN; 692 error = "port"; 693 break; 694 case SYS_RES_MEMORY: 695 bit = PCIM_CMD_MEMEN; 696 error = "memory"; 697 break; 698 default: 699 return (EINVAL); 700 } 701 pci_clear_command_bit(dev, child, bit); 702 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 703 if (command & bit) { 704 device_printf(child, "failed to disable %s mapping!\n", error); 705 return (ENXIO); 706 } 707 return (0); 708 } 709 710 /* 711 * New style pci driver. Parent device is either a pci-host-bridge or a 712 * pci-pci-bridge. Both kinds are represented by instances of pcib. 713 */ 714 715 void 716 pci_print_verbose(struct pci_devinfo *dinfo) 717 { 718 if (bootverbose) { 719 pcicfgregs *cfg = &dinfo->cfg; 720 721 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 722 cfg->vendor, cfg->device, cfg->revid); 723 printf("\tbus=%d, slot=%d, func=%d\n", 724 cfg->bus, cfg->slot, cfg->func); 725 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 726 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 727 cfg->mfdev); 728 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 729 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 730 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 731 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 732 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 733 if (cfg->intpin > 0) 734 printf("\tintpin=%c, irq=%d\n", 735 cfg->intpin +'a' -1, cfg->intline); 736 if (cfg->pp.pp_cap) { 737 uint16_t status; 738 739 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 740 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 741 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 742 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 743 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 744 status & PCIM_PSTAT_DMASK); 745 } 746 if (cfg->msi.msi_data) { 747 int ctrl; 748 749 ctrl = cfg->msi.msi_ctrl; 750 printf("\tMSI supports %d message%s%s%s\n", 751 cfg->msi.msi_msgnum, 752 (cfg->msi.msi_msgnum == 1) ? "" : "s", 753 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 754 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 755 } 756 } 757 } 758 759 static int 760 pci_porten(device_t pcib, int b, int s, int f) 761 { 762 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 763 & PCIM_CMD_PORTEN) != 0; 764 } 765 766 static int 767 pci_memen(device_t pcib, int b, int s, int f) 768 { 769 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 770 & PCIM_CMD_MEMEN) != 0; 771 } 772 773 /* 774 * Add a resource based on a pci map register. Return 1 if the map 775 * register is a 32bit map register or 2 if it is a 64bit register. 776 */ 777 static int 778 pci_add_map(device_t pcib, device_t bus, device_t dev, 779 int b, int s, int f, int reg, struct resource_list *rl) 780 { 781 uint32_t map; 782 uint64_t base; 783 uint64_t start, end, count; 784 uint8_t ln2size; 785 uint8_t ln2range; 786 uint32_t testval; 787 uint16_t cmd; 788 int type; 789 int barlen; 790 791 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 792 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 793 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 794 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 795 796 if (pci_maptype(map) & PCI_MAPMEM) 797 type = SYS_RES_MEMORY; 798 else 799 type = SYS_RES_IOPORT; 800 ln2size = pci_mapsize(testval); 801 ln2range = pci_maprange(testval); 802 base = pci_mapbase(map); 803 barlen = ln2range == 64 ? 2 : 1; 804 805 /* 806 * For I/O registers, if bottom bit is set, and the next bit up 807 * isn't clear, we know we have a BAR that doesn't conform to the 808 * spec, so ignore it. Also, sanity check the size of the data 809 * areas to the type of memory involved. Memory must be at least 810 * 32 bytes in size, while I/O ranges must be at least 4. 811 */ 812 if ((testval & 0x1) == 0x1 && 813 (testval & 0x2) != 0) 814 return (barlen); 815 if ((type == SYS_RES_MEMORY && ln2size < 5) || 816 (type == SYS_RES_IOPORT && ln2size < 2)) 817 return (barlen); 818 819 if (ln2range == 64) 820 /* Read the other half of a 64bit map register */ 821 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 822 823 if (bootverbose) { 824 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 825 reg, pci_maptype(map), ln2range, 826 (unsigned int) base, ln2size); 827 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 828 printf(", port disabled\n"); 829 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 830 printf(", memory disabled\n"); 831 else 832 printf(", enabled\n"); 833 } 834 835 /* 836 * If base is 0, then we have problems. It is best to ignore 837 * such entries for the moment. These will be allocated later if 838 * the driver specifically requests them. 839 * 840 * Similarly treat maps whose values is the same as the test value 841 * read back. These maps have had all f's written to them by the 842 * BIOS in an attempt to disable the resources. 843 */ 844 if (base == 0 || map == testval) 845 return (barlen); 846 847 /* 848 * This code theoretically does the right thing, but has 849 * undesirable side effects in some cases where peripherals 850 * respond oddly to having these bits enabled. Let the user 851 * be able to turn them off (since pci_enable_io_modes is 1 by 852 * default). 853 */ 854 if (pci_enable_io_modes) { 855 /* Turn on resources that have been left off by a lazy BIOS */ 856 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 857 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 858 cmd |= PCIM_CMD_PORTEN; 859 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 860 } 861 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 862 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 863 cmd |= PCIM_CMD_MEMEN; 864 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 865 } 866 } else { 867 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 868 return (barlen); 869 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 870 return (barlen); 871 } 872 873 start = base; 874 end = base + (1 << ln2size) - 1; 875 count = 1 << ln2size; 876 resource_list_add(rl, type, reg, start, end, count); 877 878 /* 879 * Not quite sure what to do on failure of allocating the resource 880 * since I can postulate several right answers. 881 */ 882 resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 0); 883 return (barlen); 884 } 885 886 /* 887 * For ATA devices we need to decide early what addressing mode to use. 888 * Legacy demands that the primary and secondary ATA ports sits on the 889 * same addresses that old ISA hardware did. This dictates that we use 890 * those addresses and ignore the BAR's if we cannot set PCI native 891 * addressing mode. 892 */ 893 static void 894 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 895 int s, int f, struct resource_list *rl) 896 { 897 int rid, type, progif; 898 #if 0 899 /* if this device supports PCI native addressing use it */ 900 progif = pci_read_config(dev, PCIR_PROGIF, 1); 901 if ((progif & 0x8a) == 0x8a) { 902 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 903 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 904 printf("Trying ATA native PCI addressing mode\n"); 905 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 906 } 907 } 908 #endif 909 progif = pci_read_config(dev, PCIR_PROGIF, 1); 910 type = SYS_RES_IOPORT; 911 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 912 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl); 913 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl); 914 } 915 else { 916 rid = PCIR_BAR(0); 917 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 918 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7,8,0); 919 rid = PCIR_BAR(1); 920 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 921 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6,1,0); 922 } 923 if (progif & PCIP_STORAGE_IDE_MODESEC) { 924 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl); 925 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl); 926 } 927 else { 928 rid = PCIR_BAR(2); 929 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 930 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177,8,0); 931 rid = PCIR_BAR(3); 932 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 933 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376,1,0); 934 } 935 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl); 936 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl); 937 } 938 939 static void 940 pci_add_resources(device_t pcib, device_t bus, device_t dev) 941 { 942 struct pci_devinfo *dinfo = device_get_ivars(dev); 943 pcicfgregs *cfg = &dinfo->cfg; 944 struct resource_list *rl = &dinfo->resources; 945 struct pci_quirk *q; 946 int b, i, irq, f, s; 947 948 b = cfg->bus; 949 s = cfg->slot; 950 f = cfg->func; 951 952 /* ATA devices needs special map treatment */ 953 if ((pci_get_class(dev) == PCIC_STORAGE) && 954 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 955 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 956 pci_ata_maps(pcib, bus, dev, b, s, f, rl); 957 else 958 for (i = 0; i < cfg->nummaps;) 959 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 960 rl); 961 962 for (q = &pci_quirks[0]; q->devid; q++) { 963 if (q->devid == ((cfg->device << 16) | cfg->vendor) 964 && q->type == PCI_QUIRK_MAP_REG) 965 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl); 966 } 967 968 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 969 #if defined(__ia64__) || defined(__i386__) || defined(__amd64__) || \ 970 defined(__arm__) || defined(__alpha__) 971 /* 972 * Try to re-route interrupts. Sometimes the BIOS or 973 * firmware may leave bogus values in these registers. 974 * If the re-route fails, then just stick with what we 975 * have. 976 */ 977 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 978 if (PCI_INTERRUPT_VALID(irq)) { 979 pci_write_config(dev, PCIR_INTLINE, irq, 1); 980 cfg->intline = irq; 981 } else 982 #endif 983 irq = cfg->intline; 984 resource_list_add(rl, SYS_RES_IRQ, 0, irq, irq, 1); 985 } 986 } 987 988 void 989 pci_add_children(device_t dev, int busno, size_t dinfo_size) 990 { 991 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 992 device_t pcib = device_get_parent(dev); 993 struct pci_devinfo *dinfo; 994 int maxslots; 995 int s, f, pcifunchigh; 996 uint8_t hdrtype; 997 998 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 999 ("dinfo_size too small")); 1000 maxslots = PCIB_MAXSLOTS(pcib); 1001 for (s = 0; s <= maxslots; s++) { 1002 pcifunchigh = 0; 1003 f = 0; 1004 hdrtype = REG(PCIR_HDRTYPE, 1); 1005 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 1006 continue; 1007 if (hdrtype & PCIM_MFDEV) 1008 pcifunchigh = PCI_FUNCMAX; 1009 for (f = 0; f <= pcifunchigh; f++) { 1010 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 1011 if (dinfo != NULL) { 1012 pci_add_child(dev, dinfo); 1013 } 1014 } 1015 } 1016 #undef REG 1017 } 1018 1019 void 1020 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1021 { 1022 device_t pcib; 1023 1024 pcib = device_get_parent(bus); 1025 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1026 device_set_ivars(dinfo->cfg.dev, dinfo); 1027 resource_list_init(&dinfo->resources); 1028 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 1029 pci_cfg_restore(dinfo->cfg.dev, dinfo); 1030 pci_print_verbose(dinfo); 1031 pci_add_resources(pcib, bus, dinfo->cfg.dev); 1032 } 1033 1034 static int 1035 pci_probe(device_t dev) 1036 { 1037 1038 device_set_desc(dev, "PCI bus"); 1039 1040 /* Allow other subclasses to override this driver. */ 1041 return (-1000); 1042 } 1043 1044 static int 1045 pci_attach(device_t dev) 1046 { 1047 int busno; 1048 1049 /* 1050 * Since there can be multiple independantly numbered PCI 1051 * busses on some large alpha systems, we can't use the unit 1052 * number to decide what bus we are probing. We ask the parent 1053 * pcib what our bus number is. 1054 */ 1055 busno = pcib_get_bus(dev); 1056 if (bootverbose) 1057 device_printf(dev, "physical bus=%d\n", busno); 1058 1059 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1060 1061 return (bus_generic_attach(dev)); 1062 } 1063 1064 int 1065 pci_suspend(device_t dev) 1066 { 1067 int dstate, error, i, numdevs; 1068 device_t acpi_dev, child, *devlist; 1069 struct pci_devinfo *dinfo; 1070 1071 /* 1072 * Save the PCI configuration space for each child and set the 1073 * device in the appropriate power state for this sleep state. 1074 */ 1075 acpi_dev = NULL; 1076 if (pci_do_power_resume) 1077 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1078 device_get_children(dev, &devlist, &numdevs); 1079 for (i = 0; i < numdevs; i++) { 1080 child = devlist[i]; 1081 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1082 pci_cfg_save(child, dinfo, 0); 1083 } 1084 1085 /* Suspend devices before potentially powering them down. */ 1086 error = bus_generic_suspend(dev); 1087 if (error) { 1088 free(devlist, M_TEMP); 1089 return (error); 1090 } 1091 1092 /* 1093 * Always set the device to D3. If ACPI suggests a different 1094 * power state, use it instead. If ACPI is not present, the 1095 * firmware is responsible for managing device power. Skip 1096 * children who aren't attached since they are powered down 1097 * separately. Only manage type 0 devices for now. 1098 */ 1099 for (i = 0; acpi_dev && i < numdevs; i++) { 1100 child = devlist[i]; 1101 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1102 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 1103 dstate = PCI_POWERSTATE_D3; 1104 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 1105 pci_set_powerstate(child, dstate); 1106 } 1107 } 1108 free(devlist, M_TEMP); 1109 return (0); 1110 } 1111 1112 int 1113 pci_resume(device_t dev) 1114 { 1115 int i, numdevs; 1116 device_t acpi_dev, child, *devlist; 1117 struct pci_devinfo *dinfo; 1118 1119 /* 1120 * Set each child to D0 and restore its PCI configuration space. 1121 */ 1122 acpi_dev = NULL; 1123 if (pci_do_power_resume) 1124 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1125 device_get_children(dev, &devlist, &numdevs); 1126 for (i = 0; i < numdevs; i++) { 1127 /* 1128 * Notify ACPI we're going to D0 but ignore the result. If 1129 * ACPI is not present, the firmware is responsible for 1130 * managing device power. Only manage type 0 devices for now. 1131 */ 1132 child = devlist[i]; 1133 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1134 if (acpi_dev && device_is_attached(child) && 1135 dinfo->cfg.hdrtype == 0) { 1136 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 1137 pci_set_powerstate(child, PCI_POWERSTATE_D0); 1138 } 1139 1140 /* Now the device is powered up, restore its config space. */ 1141 pci_cfg_restore(child, dinfo); 1142 } 1143 free(devlist, M_TEMP); 1144 return (bus_generic_resume(dev)); 1145 } 1146 1147 static void 1148 pci_load_vendor_data(void) 1149 { 1150 caddr_t vendordata, info; 1151 1152 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1153 info = preload_search_info(vendordata, MODINFO_ADDR); 1154 pci_vendordata = *(char **)info; 1155 info = preload_search_info(vendordata, MODINFO_SIZE); 1156 pci_vendordata_size = *(size_t *)info; 1157 /* terminate the database */ 1158 pci_vendordata[pci_vendordata_size] = '\n'; 1159 } 1160 } 1161 1162 void 1163 pci_driver_added(device_t dev, driver_t *driver) 1164 { 1165 int numdevs; 1166 device_t *devlist; 1167 device_t child; 1168 struct pci_devinfo *dinfo; 1169 int i; 1170 1171 if (bootverbose) 1172 device_printf(dev, "driver added\n"); 1173 DEVICE_IDENTIFY(driver, dev); 1174 device_get_children(dev, &devlist, &numdevs); 1175 for (i = 0; i < numdevs; i++) { 1176 child = devlist[i]; 1177 if (device_get_state(child) != DS_NOTPRESENT) 1178 continue; 1179 dinfo = device_get_ivars(child); 1180 pci_print_verbose(dinfo); 1181 if (bootverbose) 1182 printf("pci%d:%d:%d: reprobing on driver added\n", 1183 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1184 pci_cfg_restore(child, dinfo); 1185 if (device_probe_and_attach(child) != 0) 1186 pci_cfg_save(child, dinfo, 1); 1187 } 1188 free(devlist, M_TEMP); 1189 } 1190 1191 int 1192 pci_print_child(device_t dev, device_t child) 1193 { 1194 struct pci_devinfo *dinfo; 1195 struct resource_list *rl; 1196 int retval = 0; 1197 1198 dinfo = device_get_ivars(child); 1199 rl = &dinfo->resources; 1200 1201 retval += bus_print_child_header(dev, child); 1202 1203 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1204 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1205 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1206 if (device_get_flags(dev)) 1207 retval += printf(" flags %#x", device_get_flags(dev)); 1208 1209 retval += printf(" at device %d.%d", pci_get_slot(child), 1210 pci_get_function(child)); 1211 1212 retval += bus_print_child_footer(dev, child); 1213 1214 return (retval); 1215 } 1216 1217 static struct 1218 { 1219 int class; 1220 int subclass; 1221 char *desc; 1222 } pci_nomatch_tab[] = { 1223 {PCIC_OLD, -1, "old"}, 1224 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1225 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1226 {PCIC_STORAGE, -1, "mass storage"}, 1227 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1228 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1229 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1230 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1231 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1232 {PCIC_NETWORK, -1, "network"}, 1233 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1234 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1235 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1236 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1237 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"}, 1238 {PCIC_DISPLAY, -1, "display"}, 1239 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1240 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1241 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"}, 1242 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1243 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1244 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1245 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"}, 1246 {PCIC_MEMORY, -1, "memory"}, 1247 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1248 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1249 {PCIC_BRIDGE, -1, "bridge"}, 1250 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1251 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1252 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1253 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1254 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1255 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1256 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1257 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1258 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"}, 1259 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1260 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1261 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1262 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"}, 1263 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"}, 1264 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1265 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1266 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1267 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1268 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1269 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"}, 1270 {PCIC_INPUTDEV, -1, "input device"}, 1271 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1272 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1273 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1274 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"}, 1275 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"}, 1276 {PCIC_DOCKING, -1, "docking station"}, 1277 {PCIC_PROCESSOR, -1, "processor"}, 1278 {PCIC_SERIALBUS, -1, "serial bus"}, 1279 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1280 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1281 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1282 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1283 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1284 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1285 {PCIC_WIRELESS, -1, "wireless controller"}, 1286 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"}, 1287 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"}, 1288 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"}, 1289 {PCIC_INTELLIIO, -1, "intelligent I/O controller"}, 1290 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"}, 1291 {PCIC_SATCOM, -1, "satellite communication"}, 1292 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"}, 1293 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"}, 1294 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"}, 1295 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"}, 1296 {PCIC_CRYPTO, -1, "encrypt/decrypt"}, 1297 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"}, 1298 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "entertainment crypto"}, 1299 {PCIC_DASP, -1, "dasp"}, 1300 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"}, 1301 {0, 0, NULL} 1302 }; 1303 1304 void 1305 pci_probe_nomatch(device_t dev, device_t child) 1306 { 1307 int i; 1308 char *cp, *scp, *device; 1309 1310 /* 1311 * Look for a listing for this device in a loaded device database. 1312 */ 1313 if ((device = pci_describe_device(child)) != NULL) { 1314 device_printf(dev, "<%s>", device); 1315 free(device, M_DEVBUF); 1316 } else { 1317 /* 1318 * Scan the class/subclass descriptions for a general 1319 * description. 1320 */ 1321 cp = "unknown"; 1322 scp = NULL; 1323 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1324 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1325 if (pci_nomatch_tab[i].subclass == -1) { 1326 cp = pci_nomatch_tab[i].desc; 1327 } else if (pci_nomatch_tab[i].subclass == 1328 pci_get_subclass(child)) { 1329 scp = pci_nomatch_tab[i].desc; 1330 } 1331 } 1332 } 1333 device_printf(dev, "<%s%s%s>", 1334 cp ? cp : "", 1335 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1336 scp ? scp : ""); 1337 } 1338 printf(" at device %d.%d (no driver attached)\n", 1339 pci_get_slot(child), pci_get_function(child)); 1340 if (pci_do_power_nodriver) 1341 pci_cfg_save(child, 1342 (struct pci_devinfo *) device_get_ivars(child), 1); 1343 return; 1344 } 1345 1346 /* 1347 * Parse the PCI device database, if loaded, and return a pointer to a 1348 * description of the device. 1349 * 1350 * The database is flat text formatted as follows: 1351 * 1352 * Any line not in a valid format is ignored. 1353 * Lines are terminated with newline '\n' characters. 1354 * 1355 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1356 * the vendor name. 1357 * 1358 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1359 * - devices cannot be listed without a corresponding VENDOR line. 1360 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1361 * another TAB, then the device name. 1362 */ 1363 1364 /* 1365 * Assuming (ptr) points to the beginning of a line in the database, 1366 * return the vendor or device and description of the next entry. 1367 * The value of (vendor) or (device) inappropriate for the entry type 1368 * is set to -1. Returns nonzero at the end of the database. 1369 * 1370 * Note that this is slightly unrobust in the face of corrupt data; 1371 * we attempt to safeguard against this by spamming the end of the 1372 * database with a newline when we initialise. 1373 */ 1374 static int 1375 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1376 { 1377 char *cp = *ptr; 1378 int left; 1379 1380 *device = -1; 1381 *vendor = -1; 1382 **desc = '\0'; 1383 for (;;) { 1384 left = pci_vendordata_size - (cp - pci_vendordata); 1385 if (left <= 0) { 1386 *ptr = cp; 1387 return(1); 1388 } 1389 1390 /* vendor entry? */ 1391 if (*cp != '\t' && 1392 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1393 break; 1394 /* device entry? */ 1395 if (*cp == '\t' && 1396 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1397 break; 1398 1399 /* skip to next line */ 1400 while (*cp != '\n' && left > 0) { 1401 cp++; 1402 left--; 1403 } 1404 if (*cp == '\n') { 1405 cp++; 1406 left--; 1407 } 1408 } 1409 /* skip to next line */ 1410 while (*cp != '\n' && left > 0) { 1411 cp++; 1412 left--; 1413 } 1414 if (*cp == '\n' && left > 0) 1415 cp++; 1416 *ptr = cp; 1417 return(0); 1418 } 1419 1420 static char * 1421 pci_describe_device(device_t dev) 1422 { 1423 int vendor, device; 1424 char *desc, *vp, *dp, *line; 1425 1426 desc = vp = dp = NULL; 1427 1428 /* 1429 * If we have no vendor data, we can't do anything. 1430 */ 1431 if (pci_vendordata == NULL) 1432 goto out; 1433 1434 /* 1435 * Scan the vendor data looking for this device 1436 */ 1437 line = pci_vendordata; 1438 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1439 goto out; 1440 for (;;) { 1441 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1442 goto out; 1443 if (vendor == pci_get_vendor(dev)) 1444 break; 1445 } 1446 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1447 goto out; 1448 for (;;) { 1449 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1450 *dp = 0; 1451 break; 1452 } 1453 if (vendor != -1) { 1454 *dp = 0; 1455 break; 1456 } 1457 if (device == pci_get_device(dev)) 1458 break; 1459 } 1460 if (dp[0] == '\0') 1461 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1462 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1463 NULL) 1464 sprintf(desc, "%s, %s", vp, dp); 1465 out: 1466 if (vp != NULL) 1467 free(vp, M_DEVBUF); 1468 if (dp != NULL) 1469 free(dp, M_DEVBUF); 1470 return(desc); 1471 } 1472 1473 int 1474 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1475 { 1476 struct pci_devinfo *dinfo; 1477 pcicfgregs *cfg; 1478 1479 dinfo = device_get_ivars(child); 1480 cfg = &dinfo->cfg; 1481 1482 switch (which) { 1483 case PCI_IVAR_ETHADDR: 1484 /* 1485 * The generic accessor doesn't deal with failure, so 1486 * we set the return value, then return an error. 1487 */ 1488 *((uint8_t **) result) = NULL; 1489 return (EINVAL); 1490 case PCI_IVAR_SUBVENDOR: 1491 *result = cfg->subvendor; 1492 break; 1493 case PCI_IVAR_SUBDEVICE: 1494 *result = cfg->subdevice; 1495 break; 1496 case PCI_IVAR_VENDOR: 1497 *result = cfg->vendor; 1498 break; 1499 case PCI_IVAR_DEVICE: 1500 *result = cfg->device; 1501 break; 1502 case PCI_IVAR_DEVID: 1503 *result = (cfg->device << 16) | cfg->vendor; 1504 break; 1505 case PCI_IVAR_CLASS: 1506 *result = cfg->baseclass; 1507 break; 1508 case PCI_IVAR_SUBCLASS: 1509 *result = cfg->subclass; 1510 break; 1511 case PCI_IVAR_PROGIF: 1512 *result = cfg->progif; 1513 break; 1514 case PCI_IVAR_REVID: 1515 *result = cfg->revid; 1516 break; 1517 case PCI_IVAR_INTPIN: 1518 *result = cfg->intpin; 1519 break; 1520 case PCI_IVAR_IRQ: 1521 *result = cfg->intline; 1522 break; 1523 case PCI_IVAR_BUS: 1524 *result = cfg->bus; 1525 break; 1526 case PCI_IVAR_SLOT: 1527 *result = cfg->slot; 1528 break; 1529 case PCI_IVAR_FUNCTION: 1530 *result = cfg->func; 1531 break; 1532 case PCI_IVAR_CMDREG: 1533 *result = cfg->cmdreg; 1534 break; 1535 case PCI_IVAR_CACHELNSZ: 1536 *result = cfg->cachelnsz; 1537 break; 1538 case PCI_IVAR_MINGNT: 1539 *result = cfg->mingnt; 1540 break; 1541 case PCI_IVAR_MAXLAT: 1542 *result = cfg->maxlat; 1543 break; 1544 case PCI_IVAR_LATTIMER: 1545 *result = cfg->lattimer; 1546 break; 1547 default: 1548 return (ENOENT); 1549 } 1550 return (0); 1551 } 1552 1553 int 1554 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1555 { 1556 struct pci_devinfo *dinfo; 1557 1558 dinfo = device_get_ivars(child); 1559 1560 switch (which) { 1561 case PCI_IVAR_INTPIN: 1562 dinfo->cfg.intpin = value; 1563 return (0); 1564 case PCI_IVAR_ETHADDR: 1565 case PCI_IVAR_SUBVENDOR: 1566 case PCI_IVAR_SUBDEVICE: 1567 case PCI_IVAR_VENDOR: 1568 case PCI_IVAR_DEVICE: 1569 case PCI_IVAR_DEVID: 1570 case PCI_IVAR_CLASS: 1571 case PCI_IVAR_SUBCLASS: 1572 case PCI_IVAR_PROGIF: 1573 case PCI_IVAR_REVID: 1574 case PCI_IVAR_IRQ: 1575 case PCI_IVAR_BUS: 1576 case PCI_IVAR_SLOT: 1577 case PCI_IVAR_FUNCTION: 1578 return (EINVAL); /* disallow for now */ 1579 1580 default: 1581 return (ENOENT); 1582 } 1583 } 1584 1585 1586 #include "opt_ddb.h" 1587 #ifdef DDB 1588 #include <ddb/ddb.h> 1589 #include <sys/cons.h> 1590 1591 /* 1592 * List resources based on pci map registers, used for within ddb 1593 */ 1594 1595 DB_SHOW_COMMAND(pciregs, db_pci_dump) 1596 { 1597 struct pci_devinfo *dinfo; 1598 struct devlist *devlist_head; 1599 struct pci_conf *p; 1600 const char *name; 1601 int i, error, none_count, quit; 1602 1603 none_count = 0; 1604 /* get the head of the device queue */ 1605 devlist_head = &pci_devq; 1606 1607 /* 1608 * Go through the list of devices and print out devices 1609 */ 1610 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 1611 for (error = 0, i = 0, quit = 0, 1612 dinfo = STAILQ_FIRST(devlist_head); 1613 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1614 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1615 1616 /* Populate pd_name and pd_unit */ 1617 name = NULL; 1618 if (dinfo->cfg.dev) 1619 name = device_get_name(dinfo->cfg.dev); 1620 1621 p = &dinfo->conf; 1622 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1623 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1624 (name && *name) ? name : "none", 1625 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1626 none_count++, 1627 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1628 p->pc_sel.pc_func, (p->pc_class << 16) | 1629 (p->pc_subclass << 8) | p->pc_progif, 1630 (p->pc_subdevice << 16) | p->pc_subvendor, 1631 (p->pc_device << 16) | p->pc_vendor, 1632 p->pc_revid, p->pc_hdr); 1633 } 1634 } 1635 #endif /* DDB */ 1636 1637 static struct resource * 1638 pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1639 u_long start, u_long end, u_long count, u_int flags) 1640 { 1641 struct pci_devinfo *dinfo = device_get_ivars(child); 1642 struct resource_list *rl = &dinfo->resources; 1643 struct resource_list_entry *rle; 1644 struct resource *res; 1645 uint32_t map, testval; 1646 int mapsize; 1647 1648 /* 1649 * Weed out the bogons, and figure out how large the BAR/map 1650 * is. Bars that read back 0 here are bogus and unimplemented. 1651 * Note: atapci in legacy mode are special and handled elsewhere 1652 * in the code. If you have a atapci device in legacy mode and 1653 * it fails here, that other code is broken. 1654 */ 1655 res = NULL; 1656 map = pci_read_config(child, *rid, 4); 1657 pci_write_config(child, *rid, 0xffffffff, 4); 1658 testval = pci_read_config(child, *rid, 4); 1659 if (pci_mapbase(testval) == 0) 1660 goto out; 1661 if (pci_maptype(testval) & PCI_MAPMEM) { 1662 if (type != SYS_RES_MEMORY) { 1663 if (bootverbose) 1664 device_printf(dev, 1665 "child %s requested type %d for rid %#x," 1666 " but the BAR says it is an memio\n", 1667 device_get_nameunit(child), type, *rid); 1668 goto out; 1669 } 1670 } else { 1671 if (type != SYS_RES_IOPORT) { 1672 if (bootverbose) 1673 device_printf(dev, 1674 "child %s requested type %d for rid %#x," 1675 " but the BAR says it is an ioport\n", 1676 device_get_nameunit(child), type, *rid); 1677 goto out; 1678 } 1679 } 1680 /* 1681 * For real BARs, we need to override the size that 1682 * the driver requests, because that's what the BAR 1683 * actually uses and we would otherwise have a 1684 * situation where we might allocate the excess to 1685 * another driver, which won't work. 1686 */ 1687 mapsize = pci_mapsize(testval); 1688 count = 1 << mapsize; 1689 if (RF_ALIGNMENT(flags) < mapsize) 1690 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1691 1692 /* 1693 * Allocate enough resource, and then write back the 1694 * appropriate bar for that resource. 1695 */ 1696 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1697 start, end, count, flags); 1698 if (res == NULL) { 1699 device_printf(child, "%#lx bytes of rid %#x res %d failed.\n", 1700 count, *rid, type); 1701 goto out; 1702 } 1703 resource_list_add(rl, type, *rid, start, end, count); 1704 rle = resource_list_find(rl, type, *rid); 1705 if (rle == NULL) 1706 panic("pci_alloc_map: unexpectedly can't find resource."); 1707 rle->res = res; 1708 if (bootverbose) 1709 device_printf(child, 1710 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1711 count, *rid, type, rman_get_start(res)); 1712 map = rman_get_start(res); 1713 out:; 1714 pci_write_config(child, *rid, map, 4); 1715 return (res); 1716 } 1717 1718 1719 struct resource * 1720 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1721 u_long start, u_long end, u_long count, u_int flags) 1722 { 1723 struct pci_devinfo *dinfo = device_get_ivars(child); 1724 struct resource_list *rl = &dinfo->resources; 1725 struct resource_list_entry *rle; 1726 pcicfgregs *cfg = &dinfo->cfg; 1727 1728 /* 1729 * Perform lazy resource allocation 1730 */ 1731 if (device_get_parent(child) == dev) { 1732 switch (type) { 1733 case SYS_RES_IRQ: 1734 /* 1735 * If the child device doesn't have an 1736 * interrupt routed and is deserving of an 1737 * interrupt, try to assign it one. 1738 */ 1739 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1740 (cfg->intpin != 0)) { 1741 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child); 1742 if (PCI_INTERRUPT_VALID(cfg->intline)) { 1743 pci_write_config(child, PCIR_INTLINE, 1744 cfg->intline, 1); 1745 resource_list_add(rl, SYS_RES_IRQ, 0, 1746 cfg->intline, cfg->intline, 1); 1747 } 1748 } 1749 break; 1750 case SYS_RES_IOPORT: 1751 case SYS_RES_MEMORY: 1752 if (*rid < PCIR_BAR(cfg->nummaps)) { 1753 /* 1754 * Enable the I/O mode. We should 1755 * also be assigning resources too 1756 * when none are present. The 1757 * resource_list_alloc kind of sorta does 1758 * this... 1759 */ 1760 if (PCI_ENABLE_IO(dev, child, type)) 1761 return (NULL); 1762 } 1763 rle = resource_list_find(rl, type, *rid); 1764 if (rle == NULL) 1765 return (pci_alloc_map(dev, child, type, rid, 1766 start, end, count, flags)); 1767 break; 1768 } 1769 /* 1770 * If we've already allocated the resource, then 1771 * return it now. But first we may need to activate 1772 * it, since we don't allocate the resource as active 1773 * above. Normally this would be done down in the 1774 * nexus, but since we short-circuit that path we have 1775 * to do its job here. Not sure if we should free the 1776 * resource if it fails to activate. 1777 */ 1778 rle = resource_list_find(rl, type, *rid); 1779 if (rle != NULL && rle->res != NULL) { 1780 if (bootverbose) 1781 device_printf(child, 1782 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 1783 rman_get_size(rle->res), *rid, type, 1784 rman_get_start(rle->res)); 1785 if ((flags & RF_ACTIVE) && 1786 bus_generic_activate_resource(dev, child, type, 1787 *rid, rle->res) != 0) 1788 return NULL; 1789 return (rle->res); 1790 } 1791 } 1792 return (resource_list_alloc(rl, dev, child, type, rid, 1793 start, end, count, flags)); 1794 } 1795 1796 void 1797 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1798 { 1799 struct pci_devinfo *dinfo; 1800 struct resource_list *rl; 1801 struct resource_list_entry *rle; 1802 1803 if (device_get_parent(child) != dev) 1804 return; 1805 1806 dinfo = device_get_ivars(child); 1807 rl = &dinfo->resources; 1808 rle = resource_list_find(rl, type, rid); 1809 if (rle) { 1810 if (rle->res) { 1811 if (rman_get_device(rle->res) != dev || 1812 rman_get_flags(rle->res) & RF_ACTIVE) { 1813 device_printf(dev, "delete_resource: " 1814 "Resource still owned by child, oops. " 1815 "(type=%d, rid=%d, addr=%lx)\n", 1816 rle->type, rle->rid, 1817 rman_get_start(rle->res)); 1818 return; 1819 } 1820 bus_release_resource(dev, type, rid, rle->res); 1821 } 1822 resource_list_delete(rl, type, rid); 1823 } 1824 /* 1825 * Why do we turn off the PCI configuration BAR when we delete a 1826 * resource? -- imp 1827 */ 1828 pci_write_config(child, rid, 0, 4); 1829 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1830 } 1831 1832 struct resource_list * 1833 pci_get_resource_list (device_t dev, device_t child) 1834 { 1835 struct pci_devinfo *dinfo = device_get_ivars(child); 1836 1837 return (&dinfo->resources); 1838 } 1839 1840 uint32_t 1841 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1842 { 1843 struct pci_devinfo *dinfo = device_get_ivars(child); 1844 pcicfgregs *cfg = &dinfo->cfg; 1845 1846 return (PCIB_READ_CONFIG(device_get_parent(dev), 1847 cfg->bus, cfg->slot, cfg->func, reg, width)); 1848 } 1849 1850 void 1851 pci_write_config_method(device_t dev, device_t child, int reg, 1852 uint32_t val, int width) 1853 { 1854 struct pci_devinfo *dinfo = device_get_ivars(child); 1855 pcicfgregs *cfg = &dinfo->cfg; 1856 1857 PCIB_WRITE_CONFIG(device_get_parent(dev), 1858 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1859 } 1860 1861 int 1862 pci_child_location_str_method(device_t dev, device_t child, char *buf, 1863 size_t buflen) 1864 { 1865 1866 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1867 pci_get_function(child)); 1868 return (0); 1869 } 1870 1871 int 1872 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1873 size_t buflen) 1874 { 1875 struct pci_devinfo *dinfo; 1876 pcicfgregs *cfg; 1877 1878 dinfo = device_get_ivars(child); 1879 cfg = &dinfo->cfg; 1880 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1881 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1882 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1883 cfg->progif); 1884 return (0); 1885 } 1886 1887 int 1888 pci_assign_interrupt_method(device_t dev, device_t child) 1889 { 1890 struct pci_devinfo *dinfo = device_get_ivars(child); 1891 pcicfgregs *cfg = &dinfo->cfg; 1892 1893 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1894 cfg->intpin)); 1895 } 1896 1897 static int 1898 pci_modevent(module_t mod, int what, void *arg) 1899 { 1900 static struct cdev *pci_cdev; 1901 1902 switch (what) { 1903 case MOD_LOAD: 1904 STAILQ_INIT(&pci_devq); 1905 pci_generation = 0; 1906 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 1907 "pci"); 1908 pci_load_vendor_data(); 1909 break; 1910 1911 case MOD_UNLOAD: 1912 destroy_dev(pci_cdev); 1913 break; 1914 } 1915 1916 return (0); 1917 } 1918 1919 void 1920 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 1921 { 1922 int i; 1923 1924 /* 1925 * Only do header type 0 devices. Type 1 devices are bridges, 1926 * which we know need special treatment. Type 2 devices are 1927 * cardbus bridges which also require special treatment. 1928 * Other types are unknown, and we err on the side of safety 1929 * by ignoring them. 1930 */ 1931 if (dinfo->cfg.hdrtype != 0) 1932 return; 1933 1934 /* 1935 * Restore the device to full power mode. We must do this 1936 * before we restore the registers because moving from D3 to 1937 * D0 will cause the chip's BARs and some other registers to 1938 * be reset to some unknown power on reset values. Cut down 1939 * the noise on boot by doing nothing if we are already in 1940 * state D0. 1941 */ 1942 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1943 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1944 } 1945 for (i = 0; i < dinfo->cfg.nummaps; i++) 1946 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 1947 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 1948 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 1949 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 1950 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 1951 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 1952 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 1953 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 1954 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 1955 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 1956 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 1957 } 1958 1959 void 1960 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 1961 { 1962 int i; 1963 uint32_t cls; 1964 int ps; 1965 1966 /* 1967 * Only do header type 0 devices. Type 1 devices are bridges, which 1968 * we know need special treatment. Type 2 devices are cardbus bridges 1969 * which also require special treatment. Other types are unknown, and 1970 * we err on the side of safety by ignoring them. Powering down 1971 * bridges should not be undertaken lightly. 1972 */ 1973 if (dinfo->cfg.hdrtype != 0) 1974 return; 1975 for (i = 0; i < dinfo->cfg.nummaps; i++) 1976 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 1977 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 1978 1979 /* 1980 * Some drivers apparently write to these registers w/o updating our 1981 * cached copy. No harm happens if we update the copy, so do so here 1982 * so we can restore them. The COMMAND register is modified by the 1983 * bus w/o updating the cache. This should represent the normally 1984 * writable portion of the 'defined' part of type 0 headers. In 1985 * theory we also need to save/restore the PCI capability structures 1986 * we know about, but apart from power we don't know any that are 1987 * writable. 1988 */ 1989 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 1990 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 1991 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 1992 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 1993 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 1994 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 1995 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 1996 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 1997 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 1998 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1999 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2000 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 2001 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 2002 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 2003 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 2004 2005 /* 2006 * don't set the state for display devices, base peripherals and 2007 * memory devices since bad things happen when they are powered down. 2008 * We should (a) have drivers that can easily detach and (b) use 2009 * generic drivers for these devices so that some device actually 2010 * attaches. We need to make sure that when we implement (a) we don't 2011 * power the device down on a reattach. 2012 */ 2013 cls = pci_get_class(dev); 2014 if (!setstate) 2015 return; 2016 switch (pci_do_power_nodriver) 2017 { 2018 case 0: /* NO powerdown at all */ 2019 return; 2020 case 1: /* Conservative about what to power down */ 2021 if (cls == PCIC_STORAGE) 2022 return; 2023 /*FALLTHROUGH*/ 2024 case 2: /* Agressive about what to power down */ 2025 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 2026 cls == PCIC_BASEPERIPH) 2027 return; 2028 /*FALLTHROUGH*/ 2029 case 3: /* Power down everything */ 2030 break; 2031 } 2032 /* 2033 * PCI spec says we can only go into D3 state from D0 state. 2034 * Transition from D[12] into D0 before going to D3 state. 2035 */ 2036 ps = pci_get_powerstate(dev); 2037 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 2038 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2039 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 2040 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 2041 } 2042