1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 5 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000, BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice unmodified, this list of conditions, and the following 14 * disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 #include "opt_acpi.h" 33 #include "opt_iommu.h" 34 #include "opt_bus.h" 35 36 #include <sys/param.h> 37 #include <sys/conf.h> 38 #include <sys/endian.h> 39 #include <sys/eventhandler.h> 40 #include <sys/fcntl.h> 41 #include <sys/kernel.h> 42 #include <sys/limits.h> 43 #include <sys/linker.h> 44 #include <sys/malloc.h> 45 #include <sys/module.h> 46 #include <sys/queue.h> 47 #include <sys/sbuf.h> 48 #include <sys/sysctl.h> 49 #include <sys/systm.h> 50 #include <sys/taskqueue.h> 51 #include <sys/tree.h> 52 53 #include <vm/vm.h> 54 #include <vm/pmap.h> 55 #include <vm/vm_extern.h> 56 57 #include <sys/bus.h> 58 #include <machine/bus.h> 59 #include <sys/rman.h> 60 #include <machine/resource.h> 61 #include <machine/stdarg.h> 62 63 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 64 #include <machine/intr_machdep.h> 65 #endif 66 67 #include <sys/pciio.h> 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pci_private.h> 71 72 #ifdef PCI_IOV 73 #include <sys/nv.h> 74 #include <dev/pci/pci_iov_private.h> 75 #endif 76 77 #include <dev/usb/controller/xhcireg.h> 78 #include <dev/usb/controller/ehcireg.h> 79 #include <dev/usb/controller/ohcireg.h> 80 #include <dev/usb/controller/uhcireg.h> 81 82 #include <dev/iommu/iommu.h> 83 84 #include "pcib_if.h" 85 #include "pci_if.h" 86 87 #define PCIR_IS_BIOS(cfg, reg) \ 88 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ 89 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) 90 91 static device_probe_t pci_probe; 92 93 static bus_reset_post_t pci_reset_post; 94 static bus_reset_prepare_t pci_reset_prepare; 95 static bus_reset_child_t pci_reset_child; 96 static bus_hint_device_unit_t pci_hint_device_unit; 97 static bus_remap_intr_t pci_remap_intr_method; 98 99 static pci_get_id_t pci_get_id_method; 100 101 static int pci_has_quirk(uint32_t devid, int quirk); 102 static pci_addr_t pci_mapbase(uint64_t mapreg); 103 static const char *pci_maptype(uint64_t mapreg); 104 static int pci_maprange(uint64_t mapreg); 105 static pci_addr_t pci_rombase(uint64_t mapreg); 106 static int pci_romsize(uint64_t testval); 107 static void pci_fixancient(pcicfgregs *cfg); 108 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...); 109 110 static int pci_porten(device_t dev); 111 static int pci_memen(device_t dev); 112 static void pci_assign_interrupt(device_t bus, device_t dev, 113 int force_route); 114 static int pci_add_map(device_t bus, device_t dev, int reg, 115 struct resource_list *rl, int force, int prefetch); 116 static void pci_load_vendor_data(void); 117 static int pci_describe_parse_line(char **ptr, int *vendor, 118 int *device, char **desc); 119 static char *pci_describe_device(device_t dev); 120 static int pci_modevent(module_t mod, int what, void *arg); 121 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 122 pcicfgregs *cfg); 123 static void pci_read_cap(device_t pcib, pcicfgregs *cfg); 124 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 125 int reg, uint32_t *data); 126 #if 0 127 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 128 int reg, uint32_t data); 129 #endif 130 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 131 static void pci_mask_msix(device_t dev, u_int index); 132 static void pci_unmask_msix(device_t dev, u_int index); 133 static int pci_msi_blacklisted(void); 134 static int pci_msix_blacklisted(void); 135 static void pci_resume_msi(device_t dev); 136 static void pci_resume_msix(device_t dev); 137 static struct pci_devinfo * pci_fill_devinfo(device_t pcib, device_t bus, int d, 138 int b, int s, int f, uint16_t vid, uint16_t did); 139 140 static device_method_t pci_methods[] = { 141 /* Device interface */ 142 DEVMETHOD(device_probe, pci_probe), 143 DEVMETHOD(device_attach, pci_attach), 144 DEVMETHOD(device_detach, pci_detach), 145 DEVMETHOD(device_shutdown, bus_generic_shutdown), 146 DEVMETHOD(device_suspend, bus_generic_suspend), 147 DEVMETHOD(device_resume, pci_resume), 148 149 /* Bus interface */ 150 DEVMETHOD(bus_print_child, pci_print_child), 151 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 152 DEVMETHOD(bus_read_ivar, pci_read_ivar), 153 DEVMETHOD(bus_write_ivar, pci_write_ivar), 154 DEVMETHOD(bus_driver_added, pci_driver_added), 155 DEVMETHOD(bus_setup_intr, pci_setup_intr), 156 DEVMETHOD(bus_teardown_intr, pci_teardown_intr), 157 DEVMETHOD(bus_reset_prepare, pci_reset_prepare), 158 DEVMETHOD(bus_reset_post, pci_reset_post), 159 DEVMETHOD(bus_reset_child, pci_reset_child), 160 161 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag), 162 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 163 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 164 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 165 DEVMETHOD(bus_delete_resource, pci_delete_resource), 166 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 167 DEVMETHOD(bus_adjust_resource, pci_adjust_resource), 168 DEVMETHOD(bus_release_resource, pci_release_resource), 169 DEVMETHOD(bus_activate_resource, pci_activate_resource), 170 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource), 171 DEVMETHOD(bus_map_resource, pci_map_resource), 172 DEVMETHOD(bus_unmap_resource, pci_unmap_resource), 173 DEVMETHOD(bus_child_deleted, pci_child_deleted), 174 DEVMETHOD(bus_child_detached, pci_child_detached), 175 DEVMETHOD(bus_child_pnpinfo, pci_child_pnpinfo_method), 176 DEVMETHOD(bus_child_location, pci_child_location_method), 177 DEVMETHOD(bus_get_device_path, pci_get_device_path_method), 178 DEVMETHOD(bus_hint_device_unit, pci_hint_device_unit), 179 DEVMETHOD(bus_remap_intr, pci_remap_intr_method), 180 DEVMETHOD(bus_suspend_child, pci_suspend_child), 181 DEVMETHOD(bus_resume_child, pci_resume_child), 182 DEVMETHOD(bus_rescan, pci_rescan_method), 183 184 /* PCI interface */ 185 DEVMETHOD(pci_read_config, pci_read_config_method), 186 DEVMETHOD(pci_write_config, pci_write_config_method), 187 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 188 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 189 DEVMETHOD(pci_enable_io, pci_enable_io_method), 190 DEVMETHOD(pci_disable_io, pci_disable_io_method), 191 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 192 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 193 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 194 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 195 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 196 DEVMETHOD(pci_find_cap, pci_find_cap_method), 197 DEVMETHOD(pci_find_next_cap, pci_find_next_cap_method), 198 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 199 DEVMETHOD(pci_find_next_extcap, pci_find_next_extcap_method), 200 DEVMETHOD(pci_find_htcap, pci_find_htcap_method), 201 DEVMETHOD(pci_find_next_htcap, pci_find_next_htcap_method), 202 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 203 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), 204 DEVMETHOD(pci_enable_msi, pci_enable_msi_method), 205 DEVMETHOD(pci_enable_msix, pci_enable_msix_method), 206 DEVMETHOD(pci_disable_msi, pci_disable_msi_method), 207 DEVMETHOD(pci_remap_msix, pci_remap_msix_method), 208 DEVMETHOD(pci_release_msi, pci_release_msi_method), 209 DEVMETHOD(pci_msi_count, pci_msi_count_method), 210 DEVMETHOD(pci_msix_count, pci_msix_count_method), 211 DEVMETHOD(pci_msix_pba_bar, pci_msix_pba_bar_method), 212 DEVMETHOD(pci_msix_table_bar, pci_msix_table_bar_method), 213 DEVMETHOD(pci_get_id, pci_get_id_method), 214 DEVMETHOD(pci_alloc_devinfo, pci_alloc_devinfo_method), 215 DEVMETHOD(pci_child_added, pci_child_added_method), 216 #ifdef PCI_IOV 217 DEVMETHOD(pci_iov_attach, pci_iov_attach_method), 218 DEVMETHOD(pci_iov_detach, pci_iov_detach_method), 219 DEVMETHOD(pci_create_iov_child, pci_create_iov_child_method), 220 #endif 221 222 DEVMETHOD_END 223 }; 224 225 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc)); 226 227 EARLY_DRIVER_MODULE(pci, pcib, pci_driver, pci_modevent, NULL, BUS_PASS_BUS); 228 MODULE_VERSION(pci, 1); 229 230 static char *pci_vendordata; 231 static size_t pci_vendordata_size; 232 233 struct pci_quirk { 234 uint32_t devid; /* Vendor/device of the card */ 235 int type; 236 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 237 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */ 238 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */ 239 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */ 240 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */ 241 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */ 242 #define PCI_QUIRK_REALLOC_BAR 7 /* Can't allocate memory at the default address */ 243 int arg1; 244 int arg2; 245 }; 246 247 static const struct pci_quirk pci_quirks[] = { 248 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */ 249 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 250 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 251 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 252 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 253 254 /* 255 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge 256 * or the CMIC-SL (AKA ServerWorks GC_LE). 257 */ 258 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 259 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 260 261 /* 262 * MSI doesn't work on earlier Intel chipsets including 263 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855. 264 */ 265 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 266 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 267 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 268 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 269 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 270 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 271 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 272 273 /* 274 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX 275 * bridge. 276 */ 277 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 278 279 /* 280 * Some virtualization environments emulate an older chipset 281 * but support MSI just fine. QEMU uses the Intel 82440. 282 */ 283 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 }, 284 285 /* 286 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus 287 * controller depending on SoftPciRst register (PM_IO 0x55 [7]). 288 * It prevents us from attaching hpet(4) when the bit is unset. 289 * Note this quirk only affects SB600 revision A13 and earlier. 290 * For SB600 A21 and later, firmware must set the bit to hide it. 291 * For SB700 and later, it is unused and hardcoded to zero. 292 */ 293 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 }, 294 295 /* 296 * Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have 297 * a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit 298 * of the command register is set. 299 */ 300 { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 301 { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 302 { 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 303 { 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 304 { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 305 306 /* 307 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't 308 * issue MSI interrupts with PCIM_CMD_INTxDIS set either. 309 */ 310 { 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */ 311 { 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */ 312 { 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */ 313 { 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */ 314 { 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */ 315 { 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */ 316 317 /* 318 * HPE Gen 10 VGA has a memory range that can't be allocated in the 319 * expected place. 320 */ 321 { 0x98741002, PCI_QUIRK_REALLOC_BAR, 0, 0 }, 322 { 0 } 323 }; 324 325 /* map register information */ 326 #define PCI_MAPMEM 0x01 /* memory map */ 327 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 328 #define PCI_MAPPORT 0x04 /* port map */ 329 330 struct devlist pci_devq; 331 uint32_t pci_generation; 332 uint32_t pci_numdevs = 0; 333 static int pcie_chipset, pcix_chipset; 334 335 /* sysctl vars */ 336 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 337 "PCI bus tuning parameters"); 338 339 static int pci_enable_io_modes = 1; 340 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RWTUN, 341 &pci_enable_io_modes, 1, 342 "Enable I/O and memory bits in the config register. Some BIOSes do not" 343 " enable these bits correctly. We'd like to do this all the time, but" 344 " there are some peripherals that this causes problems with."); 345 346 static int pci_do_realloc_bars = 1; 347 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RWTUN, 348 &pci_do_realloc_bars, 0, 349 "Attempt to allocate a new range for any BARs whose original " 350 "firmware-assigned ranges fail to allocate during the initial device scan."); 351 352 static int pci_do_power_nodriver = 0; 353 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RWTUN, 354 &pci_do_power_nodriver, 0, 355 "Place a function into D3 state when no driver attaches to it. 0 means" 356 " disable. 1 means conservatively place function into D3 state. 2 means" 357 " aggressively place function into D3 state. 3 means put absolutely" 358 " everything in D3 state."); 359 360 int pci_do_power_resume = 1; 361 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RWTUN, 362 &pci_do_power_resume, 1, 363 "Transition from D3 -> D0 on resume."); 364 365 int pci_do_power_suspend = 1; 366 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RWTUN, 367 &pci_do_power_suspend, 1, 368 "Transition from D0 -> D3 on suspend."); 369 370 static int pci_do_msi = 1; 371 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RWTUN, &pci_do_msi, 1, 372 "Enable support for MSI interrupts"); 373 374 static int pci_do_msix = 1; 375 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RWTUN, &pci_do_msix, 1, 376 "Enable support for MSI-X interrupts"); 377 378 static int pci_msix_rewrite_table = 0; 379 SYSCTL_INT(_hw_pci, OID_AUTO, msix_rewrite_table, CTLFLAG_RWTUN, 380 &pci_msix_rewrite_table, 0, 381 "Rewrite entire MSI-X table when updating MSI-X entries"); 382 383 static int pci_honor_msi_blacklist = 1; 384 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RDTUN, 385 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X"); 386 387 #if defined(__i386__) || defined(__amd64__) 388 static int pci_usb_takeover = 1; 389 #else 390 static int pci_usb_takeover = 0; 391 #endif 392 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN, 393 &pci_usb_takeover, 1, 394 "Enable early takeover of USB controllers. Disable this if you depend on" 395 " BIOS emulation of USB devices, that is you use USB devices (like" 396 " keyboard or mouse) but do not load USB drivers"); 397 398 static int pci_clear_bars; 399 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0, 400 "Ignore firmware-assigned resources for BARs."); 401 402 static int pci_clear_buses; 403 SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0, 404 "Ignore firmware-assigned bus numbers."); 405 406 static int pci_enable_ari = 1; 407 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari, 408 0, "Enable support for PCIe Alternative RID Interpretation"); 409 410 /* 411 * Some x86 firmware only enables PCIe hotplug if we claim to support aspm, 412 * however enabling it breaks some arm64 firmware as it powers off devices. 413 */ 414 #if defined(__i386__) || defined(__amd64__) 415 int pci_enable_aspm = 1; 416 #else 417 int pci_enable_aspm = 0; 418 #endif 419 SYSCTL_INT(_hw_pci, OID_AUTO, enable_aspm, CTLFLAG_RDTUN, &pci_enable_aspm, 420 0, "Enable support for PCIe Active State Power Management"); 421 422 static int pci_clear_aer_on_attach = 0; 423 SYSCTL_INT(_hw_pci, OID_AUTO, clear_aer_on_attach, CTLFLAG_RWTUN, 424 &pci_clear_aer_on_attach, 0, 425 "Clear port and device AER state on driver attach"); 426 427 static bool pci_enable_mps_tune = true; 428 SYSCTL_BOOL(_hw_pci, OID_AUTO, enable_mps_tune, CTLFLAG_RWTUN, 429 &pci_enable_mps_tune, 1, 430 "Enable tuning of MPS(maximum payload size)." ); 431 432 static int 433 pci_has_quirk(uint32_t devid, int quirk) 434 { 435 const struct pci_quirk *q; 436 437 for (q = &pci_quirks[0]; q->devid; q++) { 438 if (q->devid == devid && q->type == quirk) 439 return (1); 440 } 441 return (0); 442 } 443 444 /* Find a device_t by bus/slot/function in domain 0 */ 445 446 device_t 447 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 448 { 449 450 return (pci_find_dbsf(0, bus, slot, func)); 451 } 452 453 /* Find a device_t by domain/bus/slot/function */ 454 455 device_t 456 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func) 457 { 458 struct pci_devinfo *dinfo = NULL; 459 460 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 461 if ((dinfo->cfg.domain == domain) && 462 (dinfo->cfg.bus == bus) && 463 (dinfo->cfg.slot == slot) && 464 (dinfo->cfg.func == func)) { 465 break; 466 } 467 } 468 469 return (dinfo != NULL ? dinfo->cfg.dev : NULL); 470 } 471 472 /* Find a device_t by vendor/device ID */ 473 474 device_t 475 pci_find_device(uint16_t vendor, uint16_t device) 476 { 477 struct pci_devinfo *dinfo; 478 479 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 480 if ((dinfo->cfg.vendor == vendor) && 481 (dinfo->cfg.device == device)) { 482 return (dinfo->cfg.dev); 483 } 484 } 485 486 return (NULL); 487 } 488 489 device_t 490 pci_find_class(uint8_t class, uint8_t subclass) 491 { 492 struct pci_devinfo *dinfo; 493 494 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 495 if (dinfo->cfg.baseclass == class && 496 dinfo->cfg.subclass == subclass) { 497 return (dinfo->cfg.dev); 498 } 499 } 500 501 return (NULL); 502 } 503 504 device_t 505 pci_find_class_from(uint8_t class, uint8_t subclass, device_t from) 506 { 507 struct pci_devinfo *dinfo; 508 bool found = false; 509 510 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 511 if (from != NULL && found == false) { 512 if (from != dinfo->cfg.dev) 513 continue; 514 found = true; 515 continue; 516 } 517 if (dinfo->cfg.baseclass == class && 518 dinfo->cfg.subclass == subclass) { 519 return (dinfo->cfg.dev); 520 } 521 } 522 523 return (NULL); 524 } 525 526 device_t 527 pci_find_base_class_from(uint8_t class, device_t from) 528 { 529 struct pci_devinfo *dinfo; 530 bool found = false; 531 532 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 533 if (from != NULL && found == false) { 534 if (from != dinfo->cfg.dev) 535 continue; 536 found = true; 537 continue; 538 } 539 if (dinfo->cfg.baseclass == class) { 540 return (dinfo->cfg.dev); 541 } 542 } 543 544 return (NULL); 545 } 546 547 static int 548 pci_printf(pcicfgregs *cfg, const char *fmt, ...) 549 { 550 va_list ap; 551 int retval; 552 553 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, 554 cfg->func); 555 va_start(ap, fmt); 556 retval += vprintf(fmt, ap); 557 va_end(ap); 558 return (retval); 559 } 560 561 /* return base address of memory or port map */ 562 563 static pci_addr_t 564 pci_mapbase(uint64_t mapreg) 565 { 566 567 if (PCI_BAR_MEM(mapreg)) 568 return (mapreg & PCIM_BAR_MEM_BASE); 569 else 570 return (mapreg & PCIM_BAR_IO_BASE); 571 } 572 573 /* return map type of memory or port map */ 574 575 static const char * 576 pci_maptype(uint64_t mapreg) 577 { 578 579 if (PCI_BAR_IO(mapreg)) 580 return ("I/O Port"); 581 if (mapreg & PCIM_BAR_MEM_PREFETCH) 582 return ("Prefetchable Memory"); 583 return ("Memory"); 584 } 585 586 /* return log2 of map size decoded for memory or port map */ 587 588 int 589 pci_mapsize(uint64_t testval) 590 { 591 int ln2size; 592 593 testval = pci_mapbase(testval); 594 ln2size = 0; 595 if (testval != 0) { 596 while ((testval & 1) == 0) 597 { 598 ln2size++; 599 testval >>= 1; 600 } 601 } 602 return (ln2size); 603 } 604 605 /* return base address of device ROM */ 606 607 static pci_addr_t 608 pci_rombase(uint64_t mapreg) 609 { 610 611 return (mapreg & PCIM_BIOS_ADDR_MASK); 612 } 613 614 /* return log2 of map size decided for device ROM */ 615 616 static int 617 pci_romsize(uint64_t testval) 618 { 619 int ln2size; 620 621 testval = pci_rombase(testval); 622 ln2size = 0; 623 if (testval != 0) { 624 while ((testval & 1) == 0) 625 { 626 ln2size++; 627 testval >>= 1; 628 } 629 } 630 return (ln2size); 631 } 632 633 /* return log2 of address range supported by map register */ 634 635 static int 636 pci_maprange(uint64_t mapreg) 637 { 638 int ln2range = 0; 639 640 if (PCI_BAR_IO(mapreg)) 641 ln2range = 32; 642 else 643 switch (mapreg & PCIM_BAR_MEM_TYPE) { 644 case PCIM_BAR_MEM_32: 645 ln2range = 32; 646 break; 647 case PCIM_BAR_MEM_1MB: 648 ln2range = 20; 649 break; 650 case PCIM_BAR_MEM_64: 651 ln2range = 64; 652 break; 653 } 654 return (ln2range); 655 } 656 657 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 658 659 static void 660 pci_fixancient(pcicfgregs *cfg) 661 { 662 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 663 return; 664 665 /* PCI to PCI bridges use header type 1 */ 666 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 667 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; 668 } 669 670 /* extract header type specific config data */ 671 672 static void 673 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 674 { 675 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 676 switch (cfg->hdrtype & PCIM_HDRTYPE) { 677 case PCIM_HDRTYPE_NORMAL: 678 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 679 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 680 cfg->mingnt = REG(PCIR_MINGNT, 1); 681 cfg->maxlat = REG(PCIR_MAXLAT, 1); 682 cfg->nummaps = PCI_MAXMAPS_0; 683 break; 684 case PCIM_HDRTYPE_BRIDGE: 685 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1); 686 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1); 687 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1); 688 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1); 689 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2); 690 cfg->nummaps = PCI_MAXMAPS_1; 691 break; 692 case PCIM_HDRTYPE_CARDBUS: 693 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1); 694 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1); 695 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1); 696 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1); 697 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2); 698 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 699 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 700 cfg->nummaps = PCI_MAXMAPS_2; 701 break; 702 } 703 #undef REG 704 } 705 706 /* read configuration header into pcicfgregs structure */ 707 struct pci_devinfo * 708 pci_read_device(device_t pcib, device_t bus, int d, int b, int s, int f) 709 { 710 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 711 uint16_t vid, did; 712 713 vid = REG(PCIR_VENDOR, 2); 714 if (vid == PCIV_INVALID) 715 return (NULL); 716 717 did = REG(PCIR_DEVICE, 2); 718 719 return (pci_fill_devinfo(pcib, bus, d, b, s, f, vid, did)); 720 } 721 722 struct pci_devinfo * 723 pci_alloc_devinfo_method(device_t dev) 724 { 725 726 return (malloc(sizeof(struct pci_devinfo), M_DEVBUF, 727 M_WAITOK | M_ZERO)); 728 } 729 730 static struct pci_devinfo * 731 pci_fill_devinfo(device_t pcib, device_t bus, int d, int b, int s, int f, 732 uint16_t vid, uint16_t did) 733 { 734 struct pci_devinfo *devlist_entry; 735 pcicfgregs *cfg; 736 737 devlist_entry = PCI_ALLOC_DEVINFO(bus); 738 739 cfg = &devlist_entry->cfg; 740 741 cfg->domain = d; 742 cfg->bus = b; 743 cfg->slot = s; 744 cfg->func = f; 745 cfg->vendor = vid; 746 cfg->device = did; 747 cfg->cmdreg = REG(PCIR_COMMAND, 2); 748 cfg->statreg = REG(PCIR_STATUS, 2); 749 cfg->baseclass = REG(PCIR_CLASS, 1); 750 cfg->subclass = REG(PCIR_SUBCLASS, 1); 751 cfg->progif = REG(PCIR_PROGIF, 1); 752 cfg->revid = REG(PCIR_REVID, 1); 753 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 754 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 755 cfg->lattimer = REG(PCIR_LATTIMER, 1); 756 cfg->intpin = REG(PCIR_INTPIN, 1); 757 cfg->intline = REG(PCIR_INTLINE, 1); 758 759 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 760 cfg->hdrtype &= ~PCIM_MFDEV; 761 STAILQ_INIT(&cfg->maps); 762 763 cfg->iov = NULL; 764 765 pci_fixancient(cfg); 766 pci_hdrtypedata(pcib, b, s, f, cfg); 767 768 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 769 pci_read_cap(pcib, cfg); 770 771 STAILQ_INSERT_TAIL(&pci_devq, devlist_entry, pci_links); 772 773 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; 774 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 775 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 776 devlist_entry->conf.pc_sel.pc_func = cfg->func; 777 devlist_entry->conf.pc_hdr = cfg->hdrtype; 778 779 devlist_entry->conf.pc_subvendor = cfg->subvendor; 780 devlist_entry->conf.pc_subdevice = cfg->subdevice; 781 devlist_entry->conf.pc_vendor = cfg->vendor; 782 devlist_entry->conf.pc_device = cfg->device; 783 784 devlist_entry->conf.pc_class = cfg->baseclass; 785 devlist_entry->conf.pc_subclass = cfg->subclass; 786 devlist_entry->conf.pc_progif = cfg->progif; 787 devlist_entry->conf.pc_revid = cfg->revid; 788 789 pci_numdevs++; 790 pci_generation++; 791 792 return (devlist_entry); 793 } 794 #undef REG 795 796 static void 797 pci_ea_fill_info(device_t pcib, pcicfgregs *cfg) 798 { 799 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \ 800 cfg->ea.ea_location + (n), w) 801 int num_ent; 802 int ptr; 803 int a, b; 804 uint32_t val; 805 int ent_size; 806 uint32_t dw[4]; 807 uint64_t base, max_offset; 808 struct pci_ea_entry *eae; 809 810 if (cfg->ea.ea_location == 0) 811 return; 812 813 STAILQ_INIT(&cfg->ea.ea_entries); 814 815 /* Determine the number of entries */ 816 num_ent = REG(PCIR_EA_NUM_ENT, 2); 817 num_ent &= PCIM_EA_NUM_ENT_MASK; 818 819 /* Find the first entry to care of */ 820 ptr = PCIR_EA_FIRST_ENT; 821 822 /* Skip DWORD 2 for type 1 functions */ 823 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) 824 ptr += 4; 825 826 for (a = 0; a < num_ent; a++) { 827 eae = malloc(sizeof(*eae), M_DEVBUF, M_WAITOK | M_ZERO); 828 eae->eae_cfg_offset = cfg->ea.ea_location + ptr; 829 830 /* Read a number of dwords in the entry */ 831 val = REG(ptr, 4); 832 ptr += 4; 833 ent_size = (val & PCIM_EA_ES); 834 835 for (b = 0; b < ent_size; b++) { 836 dw[b] = REG(ptr, 4); 837 ptr += 4; 838 } 839 840 eae->eae_flags = val; 841 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 842 843 base = dw[0] & PCIM_EA_FIELD_MASK; 844 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 845 b = 2; 846 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 847 base |= (uint64_t)dw[b] << 32UL; 848 b++; 849 } 850 if (((dw[1] & PCIM_EA_IS_64) != 0) 851 && (b < ent_size)) { 852 max_offset |= (uint64_t)dw[b] << 32UL; 853 b++; 854 } 855 856 eae->eae_base = base; 857 eae->eae_max_offset = max_offset; 858 859 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link); 860 861 if (bootverbose) { 862 printf("PCI(EA) dev %04x:%04x, bei %d, flags #%x, base #%jx, max_offset #%jx\n", 863 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags, 864 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset); 865 } 866 } 867 } 868 #undef REG 869 870 static void 871 pci_read_cap(device_t pcib, pcicfgregs *cfg) 872 { 873 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 874 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 875 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 876 uint64_t addr; 877 #endif 878 uint32_t val; 879 int ptr, nextptr, ptrptr; 880 881 switch (cfg->hdrtype & PCIM_HDRTYPE) { 882 case PCIM_HDRTYPE_NORMAL: 883 case PCIM_HDRTYPE_BRIDGE: 884 ptrptr = PCIR_CAP_PTR; 885 break; 886 case PCIM_HDRTYPE_CARDBUS: 887 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 888 break; 889 default: 890 return; /* no extended capabilities support */ 891 } 892 nextptr = REG(ptrptr, 1); /* sanity check? */ 893 894 /* 895 * Read capability entries. 896 */ 897 while (nextptr != 0) { 898 /* Sanity check */ 899 if (nextptr > 255) { 900 printf("illegal PCI extended capability offset %d\n", 901 nextptr); 902 return; 903 } 904 /* Find the next entry */ 905 ptr = nextptr; 906 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 907 908 /* Process this entry */ 909 switch (REG(ptr + PCICAP_ID, 1)) { 910 case PCIY_PMG: /* PCI power management */ 911 if (cfg->pp.pp_cap == 0) { 912 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 913 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 914 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE; 915 if ((nextptr - ptr) > PCIR_POWER_DATA) 916 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 917 } 918 break; 919 case PCIY_HT: /* HyperTransport */ 920 /* Determine HT-specific capability type. */ 921 val = REG(ptr + PCIR_HT_COMMAND, 2); 922 923 if ((val & 0xe000) == PCIM_HTCAP_SLAVE) 924 cfg->ht.ht_slave = ptr; 925 926 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 927 switch (val & PCIM_HTCMD_CAP_MASK) { 928 case PCIM_HTCAP_MSI_MAPPING: 929 if (!(val & PCIM_HTCMD_MSI_FIXED)) { 930 /* Sanity check the mapping window. */ 931 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 932 4); 933 addr <<= 32; 934 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 935 4); 936 if (addr != MSI_INTEL_ADDR_BASE) 937 device_printf(pcib, 938 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", 939 cfg->domain, cfg->bus, 940 cfg->slot, cfg->func, 941 (long long)addr); 942 } else 943 addr = MSI_INTEL_ADDR_BASE; 944 945 cfg->ht.ht_msimap = ptr; 946 cfg->ht.ht_msictrl = val; 947 cfg->ht.ht_msiaddr = addr; 948 break; 949 } 950 #endif 951 break; 952 case PCIY_MSI: /* PCI MSI */ 953 cfg->msi.msi_location = ptr; 954 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 955 break; 956 case PCIY_MSIX: /* PCI MSI-X */ 957 cfg->msix.msix_location = ptr; 958 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 959 val = REG(ptr + PCIR_MSIX_TABLE, 4); 960 cfg->msix.msix_table_bar = PCIR_BAR(val & 961 PCIM_MSIX_BIR_MASK); 962 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 963 val = REG(ptr + PCIR_MSIX_PBA, 4); 964 cfg->msix.msix_pba_bar = PCIR_BAR(val & 965 PCIM_MSIX_BIR_MASK); 966 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 967 break; 968 case PCIY_VPD: /* PCI Vital Product Data */ 969 cfg->vpd.vpd_reg = ptr; 970 break; 971 case PCIY_SUBVENDOR: 972 /* Should always be true. */ 973 if ((cfg->hdrtype & PCIM_HDRTYPE) == 974 PCIM_HDRTYPE_BRIDGE) { 975 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4); 976 cfg->subvendor = val & 0xffff; 977 cfg->subdevice = val >> 16; 978 } 979 break; 980 case PCIY_PCIX: /* PCI-X */ 981 /* 982 * Assume we have a PCI-X chipset if we have 983 * at least one PCI-PCI bridge with a PCI-X 984 * capability. Note that some systems with 985 * PCI-express or HT chipsets might match on 986 * this check as well. 987 */ 988 if ((cfg->hdrtype & PCIM_HDRTYPE) == 989 PCIM_HDRTYPE_BRIDGE) 990 pcix_chipset = 1; 991 cfg->pcix.pcix_location = ptr; 992 break; 993 case PCIY_EXPRESS: /* PCI-express */ 994 /* 995 * Assume we have a PCI-express chipset if we have 996 * at least one PCI-express device. 997 */ 998 pcie_chipset = 1; 999 cfg->pcie.pcie_location = ptr; 1000 val = REG(ptr + PCIER_FLAGS, 2); 1001 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; 1002 break; 1003 case PCIY_EA: /* Enhanced Allocation */ 1004 cfg->ea.ea_location = ptr; 1005 pci_ea_fill_info(pcib, cfg); 1006 break; 1007 default: 1008 break; 1009 } 1010 } 1011 1012 #if defined(__powerpc__) 1013 /* 1014 * Enable the MSI mapping window for all HyperTransport 1015 * slaves. PCI-PCI bridges have their windows enabled via 1016 * PCIB_MAP_MSI(). 1017 */ 1018 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && 1019 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { 1020 device_printf(pcib, 1021 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n", 1022 cfg->domain, cfg->bus, cfg->slot, cfg->func); 1023 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 1024 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, 1025 2); 1026 } 1027 #endif 1028 /* REG and WREG use carry through to next functions */ 1029 } 1030 1031 /* 1032 * PCI Vital Product Data 1033 */ 1034 1035 #define PCI_VPD_TIMEOUT 1000000 1036 1037 static int 1038 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data) 1039 { 1040 int count = PCI_VPD_TIMEOUT; 1041 1042 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1043 1044 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); 1045 1046 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { 1047 if (--count < 0) 1048 return (ENXIO); 1049 DELAY(1); /* limit looping */ 1050 } 1051 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); 1052 1053 return (0); 1054 } 1055 1056 #if 0 1057 static int 1058 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 1059 { 1060 int count = PCI_VPD_TIMEOUT; 1061 1062 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1063 1064 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4); 1065 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2); 1066 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) { 1067 if (--count < 0) 1068 return (ENXIO); 1069 DELAY(1); /* limit looping */ 1070 } 1071 1072 return (0); 1073 } 1074 #endif 1075 1076 #undef PCI_VPD_TIMEOUT 1077 1078 struct vpd_readstate { 1079 device_t pcib; 1080 pcicfgregs *cfg; 1081 uint32_t val; 1082 int bytesinval; 1083 int off; 1084 uint8_t cksum; 1085 }; 1086 1087 /* return 0 and one byte in *data if no read error, -1 else */ 1088 static int 1089 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data) 1090 { 1091 uint32_t reg; 1092 uint8_t byte; 1093 1094 if (vrs->bytesinval == 0) { 1095 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) 1096 return (-1); 1097 vrs->val = le32toh(reg); 1098 vrs->off += 4; 1099 byte = vrs->val & 0xff; 1100 vrs->bytesinval = 3; 1101 } else { 1102 vrs->val = vrs->val >> 8; 1103 byte = vrs->val & 0xff; 1104 vrs->bytesinval--; 1105 } 1106 1107 vrs->cksum += byte; 1108 *data = byte; 1109 return (0); 1110 } 1111 1112 /* return 0 on match, -1 and "unget" byte on no match */ 1113 static int 1114 vpd_expectbyte(struct vpd_readstate *vrs, uint8_t expected) 1115 { 1116 uint8_t data; 1117 1118 if (vpd_nextbyte(vrs, &data) != 0) 1119 return (-1); 1120 1121 if (data == expected) 1122 return (0); 1123 1124 vrs->cksum -= data; 1125 vrs->val = (vrs->val << 8) + data; 1126 vrs->bytesinval++; 1127 return (-1); 1128 } 1129 1130 /* return size if tag matches, -1 on no match, -2 on read error */ 1131 static int 1132 vpd_read_tag_size(struct vpd_readstate *vrs, uint8_t vpd_tag) 1133 { 1134 uint8_t byte1, byte2; 1135 1136 if (vpd_expectbyte(vrs, vpd_tag) != 0) 1137 return (-1); 1138 1139 if ((vpd_tag & 0x80) == 0) 1140 return (vpd_tag & 0x07); 1141 1142 if (vpd_nextbyte(vrs, &byte1) != 0) 1143 return (-2); 1144 if (vpd_nextbyte(vrs, &byte2) != 0) 1145 return (-2); 1146 1147 return ((byte2 << 8) + byte1); 1148 } 1149 1150 /* (re)allocate buffer in multiples of 8 elements */ 1151 static void* 1152 alloc_buffer(void* buffer, size_t element_size, int needed) 1153 { 1154 int alloc, new_alloc; 1155 1156 alloc = roundup2(needed, 8); 1157 new_alloc = roundup2(needed + 1, 8); 1158 if (alloc != new_alloc) { 1159 buffer = reallocf(buffer, 1160 new_alloc * element_size, M_DEVBUF, M_WAITOK | M_ZERO); 1161 } 1162 1163 return (buffer); 1164 } 1165 1166 /* read VPD keyword and return element size, return -1 on read error */ 1167 static int 1168 vpd_read_elem_head(struct vpd_readstate *vrs, char keyword[2]) 1169 { 1170 uint8_t data; 1171 1172 if (vpd_nextbyte(vrs, &keyword[0]) != 0) 1173 return (-1); 1174 if (vpd_nextbyte(vrs, &keyword[1]) != 0) 1175 return (-1); 1176 if (vpd_nextbyte(vrs, &data) != 0) 1177 return (-1); 1178 1179 return (data); 1180 } 1181 1182 /* read VPD data element of given size into allocated buffer */ 1183 static char * 1184 vpd_read_value(struct vpd_readstate *vrs, int size) 1185 { 1186 int i; 1187 char char1; 1188 char *value; 1189 1190 value = malloc(size + 1, M_DEVBUF, M_WAITOK); 1191 for (i = 0; i < size; i++) { 1192 if (vpd_nextbyte(vrs, &char1) != 0) { 1193 free(value, M_DEVBUF); 1194 return (NULL); 1195 } 1196 value[i] = char1; 1197 } 1198 value[size] = '\0'; 1199 1200 return (value); 1201 } 1202 1203 /* read VPD into *keyword and *value, return length of data element */ 1204 static int 1205 vpd_read_elem_data(struct vpd_readstate *vrs, char keyword[2], char **value, int maxlen) 1206 { 1207 int len; 1208 1209 len = vpd_read_elem_head(vrs, keyword); 1210 if (len < 0 || len > maxlen) 1211 return (-1); 1212 *value = vpd_read_value(vrs, len); 1213 1214 return (len); 1215 } 1216 1217 /* subtract all data following first byte from checksum of RV element */ 1218 static void 1219 vpd_fixup_cksum(struct vpd_readstate *vrs, char *rvstring, int len) 1220 { 1221 int i; 1222 uint8_t fixup; 1223 1224 fixup = 0; 1225 for (i = 1; i < len; i++) 1226 fixup += rvstring[i]; 1227 vrs->cksum -= fixup; 1228 } 1229 1230 /* fetch one read-only element and return size of heading + data */ 1231 static int 1232 next_vpd_ro_elem(struct vpd_readstate *vrs, int maxsize) 1233 { 1234 struct pcicfg_vpd *vpd; 1235 pcicfgregs *cfg; 1236 struct vpd_readonly *vpd_ros; 1237 int len; 1238 1239 cfg = vrs->cfg; 1240 vpd = &cfg->vpd; 1241 1242 if (maxsize < 3) 1243 return (-1); 1244 vpd->vpd_ros = alloc_buffer(vpd->vpd_ros, sizeof(*vpd->vpd_ros), vpd->vpd_rocnt); 1245 vpd_ros = &vpd->vpd_ros[vpd->vpd_rocnt]; 1246 maxsize -= 3; 1247 len = vpd_read_elem_data(vrs, vpd_ros->keyword, &vpd_ros->value, maxsize); 1248 if (vpd_ros->value == NULL) 1249 return (-1); 1250 vpd_ros->len = len; 1251 if (vpd_ros->keyword[0] == 'R' && vpd_ros->keyword[1] == 'V') { 1252 vpd_fixup_cksum(vrs, vpd_ros->value, len); 1253 if (vrs->cksum != 0) { 1254 pci_printf(cfg, 1255 "invalid VPD checksum %#hhx\n", vrs->cksum); 1256 return (-1); 1257 } 1258 } 1259 vpd->vpd_rocnt++; 1260 1261 return (len + 3); 1262 } 1263 1264 /* fetch one writable element and return size of heading + data */ 1265 static int 1266 next_vpd_rw_elem(struct vpd_readstate *vrs, int maxsize) 1267 { 1268 struct pcicfg_vpd *vpd; 1269 pcicfgregs *cfg; 1270 struct vpd_write *vpd_w; 1271 int len; 1272 1273 cfg = vrs->cfg; 1274 vpd = &cfg->vpd; 1275 1276 if (maxsize < 3) 1277 return (-1); 1278 vpd->vpd_w = alloc_buffer(vpd->vpd_w, sizeof(*vpd->vpd_w), vpd->vpd_wcnt); 1279 if (vpd->vpd_w == NULL) { 1280 pci_printf(cfg, "out of memory"); 1281 return (-1); 1282 } 1283 vpd_w = &vpd->vpd_w[vpd->vpd_wcnt]; 1284 maxsize -= 3; 1285 vpd_w->start = vrs->off + 3 - vrs->bytesinval; 1286 len = vpd_read_elem_data(vrs, vpd_w->keyword, &vpd_w->value, maxsize); 1287 if (vpd_w->value == NULL) 1288 return (-1); 1289 vpd_w->len = len; 1290 vpd->vpd_wcnt++; 1291 1292 return (len + 3); 1293 } 1294 1295 /* free all memory allocated for VPD data */ 1296 static void 1297 vpd_free(struct pcicfg_vpd *vpd) 1298 { 1299 int i; 1300 1301 free(vpd->vpd_ident, M_DEVBUF); 1302 for (i = 0; i < vpd->vpd_rocnt; i++) 1303 free(vpd->vpd_ros[i].value, M_DEVBUF); 1304 free(vpd->vpd_ros, M_DEVBUF); 1305 vpd->vpd_rocnt = 0; 1306 for (i = 0; i < vpd->vpd_wcnt; i++) 1307 free(vpd->vpd_w[i].value, M_DEVBUF); 1308 free(vpd->vpd_w, M_DEVBUF); 1309 vpd->vpd_wcnt = 0; 1310 } 1311 1312 #define VPD_TAG_END ((0x0f << 3) | 0) /* small tag, len == 0 */ 1313 #define VPD_TAG_IDENT (0x02 | 0x80) /* large tag */ 1314 #define VPD_TAG_RO (0x10 | 0x80) /* large tag */ 1315 #define VPD_TAG_RW (0x11 | 0x80) /* large tag */ 1316 1317 static int 1318 pci_parse_vpd(device_t pcib, pcicfgregs *cfg) 1319 { 1320 struct vpd_readstate vrs; 1321 int cksumvalid; 1322 int size, elem_size; 1323 1324 /* init vpd reader */ 1325 vrs.bytesinval = 0; 1326 vrs.off = 0; 1327 vrs.pcib = pcib; 1328 vrs.cfg = cfg; 1329 vrs.cksum = 0; 1330 1331 /* read VPD ident element - mandatory */ 1332 size = vpd_read_tag_size(&vrs, VPD_TAG_IDENT); 1333 if (size <= 0) { 1334 pci_printf(cfg, "no VPD ident found\n"); 1335 return (0); 1336 } 1337 cfg->vpd.vpd_ident = vpd_read_value(&vrs, size); 1338 if (cfg->vpd.vpd_ident == NULL) { 1339 pci_printf(cfg, "error accessing VPD ident data\n"); 1340 return (0); 1341 } 1342 1343 /* read VPD RO elements - mandatory */ 1344 size = vpd_read_tag_size(&vrs, VPD_TAG_RO); 1345 if (size <= 0) { 1346 pci_printf(cfg, "no read-only VPD data found\n"); 1347 return (0); 1348 } 1349 while (size > 0) { 1350 elem_size = next_vpd_ro_elem(&vrs, size); 1351 if (elem_size < 0) { 1352 pci_printf(cfg, "error accessing read-only VPD data\n"); 1353 return (-1); 1354 } 1355 size -= elem_size; 1356 } 1357 cksumvalid = (vrs.cksum == 0); 1358 if (!cksumvalid) 1359 return (-1); 1360 1361 /* read VPD RW elements - optional */ 1362 size = vpd_read_tag_size(&vrs, VPD_TAG_RW); 1363 if (size == -2) 1364 return (-1); 1365 while (size > 0) { 1366 elem_size = next_vpd_rw_elem(&vrs, size); 1367 if (elem_size < 0) { 1368 pci_printf(cfg, "error accessing writeable VPD data\n"); 1369 return (-1); 1370 } 1371 size -= elem_size; 1372 } 1373 1374 /* read empty END tag - mandatory */ 1375 size = vpd_read_tag_size(&vrs, VPD_TAG_END); 1376 if (size != 0) { 1377 pci_printf(cfg, "No valid VPD end tag found\n"); 1378 } 1379 return (0); 1380 } 1381 1382 static void 1383 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 1384 { 1385 int status; 1386 1387 status = pci_parse_vpd(pcib, cfg); 1388 if (status < 0) 1389 vpd_free(&cfg->vpd); 1390 cfg->vpd.vpd_cached = 1; 1391 #undef REG 1392 #undef WREG 1393 } 1394 1395 int 1396 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 1397 { 1398 struct pci_devinfo *dinfo = device_get_ivars(child); 1399 pcicfgregs *cfg = &dinfo->cfg; 1400 1401 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1402 pci_read_vpd(device_get_parent(dev), cfg); 1403 1404 *identptr = cfg->vpd.vpd_ident; 1405 1406 if (*identptr == NULL) 1407 return (ENXIO); 1408 1409 return (0); 1410 } 1411 1412 int 1413 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 1414 const char **vptr) 1415 { 1416 struct pci_devinfo *dinfo = device_get_ivars(child); 1417 pcicfgregs *cfg = &dinfo->cfg; 1418 int i; 1419 1420 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1421 pci_read_vpd(device_get_parent(dev), cfg); 1422 1423 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 1424 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 1425 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { 1426 *vptr = cfg->vpd.vpd_ros[i].value; 1427 return (0); 1428 } 1429 1430 *vptr = NULL; 1431 return (ENXIO); 1432 } 1433 1434 struct pcicfg_vpd * 1435 pci_fetch_vpd_list(device_t dev) 1436 { 1437 struct pci_devinfo *dinfo = device_get_ivars(dev); 1438 pcicfgregs *cfg = &dinfo->cfg; 1439 1440 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1441 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg); 1442 return (&cfg->vpd); 1443 } 1444 1445 /* 1446 * Find the requested HyperTransport capability and return the offset 1447 * in configuration space via the pointer provided. The function 1448 * returns 0 on success and an error code otherwise. 1449 */ 1450 int 1451 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg) 1452 { 1453 int ptr, error; 1454 uint16_t val; 1455 1456 error = pci_find_cap(child, PCIY_HT, &ptr); 1457 if (error) 1458 return (error); 1459 1460 /* 1461 * Traverse the capabilities list checking each HT capability 1462 * to see if it matches the requested HT capability. 1463 */ 1464 for (;;) { 1465 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1466 if (capability == PCIM_HTCAP_SLAVE || 1467 capability == PCIM_HTCAP_HOST) 1468 val &= 0xe000; 1469 else 1470 val &= PCIM_HTCMD_CAP_MASK; 1471 if (val == capability) { 1472 if (capreg != NULL) 1473 *capreg = ptr; 1474 return (0); 1475 } 1476 1477 /* Skip to the next HT capability. */ 1478 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1479 break; 1480 } 1481 1482 return (ENOENT); 1483 } 1484 1485 /* 1486 * Find the next requested HyperTransport capability after start and return 1487 * the offset in configuration space via the pointer provided. The function 1488 * returns 0 on success and an error code otherwise. 1489 */ 1490 int 1491 pci_find_next_htcap_method(device_t dev, device_t child, int capability, 1492 int start, int *capreg) 1493 { 1494 int ptr; 1495 uint16_t val; 1496 1497 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == PCIY_HT, 1498 ("start capability is not HyperTransport capability")); 1499 ptr = start; 1500 1501 /* 1502 * Traverse the capabilities list checking each HT capability 1503 * to see if it matches the requested HT capability. 1504 */ 1505 for (;;) { 1506 /* Skip to the next HT capability. */ 1507 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1508 break; 1509 1510 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1511 if (capability == PCIM_HTCAP_SLAVE || 1512 capability == PCIM_HTCAP_HOST) 1513 val &= 0xe000; 1514 else 1515 val &= PCIM_HTCMD_CAP_MASK; 1516 if (val == capability) { 1517 if (capreg != NULL) 1518 *capreg = ptr; 1519 return (0); 1520 } 1521 } 1522 1523 return (ENOENT); 1524 } 1525 1526 /* 1527 * Find the requested capability and return the offset in 1528 * configuration space via the pointer provided. The function returns 1529 * 0 on success and an error code otherwise. 1530 */ 1531 int 1532 pci_find_cap_method(device_t dev, device_t child, int capability, 1533 int *capreg) 1534 { 1535 struct pci_devinfo *dinfo = device_get_ivars(child); 1536 pcicfgregs *cfg = &dinfo->cfg; 1537 uint32_t status; 1538 uint8_t ptr; 1539 int cnt; 1540 1541 /* 1542 * Check the CAP_LIST bit of the PCI status register first. 1543 */ 1544 status = pci_read_config(child, PCIR_STATUS, 2); 1545 if (!(status & PCIM_STATUS_CAPPRESENT)) 1546 return (ENXIO); 1547 1548 /* 1549 * Determine the start pointer of the capabilities list. 1550 */ 1551 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1552 case PCIM_HDRTYPE_NORMAL: 1553 case PCIM_HDRTYPE_BRIDGE: 1554 ptr = PCIR_CAP_PTR; 1555 break; 1556 case PCIM_HDRTYPE_CARDBUS: 1557 ptr = PCIR_CAP_PTR_2; 1558 break; 1559 default: 1560 /* XXX: panic? */ 1561 return (ENXIO); /* no extended capabilities support */ 1562 } 1563 ptr = pci_read_config(child, ptr, 1); 1564 1565 /* 1566 * Traverse the capabilities list. Limit by total theoretical 1567 * maximum number of caps: capability needs at least id and 1568 * next registers, and any type X header cannot contain caps. 1569 */ 1570 for (cnt = 0; ptr != 0 && cnt < (PCIE_REGMAX - 0x40) / 2; cnt++) { 1571 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1572 if (capreg != NULL) 1573 *capreg = ptr; 1574 return (0); 1575 } 1576 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1577 } 1578 1579 return (ENOENT); 1580 } 1581 1582 /* 1583 * Find the next requested capability after start and return the offset in 1584 * configuration space via the pointer provided. The function returns 1585 * 0 on success and an error code otherwise. 1586 */ 1587 int 1588 pci_find_next_cap_method(device_t dev, device_t child, int capability, 1589 int start, int *capreg) 1590 { 1591 uint8_t ptr; 1592 1593 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == capability, 1594 ("start capability is not expected capability")); 1595 1596 ptr = pci_read_config(child, start + PCICAP_NEXTPTR, 1); 1597 while (ptr != 0) { 1598 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1599 if (capreg != NULL) 1600 *capreg = ptr; 1601 return (0); 1602 } 1603 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1604 } 1605 1606 return (ENOENT); 1607 } 1608 1609 /* 1610 * Find the requested extended capability and return the offset in 1611 * configuration space via the pointer provided. The function returns 1612 * 0 on success and an error code otherwise. 1613 */ 1614 int 1615 pci_find_extcap_method(device_t dev, device_t child, int capability, 1616 int *capreg) 1617 { 1618 struct pci_devinfo *dinfo = device_get_ivars(child); 1619 pcicfgregs *cfg = &dinfo->cfg; 1620 uint32_t ecap; 1621 uint16_t ptr; 1622 1623 /* Only supported for PCI-express devices. */ 1624 if (cfg->pcie.pcie_location == 0) 1625 return (ENXIO); 1626 1627 ptr = PCIR_EXTCAP; 1628 ecap = pci_read_config(child, ptr, 4); 1629 if (ecap == 0xffffffff || ecap == 0) 1630 return (ENOENT); 1631 for (;;) { 1632 if (PCI_EXTCAP_ID(ecap) == capability) { 1633 if (capreg != NULL) 1634 *capreg = ptr; 1635 return (0); 1636 } 1637 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1638 if (ptr == 0) 1639 break; 1640 ecap = pci_read_config(child, ptr, 4); 1641 } 1642 1643 return (ENOENT); 1644 } 1645 1646 /* 1647 * Find the next requested extended capability after start and return the 1648 * offset in configuration space via the pointer provided. The function 1649 * returns 0 on success and an error code otherwise. 1650 */ 1651 int 1652 pci_find_next_extcap_method(device_t dev, device_t child, int capability, 1653 int start, int *capreg) 1654 { 1655 struct pci_devinfo *dinfo = device_get_ivars(child); 1656 pcicfgregs *cfg = &dinfo->cfg; 1657 uint32_t ecap; 1658 uint16_t ptr; 1659 1660 /* Only supported for PCI-express devices. */ 1661 if (cfg->pcie.pcie_location == 0) 1662 return (ENXIO); 1663 1664 ecap = pci_read_config(child, start, 4); 1665 KASSERT(PCI_EXTCAP_ID(ecap) == capability, 1666 ("start extended capability is not expected capability")); 1667 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1668 while (ptr != 0) { 1669 ecap = pci_read_config(child, ptr, 4); 1670 if (PCI_EXTCAP_ID(ecap) == capability) { 1671 if (capreg != NULL) 1672 *capreg = ptr; 1673 return (0); 1674 } 1675 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1676 } 1677 1678 return (ENOENT); 1679 } 1680 1681 /* 1682 * Support for MSI-X message interrupts. 1683 */ 1684 static void 1685 pci_write_msix_entry(device_t dev, u_int index, uint64_t address, uint32_t data) 1686 { 1687 struct pci_devinfo *dinfo = device_get_ivars(dev); 1688 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1689 uint32_t offset; 1690 1691 KASSERT(msix->msix_table_len > index, ("bogus index")); 1692 offset = msix->msix_table_offset + index * 16; 1693 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); 1694 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); 1695 bus_write_4(msix->msix_table_res, offset + 8, data); 1696 } 1697 1698 void 1699 pci_enable_msix_method(device_t dev, device_t child, u_int index, 1700 uint64_t address, uint32_t data) 1701 { 1702 1703 if (pci_msix_rewrite_table) { 1704 struct pci_devinfo *dinfo = device_get_ivars(child); 1705 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1706 1707 /* 1708 * Some VM hosts require MSIX to be disabled in the 1709 * control register before updating the MSIX table 1710 * entries are allowed. It is not enough to only 1711 * disable MSIX while updating a single entry. MSIX 1712 * must be disabled while updating all entries in the 1713 * table. 1714 */ 1715 pci_write_config(child, 1716 msix->msix_location + PCIR_MSIX_CTRL, 1717 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2); 1718 pci_resume_msix(child); 1719 } else 1720 pci_write_msix_entry(child, index, address, data); 1721 1722 /* Enable MSI -> HT mapping. */ 1723 pci_ht_map_msi(child, address); 1724 } 1725 1726 void 1727 pci_mask_msix(device_t dev, u_int index) 1728 { 1729 struct pci_devinfo *dinfo = device_get_ivars(dev); 1730 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1731 uint32_t offset, val; 1732 1733 KASSERT(PCI_MSIX_MSGNUM(msix->msix_ctrl) > index, ("bogus index")); 1734 offset = msix->msix_table_offset + index * 16 + 12; 1735 val = bus_read_4(msix->msix_table_res, offset); 1736 val |= PCIM_MSIX_VCTRL_MASK; 1737 1738 /* 1739 * Some devices (e.g. Samsung PM961) do not support reads of this 1740 * register, so always write the new value. 1741 */ 1742 bus_write_4(msix->msix_table_res, offset, val); 1743 } 1744 1745 void 1746 pci_unmask_msix(device_t dev, u_int index) 1747 { 1748 struct pci_devinfo *dinfo = device_get_ivars(dev); 1749 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1750 uint32_t offset, val; 1751 1752 KASSERT(PCI_MSIX_MSGNUM(msix->msix_ctrl) > index, ("bogus index")); 1753 offset = msix->msix_table_offset + index * 16 + 12; 1754 val = bus_read_4(msix->msix_table_res, offset); 1755 val &= ~PCIM_MSIX_VCTRL_MASK; 1756 1757 /* 1758 * Some devices (e.g. Samsung PM961) do not support reads of this 1759 * register, so always write the new value. 1760 */ 1761 bus_write_4(msix->msix_table_res, offset, val); 1762 } 1763 1764 int 1765 pci_pending_msix(device_t dev, u_int index) 1766 { 1767 struct pci_devinfo *dinfo = device_get_ivars(dev); 1768 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1769 uint32_t offset, bit; 1770 1771 KASSERT(msix->msix_table_len > index, ("bogus index")); 1772 offset = msix->msix_pba_offset + (index / 32) * 4; 1773 bit = 1 << index % 32; 1774 return (bus_read_4(msix->msix_pba_res, offset) & bit); 1775 } 1776 1777 /* 1778 * Restore MSI-X registers and table during resume. If MSI-X is 1779 * enabled then walk the virtual table to restore the actual MSI-X 1780 * table. 1781 */ 1782 static void 1783 pci_resume_msix(device_t dev) 1784 { 1785 struct pci_devinfo *dinfo = device_get_ivars(dev); 1786 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1787 struct msix_table_entry *mte; 1788 struct msix_vector *mv; 1789 u_int i, msgnum; 1790 1791 if (msix->msix_alloc > 0) { 1792 msgnum = PCI_MSIX_MSGNUM(msix->msix_ctrl); 1793 1794 /* First, mask all vectors. */ 1795 for (i = 0; i < msgnum; i++) 1796 pci_mask_msix(dev, i); 1797 1798 /* Second, program any messages with at least one handler. */ 1799 for (i = 0; i < msix->msix_table_len; i++) { 1800 mte = &msix->msix_table[i]; 1801 if (mte->mte_vector == 0 || mte->mte_handlers == 0) 1802 continue; 1803 mv = &msix->msix_vectors[mte->mte_vector - 1]; 1804 pci_write_msix_entry(dev, i, mv->mv_address, 1805 mv->mv_data); 1806 pci_unmask_msix(dev, i); 1807 } 1808 } 1809 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, 1810 msix->msix_ctrl, 2); 1811 } 1812 1813 /* 1814 * Attempt to allocate *count MSI-X messages. The actual number allocated is 1815 * returned in *count. After this function returns, each message will be 1816 * available to the driver as SYS_RES_IRQ resources starting at rid 1. 1817 */ 1818 int 1819 pci_alloc_msix_method(device_t dev, device_t child, int *count) 1820 { 1821 struct pci_devinfo *dinfo = device_get_ivars(child); 1822 pcicfgregs *cfg = &dinfo->cfg; 1823 struct resource_list_entry *rle; 1824 u_int actual, i, max; 1825 int error, irq; 1826 uint16_t ctrl, msgnum; 1827 1828 /* Don't let count == 0 get us into trouble. */ 1829 if (*count < 1) 1830 return (EINVAL); 1831 1832 /* If rid 0 is allocated, then fail. */ 1833 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1834 if (rle != NULL && rle->res != NULL) 1835 return (ENXIO); 1836 1837 /* Already have allocated messages? */ 1838 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1839 return (ENXIO); 1840 1841 /* If MSI-X is blacklisted for this system, fail. */ 1842 if (pci_msix_blacklisted()) 1843 return (ENXIO); 1844 1845 /* MSI-X capability present? */ 1846 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1847 return (ENODEV); 1848 1849 /* Make sure the appropriate BARs are mapped. */ 1850 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1851 cfg->msix.msix_table_bar); 1852 if (rle == NULL || rle->res == NULL || 1853 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1854 return (ENXIO); 1855 cfg->msix.msix_table_res = rle->res; 1856 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1857 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1858 cfg->msix.msix_pba_bar); 1859 if (rle == NULL || rle->res == NULL || 1860 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1861 return (ENXIO); 1862 } 1863 cfg->msix.msix_pba_res = rle->res; 1864 1865 ctrl = pci_read_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1866 2); 1867 msgnum = PCI_MSIX_MSGNUM(ctrl); 1868 if (bootverbose) 1869 device_printf(child, 1870 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1871 *count, msgnum); 1872 max = min(*count, msgnum); 1873 for (i = 0; i < max; i++) { 1874 /* Allocate a message. */ 1875 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq); 1876 if (error) { 1877 if (i == 0) 1878 return (error); 1879 break; 1880 } 1881 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1882 irq, 1); 1883 } 1884 actual = i; 1885 1886 if (bootverbose) { 1887 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1888 if (actual == 1) 1889 device_printf(child, "using IRQ %ju for MSI-X\n", 1890 rle->start); 1891 else { 1892 bool run; 1893 1894 /* 1895 * Be fancy and try to print contiguous runs of 1896 * IRQ values as ranges. 'irq' is the previous IRQ. 1897 * 'run' is true if we are in a range. 1898 */ 1899 device_printf(child, "using IRQs %ju", rle->start); 1900 irq = rle->start; 1901 run = false; 1902 for (i = 1; i < actual; i++) { 1903 rle = resource_list_find(&dinfo->resources, 1904 SYS_RES_IRQ, i + 1); 1905 1906 /* Still in a run? */ 1907 if (rle->start == irq + 1) { 1908 run = true; 1909 irq++; 1910 continue; 1911 } 1912 1913 /* Finish previous range. */ 1914 if (run) { 1915 printf("-%d", irq); 1916 run = false; 1917 } 1918 1919 /* Start new range. */ 1920 printf(",%ju", rle->start); 1921 irq = rle->start; 1922 } 1923 1924 /* Unfinished range? */ 1925 if (run) 1926 printf("-%d", irq); 1927 printf(" for MSI-X\n"); 1928 } 1929 } 1930 1931 /* Mask all vectors. */ 1932 for (i = 0; i < msgnum; i++) 1933 pci_mask_msix(child, i); 1934 1935 /* Allocate and initialize vector data and virtual table. */ 1936 cfg->msix.msix_vectors = mallocarray(actual, sizeof(struct msix_vector), 1937 M_DEVBUF, M_WAITOK | M_ZERO); 1938 cfg->msix.msix_table = mallocarray(actual, 1939 sizeof(struct msix_table_entry), M_DEVBUF, M_WAITOK | M_ZERO); 1940 for (i = 0; i < actual; i++) { 1941 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1942 cfg->msix.msix_vectors[i].mv_irq = rle->start; 1943 cfg->msix.msix_table[i].mte_vector = i + 1; 1944 } 1945 1946 /* Update control register to enable MSI-X. */ 1947 ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1948 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1949 ctrl, 2); 1950 cfg->msix.msix_ctrl = ctrl; 1951 1952 /* Update counts of alloc'd messages. */ 1953 cfg->msix.msix_alloc = actual; 1954 cfg->msix.msix_table_len = actual; 1955 *count = actual; 1956 return (0); 1957 } 1958 1959 /* 1960 * By default, pci_alloc_msix() will assign the allocated IRQ 1961 * resources consecutively to the first N messages in the MSI-X table. 1962 * However, device drivers may want to use different layouts if they 1963 * either receive fewer messages than they asked for, or they wish to 1964 * populate the MSI-X table sparsely. This method allows the driver 1965 * to specify what layout it wants. It must be called after a 1966 * successful pci_alloc_msix() but before any of the associated 1967 * SYS_RES_IRQ resources are allocated via bus_alloc_resource(). 1968 * 1969 * The 'vectors' array contains 'count' message vectors. The array 1970 * maps directly to the MSI-X table in that index 0 in the array 1971 * specifies the vector for the first message in the MSI-X table, etc. 1972 * The vector value in each array index can either be 0 to indicate 1973 * that no vector should be assigned to a message slot, or it can be a 1974 * number from 1 to N (where N is the count returned from a 1975 * succcessful call to pci_alloc_msix()) to indicate which message 1976 * vector (IRQ) to be used for the corresponding message. 1977 * 1978 * On successful return, each message with a non-zero vector will have 1979 * an associated SYS_RES_IRQ whose rid is equal to the array index + 1980 * 1. Additionally, if any of the IRQs allocated via the previous 1981 * call to pci_alloc_msix() are not used in the mapping, those IRQs 1982 * will be freed back to the system automatically. 1983 * 1984 * For example, suppose a driver has a MSI-X table with 6 messages and 1985 * asks for 6 messages, but pci_alloc_msix() only returns a count of 1986 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and 1987 * C. After the call to pci_alloc_msix(), the device will be setup to 1988 * have an MSI-X table of ABC--- (where - means no vector assigned). 1989 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 }, 1990 * then the MSI-X table will look like A-AB-B, and the 'C' vector will 1991 * be freed back to the system. This device will also have valid 1992 * SYS_RES_IRQ rids of 1, 3, 4, and 6. 1993 * 1994 * In any case, the SYS_RES_IRQ rid X will always map to the message 1995 * at MSI-X table index X - 1 and will only be valid if a vector is 1996 * assigned to that table entry. 1997 */ 1998 int 1999 pci_remap_msix_method(device_t dev, device_t child, int count, 2000 const u_int *vectors) 2001 { 2002 struct pci_devinfo *dinfo = device_get_ivars(child); 2003 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2004 struct resource_list_entry *rle; 2005 u_int i, irq, j; 2006 bool *used; 2007 2008 /* 2009 * Have to have at least one message in the table but the 2010 * table can't be bigger than the actual MSI-X table in the 2011 * device. 2012 */ 2013 if (count < 1 || count > PCI_MSIX_MSGNUM(msix->msix_ctrl)) 2014 return (EINVAL); 2015 2016 /* Sanity check the vectors. */ 2017 for (i = 0; i < count; i++) 2018 if (vectors[i] > msix->msix_alloc) 2019 return (EINVAL); 2020 2021 /* 2022 * Make sure there aren't any holes in the vectors to be used. 2023 * It's a big pain to support it, and it doesn't really make 2024 * sense anyway. Also, at least one vector must be used. 2025 */ 2026 used = mallocarray(msix->msix_alloc, sizeof(*used), M_DEVBUF, M_WAITOK | 2027 M_ZERO); 2028 for (i = 0; i < count; i++) 2029 if (vectors[i] != 0) 2030 used[vectors[i] - 1] = true; 2031 for (i = 0; i < msix->msix_alloc - 1; i++) 2032 if (!used[i] && used[i + 1]) { 2033 free(used, M_DEVBUF); 2034 return (EINVAL); 2035 } 2036 if (!used[0]) { 2037 free(used, M_DEVBUF); 2038 return (EINVAL); 2039 } 2040 2041 /* Make sure none of the resources are allocated. */ 2042 for (i = 0; i < msix->msix_table_len; i++) { 2043 if (msix->msix_table[i].mte_vector == 0) 2044 continue; 2045 if (msix->msix_table[i].mte_handlers > 0) { 2046 free(used, M_DEVBUF); 2047 return (EBUSY); 2048 } 2049 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2050 KASSERT(rle != NULL, ("missing resource")); 2051 if (rle->res != NULL) { 2052 free(used, M_DEVBUF); 2053 return (EBUSY); 2054 } 2055 } 2056 2057 /* Free the existing resource list entries. */ 2058 for (i = 0; i < msix->msix_table_len; i++) { 2059 if (msix->msix_table[i].mte_vector == 0) 2060 continue; 2061 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2062 } 2063 2064 /* 2065 * Build the new virtual table keeping track of which vectors are 2066 * used. 2067 */ 2068 free(msix->msix_table, M_DEVBUF); 2069 msix->msix_table = mallocarray(count, sizeof(struct msix_table_entry), 2070 M_DEVBUF, M_WAITOK | M_ZERO); 2071 for (i = 0; i < count; i++) 2072 msix->msix_table[i].mte_vector = vectors[i]; 2073 msix->msix_table_len = count; 2074 2075 /* Free any unused IRQs and resize the vectors array if necessary. */ 2076 j = msix->msix_alloc - 1; 2077 if (!used[j]) { 2078 struct msix_vector *vec; 2079 2080 while (!used[j]) { 2081 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2082 msix->msix_vectors[j].mv_irq); 2083 j--; 2084 } 2085 vec = mallocarray(j + 1, sizeof(struct msix_vector), M_DEVBUF, 2086 M_WAITOK); 2087 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * 2088 (j + 1)); 2089 free(msix->msix_vectors, M_DEVBUF); 2090 msix->msix_vectors = vec; 2091 msix->msix_alloc = j + 1; 2092 } 2093 free(used, M_DEVBUF); 2094 2095 /* Map the IRQs onto the rids. */ 2096 for (i = 0; i < count; i++) { 2097 if (vectors[i] == 0) 2098 continue; 2099 irq = msix->msix_vectors[vectors[i] - 1].mv_irq; 2100 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 2101 irq, 1); 2102 } 2103 2104 if (bootverbose) { 2105 device_printf(child, "Remapped MSI-X IRQs as: "); 2106 for (i = 0; i < count; i++) { 2107 if (i != 0) 2108 printf(", "); 2109 if (vectors[i] == 0) 2110 printf("---"); 2111 else 2112 printf("%d", 2113 msix->msix_vectors[vectors[i] - 1].mv_irq); 2114 } 2115 printf("\n"); 2116 } 2117 2118 return (0); 2119 } 2120 2121 static int 2122 pci_release_msix(device_t dev, device_t child) 2123 { 2124 struct pci_devinfo *dinfo = device_get_ivars(child); 2125 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2126 struct resource_list_entry *rle; 2127 u_int i; 2128 2129 /* Do we have any messages to release? */ 2130 if (msix->msix_alloc == 0) 2131 return (ENODEV); 2132 2133 /* Make sure none of the resources are allocated. */ 2134 for (i = 0; i < msix->msix_table_len; i++) { 2135 if (msix->msix_table[i].mte_vector == 0) 2136 continue; 2137 if (msix->msix_table[i].mte_handlers > 0) 2138 return (EBUSY); 2139 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2140 KASSERT(rle != NULL, ("missing resource")); 2141 if (rle->res != NULL) 2142 return (EBUSY); 2143 } 2144 2145 /* Update control register to disable MSI-X. */ 2146 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 2147 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, 2148 msix->msix_ctrl, 2); 2149 2150 /* Free the resource list entries. */ 2151 for (i = 0; i < msix->msix_table_len; i++) { 2152 if (msix->msix_table[i].mte_vector == 0) 2153 continue; 2154 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2155 } 2156 free(msix->msix_table, M_DEVBUF); 2157 msix->msix_table_len = 0; 2158 2159 /* Release the IRQs. */ 2160 for (i = 0; i < msix->msix_alloc; i++) 2161 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2162 msix->msix_vectors[i].mv_irq); 2163 free(msix->msix_vectors, M_DEVBUF); 2164 msix->msix_alloc = 0; 2165 return (0); 2166 } 2167 2168 /* 2169 * Return the max supported MSI-X messages this device supports. 2170 * Basically, assuming the MD code can alloc messages, this function 2171 * should return the maximum value that pci_alloc_msix() can return. 2172 * Thus, it is subject to the tunables, etc. 2173 */ 2174 int 2175 pci_msix_count_method(device_t dev, device_t child) 2176 { 2177 struct pci_devinfo *dinfo = device_get_ivars(child); 2178 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2179 uint16_t ctrl; 2180 2181 if (pci_do_msix && msix->msix_location != 0) { 2182 ctrl = pci_read_config(child, msix->msix_location + 2183 PCIR_MSI_CTRL, 2); 2184 return (PCI_MSIX_MSGNUM(ctrl)); 2185 } 2186 return (0); 2187 } 2188 2189 int 2190 pci_msix_pba_bar_method(device_t dev, device_t child) 2191 { 2192 struct pci_devinfo *dinfo = device_get_ivars(child); 2193 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2194 2195 if (pci_do_msix && msix->msix_location != 0) 2196 return (msix->msix_pba_bar); 2197 return (-1); 2198 } 2199 2200 int 2201 pci_msix_table_bar_method(device_t dev, device_t child) 2202 { 2203 struct pci_devinfo *dinfo = device_get_ivars(child); 2204 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2205 2206 if (pci_do_msix && msix->msix_location != 0) 2207 return (msix->msix_table_bar); 2208 return (-1); 2209 } 2210 2211 /* 2212 * HyperTransport MSI mapping control 2213 */ 2214 void 2215 pci_ht_map_msi(device_t dev, uint64_t addr) 2216 { 2217 struct pci_devinfo *dinfo = device_get_ivars(dev); 2218 struct pcicfg_ht *ht = &dinfo->cfg.ht; 2219 2220 if (!ht->ht_msimap) 2221 return; 2222 2223 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && 2224 ht->ht_msiaddr >> 20 == addr >> 20) { 2225 /* Enable MSI -> HT mapping. */ 2226 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 2227 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2228 ht->ht_msictrl, 2); 2229 } 2230 2231 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { 2232 /* Disable MSI -> HT mapping. */ 2233 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; 2234 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2235 ht->ht_msictrl, 2); 2236 } 2237 } 2238 2239 int 2240 pci_get_relaxed_ordering_enabled(device_t dev) 2241 { 2242 struct pci_devinfo *dinfo = device_get_ivars(dev); 2243 int cap; 2244 uint16_t val; 2245 2246 cap = dinfo->cfg.pcie.pcie_location; 2247 if (cap == 0) 2248 return (0); 2249 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2250 val &= PCIEM_CTL_RELAXED_ORD_ENABLE; 2251 return (val != 0); 2252 } 2253 2254 int 2255 pci_get_max_payload(device_t dev) 2256 { 2257 struct pci_devinfo *dinfo = device_get_ivars(dev); 2258 int cap; 2259 uint16_t val; 2260 2261 cap = dinfo->cfg.pcie.pcie_location; 2262 if (cap == 0) 2263 return (0); 2264 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2265 val &= PCIEM_CTL_MAX_PAYLOAD; 2266 val >>= 5; 2267 return (1 << (val + 7)); 2268 } 2269 2270 int 2271 pci_get_max_read_req(device_t dev) 2272 { 2273 struct pci_devinfo *dinfo = device_get_ivars(dev); 2274 int cap; 2275 uint16_t val; 2276 2277 cap = dinfo->cfg.pcie.pcie_location; 2278 if (cap == 0) 2279 return (0); 2280 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2281 val &= PCIEM_CTL_MAX_READ_REQUEST; 2282 val >>= 12; 2283 return (1 << (val + 7)); 2284 } 2285 2286 int 2287 pci_set_max_read_req(device_t dev, int size) 2288 { 2289 struct pci_devinfo *dinfo = device_get_ivars(dev); 2290 int cap; 2291 uint16_t val; 2292 2293 cap = dinfo->cfg.pcie.pcie_location; 2294 if (cap == 0) 2295 return (0); 2296 if (size < 128) 2297 size = 128; 2298 if (size > 4096) 2299 size = 4096; 2300 size = (1 << (fls(size) - 1)); 2301 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2302 val &= ~PCIEM_CTL_MAX_READ_REQUEST; 2303 val |= (fls(size) - 8) << 12; 2304 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2); 2305 return (size); 2306 } 2307 2308 uint32_t 2309 pcie_read_config(device_t dev, int reg, int width) 2310 { 2311 struct pci_devinfo *dinfo = device_get_ivars(dev); 2312 int cap; 2313 2314 cap = dinfo->cfg.pcie.pcie_location; 2315 if (cap == 0) { 2316 if (width == 2) 2317 return (0xffff); 2318 return (0xffffffff); 2319 } 2320 2321 return (pci_read_config(dev, cap + reg, width)); 2322 } 2323 2324 void 2325 pcie_write_config(device_t dev, int reg, uint32_t value, int width) 2326 { 2327 struct pci_devinfo *dinfo = device_get_ivars(dev); 2328 int cap; 2329 2330 cap = dinfo->cfg.pcie.pcie_location; 2331 if (cap == 0) 2332 return; 2333 pci_write_config(dev, cap + reg, value, width); 2334 } 2335 2336 /* 2337 * Adjusts a PCI-e capability register by clearing the bits in mask 2338 * and setting the bits in (value & mask). Bits not set in mask are 2339 * not adjusted. 2340 * 2341 * Returns the old value on success or all ones on failure. 2342 */ 2343 uint32_t 2344 pcie_adjust_config(device_t dev, int reg, uint32_t mask, uint32_t value, 2345 int width) 2346 { 2347 struct pci_devinfo *dinfo = device_get_ivars(dev); 2348 uint32_t old, new; 2349 int cap; 2350 2351 cap = dinfo->cfg.pcie.pcie_location; 2352 if (cap == 0) { 2353 if (width == 2) 2354 return (0xffff); 2355 return (0xffffffff); 2356 } 2357 2358 old = pci_read_config(dev, cap + reg, width); 2359 new = old & ~mask; 2360 new |= (value & mask); 2361 pci_write_config(dev, cap + reg, new, width); 2362 return (old); 2363 } 2364 2365 /* 2366 * Support for MSI message signalled interrupts. 2367 */ 2368 void 2369 pci_enable_msi_method(device_t dev, device_t child, uint64_t address, 2370 uint16_t data) 2371 { 2372 struct pci_devinfo *dinfo = device_get_ivars(child); 2373 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2374 2375 /* Write data and address values. */ 2376 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, 2377 address & 0xffffffff, 4); 2378 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2379 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, 2380 address >> 32, 4); 2381 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, 2382 data, 2); 2383 } else 2384 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, 2385 2); 2386 2387 /* Enable MSI in the control register. */ 2388 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 2389 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2390 msi->msi_ctrl, 2); 2391 2392 /* Enable MSI -> HT mapping. */ 2393 pci_ht_map_msi(child, address); 2394 } 2395 2396 void 2397 pci_disable_msi_method(device_t dev, device_t child) 2398 { 2399 struct pci_devinfo *dinfo = device_get_ivars(child); 2400 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2401 2402 /* Disable MSI -> HT mapping. */ 2403 pci_ht_map_msi(child, 0); 2404 2405 /* Disable MSI in the control register. */ 2406 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; 2407 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2408 msi->msi_ctrl, 2); 2409 } 2410 2411 /* 2412 * Restore MSI registers during resume. If MSI is enabled then 2413 * restore the data and address registers in addition to the control 2414 * register. 2415 */ 2416 static void 2417 pci_resume_msi(device_t dev) 2418 { 2419 struct pci_devinfo *dinfo = device_get_ivars(dev); 2420 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2421 uint64_t address; 2422 uint16_t data; 2423 2424 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 2425 address = msi->msi_addr; 2426 data = msi->msi_data; 2427 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 2428 address & 0xffffffff, 4); 2429 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2430 pci_write_config(dev, msi->msi_location + 2431 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 2432 pci_write_config(dev, msi->msi_location + 2433 PCIR_MSI_DATA_64BIT, data, 2); 2434 } else 2435 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, 2436 data, 2); 2437 } 2438 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 2439 2); 2440 } 2441 2442 static int 2443 pci_remap_intr_method(device_t bus, device_t dev, u_int irq) 2444 { 2445 struct pci_devinfo *dinfo = device_get_ivars(dev); 2446 pcicfgregs *cfg = &dinfo->cfg; 2447 struct resource_list_entry *rle; 2448 struct msix_table_entry *mte; 2449 struct msix_vector *mv; 2450 uint64_t addr; 2451 uint32_t data; 2452 u_int i, j; 2453 int error; 2454 2455 /* 2456 * Handle MSI first. We try to find this IRQ among our list 2457 * of MSI IRQs. If we find it, we request updated address and 2458 * data registers and apply the results. 2459 */ 2460 if (cfg->msi.msi_alloc > 0) { 2461 /* If we don't have any active handlers, nothing to do. */ 2462 if (cfg->msi.msi_handlers == 0) 2463 return (0); 2464 for (i = 0; i < cfg->msi.msi_alloc; i++) { 2465 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 2466 i + 1); 2467 if (rle->start == irq) { 2468 error = PCIB_MAP_MSI(device_get_parent(bus), 2469 dev, irq, &addr, &data); 2470 if (error) 2471 return (error); 2472 pci_disable_msi(dev); 2473 dinfo->cfg.msi.msi_addr = addr; 2474 dinfo->cfg.msi.msi_data = data; 2475 pci_enable_msi(dev, addr, data); 2476 return (0); 2477 } 2478 } 2479 return (ENOENT); 2480 } 2481 2482 /* 2483 * For MSI-X, we check to see if we have this IRQ. If we do, 2484 * we request the updated mapping info. If that works, we go 2485 * through all the slots that use this IRQ and update them. 2486 */ 2487 if (cfg->msix.msix_alloc > 0) { 2488 bool found = false; 2489 2490 for (i = 0; i < cfg->msix.msix_alloc; i++) { 2491 mv = &cfg->msix.msix_vectors[i]; 2492 if (mv->mv_irq == irq) { 2493 error = PCIB_MAP_MSI(device_get_parent(bus), 2494 dev, irq, &addr, &data); 2495 if (error) 2496 return (error); 2497 mv->mv_address = addr; 2498 mv->mv_data = data; 2499 for (j = 0; j < cfg->msix.msix_table_len; j++) { 2500 mte = &cfg->msix.msix_table[j]; 2501 if (mte->mte_vector != i + 1) 2502 continue; 2503 if (mte->mte_handlers == 0) 2504 continue; 2505 pci_mask_msix(dev, j); 2506 pci_enable_msix(dev, j, addr, data); 2507 pci_unmask_msix(dev, j); 2508 } 2509 found = true; 2510 } 2511 } 2512 return (found ? 0 : ENOENT); 2513 } 2514 2515 return (ENOENT); 2516 } 2517 2518 /* 2519 * Returns true if the specified device is blacklisted because MSI 2520 * doesn't work. 2521 */ 2522 int 2523 pci_msi_device_blacklisted(device_t dev) 2524 { 2525 2526 if (!pci_honor_msi_blacklist) 2527 return (0); 2528 2529 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI)); 2530 } 2531 2532 /* 2533 * Determine if MSI is blacklisted globally on this system. Currently, 2534 * we just check for blacklisted chipsets as represented by the 2535 * host-PCI bridge at device 0:0:0. In the future, it may become 2536 * necessary to check other system attributes, such as the kenv values 2537 * that give the motherboard manufacturer and model number. 2538 */ 2539 static int 2540 pci_msi_blacklisted(void) 2541 { 2542 device_t dev; 2543 2544 if (!pci_honor_msi_blacklist) 2545 return (0); 2546 2547 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ 2548 if (!(pcie_chipset || pcix_chipset)) { 2549 if (vm_guest != VM_GUEST_NO) { 2550 /* 2551 * Whitelist older chipsets in virtual 2552 * machines known to support MSI. 2553 */ 2554 dev = pci_find_bsf(0, 0, 0); 2555 if (dev != NULL) 2556 return (!pci_has_quirk(pci_get_devid(dev), 2557 PCI_QUIRK_ENABLE_MSI_VM)); 2558 } 2559 return (1); 2560 } 2561 2562 dev = pci_find_bsf(0, 0, 0); 2563 if (dev != NULL) 2564 return (pci_msi_device_blacklisted(dev)); 2565 return (0); 2566 } 2567 2568 /* 2569 * Returns true if the specified device is blacklisted because MSI-X 2570 * doesn't work. Note that this assumes that if MSI doesn't work, 2571 * MSI-X doesn't either. 2572 */ 2573 int 2574 pci_msix_device_blacklisted(device_t dev) 2575 { 2576 2577 if (!pci_honor_msi_blacklist) 2578 return (0); 2579 2580 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX)) 2581 return (1); 2582 2583 return (pci_msi_device_blacklisted(dev)); 2584 } 2585 2586 /* 2587 * Determine if MSI-X is blacklisted globally on this system. If MSI 2588 * is blacklisted, assume that MSI-X is as well. Check for additional 2589 * chipsets where MSI works but MSI-X does not. 2590 */ 2591 static int 2592 pci_msix_blacklisted(void) 2593 { 2594 device_t dev; 2595 2596 if (!pci_honor_msi_blacklist) 2597 return (0); 2598 2599 dev = pci_find_bsf(0, 0, 0); 2600 if (dev != NULL && pci_has_quirk(pci_get_devid(dev), 2601 PCI_QUIRK_DISABLE_MSIX)) 2602 return (1); 2603 2604 return (pci_msi_blacklisted()); 2605 } 2606 2607 /* 2608 * Attempt to allocate *count MSI messages. The actual number allocated is 2609 * returned in *count. After this function returns, each message will be 2610 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 2611 */ 2612 int 2613 pci_alloc_msi_method(device_t dev, device_t child, int *count) 2614 { 2615 struct pci_devinfo *dinfo = device_get_ivars(child); 2616 pcicfgregs *cfg = &dinfo->cfg; 2617 struct resource_list_entry *rle; 2618 u_int actual, i; 2619 int error, irqs[32]; 2620 uint16_t ctrl, msgnum; 2621 2622 /* Don't let count == 0 get us into trouble. */ 2623 if (*count < 1) 2624 return (EINVAL); 2625 2626 /* If rid 0 is allocated, then fail. */ 2627 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 2628 if (rle != NULL && rle->res != NULL) 2629 return (ENXIO); 2630 2631 /* Already have allocated messages? */ 2632 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 2633 return (ENXIO); 2634 2635 /* If MSI is blacklisted for this system, fail. */ 2636 if (pci_msi_blacklisted()) 2637 return (ENXIO); 2638 2639 /* MSI capability present? */ 2640 if (cfg->msi.msi_location == 0 || !pci_do_msi) 2641 return (ENODEV); 2642 2643 ctrl = pci_read_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, 2); 2644 msgnum = PCI_MSI_MSGNUM(ctrl); 2645 if (bootverbose) 2646 device_printf(child, 2647 "attempting to allocate %d MSI vectors (%u supported)\n", 2648 *count, msgnum); 2649 2650 /* Don't ask for more than the device supports. */ 2651 actual = min(*count, msgnum); 2652 2653 /* Don't ask for more than 32 messages. */ 2654 actual = min(actual, 32); 2655 2656 /* MSI requires power of 2 number of messages. */ 2657 if (!powerof2(actual)) 2658 return (EINVAL); 2659 2660 for (;;) { 2661 /* Try to allocate N messages. */ 2662 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 2663 actual, irqs); 2664 if (error == 0) 2665 break; 2666 if (actual == 1) 2667 return (error); 2668 2669 /* Try N / 2. */ 2670 actual >>= 1; 2671 } 2672 2673 /* 2674 * We now have N actual messages mapped onto SYS_RES_IRQ 2675 * resources in the irqs[] array, so add new resources 2676 * starting at rid 1. 2677 */ 2678 for (i = 0; i < actual; i++) 2679 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 2680 irqs[i], irqs[i], 1); 2681 2682 if (bootverbose) { 2683 if (actual == 1) 2684 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 2685 else { 2686 bool run; 2687 2688 /* 2689 * Be fancy and try to print contiguous runs 2690 * of IRQ values as ranges. 'run' is true if 2691 * we are in a range. 2692 */ 2693 device_printf(child, "using IRQs %d", irqs[0]); 2694 run = false; 2695 for (i = 1; i < actual; i++) { 2696 /* Still in a run? */ 2697 if (irqs[i] == irqs[i - 1] + 1) { 2698 run = true; 2699 continue; 2700 } 2701 2702 /* Finish previous range. */ 2703 if (run) { 2704 printf("-%d", irqs[i - 1]); 2705 run = false; 2706 } 2707 2708 /* Start new range. */ 2709 printf(",%d", irqs[i]); 2710 } 2711 2712 /* Unfinished range? */ 2713 if (run) 2714 printf("-%d", irqs[actual - 1]); 2715 printf(" for MSI\n"); 2716 } 2717 } 2718 2719 /* Update control register with actual count. */ 2720 ctrl &= ~PCIM_MSICTRL_MME_MASK; 2721 ctrl |= (ffs(actual) - 1) << 4; 2722 cfg->msi.msi_ctrl = ctrl; 2723 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 2724 2725 /* Update counts of alloc'd messages. */ 2726 cfg->msi.msi_alloc = actual; 2727 cfg->msi.msi_handlers = 0; 2728 *count = actual; 2729 return (0); 2730 } 2731 2732 /* Release the MSI messages associated with this device. */ 2733 int 2734 pci_release_msi_method(device_t dev, device_t child) 2735 { 2736 struct pci_devinfo *dinfo = device_get_ivars(child); 2737 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2738 struct resource_list_entry *rle; 2739 u_int i, irqs[32]; 2740 int error; 2741 2742 /* Try MSI-X first. */ 2743 error = pci_release_msix(dev, child); 2744 if (error != ENODEV) 2745 return (error); 2746 2747 /* Do we have any messages to release? */ 2748 if (msi->msi_alloc == 0) 2749 return (ENODEV); 2750 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); 2751 2752 /* Make sure none of the resources are allocated. */ 2753 if (msi->msi_handlers > 0) 2754 return (EBUSY); 2755 for (i = 0; i < msi->msi_alloc; i++) { 2756 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2757 KASSERT(rle != NULL, ("missing MSI resource")); 2758 if (rle->res != NULL) 2759 return (EBUSY); 2760 irqs[i] = rle->start; 2761 } 2762 2763 /* Update control register with 0 count. */ 2764 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), 2765 ("%s: MSI still enabled", __func__)); 2766 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; 2767 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2768 msi->msi_ctrl, 2); 2769 2770 /* Release the messages. */ 2771 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); 2772 for (i = 0; i < msi->msi_alloc; i++) 2773 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2774 2775 /* Update alloc count. */ 2776 msi->msi_alloc = 0; 2777 msi->msi_addr = 0; 2778 msi->msi_data = 0; 2779 return (0); 2780 } 2781 2782 /* 2783 * Return the max supported MSI messages this device supports. 2784 * Basically, assuming the MD code can alloc messages, this function 2785 * should return the maximum value that pci_alloc_msi() can return. 2786 * Thus, it is subject to the tunables, etc. 2787 */ 2788 int 2789 pci_msi_count_method(device_t dev, device_t child) 2790 { 2791 struct pci_devinfo *dinfo = device_get_ivars(child); 2792 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2793 uint16_t ctrl; 2794 2795 if (pci_do_msi && msi->msi_location != 0) { 2796 ctrl = pci_read_config(child, msi->msi_location + PCIR_MSI_CTRL, 2797 2); 2798 return (PCI_MSI_MSGNUM(ctrl)); 2799 } 2800 return (0); 2801 } 2802 2803 /* free pcicfgregs structure and all depending data structures */ 2804 2805 int 2806 pci_freecfg(struct pci_devinfo *dinfo) 2807 { 2808 struct devlist *devlist_head; 2809 struct pci_map *pm, *next; 2810 2811 devlist_head = &pci_devq; 2812 2813 if (dinfo->cfg.vpd.vpd_reg) 2814 vpd_free(&dinfo->cfg.vpd); 2815 2816 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { 2817 free(pm, M_DEVBUF); 2818 } 2819 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 2820 free(dinfo, M_DEVBUF); 2821 2822 /* increment the generation count */ 2823 pci_generation++; 2824 2825 /* we're losing one device */ 2826 pci_numdevs--; 2827 return (0); 2828 } 2829 2830 /* 2831 * PCI power manangement 2832 */ 2833 int 2834 pci_set_powerstate_method(device_t dev, device_t child, int state) 2835 { 2836 struct pci_devinfo *dinfo = device_get_ivars(child); 2837 pcicfgregs *cfg = &dinfo->cfg; 2838 uint16_t status; 2839 int oldstate, highest, delay; 2840 2841 if (cfg->pp.pp_cap == 0) 2842 return (EOPNOTSUPP); 2843 2844 /* 2845 * Optimize a no state change request away. While it would be OK to 2846 * write to the hardware in theory, some devices have shown odd 2847 * behavior when going from D3 -> D3. 2848 */ 2849 oldstate = pci_get_powerstate(child); 2850 if (oldstate == state) 2851 return (0); 2852 2853 /* 2854 * The PCI power management specification states that after a state 2855 * transition between PCI power states, system software must 2856 * guarantee a minimal delay before the function accesses the device. 2857 * Compute the worst case delay that we need to guarantee before we 2858 * access the device. Many devices will be responsive much more 2859 * quickly than this delay, but there are some that don't respond 2860 * instantly to state changes. Transitions to/from D3 state require 2861 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 2862 * is done below with DELAY rather than a sleeper function because 2863 * this function can be called from contexts where we cannot sleep. 2864 */ 2865 highest = (oldstate > state) ? oldstate : state; 2866 if (highest == PCI_POWERSTATE_D3) 2867 delay = 10000; 2868 else if (highest == PCI_POWERSTATE_D2) 2869 delay = 200; 2870 else 2871 delay = 0; 2872 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 2873 & ~PCIM_PSTAT_DMASK; 2874 switch (state) { 2875 case PCI_POWERSTATE_D0: 2876 status |= PCIM_PSTAT_D0; 2877 break; 2878 case PCI_POWERSTATE_D1: 2879 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 2880 return (EOPNOTSUPP); 2881 status |= PCIM_PSTAT_D1; 2882 break; 2883 case PCI_POWERSTATE_D2: 2884 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 2885 return (EOPNOTSUPP); 2886 status |= PCIM_PSTAT_D2; 2887 break; 2888 case PCI_POWERSTATE_D3: 2889 status |= PCIM_PSTAT_D3; 2890 break; 2891 default: 2892 return (EINVAL); 2893 } 2894 2895 if (bootverbose) 2896 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate, 2897 state); 2898 2899 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 2900 if (delay) 2901 DELAY(delay); 2902 return (0); 2903 } 2904 2905 int 2906 pci_get_powerstate_method(device_t dev, device_t child) 2907 { 2908 struct pci_devinfo *dinfo = device_get_ivars(child); 2909 pcicfgregs *cfg = &dinfo->cfg; 2910 uint16_t status; 2911 int result; 2912 2913 if (cfg->pp.pp_cap != 0) { 2914 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 2915 switch (status & PCIM_PSTAT_DMASK) { 2916 case PCIM_PSTAT_D0: 2917 result = PCI_POWERSTATE_D0; 2918 break; 2919 case PCIM_PSTAT_D1: 2920 result = PCI_POWERSTATE_D1; 2921 break; 2922 case PCIM_PSTAT_D2: 2923 result = PCI_POWERSTATE_D2; 2924 break; 2925 case PCIM_PSTAT_D3: 2926 result = PCI_POWERSTATE_D3; 2927 break; 2928 default: 2929 result = PCI_POWERSTATE_UNKNOWN; 2930 break; 2931 } 2932 } else { 2933 /* No support, device is always at D0 */ 2934 result = PCI_POWERSTATE_D0; 2935 } 2936 return (result); 2937 } 2938 2939 /* 2940 * Some convenience functions for PCI device drivers. 2941 */ 2942 2943 static __inline void 2944 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 2945 { 2946 uint16_t command; 2947 2948 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2949 command |= bit; 2950 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2951 } 2952 2953 static __inline void 2954 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 2955 { 2956 uint16_t command; 2957 2958 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2959 command &= ~bit; 2960 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2961 } 2962 2963 int 2964 pci_enable_busmaster_method(device_t dev, device_t child) 2965 { 2966 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2967 return (0); 2968 } 2969 2970 int 2971 pci_disable_busmaster_method(device_t dev, device_t child) 2972 { 2973 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2974 return (0); 2975 } 2976 2977 int 2978 pci_enable_io_method(device_t dev, device_t child, int space) 2979 { 2980 uint16_t bit; 2981 2982 switch(space) { 2983 case SYS_RES_IOPORT: 2984 bit = PCIM_CMD_PORTEN; 2985 break; 2986 case SYS_RES_MEMORY: 2987 bit = PCIM_CMD_MEMEN; 2988 break; 2989 default: 2990 return (EINVAL); 2991 } 2992 pci_set_command_bit(dev, child, bit); 2993 return (0); 2994 } 2995 2996 int 2997 pci_disable_io_method(device_t dev, device_t child, int space) 2998 { 2999 uint16_t bit; 3000 3001 switch(space) { 3002 case SYS_RES_IOPORT: 3003 bit = PCIM_CMD_PORTEN; 3004 break; 3005 case SYS_RES_MEMORY: 3006 bit = PCIM_CMD_MEMEN; 3007 break; 3008 default: 3009 return (EINVAL); 3010 } 3011 pci_clear_command_bit(dev, child, bit); 3012 return (0); 3013 } 3014 3015 /* 3016 * New style pci driver. Parent device is either a pci-host-bridge or a 3017 * pci-pci-bridge. Both kinds are represented by instances of pcib. 3018 */ 3019 3020 void 3021 pci_print_verbose(struct pci_devinfo *dinfo) 3022 { 3023 3024 if (bootverbose) { 3025 pcicfgregs *cfg = &dinfo->cfg; 3026 3027 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 3028 cfg->vendor, cfg->device, cfg->revid); 3029 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n", 3030 cfg->domain, cfg->bus, cfg->slot, cfg->func); 3031 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 3032 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 3033 cfg->mfdev); 3034 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 3035 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 3036 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 3037 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 3038 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 3039 if (cfg->intpin > 0) 3040 printf("\tintpin=%c, irq=%d\n", 3041 cfg->intpin +'a' -1, cfg->intline); 3042 if (cfg->pp.pp_cap) { 3043 uint16_t status; 3044 3045 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 3046 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 3047 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 3048 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 3049 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 3050 status & PCIM_PSTAT_DMASK); 3051 } 3052 if (cfg->msi.msi_location) { 3053 uint16_t ctrl, msgnum; 3054 3055 ctrl = cfg->msi.msi_ctrl; 3056 msgnum = PCI_MSI_MSGNUM(ctrl); 3057 printf("\tMSI supports %d message%s%s%s\n", 3058 msgnum, (msgnum == 1) ? "" : "s", 3059 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 3060 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 3061 } 3062 if (cfg->msix.msix_location) { 3063 uint16_t msgnum; 3064 3065 msgnum = PCI_MSIX_MSGNUM(cfg->msix.msix_ctrl); 3066 printf("\tMSI-X supports %d message%s ", 3067 msgnum, (msgnum == 1) ? "" : "s"); 3068 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 3069 printf("in map 0x%x\n", 3070 cfg->msix.msix_table_bar); 3071 else 3072 printf("in maps 0x%x and 0x%x\n", 3073 cfg->msix.msix_table_bar, 3074 cfg->msix.msix_pba_bar); 3075 } 3076 } 3077 } 3078 3079 static int 3080 pci_porten(device_t dev) 3081 { 3082 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0; 3083 } 3084 3085 static int 3086 pci_memen(device_t dev) 3087 { 3088 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0; 3089 } 3090 3091 void 3092 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, 3093 int *bar64) 3094 { 3095 struct pci_devinfo *dinfo; 3096 pci_addr_t map, testval; 3097 int ln2range; 3098 uint16_t cmd; 3099 3100 /* 3101 * The device ROM BAR is special. It is always a 32-bit 3102 * memory BAR. Bit 0 is special and should not be set when 3103 * sizing the BAR. 3104 */ 3105 dinfo = device_get_ivars(dev); 3106 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { 3107 map = pci_read_config(dev, reg, 4); 3108 pci_write_config(dev, reg, 0xfffffffe, 4); 3109 testval = pci_read_config(dev, reg, 4); 3110 pci_write_config(dev, reg, map, 4); 3111 *mapp = map; 3112 *testvalp = testval; 3113 if (bar64 != NULL) 3114 *bar64 = 0; 3115 return; 3116 } 3117 3118 map = pci_read_config(dev, reg, 4); 3119 ln2range = pci_maprange(map); 3120 if (ln2range == 64) 3121 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3122 3123 /* 3124 * Disable decoding via the command register before 3125 * determining the BAR's length since we will be placing it in 3126 * a weird state. 3127 */ 3128 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3129 pci_write_config(dev, PCIR_COMMAND, 3130 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 3131 3132 /* 3133 * Determine the BAR's length by writing all 1's. The bottom 3134 * log_2(size) bits of the BAR will stick as 0 when we read 3135 * the value back. 3136 * 3137 * NB: according to the PCI Local Bus Specification, rev. 3.0: 3138 * "Software writes 0FFFFFFFFh to both registers, reads them back, 3139 * and combines the result into a 64-bit value." (section 6.2.5.1) 3140 * 3141 * Writes to both registers must be performed before attempting to 3142 * read back the size value. 3143 */ 3144 testval = 0; 3145 pci_write_config(dev, reg, 0xffffffff, 4); 3146 if (ln2range == 64) { 3147 pci_write_config(dev, reg + 4, 0xffffffff, 4); 3148 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3149 } 3150 testval |= pci_read_config(dev, reg, 4); 3151 3152 /* 3153 * Restore the original value of the BAR. We may have reprogrammed 3154 * the BAR of the low-level console device and when booting verbose, 3155 * we need the console device addressable. 3156 */ 3157 pci_write_config(dev, reg, map, 4); 3158 if (ln2range == 64) 3159 pci_write_config(dev, reg + 4, map >> 32, 4); 3160 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3161 3162 *mapp = map; 3163 *testvalp = testval; 3164 if (bar64 != NULL) 3165 *bar64 = (ln2range == 64); 3166 } 3167 3168 static void 3169 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base) 3170 { 3171 struct pci_devinfo *dinfo; 3172 int ln2range; 3173 3174 /* The device ROM BAR is always a 32-bit memory BAR. */ 3175 dinfo = device_get_ivars(dev); 3176 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3177 ln2range = 32; 3178 else 3179 ln2range = pci_maprange(pm->pm_value); 3180 pci_write_config(dev, pm->pm_reg, base, 4); 3181 if (ln2range == 64) 3182 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); 3183 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); 3184 if (ln2range == 64) 3185 pm->pm_value |= (pci_addr_t)pci_read_config(dev, 3186 pm->pm_reg + 4, 4) << 32; 3187 } 3188 3189 struct pci_map * 3190 pci_find_bar(device_t dev, int reg) 3191 { 3192 struct pci_devinfo *dinfo; 3193 struct pci_map *pm; 3194 3195 dinfo = device_get_ivars(dev); 3196 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3197 if (pm->pm_reg == reg) 3198 return (pm); 3199 } 3200 return (NULL); 3201 } 3202 3203 struct pci_map * 3204 pci_first_bar(device_t dev) 3205 { 3206 struct pci_devinfo *dinfo; 3207 3208 dinfo = device_get_ivars(dev); 3209 return (STAILQ_FIRST(&dinfo->cfg.maps)); 3210 } 3211 3212 struct pci_map * 3213 pci_next_bar(struct pci_map *pm) 3214 { 3215 return (STAILQ_NEXT(pm, pm_link)); 3216 } 3217 3218 int 3219 pci_bar_enabled(device_t dev, struct pci_map *pm) 3220 { 3221 struct pci_devinfo *dinfo; 3222 uint16_t cmd; 3223 3224 dinfo = device_get_ivars(dev); 3225 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && 3226 !(pm->pm_value & PCIM_BIOS_ENABLE)) 3227 return (0); 3228 #ifdef PCI_IOV 3229 if ((dinfo->cfg.flags & PCICFG_VF) != 0) { 3230 struct pcicfg_iov *iov; 3231 3232 iov = dinfo->cfg.iov; 3233 cmd = pci_read_config(iov->iov_pf, 3234 iov->iov_pos + PCIR_SRIOV_CTL, 2); 3235 return ((cmd & PCIM_SRIOV_VF_MSE) != 0); 3236 } 3237 #endif 3238 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3239 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) 3240 return ((cmd & PCIM_CMD_MEMEN) != 0); 3241 else 3242 return ((cmd & PCIM_CMD_PORTEN) != 0); 3243 } 3244 3245 struct pci_map * 3246 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size) 3247 { 3248 struct pci_devinfo *dinfo; 3249 struct pci_map *pm, *prev; 3250 3251 dinfo = device_get_ivars(dev); 3252 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO); 3253 pm->pm_reg = reg; 3254 pm->pm_value = value; 3255 pm->pm_size = size; 3256 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { 3257 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", 3258 reg)); 3259 if (STAILQ_NEXT(prev, pm_link) == NULL || 3260 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) 3261 break; 3262 } 3263 if (prev != NULL) 3264 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); 3265 else 3266 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); 3267 return (pm); 3268 } 3269 3270 static void 3271 pci_restore_bars(device_t dev) 3272 { 3273 struct pci_devinfo *dinfo; 3274 struct pci_map *pm; 3275 int ln2range; 3276 3277 dinfo = device_get_ivars(dev); 3278 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3279 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3280 ln2range = 32; 3281 else 3282 ln2range = pci_maprange(pm->pm_value); 3283 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); 3284 if (ln2range == 64) 3285 pci_write_config(dev, pm->pm_reg + 4, 3286 pm->pm_value >> 32, 4); 3287 } 3288 } 3289 3290 /* 3291 * Add a resource based on a pci map register. Return 1 if the map 3292 * register is a 32bit map register or 2 if it is a 64bit register. 3293 */ 3294 static int 3295 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, 3296 int force, int prefetch) 3297 { 3298 struct pci_map *pm; 3299 pci_addr_t base, map, testval; 3300 pci_addr_t start, end, count; 3301 int barlen, basezero, flags, maprange, mapsize, type; 3302 uint16_t cmd; 3303 struct resource *res; 3304 3305 /* 3306 * The BAR may already exist if the device is a CardBus card 3307 * whose CIS is stored in this BAR. 3308 */ 3309 pm = pci_find_bar(dev, reg); 3310 if (pm != NULL) { 3311 maprange = pci_maprange(pm->pm_value); 3312 barlen = maprange == 64 ? 2 : 1; 3313 return (barlen); 3314 } 3315 3316 pci_read_bar(dev, reg, &map, &testval, NULL); 3317 if (PCI_BAR_MEM(map)) { 3318 type = SYS_RES_MEMORY; 3319 if (map & PCIM_BAR_MEM_PREFETCH) 3320 prefetch = 1; 3321 } else 3322 type = SYS_RES_IOPORT; 3323 mapsize = pci_mapsize(testval); 3324 base = pci_mapbase(map); 3325 #ifdef __PCI_BAR_ZERO_VALID 3326 basezero = 0; 3327 #else 3328 basezero = base == 0; 3329 #endif 3330 maprange = pci_maprange(map); 3331 barlen = maprange == 64 ? 2 : 1; 3332 3333 /* 3334 * For I/O registers, if bottom bit is set, and the next bit up 3335 * isn't clear, we know we have a BAR that doesn't conform to the 3336 * spec, so ignore it. Also, sanity check the size of the data 3337 * areas to the type of memory involved. Memory must be at least 3338 * 16 bytes in size, while I/O ranges must be at least 4. 3339 */ 3340 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0) 3341 return (barlen); 3342 if ((type == SYS_RES_MEMORY && mapsize < 4) || 3343 (type == SYS_RES_IOPORT && mapsize < 2)) 3344 return (barlen); 3345 3346 /* Save a record of this BAR. */ 3347 pm = pci_add_bar(dev, reg, map, mapsize); 3348 if (bootverbose) { 3349 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d", 3350 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize); 3351 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3352 printf(", port disabled\n"); 3353 else if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3354 printf(", memory disabled\n"); 3355 else 3356 printf(", enabled\n"); 3357 } 3358 3359 /* 3360 * If base is 0, then we have problems if this architecture does 3361 * not allow that. It is best to ignore such entries for the 3362 * moment. These will be allocated later if the driver specifically 3363 * requests them. However, some removable buses look better when 3364 * all resources are allocated, so allow '0' to be overridden. 3365 * 3366 * Similarly treat maps whose values is the same as the test value 3367 * read back. These maps have had all f's written to them by the 3368 * BIOS in an attempt to disable the resources. 3369 */ 3370 if (!force && (basezero || map == testval)) 3371 return (barlen); 3372 if ((u_long)base != base) { 3373 device_printf(bus, 3374 "pci%d:%d:%d:%d bar %#x too many address bits", 3375 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev), 3376 pci_get_function(dev), reg); 3377 return (barlen); 3378 } 3379 3380 /* 3381 * This code theoretically does the right thing, but has 3382 * undesirable side effects in some cases where peripherals 3383 * respond oddly to having these bits enabled. Let the user 3384 * be able to turn them off (since pci_enable_io_modes is 1 by 3385 * default). 3386 */ 3387 if (pci_enable_io_modes) { 3388 /* Turn on resources that have been left off by a lazy BIOS */ 3389 if (type == SYS_RES_IOPORT && !pci_porten(dev)) { 3390 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3391 cmd |= PCIM_CMD_PORTEN; 3392 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3393 } 3394 if (type == SYS_RES_MEMORY && !pci_memen(dev)) { 3395 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3396 cmd |= PCIM_CMD_MEMEN; 3397 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3398 } 3399 } else { 3400 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3401 return (barlen); 3402 if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3403 return (barlen); 3404 } 3405 3406 count = (pci_addr_t)1 << mapsize; 3407 flags = RF_ALIGNMENT_LOG2(mapsize); 3408 if (prefetch) 3409 flags |= RF_PREFETCHABLE; 3410 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) { 3411 start = 0; /* Let the parent decide. */ 3412 end = ~0; 3413 } else { 3414 start = base; 3415 end = base + count - 1; 3416 } 3417 resource_list_add(rl, type, reg, start, end, count); 3418 3419 /* 3420 * Try to allocate the resource for this BAR from our parent 3421 * so that this resource range is already reserved. The 3422 * driver for this device will later inherit this resource in 3423 * pci_alloc_resource(). 3424 */ 3425 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count, 3426 flags); 3427 if ((pci_do_realloc_bars 3428 || pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_REALLOC_BAR)) 3429 && res == NULL && (start != 0 || end != ~0)) { 3430 /* 3431 * If the allocation fails, try to allocate a resource for 3432 * this BAR using any available range. The firmware felt 3433 * it was important enough to assign a resource, so don't 3434 * disable decoding if we can help it. 3435 */ 3436 resource_list_delete(rl, type, reg); 3437 resource_list_add(rl, type, reg, 0, ~0, count); 3438 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0, 3439 count, flags); 3440 } 3441 if (res == NULL) { 3442 /* 3443 * If the allocation fails, delete the resource list entry 3444 * and disable decoding for this device. 3445 * 3446 * If the driver requests this resource in the future, 3447 * pci_reserve_map() will try to allocate a fresh 3448 * resource range. 3449 */ 3450 resource_list_delete(rl, type, reg); 3451 pci_disable_io(dev, type); 3452 if (bootverbose) 3453 device_printf(bus, 3454 "pci%d:%d:%d:%d bar %#x failed to allocate\n", 3455 pci_get_domain(dev), pci_get_bus(dev), 3456 pci_get_slot(dev), pci_get_function(dev), reg); 3457 } else { 3458 start = rman_get_start(res); 3459 pci_write_bar(dev, pm, start); 3460 } 3461 return (barlen); 3462 } 3463 3464 /* 3465 * For ATA devices we need to decide early what addressing mode to use. 3466 * Legacy demands that the primary and secondary ATA ports sits on the 3467 * same addresses that old ISA hardware did. This dictates that we use 3468 * those addresses and ignore the BAR's if we cannot set PCI native 3469 * addressing mode. 3470 */ 3471 static void 3472 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, 3473 uint32_t prefetchmask) 3474 { 3475 int rid, type, progif; 3476 #if 0 3477 /* if this device supports PCI native addressing use it */ 3478 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3479 if ((progif & 0x8a) == 0x8a) { 3480 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 3481 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 3482 printf("Trying ATA native PCI addressing mode\n"); 3483 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 3484 } 3485 } 3486 #endif 3487 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3488 type = SYS_RES_IOPORT; 3489 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 3490 pci_add_map(bus, dev, PCIR_BAR(0), rl, force, 3491 prefetchmask & (1 << 0)); 3492 pci_add_map(bus, dev, PCIR_BAR(1), rl, force, 3493 prefetchmask & (1 << 1)); 3494 } else { 3495 rid = PCIR_BAR(0); 3496 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 3497 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0, 3498 0x1f7, 8, 0); 3499 rid = PCIR_BAR(1); 3500 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 3501 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6, 3502 0x3f6, 1, 0); 3503 } 3504 if (progif & PCIP_STORAGE_IDE_MODESEC) { 3505 pci_add_map(bus, dev, PCIR_BAR(2), rl, force, 3506 prefetchmask & (1 << 2)); 3507 pci_add_map(bus, dev, PCIR_BAR(3), rl, force, 3508 prefetchmask & (1 << 3)); 3509 } else { 3510 rid = PCIR_BAR(2); 3511 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 3512 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170, 3513 0x177, 8, 0); 3514 rid = PCIR_BAR(3); 3515 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 3516 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376, 3517 0x376, 1, 0); 3518 } 3519 pci_add_map(bus, dev, PCIR_BAR(4), rl, force, 3520 prefetchmask & (1 << 4)); 3521 pci_add_map(bus, dev, PCIR_BAR(5), rl, force, 3522 prefetchmask & (1 << 5)); 3523 } 3524 3525 static void 3526 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 3527 { 3528 struct pci_devinfo *dinfo = device_get_ivars(dev); 3529 pcicfgregs *cfg = &dinfo->cfg; 3530 char tunable_name[64]; 3531 int irq; 3532 3533 /* Has to have an intpin to have an interrupt. */ 3534 if (cfg->intpin == 0) 3535 return; 3536 3537 /* Let the user override the IRQ with a tunable. */ 3538 irq = PCI_INVALID_IRQ; 3539 snprintf(tunable_name, sizeof(tunable_name), 3540 "hw.pci%d.%d.%d.INT%c.irq", 3541 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 3542 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 3543 irq = PCI_INVALID_IRQ; 3544 3545 /* 3546 * If we didn't get an IRQ via the tunable, then we either use the 3547 * IRQ value in the intline register or we ask the bus to route an 3548 * interrupt for us. If force_route is true, then we only use the 3549 * value in the intline register if the bus was unable to assign an 3550 * IRQ. 3551 */ 3552 if (!PCI_INTERRUPT_VALID(irq)) { 3553 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 3554 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 3555 if (!PCI_INTERRUPT_VALID(irq)) 3556 irq = cfg->intline; 3557 } 3558 3559 /* If after all that we don't have an IRQ, just bail. */ 3560 if (!PCI_INTERRUPT_VALID(irq)) 3561 return; 3562 3563 /* Update the config register if it changed. */ 3564 if (irq != cfg->intline) { 3565 cfg->intline = irq; 3566 pci_write_config(dev, PCIR_INTLINE, irq, 1); 3567 } 3568 3569 /* Add this IRQ as rid 0 interrupt resource. */ 3570 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 3571 } 3572 3573 /* Perform early OHCI takeover from SMM. */ 3574 static void 3575 ohci_early_takeover(device_t self) 3576 { 3577 struct resource *res; 3578 uint32_t ctl; 3579 int rid; 3580 int i; 3581 3582 rid = PCIR_BAR(0); 3583 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3584 if (res == NULL) 3585 return; 3586 3587 ctl = bus_read_4(res, OHCI_CONTROL); 3588 if (ctl & OHCI_IR) { 3589 if (bootverbose) 3590 printf("ohci early: " 3591 "SMM active, request owner change\n"); 3592 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR); 3593 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 3594 DELAY(1000); 3595 ctl = bus_read_4(res, OHCI_CONTROL); 3596 } 3597 if (ctl & OHCI_IR) { 3598 if (bootverbose) 3599 printf("ohci early: " 3600 "SMM does not respond, resetting\n"); 3601 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET); 3602 } 3603 /* Disable interrupts */ 3604 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 3605 } 3606 3607 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3608 } 3609 3610 /* Perform early UHCI takeover from SMM. */ 3611 static void 3612 uhci_early_takeover(device_t self) 3613 { 3614 struct resource *res; 3615 int rid; 3616 3617 /* 3618 * Set the PIRQD enable bit and switch off all the others. We don't 3619 * want legacy support to interfere with us XXX Does this also mean 3620 * that the BIOS won't touch the keyboard anymore if it is connected 3621 * to the ports of the root hub? 3622 */ 3623 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2); 3624 3625 /* Disable interrupts */ 3626 rid = PCI_UHCI_BASE_REG; 3627 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE); 3628 if (res != NULL) { 3629 bus_write_2(res, UHCI_INTR, 0); 3630 bus_release_resource(self, SYS_RES_IOPORT, rid, res); 3631 } 3632 } 3633 3634 /* Perform early EHCI takeover from SMM. */ 3635 static void 3636 ehci_early_takeover(device_t self) 3637 { 3638 struct resource *res; 3639 uint32_t cparams; 3640 uint32_t eec; 3641 uint8_t eecp; 3642 uint8_t bios_sem; 3643 uint8_t offs; 3644 int rid; 3645 int i; 3646 3647 rid = PCIR_BAR(0); 3648 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3649 if (res == NULL) 3650 return; 3651 3652 cparams = bus_read_4(res, EHCI_HCCPARAMS); 3653 3654 /* Synchronise with the BIOS if it owns the controller. */ 3655 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0; 3656 eecp = EHCI_EECP_NEXT(eec)) { 3657 eec = pci_read_config(self, eecp, 4); 3658 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) { 3659 continue; 3660 } 3661 bios_sem = pci_read_config(self, eecp + 3662 EHCI_LEGSUP_BIOS_SEM, 1); 3663 if (bios_sem == 0) { 3664 continue; 3665 } 3666 if (bootverbose) 3667 printf("ehci early: " 3668 "SMM active, request owner change\n"); 3669 3670 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1); 3671 3672 for (i = 0; (i < 100) && (bios_sem != 0); i++) { 3673 DELAY(1000); 3674 bios_sem = pci_read_config(self, eecp + 3675 EHCI_LEGSUP_BIOS_SEM, 1); 3676 } 3677 3678 if (bios_sem != 0) { 3679 if (bootverbose) 3680 printf("ehci early: " 3681 "SMM does not respond\n"); 3682 } 3683 /* Disable interrupts */ 3684 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION)); 3685 bus_write_4(res, offs + EHCI_USBINTR, 0); 3686 } 3687 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3688 } 3689 3690 /* Perform early XHCI takeover from SMM. */ 3691 static void 3692 xhci_early_takeover(device_t self) 3693 { 3694 struct resource *res; 3695 uint32_t cparams; 3696 uint32_t eec; 3697 uint8_t eecp; 3698 uint8_t bios_sem; 3699 uint8_t offs; 3700 int rid; 3701 int i; 3702 3703 rid = PCIR_BAR(0); 3704 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3705 if (res == NULL) 3706 return; 3707 3708 cparams = bus_read_4(res, XHCI_HCSPARAMS0); 3709 3710 eec = -1; 3711 3712 /* Synchronise with the BIOS if it owns the controller. */ 3713 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 3714 eecp += XHCI_XECP_NEXT(eec) << 2) { 3715 eec = bus_read_4(res, eecp); 3716 3717 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 3718 continue; 3719 3720 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM); 3721 if (bios_sem == 0) 3722 continue; 3723 3724 if (bootverbose) 3725 printf("xhci early: " 3726 "SMM active, request owner change\n"); 3727 3728 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1); 3729 3730 /* wait a maximum of 5 second */ 3731 3732 for (i = 0; (i < 5000) && (bios_sem != 0); i++) { 3733 DELAY(1000); 3734 bios_sem = bus_read_1(res, eecp + 3735 XHCI_XECP_BIOS_SEM); 3736 } 3737 3738 if (bios_sem != 0) { 3739 if (bootverbose) 3740 printf("xhci early: " 3741 "SMM does not respond\n"); 3742 } 3743 3744 /* Disable interrupts */ 3745 offs = bus_read_1(res, XHCI_CAPLENGTH); 3746 bus_write_4(res, offs + XHCI_USBCMD, 0); 3747 bus_read_4(res, offs + XHCI_USBSTS); 3748 } 3749 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3750 } 3751 3752 static void 3753 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg, 3754 struct resource_list *rl) 3755 { 3756 struct resource *res; 3757 char *cp; 3758 rman_res_t start, end, count; 3759 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus; 3760 3761 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3762 case PCIM_HDRTYPE_BRIDGE: 3763 sec_reg = PCIR_SECBUS_1; 3764 sub_reg = PCIR_SUBBUS_1; 3765 break; 3766 case PCIM_HDRTYPE_CARDBUS: 3767 sec_reg = PCIR_SECBUS_2; 3768 sub_reg = PCIR_SUBBUS_2; 3769 break; 3770 default: 3771 return; 3772 } 3773 3774 /* 3775 * If the existing bus range is valid, attempt to reserve it 3776 * from our parent. If this fails for any reason, clear the 3777 * secbus and subbus registers. 3778 * 3779 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus? 3780 * This would at least preserve the existing sec_bus if it is 3781 * valid. 3782 */ 3783 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1); 3784 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1); 3785 3786 /* Quirk handling. */ 3787 switch (pci_get_devid(dev)) { 3788 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 3789 sup_bus = pci_read_config(dev, 0x41, 1); 3790 if (sup_bus != 0xff) { 3791 sec_bus = sup_bus + 1; 3792 sub_bus = sup_bus + 1; 3793 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1); 3794 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3795 } 3796 break; 3797 3798 case 0x00dd10de: 3799 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 3800 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 3801 break; 3802 if (strncmp(cp, "Compal", 6) != 0) { 3803 freeenv(cp); 3804 break; 3805 } 3806 freeenv(cp); 3807 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 3808 break; 3809 if (strncmp(cp, "08A0", 4) != 0) { 3810 freeenv(cp); 3811 break; 3812 } 3813 freeenv(cp); 3814 if (sub_bus < 0xa) { 3815 sub_bus = 0xa; 3816 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3817 } 3818 break; 3819 } 3820 3821 if (bootverbose) 3822 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus); 3823 if (sec_bus > 0 && sub_bus >= sec_bus) { 3824 start = sec_bus; 3825 end = sub_bus; 3826 count = end - start + 1; 3827 3828 resource_list_add(rl, PCI_RES_BUS, 0, 0, ~0, count); 3829 3830 /* 3831 * If requested, clear secondary bus registers in 3832 * bridge devices to force a complete renumbering 3833 * rather than reserving the existing range. However, 3834 * preserve the existing size. 3835 */ 3836 if (pci_clear_buses) 3837 goto clear; 3838 3839 rid = 0; 3840 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid, 3841 start, end, count, 0); 3842 if (res != NULL) 3843 return; 3844 3845 if (bootverbose) 3846 device_printf(bus, 3847 "pci%d:%d:%d:%d secbus failed to allocate\n", 3848 pci_get_domain(dev), pci_get_bus(dev), 3849 pci_get_slot(dev), pci_get_function(dev)); 3850 } 3851 3852 clear: 3853 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1); 3854 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1); 3855 } 3856 3857 static struct resource * 3858 pci_alloc_secbus(device_t dev, device_t child, int *rid, rman_res_t start, 3859 rman_res_t end, rman_res_t count, u_int flags) 3860 { 3861 struct pci_devinfo *dinfo; 3862 pcicfgregs *cfg; 3863 struct resource_list *rl; 3864 struct resource *res; 3865 int sec_reg, sub_reg; 3866 3867 dinfo = device_get_ivars(child); 3868 cfg = &dinfo->cfg; 3869 rl = &dinfo->resources; 3870 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3871 case PCIM_HDRTYPE_BRIDGE: 3872 sec_reg = PCIR_SECBUS_1; 3873 sub_reg = PCIR_SUBBUS_1; 3874 break; 3875 case PCIM_HDRTYPE_CARDBUS: 3876 sec_reg = PCIR_SECBUS_2; 3877 sub_reg = PCIR_SUBBUS_2; 3878 break; 3879 default: 3880 return (NULL); 3881 } 3882 3883 if (*rid != 0) 3884 return (NULL); 3885 3886 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL) 3887 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count); 3888 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) { 3889 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid, 3890 start, end, count, flags & ~RF_ACTIVE); 3891 if (res == NULL) { 3892 resource_list_delete(rl, PCI_RES_BUS, *rid); 3893 device_printf(child, "allocating %ju bus%s failed\n", 3894 count, count == 1 ? "" : "es"); 3895 return (NULL); 3896 } 3897 if (bootverbose) 3898 device_printf(child, 3899 "Lazy allocation of %ju bus%s at %ju\n", count, 3900 count == 1 ? "" : "es", rman_get_start(res)); 3901 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1); 3902 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1); 3903 } 3904 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start, 3905 end, count, flags)); 3906 } 3907 3908 static int 3909 pci_ea_bei_to_rid(device_t dev, int bei) 3910 { 3911 #ifdef PCI_IOV 3912 struct pci_devinfo *dinfo; 3913 int iov_pos; 3914 struct pcicfg_iov *iov; 3915 3916 dinfo = device_get_ivars(dev); 3917 iov = dinfo->cfg.iov; 3918 if (iov != NULL) 3919 iov_pos = iov->iov_pos; 3920 else 3921 iov_pos = 0; 3922 #endif 3923 3924 /* Check if matches BAR */ 3925 if ((bei >= PCIM_EA_BEI_BAR_0) && 3926 (bei <= PCIM_EA_BEI_BAR_5)) 3927 return (PCIR_BAR(bei)); 3928 3929 /* Check ROM */ 3930 if (bei == PCIM_EA_BEI_ROM) 3931 return (PCIR_BIOS); 3932 3933 #ifdef PCI_IOV 3934 /* Check if matches VF_BAR */ 3935 if ((iov != NULL) && (bei >= PCIM_EA_BEI_VF_BAR_0) && 3936 (bei <= PCIM_EA_BEI_VF_BAR_5)) 3937 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) + 3938 iov_pos); 3939 #endif 3940 3941 return (-1); 3942 } 3943 3944 int 3945 pci_ea_is_enabled(device_t dev, int rid) 3946 { 3947 struct pci_ea_entry *ea; 3948 struct pci_devinfo *dinfo; 3949 3950 dinfo = device_get_ivars(dev); 3951 3952 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3953 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid) 3954 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0); 3955 } 3956 3957 return (0); 3958 } 3959 3960 void 3961 pci_add_resources_ea(device_t bus, device_t dev, int alloc_iov) 3962 { 3963 struct pci_ea_entry *ea; 3964 struct pci_devinfo *dinfo; 3965 pci_addr_t start, end, count; 3966 struct resource_list *rl; 3967 int type, flags, rid; 3968 struct resource *res; 3969 uint32_t tmp; 3970 #ifdef PCI_IOV 3971 struct pcicfg_iov *iov; 3972 #endif 3973 3974 dinfo = device_get_ivars(dev); 3975 rl = &dinfo->resources; 3976 flags = 0; 3977 3978 #ifdef PCI_IOV 3979 iov = dinfo->cfg.iov; 3980 #endif 3981 3982 if (dinfo->cfg.ea.ea_location == 0) 3983 return; 3984 3985 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3986 /* 3987 * TODO: Ignore EA-BAR if is not enabled. 3988 * Currently the EA implementation supports 3989 * only situation, where EA structure contains 3990 * predefined entries. In case they are not enabled 3991 * leave them unallocated and proceed with 3992 * a legacy-BAR mechanism. 3993 */ 3994 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0) 3995 continue; 3996 3997 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) { 3998 case PCIM_EA_P_MEM_PREFETCH: 3999 case PCIM_EA_P_VF_MEM_PREFETCH: 4000 flags = RF_PREFETCHABLE; 4001 /* FALLTHROUGH */ 4002 case PCIM_EA_P_VF_MEM: 4003 case PCIM_EA_P_MEM: 4004 type = SYS_RES_MEMORY; 4005 break; 4006 case PCIM_EA_P_IO: 4007 type = SYS_RES_IOPORT; 4008 break; 4009 default: 4010 continue; 4011 } 4012 4013 if (alloc_iov != 0) { 4014 #ifdef PCI_IOV 4015 /* Allocating IOV, confirm BEI matches */ 4016 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) || 4017 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5)) 4018 continue; 4019 #else 4020 continue; 4021 #endif 4022 } else { 4023 /* Allocating BAR, confirm BEI matches */ 4024 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) || 4025 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) && 4026 (ea->eae_bei != PCIM_EA_BEI_ROM)) 4027 continue; 4028 } 4029 4030 rid = pci_ea_bei_to_rid(dev, ea->eae_bei); 4031 if (rid < 0) 4032 continue; 4033 4034 /* Skip resources already allocated by EA */ 4035 if ((resource_list_find(rl, SYS_RES_MEMORY, rid) != NULL) || 4036 (resource_list_find(rl, SYS_RES_IOPORT, rid) != NULL)) 4037 continue; 4038 4039 start = ea->eae_base; 4040 count = ea->eae_max_offset + 1; 4041 #ifdef PCI_IOV 4042 if (iov != NULL) 4043 count = count * iov->iov_num_vfs; 4044 #endif 4045 end = start + count - 1; 4046 if (count == 0) 4047 continue; 4048 4049 resource_list_add(rl, type, rid, start, end, count); 4050 res = resource_list_reserve(rl, bus, dev, type, &rid, start, end, count, 4051 flags); 4052 if (res == NULL) { 4053 resource_list_delete(rl, type, rid); 4054 4055 /* 4056 * Failed to allocate using EA, disable entry. 4057 * Another attempt to allocation will be performed 4058 * further, but this time using legacy BAR registers 4059 */ 4060 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4); 4061 tmp &= ~PCIM_EA_ENABLE; 4062 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4); 4063 4064 /* 4065 * Disabling entry might fail in case it is hardwired. 4066 * Read flags again to match current status. 4067 */ 4068 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4); 4069 4070 continue; 4071 } 4072 4073 /* As per specification, fill BAR with zeros */ 4074 pci_write_config(dev, rid, 0, 4); 4075 } 4076 } 4077 4078 void 4079 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 4080 { 4081 struct pci_devinfo *dinfo; 4082 pcicfgregs *cfg; 4083 struct resource_list *rl; 4084 const struct pci_quirk *q; 4085 uint32_t devid; 4086 int i; 4087 4088 dinfo = device_get_ivars(dev); 4089 cfg = &dinfo->cfg; 4090 rl = &dinfo->resources; 4091 devid = (cfg->device << 16) | cfg->vendor; 4092 4093 /* Allocate resources using Enhanced Allocation */ 4094 pci_add_resources_ea(bus, dev, 0); 4095 4096 /* ATA devices needs special map treatment */ 4097 if ((pci_get_class(dev) == PCIC_STORAGE) && 4098 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 4099 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 4100 (!pci_read_config(dev, PCIR_BAR(0), 4) && 4101 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 4102 pci_ata_maps(bus, dev, rl, force, prefetchmask); 4103 else 4104 for (i = 0; i < cfg->nummaps;) { 4105 /* Skip resources already managed by EA */ 4106 if ((resource_list_find(rl, SYS_RES_MEMORY, PCIR_BAR(i)) != NULL) || 4107 (resource_list_find(rl, SYS_RES_IOPORT, PCIR_BAR(i)) != NULL) || 4108 pci_ea_is_enabled(dev, PCIR_BAR(i))) { 4109 i++; 4110 continue; 4111 } 4112 4113 /* 4114 * Skip quirked resources. 4115 */ 4116 for (q = &pci_quirks[0]; q->devid != 0; q++) 4117 if (q->devid == devid && 4118 q->type == PCI_QUIRK_UNMAP_REG && 4119 q->arg1 == PCIR_BAR(i)) 4120 break; 4121 if (q->devid != 0) { 4122 i++; 4123 continue; 4124 } 4125 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force, 4126 prefetchmask & (1 << i)); 4127 } 4128 4129 /* 4130 * Add additional, quirked resources. 4131 */ 4132 for (q = &pci_quirks[0]; q->devid != 0; q++) 4133 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) 4134 pci_add_map(bus, dev, q->arg1, rl, force, 0); 4135 4136 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 4137 /* 4138 * Try to re-route interrupts. Sometimes the BIOS or 4139 * firmware may leave bogus values in these registers. 4140 * If the re-route fails, then just stick with what we 4141 * have. 4142 */ 4143 pci_assign_interrupt(bus, dev, 1); 4144 } 4145 4146 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS && 4147 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) { 4148 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI) 4149 xhci_early_takeover(dev); 4150 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI) 4151 ehci_early_takeover(dev); 4152 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI) 4153 ohci_early_takeover(dev); 4154 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI) 4155 uhci_early_takeover(dev); 4156 } 4157 4158 /* 4159 * Reserve resources for secondary bus ranges behind bridge 4160 * devices. 4161 */ 4162 pci_reserve_secbus(bus, dev, cfg, rl); 4163 } 4164 4165 static struct pci_devinfo * 4166 pci_identify_function(device_t pcib, device_t dev, int domain, int busno, 4167 int slot, int func) 4168 { 4169 struct pci_devinfo *dinfo; 4170 4171 dinfo = pci_read_device(pcib, dev, domain, busno, slot, func); 4172 if (dinfo != NULL) 4173 pci_add_child(dev, dinfo); 4174 4175 return (dinfo); 4176 } 4177 4178 void 4179 pci_add_children(device_t dev, int domain, int busno) 4180 { 4181 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4182 device_t pcib = device_get_parent(dev); 4183 struct pci_devinfo *dinfo; 4184 int maxslots; 4185 int s, f, pcifunchigh; 4186 uint8_t hdrtype; 4187 int first_func; 4188 4189 /* 4190 * Try to detect a device at slot 0, function 0. If it exists, try to 4191 * enable ARI. We must enable ARI before detecting the rest of the 4192 * functions on this bus as ARI changes the set of slots and functions 4193 * that are legal on this bus. 4194 */ 4195 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0); 4196 if (dinfo != NULL && pci_enable_ari) 4197 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); 4198 4199 /* 4200 * Start looking for new devices on slot 0 at function 1 because we 4201 * just identified the device at slot 0, function 0. 4202 */ 4203 first_func = 1; 4204 4205 maxslots = PCIB_MAXSLOTS(pcib); 4206 for (s = 0; s <= maxslots; s++, first_func = 0) { 4207 pcifunchigh = 0; 4208 f = 0; 4209 DELAY(1); 4210 4211 /* If function 0 is not present, skip to the next slot. */ 4212 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4213 continue; 4214 hdrtype = REG(PCIR_HDRTYPE, 1); 4215 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4216 continue; 4217 if (hdrtype & PCIM_MFDEV) 4218 pcifunchigh = PCIB_MAXFUNCS(pcib); 4219 for (f = first_func; f <= pcifunchigh; f++) 4220 pci_identify_function(pcib, dev, domain, busno, s, f); 4221 } 4222 #undef REG 4223 } 4224 4225 int 4226 pci_rescan_method(device_t dev) 4227 { 4228 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4229 device_t pcib = device_get_parent(dev); 4230 device_t child, *devlist, *unchanged; 4231 int devcount, error, i, j, maxslots, oldcount; 4232 int busno, domain, s, f, pcifunchigh; 4233 uint8_t hdrtype; 4234 4235 /* No need to check for ARI on a rescan. */ 4236 error = device_get_children(dev, &devlist, &devcount); 4237 if (error) 4238 return (error); 4239 if (devcount != 0) { 4240 unchanged = malloc(devcount * sizeof(device_t), M_TEMP, 4241 M_NOWAIT | M_ZERO); 4242 if (unchanged == NULL) { 4243 free(devlist, M_TEMP); 4244 return (ENOMEM); 4245 } 4246 } else 4247 unchanged = NULL; 4248 4249 domain = pcib_get_domain(dev); 4250 busno = pcib_get_bus(dev); 4251 maxslots = PCIB_MAXSLOTS(pcib); 4252 for (s = 0; s <= maxslots; s++) { 4253 /* If function 0 is not present, skip to the next slot. */ 4254 f = 0; 4255 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4256 continue; 4257 pcifunchigh = 0; 4258 hdrtype = REG(PCIR_HDRTYPE, 1); 4259 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4260 continue; 4261 if (hdrtype & PCIM_MFDEV) 4262 pcifunchigh = PCIB_MAXFUNCS(pcib); 4263 for (f = 0; f <= pcifunchigh; f++) { 4264 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4265 continue; 4266 4267 /* 4268 * Found a valid function. Check if a 4269 * device_t for this device already exists. 4270 */ 4271 for (i = 0; i < devcount; i++) { 4272 child = devlist[i]; 4273 if (child == NULL) 4274 continue; 4275 if (pci_get_slot(child) == s && 4276 pci_get_function(child) == f) { 4277 unchanged[i] = child; 4278 goto next_func; 4279 } 4280 } 4281 4282 pci_identify_function(pcib, dev, domain, busno, s, f); 4283 next_func:; 4284 } 4285 } 4286 4287 /* Remove devices that are no longer present. */ 4288 for (i = 0; i < devcount; i++) { 4289 if (unchanged[i] != NULL) 4290 continue; 4291 device_delete_child(dev, devlist[i]); 4292 } 4293 4294 free(devlist, M_TEMP); 4295 oldcount = devcount; 4296 4297 /* Try to attach the devices just added. */ 4298 error = device_get_children(dev, &devlist, &devcount); 4299 if (error) { 4300 free(unchanged, M_TEMP); 4301 return (error); 4302 } 4303 4304 for (i = 0; i < devcount; i++) { 4305 for (j = 0; j < oldcount; j++) { 4306 if (devlist[i] == unchanged[j]) 4307 goto next_device; 4308 } 4309 4310 device_probe_and_attach(devlist[i]); 4311 next_device:; 4312 } 4313 4314 free(unchanged, M_TEMP); 4315 free(devlist, M_TEMP); 4316 return (0); 4317 #undef REG 4318 } 4319 4320 #ifdef PCI_IOV 4321 device_t 4322 pci_add_iov_child(device_t bus, device_t pf, uint16_t rid, uint16_t vid, 4323 uint16_t did) 4324 { 4325 struct pci_devinfo *vf_dinfo; 4326 device_t pcib; 4327 int busno, slot, func; 4328 4329 pcib = device_get_parent(bus); 4330 4331 PCIB_DECODE_RID(pcib, rid, &busno, &slot, &func); 4332 4333 vf_dinfo = pci_fill_devinfo(pcib, bus, pci_get_domain(pcib), busno, 4334 slot, func, vid, did); 4335 4336 vf_dinfo->cfg.flags |= PCICFG_VF; 4337 pci_add_child(bus, vf_dinfo); 4338 4339 return (vf_dinfo->cfg.dev); 4340 } 4341 4342 device_t 4343 pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid, 4344 uint16_t vid, uint16_t did) 4345 { 4346 4347 return (pci_add_iov_child(bus, pf, rid, vid, did)); 4348 } 4349 #endif 4350 4351 /* 4352 * For PCIe device set Max_Payload_Size to match PCIe root's. 4353 */ 4354 static void 4355 pcie_setup_mps(device_t dev) 4356 { 4357 struct pci_devinfo *dinfo = device_get_ivars(dev); 4358 device_t root; 4359 uint16_t rmps, mmps, mps; 4360 4361 if (dinfo->cfg.pcie.pcie_location == 0) 4362 return; 4363 root = pci_find_pcie_root_port(dev); 4364 if (root == NULL) 4365 return; 4366 /* Check whether the MPS is already configured. */ 4367 rmps = pcie_read_config(root, PCIER_DEVICE_CTL, 2) & 4368 PCIEM_CTL_MAX_PAYLOAD; 4369 mps = pcie_read_config(dev, PCIER_DEVICE_CTL, 2) & 4370 PCIEM_CTL_MAX_PAYLOAD; 4371 if (mps == rmps) 4372 return; 4373 /* Check whether the device is capable of the root's MPS. */ 4374 mmps = (pcie_read_config(dev, PCIER_DEVICE_CAP, 2) & 4375 PCIEM_CAP_MAX_PAYLOAD) << 5; 4376 if (rmps > mmps) { 4377 /* 4378 * The device is unable to handle root's MPS. Limit root. 4379 * XXX: We should traverse through all the tree, applying 4380 * it to all the devices. 4381 */ 4382 pcie_adjust_config(root, PCIER_DEVICE_CTL, 4383 PCIEM_CTL_MAX_PAYLOAD, mmps, 2); 4384 } else { 4385 pcie_adjust_config(dev, PCIER_DEVICE_CTL, 4386 PCIEM_CTL_MAX_PAYLOAD, rmps, 2); 4387 } 4388 } 4389 4390 static void 4391 pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo) 4392 { 4393 int aer; 4394 uint32_t r; 4395 uint16_t r2; 4396 4397 if (dinfo->cfg.pcie.pcie_location != 0 && 4398 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) { 4399 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4400 PCIER_ROOT_CTL, 2); 4401 r2 &= ~(PCIEM_ROOT_CTL_SERR_CORR | 4402 PCIEM_ROOT_CTL_SERR_NONFATAL | PCIEM_ROOT_CTL_SERR_FATAL); 4403 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4404 PCIER_ROOT_CTL, r2, 2); 4405 } 4406 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 4407 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 4408 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 4409 if (r != 0 && bootverbose) { 4410 pci_printf(&dinfo->cfg, 4411 "clearing AER UC 0x%08x -> 0x%08x\n", 4412 r, pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4413 4)); 4414 } 4415 4416 r = pci_read_config(dev, aer + PCIR_AER_UC_MASK, 4); 4417 r &= ~(PCIM_AER_UC_TRAINING_ERROR | 4418 PCIM_AER_UC_DL_PROTOCOL_ERROR | 4419 PCIM_AER_UC_SURPRISE_LINK_DOWN | 4420 PCIM_AER_UC_POISONED_TLP | 4421 PCIM_AER_UC_FC_PROTOCOL_ERROR | 4422 PCIM_AER_UC_COMPLETION_TIMEOUT | 4423 PCIM_AER_UC_COMPLETER_ABORT | 4424 PCIM_AER_UC_UNEXPECTED_COMPLETION | 4425 PCIM_AER_UC_RECEIVER_OVERFLOW | 4426 PCIM_AER_UC_MALFORMED_TLP | 4427 PCIM_AER_UC_ECRC_ERROR | 4428 PCIM_AER_UC_UNSUPPORTED_REQUEST | 4429 PCIM_AER_UC_ACS_VIOLATION | 4430 PCIM_AER_UC_INTERNAL_ERROR | 4431 PCIM_AER_UC_MC_BLOCKED_TLP | 4432 PCIM_AER_UC_ATOMIC_EGRESS_BLK | 4433 PCIM_AER_UC_TLP_PREFIX_BLOCKED); 4434 pci_write_config(dev, aer + PCIR_AER_UC_MASK, r, 4); 4435 4436 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 4437 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 4438 if (r != 0 && bootverbose) { 4439 pci_printf(&dinfo->cfg, 4440 "clearing AER COR 0x%08x -> 0x%08x\n", 4441 r, pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4442 4)); 4443 } 4444 4445 r = pci_read_config(dev, aer + PCIR_AER_COR_MASK, 4); 4446 r &= ~(PCIM_AER_COR_RECEIVER_ERROR | 4447 PCIM_AER_COR_BAD_TLP | 4448 PCIM_AER_COR_BAD_DLLP | 4449 PCIM_AER_COR_REPLAY_ROLLOVER | 4450 PCIM_AER_COR_REPLAY_TIMEOUT | 4451 PCIM_AER_COR_ADVISORY_NF_ERROR | 4452 PCIM_AER_COR_INTERNAL_ERROR | 4453 PCIM_AER_COR_HEADER_LOG_OVFLOW); 4454 pci_write_config(dev, aer + PCIR_AER_COR_MASK, r, 4); 4455 4456 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4457 PCIER_DEVICE_CTL, 2); 4458 r |= PCIEM_CTL_COR_ENABLE | PCIEM_CTL_NFER_ENABLE | 4459 PCIEM_CTL_FER_ENABLE | PCIEM_CTL_URR_ENABLE; 4460 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4461 PCIER_DEVICE_CTL, r, 2); 4462 } 4463 } 4464 4465 void 4466 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 4467 { 4468 device_t dev; 4469 4470 dinfo->cfg.dev = dev = device_add_child(bus, NULL, DEVICE_UNIT_ANY); 4471 device_set_ivars(dev, dinfo); 4472 resource_list_init(&dinfo->resources); 4473 pci_cfg_save(dev, dinfo, 0); 4474 pci_cfg_restore(dev, dinfo); 4475 pci_print_verbose(dinfo); 4476 pci_add_resources(bus, dev, 0, 0); 4477 if (pci_enable_mps_tune) 4478 pcie_setup_mps(dev); 4479 pci_child_added(dinfo->cfg.dev); 4480 4481 if (pci_clear_aer_on_attach) 4482 pci_add_child_clear_aer(dev, dinfo); 4483 4484 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev); 4485 } 4486 4487 void 4488 pci_child_added_method(device_t dev, device_t child) 4489 { 4490 4491 } 4492 4493 static int 4494 pci_probe(device_t dev) 4495 { 4496 4497 device_set_desc(dev, "PCI bus"); 4498 4499 /* Allow other subclasses to override this driver. */ 4500 return (BUS_PROBE_GENERIC); 4501 } 4502 4503 int 4504 pci_attach_common(device_t dev) 4505 { 4506 struct pci_softc *sc; 4507 int busno, domain; 4508 int rid; 4509 4510 sc = device_get_softc(dev); 4511 domain = pcib_get_domain(dev); 4512 busno = pcib_get_bus(dev); 4513 rid = 0; 4514 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, 4515 1, 0); 4516 if (sc->sc_bus == NULL) { 4517 device_printf(dev, "failed to allocate bus number\n"); 4518 return (ENXIO); 4519 } 4520 if (bootverbose) 4521 device_printf(dev, "domain=%d, physical bus=%d\n", 4522 domain, busno); 4523 sc->sc_dma_tag = bus_get_dma_tag(dev); 4524 return (0); 4525 } 4526 4527 int 4528 pci_attach(device_t dev) 4529 { 4530 int busno, domain, error; 4531 4532 error = pci_attach_common(dev); 4533 if (error) 4534 return (error); 4535 4536 /* 4537 * Since there can be multiple independently numbered PCI 4538 * buses on systems with multiple PCI domains, we can't use 4539 * the unit number to decide which bus we are probing. We ask 4540 * the parent pcib what our domain and bus numbers are. 4541 */ 4542 domain = pcib_get_domain(dev); 4543 busno = pcib_get_bus(dev); 4544 pci_add_children(dev, domain, busno); 4545 bus_attach_children(dev); 4546 return (0); 4547 } 4548 4549 int 4550 pci_detach(device_t dev) 4551 { 4552 struct pci_softc *sc; 4553 int error; 4554 4555 error = bus_generic_detach(dev); 4556 if (error) 4557 return (error); 4558 sc = device_get_softc(dev); 4559 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus); 4560 return (error); 4561 } 4562 4563 static void 4564 pci_hint_device_unit(device_t dev, device_t child, const char *name, int *unitp) 4565 { 4566 int line, unit; 4567 const char *at; 4568 char me1[24], me2[32]; 4569 uint8_t b, s, f; 4570 uint32_t d; 4571 device_location_cache_t *cache; 4572 4573 d = pci_get_domain(child); 4574 b = pci_get_bus(child); 4575 s = pci_get_slot(child); 4576 f = pci_get_function(child); 4577 snprintf(me1, sizeof(me1), "pci%u:%u:%u", b, s, f); 4578 snprintf(me2, sizeof(me2), "pci%u:%u:%u:%u", d, b, s, f); 4579 line = 0; 4580 cache = dev_wired_cache_init(); 4581 while (resource_find_dev(&line, name, &unit, "at", NULL) == 0) { 4582 resource_string_value(name, unit, "at", &at); 4583 if (strcmp(at, me1) == 0 || strcmp(at, me2) == 0) { 4584 *unitp = unit; 4585 break; 4586 } 4587 if (dev_wired_cache_match(cache, child, at)) { 4588 *unitp = unit; 4589 break; 4590 } 4591 } 4592 dev_wired_cache_fini(cache); 4593 } 4594 4595 static void 4596 pci_set_power_child(device_t dev, device_t child, int state) 4597 { 4598 device_t pcib; 4599 int dstate; 4600 4601 /* 4602 * Set the device to the given state. If the firmware suggests 4603 * a different power state, use it instead. If power management 4604 * is not present, the firmware is responsible for managing 4605 * device power. Skip children who aren't attached since they 4606 * are handled separately. 4607 */ 4608 pcib = device_get_parent(dev); 4609 dstate = state; 4610 if (device_is_attached(child) && 4611 PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0) 4612 pci_set_powerstate(child, dstate); 4613 } 4614 4615 int 4616 pci_suspend_child(device_t dev, device_t child) 4617 { 4618 struct pci_devinfo *dinfo; 4619 struct resource_list_entry *rle; 4620 int error; 4621 4622 dinfo = device_get_ivars(child); 4623 4624 /* 4625 * Save the PCI configuration space for the child and set the 4626 * device in the appropriate power state for this sleep state. 4627 */ 4628 pci_cfg_save(child, dinfo, 0); 4629 4630 /* Suspend devices before potentially powering them down. */ 4631 error = bus_generic_suspend_child(dev, child); 4632 4633 if (error) 4634 return (error); 4635 4636 if (pci_do_power_suspend) { 4637 /* 4638 * Make sure this device's interrupt handler is not invoked 4639 * in the case the device uses a shared interrupt that can 4640 * be raised by some other device. 4641 * This is applicable only to regular (legacy) PCI interrupts 4642 * as MSI/MSI-X interrupts are never shared. 4643 */ 4644 rle = resource_list_find(&dinfo->resources, 4645 SYS_RES_IRQ, 0); 4646 if (rle != NULL && rle->res != NULL) 4647 (void)bus_suspend_intr(child, rle->res); 4648 pci_set_power_child(dev, child, PCI_POWERSTATE_D3); 4649 } 4650 4651 return (0); 4652 } 4653 4654 int 4655 pci_resume_child(device_t dev, device_t child) 4656 { 4657 struct pci_devinfo *dinfo; 4658 struct resource_list_entry *rle; 4659 4660 if (pci_do_power_resume) 4661 pci_set_power_child(dev, child, PCI_POWERSTATE_D0); 4662 4663 dinfo = device_get_ivars(child); 4664 pci_cfg_restore(child, dinfo); 4665 if (!device_is_attached(child)) 4666 pci_cfg_save(child, dinfo, 1); 4667 4668 bus_generic_resume_child(dev, child); 4669 4670 /* 4671 * Allow interrupts only after fully resuming the driver and hardware. 4672 */ 4673 if (pci_do_power_suspend) { 4674 /* See pci_suspend_child for details. */ 4675 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 4676 if (rle != NULL && rle->res != NULL) 4677 (void)bus_resume_intr(child, rle->res); 4678 } 4679 4680 return (0); 4681 } 4682 4683 int 4684 pci_resume(device_t dev) 4685 { 4686 device_t child, *devlist; 4687 int error, i, numdevs; 4688 4689 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 4690 return (error); 4691 4692 /* 4693 * Resume critical devices first, then everything else later. 4694 */ 4695 for (i = 0; i < numdevs; i++) { 4696 child = devlist[i]; 4697 switch (pci_get_class(child)) { 4698 case PCIC_DISPLAY: 4699 case PCIC_MEMORY: 4700 case PCIC_BRIDGE: 4701 case PCIC_BASEPERIPH: 4702 BUS_RESUME_CHILD(dev, child); 4703 break; 4704 } 4705 } 4706 for (i = 0; i < numdevs; i++) { 4707 child = devlist[i]; 4708 switch (pci_get_class(child)) { 4709 case PCIC_DISPLAY: 4710 case PCIC_MEMORY: 4711 case PCIC_BRIDGE: 4712 case PCIC_BASEPERIPH: 4713 break; 4714 default: 4715 BUS_RESUME_CHILD(dev, child); 4716 } 4717 } 4718 free(devlist, M_TEMP); 4719 return (0); 4720 } 4721 4722 static void 4723 pci_load_vendor_data(void) 4724 { 4725 caddr_t data; 4726 void *ptr; 4727 size_t sz; 4728 4729 data = preload_search_by_type("pci_vendor_data"); 4730 if (data != NULL) { 4731 ptr = preload_fetch_addr(data); 4732 sz = preload_fetch_size(data); 4733 if (ptr != NULL && sz != 0) { 4734 pci_vendordata = ptr; 4735 pci_vendordata_size = sz; 4736 /* terminate the database */ 4737 pci_vendordata[pci_vendordata_size] = '\n'; 4738 } 4739 } 4740 } 4741 4742 void 4743 pci_driver_added(device_t dev, driver_t *driver) 4744 { 4745 int numdevs; 4746 device_t *devlist; 4747 device_t child; 4748 struct pci_devinfo *dinfo; 4749 int i; 4750 4751 if (bootverbose) 4752 device_printf(dev, "driver added\n"); 4753 DEVICE_IDENTIFY(driver, dev); 4754 if (device_get_children(dev, &devlist, &numdevs) != 0) 4755 return; 4756 for (i = 0; i < numdevs; i++) { 4757 child = devlist[i]; 4758 if (device_get_state(child) != DS_NOTPRESENT) 4759 continue; 4760 dinfo = device_get_ivars(child); 4761 pci_print_verbose(dinfo); 4762 if (bootverbose) 4763 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); 4764 pci_cfg_restore(child, dinfo); 4765 if (device_probe_and_attach(child) != 0) 4766 pci_child_detached(dev, child); 4767 } 4768 free(devlist, M_TEMP); 4769 } 4770 4771 int 4772 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, 4773 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep) 4774 { 4775 struct pci_devinfo *dinfo; 4776 struct msix_table_entry *mte; 4777 struct msix_vector *mv; 4778 uint64_t addr; 4779 uint32_t data; 4780 void *cookie; 4781 int error, rid; 4782 4783 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr, 4784 arg, &cookie); 4785 if (error) 4786 return (error); 4787 4788 /* If this is not a direct child, just bail out. */ 4789 if (device_get_parent(child) != dev) { 4790 *cookiep = cookie; 4791 return(0); 4792 } 4793 4794 rid = rman_get_rid(irq); 4795 if (rid == 0) { 4796 /* Make sure that INTx is enabled */ 4797 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4798 } else { 4799 /* 4800 * Check to see if the interrupt is MSI or MSI-X. 4801 * Ask our parent to map the MSI and give 4802 * us the address and data register values. 4803 * If we fail for some reason, teardown the 4804 * interrupt handler. 4805 */ 4806 dinfo = device_get_ivars(child); 4807 if (dinfo->cfg.msi.msi_alloc > 0) { 4808 if (dinfo->cfg.msi.msi_addr == 0) { 4809 KASSERT(dinfo->cfg.msi.msi_handlers == 0, 4810 ("MSI has handlers, but vectors not mapped")); 4811 error = PCIB_MAP_MSI(device_get_parent(dev), 4812 child, rman_get_start(irq), &addr, &data); 4813 if (error) 4814 goto bad; 4815 dinfo->cfg.msi.msi_addr = addr; 4816 dinfo->cfg.msi.msi_data = data; 4817 } 4818 if (dinfo->cfg.msi.msi_handlers == 0) 4819 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, 4820 dinfo->cfg.msi.msi_data); 4821 dinfo->cfg.msi.msi_handlers++; 4822 } else { 4823 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4824 ("No MSI or MSI-X interrupts allocated")); 4825 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4826 ("MSI-X index too high")); 4827 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4828 KASSERT(mte->mte_vector != 0, ("no message vector")); 4829 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; 4830 KASSERT(mv->mv_irq == rman_get_start(irq), 4831 ("IRQ mismatch")); 4832 if (mv->mv_address == 0) { 4833 KASSERT(mte->mte_handlers == 0, 4834 ("MSI-X table entry has handlers, but vector not mapped")); 4835 error = PCIB_MAP_MSI(device_get_parent(dev), 4836 child, rman_get_start(irq), &addr, &data); 4837 if (error) 4838 goto bad; 4839 mv->mv_address = addr; 4840 mv->mv_data = data; 4841 } 4842 4843 /* 4844 * The MSIX table entry must be made valid by 4845 * incrementing the mte_handlers before 4846 * calling pci_enable_msix() and 4847 * pci_resume_msix(). Else the MSIX rewrite 4848 * table quirk will not work as expected. 4849 */ 4850 mte->mte_handlers++; 4851 if (mte->mte_handlers == 1) { 4852 pci_enable_msix(child, rid - 1, mv->mv_address, 4853 mv->mv_data); 4854 pci_unmask_msix(child, rid - 1); 4855 } 4856 } 4857 4858 /* 4859 * Make sure that INTx is disabled if we are using MSI/MSI-X, 4860 * unless the device is affected by PCI_QUIRK_MSI_INTX_BUG, 4861 * in which case we "enable" INTx so MSI/MSI-X actually works. 4862 */ 4863 if (!pci_has_quirk(pci_get_devid(child), 4864 PCI_QUIRK_MSI_INTX_BUG)) 4865 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4866 else 4867 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4868 bad: 4869 if (error) { 4870 (void)bus_generic_teardown_intr(dev, child, irq, 4871 cookie); 4872 return (error); 4873 } 4874 } 4875 *cookiep = cookie; 4876 return (0); 4877 } 4878 4879 int 4880 pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 4881 void *cookie) 4882 { 4883 struct msix_table_entry *mte; 4884 struct resource_list_entry *rle; 4885 struct pci_devinfo *dinfo; 4886 int error, rid; 4887 4888 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE)) 4889 return (EINVAL); 4890 4891 /* If this isn't a direct child, just bail out */ 4892 if (device_get_parent(child) != dev) 4893 return(bus_generic_teardown_intr(dev, child, irq, cookie)); 4894 4895 rid = rman_get_rid(irq); 4896 if (rid == 0) { 4897 /* Mask INTx */ 4898 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4899 } else { 4900 /* 4901 * Check to see if the interrupt is MSI or MSI-X. If so, 4902 * decrement the appropriate handlers count and mask the 4903 * MSI-X message, or disable MSI messages if the count 4904 * drops to 0. 4905 */ 4906 dinfo = device_get_ivars(child); 4907 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); 4908 if (rle->res != irq) 4909 return (EINVAL); 4910 if (dinfo->cfg.msi.msi_alloc > 0) { 4911 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, 4912 ("MSI-X index too high")); 4913 if (dinfo->cfg.msi.msi_handlers == 0) 4914 return (EINVAL); 4915 dinfo->cfg.msi.msi_handlers--; 4916 if (dinfo->cfg.msi.msi_handlers == 0) 4917 pci_disable_msi(child); 4918 } else { 4919 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4920 ("No MSI or MSI-X interrupts allocated")); 4921 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4922 ("MSI-X index too high")); 4923 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4924 if (mte->mte_handlers == 0) 4925 return (EINVAL); 4926 mte->mte_handlers--; 4927 if (mte->mte_handlers == 0) 4928 pci_mask_msix(child, rid - 1); 4929 } 4930 } 4931 error = bus_generic_teardown_intr(dev, child, irq, cookie); 4932 if (rid > 0) 4933 KASSERT(error == 0, 4934 ("%s: generic teardown failed for MSI/MSI-X", __func__)); 4935 return (error); 4936 } 4937 4938 int 4939 pci_print_child(device_t dev, device_t child) 4940 { 4941 struct pci_devinfo *dinfo; 4942 struct resource_list *rl; 4943 int retval = 0; 4944 4945 dinfo = device_get_ivars(child); 4946 rl = &dinfo->resources; 4947 4948 retval += bus_print_child_header(dev, child); 4949 4950 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#jx"); 4951 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 4952 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 4953 if (device_get_flags(dev)) 4954 retval += printf(" flags %#x", device_get_flags(dev)); 4955 4956 retval += printf(" at device %d.%d", pci_get_slot(child), 4957 pci_get_function(child)); 4958 4959 retval += bus_print_child_domain(dev, child); 4960 retval += bus_print_child_footer(dev, child); 4961 4962 return (retval); 4963 } 4964 4965 static const struct 4966 { 4967 int class; 4968 int subclass; 4969 int report; /* 0 = bootverbose, 1 = always */ 4970 const char *desc; 4971 } pci_nomatch_tab[] = { 4972 {PCIC_OLD, -1, 1, "old"}, 4973 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"}, 4974 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"}, 4975 {PCIC_STORAGE, -1, 1, "mass storage"}, 4976 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"}, 4977 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"}, 4978 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"}, 4979 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"}, 4980 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"}, 4981 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"}, 4982 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"}, 4983 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"}, 4984 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"}, 4985 {PCIC_NETWORK, -1, 1, "network"}, 4986 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"}, 4987 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"}, 4988 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"}, 4989 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"}, 4990 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"}, 4991 {PCIC_DISPLAY, -1, 1, "display"}, 4992 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"}, 4993 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"}, 4994 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"}, 4995 {PCIC_MULTIMEDIA, -1, 1, "multimedia"}, 4996 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"}, 4997 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"}, 4998 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"}, 4999 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"}, 5000 {PCIC_MEMORY, -1, 1, "memory"}, 5001 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"}, 5002 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"}, 5003 {PCIC_BRIDGE, -1, 1, "bridge"}, 5004 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"}, 5005 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"}, 5006 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"}, 5007 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"}, 5008 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"}, 5009 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"}, 5010 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"}, 5011 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"}, 5012 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"}, 5013 {PCIC_SIMPLECOMM, -1, 1, "simple comms"}, 5014 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */ 5015 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"}, 5016 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"}, 5017 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"}, 5018 {PCIC_BASEPERIPH, -1, 0, "base peripheral"}, 5019 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"}, 5020 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"}, 5021 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"}, 5022 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"}, 5023 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"}, 5024 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"}, 5025 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"}, 5026 {PCIC_INPUTDEV, -1, 1, "input device"}, 5027 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"}, 5028 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"}, 5029 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"}, 5030 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"}, 5031 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"}, 5032 {PCIC_DOCKING, -1, 1, "docking station"}, 5033 {PCIC_PROCESSOR, -1, 1, "processor"}, 5034 {PCIC_SERIALBUS, -1, 1, "serial bus"}, 5035 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"}, 5036 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"}, 5037 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"}, 5038 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"}, 5039 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"}, 5040 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"}, 5041 {PCIC_WIRELESS, -1, 1, "wireless controller"}, 5042 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"}, 5043 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"}, 5044 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"}, 5045 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"}, 5046 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"}, 5047 {PCIC_SATCOM, -1, 1, "satellite communication"}, 5048 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"}, 5049 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"}, 5050 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"}, 5051 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"}, 5052 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"}, 5053 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"}, 5054 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"}, 5055 {PCIC_DASP, -1, 0, "dasp"}, 5056 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"}, 5057 {PCIC_DASP, PCIS_DASP_PERFCNTRS, 1, "performance counters"}, 5058 {PCIC_DASP, PCIS_DASP_COMM_SYNC, 1, "communication synchronizer"}, 5059 {PCIC_DASP, PCIS_DASP_MGMT_CARD, 1, "signal processing management"}, 5060 {PCIC_INSTRUMENT, -1, 0, "non-essential instrumentation"}, 5061 {0, 0, 0, NULL} 5062 }; 5063 5064 void 5065 pci_probe_nomatch(device_t dev, device_t child) 5066 { 5067 int i, report; 5068 const char *cp, *scp; 5069 char *device; 5070 5071 /* 5072 * Look for a listing for this device in a loaded device database. 5073 */ 5074 report = 1; 5075 if ((device = pci_describe_device(child)) != NULL) { 5076 device_printf(dev, "<%s>", device); 5077 free(device, M_DEVBUF); 5078 } else { 5079 /* 5080 * Scan the class/subclass descriptions for a general 5081 * description. 5082 */ 5083 cp = "unknown"; 5084 scp = NULL; 5085 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 5086 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 5087 if (pci_nomatch_tab[i].subclass == -1) { 5088 cp = pci_nomatch_tab[i].desc; 5089 report = pci_nomatch_tab[i].report; 5090 } else if (pci_nomatch_tab[i].subclass == 5091 pci_get_subclass(child)) { 5092 scp = pci_nomatch_tab[i].desc; 5093 report = pci_nomatch_tab[i].report; 5094 } 5095 } 5096 } 5097 if (report || bootverbose) { 5098 device_printf(dev, "<%s%s%s>", 5099 cp ? cp : "", 5100 ((cp != NULL) && (scp != NULL)) ? ", " : "", 5101 scp ? scp : ""); 5102 } 5103 } 5104 if (report || bootverbose) { 5105 printf(" at device %d.%d (no driver attached)\n", 5106 pci_get_slot(child), pci_get_function(child)); 5107 } 5108 pci_cfg_save(child, device_get_ivars(child), 1); 5109 } 5110 5111 void 5112 pci_child_detached(device_t dev, device_t child) 5113 { 5114 struct pci_devinfo *dinfo; 5115 struct resource_list *rl; 5116 5117 dinfo = device_get_ivars(child); 5118 rl = &dinfo->resources; 5119 5120 /* 5121 * Have to deallocate IRQs before releasing any MSI messages and 5122 * have to release MSI messages before deallocating any memory 5123 * BARs. 5124 */ 5125 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0) 5126 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); 5127 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { 5128 if (dinfo->cfg.msi.msi_alloc != 0) 5129 pci_printf(&dinfo->cfg, "Device leaked %d MSI " 5130 "vectors\n", dinfo->cfg.msi.msi_alloc); 5131 else 5132 pci_printf(&dinfo->cfg, "Device leaked %d MSI-X " 5133 "vectors\n", dinfo->cfg.msix.msix_alloc); 5134 (void)pci_release_msi(child); 5135 } 5136 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0) 5137 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); 5138 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0) 5139 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); 5140 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0) 5141 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); 5142 5143 pci_cfg_save(child, dinfo, 1); 5144 } 5145 5146 /* 5147 * Parse the PCI device database, if loaded, and return a pointer to a 5148 * description of the device. 5149 * 5150 * The database is flat text formatted as follows: 5151 * 5152 * Any line not in a valid format is ignored. 5153 * Lines are terminated with newline '\n' characters. 5154 * 5155 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 5156 * the vendor name. 5157 * 5158 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 5159 * - devices cannot be listed without a corresponding VENDOR line. 5160 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 5161 * another TAB, then the device name. 5162 */ 5163 5164 /* 5165 * Assuming (ptr) points to the beginning of a line in the database, 5166 * return the vendor or device and description of the next entry. 5167 * The value of (vendor) or (device) inappropriate for the entry type 5168 * is set to -1. Returns nonzero at the end of the database. 5169 * 5170 * Note that this is slightly unrobust in the face of corrupt data; 5171 * we attempt to safeguard against this by spamming the end of the 5172 * database with a newline when we initialise. 5173 */ 5174 static int 5175 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 5176 { 5177 char *cp = *ptr; 5178 int left; 5179 5180 *device = -1; 5181 *vendor = -1; 5182 **desc = '\0'; 5183 for (;;) { 5184 left = pci_vendordata_size - (cp - pci_vendordata); 5185 if (left <= 0) { 5186 *ptr = cp; 5187 return(1); 5188 } 5189 5190 /* vendor entry? */ 5191 if (*cp != '\t' && 5192 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 5193 break; 5194 /* device entry? */ 5195 if (*cp == '\t' && 5196 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 5197 break; 5198 5199 /* skip to next line */ 5200 while (*cp != '\n' && left > 0) { 5201 cp++; 5202 left--; 5203 } 5204 if (*cp == '\n') { 5205 cp++; 5206 left--; 5207 } 5208 } 5209 /* skip to next line */ 5210 while (*cp != '\n' && left > 0) { 5211 cp++; 5212 left--; 5213 } 5214 if (*cp == '\n' && left > 0) 5215 cp++; 5216 *ptr = cp; 5217 return(0); 5218 } 5219 5220 static char * 5221 pci_describe_device(device_t dev) 5222 { 5223 int vendor, device; 5224 char *desc, *vp, *dp, *line; 5225 5226 desc = vp = dp = NULL; 5227 5228 /* 5229 * If we have no vendor data, we can't do anything. 5230 */ 5231 if (pci_vendordata == NULL) 5232 goto out; 5233 5234 /* 5235 * Scan the vendor data looking for this device 5236 */ 5237 line = pci_vendordata; 5238 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5239 goto out; 5240 for (;;) { 5241 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 5242 goto out; 5243 if (vendor == pci_get_vendor(dev)) 5244 break; 5245 } 5246 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5247 goto out; 5248 for (;;) { 5249 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 5250 *dp = 0; 5251 break; 5252 } 5253 if (vendor != -1) { 5254 *dp = 0; 5255 break; 5256 } 5257 if (device == pci_get_device(dev)) 5258 break; 5259 } 5260 if (dp[0] == '\0') 5261 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 5262 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 5263 NULL) 5264 sprintf(desc, "%s, %s", vp, dp); 5265 out: 5266 if (vp != NULL) 5267 free(vp, M_DEVBUF); 5268 if (dp != NULL) 5269 free(dp, M_DEVBUF); 5270 return(desc); 5271 } 5272 5273 int 5274 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 5275 { 5276 struct pci_devinfo *dinfo; 5277 pcicfgregs *cfg; 5278 5279 dinfo = device_get_ivars(child); 5280 cfg = &dinfo->cfg; 5281 5282 switch (which) { 5283 case PCI_IVAR_ETHADDR: 5284 /* 5285 * The generic accessor doesn't deal with failure, so 5286 * we set the return value, then return an error. 5287 */ 5288 *((uint8_t **) result) = NULL; 5289 return (EINVAL); 5290 case PCI_IVAR_SUBVENDOR: 5291 *result = cfg->subvendor; 5292 break; 5293 case PCI_IVAR_SUBDEVICE: 5294 *result = cfg->subdevice; 5295 break; 5296 case PCI_IVAR_VENDOR: 5297 *result = cfg->vendor; 5298 break; 5299 case PCI_IVAR_DEVICE: 5300 *result = cfg->device; 5301 break; 5302 case PCI_IVAR_DEVID: 5303 *result = (cfg->device << 16) | cfg->vendor; 5304 break; 5305 case PCI_IVAR_CLASS: 5306 *result = cfg->baseclass; 5307 break; 5308 case PCI_IVAR_SUBCLASS: 5309 *result = cfg->subclass; 5310 break; 5311 case PCI_IVAR_PROGIF: 5312 *result = cfg->progif; 5313 break; 5314 case PCI_IVAR_REVID: 5315 *result = cfg->revid; 5316 break; 5317 case PCI_IVAR_INTPIN: 5318 *result = cfg->intpin; 5319 break; 5320 case PCI_IVAR_IRQ: 5321 *result = cfg->intline; 5322 break; 5323 case PCI_IVAR_DOMAIN: 5324 *result = cfg->domain; 5325 break; 5326 case PCI_IVAR_BUS: 5327 *result = cfg->bus; 5328 break; 5329 case PCI_IVAR_SLOT: 5330 *result = cfg->slot; 5331 break; 5332 case PCI_IVAR_FUNCTION: 5333 *result = cfg->func; 5334 break; 5335 case PCI_IVAR_CMDREG: 5336 *result = cfg->cmdreg; 5337 break; 5338 case PCI_IVAR_CACHELNSZ: 5339 *result = cfg->cachelnsz; 5340 break; 5341 case PCI_IVAR_MINGNT: 5342 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5343 *result = -1; 5344 return (EINVAL); 5345 } 5346 *result = cfg->mingnt; 5347 break; 5348 case PCI_IVAR_MAXLAT: 5349 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5350 *result = -1; 5351 return (EINVAL); 5352 } 5353 *result = cfg->maxlat; 5354 break; 5355 case PCI_IVAR_LATTIMER: 5356 *result = cfg->lattimer; 5357 break; 5358 default: 5359 return (ENOENT); 5360 } 5361 return (0); 5362 } 5363 5364 int 5365 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 5366 { 5367 struct pci_devinfo *dinfo; 5368 5369 dinfo = device_get_ivars(child); 5370 5371 switch (which) { 5372 case PCI_IVAR_INTPIN: 5373 dinfo->cfg.intpin = value; 5374 return (0); 5375 case PCI_IVAR_ETHADDR: 5376 case PCI_IVAR_SUBVENDOR: 5377 case PCI_IVAR_SUBDEVICE: 5378 case PCI_IVAR_VENDOR: 5379 case PCI_IVAR_DEVICE: 5380 case PCI_IVAR_DEVID: 5381 case PCI_IVAR_CLASS: 5382 case PCI_IVAR_SUBCLASS: 5383 case PCI_IVAR_PROGIF: 5384 case PCI_IVAR_REVID: 5385 case PCI_IVAR_IRQ: 5386 case PCI_IVAR_DOMAIN: 5387 case PCI_IVAR_BUS: 5388 case PCI_IVAR_SLOT: 5389 case PCI_IVAR_FUNCTION: 5390 return (EINVAL); /* disallow for now */ 5391 5392 default: 5393 return (ENOENT); 5394 } 5395 } 5396 5397 #include "opt_ddb.h" 5398 #ifdef DDB 5399 #include <ddb/ddb.h> 5400 #include <sys/cons.h> 5401 5402 /* 5403 * List resources based on pci map registers, used for within ddb 5404 */ 5405 5406 DB_SHOW_COMMAND_FLAGS(pciregs, db_pci_dump, DB_CMD_MEMSAFE) 5407 { 5408 struct pci_devinfo *dinfo; 5409 struct devlist *devlist_head; 5410 struct pci_conf *p; 5411 const char *name; 5412 int i, error, none_count; 5413 5414 none_count = 0; 5415 /* get the head of the device queue */ 5416 devlist_head = &pci_devq; 5417 5418 /* 5419 * Go through the list of devices and print out devices 5420 */ 5421 for (error = 0, i = 0, 5422 dinfo = STAILQ_FIRST(devlist_head); 5423 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 5424 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 5425 /* Populate pd_name and pd_unit */ 5426 name = NULL; 5427 if (dinfo->cfg.dev) 5428 name = device_get_name(dinfo->cfg.dev); 5429 5430 p = &dinfo->conf; 5431 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x " 5432 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 5433 (name && *name) ? name : "none", 5434 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 5435 none_count++, 5436 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, 5437 p->pc_sel.pc_func, (p->pc_class << 16) | 5438 (p->pc_subclass << 8) | p->pc_progif, 5439 (p->pc_subdevice << 16) | p->pc_subvendor, 5440 (p->pc_device << 16) | p->pc_vendor, 5441 p->pc_revid, p->pc_hdr); 5442 } 5443 } 5444 #endif /* DDB */ 5445 5446 struct resource * 5447 pci_reserve_map(device_t dev, device_t child, int type, int *rid, 5448 rman_res_t start, rman_res_t end, rman_res_t count, u_int num, 5449 u_int flags) 5450 { 5451 struct pci_devinfo *dinfo = device_get_ivars(child); 5452 struct resource_list *rl = &dinfo->resources; 5453 struct resource *res; 5454 struct pci_map *pm; 5455 uint16_t cmd; 5456 pci_addr_t map, testval; 5457 int mapsize; 5458 5459 res = NULL; 5460 5461 /* If rid is managed by EA, ignore it */ 5462 if (pci_ea_is_enabled(child, *rid)) 5463 goto out; 5464 5465 pm = pci_find_bar(child, *rid); 5466 if (pm != NULL) { 5467 /* This is a BAR that we failed to allocate earlier. */ 5468 mapsize = pm->pm_size; 5469 map = pm->pm_value; 5470 } else { 5471 /* 5472 * Weed out the bogons, and figure out how large the 5473 * BAR/map is. BARs that read back 0 here are bogus 5474 * and unimplemented. Note: atapci in legacy mode are 5475 * special and handled elsewhere in the code. If you 5476 * have a atapci device in legacy mode and it fails 5477 * here, that other code is broken. 5478 */ 5479 pci_read_bar(child, *rid, &map, &testval, NULL); 5480 5481 /* 5482 * Determine the size of the BAR and ignore BARs with a size 5483 * of 0. Device ROM BARs use a different mask value. 5484 */ 5485 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) 5486 mapsize = pci_romsize(testval); 5487 else 5488 mapsize = pci_mapsize(testval); 5489 if (mapsize == 0) 5490 goto out; 5491 pm = pci_add_bar(child, *rid, map, mapsize); 5492 } 5493 5494 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { 5495 if (type != SYS_RES_MEMORY) { 5496 if (bootverbose) 5497 device_printf(dev, 5498 "child %s requested type %d for rid %#x," 5499 " but the BAR says it is an memio\n", 5500 device_get_nameunit(child), type, *rid); 5501 goto out; 5502 } 5503 } else { 5504 if (type != SYS_RES_IOPORT) { 5505 if (bootverbose) 5506 device_printf(dev, 5507 "child %s requested type %d for rid %#x," 5508 " but the BAR says it is an ioport\n", 5509 device_get_nameunit(child), type, *rid); 5510 goto out; 5511 } 5512 } 5513 5514 /* 5515 * For real BARs, we need to override the size that 5516 * the driver requests, because that's what the BAR 5517 * actually uses and we would otherwise have a 5518 * situation where we might allocate the excess to 5519 * another driver, which won't work. 5520 */ 5521 count = ((pci_addr_t)1 << mapsize) * num; 5522 if (RF_ALIGNMENT(flags) < mapsize) 5523 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 5524 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH)) 5525 flags |= RF_PREFETCHABLE; 5526 5527 /* 5528 * Allocate enough resource, and then write back the 5529 * appropriate BAR for that resource. 5530 */ 5531 resource_list_add(rl, type, *rid, start, end, count); 5532 res = resource_list_reserve(rl, dev, child, type, rid, start, end, 5533 count, flags & ~RF_ACTIVE); 5534 if (res == NULL) { 5535 resource_list_delete(rl, type, *rid); 5536 device_printf(child, 5537 "%#jx bytes of rid %#x res %d failed (%#jx, %#jx).\n", 5538 count, *rid, type, start, end); 5539 goto out; 5540 } 5541 if (bootverbose) 5542 device_printf(child, 5543 "Lazy allocation of %#jx bytes rid %#x type %d at %#jx\n", 5544 count, *rid, type, rman_get_start(res)); 5545 5546 /* Disable decoding via the CMD register before updating the BAR */ 5547 cmd = pci_read_config(child, PCIR_COMMAND, 2); 5548 pci_write_config(child, PCIR_COMMAND, 5549 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 5550 5551 map = rman_get_start(res); 5552 pci_write_bar(child, pm, map); 5553 5554 /* Restore the original value of the CMD register */ 5555 pci_write_config(child, PCIR_COMMAND, cmd, 2); 5556 out: 5557 return (res); 5558 } 5559 5560 struct resource * 5561 pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid, 5562 rman_res_t start, rman_res_t end, rman_res_t count, u_long num, 5563 u_int flags) 5564 { 5565 struct pci_devinfo *dinfo; 5566 struct resource_list *rl; 5567 struct resource_list_entry *rle; 5568 struct resource *res; 5569 pcicfgregs *cfg; 5570 5571 /* 5572 * Perform lazy resource allocation 5573 */ 5574 dinfo = device_get_ivars(child); 5575 rl = &dinfo->resources; 5576 cfg = &dinfo->cfg; 5577 switch (type) { 5578 case PCI_RES_BUS: 5579 return (pci_alloc_secbus(dev, child, rid, start, end, count, 5580 flags)); 5581 case SYS_RES_IRQ: 5582 /* 5583 * Can't alloc legacy interrupt once MSI messages have 5584 * been allocated. 5585 */ 5586 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 5587 cfg->msix.msix_alloc > 0)) 5588 return (NULL); 5589 5590 /* 5591 * If the child device doesn't have an interrupt 5592 * routed and is deserving of an interrupt, try to 5593 * assign it one. 5594 */ 5595 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 5596 (cfg->intpin != 0)) 5597 pci_assign_interrupt(dev, child, 0); 5598 break; 5599 case SYS_RES_IOPORT: 5600 case SYS_RES_MEMORY: 5601 /* 5602 * PCI-PCI bridge I/O window resources are not BARs. 5603 * For those allocations just pass the request up the 5604 * tree. 5605 */ 5606 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { 5607 switch (*rid) { 5608 case PCIR_IOBASEL_1: 5609 case PCIR_MEMBASE_1: 5610 case PCIR_PMBASEL_1: 5611 /* 5612 * XXX: Should we bother creating a resource 5613 * list entry? 5614 */ 5615 return (bus_generic_alloc_resource(dev, child, 5616 type, rid, start, end, count, flags)); 5617 } 5618 } 5619 /* Reserve resources for this BAR if needed. */ 5620 rle = resource_list_find(rl, type, *rid); 5621 if (rle == NULL) { 5622 res = pci_reserve_map(dev, child, type, rid, start, end, 5623 count, num, flags); 5624 if (res == NULL) 5625 return (NULL); 5626 } 5627 } 5628 return (resource_list_alloc(rl, dev, child, type, rid, 5629 start, end, count, flags)); 5630 } 5631 5632 struct resource * 5633 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 5634 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 5635 { 5636 #ifdef PCI_IOV 5637 struct pci_devinfo *dinfo; 5638 #endif 5639 5640 if (device_get_parent(child) != dev) 5641 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 5642 type, rid, start, end, count, flags)); 5643 5644 #ifdef PCI_IOV 5645 dinfo = device_get_ivars(child); 5646 if (dinfo->cfg.flags & PCICFG_VF) { 5647 switch (type) { 5648 /* VFs can't have I/O BARs. */ 5649 case SYS_RES_IOPORT: 5650 return (NULL); 5651 case SYS_RES_MEMORY: 5652 return (pci_vf_alloc_mem_resource(dev, child, rid, 5653 start, end, count, flags)); 5654 } 5655 5656 /* Fall through for other types of resource allocations. */ 5657 } 5658 #endif 5659 5660 return (pci_alloc_multi_resource(dev, child, type, rid, start, end, 5661 count, 1, flags)); 5662 } 5663 5664 int 5665 pci_release_resource(device_t dev, device_t child, struct resource *r) 5666 { 5667 struct pci_devinfo *dinfo; 5668 struct resource_list *rl; 5669 pcicfgregs *cfg __unused; 5670 5671 if (device_get_parent(child) != dev) 5672 return (bus_generic_release_resource(dev, child, r)); 5673 5674 dinfo = device_get_ivars(child); 5675 cfg = &dinfo->cfg; 5676 5677 #ifdef PCI_IOV 5678 if (cfg->flags & PCICFG_VF) { 5679 switch (rman_get_type(r)) { 5680 /* VFs can't have I/O BARs. */ 5681 case SYS_RES_IOPORT: 5682 return (EDOOFUS); 5683 case SYS_RES_MEMORY: 5684 return (pci_vf_release_mem_resource(dev, child, r)); 5685 } 5686 5687 /* Fall through for other types of resource allocations. */ 5688 } 5689 #endif 5690 5691 /* 5692 * PCI-PCI bridge I/O window resources are not BARs. For 5693 * those allocations just pass the request up the tree. 5694 */ 5695 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && 5696 (rman_get_type(r) == SYS_RES_IOPORT || 5697 rman_get_type(r) == SYS_RES_MEMORY)) { 5698 switch (rman_get_rid(r)) { 5699 case PCIR_IOBASEL_1: 5700 case PCIR_MEMBASE_1: 5701 case PCIR_PMBASEL_1: 5702 return (bus_generic_release_resource(dev, child, r)); 5703 } 5704 } 5705 5706 rl = &dinfo->resources; 5707 return (resource_list_release(rl, dev, child, r)); 5708 } 5709 5710 int 5711 pci_activate_resource(device_t dev, device_t child, struct resource *r) 5712 { 5713 struct pci_devinfo *dinfo; 5714 int error, rid, type; 5715 5716 if (device_get_parent(child) != dev) 5717 return (bus_generic_activate_resource(dev, child, r)); 5718 5719 dinfo = device_get_ivars(child); 5720 #ifdef PCI_IOV 5721 if (dinfo->cfg.flags & PCICFG_VF) { 5722 switch (rman_get_type(r)) { 5723 /* VFs can't have I/O BARs. */ 5724 case SYS_RES_IOPORT: 5725 error = EINVAL; 5726 break; 5727 case SYS_RES_MEMORY: 5728 error = pci_vf_activate_mem_resource(dev, child, r); 5729 break; 5730 default: 5731 error = bus_generic_activate_resource(dev, child, r); 5732 break; 5733 } 5734 } else 5735 #endif 5736 error = bus_generic_activate_resource(dev, child, r); 5737 if (error) 5738 return (error); 5739 5740 rid = rman_get_rid(r); 5741 type = rman_get_type(r); 5742 5743 /* Device ROMs need their decoding explicitly enabled. */ 5744 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5745 pci_write_bar(child, pci_find_bar(child, rid), 5746 rman_get_start(r) | PCIM_BIOS_ENABLE); 5747 5748 /* Enable decoding in the command register when activating BARs. */ 5749 switch (type) { 5750 case SYS_RES_IOPORT: 5751 case SYS_RES_MEMORY: 5752 error = PCI_ENABLE_IO(dev, child, type); 5753 break; 5754 } 5755 return (error); 5756 } 5757 5758 int 5759 pci_deactivate_resource(device_t dev, device_t child, struct resource *r) 5760 { 5761 struct pci_devinfo *dinfo; 5762 int error, rid, type; 5763 5764 if (device_get_parent(child) != dev) 5765 return (bus_generic_deactivate_resource(dev, child, r)); 5766 5767 dinfo = device_get_ivars(child); 5768 #ifdef PCI_IOV 5769 if (dinfo->cfg.flags & PCICFG_VF) { 5770 switch (rman_get_type(r)) { 5771 /* VFs can't have I/O BARs. */ 5772 case SYS_RES_IOPORT: 5773 error = EINVAL; 5774 break; 5775 case SYS_RES_MEMORY: 5776 error = pci_vf_deactivate_mem_resource(dev, child, r); 5777 break; 5778 default: 5779 error = bus_generic_deactivate_resource(dev, child, r); 5780 break; 5781 } 5782 } else 5783 #endif 5784 error = bus_generic_deactivate_resource(dev, child, r); 5785 if (error) 5786 return (error); 5787 5788 /* Disable decoding for device ROMs. */ 5789 rid = rman_get_rid(r); 5790 type = rman_get_type(r); 5791 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5792 pci_write_bar(child, pci_find_bar(child, rid), 5793 rman_get_start(r)); 5794 return (0); 5795 } 5796 5797 int 5798 pci_adjust_resource(device_t dev, device_t child, struct resource *r, 5799 rman_res_t start, rman_res_t end) 5800 { 5801 #ifdef PCI_IOV 5802 struct pci_devinfo *dinfo; 5803 5804 if (device_get_parent(child) != dev) 5805 return (bus_generic_adjust_resource(dev, child, r, start, 5806 end)); 5807 5808 dinfo = device_get_ivars(child); 5809 if (dinfo->cfg.flags & PCICFG_VF) { 5810 switch (rman_get_type(r)) { 5811 /* VFs can't have I/O BARs. */ 5812 case SYS_RES_IOPORT: 5813 return (EINVAL); 5814 case SYS_RES_MEMORY: 5815 return (pci_vf_adjust_mem_resource(dev, child, r, 5816 start, end)); 5817 } 5818 5819 /* Fall through for other types of resource allocations. */ 5820 } 5821 #endif 5822 5823 return (bus_generic_adjust_resource(dev, child, r, start, end)); 5824 } 5825 5826 int 5827 pci_map_resource(device_t dev, device_t child, struct resource *r, 5828 struct resource_map_request *argsp, struct resource_map *map) 5829 { 5830 #ifdef PCI_IOV 5831 struct pci_devinfo *dinfo; 5832 5833 if (device_get_parent(child) != dev) 5834 return (bus_generic_map_resource(dev, child, r, argsp, 5835 map)); 5836 5837 dinfo = device_get_ivars(child); 5838 if (dinfo->cfg.flags & PCICFG_VF) { 5839 switch (rman_get_type(r)) { 5840 /* VFs can't have I/O BARs. */ 5841 case SYS_RES_IOPORT: 5842 return (EINVAL); 5843 case SYS_RES_MEMORY: 5844 return (pci_vf_map_mem_resource(dev, child, r, argsp, 5845 map)); 5846 } 5847 5848 /* Fall through for other types of resource allocations. */ 5849 } 5850 #endif 5851 5852 return (bus_generic_map_resource(dev, child, r, argsp, map)); 5853 } 5854 5855 int 5856 pci_unmap_resource(device_t dev, device_t child, struct resource *r, 5857 struct resource_map *map) 5858 { 5859 #ifdef PCI_IOV 5860 struct pci_devinfo *dinfo; 5861 5862 if (device_get_parent(child) != dev) 5863 return (bus_generic_unmap_resource(dev, child, r, map)); 5864 5865 dinfo = device_get_ivars(child); 5866 if (dinfo->cfg.flags & PCICFG_VF) { 5867 switch (rman_get_type(r)) { 5868 /* VFs can't have I/O BARs. */ 5869 case SYS_RES_IOPORT: 5870 return (EINVAL); 5871 case SYS_RES_MEMORY: 5872 return (pci_vf_unmap_mem_resource(dev, child, r, map)); 5873 } 5874 5875 /* Fall through for other types of resource allocations. */ 5876 } 5877 #endif 5878 5879 return (bus_generic_unmap_resource(dev, child, r, map)); 5880 } 5881 5882 void 5883 pci_child_deleted(device_t dev, device_t child) 5884 { 5885 struct resource_list_entry *rle; 5886 struct resource_list *rl; 5887 struct pci_devinfo *dinfo; 5888 5889 dinfo = device_get_ivars(child); 5890 rl = &dinfo->resources; 5891 5892 EVENTHANDLER_INVOKE(pci_delete_device, child); 5893 5894 /* Turn off access to resources we're about to free */ 5895 if (bus_child_present(child) != 0) { 5896 pci_write_config(child, PCIR_COMMAND, pci_read_config(child, 5897 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2); 5898 5899 pci_disable_busmaster(child); 5900 } 5901 5902 /* Free all allocated resources */ 5903 STAILQ_FOREACH(rle, rl, link) { 5904 if (rle->res) { 5905 if (rman_get_flags(rle->res) & RF_ACTIVE || 5906 resource_list_busy(rl, rle->type, rle->rid)) { 5907 pci_printf(&dinfo->cfg, 5908 "Resource still owned, oops. " 5909 "(type=%d, rid=%d, addr=%lx)\n", 5910 rle->type, rle->rid, 5911 rman_get_start(rle->res)); 5912 bus_release_resource(child, rle->type, rle->rid, 5913 rle->res); 5914 } 5915 resource_list_unreserve(rl, dev, child, rle->type, 5916 rle->rid); 5917 } 5918 } 5919 resource_list_free(rl); 5920 5921 pci_freecfg(dinfo); 5922 } 5923 5924 void 5925 pci_delete_resource(device_t dev, device_t child, int type, int rid) 5926 { 5927 struct pci_devinfo *dinfo; 5928 struct resource_list *rl; 5929 struct resource_list_entry *rle; 5930 5931 if (device_get_parent(child) != dev) 5932 return; 5933 5934 dinfo = device_get_ivars(child); 5935 rl = &dinfo->resources; 5936 rle = resource_list_find(rl, type, rid); 5937 if (rle == NULL) 5938 return; 5939 5940 if (rle->res) { 5941 if (rman_get_flags(rle->res) & RF_ACTIVE || 5942 resource_list_busy(rl, type, rid)) { 5943 device_printf(dev, "delete_resource: " 5944 "Resource still owned by child, oops. " 5945 "(type=%d, rid=%d, addr=%jx)\n", 5946 type, rid, rman_get_start(rle->res)); 5947 return; 5948 } 5949 resource_list_unreserve(rl, dev, child, type, rid); 5950 } 5951 resource_list_delete(rl, type, rid); 5952 } 5953 5954 struct resource_list * 5955 pci_get_resource_list (device_t dev, device_t child) 5956 { 5957 struct pci_devinfo *dinfo = device_get_ivars(child); 5958 5959 return (&dinfo->resources); 5960 } 5961 5962 #ifdef IOMMU 5963 bus_dma_tag_t 5964 pci_get_dma_tag(device_t bus, device_t dev) 5965 { 5966 bus_dma_tag_t tag; 5967 struct pci_softc *sc; 5968 5969 if (device_get_parent(dev) == bus) { 5970 /* try iommu and return if it works */ 5971 tag = iommu_get_dma_tag(bus, dev); 5972 } else 5973 tag = NULL; 5974 if (tag == NULL) { 5975 sc = device_get_softc(bus); 5976 tag = sc->sc_dma_tag; 5977 } 5978 return (tag); 5979 } 5980 #else 5981 bus_dma_tag_t 5982 pci_get_dma_tag(device_t bus, device_t dev) 5983 { 5984 struct pci_softc *sc = device_get_softc(bus); 5985 5986 return (sc->sc_dma_tag); 5987 } 5988 #endif 5989 5990 uint32_t 5991 pci_read_config_method(device_t dev, device_t child, int reg, int width) 5992 { 5993 struct pci_devinfo *dinfo = device_get_ivars(child); 5994 pcicfgregs *cfg = &dinfo->cfg; 5995 5996 #ifdef PCI_IOV 5997 /* 5998 * SR-IOV VFs don't implement the VID or DID registers, so we have to 5999 * emulate them here. 6000 */ 6001 if (cfg->flags & PCICFG_VF) { 6002 if (reg == PCIR_VENDOR) { 6003 switch (width) { 6004 case 4: 6005 return (cfg->device << 16 | cfg->vendor); 6006 case 2: 6007 return (cfg->vendor); 6008 case 1: 6009 return (cfg->vendor & 0xff); 6010 default: 6011 return (0xffffffff); 6012 } 6013 } else if (reg == PCIR_DEVICE) { 6014 switch (width) { 6015 /* Note that an unaligned 4-byte read is an error. */ 6016 case 2: 6017 return (cfg->device); 6018 case 1: 6019 return (cfg->device & 0xff); 6020 default: 6021 return (0xffffffff); 6022 } 6023 } 6024 } 6025 #endif 6026 6027 return (PCIB_READ_CONFIG(device_get_parent(dev), 6028 cfg->bus, cfg->slot, cfg->func, reg, width)); 6029 } 6030 6031 void 6032 pci_write_config_method(device_t dev, device_t child, int reg, 6033 uint32_t val, int width) 6034 { 6035 struct pci_devinfo *dinfo = device_get_ivars(child); 6036 pcicfgregs *cfg = &dinfo->cfg; 6037 6038 PCIB_WRITE_CONFIG(device_get_parent(dev), 6039 cfg->bus, cfg->slot, cfg->func, reg, val, width); 6040 } 6041 6042 int 6043 pci_child_location_method(device_t dev, device_t child, struct sbuf *sb) 6044 { 6045 6046 sbuf_printf(sb, "slot=%d function=%d dbsf=pci%d:%d:%d:%d", 6047 pci_get_slot(child), pci_get_function(child), pci_get_domain(child), 6048 pci_get_bus(child), pci_get_slot(child), pci_get_function(child)); 6049 return (0); 6050 } 6051 6052 int 6053 pci_child_pnpinfo_method(device_t dev, device_t child, struct sbuf *sb) 6054 { 6055 struct pci_devinfo *dinfo; 6056 pcicfgregs *cfg; 6057 6058 dinfo = device_get_ivars(child); 6059 cfg = &dinfo->cfg; 6060 sbuf_printf(sb, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 6061 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 6062 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 6063 cfg->progif); 6064 return (0); 6065 } 6066 6067 int 6068 pci_get_device_path_method(device_t bus, device_t child, const char *locator, 6069 struct sbuf *sb) 6070 { 6071 device_t parent = device_get_parent(bus); 6072 int rv; 6073 6074 if (strcmp(locator, BUS_LOCATOR_UEFI) == 0) { 6075 rv = bus_generic_get_device_path(parent, bus, locator, sb); 6076 if (rv == 0) { 6077 sbuf_printf(sb, "/Pci(0x%x,0x%x)", pci_get_slot(child), 6078 pci_get_function(child)); 6079 } 6080 return (0); 6081 } 6082 return (bus_generic_get_device_path(bus, child, locator, sb)); 6083 } 6084 6085 int 6086 pci_assign_interrupt_method(device_t dev, device_t child) 6087 { 6088 struct pci_devinfo *dinfo = device_get_ivars(child); 6089 pcicfgregs *cfg = &dinfo->cfg; 6090 6091 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 6092 cfg->intpin)); 6093 } 6094 6095 static void 6096 pci_lookup(void *arg, const char *name, device_t *dev) 6097 { 6098 long val; 6099 char *end; 6100 int domain, bus, slot, func; 6101 6102 if (*dev != NULL) 6103 return; 6104 6105 /* 6106 * Accept pciconf-style selectors of either pciD:B:S:F or 6107 * pciB:S:F. In the latter case, the domain is assumed to 6108 * be zero. 6109 */ 6110 if (strncmp(name, "pci", 3) != 0) 6111 return; 6112 val = strtol(name + 3, &end, 10); 6113 if (val < 0 || val > INT_MAX || *end != ':') 6114 return; 6115 domain = val; 6116 val = strtol(end + 1, &end, 10); 6117 if (val < 0 || val > INT_MAX || *end != ':') 6118 return; 6119 bus = val; 6120 val = strtol(end + 1, &end, 10); 6121 if (val < 0 || val > INT_MAX) 6122 return; 6123 slot = val; 6124 if (*end == ':') { 6125 val = strtol(end + 1, &end, 10); 6126 if (val < 0 || val > INT_MAX || *end != '\0') 6127 return; 6128 func = val; 6129 } else if (*end == '\0') { 6130 func = slot; 6131 slot = bus; 6132 bus = domain; 6133 domain = 0; 6134 } else 6135 return; 6136 6137 if (domain > PCI_DOMAINMAX || bus > PCI_BUSMAX || slot > PCI_SLOTMAX || 6138 func > PCIE_ARI_FUNCMAX || (slot != 0 && func > PCI_FUNCMAX)) 6139 return; 6140 6141 *dev = pci_find_dbsf(domain, bus, slot, func); 6142 } 6143 6144 static int 6145 pci_modevent(module_t mod, int what, void *arg) 6146 { 6147 static struct cdev *pci_cdev; 6148 static eventhandler_tag tag; 6149 6150 switch (what) { 6151 case MOD_LOAD: 6152 STAILQ_INIT(&pci_devq); 6153 pci_generation = 0; 6154 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 6155 "pci"); 6156 pci_load_vendor_data(); 6157 tag = EVENTHANDLER_REGISTER(dev_lookup, pci_lookup, NULL, 6158 1000); 6159 break; 6160 6161 case MOD_UNLOAD: 6162 if (tag != NULL) 6163 EVENTHANDLER_DEREGISTER(dev_lookup, tag); 6164 destroy_dev(pci_cdev); 6165 break; 6166 } 6167 6168 return (0); 6169 } 6170 6171 static void 6172 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo) 6173 { 6174 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2) 6175 struct pcicfg_pcie *cfg; 6176 int version, pos; 6177 6178 cfg = &dinfo->cfg.pcie; 6179 pos = cfg->pcie_location; 6180 6181 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6182 6183 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); 6184 6185 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6186 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6187 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6188 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); 6189 6190 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6191 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6192 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6193 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); 6194 6195 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6196 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6197 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); 6198 6199 if (version > 1) { 6200 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); 6201 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); 6202 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); 6203 } 6204 #undef WREG 6205 } 6206 6207 static void 6208 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo) 6209 { 6210 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 6211 dinfo->cfg.pcix.pcix_command, 2); 6212 } 6213 6214 void 6215 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 6216 { 6217 6218 /* 6219 * Restore the device to full power mode. We must do this 6220 * before we restore the registers because moving from D3 to 6221 * D0 will cause the chip's BARs and some other registers to 6222 * be reset to some unknown power on reset values. Cut down 6223 * the noise on boot by doing nothing if we are already in 6224 * state D0. 6225 */ 6226 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) 6227 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6228 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 6229 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 6230 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 6231 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 6232 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 6233 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 6234 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6235 case PCIM_HDRTYPE_NORMAL: 6236 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 6237 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 6238 break; 6239 case PCIM_HDRTYPE_BRIDGE: 6240 pci_write_config(dev, PCIR_SECLAT_1, 6241 dinfo->cfg.bridge.br_seclat, 1); 6242 pci_write_config(dev, PCIR_SUBBUS_1, 6243 dinfo->cfg.bridge.br_subbus, 1); 6244 pci_write_config(dev, PCIR_SECBUS_1, 6245 dinfo->cfg.bridge.br_secbus, 1); 6246 pci_write_config(dev, PCIR_PRIBUS_1, 6247 dinfo->cfg.bridge.br_pribus, 1); 6248 pci_write_config(dev, PCIR_BRIDGECTL_1, 6249 dinfo->cfg.bridge.br_control, 2); 6250 break; 6251 case PCIM_HDRTYPE_CARDBUS: 6252 pci_write_config(dev, PCIR_SECLAT_2, 6253 dinfo->cfg.bridge.br_seclat, 1); 6254 pci_write_config(dev, PCIR_SUBBUS_2, 6255 dinfo->cfg.bridge.br_subbus, 1); 6256 pci_write_config(dev, PCIR_SECBUS_2, 6257 dinfo->cfg.bridge.br_secbus, 1); 6258 pci_write_config(dev, PCIR_PRIBUS_2, 6259 dinfo->cfg.bridge.br_pribus, 1); 6260 pci_write_config(dev, PCIR_BRIDGECTL_2, 6261 dinfo->cfg.bridge.br_control, 2); 6262 break; 6263 } 6264 pci_restore_bars(dev); 6265 6266 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE) 6267 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 6268 6269 /* 6270 * Restore extended capabilities for PCI-Express and PCI-X 6271 */ 6272 if (dinfo->cfg.pcie.pcie_location != 0) 6273 pci_cfg_restore_pcie(dev, dinfo); 6274 if (dinfo->cfg.pcix.pcix_location != 0) 6275 pci_cfg_restore_pcix(dev, dinfo); 6276 6277 /* Restore MSI and MSI-X configurations if they are present. */ 6278 if (dinfo->cfg.msi.msi_location != 0) 6279 pci_resume_msi(dev); 6280 if (dinfo->cfg.msix.msix_location != 0) 6281 pci_resume_msix(dev); 6282 6283 #ifdef PCI_IOV 6284 if (dinfo->cfg.iov != NULL) 6285 pci_iov_cfg_restore(dev, dinfo); 6286 #endif 6287 } 6288 6289 static void 6290 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo) 6291 { 6292 #define RREG(n) pci_read_config(dev, pos + (n), 2) 6293 struct pcicfg_pcie *cfg; 6294 int version, pos; 6295 6296 cfg = &dinfo->cfg.pcie; 6297 pos = cfg->pcie_location; 6298 6299 cfg->pcie_flags = RREG(PCIER_FLAGS); 6300 6301 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6302 6303 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); 6304 6305 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6306 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6307 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6308 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); 6309 6310 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6311 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6312 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6313 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); 6314 6315 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6316 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6317 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); 6318 6319 if (version > 1) { 6320 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); 6321 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); 6322 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); 6323 } 6324 #undef RREG 6325 } 6326 6327 static void 6328 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo) 6329 { 6330 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, 6331 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); 6332 } 6333 6334 void 6335 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 6336 { 6337 uint32_t cls; 6338 int ps; 6339 6340 /* 6341 * Some drivers apparently write to these registers w/o updating our 6342 * cached copy. No harm happens if we update the copy, so do so here 6343 * so we can restore them. The COMMAND register is modified by the 6344 * bus w/o updating the cache. This should represent the normally 6345 * writable portion of the 'defined' part of type 0/1/2 headers. 6346 */ 6347 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 6348 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 6349 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 6350 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 6351 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 6352 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 6353 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 6354 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 6355 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 6356 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 6357 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 6358 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6359 case PCIM_HDRTYPE_NORMAL: 6360 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 6361 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 6362 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 6363 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 6364 break; 6365 case PCIM_HDRTYPE_BRIDGE: 6366 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6367 PCIR_SECLAT_1, 1); 6368 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6369 PCIR_SUBBUS_1, 1); 6370 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6371 PCIR_SECBUS_1, 1); 6372 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6373 PCIR_PRIBUS_1, 1); 6374 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6375 PCIR_BRIDGECTL_1, 2); 6376 break; 6377 case PCIM_HDRTYPE_CARDBUS: 6378 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6379 PCIR_SECLAT_2, 1); 6380 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6381 PCIR_SUBBUS_2, 1); 6382 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6383 PCIR_SECBUS_2, 1); 6384 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6385 PCIR_PRIBUS_2, 1); 6386 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6387 PCIR_BRIDGECTL_2, 2); 6388 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2); 6389 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2); 6390 break; 6391 } 6392 6393 if (dinfo->cfg.pcie.pcie_location != 0) 6394 pci_cfg_save_pcie(dev, dinfo); 6395 6396 if (dinfo->cfg.pcix.pcix_location != 0) 6397 pci_cfg_save_pcix(dev, dinfo); 6398 6399 #ifdef PCI_IOV 6400 if (dinfo->cfg.iov != NULL) 6401 pci_iov_cfg_save(dev, dinfo); 6402 #endif 6403 6404 /* 6405 * don't set the state for display devices, base peripherals and 6406 * memory devices since bad things happen when they are powered down. 6407 * We should (a) have drivers that can easily detach and (b) use 6408 * generic drivers for these devices so that some device actually 6409 * attaches. We need to make sure that when we implement (a) we don't 6410 * power the device down on a reattach. 6411 */ 6412 cls = pci_get_class(dev); 6413 if (!setstate) 6414 return; 6415 switch (pci_do_power_nodriver) 6416 { 6417 case 0: /* NO powerdown at all */ 6418 return; 6419 case 1: /* Conservative about what to power down */ 6420 if (cls == PCIC_STORAGE) 6421 return; 6422 /*FALLTHROUGH*/ 6423 case 2: /* Aggressive about what to power down */ 6424 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 6425 cls == PCIC_BASEPERIPH) 6426 return; 6427 /*FALLTHROUGH*/ 6428 case 3: /* Power down everything */ 6429 break; 6430 } 6431 /* 6432 * PCI spec says we can only go into D3 state from D0 state. 6433 * Transition from D[12] into D0 before going to D3 state. 6434 */ 6435 ps = pci_get_powerstate(dev); 6436 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6437 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6438 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 6439 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6440 } 6441 6442 /* Wrapper APIs suitable for device driver use. */ 6443 void 6444 pci_save_state(device_t dev) 6445 { 6446 struct pci_devinfo *dinfo; 6447 6448 dinfo = device_get_ivars(dev); 6449 pci_cfg_save(dev, dinfo, 0); 6450 } 6451 6452 void 6453 pci_restore_state(device_t dev) 6454 { 6455 struct pci_devinfo *dinfo; 6456 6457 dinfo = device_get_ivars(dev); 6458 pci_cfg_restore(dev, dinfo); 6459 } 6460 6461 static int 6462 pci_get_id_method(device_t dev, device_t child, enum pci_id_type type, 6463 uintptr_t *id) 6464 { 6465 6466 return (PCIB_GET_ID(device_get_parent(dev), child, type, id)); 6467 } 6468 6469 /* Find the upstream port of a given PCI device in a root complex. */ 6470 device_t 6471 pci_find_pcie_root_port(device_t dev) 6472 { 6473 struct pci_devinfo *dinfo; 6474 devclass_t pci_class; 6475 device_t pcib, bus; 6476 6477 pci_class = devclass_find("pci"); 6478 KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class, 6479 ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); 6480 6481 /* 6482 * Walk the bridge hierarchy until we find a PCI-e root 6483 * port or a non-PCI device. 6484 */ 6485 for (;;) { 6486 bus = device_get_parent(dev); 6487 KASSERT(bus != NULL, ("%s: null parent of %s", __func__, 6488 device_get_nameunit(dev))); 6489 6490 pcib = device_get_parent(bus); 6491 KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__, 6492 device_get_nameunit(bus))); 6493 6494 /* 6495 * pcib's parent must be a PCI bus for this to be a 6496 * PCI-PCI bridge. 6497 */ 6498 if (device_get_devclass(device_get_parent(pcib)) != pci_class) 6499 return (NULL); 6500 6501 dinfo = device_get_ivars(pcib); 6502 if (dinfo->cfg.pcie.pcie_location != 0 && 6503 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) 6504 return (pcib); 6505 6506 dev = pcib; 6507 } 6508 } 6509 6510 /* 6511 * Wait for pending transactions to complete on a PCI-express function. 6512 * 6513 * The maximum delay is specified in milliseconds in max_delay. Note 6514 * that this function may sleep. 6515 * 6516 * Returns true if the function is idle and false if the timeout is 6517 * exceeded. If dev is not a PCI-express function, this returns true. 6518 */ 6519 bool 6520 pcie_wait_for_pending_transactions(device_t dev, u_int max_delay) 6521 { 6522 struct pci_devinfo *dinfo = device_get_ivars(dev); 6523 uint16_t sta; 6524 int cap; 6525 6526 cap = dinfo->cfg.pcie.pcie_location; 6527 if (cap == 0) 6528 return (true); 6529 6530 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6531 while (sta & PCIEM_STA_TRANSACTION_PND) { 6532 if (max_delay == 0) 6533 return (false); 6534 6535 /* Poll once every 100 milliseconds up to the timeout. */ 6536 if (max_delay > 100) { 6537 pause_sbt("pcietp", 100 * SBT_1MS, 0, C_HARDCLOCK); 6538 max_delay -= 100; 6539 } else { 6540 pause_sbt("pcietp", max_delay * SBT_1MS, 0, 6541 C_HARDCLOCK); 6542 max_delay = 0; 6543 } 6544 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6545 } 6546 6547 return (true); 6548 } 6549 6550 /* 6551 * Determine the maximum Completion Timeout in microseconds. 6552 * 6553 * For non-PCI-express functions this returns 0. 6554 */ 6555 int 6556 pcie_get_max_completion_timeout(device_t dev) 6557 { 6558 struct pci_devinfo *dinfo = device_get_ivars(dev); 6559 int cap; 6560 6561 cap = dinfo->cfg.pcie.pcie_location; 6562 if (cap == 0) 6563 return (0); 6564 6565 /* 6566 * Functions using the 1.x spec use the default timeout range of 6567 * 50 microseconds to 50 milliseconds. Functions that do not 6568 * support programmable timeouts also use this range. 6569 */ 6570 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 || 6571 (pci_read_config(dev, cap + PCIER_DEVICE_CAP2, 4) & 6572 PCIEM_CAP2_COMP_TIMO_RANGES) == 0) 6573 return (50 * 1000); 6574 6575 switch (pci_read_config(dev, cap + PCIER_DEVICE_CTL2, 2) & 6576 PCIEM_CTL2_COMP_TIMO_VAL) { 6577 case PCIEM_CTL2_COMP_TIMO_100US: 6578 return (100); 6579 case PCIEM_CTL2_COMP_TIMO_10MS: 6580 return (10 * 1000); 6581 case PCIEM_CTL2_COMP_TIMO_55MS: 6582 return (55 * 1000); 6583 case PCIEM_CTL2_COMP_TIMO_210MS: 6584 return (210 * 1000); 6585 case PCIEM_CTL2_COMP_TIMO_900MS: 6586 return (900 * 1000); 6587 case PCIEM_CTL2_COMP_TIMO_3500MS: 6588 return (3500 * 1000); 6589 case PCIEM_CTL2_COMP_TIMO_13S: 6590 return (13 * 1000 * 1000); 6591 case PCIEM_CTL2_COMP_TIMO_64S: 6592 return (64 * 1000 * 1000); 6593 default: 6594 return (50 * 1000); 6595 } 6596 } 6597 6598 void 6599 pcie_apei_error(device_t dev, int sev, uint8_t *aerp) 6600 { 6601 struct pci_devinfo *dinfo = device_get_ivars(dev); 6602 const char *s; 6603 int aer; 6604 uint32_t r, r1; 6605 uint16_t rs; 6606 6607 if (sev == PCIEM_STA_CORRECTABLE_ERROR) 6608 s = "Correctable"; 6609 else if (sev == PCIEM_STA_NON_FATAL_ERROR) 6610 s = "Uncorrectable (Non-Fatal)"; 6611 else 6612 s = "Uncorrectable (Fatal)"; 6613 device_printf(dev, "%s PCIe error reported by APEI\n", s); 6614 if (aerp) { 6615 if (sev == PCIEM_STA_CORRECTABLE_ERROR) { 6616 r = le32dec(aerp + PCIR_AER_COR_STATUS); 6617 r1 = le32dec(aerp + PCIR_AER_COR_MASK); 6618 } else { 6619 r = le32dec(aerp + PCIR_AER_UC_STATUS); 6620 r1 = le32dec(aerp + PCIR_AER_UC_MASK); 6621 } 6622 device_printf(dev, "status 0x%08x mask 0x%08x", r, r1); 6623 if (sev != PCIEM_STA_CORRECTABLE_ERROR) { 6624 r = le32dec(aerp + PCIR_AER_UC_SEVERITY); 6625 rs = le16dec(aerp + PCIR_AER_CAP_CONTROL); 6626 printf(" severity 0x%08x first %d\n", 6627 r, rs & 0x1f); 6628 } else 6629 printf("\n"); 6630 } 6631 6632 /* As kind of recovery just report and clear the error statuses. */ 6633 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6634 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6635 if (r != 0) { 6636 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6637 device_printf(dev, "Clearing UC AER errors 0x%08x\n", r); 6638 } 6639 6640 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6641 if (r != 0) { 6642 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6643 device_printf(dev, "Clearing COR AER errors 0x%08x\n", r); 6644 } 6645 } 6646 if (dinfo->cfg.pcie.pcie_location != 0) { 6647 rs = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6648 PCIER_DEVICE_STA, 2); 6649 if ((rs & (PCIEM_STA_CORRECTABLE_ERROR | 6650 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6651 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6652 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6653 PCIER_DEVICE_STA, rs, 2); 6654 device_printf(dev, "Clearing PCIe errors 0x%04x\n", rs); 6655 } 6656 } 6657 } 6658 6659 /* 6660 * Perform a Function Level Reset (FLR) on a device. 6661 * 6662 * This function first waits for any pending transactions to complete 6663 * within the timeout specified by max_delay. If transactions are 6664 * still pending, the function will return false without attempting a 6665 * reset. 6666 * 6667 * If dev is not a PCI-express function or does not support FLR, this 6668 * function returns false. 6669 * 6670 * Note that no registers are saved or restored. The caller is 6671 * responsible for saving and restoring any registers including 6672 * PCI-standard registers via pci_save_state() and 6673 * pci_restore_state(). 6674 */ 6675 bool 6676 pcie_flr(device_t dev, u_int max_delay, bool force) 6677 { 6678 struct pci_devinfo *dinfo = device_get_ivars(dev); 6679 uint16_t cmd, ctl; 6680 int compl_delay; 6681 int cap; 6682 6683 cap = dinfo->cfg.pcie.pcie_location; 6684 if (cap == 0) 6685 return (false); 6686 6687 if (!(pci_read_config(dev, cap + PCIER_DEVICE_CAP, 4) & PCIEM_CAP_FLR)) 6688 return (false); 6689 6690 /* 6691 * Disable busmastering to prevent generation of new 6692 * transactions while waiting for the device to go idle. If 6693 * the idle timeout fails, the command register is restored 6694 * which will re-enable busmastering. 6695 */ 6696 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 6697 pci_write_config(dev, PCIR_COMMAND, cmd & ~(PCIM_CMD_BUSMASTEREN), 2); 6698 if (!pcie_wait_for_pending_transactions(dev, max_delay)) { 6699 if (!force) { 6700 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 6701 return (false); 6702 } 6703 pci_printf(&dinfo->cfg, 6704 "Resetting with transactions pending after %d ms\n", 6705 max_delay); 6706 6707 /* 6708 * Extend the post-FLR delay to cover the maximum 6709 * Completion Timeout delay of anything in flight 6710 * during the FLR delay. Enforce a minimum delay of 6711 * at least 10ms. 6712 */ 6713 compl_delay = pcie_get_max_completion_timeout(dev) / 1000; 6714 if (compl_delay < 10) 6715 compl_delay = 10; 6716 } else 6717 compl_delay = 0; 6718 6719 /* Initiate the reset. */ 6720 ctl = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 6721 pci_write_config(dev, cap + PCIER_DEVICE_CTL, ctl | 6722 PCIEM_CTL_INITIATE_FLR, 2); 6723 6724 /* Wait for 100ms. */ 6725 pause_sbt("pcieflr", (100 + compl_delay) * SBT_1MS, 0, C_HARDCLOCK); 6726 6727 if (pci_read_config(dev, cap + PCIER_DEVICE_STA, 2) & 6728 PCIEM_STA_TRANSACTION_PND) 6729 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n"); 6730 return (true); 6731 } 6732 6733 /* 6734 * Attempt a power-management reset by cycling the device in/out of D3 6735 * state. PCI spec says we can only go into D3 state from D0 state. 6736 * Transition from D[12] into D0 before going to D3 state. 6737 */ 6738 int 6739 pci_power_reset(device_t dev) 6740 { 6741 int ps; 6742 6743 ps = pci_get_powerstate(dev); 6744 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6745 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6746 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6747 pci_set_powerstate(dev, ps); 6748 return (0); 6749 } 6750 6751 /* 6752 * Try link drop and retrain of the downstream port of upstream 6753 * switch, for PCIe. According to the PCIe 3.0 spec 6.6.1, this must 6754 * cause Conventional Hot reset of the device in the slot. 6755 * Alternative, for PCIe, could be the secondary bus reset initiatied 6756 * on the upstream switch PCIR_BRIDGECTL_1, bit 6. 6757 */ 6758 int 6759 pcie_link_reset(device_t port, int pcie_location) 6760 { 6761 uint16_t v; 6762 6763 v = pci_read_config(port, pcie_location + PCIER_LINK_CTL, 2); 6764 v |= PCIEM_LINK_CTL_LINK_DIS; 6765 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6766 pause_sbt("pcier1", mstosbt(20), 0, 0); 6767 v &= ~PCIEM_LINK_CTL_LINK_DIS; 6768 v |= PCIEM_LINK_CTL_RETRAIN_LINK; 6769 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6770 pause_sbt("pcier2", mstosbt(100), 0, 0); /* 100 ms */ 6771 v = pci_read_config(port, pcie_location + PCIER_LINK_STA, 2); 6772 return ((v & PCIEM_LINK_STA_TRAINING) != 0 ? ETIMEDOUT : 0); 6773 } 6774 6775 static int 6776 pci_reset_post(device_t dev, device_t child) 6777 { 6778 6779 if (dev == device_get_parent(child)) 6780 pci_restore_state(child); 6781 return (0); 6782 } 6783 6784 static int 6785 pci_reset_prepare(device_t dev, device_t child) 6786 { 6787 6788 if (dev == device_get_parent(child)) 6789 pci_save_state(child); 6790 return (0); 6791 } 6792 6793 static int 6794 pci_reset_child(device_t dev, device_t child, int flags) 6795 { 6796 int error; 6797 6798 if (dev == NULL || device_get_parent(child) != dev) 6799 return (0); 6800 if ((flags & DEVF_RESET_DETACH) != 0) { 6801 error = device_get_state(child) == DS_ATTACHED ? 6802 device_detach(child) : 0; 6803 } else { 6804 error = BUS_SUSPEND_CHILD(dev, child); 6805 } 6806 if (error == 0) { 6807 if (!pcie_flr(child, 1000, false)) { 6808 error = BUS_RESET_PREPARE(dev, child); 6809 if (error == 0) 6810 pci_power_reset(child); 6811 BUS_RESET_POST(dev, child); 6812 } 6813 if ((flags & DEVF_RESET_DETACH) != 0) 6814 device_probe_and_attach(child); 6815 else 6816 BUS_RESUME_CHILD(dev, child); 6817 } 6818 return (error); 6819 } 6820 6821 const struct pci_device_table * 6822 pci_match_device(device_t child, const struct pci_device_table *id, size_t nelt) 6823 { 6824 bool match; 6825 uint16_t vendor, device, subvendor, subdevice, class, subclass, revid; 6826 6827 vendor = pci_get_vendor(child); 6828 device = pci_get_device(child); 6829 subvendor = pci_get_subvendor(child); 6830 subdevice = pci_get_subdevice(child); 6831 class = pci_get_class(child); 6832 subclass = pci_get_subclass(child); 6833 revid = pci_get_revid(child); 6834 while (nelt-- > 0) { 6835 match = true; 6836 if (id->match_flag_vendor) 6837 match &= vendor == id->vendor; 6838 if (id->match_flag_device) 6839 match &= device == id->device; 6840 if (id->match_flag_subvendor) 6841 match &= subvendor == id->subvendor; 6842 if (id->match_flag_subdevice) 6843 match &= subdevice == id->subdevice; 6844 if (id->match_flag_class) 6845 match &= class == id->class_id; 6846 if (id->match_flag_subclass) 6847 match &= subclass == id->subclass; 6848 if (id->match_flag_revid) 6849 match &= revid == id->revid; 6850 if (match) 6851 return (id); 6852 id++; 6853 } 6854 return (NULL); 6855 } 6856 6857 static void 6858 pci_print_faulted_dev_name(const struct pci_devinfo *dinfo) 6859 { 6860 const char *dev_name; 6861 device_t dev; 6862 6863 dev = dinfo->cfg.dev; 6864 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus, 6865 dinfo->cfg.slot, dinfo->cfg.func); 6866 dev_name = device_get_name(dev); 6867 if (dev_name != NULL) 6868 printf(" (%s%d)", dev_name, device_get_unit(dev)); 6869 } 6870 6871 void 6872 pci_print_faulted_dev(void) 6873 { 6874 struct pci_devinfo *dinfo; 6875 device_t dev; 6876 int aer, i; 6877 uint32_t r1, r2; 6878 uint16_t status; 6879 6880 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6881 dev = dinfo->cfg.dev; 6882 status = pci_read_config(dev, PCIR_STATUS, 2); 6883 status &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6884 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6885 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6886 if (status != 0) { 6887 pci_print_faulted_dev_name(dinfo); 6888 printf(" error 0x%04x\n", status); 6889 } 6890 if (dinfo->cfg.pcie.pcie_location != 0) { 6891 status = pci_read_config(dev, 6892 dinfo->cfg.pcie.pcie_location + 6893 PCIER_DEVICE_STA, 2); 6894 if ((status & (PCIEM_STA_CORRECTABLE_ERROR | 6895 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6896 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6897 pci_print_faulted_dev_name(dinfo); 6898 printf(" PCIe DEVCTL 0x%04x DEVSTA 0x%04x\n", 6899 pci_read_config(dev, 6900 dinfo->cfg.pcie.pcie_location + 6901 PCIER_DEVICE_CTL, 2), 6902 status); 6903 } 6904 } 6905 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6906 r1 = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6907 r2 = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6908 if (r1 != 0 || r2 != 0) { 6909 pci_print_faulted_dev_name(dinfo); 6910 printf(" AER UC 0x%08x Mask 0x%08x Svr 0x%08x\n" 6911 " COR 0x%08x Mask 0x%08x Ctl 0x%08x\n", 6912 r1, pci_read_config(dev, aer + 6913 PCIR_AER_UC_MASK, 4), 6914 pci_read_config(dev, aer + 6915 PCIR_AER_UC_SEVERITY, 4), 6916 r2, pci_read_config(dev, aer + 6917 PCIR_AER_COR_MASK, 4), 6918 pci_read_config(dev, aer + 6919 PCIR_AER_CAP_CONTROL, 4)); 6920 for (i = 0; i < 4; i++) { 6921 r1 = pci_read_config(dev, aer + 6922 PCIR_AER_HEADER_LOG + i * 4, 4); 6923 printf(" HL%d: 0x%08x\n", i, r1); 6924 } 6925 } 6926 } 6927 } 6928 } 6929 6930 #ifdef DDB 6931 DB_SHOW_COMMAND_FLAGS(pcierr, pci_print_faulted_dev_db, DB_CMD_MEMSAFE) 6932 { 6933 6934 pci_print_faulted_dev(); 6935 } 6936 6937 static void 6938 db_clear_pcie_errors(const struct pci_devinfo *dinfo) 6939 { 6940 device_t dev; 6941 int aer; 6942 uint32_t r; 6943 6944 dev = dinfo->cfg.dev; 6945 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6946 PCIER_DEVICE_STA, 2); 6947 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6948 PCIER_DEVICE_STA, r, 2); 6949 6950 if (pci_find_extcap(dev, PCIZ_AER, &aer) != 0) 6951 return; 6952 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6953 if (r != 0) 6954 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6955 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6956 if (r != 0) 6957 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6958 } 6959 6960 DB_COMMAND_FLAGS(pci_clearerr, db_pci_clearerr, DB_CMD_MEMSAFE) 6961 { 6962 struct pci_devinfo *dinfo; 6963 device_t dev; 6964 uint16_t status, status1; 6965 6966 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6967 dev = dinfo->cfg.dev; 6968 status1 = status = pci_read_config(dev, PCIR_STATUS, 2); 6969 status1 &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6970 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6971 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6972 if (status1 != 0) { 6973 status &= ~status1; 6974 pci_write_config(dev, PCIR_STATUS, status, 2); 6975 } 6976 if (dinfo->cfg.pcie.pcie_location != 0) 6977 db_clear_pcie_errors(dinfo); 6978 } 6979 } 6980 #endif 6981