1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 * 30 */ 31 32 #include "opt_bus.h" 33 #include "opt_pci.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/linker.h> 40 #include <sys/fcntl.h> 41 #include <sys/conf.h> 42 #include <sys/kernel.h> 43 #include <sys/queue.h> 44 #include <sys/types.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 55 #include <sys/pciio.h> 56 #include <pci/pcireg.h> 57 #include <pci/pcivar.h> 58 59 #include "pcib_if.h" 60 #include "pci_if.h" 61 62 static u_int32_t pci_mapbase(unsigned mapreg); 63 static int pci_maptype(unsigned mapreg); 64 static int pci_mapsize(unsigned testval); 65 static int pci_maprange(unsigned mapreg); 66 static void pci_fixancient(pcicfgregs *cfg); 67 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 68 pcicfgregs *cfg); 69 static struct pci_devinfo *pci_read_device(device_t pcib, int b, int s, int f); 70 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 71 72 static void pci_print_verbose(struct pci_devinfo *dinfo); 73 static int pci_porten(device_t pcib, int b, int s, int f); 74 static int pci_memen(device_t pcib, int b, int s, int f); 75 static int pci_add_map(device_t pcib, int b, int s, int f, int reg, 76 struct resource_list *rl); 77 static void pci_add_resources(device_t pcib, int b, int s, int f, 78 device_t dev); 79 static void pci_add_children(device_t dev, int busno); 80 static int pci_probe(device_t dev); 81 static int pci_print_child(device_t dev, device_t child); 82 static void pci_probe_nomatch(device_t dev, device_t child); 83 static int pci_describe_parse_line(char **ptr, int *vendor, 84 int *device, char **desc); 85 static char *pci_describe_device(device_t dev); 86 static int pci_read_ivar(device_t dev, device_t child, int which, 87 uintptr_t *result); 88 static int pci_write_ivar(device_t dev, device_t child, int which, 89 uintptr_t value); 90 static struct resource *pci_alloc_resource(device_t dev, device_t child, 91 int type, int *rid, u_long start, 92 u_long end, u_long count, u_int flags); 93 static void pci_delete_resource(device_t dev, device_t child, 94 int type, int rid); 95 static struct resource_list *pci_get_resource_list (device_t dev, device_t child); 96 static u_int32_t pci_read_config_method(device_t dev, device_t child, 97 int reg, int width); 98 static void pci_write_config_method(device_t dev, device_t child, 99 int reg, u_int32_t val, int width); 100 static void pci_enable_busmaster_method(device_t dev, 101 device_t child); 102 static void pci_disable_busmaster_method(device_t dev, 103 device_t child); 104 static void pci_enable_io_method(device_t dev, device_t child, 105 int space); 106 static void pci_disable_io_method(device_t dev, device_t child, 107 int space); 108 static int pci_set_powerstate_method(device_t dev, device_t child, 109 int state); 110 static int pci_get_powerstate_method(device_t dev, device_t child); 111 static int pci_modevent(module_t mod, int what, void *arg); 112 113 static device_method_t pci_methods[] = { 114 /* Device interface */ 115 DEVMETHOD(device_probe, pci_probe), 116 DEVMETHOD(device_attach, bus_generic_attach), 117 DEVMETHOD(device_shutdown, bus_generic_shutdown), 118 DEVMETHOD(device_suspend, bus_generic_suspend), 119 DEVMETHOD(device_resume, bus_generic_resume), 120 121 /* Bus interface */ 122 DEVMETHOD(bus_print_child, pci_print_child), 123 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 124 DEVMETHOD(bus_read_ivar, pci_read_ivar), 125 DEVMETHOD(bus_write_ivar, pci_write_ivar), 126 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 127 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 128 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 129 130 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 131 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 132 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 133 DEVMETHOD(bus_delete_resource, pci_delete_resource), 134 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 135 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 136 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 137 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 138 139 /* PCI interface */ 140 DEVMETHOD(pci_read_config, pci_read_config_method), 141 DEVMETHOD(pci_write_config, pci_write_config_method), 142 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 143 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 144 DEVMETHOD(pci_enable_io, pci_enable_io_method), 145 DEVMETHOD(pci_disable_io, pci_disable_io_method), 146 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 147 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 148 149 { 0, 0 } 150 }; 151 152 static driver_t pci_driver = { 153 "pci", 154 pci_methods, 155 0, /* no softc */ 156 }; 157 158 static devclass_t pci_devclass; 159 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 160 DRIVER_MODULE(pci, acpi_pcib, pci_driver, pci_devclass, pci_modevent, 0); 161 162 static char *pci_vendordata; 163 static size_t pci_vendordata_size; 164 165 166 struct pci_quirk { 167 u_int32_t devid; /* Vendor/device of the card */ 168 int type; 169 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 170 int arg1; 171 int arg2; 172 }; 173 174 struct pci_quirk pci_quirks[] = { 175 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 176 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 177 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 178 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 179 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 180 181 { 0 } 182 }; 183 184 /* map register information */ 185 #define PCI_MAPMEM 0x01 /* memory map */ 186 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 187 #define PCI_MAPPORT 0x04 /* port map */ 188 189 struct devlist pci_devq; 190 u_int32_t pci_generation; 191 u_int32_t pci_numdevs = 0; 192 193 /* return base address of memory or port map */ 194 195 static u_int32_t 196 pci_mapbase(unsigned mapreg) 197 { 198 int mask = 0x03; 199 if ((mapreg & 0x01) == 0) 200 mask = 0x0f; 201 return (mapreg & ~mask); 202 } 203 204 /* return map type of memory or port map */ 205 206 static int 207 pci_maptype(unsigned mapreg) 208 { 209 static u_int8_t maptype[0x10] = { 210 PCI_MAPMEM, PCI_MAPPORT, 211 PCI_MAPMEM, 0, 212 PCI_MAPMEM, PCI_MAPPORT, 213 0, 0, 214 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 215 PCI_MAPMEM|PCI_MAPMEMP, 0, 216 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 217 0, 0, 218 }; 219 220 return maptype[mapreg & 0x0f]; 221 } 222 223 /* return log2 of map size decoded for memory or port map */ 224 225 static int 226 pci_mapsize(unsigned testval) 227 { 228 int ln2size; 229 230 testval = pci_mapbase(testval); 231 ln2size = 0; 232 if (testval != 0) { 233 while ((testval & 1) == 0) 234 { 235 ln2size++; 236 testval >>= 1; 237 } 238 } 239 return (ln2size); 240 } 241 242 /* return log2 of address range supported by map register */ 243 244 static int 245 pci_maprange(unsigned mapreg) 246 { 247 int ln2range = 0; 248 switch (mapreg & 0x07) { 249 case 0x00: 250 case 0x01: 251 case 0x05: 252 ln2range = 32; 253 break; 254 case 0x02: 255 ln2range = 20; 256 break; 257 case 0x04: 258 ln2range = 64; 259 break; 260 } 261 return (ln2range); 262 } 263 264 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 265 266 static void 267 pci_fixancient(pcicfgregs *cfg) 268 { 269 if (cfg->hdrtype != 0) 270 return; 271 272 /* PCI to PCI bridges use header type 1 */ 273 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 274 cfg->hdrtype = 1; 275 } 276 277 /* extract header type specific config data */ 278 279 static void 280 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 281 { 282 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 283 switch (cfg->hdrtype) { 284 case 0: 285 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 286 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 287 cfg->nummaps = PCI_MAXMAPS_0; 288 break; 289 case 1: 290 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 291 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 292 cfg->nummaps = PCI_MAXMAPS_1; 293 break; 294 case 2: 295 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 296 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 297 cfg->nummaps = PCI_MAXMAPS_2; 298 break; 299 } 300 #undef REG 301 } 302 303 /* read configuration header into pcicfgregs structure */ 304 305 static struct pci_devinfo * 306 pci_read_device(device_t pcib, int b, int s, int f) 307 { 308 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 309 pcicfgregs *cfg = NULL; 310 struct pci_devinfo *devlist_entry; 311 struct devlist *devlist_head; 312 313 devlist_head = &pci_devq; 314 315 devlist_entry = NULL; 316 317 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 318 devlist_entry = malloc(sizeof(struct pci_devinfo), 319 M_DEVBUF, M_WAITOK | M_ZERO); 320 if (devlist_entry == NULL) 321 return (NULL); 322 323 cfg = &devlist_entry->cfg; 324 325 cfg->bus = b; 326 cfg->slot = s; 327 cfg->func = f; 328 cfg->vendor = REG(PCIR_VENDOR, 2); 329 cfg->device = REG(PCIR_DEVICE, 2); 330 cfg->cmdreg = REG(PCIR_COMMAND, 2); 331 cfg->statreg = REG(PCIR_STATUS, 2); 332 cfg->baseclass = REG(PCIR_CLASS, 1); 333 cfg->subclass = REG(PCIR_SUBCLASS, 1); 334 cfg->progif = REG(PCIR_PROGIF, 1); 335 cfg->revid = REG(PCIR_REVID, 1); 336 cfg->hdrtype = REG(PCIR_HEADERTYPE, 1); 337 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 338 cfg->lattimer = REG(PCIR_LATTIMER, 1); 339 cfg->intpin = REG(PCIR_INTPIN, 1); 340 cfg->intline = REG(PCIR_INTLINE, 1); 341 342 cfg->mingnt = REG(PCIR_MINGNT, 1); 343 cfg->maxlat = REG(PCIR_MAXLAT, 1); 344 345 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 346 cfg->hdrtype &= ~PCIM_MFDEV; 347 348 pci_fixancient(cfg); 349 pci_hdrtypedata(pcib, b, s, f, cfg); 350 351 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 352 pci_read_extcap(pcib, cfg); 353 354 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 355 356 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 357 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 358 devlist_entry->conf.pc_sel.pc_func = cfg->func; 359 devlist_entry->conf.pc_hdr = cfg->hdrtype; 360 361 devlist_entry->conf.pc_subvendor = cfg->subvendor; 362 devlist_entry->conf.pc_subdevice = cfg->subdevice; 363 devlist_entry->conf.pc_vendor = cfg->vendor; 364 devlist_entry->conf.pc_device = cfg->device; 365 366 devlist_entry->conf.pc_class = cfg->baseclass; 367 devlist_entry->conf.pc_subclass = cfg->subclass; 368 devlist_entry->conf.pc_progif = cfg->progif; 369 devlist_entry->conf.pc_revid = cfg->revid; 370 371 pci_numdevs++; 372 pci_generation++; 373 } 374 return (devlist_entry); 375 #undef REG 376 } 377 378 static void 379 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 380 { 381 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 382 int ptr, nextptr, ptrptr; 383 384 switch (cfg->hdrtype) { 385 case 0: 386 ptrptr = 0x34; 387 break; 388 case 2: 389 ptrptr = 0x14; 390 break; 391 default: 392 return; /* no extended capabilities support */ 393 } 394 nextptr = REG(ptrptr, 1); /* sanity check? */ 395 396 /* 397 * Read capability entries. 398 */ 399 while (nextptr != 0) { 400 /* Sanity check */ 401 if (nextptr > 255) { 402 printf("illegal PCI extended capability offset %d\n", 403 nextptr); 404 return; 405 } 406 /* Find the next entry */ 407 ptr = nextptr; 408 nextptr = REG(ptr + 1, 1); 409 410 /* Process this entry */ 411 switch (REG(ptr, 1)) { 412 case 0x01: /* PCI power management */ 413 if (cfg->pp_cap == 0) { 414 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 415 cfg->pp_status = ptr + PCIR_POWER_STATUS; 416 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR; 417 if ((nextptr - ptr) > PCIR_POWER_DATA) 418 cfg->pp_data = ptr + PCIR_POWER_DATA; 419 } 420 break; 421 default: 422 break; 423 } 424 } 425 #undef REG 426 } 427 428 #if 0 429 /* free pcicfgregs structure and all depending data structures */ 430 431 static int 432 pci_freecfg(struct pci_devinfo *dinfo) 433 { 434 struct devlist *devlist_head; 435 436 devlist_head = &pci_devq; 437 438 if (dinfo->cfg.map != NULL) 439 free(dinfo->cfg.map, M_DEVBUF); 440 /* XXX this hasn't been tested */ 441 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 442 free(dinfo, M_DEVBUF); 443 444 /* increment the generation count */ 445 pci_generation++; 446 447 /* we're losing one device */ 448 pci_numdevs--; 449 return (0); 450 } 451 #endif 452 453 /* 454 * PCI power manangement 455 */ 456 static int 457 pci_set_powerstate_method(device_t dev, device_t child, int state) 458 { 459 struct pci_devinfo *dinfo = device_get_ivars(child); 460 pcicfgregs *cfg = &dinfo->cfg; 461 u_int16_t status; 462 int result; 463 464 if (cfg->pp_cap != 0) { 465 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK; 466 result = 0; 467 switch (state) { 468 case PCI_POWERSTATE_D0: 469 status |= PCIM_PSTAT_D0; 470 break; 471 case PCI_POWERSTATE_D1: 472 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) { 473 status |= PCIM_PSTAT_D1; 474 } else { 475 result = EOPNOTSUPP; 476 } 477 break; 478 case PCI_POWERSTATE_D2: 479 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) { 480 status |= PCIM_PSTAT_D2; 481 } else { 482 result = EOPNOTSUPP; 483 } 484 break; 485 case PCI_POWERSTATE_D3: 486 status |= PCIM_PSTAT_D3; 487 break; 488 default: 489 result = EINVAL; 490 } 491 if (result == 0) 492 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2); 493 } else { 494 result = ENXIO; 495 } 496 return(result); 497 } 498 499 static int 500 pci_get_powerstate_method(device_t dev, device_t child) 501 { 502 struct pci_devinfo *dinfo = device_get_ivars(child); 503 pcicfgregs *cfg = &dinfo->cfg; 504 u_int16_t status; 505 int result; 506 507 if (cfg->pp_cap != 0) { 508 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2); 509 switch (status & PCIM_PSTAT_DMASK) { 510 case PCIM_PSTAT_D0: 511 result = PCI_POWERSTATE_D0; 512 break; 513 case PCIM_PSTAT_D1: 514 result = PCI_POWERSTATE_D1; 515 break; 516 case PCIM_PSTAT_D2: 517 result = PCI_POWERSTATE_D2; 518 break; 519 case PCIM_PSTAT_D3: 520 result = PCI_POWERSTATE_D3; 521 break; 522 default: 523 result = PCI_POWERSTATE_UNKNOWN; 524 break; 525 } 526 } else { 527 /* No support, device is always at D0 */ 528 result = PCI_POWERSTATE_D0; 529 } 530 return(result); 531 } 532 533 /* 534 * Some convenience functions for PCI device drivers. 535 */ 536 537 static __inline void 538 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit) 539 { 540 u_int16_t command; 541 542 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 543 command |= bit; 544 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 545 } 546 547 static __inline void 548 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit) 549 { 550 u_int16_t command; 551 552 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 553 command &= ~bit; 554 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 555 } 556 557 static void 558 pci_enable_busmaster_method(device_t dev, device_t child) 559 { 560 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 561 } 562 563 static void 564 pci_disable_busmaster_method(device_t dev, device_t child) 565 { 566 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 567 } 568 569 static void 570 pci_enable_io_method(device_t dev, device_t child, int space) 571 { 572 switch(space) { 573 case SYS_RES_IOPORT: 574 pci_set_command_bit(dev, child, PCIM_CMD_PORTEN); 575 break; 576 case SYS_RES_MEMORY: 577 pci_set_command_bit(dev, child, PCIM_CMD_MEMEN); 578 break; 579 } 580 } 581 582 static void 583 pci_disable_io_method(device_t dev, device_t child, int space) 584 { 585 switch(space) { 586 case SYS_RES_IOPORT: 587 pci_clear_command_bit(dev, child, PCIM_CMD_PORTEN); 588 break; 589 case SYS_RES_MEMORY: 590 pci_clear_command_bit(dev, child, PCIM_CMD_MEMEN); 591 break; 592 } 593 } 594 595 /* 596 * New style pci driver. Parent device is either a pci-host-bridge or a 597 * pci-pci-bridge. Both kinds are represented by instances of pcib. 598 */ 599 600 static void 601 pci_print_verbose(struct pci_devinfo *dinfo) 602 { 603 if (bootverbose) { 604 pcicfgregs *cfg = &dinfo->cfg; 605 606 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 607 cfg->vendor, cfg->device, cfg->revid); 608 printf("\tbus=%d, slot=%d, func=%d\n", 609 cfg->bus, cfg->slot, cfg->func); 610 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 611 cfg->baseclass, cfg->subclass, cfg->progif, 612 cfg->hdrtype, cfg->mfdev); 613 #ifdef PCI_DEBUG 614 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 615 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 616 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 617 cfg->lattimer, cfg->lattimer * 30, 618 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 619 #endif /* PCI_DEBUG */ 620 if (cfg->intpin > 0) 621 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 622 if (cfg->pp_cap) { 623 u_int16_t status; 624 625 status = pci_read_config(cfg->dev, cfg->pp_status, 2); 626 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 627 cfg->pp_cap & PCIM_PCAP_SPEC, 628 cfg->pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 629 cfg->pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 630 status & PCIM_PSTAT_DMASK); 631 } 632 } 633 } 634 635 static int 636 pci_porten(device_t pcib, int b, int s, int f) 637 { 638 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 639 & PCIM_CMD_PORTEN) != 0; 640 } 641 642 static int 643 pci_memen(device_t pcib, int b, int s, int f) 644 { 645 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 646 & PCIM_CMD_MEMEN) != 0; 647 } 648 649 /* 650 * Add a resource based on a pci map register. Return 1 if the map 651 * register is a 32bit map register or 2 if it is a 64bit register. 652 */ 653 static int 654 pci_add_map(device_t pcib, int b, int s, int f, int reg, 655 struct resource_list *rl) 656 { 657 u_int32_t map; 658 u_int64_t base; 659 u_int8_t ln2size; 660 u_int8_t ln2range; 661 u_int32_t testval; 662 #ifdef PCI_ENABLE_IO_MODES 663 u_int16_t cmd; 664 #endif 665 int type; 666 667 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 668 669 if (map == 0 || map == 0xffffffff) 670 return 1; /* skip invalid entry */ 671 672 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 673 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 674 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 675 676 base = pci_mapbase(map); 677 if (pci_maptype(map) & PCI_MAPMEM) 678 type = SYS_RES_MEMORY; 679 else 680 type = SYS_RES_IOPORT; 681 ln2size = pci_mapsize(testval); 682 ln2range = pci_maprange(testval); 683 if (ln2range == 64) { 684 /* Read the other half of a 64bit map register */ 685 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 686 } 687 688 if (bootverbose) { 689 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 690 reg, pci_maptype(map), ln2range, 691 (unsigned int) base, ln2size); 692 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 693 printf(", port disabled\n"); 694 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 695 printf(", memory disabled\n"); 696 else 697 printf(", enabled\n"); 698 } 699 700 /* 701 * This code theoretically does the right thing, but has 702 * undesirable side effects in some cases where 703 * peripherals respond oddly to having these bits 704 * enabled. Leave them alone by default. 705 */ 706 #ifdef PCI_ENABLE_IO_MODES 707 /* Turn on resources that have been left off by a lazy BIOS */ 708 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 709 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 710 cmd |= PCIM_CMD_PORTEN; 711 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 712 } 713 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 714 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 715 cmd |= PCIM_CMD_MEMEN; 716 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 717 } 718 #else 719 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 720 return 1; 721 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 722 return 1; 723 #endif 724 725 resource_list_add(rl, type, reg, 726 base, base + (1 << ln2size) - 1, 727 (1 << ln2size)); 728 729 return (ln2range == 64) ? 2 : 1; 730 } 731 732 static void 733 pci_add_resources(device_t pcib, int b, int s, int f, device_t dev) 734 { 735 struct pci_devinfo *dinfo = device_get_ivars(dev); 736 pcicfgregs *cfg = &dinfo->cfg; 737 struct resource_list *rl = &dinfo->resources; 738 struct pci_quirk *q; 739 int i; 740 741 for (i = 0; i < cfg->nummaps;) { 742 i += pci_add_map(pcib, b, s, f, PCIR_MAPS + i*4, rl); 743 } 744 745 for (q = &pci_quirks[0]; q->devid; q++) { 746 if (q->devid == ((cfg->device << 16) | cfg->vendor) 747 && q->type == PCI_QUIRK_MAP_REG) 748 pci_add_map(pcib, b, s, f, q->arg1, rl); 749 } 750 751 if (cfg->intpin > 0 && cfg->intline != 255) { 752 #ifdef __ia64__ 753 /* 754 * Re-route interrupts on ia64 so that we can get the 755 * I/O SAPIC interrupt numbers (the BIOS leaves legacy 756 * PIC interrupt numbers in the intline registers). 757 */ 758 cfg->intline = PCIB_ROUTE_INTERRUPT(pcib, 759 dev, 760 cfg->intpin); 761 #endif 762 resource_list_add(rl, SYS_RES_IRQ, 0, 763 cfg->intline, cfg->intline, 1); 764 } 765 } 766 767 static void 768 pci_add_children(device_t dev, int busno) 769 { 770 device_t pcib = device_get_parent(dev); 771 int maxslots; 772 int s, f; 773 774 maxslots = PCIB_MAXSLOTS(pcib); 775 776 for (s = 0; s <= maxslots; s++) { 777 int pcifunchigh = 0; 778 for (f = 0; f <= pcifunchigh; f++) { 779 struct pci_devinfo *dinfo = 780 pci_read_device(pcib, busno, s, f); 781 if (dinfo != NULL) { 782 if (dinfo->cfg.mfdev) 783 pcifunchigh = PCI_FUNCMAX; 784 785 dinfo->cfg.dev = device_add_child(dev, NULL, -1); 786 device_set_ivars(dinfo->cfg.dev, dinfo); 787 pci_add_resources(pcib, busno, s, f, 788 dinfo->cfg.dev); 789 pci_print_verbose(dinfo); 790 } 791 } 792 } 793 } 794 795 static int 796 pci_probe(device_t dev) 797 { 798 static int once, busno; 799 caddr_t vendordata, info; 800 801 device_set_desc(dev, "PCI bus"); 802 803 if (bootverbose) 804 device_printf(dev, "physical bus=%d\n", pcib_get_bus(dev)); 805 806 /* 807 * Since there can be multiple independantly numbered PCI 808 * busses on some large alpha systems, we can't use the unit 809 * number to decide what bus we are probing. We ask the parent 810 * pcib what our bus number is. 811 */ 812 busno = pcib_get_bus(dev); 813 if (busno < 0) 814 return ENXIO; 815 pci_add_children(dev, busno); 816 817 if (!once) { 818 make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, "pci"); 819 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 820 info = preload_search_info(vendordata, MODINFO_ADDR); 821 pci_vendordata = *(char **)info; 822 info = preload_search_info(vendordata, MODINFO_SIZE); 823 pci_vendordata_size = *(size_t *)info; 824 /* terminate the database */ 825 pci_vendordata[pci_vendordata_size] = '\n'; 826 } 827 once++; 828 } 829 830 return 0; 831 } 832 833 static int 834 pci_print_child(device_t dev, device_t child) 835 { 836 struct pci_devinfo *dinfo; 837 struct resource_list *rl; 838 pcicfgregs *cfg; 839 int retval = 0; 840 841 dinfo = device_get_ivars(child); 842 cfg = &dinfo->cfg; 843 rl = &dinfo->resources; 844 845 retval += bus_print_child_header(dev, child); 846 847 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 848 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 849 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 850 if (device_get_flags(dev)) 851 retval += printf(" flags %#x", device_get_flags(dev)); 852 853 retval += printf(" at device %d.%d", pci_get_slot(child), 854 pci_get_function(child)); 855 856 retval += bus_print_child_footer(dev, child); 857 858 return (retval); 859 } 860 861 static struct 862 { 863 int class; 864 int subclass; 865 char *desc; 866 } pci_nomatch_tab[] = { 867 {PCIC_OLD, -1, "old"}, 868 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 869 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 870 {PCIC_STORAGE, -1, "mass storage"}, 871 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 872 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 873 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 874 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 875 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 876 {PCIC_NETWORK, -1, "network"}, 877 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 878 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 879 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 880 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 881 {PCIC_DISPLAY, -1, "display"}, 882 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 883 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 884 {PCIC_MULTIMEDIA, -1, "multimedia"}, 885 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 886 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 887 {PCIC_MEMORY, -1, "memory"}, 888 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 889 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 890 {PCIC_BRIDGE, -1, "bridge"}, 891 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 892 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 893 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 894 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 895 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 896 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 897 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 898 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 899 {PCIC_BRIDGE, PCIS_BRIDGE_OTHER, "PCI-unknown"}, 900 {PCIC_SIMPLECOMM, -1, "simple comms"}, 901 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 902 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 903 {PCIC_BASEPERIPH, -1, "base peripheral"}, 904 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 905 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 906 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 907 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 908 {PCIC_INPUTDEV, -1, "input device"}, 909 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 910 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 911 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 912 {PCIC_DOCKING, -1, "docking station"}, 913 {PCIC_PROCESSOR, -1, "processor"}, 914 {PCIC_SERIALBUS, -1, "serial bus"}, 915 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 916 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 917 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 918 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 919 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 920 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 921 {0, 0, NULL} 922 }; 923 924 static void 925 pci_probe_nomatch(device_t dev, device_t child) 926 { 927 int i; 928 char *cp, *scp, *device; 929 930 /* 931 * Look for a listing for this device in a loaded device database. 932 */ 933 if ((device = pci_describe_device(child)) != NULL) { 934 device_printf(dev, "<%s>", device); 935 free(device, M_DEVBUF); 936 } else { 937 /* 938 * Scan the class/subclass descriptions for a general description. 939 */ 940 cp = "unknown"; 941 scp = NULL; 942 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 943 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 944 if (pci_nomatch_tab[i].subclass == -1) { 945 cp = pci_nomatch_tab[i].desc; 946 } else if (pci_nomatch_tab[i].subclass == pci_get_subclass(child)) { 947 scp = pci_nomatch_tab[i].desc; 948 } 949 } 950 } 951 device_printf(dev, "<%s%s%s>", 952 cp ? : "", 953 ((cp != NULL) && (scp != NULL)) ? ", " : "", 954 scp ? : ""); 955 } 956 printf(" at device %d.%d (no driver attached)\n", 957 pci_get_slot(child), 958 pci_get_function(child)); 959 return; 960 } 961 962 /* 963 * Parse the PCI device database, if loaded, and return a pointer to a 964 * description of the device. 965 * 966 * The database is flat text formatted as follows: 967 * 968 * Any line not in a valid format is ignored. 969 * Lines are terminated with newline '\n' characters. 970 * 971 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 972 * the vendor name. 973 * 974 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 975 * - devices cannot be listed without a corresponding VENDOR line. 976 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 977 * another TAB, then the device name. 978 */ 979 980 /* 981 * Assuming (ptr) points to the beginning of a line in the database, 982 * return the vendor or device and description of the next entry. 983 * The value of (vendor) or (device) inappropriate for the entry type 984 * is set to -1. Returns nonzero at the end of the database. 985 * 986 * Note that this is slightly unrobust in the face of corrupt data; 987 * we attempt to safeguard against this by spamming the end of the 988 * database with a newline when we initialise. 989 */ 990 static int 991 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 992 { 993 char *cp = *ptr; 994 int left; 995 996 *device = -1; 997 *vendor = -1; 998 **desc = '\0'; 999 for (;;) { 1000 left = pci_vendordata_size - (cp - pci_vendordata); 1001 if (left <= 0) { 1002 *ptr = cp; 1003 return(1); 1004 } 1005 1006 /* vendor entry? */ 1007 if (*cp != '\t' && sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1008 break; 1009 /* device entry? */ 1010 if (*cp == '\t' && sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1011 break; 1012 1013 /* skip to next line */ 1014 while (*cp != '\n' && left > 0) { 1015 cp++; 1016 left--; 1017 } 1018 if (*cp == '\n') { 1019 cp++; 1020 left--; 1021 } 1022 } 1023 /* skip to next line */ 1024 while (*cp != '\n' && left > 0) { 1025 cp++; 1026 left--; 1027 } 1028 if (*cp == '\n' && left > 0) 1029 cp++; 1030 *ptr = cp; 1031 return(0); 1032 } 1033 1034 static char * 1035 pci_describe_device(device_t dev) 1036 { 1037 int vendor, device; 1038 char *desc, *vp, *dp, *line; 1039 1040 desc = vp = dp = NULL; 1041 1042 /* 1043 * If we have no vendor data, we can't do anything. 1044 */ 1045 if (pci_vendordata == NULL) 1046 goto out; 1047 1048 /* 1049 * Scan the vendor data looking for this device 1050 */ 1051 line = pci_vendordata; 1052 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1053 goto out; 1054 for (;;) { 1055 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1056 goto out; 1057 if (vendor == pci_get_vendor(dev)) 1058 break; 1059 } 1060 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1061 goto out; 1062 for (;;) { 1063 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1064 *dp = 0; 1065 break; 1066 } 1067 if (vendor != -1) { 1068 *dp = 0; 1069 break; 1070 } 1071 if (device == pci_get_device(dev)) 1072 break; 1073 } 1074 if (dp[0] == '\0') 1075 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1076 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != NULL) 1077 sprintf(desc, "%s, %s", vp, dp); 1078 out: 1079 if (vp != NULL) 1080 free(vp, M_DEVBUF); 1081 if (dp != NULL) 1082 free(dp, M_DEVBUF); 1083 return(desc); 1084 } 1085 1086 static int 1087 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1088 { 1089 struct pci_devinfo *dinfo; 1090 pcicfgregs *cfg; 1091 1092 dinfo = device_get_ivars(child); 1093 cfg = &dinfo->cfg; 1094 1095 switch (which) { 1096 case PCI_IVAR_SUBVENDOR: 1097 *result = cfg->subvendor; 1098 break; 1099 case PCI_IVAR_SUBDEVICE: 1100 *result = cfg->subdevice; 1101 break; 1102 case PCI_IVAR_VENDOR: 1103 *result = cfg->vendor; 1104 break; 1105 case PCI_IVAR_DEVICE: 1106 *result = cfg->device; 1107 break; 1108 case PCI_IVAR_DEVID: 1109 *result = (cfg->device << 16) | cfg->vendor; 1110 break; 1111 case PCI_IVAR_CLASS: 1112 *result = cfg->baseclass; 1113 break; 1114 case PCI_IVAR_SUBCLASS: 1115 *result = cfg->subclass; 1116 break; 1117 case PCI_IVAR_PROGIF: 1118 *result = cfg->progif; 1119 break; 1120 case PCI_IVAR_REVID: 1121 *result = cfg->revid; 1122 break; 1123 case PCI_IVAR_INTPIN: 1124 *result = cfg->intpin; 1125 break; 1126 case PCI_IVAR_IRQ: 1127 *result = cfg->intline; 1128 break; 1129 case PCI_IVAR_BUS: 1130 *result = cfg->bus; 1131 break; 1132 case PCI_IVAR_SLOT: 1133 *result = cfg->slot; 1134 break; 1135 case PCI_IVAR_FUNCTION: 1136 *result = cfg->func; 1137 break; 1138 default: 1139 return ENOENT; 1140 } 1141 return 0; 1142 } 1143 1144 static int 1145 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1146 { 1147 struct pci_devinfo *dinfo; 1148 pcicfgregs *cfg; 1149 1150 dinfo = device_get_ivars(child); 1151 cfg = &dinfo->cfg; 1152 1153 switch (which) { 1154 case PCI_IVAR_SUBVENDOR: 1155 case PCI_IVAR_SUBDEVICE: 1156 case PCI_IVAR_VENDOR: 1157 case PCI_IVAR_DEVICE: 1158 case PCI_IVAR_DEVID: 1159 case PCI_IVAR_CLASS: 1160 case PCI_IVAR_SUBCLASS: 1161 case PCI_IVAR_PROGIF: 1162 case PCI_IVAR_REVID: 1163 case PCI_IVAR_INTPIN: 1164 case PCI_IVAR_IRQ: 1165 case PCI_IVAR_BUS: 1166 case PCI_IVAR_SLOT: 1167 case PCI_IVAR_FUNCTION: 1168 return EINVAL; /* disallow for now */ 1169 1170 default: 1171 return ENOENT; 1172 } 1173 return 0; 1174 } 1175 1176 static struct resource * 1177 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1178 u_long start, u_long end, u_long count, u_int flags) 1179 { 1180 struct pci_devinfo *dinfo = device_get_ivars(child); 1181 struct resource_list *rl = &dinfo->resources; 1182 pcicfgregs *cfg = &dinfo->cfg; 1183 1184 /* 1185 * Perform lazy resource allocation 1186 * 1187 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY 1188 */ 1189 if (device_get_parent(child) == dev) { 1190 /* 1191 * If device doesn't have an interrupt routed, and is deserving of 1192 * an interrupt, try to assign it one. 1193 */ 1194 if ((type == SYS_RES_IRQ) && (cfg->intline == 255 || cfg->intline == 0) && (cfg->intpin != 0)) { 1195 cfg->intline = PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 1196 cfg->intpin); 1197 if (cfg->intline != 255) { 1198 pci_write_config(child, PCIR_INTLINE, cfg->intline, 1); 1199 resource_list_add(rl, SYS_RES_IRQ, 0, 1200 cfg->intline, cfg->intline, 1); 1201 } 1202 } 1203 } 1204 1205 return resource_list_alloc(rl, dev, child, type, rid, 1206 start, end, count, flags); 1207 } 1208 1209 static void 1210 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1211 { 1212 printf("pci_delete_resource: PCI resources can not be deleted\n"); 1213 } 1214 1215 static struct resource_list * 1216 pci_get_resource_list (device_t dev, device_t child) 1217 { 1218 struct pci_devinfo * dinfo = device_get_ivars(child); 1219 struct resource_list * rl = &dinfo->resources; 1220 1221 if (!rl) 1222 return (NULL); 1223 1224 return (rl); 1225 } 1226 1227 static u_int32_t 1228 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1229 { 1230 struct pci_devinfo *dinfo = device_get_ivars(child); 1231 pcicfgregs *cfg = &dinfo->cfg; 1232 1233 return PCIB_READ_CONFIG(device_get_parent(dev), 1234 cfg->bus, cfg->slot, cfg->func, 1235 reg, width); 1236 } 1237 1238 static void 1239 pci_write_config_method(device_t dev, device_t child, int reg, 1240 u_int32_t val, int width) 1241 { 1242 struct pci_devinfo *dinfo = device_get_ivars(child); 1243 pcicfgregs *cfg = &dinfo->cfg; 1244 1245 PCIB_WRITE_CONFIG(device_get_parent(dev), 1246 cfg->bus, cfg->slot, cfg->func, 1247 reg, val, width); 1248 } 1249 1250 static int 1251 pci_modevent(module_t mod, int what, void *arg) 1252 { 1253 switch (what) { 1254 case MOD_LOAD: 1255 STAILQ_INIT(&pci_devq); 1256 pci_generation = 0; 1257 break; 1258 1259 case MOD_UNLOAD: 1260 break; 1261 } 1262 1263 return 0; 1264 } 1265