1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/linker.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/sysctl.h> 44 #include <sys/endian.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 #include <machine/stdarg.h> 55 56 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 57 #include <machine/intr_machdep.h> 58 #endif 59 60 #include <sys/pciio.h> 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcivar.h> 63 #include <dev/pci/pci_private.h> 64 65 #include <dev/usb/controller/xhcireg.h> 66 #include <dev/usb/controller/ehcireg.h> 67 #include <dev/usb/controller/ohcireg.h> 68 #include <dev/usb/controller/uhcireg.h> 69 70 #include "pcib_if.h" 71 #include "pci_if.h" 72 73 #define PCIR_IS_BIOS(cfg, reg) \ 74 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ 75 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) 76 77 static int pci_has_quirk(uint32_t devid, int quirk); 78 static pci_addr_t pci_mapbase(uint64_t mapreg); 79 static const char *pci_maptype(uint64_t mapreg); 80 static int pci_mapsize(uint64_t testval); 81 static int pci_maprange(uint64_t mapreg); 82 static pci_addr_t pci_rombase(uint64_t mapreg); 83 static int pci_romsize(uint64_t testval); 84 static void pci_fixancient(pcicfgregs *cfg); 85 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...); 86 87 static int pci_porten(device_t dev); 88 static int pci_memen(device_t dev); 89 static void pci_assign_interrupt(device_t bus, device_t dev, 90 int force_route); 91 static int pci_add_map(device_t bus, device_t dev, int reg, 92 struct resource_list *rl, int force, int prefetch); 93 static int pci_probe(device_t dev); 94 static int pci_attach(device_t dev); 95 #ifdef PCI_RES_BUS 96 static int pci_detach(device_t dev); 97 #endif 98 static void pci_load_vendor_data(void); 99 static int pci_describe_parse_line(char **ptr, int *vendor, 100 int *device, char **desc); 101 static char *pci_describe_device(device_t dev); 102 static int pci_modevent(module_t mod, int what, void *arg); 103 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 104 pcicfgregs *cfg); 105 static void pci_read_cap(device_t pcib, pcicfgregs *cfg); 106 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 107 int reg, uint32_t *data); 108 #if 0 109 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 110 int reg, uint32_t data); 111 #endif 112 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 113 static void pci_disable_msi(device_t dev); 114 static void pci_enable_msi(device_t dev, uint64_t address, 115 uint16_t data); 116 static void pci_enable_msix(device_t dev, u_int index, 117 uint64_t address, uint32_t data); 118 static void pci_mask_msix(device_t dev, u_int index); 119 static void pci_unmask_msix(device_t dev, u_int index); 120 static int pci_msi_blacklisted(void); 121 static int pci_msix_blacklisted(void); 122 static void pci_resume_msi(device_t dev); 123 static void pci_resume_msix(device_t dev); 124 static int pci_remap_intr_method(device_t bus, device_t dev, 125 u_int irq); 126 127 static uint16_t pci_get_rid_method(device_t dev, device_t child); 128 129 static device_method_t pci_methods[] = { 130 /* Device interface */ 131 DEVMETHOD(device_probe, pci_probe), 132 DEVMETHOD(device_attach, pci_attach), 133 #ifdef PCI_RES_BUS 134 DEVMETHOD(device_detach, pci_detach), 135 #else 136 DEVMETHOD(device_detach, bus_generic_detach), 137 #endif 138 DEVMETHOD(device_shutdown, bus_generic_shutdown), 139 DEVMETHOD(device_suspend, pci_suspend), 140 DEVMETHOD(device_resume, pci_resume), 141 142 /* Bus interface */ 143 DEVMETHOD(bus_print_child, pci_print_child), 144 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 145 DEVMETHOD(bus_read_ivar, pci_read_ivar), 146 DEVMETHOD(bus_write_ivar, pci_write_ivar), 147 DEVMETHOD(bus_driver_added, pci_driver_added), 148 DEVMETHOD(bus_setup_intr, pci_setup_intr), 149 DEVMETHOD(bus_teardown_intr, pci_teardown_intr), 150 151 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag), 152 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 153 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 154 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 155 DEVMETHOD(bus_delete_resource, pci_delete_resource), 156 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 157 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 158 DEVMETHOD(bus_release_resource, pci_release_resource), 159 DEVMETHOD(bus_activate_resource, pci_activate_resource), 160 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource), 161 DEVMETHOD(bus_child_detached, pci_child_detached), 162 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 163 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 164 DEVMETHOD(bus_remap_intr, pci_remap_intr_method), 165 166 /* PCI interface */ 167 DEVMETHOD(pci_read_config, pci_read_config_method), 168 DEVMETHOD(pci_write_config, pci_write_config_method), 169 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 170 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 171 DEVMETHOD(pci_enable_io, pci_enable_io_method), 172 DEVMETHOD(pci_disable_io, pci_disable_io_method), 173 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 174 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 175 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 176 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 177 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 178 DEVMETHOD(pci_find_cap, pci_find_cap_method), 179 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 180 DEVMETHOD(pci_find_htcap, pci_find_htcap_method), 181 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 182 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), 183 DEVMETHOD(pci_remap_msix, pci_remap_msix_method), 184 DEVMETHOD(pci_release_msi, pci_release_msi_method), 185 DEVMETHOD(pci_msi_count, pci_msi_count_method), 186 DEVMETHOD(pci_msix_count, pci_msix_count_method), 187 DEVMETHOD(pci_get_rid, pci_get_rid_method), 188 189 DEVMETHOD_END 190 }; 191 192 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc)); 193 194 static devclass_t pci_devclass; 195 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL); 196 MODULE_VERSION(pci, 1); 197 198 static char *pci_vendordata; 199 static size_t pci_vendordata_size; 200 201 struct pci_quirk { 202 uint32_t devid; /* Vendor/device of the card */ 203 int type; 204 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 205 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */ 206 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */ 207 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */ 208 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */ 209 int arg1; 210 int arg2; 211 }; 212 213 static const struct pci_quirk pci_quirks[] = { 214 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */ 215 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 216 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 217 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 218 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 219 220 /* 221 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge 222 * or the CMIC-SL (AKA ServerWorks GC_LE). 223 */ 224 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 225 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 226 227 /* 228 * MSI doesn't work on earlier Intel chipsets including 229 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855. 230 */ 231 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 232 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 233 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 234 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 235 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 236 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 237 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 238 239 /* 240 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX 241 * bridge. 242 */ 243 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 244 245 /* 246 * MSI-X allocation doesn't work properly for devices passed through 247 * by VMware up to at least ESXi 5.1. 248 */ 249 { 0x079015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCI/PCI-X */ 250 { 0x07a015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCIe */ 251 252 /* 253 * Some virtualization environments emulate an older chipset 254 * but support MSI just fine. QEMU uses the Intel 82440. 255 */ 256 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 }, 257 258 /* 259 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus 260 * controller depending on SoftPciRst register (PM_IO 0x55 [7]). 261 * It prevents us from attaching hpet(4) when the bit is unset. 262 * Note this quirk only affects SB600 revision A13 and earlier. 263 * For SB600 A21 and later, firmware must set the bit to hide it. 264 * For SB700 and later, it is unused and hardcoded to zero. 265 */ 266 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 }, 267 268 { 0 } 269 }; 270 271 /* map register information */ 272 #define PCI_MAPMEM 0x01 /* memory map */ 273 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 274 #define PCI_MAPPORT 0x04 /* port map */ 275 276 struct devlist pci_devq; 277 uint32_t pci_generation; 278 uint32_t pci_numdevs = 0; 279 static int pcie_chipset, pcix_chipset; 280 281 /* sysctl vars */ 282 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 283 284 static int pci_enable_io_modes = 1; 285 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 286 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 287 &pci_enable_io_modes, 1, 288 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 289 enable these bits correctly. We'd like to do this all the time, but there\n\ 290 are some peripherals that this causes problems with."); 291 292 static int pci_do_realloc_bars = 0; 293 TUNABLE_INT("hw.pci.realloc_bars", &pci_do_realloc_bars); 294 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RW, 295 &pci_do_realloc_bars, 0, 296 "Attempt to allocate a new range for any BARs whose original firmware-assigned ranges fail to allocate during the initial device scan."); 297 298 static int pci_do_power_nodriver = 0; 299 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver); 300 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW, 301 &pci_do_power_nodriver, 0, 302 "Place a function into D3 state when no driver attaches to it. 0 means\n\ 303 disable. 1 means conservatively place devices into D3 state. 2 means\n\ 304 agressively place devices into D3 state. 3 means put absolutely everything\n\ 305 in D3 state."); 306 307 int pci_do_power_resume = 1; 308 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume); 309 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW, 310 &pci_do_power_resume, 1, 311 "Transition from D3 -> D0 on resume."); 312 313 int pci_do_power_suspend = 1; 314 TUNABLE_INT("hw.pci.do_power_suspend", &pci_do_power_suspend); 315 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RW, 316 &pci_do_power_suspend, 1, 317 "Transition from D0 -> D3 on suspend."); 318 319 static int pci_do_msi = 1; 320 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi); 321 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1, 322 "Enable support for MSI interrupts"); 323 324 static int pci_do_msix = 1; 325 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix); 326 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1, 327 "Enable support for MSI-X interrupts"); 328 329 static int pci_honor_msi_blacklist = 1; 330 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist); 331 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD, 332 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X"); 333 334 #if defined(__i386__) || defined(__amd64__) 335 static int pci_usb_takeover = 1; 336 #else 337 static int pci_usb_takeover = 0; 338 #endif 339 TUNABLE_INT("hw.pci.usb_early_takeover", &pci_usb_takeover); 340 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN, 341 &pci_usb_takeover, 1, "Enable early takeover of USB controllers.\n\ 342 Disable this if you depend on BIOS emulation of USB devices, that is\n\ 343 you use USB devices (like keyboard or mouse) but do not load USB drivers"); 344 345 static int pci_clear_bars; 346 TUNABLE_INT("hw.pci.clear_bars", &pci_clear_bars); 347 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0, 348 "Ignore firmware-assigned resources for BARs."); 349 350 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 351 static int pci_clear_buses; 352 TUNABLE_INT("hw.pci.clear_buses", &pci_clear_buses); 353 SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0, 354 "Ignore firmware-assigned bus numbers."); 355 #endif 356 357 static int pci_enable_ari = 1; 358 TUNABLE_INT("hw.pci.enable_ari", &pci_enable_ari); 359 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari, 360 0, "Enable support for PCIe Alternative RID Interpretation"); 361 362 static int 363 pci_has_quirk(uint32_t devid, int quirk) 364 { 365 const struct pci_quirk *q; 366 367 for (q = &pci_quirks[0]; q->devid; q++) { 368 if (q->devid == devid && q->type == quirk) 369 return (1); 370 } 371 return (0); 372 } 373 374 /* Find a device_t by bus/slot/function in domain 0 */ 375 376 device_t 377 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 378 { 379 380 return (pci_find_dbsf(0, bus, slot, func)); 381 } 382 383 /* Find a device_t by domain/bus/slot/function */ 384 385 device_t 386 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func) 387 { 388 struct pci_devinfo *dinfo; 389 390 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 391 if ((dinfo->cfg.domain == domain) && 392 (dinfo->cfg.bus == bus) && 393 (dinfo->cfg.slot == slot) && 394 (dinfo->cfg.func == func)) { 395 return (dinfo->cfg.dev); 396 } 397 } 398 399 return (NULL); 400 } 401 402 /* Find a device_t by vendor/device ID */ 403 404 device_t 405 pci_find_device(uint16_t vendor, uint16_t device) 406 { 407 struct pci_devinfo *dinfo; 408 409 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 410 if ((dinfo->cfg.vendor == vendor) && 411 (dinfo->cfg.device == device)) { 412 return (dinfo->cfg.dev); 413 } 414 } 415 416 return (NULL); 417 } 418 419 device_t 420 pci_find_class(uint8_t class, uint8_t subclass) 421 { 422 struct pci_devinfo *dinfo; 423 424 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 425 if (dinfo->cfg.baseclass == class && 426 dinfo->cfg.subclass == subclass) { 427 return (dinfo->cfg.dev); 428 } 429 } 430 431 return (NULL); 432 } 433 434 static int 435 pci_printf(pcicfgregs *cfg, const char *fmt, ...) 436 { 437 va_list ap; 438 int retval; 439 440 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, 441 cfg->func); 442 va_start(ap, fmt); 443 retval += vprintf(fmt, ap); 444 va_end(ap); 445 return (retval); 446 } 447 448 /* return base address of memory or port map */ 449 450 static pci_addr_t 451 pci_mapbase(uint64_t mapreg) 452 { 453 454 if (PCI_BAR_MEM(mapreg)) 455 return (mapreg & PCIM_BAR_MEM_BASE); 456 else 457 return (mapreg & PCIM_BAR_IO_BASE); 458 } 459 460 /* return map type of memory or port map */ 461 462 static const char * 463 pci_maptype(uint64_t mapreg) 464 { 465 466 if (PCI_BAR_IO(mapreg)) 467 return ("I/O Port"); 468 if (mapreg & PCIM_BAR_MEM_PREFETCH) 469 return ("Prefetchable Memory"); 470 return ("Memory"); 471 } 472 473 /* return log2 of map size decoded for memory or port map */ 474 475 static int 476 pci_mapsize(uint64_t testval) 477 { 478 int ln2size; 479 480 testval = pci_mapbase(testval); 481 ln2size = 0; 482 if (testval != 0) { 483 while ((testval & 1) == 0) 484 { 485 ln2size++; 486 testval >>= 1; 487 } 488 } 489 return (ln2size); 490 } 491 492 /* return base address of device ROM */ 493 494 static pci_addr_t 495 pci_rombase(uint64_t mapreg) 496 { 497 498 return (mapreg & PCIM_BIOS_ADDR_MASK); 499 } 500 501 /* return log2 of map size decided for device ROM */ 502 503 static int 504 pci_romsize(uint64_t testval) 505 { 506 int ln2size; 507 508 testval = pci_rombase(testval); 509 ln2size = 0; 510 if (testval != 0) { 511 while ((testval & 1) == 0) 512 { 513 ln2size++; 514 testval >>= 1; 515 } 516 } 517 return (ln2size); 518 } 519 520 /* return log2 of address range supported by map register */ 521 522 static int 523 pci_maprange(uint64_t mapreg) 524 { 525 int ln2range = 0; 526 527 if (PCI_BAR_IO(mapreg)) 528 ln2range = 32; 529 else 530 switch (mapreg & PCIM_BAR_MEM_TYPE) { 531 case PCIM_BAR_MEM_32: 532 ln2range = 32; 533 break; 534 case PCIM_BAR_MEM_1MB: 535 ln2range = 20; 536 break; 537 case PCIM_BAR_MEM_64: 538 ln2range = 64; 539 break; 540 } 541 return (ln2range); 542 } 543 544 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 545 546 static void 547 pci_fixancient(pcicfgregs *cfg) 548 { 549 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 550 return; 551 552 /* PCI to PCI bridges use header type 1 */ 553 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 554 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; 555 } 556 557 /* extract header type specific config data */ 558 559 static void 560 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 561 { 562 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 563 switch (cfg->hdrtype & PCIM_HDRTYPE) { 564 case PCIM_HDRTYPE_NORMAL: 565 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 566 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 567 cfg->nummaps = PCI_MAXMAPS_0; 568 break; 569 case PCIM_HDRTYPE_BRIDGE: 570 cfg->nummaps = PCI_MAXMAPS_1; 571 break; 572 case PCIM_HDRTYPE_CARDBUS: 573 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 574 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 575 cfg->nummaps = PCI_MAXMAPS_2; 576 break; 577 } 578 #undef REG 579 } 580 581 /* read configuration header into pcicfgregs structure */ 582 struct pci_devinfo * 583 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size) 584 { 585 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 586 pcicfgregs *cfg = NULL; 587 struct pci_devinfo *devlist_entry; 588 struct devlist *devlist_head; 589 590 devlist_head = &pci_devq; 591 592 devlist_entry = NULL; 593 594 if (REG(PCIR_DEVVENDOR, 4) != 0xfffffffful) { 595 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 596 if (devlist_entry == NULL) 597 return (NULL); 598 599 cfg = &devlist_entry->cfg; 600 601 cfg->domain = d; 602 cfg->bus = b; 603 cfg->slot = s; 604 cfg->func = f; 605 cfg->vendor = REG(PCIR_VENDOR, 2); 606 cfg->device = REG(PCIR_DEVICE, 2); 607 cfg->cmdreg = REG(PCIR_COMMAND, 2); 608 cfg->statreg = REG(PCIR_STATUS, 2); 609 cfg->baseclass = REG(PCIR_CLASS, 1); 610 cfg->subclass = REG(PCIR_SUBCLASS, 1); 611 cfg->progif = REG(PCIR_PROGIF, 1); 612 cfg->revid = REG(PCIR_REVID, 1); 613 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 614 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 615 cfg->lattimer = REG(PCIR_LATTIMER, 1); 616 cfg->intpin = REG(PCIR_INTPIN, 1); 617 cfg->intline = REG(PCIR_INTLINE, 1); 618 619 cfg->mingnt = REG(PCIR_MINGNT, 1); 620 cfg->maxlat = REG(PCIR_MAXLAT, 1); 621 622 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 623 cfg->hdrtype &= ~PCIM_MFDEV; 624 STAILQ_INIT(&cfg->maps); 625 626 pci_fixancient(cfg); 627 pci_hdrtypedata(pcib, b, s, f, cfg); 628 629 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 630 pci_read_cap(pcib, cfg); 631 632 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 633 634 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; 635 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 636 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 637 devlist_entry->conf.pc_sel.pc_func = cfg->func; 638 devlist_entry->conf.pc_hdr = cfg->hdrtype; 639 640 devlist_entry->conf.pc_subvendor = cfg->subvendor; 641 devlist_entry->conf.pc_subdevice = cfg->subdevice; 642 devlist_entry->conf.pc_vendor = cfg->vendor; 643 devlist_entry->conf.pc_device = cfg->device; 644 645 devlist_entry->conf.pc_class = cfg->baseclass; 646 devlist_entry->conf.pc_subclass = cfg->subclass; 647 devlist_entry->conf.pc_progif = cfg->progif; 648 devlist_entry->conf.pc_revid = cfg->revid; 649 650 pci_numdevs++; 651 pci_generation++; 652 } 653 return (devlist_entry); 654 #undef REG 655 } 656 657 static void 658 pci_read_cap(device_t pcib, pcicfgregs *cfg) 659 { 660 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 661 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 662 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 663 uint64_t addr; 664 #endif 665 uint32_t val; 666 int ptr, nextptr, ptrptr; 667 668 switch (cfg->hdrtype & PCIM_HDRTYPE) { 669 case PCIM_HDRTYPE_NORMAL: 670 case PCIM_HDRTYPE_BRIDGE: 671 ptrptr = PCIR_CAP_PTR; 672 break; 673 case PCIM_HDRTYPE_CARDBUS: 674 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 675 break; 676 default: 677 return; /* no extended capabilities support */ 678 } 679 nextptr = REG(ptrptr, 1); /* sanity check? */ 680 681 /* 682 * Read capability entries. 683 */ 684 while (nextptr != 0) { 685 /* Sanity check */ 686 if (nextptr > 255) { 687 printf("illegal PCI extended capability offset %d\n", 688 nextptr); 689 return; 690 } 691 /* Find the next entry */ 692 ptr = nextptr; 693 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 694 695 /* Process this entry */ 696 switch (REG(ptr + PCICAP_ID, 1)) { 697 case PCIY_PMG: /* PCI power management */ 698 if (cfg->pp.pp_cap == 0) { 699 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 700 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 701 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE; 702 if ((nextptr - ptr) > PCIR_POWER_DATA) 703 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 704 } 705 break; 706 case PCIY_HT: /* HyperTransport */ 707 /* Determine HT-specific capability type. */ 708 val = REG(ptr + PCIR_HT_COMMAND, 2); 709 710 if ((val & 0xe000) == PCIM_HTCAP_SLAVE) 711 cfg->ht.ht_slave = ptr; 712 713 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 714 switch (val & PCIM_HTCMD_CAP_MASK) { 715 case PCIM_HTCAP_MSI_MAPPING: 716 if (!(val & PCIM_HTCMD_MSI_FIXED)) { 717 /* Sanity check the mapping window. */ 718 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 719 4); 720 addr <<= 32; 721 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 722 4); 723 if (addr != MSI_INTEL_ADDR_BASE) 724 device_printf(pcib, 725 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", 726 cfg->domain, cfg->bus, 727 cfg->slot, cfg->func, 728 (long long)addr); 729 } else 730 addr = MSI_INTEL_ADDR_BASE; 731 732 cfg->ht.ht_msimap = ptr; 733 cfg->ht.ht_msictrl = val; 734 cfg->ht.ht_msiaddr = addr; 735 break; 736 } 737 #endif 738 break; 739 case PCIY_MSI: /* PCI MSI */ 740 cfg->msi.msi_location = ptr; 741 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 742 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 743 PCIM_MSICTRL_MMC_MASK)>>1); 744 break; 745 case PCIY_MSIX: /* PCI MSI-X */ 746 cfg->msix.msix_location = ptr; 747 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 748 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl & 749 PCIM_MSIXCTRL_TABLE_SIZE) + 1; 750 val = REG(ptr + PCIR_MSIX_TABLE, 4); 751 cfg->msix.msix_table_bar = PCIR_BAR(val & 752 PCIM_MSIX_BIR_MASK); 753 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 754 val = REG(ptr + PCIR_MSIX_PBA, 4); 755 cfg->msix.msix_pba_bar = PCIR_BAR(val & 756 PCIM_MSIX_BIR_MASK); 757 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 758 break; 759 case PCIY_VPD: /* PCI Vital Product Data */ 760 cfg->vpd.vpd_reg = ptr; 761 break; 762 case PCIY_SUBVENDOR: 763 /* Should always be true. */ 764 if ((cfg->hdrtype & PCIM_HDRTYPE) == 765 PCIM_HDRTYPE_BRIDGE) { 766 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4); 767 cfg->subvendor = val & 0xffff; 768 cfg->subdevice = val >> 16; 769 } 770 break; 771 case PCIY_PCIX: /* PCI-X */ 772 /* 773 * Assume we have a PCI-X chipset if we have 774 * at least one PCI-PCI bridge with a PCI-X 775 * capability. Note that some systems with 776 * PCI-express or HT chipsets might match on 777 * this check as well. 778 */ 779 if ((cfg->hdrtype & PCIM_HDRTYPE) == 780 PCIM_HDRTYPE_BRIDGE) 781 pcix_chipset = 1; 782 cfg->pcix.pcix_location = ptr; 783 break; 784 case PCIY_EXPRESS: /* PCI-express */ 785 /* 786 * Assume we have a PCI-express chipset if we have 787 * at least one PCI-express device. 788 */ 789 pcie_chipset = 1; 790 cfg->pcie.pcie_location = ptr; 791 val = REG(ptr + PCIER_FLAGS, 2); 792 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; 793 break; 794 default: 795 break; 796 } 797 } 798 799 #if defined(__powerpc__) 800 /* 801 * Enable the MSI mapping window for all HyperTransport 802 * slaves. PCI-PCI bridges have their windows enabled via 803 * PCIB_MAP_MSI(). 804 */ 805 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && 806 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { 807 device_printf(pcib, 808 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n", 809 cfg->domain, cfg->bus, cfg->slot, cfg->func); 810 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 811 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, 812 2); 813 } 814 #endif 815 /* REG and WREG use carry through to next functions */ 816 } 817 818 /* 819 * PCI Vital Product Data 820 */ 821 822 #define PCI_VPD_TIMEOUT 1000000 823 824 static int 825 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data) 826 { 827 int count = PCI_VPD_TIMEOUT; 828 829 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 830 831 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); 832 833 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { 834 if (--count < 0) 835 return (ENXIO); 836 DELAY(1); /* limit looping */ 837 } 838 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); 839 840 return (0); 841 } 842 843 #if 0 844 static int 845 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 846 { 847 int count = PCI_VPD_TIMEOUT; 848 849 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 850 851 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4); 852 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2); 853 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) { 854 if (--count < 0) 855 return (ENXIO); 856 DELAY(1); /* limit looping */ 857 } 858 859 return (0); 860 } 861 #endif 862 863 #undef PCI_VPD_TIMEOUT 864 865 struct vpd_readstate { 866 device_t pcib; 867 pcicfgregs *cfg; 868 uint32_t val; 869 int bytesinval; 870 int off; 871 uint8_t cksum; 872 }; 873 874 static int 875 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data) 876 { 877 uint32_t reg; 878 uint8_t byte; 879 880 if (vrs->bytesinval == 0) { 881 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) 882 return (ENXIO); 883 vrs->val = le32toh(reg); 884 vrs->off += 4; 885 byte = vrs->val & 0xff; 886 vrs->bytesinval = 3; 887 } else { 888 vrs->val = vrs->val >> 8; 889 byte = vrs->val & 0xff; 890 vrs->bytesinval--; 891 } 892 893 vrs->cksum += byte; 894 *data = byte; 895 return (0); 896 } 897 898 static void 899 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 900 { 901 struct vpd_readstate vrs; 902 int state; 903 int name; 904 int remain; 905 int i; 906 int alloc, off; /* alloc/off for RO/W arrays */ 907 int cksumvalid; 908 int dflen; 909 uint8_t byte; 910 uint8_t byte2; 911 912 /* init vpd reader */ 913 vrs.bytesinval = 0; 914 vrs.off = 0; 915 vrs.pcib = pcib; 916 vrs.cfg = cfg; 917 vrs.cksum = 0; 918 919 state = 0; 920 name = remain = i = 0; /* shut up stupid gcc */ 921 alloc = off = 0; /* shut up stupid gcc */ 922 dflen = 0; /* shut up stupid gcc */ 923 cksumvalid = -1; 924 while (state >= 0) { 925 if (vpd_nextbyte(&vrs, &byte)) { 926 state = -2; 927 break; 928 } 929 #if 0 930 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \ 931 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val, 932 vrs.off, vrs.bytesinval, byte, state, remain, name, i); 933 #endif 934 switch (state) { 935 case 0: /* item name */ 936 if (byte & 0x80) { 937 if (vpd_nextbyte(&vrs, &byte2)) { 938 state = -2; 939 break; 940 } 941 remain = byte2; 942 if (vpd_nextbyte(&vrs, &byte2)) { 943 state = -2; 944 break; 945 } 946 remain |= byte2 << 8; 947 if (remain > (0x7f*4 - vrs.off)) { 948 state = -1; 949 pci_printf(cfg, 950 "invalid VPD data, remain %#x\n", 951 remain); 952 } 953 name = byte & 0x7f; 954 } else { 955 remain = byte & 0x7; 956 name = (byte >> 3) & 0xf; 957 } 958 switch (name) { 959 case 0x2: /* String */ 960 cfg->vpd.vpd_ident = malloc(remain + 1, 961 M_DEVBUF, M_WAITOK); 962 i = 0; 963 state = 1; 964 break; 965 case 0xf: /* End */ 966 state = -1; 967 break; 968 case 0x10: /* VPD-R */ 969 alloc = 8; 970 off = 0; 971 cfg->vpd.vpd_ros = malloc(alloc * 972 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF, 973 M_WAITOK | M_ZERO); 974 state = 2; 975 break; 976 case 0x11: /* VPD-W */ 977 alloc = 8; 978 off = 0; 979 cfg->vpd.vpd_w = malloc(alloc * 980 sizeof(*cfg->vpd.vpd_w), M_DEVBUF, 981 M_WAITOK | M_ZERO); 982 state = 5; 983 break; 984 default: /* Invalid data, abort */ 985 state = -1; 986 break; 987 } 988 break; 989 990 case 1: /* Identifier String */ 991 cfg->vpd.vpd_ident[i++] = byte; 992 remain--; 993 if (remain == 0) { 994 cfg->vpd.vpd_ident[i] = '\0'; 995 state = 0; 996 } 997 break; 998 999 case 2: /* VPD-R Keyword Header */ 1000 if (off == alloc) { 1001 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1002 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros), 1003 M_DEVBUF, M_WAITOK | M_ZERO); 1004 } 1005 cfg->vpd.vpd_ros[off].keyword[0] = byte; 1006 if (vpd_nextbyte(&vrs, &byte2)) { 1007 state = -2; 1008 break; 1009 } 1010 cfg->vpd.vpd_ros[off].keyword[1] = byte2; 1011 if (vpd_nextbyte(&vrs, &byte2)) { 1012 state = -2; 1013 break; 1014 } 1015 cfg->vpd.vpd_ros[off].len = dflen = byte2; 1016 if (dflen == 0 && 1017 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV", 1018 2) == 0) { 1019 /* 1020 * if this happens, we can't trust the rest 1021 * of the VPD. 1022 */ 1023 pci_printf(cfg, "bad keyword length: %d\n", 1024 dflen); 1025 cksumvalid = 0; 1026 state = -1; 1027 break; 1028 } else if (dflen == 0) { 1029 cfg->vpd.vpd_ros[off].value = malloc(1 * 1030 sizeof(*cfg->vpd.vpd_ros[off].value), 1031 M_DEVBUF, M_WAITOK); 1032 cfg->vpd.vpd_ros[off].value[0] = '\x00'; 1033 } else 1034 cfg->vpd.vpd_ros[off].value = malloc( 1035 (dflen + 1) * 1036 sizeof(*cfg->vpd.vpd_ros[off].value), 1037 M_DEVBUF, M_WAITOK); 1038 remain -= 3; 1039 i = 0; 1040 /* keep in sync w/ state 3's transistions */ 1041 if (dflen == 0 && remain == 0) 1042 state = 0; 1043 else if (dflen == 0) 1044 state = 2; 1045 else 1046 state = 3; 1047 break; 1048 1049 case 3: /* VPD-R Keyword Value */ 1050 cfg->vpd.vpd_ros[off].value[i++] = byte; 1051 if (strncmp(cfg->vpd.vpd_ros[off].keyword, 1052 "RV", 2) == 0 && cksumvalid == -1) { 1053 if (vrs.cksum == 0) 1054 cksumvalid = 1; 1055 else { 1056 if (bootverbose) 1057 pci_printf(cfg, 1058 "bad VPD cksum, remain %hhu\n", 1059 vrs.cksum); 1060 cksumvalid = 0; 1061 state = -1; 1062 break; 1063 } 1064 } 1065 dflen--; 1066 remain--; 1067 /* keep in sync w/ state 2's transistions */ 1068 if (dflen == 0) 1069 cfg->vpd.vpd_ros[off++].value[i++] = '\0'; 1070 if (dflen == 0 && remain == 0) { 1071 cfg->vpd.vpd_rocnt = off; 1072 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 1073 off * sizeof(*cfg->vpd.vpd_ros), 1074 M_DEVBUF, M_WAITOK | M_ZERO); 1075 state = 0; 1076 } else if (dflen == 0) 1077 state = 2; 1078 break; 1079 1080 case 4: 1081 remain--; 1082 if (remain == 0) 1083 state = 0; 1084 break; 1085 1086 case 5: /* VPD-W Keyword Header */ 1087 if (off == alloc) { 1088 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1089 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w), 1090 M_DEVBUF, M_WAITOK | M_ZERO); 1091 } 1092 cfg->vpd.vpd_w[off].keyword[0] = byte; 1093 if (vpd_nextbyte(&vrs, &byte2)) { 1094 state = -2; 1095 break; 1096 } 1097 cfg->vpd.vpd_w[off].keyword[1] = byte2; 1098 if (vpd_nextbyte(&vrs, &byte2)) { 1099 state = -2; 1100 break; 1101 } 1102 cfg->vpd.vpd_w[off].len = dflen = byte2; 1103 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval; 1104 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) * 1105 sizeof(*cfg->vpd.vpd_w[off].value), 1106 M_DEVBUF, M_WAITOK); 1107 remain -= 3; 1108 i = 0; 1109 /* keep in sync w/ state 6's transistions */ 1110 if (dflen == 0 && remain == 0) 1111 state = 0; 1112 else if (dflen == 0) 1113 state = 5; 1114 else 1115 state = 6; 1116 break; 1117 1118 case 6: /* VPD-W Keyword Value */ 1119 cfg->vpd.vpd_w[off].value[i++] = byte; 1120 dflen--; 1121 remain--; 1122 /* keep in sync w/ state 5's transistions */ 1123 if (dflen == 0) 1124 cfg->vpd.vpd_w[off++].value[i++] = '\0'; 1125 if (dflen == 0 && remain == 0) { 1126 cfg->vpd.vpd_wcnt = off; 1127 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 1128 off * sizeof(*cfg->vpd.vpd_w), 1129 M_DEVBUF, M_WAITOK | M_ZERO); 1130 state = 0; 1131 } else if (dflen == 0) 1132 state = 5; 1133 break; 1134 1135 default: 1136 pci_printf(cfg, "invalid state: %d\n", state); 1137 state = -1; 1138 break; 1139 } 1140 } 1141 1142 if (cksumvalid == 0 || state < -1) { 1143 /* read-only data bad, clean up */ 1144 if (cfg->vpd.vpd_ros != NULL) { 1145 for (off = 0; cfg->vpd.vpd_ros[off].value; off++) 1146 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF); 1147 free(cfg->vpd.vpd_ros, M_DEVBUF); 1148 cfg->vpd.vpd_ros = NULL; 1149 } 1150 } 1151 if (state < -1) { 1152 /* I/O error, clean up */ 1153 pci_printf(cfg, "failed to read VPD data.\n"); 1154 if (cfg->vpd.vpd_ident != NULL) { 1155 free(cfg->vpd.vpd_ident, M_DEVBUF); 1156 cfg->vpd.vpd_ident = NULL; 1157 } 1158 if (cfg->vpd.vpd_w != NULL) { 1159 for (off = 0; cfg->vpd.vpd_w[off].value; off++) 1160 free(cfg->vpd.vpd_w[off].value, M_DEVBUF); 1161 free(cfg->vpd.vpd_w, M_DEVBUF); 1162 cfg->vpd.vpd_w = NULL; 1163 } 1164 } 1165 cfg->vpd.vpd_cached = 1; 1166 #undef REG 1167 #undef WREG 1168 } 1169 1170 int 1171 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 1172 { 1173 struct pci_devinfo *dinfo = device_get_ivars(child); 1174 pcicfgregs *cfg = &dinfo->cfg; 1175 1176 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1177 pci_read_vpd(device_get_parent(dev), cfg); 1178 1179 *identptr = cfg->vpd.vpd_ident; 1180 1181 if (*identptr == NULL) 1182 return (ENXIO); 1183 1184 return (0); 1185 } 1186 1187 int 1188 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 1189 const char **vptr) 1190 { 1191 struct pci_devinfo *dinfo = device_get_ivars(child); 1192 pcicfgregs *cfg = &dinfo->cfg; 1193 int i; 1194 1195 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1196 pci_read_vpd(device_get_parent(dev), cfg); 1197 1198 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 1199 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 1200 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { 1201 *vptr = cfg->vpd.vpd_ros[i].value; 1202 return (0); 1203 } 1204 1205 *vptr = NULL; 1206 return (ENXIO); 1207 } 1208 1209 struct pcicfg_vpd * 1210 pci_fetch_vpd_list(device_t dev) 1211 { 1212 struct pci_devinfo *dinfo = device_get_ivars(dev); 1213 pcicfgregs *cfg = &dinfo->cfg; 1214 1215 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1216 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg); 1217 return (&cfg->vpd); 1218 } 1219 1220 /* 1221 * Find the requested HyperTransport capability and return the offset 1222 * in configuration space via the pointer provided. The function 1223 * returns 0 on success and an error code otherwise. 1224 */ 1225 int 1226 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg) 1227 { 1228 int ptr, error; 1229 uint16_t val; 1230 1231 error = pci_find_cap(child, PCIY_HT, &ptr); 1232 if (error) 1233 return (error); 1234 1235 /* 1236 * Traverse the capabilities list checking each HT capability 1237 * to see if it matches the requested HT capability. 1238 */ 1239 while (ptr != 0) { 1240 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1241 if (capability == PCIM_HTCAP_SLAVE || 1242 capability == PCIM_HTCAP_HOST) 1243 val &= 0xe000; 1244 else 1245 val &= PCIM_HTCMD_CAP_MASK; 1246 if (val == capability) { 1247 if (capreg != NULL) 1248 *capreg = ptr; 1249 return (0); 1250 } 1251 1252 /* Skip to the next HT capability. */ 1253 while (ptr != 0) { 1254 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1255 if (pci_read_config(child, ptr + PCICAP_ID, 1) == 1256 PCIY_HT) 1257 break; 1258 } 1259 } 1260 return (ENOENT); 1261 } 1262 1263 /* 1264 * Find the requested capability and return the offset in 1265 * configuration space via the pointer provided. The function returns 1266 * 0 on success and an error code otherwise. 1267 */ 1268 int 1269 pci_find_cap_method(device_t dev, device_t child, int capability, 1270 int *capreg) 1271 { 1272 struct pci_devinfo *dinfo = device_get_ivars(child); 1273 pcicfgregs *cfg = &dinfo->cfg; 1274 u_int32_t status; 1275 u_int8_t ptr; 1276 1277 /* 1278 * Check the CAP_LIST bit of the PCI status register first. 1279 */ 1280 status = pci_read_config(child, PCIR_STATUS, 2); 1281 if (!(status & PCIM_STATUS_CAPPRESENT)) 1282 return (ENXIO); 1283 1284 /* 1285 * Determine the start pointer of the capabilities list. 1286 */ 1287 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1288 case PCIM_HDRTYPE_NORMAL: 1289 case PCIM_HDRTYPE_BRIDGE: 1290 ptr = PCIR_CAP_PTR; 1291 break; 1292 case PCIM_HDRTYPE_CARDBUS: 1293 ptr = PCIR_CAP_PTR_2; 1294 break; 1295 default: 1296 /* XXX: panic? */ 1297 return (ENXIO); /* no extended capabilities support */ 1298 } 1299 ptr = pci_read_config(child, ptr, 1); 1300 1301 /* 1302 * Traverse the capabilities list. 1303 */ 1304 while (ptr != 0) { 1305 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1306 if (capreg != NULL) 1307 *capreg = ptr; 1308 return (0); 1309 } 1310 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1311 } 1312 1313 return (ENOENT); 1314 } 1315 1316 /* 1317 * Find the requested extended capability and return the offset in 1318 * configuration space via the pointer provided. The function returns 1319 * 0 on success and an error code otherwise. 1320 */ 1321 int 1322 pci_find_extcap_method(device_t dev, device_t child, int capability, 1323 int *capreg) 1324 { 1325 struct pci_devinfo *dinfo = device_get_ivars(child); 1326 pcicfgregs *cfg = &dinfo->cfg; 1327 uint32_t ecap; 1328 uint16_t ptr; 1329 1330 /* Only supported for PCI-express devices. */ 1331 if (cfg->pcie.pcie_location == 0) 1332 return (ENXIO); 1333 1334 ptr = PCIR_EXTCAP; 1335 ecap = pci_read_config(child, ptr, 4); 1336 if (ecap == 0xffffffff || ecap == 0) 1337 return (ENOENT); 1338 for (;;) { 1339 if (PCI_EXTCAP_ID(ecap) == capability) { 1340 if (capreg != NULL) 1341 *capreg = ptr; 1342 return (0); 1343 } 1344 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1345 if (ptr == 0) 1346 break; 1347 ecap = pci_read_config(child, ptr, 4); 1348 } 1349 1350 return (ENOENT); 1351 } 1352 1353 /* 1354 * Support for MSI-X message interrupts. 1355 */ 1356 void 1357 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data) 1358 { 1359 struct pci_devinfo *dinfo = device_get_ivars(dev); 1360 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1361 uint32_t offset; 1362 1363 KASSERT(msix->msix_table_len > index, ("bogus index")); 1364 offset = msix->msix_table_offset + index * 16; 1365 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); 1366 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); 1367 bus_write_4(msix->msix_table_res, offset + 8, data); 1368 1369 /* Enable MSI -> HT mapping. */ 1370 pci_ht_map_msi(dev, address); 1371 } 1372 1373 void 1374 pci_mask_msix(device_t dev, u_int index) 1375 { 1376 struct pci_devinfo *dinfo = device_get_ivars(dev); 1377 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1378 uint32_t offset, val; 1379 1380 KASSERT(msix->msix_msgnum > index, ("bogus index")); 1381 offset = msix->msix_table_offset + index * 16 + 12; 1382 val = bus_read_4(msix->msix_table_res, offset); 1383 if (!(val & PCIM_MSIX_VCTRL_MASK)) { 1384 val |= PCIM_MSIX_VCTRL_MASK; 1385 bus_write_4(msix->msix_table_res, offset, val); 1386 } 1387 } 1388 1389 void 1390 pci_unmask_msix(device_t dev, u_int index) 1391 { 1392 struct pci_devinfo *dinfo = device_get_ivars(dev); 1393 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1394 uint32_t offset, val; 1395 1396 KASSERT(msix->msix_table_len > index, ("bogus index")); 1397 offset = msix->msix_table_offset + index * 16 + 12; 1398 val = bus_read_4(msix->msix_table_res, offset); 1399 if (val & PCIM_MSIX_VCTRL_MASK) { 1400 val &= ~PCIM_MSIX_VCTRL_MASK; 1401 bus_write_4(msix->msix_table_res, offset, val); 1402 } 1403 } 1404 1405 int 1406 pci_pending_msix(device_t dev, u_int index) 1407 { 1408 struct pci_devinfo *dinfo = device_get_ivars(dev); 1409 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1410 uint32_t offset, bit; 1411 1412 KASSERT(msix->msix_table_len > index, ("bogus index")); 1413 offset = msix->msix_pba_offset + (index / 32) * 4; 1414 bit = 1 << index % 32; 1415 return (bus_read_4(msix->msix_pba_res, offset) & bit); 1416 } 1417 1418 /* 1419 * Restore MSI-X registers and table during resume. If MSI-X is 1420 * enabled then walk the virtual table to restore the actual MSI-X 1421 * table. 1422 */ 1423 static void 1424 pci_resume_msix(device_t dev) 1425 { 1426 struct pci_devinfo *dinfo = device_get_ivars(dev); 1427 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1428 struct msix_table_entry *mte; 1429 struct msix_vector *mv; 1430 int i; 1431 1432 if (msix->msix_alloc > 0) { 1433 /* First, mask all vectors. */ 1434 for (i = 0; i < msix->msix_msgnum; i++) 1435 pci_mask_msix(dev, i); 1436 1437 /* Second, program any messages with at least one handler. */ 1438 for (i = 0; i < msix->msix_table_len; i++) { 1439 mte = &msix->msix_table[i]; 1440 if (mte->mte_vector == 0 || mte->mte_handlers == 0) 1441 continue; 1442 mv = &msix->msix_vectors[mte->mte_vector - 1]; 1443 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data); 1444 pci_unmask_msix(dev, i); 1445 } 1446 } 1447 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, 1448 msix->msix_ctrl, 2); 1449 } 1450 1451 /* 1452 * Attempt to allocate *count MSI-X messages. The actual number allocated is 1453 * returned in *count. After this function returns, each message will be 1454 * available to the driver as SYS_RES_IRQ resources starting at rid 1. 1455 */ 1456 int 1457 pci_alloc_msix_method(device_t dev, device_t child, int *count) 1458 { 1459 struct pci_devinfo *dinfo = device_get_ivars(child); 1460 pcicfgregs *cfg = &dinfo->cfg; 1461 struct resource_list_entry *rle; 1462 int actual, error, i, irq, max; 1463 1464 /* Don't let count == 0 get us into trouble. */ 1465 if (*count == 0) 1466 return (EINVAL); 1467 1468 /* If rid 0 is allocated, then fail. */ 1469 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1470 if (rle != NULL && rle->res != NULL) 1471 return (ENXIO); 1472 1473 /* Already have allocated messages? */ 1474 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1475 return (ENXIO); 1476 1477 /* If MSI-X is blacklisted for this system, fail. */ 1478 if (pci_msix_blacklisted()) 1479 return (ENXIO); 1480 1481 /* MSI-X capability present? */ 1482 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1483 return (ENODEV); 1484 1485 /* Make sure the appropriate BARs are mapped. */ 1486 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1487 cfg->msix.msix_table_bar); 1488 if (rle == NULL || rle->res == NULL || 1489 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1490 return (ENXIO); 1491 cfg->msix.msix_table_res = rle->res; 1492 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1493 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1494 cfg->msix.msix_pba_bar); 1495 if (rle == NULL || rle->res == NULL || 1496 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1497 return (ENXIO); 1498 } 1499 cfg->msix.msix_pba_res = rle->res; 1500 1501 if (bootverbose) 1502 device_printf(child, 1503 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1504 *count, cfg->msix.msix_msgnum); 1505 max = min(*count, cfg->msix.msix_msgnum); 1506 for (i = 0; i < max; i++) { 1507 /* Allocate a message. */ 1508 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq); 1509 if (error) { 1510 if (i == 0) 1511 return (error); 1512 break; 1513 } 1514 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1515 irq, 1); 1516 } 1517 actual = i; 1518 1519 if (bootverbose) { 1520 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1521 if (actual == 1) 1522 device_printf(child, "using IRQ %lu for MSI-X\n", 1523 rle->start); 1524 else { 1525 int run; 1526 1527 /* 1528 * Be fancy and try to print contiguous runs of 1529 * IRQ values as ranges. 'irq' is the previous IRQ. 1530 * 'run' is true if we are in a range. 1531 */ 1532 device_printf(child, "using IRQs %lu", rle->start); 1533 irq = rle->start; 1534 run = 0; 1535 for (i = 1; i < actual; i++) { 1536 rle = resource_list_find(&dinfo->resources, 1537 SYS_RES_IRQ, i + 1); 1538 1539 /* Still in a run? */ 1540 if (rle->start == irq + 1) { 1541 run = 1; 1542 irq++; 1543 continue; 1544 } 1545 1546 /* Finish previous range. */ 1547 if (run) { 1548 printf("-%d", irq); 1549 run = 0; 1550 } 1551 1552 /* Start new range. */ 1553 printf(",%lu", rle->start); 1554 irq = rle->start; 1555 } 1556 1557 /* Unfinished range? */ 1558 if (run) 1559 printf("-%d", irq); 1560 printf(" for MSI-X\n"); 1561 } 1562 } 1563 1564 /* Mask all vectors. */ 1565 for (i = 0; i < cfg->msix.msix_msgnum; i++) 1566 pci_mask_msix(child, i); 1567 1568 /* Allocate and initialize vector data and virtual table. */ 1569 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual, 1570 M_DEVBUF, M_WAITOK | M_ZERO); 1571 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual, 1572 M_DEVBUF, M_WAITOK | M_ZERO); 1573 for (i = 0; i < actual; i++) { 1574 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1575 cfg->msix.msix_vectors[i].mv_irq = rle->start; 1576 cfg->msix.msix_table[i].mte_vector = i + 1; 1577 } 1578 1579 /* Update control register to enable MSI-X. */ 1580 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1581 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1582 cfg->msix.msix_ctrl, 2); 1583 1584 /* Update counts of alloc'd messages. */ 1585 cfg->msix.msix_alloc = actual; 1586 cfg->msix.msix_table_len = actual; 1587 *count = actual; 1588 return (0); 1589 } 1590 1591 /* 1592 * By default, pci_alloc_msix() will assign the allocated IRQ 1593 * resources consecutively to the first N messages in the MSI-X table. 1594 * However, device drivers may want to use different layouts if they 1595 * either receive fewer messages than they asked for, or they wish to 1596 * populate the MSI-X table sparsely. This method allows the driver 1597 * to specify what layout it wants. It must be called after a 1598 * successful pci_alloc_msix() but before any of the associated 1599 * SYS_RES_IRQ resources are allocated via bus_alloc_resource(). 1600 * 1601 * The 'vectors' array contains 'count' message vectors. The array 1602 * maps directly to the MSI-X table in that index 0 in the array 1603 * specifies the vector for the first message in the MSI-X table, etc. 1604 * The vector value in each array index can either be 0 to indicate 1605 * that no vector should be assigned to a message slot, or it can be a 1606 * number from 1 to N (where N is the count returned from a 1607 * succcessful call to pci_alloc_msix()) to indicate which message 1608 * vector (IRQ) to be used for the corresponding message. 1609 * 1610 * On successful return, each message with a non-zero vector will have 1611 * an associated SYS_RES_IRQ whose rid is equal to the array index + 1612 * 1. Additionally, if any of the IRQs allocated via the previous 1613 * call to pci_alloc_msix() are not used in the mapping, those IRQs 1614 * will be freed back to the system automatically. 1615 * 1616 * For example, suppose a driver has a MSI-X table with 6 messages and 1617 * asks for 6 messages, but pci_alloc_msix() only returns a count of 1618 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and 1619 * C. After the call to pci_alloc_msix(), the device will be setup to 1620 * have an MSI-X table of ABC--- (where - means no vector assigned). 1621 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 }, 1622 * then the MSI-X table will look like A-AB-B, and the 'C' vector will 1623 * be freed back to the system. This device will also have valid 1624 * SYS_RES_IRQ rids of 1, 3, 4, and 6. 1625 * 1626 * In any case, the SYS_RES_IRQ rid X will always map to the message 1627 * at MSI-X table index X - 1 and will only be valid if a vector is 1628 * assigned to that table entry. 1629 */ 1630 int 1631 pci_remap_msix_method(device_t dev, device_t child, int count, 1632 const u_int *vectors) 1633 { 1634 struct pci_devinfo *dinfo = device_get_ivars(child); 1635 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1636 struct resource_list_entry *rle; 1637 int i, irq, j, *used; 1638 1639 /* 1640 * Have to have at least one message in the table but the 1641 * table can't be bigger than the actual MSI-X table in the 1642 * device. 1643 */ 1644 if (count == 0 || count > msix->msix_msgnum) 1645 return (EINVAL); 1646 1647 /* Sanity check the vectors. */ 1648 for (i = 0; i < count; i++) 1649 if (vectors[i] > msix->msix_alloc) 1650 return (EINVAL); 1651 1652 /* 1653 * Make sure there aren't any holes in the vectors to be used. 1654 * It's a big pain to support it, and it doesn't really make 1655 * sense anyway. Also, at least one vector must be used. 1656 */ 1657 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK | 1658 M_ZERO); 1659 for (i = 0; i < count; i++) 1660 if (vectors[i] != 0) 1661 used[vectors[i] - 1] = 1; 1662 for (i = 0; i < msix->msix_alloc - 1; i++) 1663 if (used[i] == 0 && used[i + 1] == 1) { 1664 free(used, M_DEVBUF); 1665 return (EINVAL); 1666 } 1667 if (used[0] != 1) { 1668 free(used, M_DEVBUF); 1669 return (EINVAL); 1670 } 1671 1672 /* Make sure none of the resources are allocated. */ 1673 for (i = 0; i < msix->msix_table_len; i++) { 1674 if (msix->msix_table[i].mte_vector == 0) 1675 continue; 1676 if (msix->msix_table[i].mte_handlers > 0) 1677 return (EBUSY); 1678 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1679 KASSERT(rle != NULL, ("missing resource")); 1680 if (rle->res != NULL) 1681 return (EBUSY); 1682 } 1683 1684 /* Free the existing resource list entries. */ 1685 for (i = 0; i < msix->msix_table_len; i++) { 1686 if (msix->msix_table[i].mte_vector == 0) 1687 continue; 1688 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1689 } 1690 1691 /* 1692 * Build the new virtual table keeping track of which vectors are 1693 * used. 1694 */ 1695 free(msix->msix_table, M_DEVBUF); 1696 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count, 1697 M_DEVBUF, M_WAITOK | M_ZERO); 1698 for (i = 0; i < count; i++) 1699 msix->msix_table[i].mte_vector = vectors[i]; 1700 msix->msix_table_len = count; 1701 1702 /* Free any unused IRQs and resize the vectors array if necessary. */ 1703 j = msix->msix_alloc - 1; 1704 if (used[j] == 0) { 1705 struct msix_vector *vec; 1706 1707 while (used[j] == 0) { 1708 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 1709 msix->msix_vectors[j].mv_irq); 1710 j--; 1711 } 1712 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF, 1713 M_WAITOK); 1714 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * 1715 (j + 1)); 1716 free(msix->msix_vectors, M_DEVBUF); 1717 msix->msix_vectors = vec; 1718 msix->msix_alloc = j + 1; 1719 } 1720 free(used, M_DEVBUF); 1721 1722 /* Map the IRQs onto the rids. */ 1723 for (i = 0; i < count; i++) { 1724 if (vectors[i] == 0) 1725 continue; 1726 irq = msix->msix_vectors[vectors[i]].mv_irq; 1727 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1728 irq, 1); 1729 } 1730 1731 if (bootverbose) { 1732 device_printf(child, "Remapped MSI-X IRQs as: "); 1733 for (i = 0; i < count; i++) { 1734 if (i != 0) 1735 printf(", "); 1736 if (vectors[i] == 0) 1737 printf("---"); 1738 else 1739 printf("%d", 1740 msix->msix_vectors[vectors[i]].mv_irq); 1741 } 1742 printf("\n"); 1743 } 1744 1745 return (0); 1746 } 1747 1748 static int 1749 pci_release_msix(device_t dev, device_t child) 1750 { 1751 struct pci_devinfo *dinfo = device_get_ivars(child); 1752 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1753 struct resource_list_entry *rle; 1754 int i; 1755 1756 /* Do we have any messages to release? */ 1757 if (msix->msix_alloc == 0) 1758 return (ENODEV); 1759 1760 /* Make sure none of the resources are allocated. */ 1761 for (i = 0; i < msix->msix_table_len; i++) { 1762 if (msix->msix_table[i].mte_vector == 0) 1763 continue; 1764 if (msix->msix_table[i].mte_handlers > 0) 1765 return (EBUSY); 1766 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1767 KASSERT(rle != NULL, ("missing resource")); 1768 if (rle->res != NULL) 1769 return (EBUSY); 1770 } 1771 1772 /* Update control register to disable MSI-X. */ 1773 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 1774 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, 1775 msix->msix_ctrl, 2); 1776 1777 /* Free the resource list entries. */ 1778 for (i = 0; i < msix->msix_table_len; i++) { 1779 if (msix->msix_table[i].mte_vector == 0) 1780 continue; 1781 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 1782 } 1783 free(msix->msix_table, M_DEVBUF); 1784 msix->msix_table_len = 0; 1785 1786 /* Release the IRQs. */ 1787 for (i = 0; i < msix->msix_alloc; i++) 1788 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 1789 msix->msix_vectors[i].mv_irq); 1790 free(msix->msix_vectors, M_DEVBUF); 1791 msix->msix_alloc = 0; 1792 return (0); 1793 } 1794 1795 /* 1796 * Return the max supported MSI-X messages this device supports. 1797 * Basically, assuming the MD code can alloc messages, this function 1798 * should return the maximum value that pci_alloc_msix() can return. 1799 * Thus, it is subject to the tunables, etc. 1800 */ 1801 int 1802 pci_msix_count_method(device_t dev, device_t child) 1803 { 1804 struct pci_devinfo *dinfo = device_get_ivars(child); 1805 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1806 1807 if (pci_do_msix && msix->msix_location != 0) 1808 return (msix->msix_msgnum); 1809 return (0); 1810 } 1811 1812 /* 1813 * HyperTransport MSI mapping control 1814 */ 1815 void 1816 pci_ht_map_msi(device_t dev, uint64_t addr) 1817 { 1818 struct pci_devinfo *dinfo = device_get_ivars(dev); 1819 struct pcicfg_ht *ht = &dinfo->cfg.ht; 1820 1821 if (!ht->ht_msimap) 1822 return; 1823 1824 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && 1825 ht->ht_msiaddr >> 20 == addr >> 20) { 1826 /* Enable MSI -> HT mapping. */ 1827 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 1828 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 1829 ht->ht_msictrl, 2); 1830 } 1831 1832 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { 1833 /* Disable MSI -> HT mapping. */ 1834 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; 1835 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 1836 ht->ht_msictrl, 2); 1837 } 1838 } 1839 1840 int 1841 pci_get_max_read_req(device_t dev) 1842 { 1843 struct pci_devinfo *dinfo = device_get_ivars(dev); 1844 int cap; 1845 uint16_t val; 1846 1847 cap = dinfo->cfg.pcie.pcie_location; 1848 if (cap == 0) 1849 return (0); 1850 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 1851 val &= PCIEM_CTL_MAX_READ_REQUEST; 1852 val >>= 12; 1853 return (1 << (val + 7)); 1854 } 1855 1856 int 1857 pci_set_max_read_req(device_t dev, int size) 1858 { 1859 struct pci_devinfo *dinfo = device_get_ivars(dev); 1860 int cap; 1861 uint16_t val; 1862 1863 cap = dinfo->cfg.pcie.pcie_location; 1864 if (cap == 0) 1865 return (0); 1866 if (size < 128) 1867 size = 128; 1868 if (size > 4096) 1869 size = 4096; 1870 size = (1 << (fls(size) - 1)); 1871 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 1872 val &= ~PCIEM_CTL_MAX_READ_REQUEST; 1873 val |= (fls(size) - 8) << 12; 1874 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2); 1875 return (size); 1876 } 1877 1878 /* 1879 * Support for MSI message signalled interrupts. 1880 */ 1881 void 1882 pci_enable_msi(device_t dev, uint64_t address, uint16_t data) 1883 { 1884 struct pci_devinfo *dinfo = device_get_ivars(dev); 1885 struct pcicfg_msi *msi = &dinfo->cfg.msi; 1886 1887 /* Write data and address values. */ 1888 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 1889 address & 0xffffffff, 4); 1890 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 1891 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH, 1892 address >> 32, 4); 1893 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT, 1894 data, 2); 1895 } else 1896 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data, 1897 2); 1898 1899 /* Enable MSI in the control register. */ 1900 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 1901 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 1902 2); 1903 1904 /* Enable MSI -> HT mapping. */ 1905 pci_ht_map_msi(dev, address); 1906 } 1907 1908 void 1909 pci_disable_msi(device_t dev) 1910 { 1911 struct pci_devinfo *dinfo = device_get_ivars(dev); 1912 struct pcicfg_msi *msi = &dinfo->cfg.msi; 1913 1914 /* Disable MSI -> HT mapping. */ 1915 pci_ht_map_msi(dev, 0); 1916 1917 /* Disable MSI in the control register. */ 1918 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; 1919 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 1920 2); 1921 } 1922 1923 /* 1924 * Restore MSI registers during resume. If MSI is enabled then 1925 * restore the data and address registers in addition to the control 1926 * register. 1927 */ 1928 static void 1929 pci_resume_msi(device_t dev) 1930 { 1931 struct pci_devinfo *dinfo = device_get_ivars(dev); 1932 struct pcicfg_msi *msi = &dinfo->cfg.msi; 1933 uint64_t address; 1934 uint16_t data; 1935 1936 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 1937 address = msi->msi_addr; 1938 data = msi->msi_data; 1939 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 1940 address & 0xffffffff, 4); 1941 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 1942 pci_write_config(dev, msi->msi_location + 1943 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 1944 pci_write_config(dev, msi->msi_location + 1945 PCIR_MSI_DATA_64BIT, data, 2); 1946 } else 1947 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, 1948 data, 2); 1949 } 1950 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 1951 2); 1952 } 1953 1954 static int 1955 pci_remap_intr_method(device_t bus, device_t dev, u_int irq) 1956 { 1957 struct pci_devinfo *dinfo = device_get_ivars(dev); 1958 pcicfgregs *cfg = &dinfo->cfg; 1959 struct resource_list_entry *rle; 1960 struct msix_table_entry *mte; 1961 struct msix_vector *mv; 1962 uint64_t addr; 1963 uint32_t data; 1964 int error, i, j; 1965 1966 /* 1967 * Handle MSI first. We try to find this IRQ among our list 1968 * of MSI IRQs. If we find it, we request updated address and 1969 * data registers and apply the results. 1970 */ 1971 if (cfg->msi.msi_alloc > 0) { 1972 1973 /* If we don't have any active handlers, nothing to do. */ 1974 if (cfg->msi.msi_handlers == 0) 1975 return (0); 1976 for (i = 0; i < cfg->msi.msi_alloc; i++) { 1977 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1978 i + 1); 1979 if (rle->start == irq) { 1980 error = PCIB_MAP_MSI(device_get_parent(bus), 1981 dev, irq, &addr, &data); 1982 if (error) 1983 return (error); 1984 pci_disable_msi(dev); 1985 dinfo->cfg.msi.msi_addr = addr; 1986 dinfo->cfg.msi.msi_data = data; 1987 pci_enable_msi(dev, addr, data); 1988 return (0); 1989 } 1990 } 1991 return (ENOENT); 1992 } 1993 1994 /* 1995 * For MSI-X, we check to see if we have this IRQ. If we do, 1996 * we request the updated mapping info. If that works, we go 1997 * through all the slots that use this IRQ and update them. 1998 */ 1999 if (cfg->msix.msix_alloc > 0) { 2000 for (i = 0; i < cfg->msix.msix_alloc; i++) { 2001 mv = &cfg->msix.msix_vectors[i]; 2002 if (mv->mv_irq == irq) { 2003 error = PCIB_MAP_MSI(device_get_parent(bus), 2004 dev, irq, &addr, &data); 2005 if (error) 2006 return (error); 2007 mv->mv_address = addr; 2008 mv->mv_data = data; 2009 for (j = 0; j < cfg->msix.msix_table_len; j++) { 2010 mte = &cfg->msix.msix_table[j]; 2011 if (mte->mte_vector != i + 1) 2012 continue; 2013 if (mte->mte_handlers == 0) 2014 continue; 2015 pci_mask_msix(dev, j); 2016 pci_enable_msix(dev, j, addr, data); 2017 pci_unmask_msix(dev, j); 2018 } 2019 } 2020 } 2021 return (ENOENT); 2022 } 2023 2024 return (ENOENT); 2025 } 2026 2027 /* 2028 * Returns true if the specified device is blacklisted because MSI 2029 * doesn't work. 2030 */ 2031 int 2032 pci_msi_device_blacklisted(device_t dev) 2033 { 2034 2035 if (!pci_honor_msi_blacklist) 2036 return (0); 2037 2038 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI)); 2039 } 2040 2041 /* 2042 * Determine if MSI is blacklisted globally on this system. Currently, 2043 * we just check for blacklisted chipsets as represented by the 2044 * host-PCI bridge at device 0:0:0. In the future, it may become 2045 * necessary to check other system attributes, such as the kenv values 2046 * that give the motherboard manufacturer and model number. 2047 */ 2048 static int 2049 pci_msi_blacklisted(void) 2050 { 2051 device_t dev; 2052 2053 if (!pci_honor_msi_blacklist) 2054 return (0); 2055 2056 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ 2057 if (!(pcie_chipset || pcix_chipset)) { 2058 if (vm_guest != VM_GUEST_NO) { 2059 /* 2060 * Whitelist older chipsets in virtual 2061 * machines known to support MSI. 2062 */ 2063 dev = pci_find_bsf(0, 0, 0); 2064 if (dev != NULL) 2065 return (!pci_has_quirk(pci_get_devid(dev), 2066 PCI_QUIRK_ENABLE_MSI_VM)); 2067 } 2068 return (1); 2069 } 2070 2071 dev = pci_find_bsf(0, 0, 0); 2072 if (dev != NULL) 2073 return (pci_msi_device_blacklisted(dev)); 2074 return (0); 2075 } 2076 2077 /* 2078 * Returns true if the specified device is blacklisted because MSI-X 2079 * doesn't work. Note that this assumes that if MSI doesn't work, 2080 * MSI-X doesn't either. 2081 */ 2082 int 2083 pci_msix_device_blacklisted(device_t dev) 2084 { 2085 2086 if (!pci_honor_msi_blacklist) 2087 return (0); 2088 2089 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX)) 2090 return (1); 2091 2092 return (pci_msi_device_blacklisted(dev)); 2093 } 2094 2095 /* 2096 * Determine if MSI-X is blacklisted globally on this system. If MSI 2097 * is blacklisted, assume that MSI-X is as well. Check for additional 2098 * chipsets where MSI works but MSI-X does not. 2099 */ 2100 static int 2101 pci_msix_blacklisted(void) 2102 { 2103 device_t dev; 2104 2105 if (!pci_honor_msi_blacklist) 2106 return (0); 2107 2108 dev = pci_find_bsf(0, 0, 0); 2109 if (dev != NULL && pci_has_quirk(pci_get_devid(dev), 2110 PCI_QUIRK_DISABLE_MSIX)) 2111 return (1); 2112 2113 return (pci_msi_blacklisted()); 2114 } 2115 2116 /* 2117 * Attempt to allocate *count MSI messages. The actual number allocated is 2118 * returned in *count. After this function returns, each message will be 2119 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 2120 */ 2121 int 2122 pci_alloc_msi_method(device_t dev, device_t child, int *count) 2123 { 2124 struct pci_devinfo *dinfo = device_get_ivars(child); 2125 pcicfgregs *cfg = &dinfo->cfg; 2126 struct resource_list_entry *rle; 2127 int actual, error, i, irqs[32]; 2128 uint16_t ctrl; 2129 2130 /* Don't let count == 0 get us into trouble. */ 2131 if (*count == 0) 2132 return (EINVAL); 2133 2134 /* If rid 0 is allocated, then fail. */ 2135 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 2136 if (rle != NULL && rle->res != NULL) 2137 return (ENXIO); 2138 2139 /* Already have allocated messages? */ 2140 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 2141 return (ENXIO); 2142 2143 /* If MSI is blacklisted for this system, fail. */ 2144 if (pci_msi_blacklisted()) 2145 return (ENXIO); 2146 2147 /* MSI capability present? */ 2148 if (cfg->msi.msi_location == 0 || !pci_do_msi) 2149 return (ENODEV); 2150 2151 if (bootverbose) 2152 device_printf(child, 2153 "attempting to allocate %d MSI vectors (%d supported)\n", 2154 *count, cfg->msi.msi_msgnum); 2155 2156 /* Don't ask for more than the device supports. */ 2157 actual = min(*count, cfg->msi.msi_msgnum); 2158 2159 /* Don't ask for more than 32 messages. */ 2160 actual = min(actual, 32); 2161 2162 /* MSI requires power of 2 number of messages. */ 2163 if (!powerof2(actual)) 2164 return (EINVAL); 2165 2166 for (;;) { 2167 /* Try to allocate N messages. */ 2168 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 2169 actual, irqs); 2170 if (error == 0) 2171 break; 2172 if (actual == 1) 2173 return (error); 2174 2175 /* Try N / 2. */ 2176 actual >>= 1; 2177 } 2178 2179 /* 2180 * We now have N actual messages mapped onto SYS_RES_IRQ 2181 * resources in the irqs[] array, so add new resources 2182 * starting at rid 1. 2183 */ 2184 for (i = 0; i < actual; i++) 2185 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 2186 irqs[i], irqs[i], 1); 2187 2188 if (bootverbose) { 2189 if (actual == 1) 2190 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 2191 else { 2192 int run; 2193 2194 /* 2195 * Be fancy and try to print contiguous runs 2196 * of IRQ values as ranges. 'run' is true if 2197 * we are in a range. 2198 */ 2199 device_printf(child, "using IRQs %d", irqs[0]); 2200 run = 0; 2201 for (i = 1; i < actual; i++) { 2202 2203 /* Still in a run? */ 2204 if (irqs[i] == irqs[i - 1] + 1) { 2205 run = 1; 2206 continue; 2207 } 2208 2209 /* Finish previous range. */ 2210 if (run) { 2211 printf("-%d", irqs[i - 1]); 2212 run = 0; 2213 } 2214 2215 /* Start new range. */ 2216 printf(",%d", irqs[i]); 2217 } 2218 2219 /* Unfinished range? */ 2220 if (run) 2221 printf("-%d", irqs[actual - 1]); 2222 printf(" for MSI\n"); 2223 } 2224 } 2225 2226 /* Update control register with actual count. */ 2227 ctrl = cfg->msi.msi_ctrl; 2228 ctrl &= ~PCIM_MSICTRL_MME_MASK; 2229 ctrl |= (ffs(actual) - 1) << 4; 2230 cfg->msi.msi_ctrl = ctrl; 2231 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 2232 2233 /* Update counts of alloc'd messages. */ 2234 cfg->msi.msi_alloc = actual; 2235 cfg->msi.msi_handlers = 0; 2236 *count = actual; 2237 return (0); 2238 } 2239 2240 /* Release the MSI messages associated with this device. */ 2241 int 2242 pci_release_msi_method(device_t dev, device_t child) 2243 { 2244 struct pci_devinfo *dinfo = device_get_ivars(child); 2245 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2246 struct resource_list_entry *rle; 2247 int error, i, irqs[32]; 2248 2249 /* Try MSI-X first. */ 2250 error = pci_release_msix(dev, child); 2251 if (error != ENODEV) 2252 return (error); 2253 2254 /* Do we have any messages to release? */ 2255 if (msi->msi_alloc == 0) 2256 return (ENODEV); 2257 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); 2258 2259 /* Make sure none of the resources are allocated. */ 2260 if (msi->msi_handlers > 0) 2261 return (EBUSY); 2262 for (i = 0; i < msi->msi_alloc; i++) { 2263 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2264 KASSERT(rle != NULL, ("missing MSI resource")); 2265 if (rle->res != NULL) 2266 return (EBUSY); 2267 irqs[i] = rle->start; 2268 } 2269 2270 /* Update control register with 0 count. */ 2271 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), 2272 ("%s: MSI still enabled", __func__)); 2273 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; 2274 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2275 msi->msi_ctrl, 2); 2276 2277 /* Release the messages. */ 2278 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); 2279 for (i = 0; i < msi->msi_alloc; i++) 2280 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2281 2282 /* Update alloc count. */ 2283 msi->msi_alloc = 0; 2284 msi->msi_addr = 0; 2285 msi->msi_data = 0; 2286 return (0); 2287 } 2288 2289 /* 2290 * Return the max supported MSI messages this device supports. 2291 * Basically, assuming the MD code can alloc messages, this function 2292 * should return the maximum value that pci_alloc_msi() can return. 2293 * Thus, it is subject to the tunables, etc. 2294 */ 2295 int 2296 pci_msi_count_method(device_t dev, device_t child) 2297 { 2298 struct pci_devinfo *dinfo = device_get_ivars(child); 2299 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2300 2301 if (pci_do_msi && msi->msi_location != 0) 2302 return (msi->msi_msgnum); 2303 return (0); 2304 } 2305 2306 /* free pcicfgregs structure and all depending data structures */ 2307 2308 int 2309 pci_freecfg(struct pci_devinfo *dinfo) 2310 { 2311 struct devlist *devlist_head; 2312 struct pci_map *pm, *next; 2313 int i; 2314 2315 devlist_head = &pci_devq; 2316 2317 if (dinfo->cfg.vpd.vpd_reg) { 2318 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF); 2319 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++) 2320 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF); 2321 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF); 2322 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++) 2323 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF); 2324 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF); 2325 } 2326 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { 2327 free(pm, M_DEVBUF); 2328 } 2329 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 2330 free(dinfo, M_DEVBUF); 2331 2332 /* increment the generation count */ 2333 pci_generation++; 2334 2335 /* we're losing one device */ 2336 pci_numdevs--; 2337 return (0); 2338 } 2339 2340 /* 2341 * PCI power manangement 2342 */ 2343 int 2344 pci_set_powerstate_method(device_t dev, device_t child, int state) 2345 { 2346 struct pci_devinfo *dinfo = device_get_ivars(child); 2347 pcicfgregs *cfg = &dinfo->cfg; 2348 uint16_t status; 2349 int result, oldstate, highest, delay; 2350 2351 if (cfg->pp.pp_cap == 0) 2352 return (EOPNOTSUPP); 2353 2354 /* 2355 * Optimize a no state change request away. While it would be OK to 2356 * write to the hardware in theory, some devices have shown odd 2357 * behavior when going from D3 -> D3. 2358 */ 2359 oldstate = pci_get_powerstate(child); 2360 if (oldstate == state) 2361 return (0); 2362 2363 /* 2364 * The PCI power management specification states that after a state 2365 * transition between PCI power states, system software must 2366 * guarantee a minimal delay before the function accesses the device. 2367 * Compute the worst case delay that we need to guarantee before we 2368 * access the device. Many devices will be responsive much more 2369 * quickly than this delay, but there are some that don't respond 2370 * instantly to state changes. Transitions to/from D3 state require 2371 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 2372 * is done below with DELAY rather than a sleeper function because 2373 * this function can be called from contexts where we cannot sleep. 2374 */ 2375 highest = (oldstate > state) ? oldstate : state; 2376 if (highest == PCI_POWERSTATE_D3) 2377 delay = 10000; 2378 else if (highest == PCI_POWERSTATE_D2) 2379 delay = 200; 2380 else 2381 delay = 0; 2382 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 2383 & ~PCIM_PSTAT_DMASK; 2384 result = 0; 2385 switch (state) { 2386 case PCI_POWERSTATE_D0: 2387 status |= PCIM_PSTAT_D0; 2388 break; 2389 case PCI_POWERSTATE_D1: 2390 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 2391 return (EOPNOTSUPP); 2392 status |= PCIM_PSTAT_D1; 2393 break; 2394 case PCI_POWERSTATE_D2: 2395 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 2396 return (EOPNOTSUPP); 2397 status |= PCIM_PSTAT_D2; 2398 break; 2399 case PCI_POWERSTATE_D3: 2400 status |= PCIM_PSTAT_D3; 2401 break; 2402 default: 2403 return (EINVAL); 2404 } 2405 2406 if (bootverbose) 2407 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate, 2408 state); 2409 2410 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 2411 if (delay) 2412 DELAY(delay); 2413 return (0); 2414 } 2415 2416 int 2417 pci_get_powerstate_method(device_t dev, device_t child) 2418 { 2419 struct pci_devinfo *dinfo = device_get_ivars(child); 2420 pcicfgregs *cfg = &dinfo->cfg; 2421 uint16_t status; 2422 int result; 2423 2424 if (cfg->pp.pp_cap != 0) { 2425 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 2426 switch (status & PCIM_PSTAT_DMASK) { 2427 case PCIM_PSTAT_D0: 2428 result = PCI_POWERSTATE_D0; 2429 break; 2430 case PCIM_PSTAT_D1: 2431 result = PCI_POWERSTATE_D1; 2432 break; 2433 case PCIM_PSTAT_D2: 2434 result = PCI_POWERSTATE_D2; 2435 break; 2436 case PCIM_PSTAT_D3: 2437 result = PCI_POWERSTATE_D3; 2438 break; 2439 default: 2440 result = PCI_POWERSTATE_UNKNOWN; 2441 break; 2442 } 2443 } else { 2444 /* No support, device is always at D0 */ 2445 result = PCI_POWERSTATE_D0; 2446 } 2447 return (result); 2448 } 2449 2450 /* 2451 * Some convenience functions for PCI device drivers. 2452 */ 2453 2454 static __inline void 2455 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 2456 { 2457 uint16_t command; 2458 2459 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2460 command |= bit; 2461 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2462 } 2463 2464 static __inline void 2465 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 2466 { 2467 uint16_t command; 2468 2469 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2470 command &= ~bit; 2471 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2472 } 2473 2474 int 2475 pci_enable_busmaster_method(device_t dev, device_t child) 2476 { 2477 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2478 return (0); 2479 } 2480 2481 int 2482 pci_disable_busmaster_method(device_t dev, device_t child) 2483 { 2484 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 2485 return (0); 2486 } 2487 2488 int 2489 pci_enable_io_method(device_t dev, device_t child, int space) 2490 { 2491 uint16_t bit; 2492 2493 switch(space) { 2494 case SYS_RES_IOPORT: 2495 bit = PCIM_CMD_PORTEN; 2496 break; 2497 case SYS_RES_MEMORY: 2498 bit = PCIM_CMD_MEMEN; 2499 break; 2500 default: 2501 return (EINVAL); 2502 } 2503 pci_set_command_bit(dev, child, bit); 2504 return (0); 2505 } 2506 2507 int 2508 pci_disable_io_method(device_t dev, device_t child, int space) 2509 { 2510 uint16_t bit; 2511 2512 switch(space) { 2513 case SYS_RES_IOPORT: 2514 bit = PCIM_CMD_PORTEN; 2515 break; 2516 case SYS_RES_MEMORY: 2517 bit = PCIM_CMD_MEMEN; 2518 break; 2519 default: 2520 return (EINVAL); 2521 } 2522 pci_clear_command_bit(dev, child, bit); 2523 return (0); 2524 } 2525 2526 /* 2527 * New style pci driver. Parent device is either a pci-host-bridge or a 2528 * pci-pci-bridge. Both kinds are represented by instances of pcib. 2529 */ 2530 2531 void 2532 pci_print_verbose(struct pci_devinfo *dinfo) 2533 { 2534 2535 if (bootverbose) { 2536 pcicfgregs *cfg = &dinfo->cfg; 2537 2538 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 2539 cfg->vendor, cfg->device, cfg->revid); 2540 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n", 2541 cfg->domain, cfg->bus, cfg->slot, cfg->func); 2542 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 2543 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 2544 cfg->mfdev); 2545 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 2546 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 2547 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 2548 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 2549 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 2550 if (cfg->intpin > 0) 2551 printf("\tintpin=%c, irq=%d\n", 2552 cfg->intpin +'a' -1, cfg->intline); 2553 if (cfg->pp.pp_cap) { 2554 uint16_t status; 2555 2556 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 2557 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 2558 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 2559 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 2560 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 2561 status & PCIM_PSTAT_DMASK); 2562 } 2563 if (cfg->msi.msi_location) { 2564 int ctrl; 2565 2566 ctrl = cfg->msi.msi_ctrl; 2567 printf("\tMSI supports %d message%s%s%s\n", 2568 cfg->msi.msi_msgnum, 2569 (cfg->msi.msi_msgnum == 1) ? "" : "s", 2570 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 2571 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 2572 } 2573 if (cfg->msix.msix_location) { 2574 printf("\tMSI-X supports %d message%s ", 2575 cfg->msix.msix_msgnum, 2576 (cfg->msix.msix_msgnum == 1) ? "" : "s"); 2577 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 2578 printf("in map 0x%x\n", 2579 cfg->msix.msix_table_bar); 2580 else 2581 printf("in maps 0x%x and 0x%x\n", 2582 cfg->msix.msix_table_bar, 2583 cfg->msix.msix_pba_bar); 2584 } 2585 } 2586 } 2587 2588 static int 2589 pci_porten(device_t dev) 2590 { 2591 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0; 2592 } 2593 2594 static int 2595 pci_memen(device_t dev) 2596 { 2597 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0; 2598 } 2599 2600 static void 2601 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp) 2602 { 2603 struct pci_devinfo *dinfo; 2604 pci_addr_t map, testval; 2605 int ln2range; 2606 uint16_t cmd; 2607 2608 /* 2609 * The device ROM BAR is special. It is always a 32-bit 2610 * memory BAR. Bit 0 is special and should not be set when 2611 * sizing the BAR. 2612 */ 2613 dinfo = device_get_ivars(dev); 2614 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { 2615 map = pci_read_config(dev, reg, 4); 2616 pci_write_config(dev, reg, 0xfffffffe, 4); 2617 testval = pci_read_config(dev, reg, 4); 2618 pci_write_config(dev, reg, map, 4); 2619 *mapp = map; 2620 *testvalp = testval; 2621 return; 2622 } 2623 2624 map = pci_read_config(dev, reg, 4); 2625 ln2range = pci_maprange(map); 2626 if (ln2range == 64) 2627 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 2628 2629 /* 2630 * Disable decoding via the command register before 2631 * determining the BAR's length since we will be placing it in 2632 * a weird state. 2633 */ 2634 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 2635 pci_write_config(dev, PCIR_COMMAND, 2636 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 2637 2638 /* 2639 * Determine the BAR's length by writing all 1's. The bottom 2640 * log_2(size) bits of the BAR will stick as 0 when we read 2641 * the value back. 2642 */ 2643 pci_write_config(dev, reg, 0xffffffff, 4); 2644 testval = pci_read_config(dev, reg, 4); 2645 if (ln2range == 64) { 2646 pci_write_config(dev, reg + 4, 0xffffffff, 4); 2647 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 2648 } 2649 2650 /* 2651 * Restore the original value of the BAR. We may have reprogrammed 2652 * the BAR of the low-level console device and when booting verbose, 2653 * we need the console device addressable. 2654 */ 2655 pci_write_config(dev, reg, map, 4); 2656 if (ln2range == 64) 2657 pci_write_config(dev, reg + 4, map >> 32, 4); 2658 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 2659 2660 *mapp = map; 2661 *testvalp = testval; 2662 } 2663 2664 static void 2665 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base) 2666 { 2667 struct pci_devinfo *dinfo; 2668 int ln2range; 2669 2670 /* The device ROM BAR is always a 32-bit memory BAR. */ 2671 dinfo = device_get_ivars(dev); 2672 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 2673 ln2range = 32; 2674 else 2675 ln2range = pci_maprange(pm->pm_value); 2676 pci_write_config(dev, pm->pm_reg, base, 4); 2677 if (ln2range == 64) 2678 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); 2679 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); 2680 if (ln2range == 64) 2681 pm->pm_value |= (pci_addr_t)pci_read_config(dev, 2682 pm->pm_reg + 4, 4) << 32; 2683 } 2684 2685 struct pci_map * 2686 pci_find_bar(device_t dev, int reg) 2687 { 2688 struct pci_devinfo *dinfo; 2689 struct pci_map *pm; 2690 2691 dinfo = device_get_ivars(dev); 2692 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 2693 if (pm->pm_reg == reg) 2694 return (pm); 2695 } 2696 return (NULL); 2697 } 2698 2699 int 2700 pci_bar_enabled(device_t dev, struct pci_map *pm) 2701 { 2702 struct pci_devinfo *dinfo; 2703 uint16_t cmd; 2704 2705 dinfo = device_get_ivars(dev); 2706 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && 2707 !(pm->pm_value & PCIM_BIOS_ENABLE)) 2708 return (0); 2709 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 2710 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) 2711 return ((cmd & PCIM_CMD_MEMEN) != 0); 2712 else 2713 return ((cmd & PCIM_CMD_PORTEN) != 0); 2714 } 2715 2716 static struct pci_map * 2717 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size) 2718 { 2719 struct pci_devinfo *dinfo; 2720 struct pci_map *pm, *prev; 2721 2722 dinfo = device_get_ivars(dev); 2723 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO); 2724 pm->pm_reg = reg; 2725 pm->pm_value = value; 2726 pm->pm_size = size; 2727 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { 2728 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", 2729 reg)); 2730 if (STAILQ_NEXT(prev, pm_link) == NULL || 2731 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) 2732 break; 2733 } 2734 if (prev != NULL) 2735 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); 2736 else 2737 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); 2738 return (pm); 2739 } 2740 2741 static void 2742 pci_restore_bars(device_t dev) 2743 { 2744 struct pci_devinfo *dinfo; 2745 struct pci_map *pm; 2746 int ln2range; 2747 2748 dinfo = device_get_ivars(dev); 2749 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 2750 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 2751 ln2range = 32; 2752 else 2753 ln2range = pci_maprange(pm->pm_value); 2754 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); 2755 if (ln2range == 64) 2756 pci_write_config(dev, pm->pm_reg + 4, 2757 pm->pm_value >> 32, 4); 2758 } 2759 } 2760 2761 /* 2762 * Add a resource based on a pci map register. Return 1 if the map 2763 * register is a 32bit map register or 2 if it is a 64bit register. 2764 */ 2765 static int 2766 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, 2767 int force, int prefetch) 2768 { 2769 struct pci_map *pm; 2770 pci_addr_t base, map, testval; 2771 pci_addr_t start, end, count; 2772 int barlen, basezero, flags, maprange, mapsize, type; 2773 uint16_t cmd; 2774 struct resource *res; 2775 2776 /* 2777 * The BAR may already exist if the device is a CardBus card 2778 * whose CIS is stored in this BAR. 2779 */ 2780 pm = pci_find_bar(dev, reg); 2781 if (pm != NULL) { 2782 maprange = pci_maprange(pm->pm_value); 2783 barlen = maprange == 64 ? 2 : 1; 2784 return (barlen); 2785 } 2786 2787 pci_read_bar(dev, reg, &map, &testval); 2788 if (PCI_BAR_MEM(map)) { 2789 type = SYS_RES_MEMORY; 2790 if (map & PCIM_BAR_MEM_PREFETCH) 2791 prefetch = 1; 2792 } else 2793 type = SYS_RES_IOPORT; 2794 mapsize = pci_mapsize(testval); 2795 base = pci_mapbase(map); 2796 #ifdef __PCI_BAR_ZERO_VALID 2797 basezero = 0; 2798 #else 2799 basezero = base == 0; 2800 #endif 2801 maprange = pci_maprange(map); 2802 barlen = maprange == 64 ? 2 : 1; 2803 2804 /* 2805 * For I/O registers, if bottom bit is set, and the next bit up 2806 * isn't clear, we know we have a BAR that doesn't conform to the 2807 * spec, so ignore it. Also, sanity check the size of the data 2808 * areas to the type of memory involved. Memory must be at least 2809 * 16 bytes in size, while I/O ranges must be at least 4. 2810 */ 2811 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0) 2812 return (barlen); 2813 if ((type == SYS_RES_MEMORY && mapsize < 4) || 2814 (type == SYS_RES_IOPORT && mapsize < 2)) 2815 return (barlen); 2816 2817 /* Save a record of this BAR. */ 2818 pm = pci_add_bar(dev, reg, map, mapsize); 2819 if (bootverbose) { 2820 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d", 2821 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize); 2822 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 2823 printf(", port disabled\n"); 2824 else if (type == SYS_RES_MEMORY && !pci_memen(dev)) 2825 printf(", memory disabled\n"); 2826 else 2827 printf(", enabled\n"); 2828 } 2829 2830 /* 2831 * If base is 0, then we have problems if this architecture does 2832 * not allow that. It is best to ignore such entries for the 2833 * moment. These will be allocated later if the driver specifically 2834 * requests them. However, some removable busses look better when 2835 * all resources are allocated, so allow '0' to be overriden. 2836 * 2837 * Similarly treat maps whose values is the same as the test value 2838 * read back. These maps have had all f's written to them by the 2839 * BIOS in an attempt to disable the resources. 2840 */ 2841 if (!force && (basezero || map == testval)) 2842 return (barlen); 2843 if ((u_long)base != base) { 2844 device_printf(bus, 2845 "pci%d:%d:%d:%d bar %#x too many address bits", 2846 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev), 2847 pci_get_function(dev), reg); 2848 return (barlen); 2849 } 2850 2851 /* 2852 * This code theoretically does the right thing, but has 2853 * undesirable side effects in some cases where peripherals 2854 * respond oddly to having these bits enabled. Let the user 2855 * be able to turn them off (since pci_enable_io_modes is 1 by 2856 * default). 2857 */ 2858 if (pci_enable_io_modes) { 2859 /* Turn on resources that have been left off by a lazy BIOS */ 2860 if (type == SYS_RES_IOPORT && !pci_porten(dev)) { 2861 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 2862 cmd |= PCIM_CMD_PORTEN; 2863 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 2864 } 2865 if (type == SYS_RES_MEMORY && !pci_memen(dev)) { 2866 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 2867 cmd |= PCIM_CMD_MEMEN; 2868 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 2869 } 2870 } else { 2871 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 2872 return (barlen); 2873 if (type == SYS_RES_MEMORY && !pci_memen(dev)) 2874 return (barlen); 2875 } 2876 2877 count = (pci_addr_t)1 << mapsize; 2878 flags = RF_ALIGNMENT_LOG2(mapsize); 2879 if (prefetch) 2880 flags |= RF_PREFETCHABLE; 2881 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) { 2882 start = 0; /* Let the parent decide. */ 2883 end = ~0ul; 2884 } else { 2885 start = base; 2886 end = base + count - 1; 2887 } 2888 resource_list_add(rl, type, reg, start, end, count); 2889 2890 /* 2891 * Try to allocate the resource for this BAR from our parent 2892 * so that this resource range is already reserved. The 2893 * driver for this device will later inherit this resource in 2894 * pci_alloc_resource(). 2895 */ 2896 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count, 2897 flags); 2898 if (pci_do_realloc_bars && res == NULL && (start != 0 || end != ~0ul)) { 2899 /* 2900 * If the allocation fails, try to allocate a resource for 2901 * this BAR using any available range. The firmware felt 2902 * it was important enough to assign a resource, so don't 2903 * disable decoding if we can help it. 2904 */ 2905 resource_list_delete(rl, type, reg); 2906 resource_list_add(rl, type, reg, 0, ~0ul, count); 2907 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0ul, 2908 count, flags); 2909 } 2910 if (res == NULL) { 2911 /* 2912 * If the allocation fails, delete the resource list entry 2913 * and disable decoding for this device. 2914 * 2915 * If the driver requests this resource in the future, 2916 * pci_reserve_map() will try to allocate a fresh 2917 * resource range. 2918 */ 2919 resource_list_delete(rl, type, reg); 2920 pci_disable_io(dev, type); 2921 if (bootverbose) 2922 device_printf(bus, 2923 "pci%d:%d:%d:%d bar %#x failed to allocate\n", 2924 pci_get_domain(dev), pci_get_bus(dev), 2925 pci_get_slot(dev), pci_get_function(dev), reg); 2926 } else { 2927 start = rman_get_start(res); 2928 pci_write_bar(dev, pm, start); 2929 } 2930 return (barlen); 2931 } 2932 2933 /* 2934 * For ATA devices we need to decide early what addressing mode to use. 2935 * Legacy demands that the primary and secondary ATA ports sits on the 2936 * same addresses that old ISA hardware did. This dictates that we use 2937 * those addresses and ignore the BAR's if we cannot set PCI native 2938 * addressing mode. 2939 */ 2940 static void 2941 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, 2942 uint32_t prefetchmask) 2943 { 2944 struct resource *r; 2945 int rid, type, progif; 2946 #if 0 2947 /* if this device supports PCI native addressing use it */ 2948 progif = pci_read_config(dev, PCIR_PROGIF, 1); 2949 if ((progif & 0x8a) == 0x8a) { 2950 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 2951 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 2952 printf("Trying ATA native PCI addressing mode\n"); 2953 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 2954 } 2955 } 2956 #endif 2957 progif = pci_read_config(dev, PCIR_PROGIF, 1); 2958 type = SYS_RES_IOPORT; 2959 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 2960 pci_add_map(bus, dev, PCIR_BAR(0), rl, force, 2961 prefetchmask & (1 << 0)); 2962 pci_add_map(bus, dev, PCIR_BAR(1), rl, force, 2963 prefetchmask & (1 << 1)); 2964 } else { 2965 rid = PCIR_BAR(0); 2966 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 2967 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0, 2968 0x1f7, 8, 0); 2969 rid = PCIR_BAR(1); 2970 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 2971 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6, 2972 0x3f6, 1, 0); 2973 } 2974 if (progif & PCIP_STORAGE_IDE_MODESEC) { 2975 pci_add_map(bus, dev, PCIR_BAR(2), rl, force, 2976 prefetchmask & (1 << 2)); 2977 pci_add_map(bus, dev, PCIR_BAR(3), rl, force, 2978 prefetchmask & (1 << 3)); 2979 } else { 2980 rid = PCIR_BAR(2); 2981 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 2982 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x170, 2983 0x177, 8, 0); 2984 rid = PCIR_BAR(3); 2985 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 2986 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x376, 2987 0x376, 1, 0); 2988 } 2989 pci_add_map(bus, dev, PCIR_BAR(4), rl, force, 2990 prefetchmask & (1 << 4)); 2991 pci_add_map(bus, dev, PCIR_BAR(5), rl, force, 2992 prefetchmask & (1 << 5)); 2993 } 2994 2995 static void 2996 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 2997 { 2998 struct pci_devinfo *dinfo = device_get_ivars(dev); 2999 pcicfgregs *cfg = &dinfo->cfg; 3000 char tunable_name[64]; 3001 int irq; 3002 3003 /* Has to have an intpin to have an interrupt. */ 3004 if (cfg->intpin == 0) 3005 return; 3006 3007 /* Let the user override the IRQ with a tunable. */ 3008 irq = PCI_INVALID_IRQ; 3009 snprintf(tunable_name, sizeof(tunable_name), 3010 "hw.pci%d.%d.%d.INT%c.irq", 3011 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 3012 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 3013 irq = PCI_INVALID_IRQ; 3014 3015 /* 3016 * If we didn't get an IRQ via the tunable, then we either use the 3017 * IRQ value in the intline register or we ask the bus to route an 3018 * interrupt for us. If force_route is true, then we only use the 3019 * value in the intline register if the bus was unable to assign an 3020 * IRQ. 3021 */ 3022 if (!PCI_INTERRUPT_VALID(irq)) { 3023 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 3024 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 3025 if (!PCI_INTERRUPT_VALID(irq)) 3026 irq = cfg->intline; 3027 } 3028 3029 /* If after all that we don't have an IRQ, just bail. */ 3030 if (!PCI_INTERRUPT_VALID(irq)) 3031 return; 3032 3033 /* Update the config register if it changed. */ 3034 if (irq != cfg->intline) { 3035 cfg->intline = irq; 3036 pci_write_config(dev, PCIR_INTLINE, irq, 1); 3037 } 3038 3039 /* Add this IRQ as rid 0 interrupt resource. */ 3040 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 3041 } 3042 3043 /* Perform early OHCI takeover from SMM. */ 3044 static void 3045 ohci_early_takeover(device_t self) 3046 { 3047 struct resource *res; 3048 uint32_t ctl; 3049 int rid; 3050 int i; 3051 3052 rid = PCIR_BAR(0); 3053 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3054 if (res == NULL) 3055 return; 3056 3057 ctl = bus_read_4(res, OHCI_CONTROL); 3058 if (ctl & OHCI_IR) { 3059 if (bootverbose) 3060 printf("ohci early: " 3061 "SMM active, request owner change\n"); 3062 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR); 3063 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 3064 DELAY(1000); 3065 ctl = bus_read_4(res, OHCI_CONTROL); 3066 } 3067 if (ctl & OHCI_IR) { 3068 if (bootverbose) 3069 printf("ohci early: " 3070 "SMM does not respond, resetting\n"); 3071 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET); 3072 } 3073 /* Disable interrupts */ 3074 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 3075 } 3076 3077 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3078 } 3079 3080 /* Perform early UHCI takeover from SMM. */ 3081 static void 3082 uhci_early_takeover(device_t self) 3083 { 3084 struct resource *res; 3085 int rid; 3086 3087 /* 3088 * Set the PIRQD enable bit and switch off all the others. We don't 3089 * want legacy support to interfere with us XXX Does this also mean 3090 * that the BIOS won't touch the keyboard anymore if it is connected 3091 * to the ports of the root hub? 3092 */ 3093 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2); 3094 3095 /* Disable interrupts */ 3096 rid = PCI_UHCI_BASE_REG; 3097 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE); 3098 if (res != NULL) { 3099 bus_write_2(res, UHCI_INTR, 0); 3100 bus_release_resource(self, SYS_RES_IOPORT, rid, res); 3101 } 3102 } 3103 3104 /* Perform early EHCI takeover from SMM. */ 3105 static void 3106 ehci_early_takeover(device_t self) 3107 { 3108 struct resource *res; 3109 uint32_t cparams; 3110 uint32_t eec; 3111 uint8_t eecp; 3112 uint8_t bios_sem; 3113 uint8_t offs; 3114 int rid; 3115 int i; 3116 3117 rid = PCIR_BAR(0); 3118 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3119 if (res == NULL) 3120 return; 3121 3122 cparams = bus_read_4(res, EHCI_HCCPARAMS); 3123 3124 /* Synchronise with the BIOS if it owns the controller. */ 3125 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0; 3126 eecp = EHCI_EECP_NEXT(eec)) { 3127 eec = pci_read_config(self, eecp, 4); 3128 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) { 3129 continue; 3130 } 3131 bios_sem = pci_read_config(self, eecp + 3132 EHCI_LEGSUP_BIOS_SEM, 1); 3133 if (bios_sem == 0) { 3134 continue; 3135 } 3136 if (bootverbose) 3137 printf("ehci early: " 3138 "SMM active, request owner change\n"); 3139 3140 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1); 3141 3142 for (i = 0; (i < 100) && (bios_sem != 0); i++) { 3143 DELAY(1000); 3144 bios_sem = pci_read_config(self, eecp + 3145 EHCI_LEGSUP_BIOS_SEM, 1); 3146 } 3147 3148 if (bios_sem != 0) { 3149 if (bootverbose) 3150 printf("ehci early: " 3151 "SMM does not respond\n"); 3152 } 3153 /* Disable interrupts */ 3154 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION)); 3155 bus_write_4(res, offs + EHCI_USBINTR, 0); 3156 } 3157 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3158 } 3159 3160 /* Perform early XHCI takeover from SMM. */ 3161 static void 3162 xhci_early_takeover(device_t self) 3163 { 3164 struct resource *res; 3165 uint32_t cparams; 3166 uint32_t eec; 3167 uint8_t eecp; 3168 uint8_t bios_sem; 3169 uint8_t offs; 3170 int rid; 3171 int i; 3172 3173 rid = PCIR_BAR(0); 3174 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3175 if (res == NULL) 3176 return; 3177 3178 cparams = bus_read_4(res, XHCI_HCSPARAMS0); 3179 3180 eec = -1; 3181 3182 /* Synchronise with the BIOS if it owns the controller. */ 3183 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 3184 eecp += XHCI_XECP_NEXT(eec) << 2) { 3185 eec = bus_read_4(res, eecp); 3186 3187 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 3188 continue; 3189 3190 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM); 3191 if (bios_sem == 0) 3192 continue; 3193 3194 if (bootverbose) 3195 printf("xhci early: " 3196 "SMM active, request owner change\n"); 3197 3198 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1); 3199 3200 /* wait a maximum of 5 second */ 3201 3202 for (i = 0; (i < 5000) && (bios_sem != 0); i++) { 3203 DELAY(1000); 3204 bios_sem = bus_read_1(res, eecp + 3205 XHCI_XECP_BIOS_SEM); 3206 } 3207 3208 if (bios_sem != 0) { 3209 if (bootverbose) 3210 printf("xhci early: " 3211 "SMM does not respond\n"); 3212 } 3213 3214 /* Disable interrupts */ 3215 offs = bus_read_1(res, XHCI_CAPLENGTH); 3216 bus_write_4(res, offs + XHCI_USBCMD, 0); 3217 bus_read_4(res, offs + XHCI_USBSTS); 3218 } 3219 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3220 } 3221 3222 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 3223 static void 3224 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg, 3225 struct resource_list *rl) 3226 { 3227 struct resource *res; 3228 char *cp; 3229 u_long start, end, count; 3230 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus; 3231 3232 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3233 case PCIM_HDRTYPE_BRIDGE: 3234 sec_reg = PCIR_SECBUS_1; 3235 sub_reg = PCIR_SUBBUS_1; 3236 break; 3237 case PCIM_HDRTYPE_CARDBUS: 3238 sec_reg = PCIR_SECBUS_2; 3239 sub_reg = PCIR_SUBBUS_2; 3240 break; 3241 default: 3242 return; 3243 } 3244 3245 /* 3246 * If the existing bus range is valid, attempt to reserve it 3247 * from our parent. If this fails for any reason, clear the 3248 * secbus and subbus registers. 3249 * 3250 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus? 3251 * This would at least preserve the existing sec_bus if it is 3252 * valid. 3253 */ 3254 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1); 3255 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1); 3256 3257 /* Quirk handling. */ 3258 switch (pci_get_devid(dev)) { 3259 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 3260 sup_bus = pci_read_config(dev, 0x41, 1); 3261 if (sup_bus != 0xff) { 3262 sec_bus = sup_bus + 1; 3263 sub_bus = sup_bus + 1; 3264 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1); 3265 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3266 } 3267 break; 3268 3269 case 0x00dd10de: 3270 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 3271 if ((cp = getenv("smbios.planar.maker")) == NULL) 3272 break; 3273 if (strncmp(cp, "Compal", 6) != 0) { 3274 freeenv(cp); 3275 break; 3276 } 3277 freeenv(cp); 3278 if ((cp = getenv("smbios.planar.product")) == NULL) 3279 break; 3280 if (strncmp(cp, "08A0", 4) != 0) { 3281 freeenv(cp); 3282 break; 3283 } 3284 freeenv(cp); 3285 if (sub_bus < 0xa) { 3286 sub_bus = 0xa; 3287 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3288 } 3289 break; 3290 } 3291 3292 if (bootverbose) 3293 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus); 3294 if (sec_bus > 0 && sub_bus >= sec_bus) { 3295 start = sec_bus; 3296 end = sub_bus; 3297 count = end - start + 1; 3298 3299 resource_list_add(rl, PCI_RES_BUS, 0, 0ul, ~0ul, count); 3300 3301 /* 3302 * If requested, clear secondary bus registers in 3303 * bridge devices to force a complete renumbering 3304 * rather than reserving the existing range. However, 3305 * preserve the existing size. 3306 */ 3307 if (pci_clear_buses) 3308 goto clear; 3309 3310 rid = 0; 3311 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid, 3312 start, end, count, 0); 3313 if (res != NULL) 3314 return; 3315 3316 if (bootverbose) 3317 device_printf(bus, 3318 "pci%d:%d:%d:%d secbus failed to allocate\n", 3319 pci_get_domain(dev), pci_get_bus(dev), 3320 pci_get_slot(dev), pci_get_function(dev)); 3321 } 3322 3323 clear: 3324 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1); 3325 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1); 3326 } 3327 3328 static struct resource * 3329 pci_alloc_secbus(device_t dev, device_t child, int *rid, u_long start, 3330 u_long end, u_long count, u_int flags) 3331 { 3332 struct pci_devinfo *dinfo; 3333 pcicfgregs *cfg; 3334 struct resource_list *rl; 3335 struct resource *res; 3336 int sec_reg, sub_reg; 3337 3338 dinfo = device_get_ivars(child); 3339 cfg = &dinfo->cfg; 3340 rl = &dinfo->resources; 3341 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3342 case PCIM_HDRTYPE_BRIDGE: 3343 sec_reg = PCIR_SECBUS_1; 3344 sub_reg = PCIR_SUBBUS_1; 3345 break; 3346 case PCIM_HDRTYPE_CARDBUS: 3347 sec_reg = PCIR_SECBUS_2; 3348 sub_reg = PCIR_SUBBUS_2; 3349 break; 3350 default: 3351 return (NULL); 3352 } 3353 3354 if (*rid != 0) 3355 return (NULL); 3356 3357 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL) 3358 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count); 3359 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) { 3360 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid, 3361 start, end, count, flags & ~RF_ACTIVE); 3362 if (res == NULL) { 3363 resource_list_delete(rl, PCI_RES_BUS, *rid); 3364 device_printf(child, "allocating %lu bus%s failed\n", 3365 count, count == 1 ? "" : "es"); 3366 return (NULL); 3367 } 3368 if (bootverbose) 3369 device_printf(child, 3370 "Lazy allocation of %lu bus%s at %lu\n", count, 3371 count == 1 ? "" : "es", rman_get_start(res)); 3372 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1); 3373 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1); 3374 } 3375 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start, 3376 end, count, flags)); 3377 } 3378 #endif 3379 3380 void 3381 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 3382 { 3383 struct pci_devinfo *dinfo; 3384 pcicfgregs *cfg; 3385 struct resource_list *rl; 3386 const struct pci_quirk *q; 3387 uint32_t devid; 3388 int i; 3389 3390 dinfo = device_get_ivars(dev); 3391 cfg = &dinfo->cfg; 3392 rl = &dinfo->resources; 3393 devid = (cfg->device << 16) | cfg->vendor; 3394 3395 /* ATA devices needs special map treatment */ 3396 if ((pci_get_class(dev) == PCIC_STORAGE) && 3397 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 3398 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 3399 (!pci_read_config(dev, PCIR_BAR(0), 4) && 3400 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 3401 pci_ata_maps(bus, dev, rl, force, prefetchmask); 3402 else 3403 for (i = 0; i < cfg->nummaps;) { 3404 /* 3405 * Skip quirked resources. 3406 */ 3407 for (q = &pci_quirks[0]; q->devid != 0; q++) 3408 if (q->devid == devid && 3409 q->type == PCI_QUIRK_UNMAP_REG && 3410 q->arg1 == PCIR_BAR(i)) 3411 break; 3412 if (q->devid != 0) { 3413 i++; 3414 continue; 3415 } 3416 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force, 3417 prefetchmask & (1 << i)); 3418 } 3419 3420 /* 3421 * Add additional, quirked resources. 3422 */ 3423 for (q = &pci_quirks[0]; q->devid != 0; q++) 3424 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) 3425 pci_add_map(bus, dev, q->arg1, rl, force, 0); 3426 3427 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 3428 #ifdef __PCI_REROUTE_INTERRUPT 3429 /* 3430 * Try to re-route interrupts. Sometimes the BIOS or 3431 * firmware may leave bogus values in these registers. 3432 * If the re-route fails, then just stick with what we 3433 * have. 3434 */ 3435 pci_assign_interrupt(bus, dev, 1); 3436 #else 3437 pci_assign_interrupt(bus, dev, 0); 3438 #endif 3439 } 3440 3441 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS && 3442 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) { 3443 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI) 3444 xhci_early_takeover(dev); 3445 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI) 3446 ehci_early_takeover(dev); 3447 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI) 3448 ohci_early_takeover(dev); 3449 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI) 3450 uhci_early_takeover(dev); 3451 } 3452 3453 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 3454 /* 3455 * Reserve resources for secondary bus ranges behind bridge 3456 * devices. 3457 */ 3458 pci_reserve_secbus(bus, dev, cfg, rl); 3459 #endif 3460 } 3461 3462 static struct pci_devinfo * 3463 pci_identify_function(device_t pcib, device_t dev, int domain, int busno, 3464 int slot, int func, size_t dinfo_size) 3465 { 3466 struct pci_devinfo *dinfo; 3467 3468 dinfo = pci_read_device(pcib, domain, busno, slot, func, dinfo_size); 3469 if (dinfo != NULL) 3470 pci_add_child(dev, dinfo); 3471 3472 return (dinfo); 3473 } 3474 3475 void 3476 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size) 3477 { 3478 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 3479 device_t pcib = device_get_parent(dev); 3480 struct pci_devinfo *dinfo; 3481 int maxslots; 3482 int s, f, pcifunchigh; 3483 uint8_t hdrtype; 3484 int first_func; 3485 3486 /* 3487 * Try to detect a device at slot 0, function 0. If it exists, try to 3488 * enable ARI. We must enable ARI before detecting the rest of the 3489 * functions on this bus as ARI changes the set of slots and functions 3490 * that are legal on this bus. 3491 */ 3492 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0, 3493 dinfo_size); 3494 if (dinfo != NULL && pci_enable_ari) 3495 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); 3496 3497 /* 3498 * Start looking for new devices on slot 0 at function 1 because we 3499 * just identified the device at slot 0, function 0. 3500 */ 3501 first_func = 1; 3502 3503 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 3504 ("dinfo_size too small")); 3505 maxslots = PCIB_MAXSLOTS(pcib); 3506 for (s = 0; s <= maxslots; s++, first_func = 0) { 3507 pcifunchigh = 0; 3508 f = 0; 3509 DELAY(1); 3510 hdrtype = REG(PCIR_HDRTYPE, 1); 3511 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 3512 continue; 3513 if (hdrtype & PCIM_MFDEV) 3514 pcifunchigh = PCIB_MAXFUNCS(pcib); 3515 for (f = first_func; f <= pcifunchigh; f++) 3516 pci_identify_function(pcib, dev, domain, busno, s, f, 3517 dinfo_size); 3518 } 3519 #undef REG 3520 } 3521 3522 void 3523 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 3524 { 3525 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 3526 device_set_ivars(dinfo->cfg.dev, dinfo); 3527 resource_list_init(&dinfo->resources); 3528 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 3529 pci_cfg_restore(dinfo->cfg.dev, dinfo); 3530 pci_print_verbose(dinfo); 3531 pci_add_resources(bus, dinfo->cfg.dev, 0, 0); 3532 } 3533 3534 static int 3535 pci_probe(device_t dev) 3536 { 3537 3538 device_set_desc(dev, "PCI bus"); 3539 3540 /* Allow other subclasses to override this driver. */ 3541 return (BUS_PROBE_GENERIC); 3542 } 3543 3544 int 3545 pci_attach_common(device_t dev) 3546 { 3547 struct pci_softc *sc; 3548 int busno, domain; 3549 #ifdef PCI_DMA_BOUNDARY 3550 int error, tag_valid; 3551 #endif 3552 #ifdef PCI_RES_BUS 3553 int rid; 3554 #endif 3555 3556 sc = device_get_softc(dev); 3557 domain = pcib_get_domain(dev); 3558 busno = pcib_get_bus(dev); 3559 #ifdef PCI_RES_BUS 3560 rid = 0; 3561 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, 3562 1, 0); 3563 if (sc->sc_bus == NULL) { 3564 device_printf(dev, "failed to allocate bus number\n"); 3565 return (ENXIO); 3566 } 3567 #endif 3568 if (bootverbose) 3569 device_printf(dev, "domain=%d, physical bus=%d\n", 3570 domain, busno); 3571 #ifdef PCI_DMA_BOUNDARY 3572 tag_valid = 0; 3573 if (device_get_devclass(device_get_parent(device_get_parent(dev))) != 3574 devclass_find("pci")) { 3575 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 3576 PCI_DMA_BOUNDARY, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3577 NULL, NULL, BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, 3578 BUS_SPACE_MAXSIZE, 0, NULL, NULL, &sc->sc_dma_tag); 3579 if (error) 3580 device_printf(dev, "Failed to create DMA tag: %d\n", 3581 error); 3582 else 3583 tag_valid = 1; 3584 } 3585 if (!tag_valid) 3586 #endif 3587 sc->sc_dma_tag = bus_get_dma_tag(dev); 3588 return (0); 3589 } 3590 3591 static int 3592 pci_attach(device_t dev) 3593 { 3594 int busno, domain, error; 3595 3596 error = pci_attach_common(dev); 3597 if (error) 3598 return (error); 3599 3600 /* 3601 * Since there can be multiple independantly numbered PCI 3602 * busses on systems with multiple PCI domains, we can't use 3603 * the unit number to decide which bus we are probing. We ask 3604 * the parent pcib what our domain and bus numbers are. 3605 */ 3606 domain = pcib_get_domain(dev); 3607 busno = pcib_get_bus(dev); 3608 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo)); 3609 return (bus_generic_attach(dev)); 3610 } 3611 3612 #ifdef PCI_RES_BUS 3613 static int 3614 pci_detach(device_t dev) 3615 { 3616 struct pci_softc *sc; 3617 int error; 3618 3619 error = bus_generic_detach(dev); 3620 if (error) 3621 return (error); 3622 sc = device_get_softc(dev); 3623 return (bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus)); 3624 } 3625 #endif 3626 3627 static void 3628 pci_set_power_children(device_t dev, device_t *devlist, int numdevs, 3629 int state) 3630 { 3631 device_t child, pcib; 3632 struct pci_devinfo *dinfo; 3633 int dstate, i; 3634 3635 /* 3636 * Set the device to the given state. If the firmware suggests 3637 * a different power state, use it instead. If power management 3638 * is not present, the firmware is responsible for managing 3639 * device power. Skip children who aren't attached since they 3640 * are handled separately. 3641 */ 3642 pcib = device_get_parent(dev); 3643 for (i = 0; i < numdevs; i++) { 3644 child = devlist[i]; 3645 dinfo = device_get_ivars(child); 3646 dstate = state; 3647 if (device_is_attached(child) && 3648 PCIB_POWER_FOR_SLEEP(pcib, dev, &dstate) == 0) 3649 pci_set_powerstate(child, dstate); 3650 } 3651 } 3652 3653 int 3654 pci_suspend(device_t dev) 3655 { 3656 device_t child, *devlist; 3657 struct pci_devinfo *dinfo; 3658 int error, i, numdevs; 3659 3660 /* 3661 * Save the PCI configuration space for each child and set the 3662 * device in the appropriate power state for this sleep state. 3663 */ 3664 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 3665 return (error); 3666 for (i = 0; i < numdevs; i++) { 3667 child = devlist[i]; 3668 dinfo = device_get_ivars(child); 3669 pci_cfg_save(child, dinfo, 0); 3670 } 3671 3672 /* Suspend devices before potentially powering them down. */ 3673 error = bus_generic_suspend(dev); 3674 if (error) { 3675 free(devlist, M_TEMP); 3676 return (error); 3677 } 3678 if (pci_do_power_suspend) 3679 pci_set_power_children(dev, devlist, numdevs, 3680 PCI_POWERSTATE_D3); 3681 free(devlist, M_TEMP); 3682 return (0); 3683 } 3684 3685 int 3686 pci_resume(device_t dev) 3687 { 3688 device_t child, *devlist; 3689 struct pci_devinfo *dinfo; 3690 int error, i, numdevs; 3691 3692 /* 3693 * Set each child to D0 and restore its PCI configuration space. 3694 */ 3695 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 3696 return (error); 3697 if (pci_do_power_resume) 3698 pci_set_power_children(dev, devlist, numdevs, 3699 PCI_POWERSTATE_D0); 3700 3701 /* Now the device is powered up, restore its config space. */ 3702 for (i = 0; i < numdevs; i++) { 3703 child = devlist[i]; 3704 dinfo = device_get_ivars(child); 3705 3706 pci_cfg_restore(child, dinfo); 3707 if (!device_is_attached(child)) 3708 pci_cfg_save(child, dinfo, 1); 3709 } 3710 3711 /* 3712 * Resume critical devices first, then everything else later. 3713 */ 3714 for (i = 0; i < numdevs; i++) { 3715 child = devlist[i]; 3716 switch (pci_get_class(child)) { 3717 case PCIC_DISPLAY: 3718 case PCIC_MEMORY: 3719 case PCIC_BRIDGE: 3720 case PCIC_BASEPERIPH: 3721 DEVICE_RESUME(child); 3722 break; 3723 } 3724 } 3725 for (i = 0; i < numdevs; i++) { 3726 child = devlist[i]; 3727 switch (pci_get_class(child)) { 3728 case PCIC_DISPLAY: 3729 case PCIC_MEMORY: 3730 case PCIC_BRIDGE: 3731 case PCIC_BASEPERIPH: 3732 break; 3733 default: 3734 DEVICE_RESUME(child); 3735 } 3736 } 3737 free(devlist, M_TEMP); 3738 return (0); 3739 } 3740 3741 static void 3742 pci_load_vendor_data(void) 3743 { 3744 caddr_t data; 3745 void *ptr; 3746 size_t sz; 3747 3748 data = preload_search_by_type("pci_vendor_data"); 3749 if (data != NULL) { 3750 ptr = preload_fetch_addr(data); 3751 sz = preload_fetch_size(data); 3752 if (ptr != NULL && sz != 0) { 3753 pci_vendordata = ptr; 3754 pci_vendordata_size = sz; 3755 /* terminate the database */ 3756 pci_vendordata[pci_vendordata_size] = '\n'; 3757 } 3758 } 3759 } 3760 3761 void 3762 pci_driver_added(device_t dev, driver_t *driver) 3763 { 3764 int numdevs; 3765 device_t *devlist; 3766 device_t child; 3767 struct pci_devinfo *dinfo; 3768 int i; 3769 3770 if (bootverbose) 3771 device_printf(dev, "driver added\n"); 3772 DEVICE_IDENTIFY(driver, dev); 3773 if (device_get_children(dev, &devlist, &numdevs) != 0) 3774 return; 3775 for (i = 0; i < numdevs; i++) { 3776 child = devlist[i]; 3777 if (device_get_state(child) != DS_NOTPRESENT) 3778 continue; 3779 dinfo = device_get_ivars(child); 3780 pci_print_verbose(dinfo); 3781 if (bootverbose) 3782 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); 3783 pci_cfg_restore(child, dinfo); 3784 if (device_probe_and_attach(child) != 0) 3785 pci_child_detached(dev, child); 3786 } 3787 free(devlist, M_TEMP); 3788 } 3789 3790 int 3791 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, 3792 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep) 3793 { 3794 struct pci_devinfo *dinfo; 3795 struct msix_table_entry *mte; 3796 struct msix_vector *mv; 3797 uint64_t addr; 3798 uint32_t data; 3799 void *cookie; 3800 int error, rid; 3801 3802 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr, 3803 arg, &cookie); 3804 if (error) 3805 return (error); 3806 3807 /* If this is not a direct child, just bail out. */ 3808 if (device_get_parent(child) != dev) { 3809 *cookiep = cookie; 3810 return(0); 3811 } 3812 3813 rid = rman_get_rid(irq); 3814 if (rid == 0) { 3815 /* Make sure that INTx is enabled */ 3816 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 3817 } else { 3818 /* 3819 * Check to see if the interrupt is MSI or MSI-X. 3820 * Ask our parent to map the MSI and give 3821 * us the address and data register values. 3822 * If we fail for some reason, teardown the 3823 * interrupt handler. 3824 */ 3825 dinfo = device_get_ivars(child); 3826 if (dinfo->cfg.msi.msi_alloc > 0) { 3827 if (dinfo->cfg.msi.msi_addr == 0) { 3828 KASSERT(dinfo->cfg.msi.msi_handlers == 0, 3829 ("MSI has handlers, but vectors not mapped")); 3830 error = PCIB_MAP_MSI(device_get_parent(dev), 3831 child, rman_get_start(irq), &addr, &data); 3832 if (error) 3833 goto bad; 3834 dinfo->cfg.msi.msi_addr = addr; 3835 dinfo->cfg.msi.msi_data = data; 3836 } 3837 if (dinfo->cfg.msi.msi_handlers == 0) 3838 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, 3839 dinfo->cfg.msi.msi_data); 3840 dinfo->cfg.msi.msi_handlers++; 3841 } else { 3842 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 3843 ("No MSI or MSI-X interrupts allocated")); 3844 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 3845 ("MSI-X index too high")); 3846 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 3847 KASSERT(mte->mte_vector != 0, ("no message vector")); 3848 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; 3849 KASSERT(mv->mv_irq == rman_get_start(irq), 3850 ("IRQ mismatch")); 3851 if (mv->mv_address == 0) { 3852 KASSERT(mte->mte_handlers == 0, 3853 ("MSI-X table entry has handlers, but vector not mapped")); 3854 error = PCIB_MAP_MSI(device_get_parent(dev), 3855 child, rman_get_start(irq), &addr, &data); 3856 if (error) 3857 goto bad; 3858 mv->mv_address = addr; 3859 mv->mv_data = data; 3860 } 3861 if (mte->mte_handlers == 0) { 3862 pci_enable_msix(child, rid - 1, mv->mv_address, 3863 mv->mv_data); 3864 pci_unmask_msix(child, rid - 1); 3865 } 3866 mte->mte_handlers++; 3867 } 3868 3869 /* Make sure that INTx is disabled if we are using MSI/MSIX */ 3870 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 3871 bad: 3872 if (error) { 3873 (void)bus_generic_teardown_intr(dev, child, irq, 3874 cookie); 3875 return (error); 3876 } 3877 } 3878 *cookiep = cookie; 3879 return (0); 3880 } 3881 3882 int 3883 pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 3884 void *cookie) 3885 { 3886 struct msix_table_entry *mte; 3887 struct resource_list_entry *rle; 3888 struct pci_devinfo *dinfo; 3889 int error, rid; 3890 3891 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE)) 3892 return (EINVAL); 3893 3894 /* If this isn't a direct child, just bail out */ 3895 if (device_get_parent(child) != dev) 3896 return(bus_generic_teardown_intr(dev, child, irq, cookie)); 3897 3898 rid = rman_get_rid(irq); 3899 if (rid == 0) { 3900 /* Mask INTx */ 3901 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 3902 } else { 3903 /* 3904 * Check to see if the interrupt is MSI or MSI-X. If so, 3905 * decrement the appropriate handlers count and mask the 3906 * MSI-X message, or disable MSI messages if the count 3907 * drops to 0. 3908 */ 3909 dinfo = device_get_ivars(child); 3910 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); 3911 if (rle->res != irq) 3912 return (EINVAL); 3913 if (dinfo->cfg.msi.msi_alloc > 0) { 3914 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, 3915 ("MSI-X index too high")); 3916 if (dinfo->cfg.msi.msi_handlers == 0) 3917 return (EINVAL); 3918 dinfo->cfg.msi.msi_handlers--; 3919 if (dinfo->cfg.msi.msi_handlers == 0) 3920 pci_disable_msi(child); 3921 } else { 3922 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 3923 ("No MSI or MSI-X interrupts allocated")); 3924 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 3925 ("MSI-X index too high")); 3926 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 3927 if (mte->mte_handlers == 0) 3928 return (EINVAL); 3929 mte->mte_handlers--; 3930 if (mte->mte_handlers == 0) 3931 pci_mask_msix(child, rid - 1); 3932 } 3933 } 3934 error = bus_generic_teardown_intr(dev, child, irq, cookie); 3935 if (rid > 0) 3936 KASSERT(error == 0, 3937 ("%s: generic teardown failed for MSI/MSI-X", __func__)); 3938 return (error); 3939 } 3940 3941 int 3942 pci_print_child(device_t dev, device_t child) 3943 { 3944 struct pci_devinfo *dinfo; 3945 struct resource_list *rl; 3946 int retval = 0; 3947 3948 dinfo = device_get_ivars(child); 3949 rl = &dinfo->resources; 3950 3951 retval += bus_print_child_header(dev, child); 3952 3953 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 3954 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 3955 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 3956 if (device_get_flags(dev)) 3957 retval += printf(" flags %#x", device_get_flags(dev)); 3958 3959 retval += printf(" at device %d.%d", pci_get_slot(child), 3960 pci_get_function(child)); 3961 3962 retval += bus_print_child_footer(dev, child); 3963 3964 return (retval); 3965 } 3966 3967 static const struct 3968 { 3969 int class; 3970 int subclass; 3971 int report; /* 0 = bootverbose, 1 = always */ 3972 const char *desc; 3973 } pci_nomatch_tab[] = { 3974 {PCIC_OLD, -1, 1, "old"}, 3975 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"}, 3976 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"}, 3977 {PCIC_STORAGE, -1, 1, "mass storage"}, 3978 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"}, 3979 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"}, 3980 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"}, 3981 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"}, 3982 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"}, 3983 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"}, 3984 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"}, 3985 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"}, 3986 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"}, 3987 {PCIC_NETWORK, -1, 1, "network"}, 3988 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"}, 3989 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"}, 3990 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"}, 3991 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"}, 3992 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"}, 3993 {PCIC_DISPLAY, -1, 1, "display"}, 3994 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"}, 3995 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"}, 3996 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"}, 3997 {PCIC_MULTIMEDIA, -1, 1, "multimedia"}, 3998 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"}, 3999 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"}, 4000 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"}, 4001 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"}, 4002 {PCIC_MEMORY, -1, 1, "memory"}, 4003 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"}, 4004 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"}, 4005 {PCIC_BRIDGE, -1, 1, "bridge"}, 4006 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"}, 4007 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"}, 4008 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"}, 4009 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"}, 4010 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"}, 4011 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"}, 4012 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"}, 4013 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"}, 4014 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"}, 4015 {PCIC_SIMPLECOMM, -1, 1, "simple comms"}, 4016 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */ 4017 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"}, 4018 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"}, 4019 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"}, 4020 {PCIC_BASEPERIPH, -1, 0, "base peripheral"}, 4021 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"}, 4022 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"}, 4023 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"}, 4024 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"}, 4025 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"}, 4026 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"}, 4027 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"}, 4028 {PCIC_INPUTDEV, -1, 1, "input device"}, 4029 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"}, 4030 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"}, 4031 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"}, 4032 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"}, 4033 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"}, 4034 {PCIC_DOCKING, -1, 1, "docking station"}, 4035 {PCIC_PROCESSOR, -1, 1, "processor"}, 4036 {PCIC_SERIALBUS, -1, 1, "serial bus"}, 4037 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"}, 4038 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"}, 4039 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"}, 4040 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"}, 4041 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"}, 4042 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"}, 4043 {PCIC_WIRELESS, -1, 1, "wireless controller"}, 4044 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"}, 4045 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"}, 4046 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"}, 4047 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"}, 4048 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"}, 4049 {PCIC_SATCOM, -1, 1, "satellite communication"}, 4050 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"}, 4051 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"}, 4052 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"}, 4053 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"}, 4054 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"}, 4055 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"}, 4056 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"}, 4057 {PCIC_DASP, -1, 0, "dasp"}, 4058 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"}, 4059 {0, 0, 0, NULL} 4060 }; 4061 4062 void 4063 pci_probe_nomatch(device_t dev, device_t child) 4064 { 4065 int i, report; 4066 const char *cp, *scp; 4067 char *device; 4068 4069 /* 4070 * Look for a listing for this device in a loaded device database. 4071 */ 4072 report = 1; 4073 if ((device = pci_describe_device(child)) != NULL) { 4074 device_printf(dev, "<%s>", device); 4075 free(device, M_DEVBUF); 4076 } else { 4077 /* 4078 * Scan the class/subclass descriptions for a general 4079 * description. 4080 */ 4081 cp = "unknown"; 4082 scp = NULL; 4083 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 4084 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 4085 if (pci_nomatch_tab[i].subclass == -1) { 4086 cp = pci_nomatch_tab[i].desc; 4087 report = pci_nomatch_tab[i].report; 4088 } else if (pci_nomatch_tab[i].subclass == 4089 pci_get_subclass(child)) { 4090 scp = pci_nomatch_tab[i].desc; 4091 report = pci_nomatch_tab[i].report; 4092 } 4093 } 4094 } 4095 if (report || bootverbose) { 4096 device_printf(dev, "<%s%s%s>", 4097 cp ? cp : "", 4098 ((cp != NULL) && (scp != NULL)) ? ", " : "", 4099 scp ? scp : ""); 4100 } 4101 } 4102 if (report || bootverbose) { 4103 printf(" at device %d.%d (no driver attached)\n", 4104 pci_get_slot(child), pci_get_function(child)); 4105 } 4106 pci_cfg_save(child, device_get_ivars(child), 1); 4107 } 4108 4109 void 4110 pci_child_detached(device_t dev, device_t child) 4111 { 4112 struct pci_devinfo *dinfo; 4113 struct resource_list *rl; 4114 4115 dinfo = device_get_ivars(child); 4116 rl = &dinfo->resources; 4117 4118 /* 4119 * Have to deallocate IRQs before releasing any MSI messages and 4120 * have to release MSI messages before deallocating any memory 4121 * BARs. 4122 */ 4123 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0) 4124 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); 4125 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { 4126 pci_printf(&dinfo->cfg, "Device leaked MSI vectors\n"); 4127 (void)pci_release_msi(child); 4128 } 4129 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0) 4130 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); 4131 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0) 4132 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); 4133 #ifdef PCI_RES_BUS 4134 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0) 4135 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); 4136 #endif 4137 4138 pci_cfg_save(child, dinfo, 1); 4139 } 4140 4141 /* 4142 * Parse the PCI device database, if loaded, and return a pointer to a 4143 * description of the device. 4144 * 4145 * The database is flat text formatted as follows: 4146 * 4147 * Any line not in a valid format is ignored. 4148 * Lines are terminated with newline '\n' characters. 4149 * 4150 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 4151 * the vendor name. 4152 * 4153 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 4154 * - devices cannot be listed without a corresponding VENDOR line. 4155 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 4156 * another TAB, then the device name. 4157 */ 4158 4159 /* 4160 * Assuming (ptr) points to the beginning of a line in the database, 4161 * return the vendor or device and description of the next entry. 4162 * The value of (vendor) or (device) inappropriate for the entry type 4163 * is set to -1. Returns nonzero at the end of the database. 4164 * 4165 * Note that this is slightly unrobust in the face of corrupt data; 4166 * we attempt to safeguard against this by spamming the end of the 4167 * database with a newline when we initialise. 4168 */ 4169 static int 4170 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 4171 { 4172 char *cp = *ptr; 4173 int left; 4174 4175 *device = -1; 4176 *vendor = -1; 4177 **desc = '\0'; 4178 for (;;) { 4179 left = pci_vendordata_size - (cp - pci_vendordata); 4180 if (left <= 0) { 4181 *ptr = cp; 4182 return(1); 4183 } 4184 4185 /* vendor entry? */ 4186 if (*cp != '\t' && 4187 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 4188 break; 4189 /* device entry? */ 4190 if (*cp == '\t' && 4191 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 4192 break; 4193 4194 /* skip to next line */ 4195 while (*cp != '\n' && left > 0) { 4196 cp++; 4197 left--; 4198 } 4199 if (*cp == '\n') { 4200 cp++; 4201 left--; 4202 } 4203 } 4204 /* skip to next line */ 4205 while (*cp != '\n' && left > 0) { 4206 cp++; 4207 left--; 4208 } 4209 if (*cp == '\n' && left > 0) 4210 cp++; 4211 *ptr = cp; 4212 return(0); 4213 } 4214 4215 static char * 4216 pci_describe_device(device_t dev) 4217 { 4218 int vendor, device; 4219 char *desc, *vp, *dp, *line; 4220 4221 desc = vp = dp = NULL; 4222 4223 /* 4224 * If we have no vendor data, we can't do anything. 4225 */ 4226 if (pci_vendordata == NULL) 4227 goto out; 4228 4229 /* 4230 * Scan the vendor data looking for this device 4231 */ 4232 line = pci_vendordata; 4233 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 4234 goto out; 4235 for (;;) { 4236 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 4237 goto out; 4238 if (vendor == pci_get_vendor(dev)) 4239 break; 4240 } 4241 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 4242 goto out; 4243 for (;;) { 4244 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 4245 *dp = 0; 4246 break; 4247 } 4248 if (vendor != -1) { 4249 *dp = 0; 4250 break; 4251 } 4252 if (device == pci_get_device(dev)) 4253 break; 4254 } 4255 if (dp[0] == '\0') 4256 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 4257 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 4258 NULL) 4259 sprintf(desc, "%s, %s", vp, dp); 4260 out: 4261 if (vp != NULL) 4262 free(vp, M_DEVBUF); 4263 if (dp != NULL) 4264 free(dp, M_DEVBUF); 4265 return(desc); 4266 } 4267 4268 int 4269 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 4270 { 4271 struct pci_devinfo *dinfo; 4272 pcicfgregs *cfg; 4273 4274 dinfo = device_get_ivars(child); 4275 cfg = &dinfo->cfg; 4276 4277 switch (which) { 4278 case PCI_IVAR_ETHADDR: 4279 /* 4280 * The generic accessor doesn't deal with failure, so 4281 * we set the return value, then return an error. 4282 */ 4283 *((uint8_t **) result) = NULL; 4284 return (EINVAL); 4285 case PCI_IVAR_SUBVENDOR: 4286 *result = cfg->subvendor; 4287 break; 4288 case PCI_IVAR_SUBDEVICE: 4289 *result = cfg->subdevice; 4290 break; 4291 case PCI_IVAR_VENDOR: 4292 *result = cfg->vendor; 4293 break; 4294 case PCI_IVAR_DEVICE: 4295 *result = cfg->device; 4296 break; 4297 case PCI_IVAR_DEVID: 4298 *result = (cfg->device << 16) | cfg->vendor; 4299 break; 4300 case PCI_IVAR_CLASS: 4301 *result = cfg->baseclass; 4302 break; 4303 case PCI_IVAR_SUBCLASS: 4304 *result = cfg->subclass; 4305 break; 4306 case PCI_IVAR_PROGIF: 4307 *result = cfg->progif; 4308 break; 4309 case PCI_IVAR_REVID: 4310 *result = cfg->revid; 4311 break; 4312 case PCI_IVAR_INTPIN: 4313 *result = cfg->intpin; 4314 break; 4315 case PCI_IVAR_IRQ: 4316 *result = cfg->intline; 4317 break; 4318 case PCI_IVAR_DOMAIN: 4319 *result = cfg->domain; 4320 break; 4321 case PCI_IVAR_BUS: 4322 *result = cfg->bus; 4323 break; 4324 case PCI_IVAR_SLOT: 4325 *result = cfg->slot; 4326 break; 4327 case PCI_IVAR_FUNCTION: 4328 *result = cfg->func; 4329 break; 4330 case PCI_IVAR_CMDREG: 4331 *result = cfg->cmdreg; 4332 break; 4333 case PCI_IVAR_CACHELNSZ: 4334 *result = cfg->cachelnsz; 4335 break; 4336 case PCI_IVAR_MINGNT: 4337 *result = cfg->mingnt; 4338 break; 4339 case PCI_IVAR_MAXLAT: 4340 *result = cfg->maxlat; 4341 break; 4342 case PCI_IVAR_LATTIMER: 4343 *result = cfg->lattimer; 4344 break; 4345 default: 4346 return (ENOENT); 4347 } 4348 return (0); 4349 } 4350 4351 int 4352 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 4353 { 4354 struct pci_devinfo *dinfo; 4355 4356 dinfo = device_get_ivars(child); 4357 4358 switch (which) { 4359 case PCI_IVAR_INTPIN: 4360 dinfo->cfg.intpin = value; 4361 return (0); 4362 case PCI_IVAR_ETHADDR: 4363 case PCI_IVAR_SUBVENDOR: 4364 case PCI_IVAR_SUBDEVICE: 4365 case PCI_IVAR_VENDOR: 4366 case PCI_IVAR_DEVICE: 4367 case PCI_IVAR_DEVID: 4368 case PCI_IVAR_CLASS: 4369 case PCI_IVAR_SUBCLASS: 4370 case PCI_IVAR_PROGIF: 4371 case PCI_IVAR_REVID: 4372 case PCI_IVAR_IRQ: 4373 case PCI_IVAR_DOMAIN: 4374 case PCI_IVAR_BUS: 4375 case PCI_IVAR_SLOT: 4376 case PCI_IVAR_FUNCTION: 4377 return (EINVAL); /* disallow for now */ 4378 4379 default: 4380 return (ENOENT); 4381 } 4382 } 4383 4384 #include "opt_ddb.h" 4385 #ifdef DDB 4386 #include <ddb/ddb.h> 4387 #include <sys/cons.h> 4388 4389 /* 4390 * List resources based on pci map registers, used for within ddb 4391 */ 4392 4393 DB_SHOW_COMMAND(pciregs, db_pci_dump) 4394 { 4395 struct pci_devinfo *dinfo; 4396 struct devlist *devlist_head; 4397 struct pci_conf *p; 4398 const char *name; 4399 int i, error, none_count; 4400 4401 none_count = 0; 4402 /* get the head of the device queue */ 4403 devlist_head = &pci_devq; 4404 4405 /* 4406 * Go through the list of devices and print out devices 4407 */ 4408 for (error = 0, i = 0, 4409 dinfo = STAILQ_FIRST(devlist_head); 4410 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 4411 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 4412 4413 /* Populate pd_name and pd_unit */ 4414 name = NULL; 4415 if (dinfo->cfg.dev) 4416 name = device_get_name(dinfo->cfg.dev); 4417 4418 p = &dinfo->conf; 4419 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x " 4420 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 4421 (name && *name) ? name : "none", 4422 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 4423 none_count++, 4424 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, 4425 p->pc_sel.pc_func, (p->pc_class << 16) | 4426 (p->pc_subclass << 8) | p->pc_progif, 4427 (p->pc_subdevice << 16) | p->pc_subvendor, 4428 (p->pc_device << 16) | p->pc_vendor, 4429 p->pc_revid, p->pc_hdr); 4430 } 4431 } 4432 #endif /* DDB */ 4433 4434 static struct resource * 4435 pci_reserve_map(device_t dev, device_t child, int type, int *rid, 4436 u_long start, u_long end, u_long count, u_int flags) 4437 { 4438 struct pci_devinfo *dinfo = device_get_ivars(child); 4439 struct resource_list *rl = &dinfo->resources; 4440 struct resource *res; 4441 struct pci_map *pm; 4442 pci_addr_t map, testval; 4443 int mapsize; 4444 4445 res = NULL; 4446 pm = pci_find_bar(child, *rid); 4447 if (pm != NULL) { 4448 /* This is a BAR that we failed to allocate earlier. */ 4449 mapsize = pm->pm_size; 4450 map = pm->pm_value; 4451 } else { 4452 /* 4453 * Weed out the bogons, and figure out how large the 4454 * BAR/map is. BARs that read back 0 here are bogus 4455 * and unimplemented. Note: atapci in legacy mode are 4456 * special and handled elsewhere in the code. If you 4457 * have a atapci device in legacy mode and it fails 4458 * here, that other code is broken. 4459 */ 4460 pci_read_bar(child, *rid, &map, &testval); 4461 4462 /* 4463 * Determine the size of the BAR and ignore BARs with a size 4464 * of 0. Device ROM BARs use a different mask value. 4465 */ 4466 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) 4467 mapsize = pci_romsize(testval); 4468 else 4469 mapsize = pci_mapsize(testval); 4470 if (mapsize == 0) 4471 goto out; 4472 pm = pci_add_bar(child, *rid, map, mapsize); 4473 } 4474 4475 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { 4476 if (type != SYS_RES_MEMORY) { 4477 if (bootverbose) 4478 device_printf(dev, 4479 "child %s requested type %d for rid %#x," 4480 " but the BAR says it is an memio\n", 4481 device_get_nameunit(child), type, *rid); 4482 goto out; 4483 } 4484 } else { 4485 if (type != SYS_RES_IOPORT) { 4486 if (bootverbose) 4487 device_printf(dev, 4488 "child %s requested type %d for rid %#x," 4489 " but the BAR says it is an ioport\n", 4490 device_get_nameunit(child), type, *rid); 4491 goto out; 4492 } 4493 } 4494 4495 /* 4496 * For real BARs, we need to override the size that 4497 * the driver requests, because that's what the BAR 4498 * actually uses and we would otherwise have a 4499 * situation where we might allocate the excess to 4500 * another driver, which won't work. 4501 */ 4502 count = (pci_addr_t)1 << mapsize; 4503 if (RF_ALIGNMENT(flags) < mapsize) 4504 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 4505 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH)) 4506 flags |= RF_PREFETCHABLE; 4507 4508 /* 4509 * Allocate enough resource, and then write back the 4510 * appropriate BAR for that resource. 4511 */ 4512 resource_list_add(rl, type, *rid, start, end, count); 4513 res = resource_list_reserve(rl, dev, child, type, rid, start, end, 4514 count, flags & ~RF_ACTIVE); 4515 if (res == NULL) { 4516 resource_list_delete(rl, type, *rid); 4517 device_printf(child, 4518 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n", 4519 count, *rid, type, start, end); 4520 goto out; 4521 } 4522 if (bootverbose) 4523 device_printf(child, 4524 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 4525 count, *rid, type, rman_get_start(res)); 4526 map = rman_get_start(res); 4527 pci_write_bar(child, pm, map); 4528 out: 4529 return (res); 4530 } 4531 4532 struct resource * 4533 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 4534 u_long start, u_long end, u_long count, u_int flags) 4535 { 4536 struct pci_devinfo *dinfo; 4537 struct resource_list *rl; 4538 struct resource_list_entry *rle; 4539 struct resource *res; 4540 pcicfgregs *cfg; 4541 4542 if (device_get_parent(child) != dev) 4543 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 4544 type, rid, start, end, count, flags)); 4545 4546 /* 4547 * Perform lazy resource allocation 4548 */ 4549 dinfo = device_get_ivars(child); 4550 rl = &dinfo->resources; 4551 cfg = &dinfo->cfg; 4552 switch (type) { 4553 #if defined(NEW_PCIB) && defined(PCI_RES_BUS) 4554 case PCI_RES_BUS: 4555 return (pci_alloc_secbus(dev, child, rid, start, end, count, 4556 flags)); 4557 #endif 4558 case SYS_RES_IRQ: 4559 /* 4560 * Can't alloc legacy interrupt once MSI messages have 4561 * been allocated. 4562 */ 4563 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 4564 cfg->msix.msix_alloc > 0)) 4565 return (NULL); 4566 4567 /* 4568 * If the child device doesn't have an interrupt 4569 * routed and is deserving of an interrupt, try to 4570 * assign it one. 4571 */ 4572 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 4573 (cfg->intpin != 0)) 4574 pci_assign_interrupt(dev, child, 0); 4575 break; 4576 case SYS_RES_IOPORT: 4577 case SYS_RES_MEMORY: 4578 #ifdef NEW_PCIB 4579 /* 4580 * PCI-PCI bridge I/O window resources are not BARs. 4581 * For those allocations just pass the request up the 4582 * tree. 4583 */ 4584 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { 4585 switch (*rid) { 4586 case PCIR_IOBASEL_1: 4587 case PCIR_MEMBASE_1: 4588 case PCIR_PMBASEL_1: 4589 /* 4590 * XXX: Should we bother creating a resource 4591 * list entry? 4592 */ 4593 return (bus_generic_alloc_resource(dev, child, 4594 type, rid, start, end, count, flags)); 4595 } 4596 } 4597 #endif 4598 /* Reserve resources for this BAR if needed. */ 4599 rle = resource_list_find(rl, type, *rid); 4600 if (rle == NULL) { 4601 res = pci_reserve_map(dev, child, type, rid, start, end, 4602 count, flags); 4603 if (res == NULL) 4604 return (NULL); 4605 } 4606 } 4607 return (resource_list_alloc(rl, dev, child, type, rid, 4608 start, end, count, flags)); 4609 } 4610 4611 int 4612 pci_release_resource(device_t dev, device_t child, int type, int rid, 4613 struct resource *r) 4614 { 4615 struct pci_devinfo *dinfo; 4616 struct resource_list *rl; 4617 pcicfgregs *cfg; 4618 4619 if (device_get_parent(child) != dev) 4620 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 4621 type, rid, r)); 4622 4623 dinfo = device_get_ivars(child); 4624 cfg = &dinfo->cfg; 4625 #ifdef NEW_PCIB 4626 /* 4627 * PCI-PCI bridge I/O window resources are not BARs. For 4628 * those allocations just pass the request up the tree. 4629 */ 4630 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && 4631 (type == SYS_RES_IOPORT || type == SYS_RES_MEMORY)) { 4632 switch (rid) { 4633 case PCIR_IOBASEL_1: 4634 case PCIR_MEMBASE_1: 4635 case PCIR_PMBASEL_1: 4636 return (bus_generic_release_resource(dev, child, type, 4637 rid, r)); 4638 } 4639 } 4640 #endif 4641 4642 rl = &dinfo->resources; 4643 return (resource_list_release(rl, dev, child, type, rid, r)); 4644 } 4645 4646 int 4647 pci_activate_resource(device_t dev, device_t child, int type, int rid, 4648 struct resource *r) 4649 { 4650 struct pci_devinfo *dinfo; 4651 int error; 4652 4653 error = bus_generic_activate_resource(dev, child, type, rid, r); 4654 if (error) 4655 return (error); 4656 4657 /* Enable decoding in the command register when activating BARs. */ 4658 if (device_get_parent(child) == dev) { 4659 /* Device ROMs need their decoding explicitly enabled. */ 4660 dinfo = device_get_ivars(child); 4661 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 4662 pci_write_bar(child, pci_find_bar(child, rid), 4663 rman_get_start(r) | PCIM_BIOS_ENABLE); 4664 switch (type) { 4665 case SYS_RES_IOPORT: 4666 case SYS_RES_MEMORY: 4667 error = PCI_ENABLE_IO(dev, child, type); 4668 break; 4669 } 4670 } 4671 return (error); 4672 } 4673 4674 int 4675 pci_deactivate_resource(device_t dev, device_t child, int type, 4676 int rid, struct resource *r) 4677 { 4678 struct pci_devinfo *dinfo; 4679 int error; 4680 4681 error = bus_generic_deactivate_resource(dev, child, type, rid, r); 4682 if (error) 4683 return (error); 4684 4685 /* Disable decoding for device ROMs. */ 4686 if (device_get_parent(child) == dev) { 4687 dinfo = device_get_ivars(child); 4688 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 4689 pci_write_bar(child, pci_find_bar(child, rid), 4690 rman_get_start(r)); 4691 } 4692 return (0); 4693 } 4694 4695 void 4696 pci_delete_child(device_t dev, device_t child) 4697 { 4698 struct resource_list_entry *rle; 4699 struct resource_list *rl; 4700 struct pci_devinfo *dinfo; 4701 4702 dinfo = device_get_ivars(child); 4703 rl = &dinfo->resources; 4704 4705 if (device_is_attached(child)) 4706 device_detach(child); 4707 4708 /* Turn off access to resources we're about to free */ 4709 pci_write_config(child, PCIR_COMMAND, pci_read_config(child, 4710 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2); 4711 4712 /* Free all allocated resources */ 4713 STAILQ_FOREACH(rle, rl, link) { 4714 if (rle->res) { 4715 if (rman_get_flags(rle->res) & RF_ACTIVE || 4716 resource_list_busy(rl, rle->type, rle->rid)) { 4717 pci_printf(&dinfo->cfg, 4718 "Resource still owned, oops. " 4719 "(type=%d, rid=%d, addr=%lx)\n", 4720 rle->type, rle->rid, 4721 rman_get_start(rle->res)); 4722 bus_release_resource(child, rle->type, rle->rid, 4723 rle->res); 4724 } 4725 resource_list_unreserve(rl, dev, child, rle->type, 4726 rle->rid); 4727 } 4728 } 4729 resource_list_free(rl); 4730 4731 device_delete_child(dev, child); 4732 pci_freecfg(dinfo); 4733 } 4734 4735 void 4736 pci_delete_resource(device_t dev, device_t child, int type, int rid) 4737 { 4738 struct pci_devinfo *dinfo; 4739 struct resource_list *rl; 4740 struct resource_list_entry *rle; 4741 4742 if (device_get_parent(child) != dev) 4743 return; 4744 4745 dinfo = device_get_ivars(child); 4746 rl = &dinfo->resources; 4747 rle = resource_list_find(rl, type, rid); 4748 if (rle == NULL) 4749 return; 4750 4751 if (rle->res) { 4752 if (rman_get_flags(rle->res) & RF_ACTIVE || 4753 resource_list_busy(rl, type, rid)) { 4754 device_printf(dev, "delete_resource: " 4755 "Resource still owned by child, oops. " 4756 "(type=%d, rid=%d, addr=%lx)\n", 4757 type, rid, rman_get_start(rle->res)); 4758 return; 4759 } 4760 resource_list_unreserve(rl, dev, child, type, rid); 4761 } 4762 resource_list_delete(rl, type, rid); 4763 } 4764 4765 struct resource_list * 4766 pci_get_resource_list (device_t dev, device_t child) 4767 { 4768 struct pci_devinfo *dinfo = device_get_ivars(child); 4769 4770 return (&dinfo->resources); 4771 } 4772 4773 bus_dma_tag_t 4774 pci_get_dma_tag(device_t bus, device_t dev) 4775 { 4776 struct pci_softc *sc = device_get_softc(bus); 4777 4778 return (sc->sc_dma_tag); 4779 } 4780 4781 uint32_t 4782 pci_read_config_method(device_t dev, device_t child, int reg, int width) 4783 { 4784 struct pci_devinfo *dinfo = device_get_ivars(child); 4785 pcicfgregs *cfg = &dinfo->cfg; 4786 4787 return (PCIB_READ_CONFIG(device_get_parent(dev), 4788 cfg->bus, cfg->slot, cfg->func, reg, width)); 4789 } 4790 4791 void 4792 pci_write_config_method(device_t dev, device_t child, int reg, 4793 uint32_t val, int width) 4794 { 4795 struct pci_devinfo *dinfo = device_get_ivars(child); 4796 pcicfgregs *cfg = &dinfo->cfg; 4797 4798 PCIB_WRITE_CONFIG(device_get_parent(dev), 4799 cfg->bus, cfg->slot, cfg->func, reg, val, width); 4800 } 4801 4802 int 4803 pci_child_location_str_method(device_t dev, device_t child, char *buf, 4804 size_t buflen) 4805 { 4806 4807 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 4808 pci_get_function(child)); 4809 return (0); 4810 } 4811 4812 int 4813 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 4814 size_t buflen) 4815 { 4816 struct pci_devinfo *dinfo; 4817 pcicfgregs *cfg; 4818 4819 dinfo = device_get_ivars(child); 4820 cfg = &dinfo->cfg; 4821 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 4822 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 4823 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 4824 cfg->progif); 4825 return (0); 4826 } 4827 4828 int 4829 pci_assign_interrupt_method(device_t dev, device_t child) 4830 { 4831 struct pci_devinfo *dinfo = device_get_ivars(child); 4832 pcicfgregs *cfg = &dinfo->cfg; 4833 4834 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 4835 cfg->intpin)); 4836 } 4837 4838 static int 4839 pci_modevent(module_t mod, int what, void *arg) 4840 { 4841 static struct cdev *pci_cdev; 4842 4843 switch (what) { 4844 case MOD_LOAD: 4845 STAILQ_INIT(&pci_devq); 4846 pci_generation = 0; 4847 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 4848 "pci"); 4849 pci_load_vendor_data(); 4850 break; 4851 4852 case MOD_UNLOAD: 4853 destroy_dev(pci_cdev); 4854 break; 4855 } 4856 4857 return (0); 4858 } 4859 4860 static void 4861 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo) 4862 { 4863 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2) 4864 struct pcicfg_pcie *cfg; 4865 int version, pos; 4866 4867 cfg = &dinfo->cfg.pcie; 4868 pos = cfg->pcie_location; 4869 4870 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 4871 4872 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); 4873 4874 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 4875 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 4876 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 4877 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); 4878 4879 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 4880 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 4881 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 4882 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); 4883 4884 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 4885 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 4886 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); 4887 4888 if (version > 1) { 4889 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); 4890 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); 4891 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); 4892 } 4893 #undef WREG 4894 } 4895 4896 static void 4897 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo) 4898 { 4899 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 4900 dinfo->cfg.pcix.pcix_command, 2); 4901 } 4902 4903 void 4904 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 4905 { 4906 4907 /* 4908 * Only do header type 0 devices. Type 1 devices are bridges, 4909 * which we know need special treatment. Type 2 devices are 4910 * cardbus bridges which also require special treatment. 4911 * Other types are unknown, and we err on the side of safety 4912 * by ignoring them. 4913 */ 4914 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 4915 return; 4916 4917 /* 4918 * Restore the device to full power mode. We must do this 4919 * before we restore the registers because moving from D3 to 4920 * D0 will cause the chip's BARs and some other registers to 4921 * be reset to some unknown power on reset values. Cut down 4922 * the noise on boot by doing nothing if we are already in 4923 * state D0. 4924 */ 4925 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) 4926 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 4927 pci_restore_bars(dev); 4928 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 4929 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 4930 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 4931 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 4932 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 4933 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 4934 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 4935 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 4936 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 4937 4938 /* 4939 * Restore extended capabilities for PCI-Express and PCI-X 4940 */ 4941 if (dinfo->cfg.pcie.pcie_location != 0) 4942 pci_cfg_restore_pcie(dev, dinfo); 4943 if (dinfo->cfg.pcix.pcix_location != 0) 4944 pci_cfg_restore_pcix(dev, dinfo); 4945 4946 /* Restore MSI and MSI-X configurations if they are present. */ 4947 if (dinfo->cfg.msi.msi_location != 0) 4948 pci_resume_msi(dev); 4949 if (dinfo->cfg.msix.msix_location != 0) 4950 pci_resume_msix(dev); 4951 } 4952 4953 static void 4954 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo) 4955 { 4956 #define RREG(n) pci_read_config(dev, pos + (n), 2) 4957 struct pcicfg_pcie *cfg; 4958 int version, pos; 4959 4960 cfg = &dinfo->cfg.pcie; 4961 pos = cfg->pcie_location; 4962 4963 cfg->pcie_flags = RREG(PCIER_FLAGS); 4964 4965 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 4966 4967 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); 4968 4969 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 4970 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 4971 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 4972 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); 4973 4974 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 4975 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 4976 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 4977 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); 4978 4979 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 4980 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 4981 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); 4982 4983 if (version > 1) { 4984 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); 4985 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); 4986 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); 4987 } 4988 #undef RREG 4989 } 4990 4991 static void 4992 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo) 4993 { 4994 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, 4995 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); 4996 } 4997 4998 void 4999 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 5000 { 5001 uint32_t cls; 5002 int ps; 5003 5004 /* 5005 * Only do header type 0 devices. Type 1 devices are bridges, which 5006 * we know need special treatment. Type 2 devices are cardbus bridges 5007 * which also require special treatment. Other types are unknown, and 5008 * we err on the side of safety by ignoring them. Powering down 5009 * bridges should not be undertaken lightly. 5010 */ 5011 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 5012 return; 5013 5014 /* 5015 * Some drivers apparently write to these registers w/o updating our 5016 * cached copy. No harm happens if we update the copy, so do so here 5017 * so we can restore them. The COMMAND register is modified by the 5018 * bus w/o updating the cache. This should represent the normally 5019 * writable portion of the 'defined' part of type 0 headers. In 5020 * theory we also need to save/restore the PCI capability structures 5021 * we know about, but apart from power we don't know any that are 5022 * writable. 5023 */ 5024 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 5025 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 5026 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 5027 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 5028 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 5029 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 5030 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 5031 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 5032 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 5033 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 5034 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 5035 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 5036 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 5037 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 5038 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 5039 5040 if (dinfo->cfg.pcie.pcie_location != 0) 5041 pci_cfg_save_pcie(dev, dinfo); 5042 5043 if (dinfo->cfg.pcix.pcix_location != 0) 5044 pci_cfg_save_pcix(dev, dinfo); 5045 5046 /* 5047 * don't set the state for display devices, base peripherals and 5048 * memory devices since bad things happen when they are powered down. 5049 * We should (a) have drivers that can easily detach and (b) use 5050 * generic drivers for these devices so that some device actually 5051 * attaches. We need to make sure that when we implement (a) we don't 5052 * power the device down on a reattach. 5053 */ 5054 cls = pci_get_class(dev); 5055 if (!setstate) 5056 return; 5057 switch (pci_do_power_nodriver) 5058 { 5059 case 0: /* NO powerdown at all */ 5060 return; 5061 case 1: /* Conservative about what to power down */ 5062 if (cls == PCIC_STORAGE) 5063 return; 5064 /*FALLTHROUGH*/ 5065 case 2: /* Agressive about what to power down */ 5066 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 5067 cls == PCIC_BASEPERIPH) 5068 return; 5069 /*FALLTHROUGH*/ 5070 case 3: /* Power down everything */ 5071 break; 5072 } 5073 /* 5074 * PCI spec says we can only go into D3 state from D0 state. 5075 * Transition from D[12] into D0 before going to D3 state. 5076 */ 5077 ps = pci_get_powerstate(dev); 5078 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 5079 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 5080 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 5081 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 5082 } 5083 5084 /* Wrapper APIs suitable for device driver use. */ 5085 void 5086 pci_save_state(device_t dev) 5087 { 5088 struct pci_devinfo *dinfo; 5089 5090 dinfo = device_get_ivars(dev); 5091 pci_cfg_save(dev, dinfo, 0); 5092 } 5093 5094 void 5095 pci_restore_state(device_t dev) 5096 { 5097 struct pci_devinfo *dinfo; 5098 5099 dinfo = device_get_ivars(dev); 5100 pci_cfg_restore(dev, dinfo); 5101 } 5102 5103 static uint16_t 5104 pci_get_rid_method(device_t dev, device_t child) 5105 { 5106 5107 return (PCIB_GET_RID(device_get_parent(dev), child)); 5108 } 5109