1 /************************************************************************** 2 ** 3 ** $Id: pci.c,v 1.56 1996/10/14 13:04:34 se Exp $ 4 ** 5 ** General subroutines for the PCI bus. 6 ** pci_configure () 7 ** 8 ** FreeBSD 9 ** 10 **------------------------------------------------------------------------- 11 ** 12 ** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved. 13 ** 14 ** Redistribution and use in source and binary forms, with or without 15 ** modification, are permitted provided that the following conditions 16 ** are met: 17 ** 1. Redistributions of source code must retain the above copyright 18 ** notice, this list of conditions and the following disclaimer. 19 ** 2. Redistributions in binary form must reproduce the above copyright 20 ** notice, this list of conditions and the following disclaimer in the 21 ** documentation and/or other materials provided with the distribution. 22 ** 3. The name of the author may not be used to endorse or promote products 23 ** derived from this software without specific prior written permission. 24 ** 25 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 ** 36 *************************************************************************** 37 */ 38 39 #include "pci.h" 40 #if NPCI > 0 41 42 /*======================================================== 43 ** 44 ** #includes and declarations 45 ** 46 **======================================================== 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/malloc.h> 52 #include <sys/errno.h> 53 #include <sys/kernel.h> 54 #include <sys/proc.h> /* declaration of wakeup(), used by vm.h */ 55 #include <sys/conf.h> 56 #ifdef DEVFS 57 #include <sys/devfsext.h> 58 #endif /* DEVFS */ 59 #include <sys/fcntl.h> 60 61 #include <vm/vm.h> 62 #include <vm/vm_param.h> 63 #include <vm/pmap.h> 64 65 66 #include <i386/isa/isa_device.h> /* XXX inthand2_t */ 67 68 #include <pci/pcivar.h> 69 #include <pci/pcireg.h> 70 #include <pci/pcibus.h> 71 #include <pci/pci_ioctl.h> 72 73 #define PCI_MAX_IRQ (16) 74 75 76 /*======================================================== 77 ** 78 ** Structs and Functions 79 ** 80 **======================================================== 81 */ 82 83 struct pcicb { 84 struct pcicb *pcicb_next; 85 struct pcicb *pcicb_up; 86 struct pcicb *pcicb_down; 87 pcici_t pcicb_bridge; 88 89 u_long pcicb_seen; 90 u_char pcicb_bus; 91 u_char pcicb_subordinate; 92 u_char pcicb_flags; 93 #define PCICB_ISAMEM 0x01 94 u_int pcicb_mfrom; 95 u_int pcicb_mupto; 96 u_int pcicb_mamount; 97 u_short pcicb_pfrom; 98 u_short pcicb_pupto; 99 u_short pcicb_pamount; 100 u_char pcicb_bfrom; 101 u_char pcicb_bupto; 102 103 u_long pcicb_iobase; 104 u_long pcicb_iolimit; 105 u_long pcicb_membase; 106 u_long pcicb_memlimit; 107 u_long pcicb_p_membase; 108 u_long pcicb_p_memlimit; 109 }; 110 111 static void 112 not_supported (pcici_t tag, u_long type); 113 114 static void 115 pci_bus_config (void); 116 117 static int 118 pci_bridge_config (void); 119 120 static int 121 pci_mfdev (int bus, int device); 122 123 static void pci_remember (int bus, int dev, int func); 124 125 /*======================================================== 126 ** 127 ** Variables 128 ** 129 **======================================================== 130 */ 131 132 /* 133 ** log2 of safe burst len (in words) 134 */ 135 136 unsigned pci_max_burst_len = 3; /* 2=16Byte, 3=32Byte, 4=64Byte, ... */ 137 unsigned pci_mechanism = 0; 138 unsigned pci_maxdevice = 0; 139 unsigned pciroots = 0; /* XXX pcisupport.c increments this 140 * for the Orion host to PCI bridge 141 * UGLY hack ... :( Will be changed :) 142 */ 143 static struct pcibus* pcibus; 144 145 /*-------------------------------------------------------- 146 ** 147 ** Local variables. 148 ** 149 **-------------------------------------------------------- 150 */ 151 152 static int pci_conf_count; 153 static int pci_info_done; 154 static int pcibusmax; 155 static struct pcicb *pcicb; 156 157 /*----------------------------------------------------------------- 158 ** 159 ** The following functions are provided for the device driver 160 ** to read/write the configuration space. 161 ** 162 ** pci_conf_read(): 163 ** Read a long word from the pci configuration space. 164 ** Requires a tag (from pcitag) and the register 165 ** number (should be a long word alligned one). 166 ** 167 ** pci_conf_write(): 168 ** Writes a long word to the pci configuration space. 169 ** Requires a tag (from pcitag), the register number 170 ** (should be a long word alligned one), and a value. 171 ** 172 **----------------------------------------------------------------- 173 */ 174 175 u_long 176 pci_conf_read (pcici_t tag, u_long reg) 177 { 178 return (pcibus->pb_read (tag, reg)); 179 } 180 181 void 182 pci_conf_write (pcici_t tag, u_long reg, u_long data) 183 { 184 pcibus->pb_write (tag, reg, data); 185 } 186 187 /*======================================================== 188 ** 189 ** Subroutines for configuration. 190 ** 191 **======================================================== 192 */ 193 194 static void 195 pci_register_io (struct pcicb * cb, u_int base, u_int limit) 196 { 197 #ifdef PCI_BRIDGE_DEBUG 198 if (bootverbose) 199 printf ("register_io: bus=%d base=%x limit=%x\n", 200 cb->pcicb_bus, base, limit); 201 #endif 202 203 if (!cb->pcicb_pfrom || base < cb->pcicb_pfrom) 204 cb->pcicb_pfrom = base; 205 if (limit > cb->pcicb_pupto) 206 cb->pcicb_pupto = limit; 207 208 /* 209 ** XXX should set bridge io mapping here 210 ** but it can be mapped in 4k blocks only, 211 ** leading to conflicts with isa/eisa .. 212 */ 213 } 214 215 static void 216 pci_register_memory (struct pcicb * cb, u_int base, u_int limit) 217 { 218 #ifdef PCI_BRIDGE_DEBUG 219 if (bootverbose) 220 printf ("register_mem: bus=%d base=%x limit=%x\n", 221 cb->pcicb_bus, base, limit); 222 #endif 223 224 if (!cb->pcicb_mfrom || base < cb->pcicb_mfrom) 225 cb->pcicb_mfrom = base; 226 if (limit > cb->pcicb_mupto) 227 cb->pcicb_mupto = limit; 228 /* 229 ** set the bridges mapping 230 ** 231 ** XXX should handle the 1Mb granularity. 232 */ 233 if (cb->pcicb_bridge.tag) { 234 pci_conf_write(cb->pcicb_bridge, 235 PCI_PCI_BRIDGE_MEM_REG, 236 (cb->pcicb_memlimit & 0xffff0000) | 237 (cb->pcicb_membase >> 16)); 238 if (bootverbose) 239 printf ("\t[pci%d uses memory from %x to %x]\n", 240 cb->pcicb_bus, 241 (unsigned) cb->pcicb_membase, 242 (unsigned) cb->pcicb_memlimit); 243 } 244 } 245 246 /* 247 ** XXX This function is neither complete nor tested. 248 ** It's only used if the bios hasn't done it's job 249 ** of mapping the pci devices in the physical memory. 250 */ 251 252 static u_int 253 pci_memalloc (struct pcicb * cb, u_int addr, u_int size) 254 { 255 u_int result = 0, limit=0, newbase=0; 256 #ifdef PCI_BRIDGE_DEBUG 257 if (bootverbose) 258 printf ("memalloc: bus=%d addr=%x size=%x ..\n", 259 cb->pcicb_bus, addr, size); 260 #endif 261 262 if (!cb) goto done; 263 264 if (!cb->pcicb_membase) { 265 printf ("memalloc: bus%d: membase not set.\n", 266 cb->pcicb_bus); 267 goto done; 268 } 269 270 /* 271 ** get upper allocation limit 272 */ 273 limit = cb->pcicb_memlimit; 274 if (cb->pcicb_mfrom && cb->pcicb_mfrom <= limit) 275 limit = cb->pcicb_mfrom-1; 276 277 /* 278 ** address fixed, and impossible to allocate ? 279 */ 280 if (addr && addr+size-1 > limit) 281 goto done; 282 283 /* 284 ** get possible address 285 */ 286 287 result = addr; 288 if (!result) result = ((limit + 1) / size - 1) * size; 289 290 /* 291 ** if not local available, request from parent. 292 */ 293 294 if (result < cb->pcicb_membase) { 295 newbase = pci_memalloc (cb->pcicb_up, result, size); 296 if (newbase) cb->pcicb_membase = result; 297 else result=0; 298 } 299 done: 300 if (result) 301 pci_register_memory (cb, result, result+size-1); 302 303 #ifdef PCI_BRIDGE_DEBUG 304 printf ("memalloc: bus=%d addr=%x size=%x --> %x (limit=%x).\n", 305 cb->pcicb_bus, addr, size, result, limit); 306 #endif 307 308 return (result); 309 } 310 311 /*======================================================== 312 ** 313 ** pci_bridge_config() 314 ** 315 ** Configuration of a pci bridge. 316 ** 317 **======================================================== 318 */ 319 320 static int 321 pci_bridge_config (void) 322 { 323 pcici_t tag; 324 struct pcicb* parent; 325 326 tag = pcicb->pcicb_bridge; 327 if (tag.tag) { 328 329 if (!pcicb->pcicb_bus) { 330 u_int data; 331 /* 332 ** Get the lowest available bus number. 333 */ 334 pcicb->pcicb_bus = ++pcibusmax; 335 336 /* 337 ** and configure the bridge 338 */ 339 data = pci_conf_read (tag, PCI_PCI_BRIDGE_BUS_REG); 340 data = PCI_PRIMARY_BUS_INSERT(data, pcicb->pcicb_up->pcicb_bus); 341 data = PCI_SECONDARY_BUS_INSERT(data, pcicb->pcicb_bus); 342 data = PCI_SUBORDINATE_BUS_INSERT(data, pcicb->pcicb_bus); 343 pci_conf_write (tag, PCI_PCI_BRIDGE_BUS_REG, data); 344 345 /* 346 ** Propagate the new upper bus number limit. 347 */ 348 for (parent = pcicb->pcicb_up; parent != NULL; 349 parent = parent->pcicb_up) 350 { 351 if (parent->pcicb_subordinate >= pcicb->pcicb_bus) 352 continue; 353 parent->pcicb_subordinate = pcicb->pcicb_bus; 354 if (!parent->pcicb_bridge.tag) 355 continue; 356 data = pci_conf_read 357 (parent->pcicb_bridge, PCI_PCI_BRIDGE_BUS_REG); 358 data = PCI_SUBORDINATE_BUS_INSERT 359 (data, pcicb->pcicb_bus); 360 pci_conf_write (parent->pcicb_bridge, 361 PCI_PCI_BRIDGE_BUS_REG, data); 362 } 363 } 364 365 if (!pcicb->pcicb_membase) { 366 u_int size = 0x100000; 367 pcicb->pcicb_membase = pci_memalloc (pcicb->pcicb_up, 0, size); 368 if (pcicb->pcicb_membase) 369 pcicb->pcicb_memlimit = pcicb->pcicb_membase+size-1; 370 } 371 } 372 return pcicb->pcicb_bus; 373 } 374 375 /*======================================================== 376 ** 377 ** pci_bus_config() 378 ** 379 ** Autoconfiguration of one pci bus. 380 ** 381 **======================================================== 382 */ 383 384 static int 385 pci_mfdev (int bus, int device) 386 { 387 pcici_t tag0,tag1; 388 unsigned pci_id0, pci_id1; 389 390 /* 391 ** Detect a multi-function device that complies to the PCI 2.0 spec 392 */ 393 tag0 = pcibus->pb_tag (bus, device, 0); 394 if (pci_conf_read (tag0, PCI_HEADER_MISC) & PCI_HEADER_MULTIFUNCTION) 395 return 1; 396 397 /* 398 ** Well, as always: Theory and implementation of PCI ... 399 ** 400 ** If there is a valid device ID returned for function 1 AND 401 ** the device ID of function 0 and 1 is different OR 402 ** the first mapping register of 0 and 1 differs, 403 ** then assume a multi-function device anyway ... 404 ** 405 ** Example of such a broken device: ISA and IDE chip i83371FB (Triton) 406 */ 407 tag1 = pcibus->pb_tag (bus, device, 1); 408 pci_id1 = pci_conf_read (tag1, PCI_ID_REG); 409 410 if (pci_id1 != 0xffffffff) { 411 412 pci_id0 = pci_conf_read (tag0, PCI_ID_REG); 413 414 if (pci_id0 != pci_id1) 415 return 1; 416 417 if (pci_conf_read (tag0, PCI_MAP_REG_START) 418 != pci_conf_read (tag1, PCI_MAP_REG_START)) 419 return 1; 420 } 421 return 0; 422 } 423 424 static void 425 pci_bus_config (void) 426 { 427 int bus_no; 428 u_char device; 429 u_char reg; 430 pcici_t tag, mtag; 431 pcidi_t type; 432 u_long data; 433 int unit; 434 u_char pciint; 435 int irq; 436 437 struct pci_device *dvp; 438 439 /* 440 ** first initialize the bridge (bus controller chip) 441 */ 442 bus_no = pci_bridge_config (); 443 444 printf ("Probing for devices on PCI bus %d:\n", bus_no); 445 #ifndef PCI_QUIET 446 if (bootverbose && !pci_info_done) { 447 pci_info_done=1; 448 printf ("\tconfiguration mode %d allows %d devices.\n", 449 pci_mechanism, pci_maxdevice); 450 }; 451 #endif 452 for (device=0; device<pci_maxdevice; device ++) { 453 char *name = NULL; 454 struct pci_device **dvpp; 455 int func, maxfunc = 0; 456 457 if ((pcicb->pcicb_seen >> device) & 1) 458 continue; 459 460 for (func=0; func <= maxfunc; func++) { 461 tag = pcibus->pb_tag (bus_no, device, func); 462 type = pci_conf_read (tag, PCI_ID_REG); 463 464 if ((!type) || (type==0xfffffffful)) continue; 465 466 /* 467 ** lookup device in ioconfiguration: 468 */ 469 470 dvpp = (struct pci_device **)pcidevice_set.ls_items; 471 472 while (dvp = *dvpp++) { 473 if (dvp->pd_probe) { 474 if (name=(*dvp->pd_probe)(tag, type)) 475 break; 476 } 477 }; 478 /* 479 ** check for mirrored devices. 480 */ 481 if (func != 0) { 482 goto real_device; 483 } 484 if (device & 0x10) { 485 mtag=pcibus->pb_tag (bus_no, 486 (u_char)(device & ~0x10), 0); 487 } else if (device & 0x08) { 488 mtag=pcibus->pb_tag (bus_no, 489 (u_char)(device & ~0x08), 0); 490 } else goto real_device; 491 492 if (type!=pci_conf_read (mtag, PCI_ID_REG)) 493 goto real_device; 494 495 for (reg=PCI_MAP_REG_START;reg<PCI_MAP_REG_END;reg+=4) 496 if (pci_conf_read(tag,reg)!=pci_conf_read(mtag,reg)) 497 goto real_device; 498 499 #ifndef PCI_QUIET 500 if (dvp==NULL) continue; 501 if (bootverbose) 502 printf ("%s? <%s> mirrored on pci%d:%d\n", 503 dvp->pd_name, name, bus_no, device); 504 #endif 505 continue; 506 507 real_device: 508 509 #ifndef PCI_QUIET 510 #ifdef PCI_BRIDGE_DEBUG 511 if (bootverbose) { 512 printf ("\tconfig header: 0x%08x 0x%08x 0x%08x 0x%08x\n", 513 pci_conf_read (tag, 0), 514 pci_conf_read (tag, 4), 515 pci_conf_read (tag, 8), 516 pci_conf_read (tag, 12)); 517 } 518 #endif 519 #endif 520 521 if (func == 0 && pci_mfdev (bus_no, device)) { 522 maxfunc = 7; 523 } 524 525 pci_remember(bus_no, device, func); 526 527 if (dvp==NULL) { 528 #ifndef PCI_QUIET 529 if (pci_conf_count) 530 continue; 531 532 if (maxfunc == 0) 533 printf("%s%d:%d: ", 534 pcibus->pb_name, bus_no, device); 535 else 536 printf("%s%d:%d:%d: ", 537 pcibus->pb_name, bus_no, device, func); 538 not_supported (tag, type); 539 #endif 540 continue; 541 }; 542 543 pcicb->pcicb_seen |= (1ul << device); 544 545 /* 546 ** Get and increment the unit. 547 */ 548 549 unit = (*dvp->pd_count)++; 550 551 /* 552 ** ignore device ? 553 */ 554 555 if (!*name) continue; 556 557 /* 558 ** Announce this device 559 */ 560 561 printf ("%s%d <%s> rev %d", dvp->pd_name, unit, name, 562 (unsigned) pci_conf_read (tag, PCI_CLASS_REG) & 0xff); 563 564 /* 565 ** Get the int pin number (pci interrupt number a-d) 566 ** from the pci configuration space. 567 */ 568 569 data = pci_conf_read (tag, PCI_INTERRUPT_REG); 570 pciint = PCI_INTERRUPT_PIN_EXTRACT(data); 571 572 if (pciint) { 573 574 printf (" int %c irq ", 0x60+pciint); 575 576 irq = PCI_INTERRUPT_LINE_EXTRACT(data); 577 578 /* 579 ** If it's zero, the isa irq number is unknown, 580 ** and we cannot bind the pci interrupt. 581 */ 582 583 if (irq && (irq != 0xff)) 584 printf ("%d", irq); 585 else 586 printf ("??"); 587 }; 588 589 if (maxfunc == 0) 590 printf (" on pci%d:%d\n", bus_no, device); 591 else 592 printf (" on pci%d:%d:%d\n", bus_no, device, func); 593 594 /* 595 ** Read the current mapping, 596 ** and update the pcicb fields. 597 */ 598 599 for (reg=PCI_MAP_REG_START;reg<PCI_MAP_REG_END;reg+=4) { 600 u_int map, addr, size; 601 602 data = pci_conf_read(tag, PCI_CLASS_REG); 603 switch (data & (PCI_CLASS_MASK|PCI_SUBCLASS_MASK)) { 604 case PCI_CLASS_BRIDGE|PCI_SUBCLASS_BRIDGE_PCI: 605 continue; 606 }; 607 608 map = pci_conf_read (tag, reg); 609 if (!(map & PCI_MAP_MEMORY_ADDRESS_MASK)) 610 continue; 611 612 pci_conf_write (tag, reg, 0xffffffff); 613 data = pci_conf_read (tag, reg); 614 pci_conf_write (tag, reg, map); 615 616 switch (data & 7) { 617 618 default: 619 continue; 620 case 1: 621 case 5: 622 addr = map & PCI_MAP_IO_ADDRESS_MASK; 623 size = -(data & PCI_MAP_IO_ADDRESS_MASK); 624 size &= ~(addr ^ -addr); 625 626 pci_register_io (pcicb, addr, addr+size-1); 627 pcicb->pcicb_pamount += size; 628 break; 629 630 case 0: 631 case 2: 632 case 4: 633 size = -(data & PCI_MAP_MEMORY_ADDRESS_MASK); 634 addr = map & PCI_MAP_MEMORY_ADDRESS_MASK; 635 if (addr >= 0x100000) { 636 pci_register_memory 637 (pcicb, addr, addr+size-1); 638 pcicb->pcicb_mamount += size; 639 } else { 640 pcicb->pcicb_flags |= PCICB_ISAMEM; 641 }; 642 break; 643 }; 644 if (bootverbose) 645 printf ("\tmapreg[%02x] type=%d addr=%08x size=%04x.\n", 646 reg, map&7, addr, size); 647 }; 648 649 /* 650 ** attach device 651 ** may produce additional log messages, 652 ** i.e. when installing subdevices. 653 */ 654 655 (*dvp->pd_attach) (tag, unit); 656 657 /* 658 ** Special processing of certain classes 659 */ 660 661 data = pci_conf_read(tag, PCI_CLASS_REG); 662 663 switch (data & (PCI_CLASS_MASK|PCI_SUBCLASS_MASK)) { 664 struct pcicb *this, **link; 665 unsigned char primary, secondary, subordinate; 666 u_int command; 667 668 case PCI_CLASS_BRIDGE|PCI_SUBCLASS_BRIDGE_PCI: 669 670 /* 671 ** get current configuration of the bridge. 672 */ 673 data = pci_conf_read (tag, PCI_PCI_BRIDGE_BUS_REG); 674 primary = PCI_PRIMARY_BUS_EXTRACT (data); 675 secondary = PCI_SECONDARY_BUS_EXTRACT(data); 676 subordinate = PCI_SUBORDINATE_BUS_EXTRACT(data); 677 #ifndef PCI_QUIET 678 if (bootverbose) { 679 printf ("\tbridge from pci%d to pci%d through %d.\n", 680 primary, secondary, subordinate); 681 printf ("\tmapping regs: io:%08lx mem:%08lx pmem:%08lx\n", 682 pci_conf_read (tag, PCI_PCI_BRIDGE_IO_REG), 683 pci_conf_read (tag, PCI_PCI_BRIDGE_MEM_REG), 684 pci_conf_read (tag, PCI_PCI_BRIDGE_PMEM_REG)); 685 } 686 #endif 687 /* 688 ** check for uninitialized bridge. 689 */ 690 if (!(primary < secondary 691 && secondary <= subordinate 692 && bus_no == primary)) 693 { 694 printf ("\tINCORRECTLY or NEVER CONFIGURED.\n"); 695 /* 696 ** disable this bridge 697 */ 698 pci_conf_write (tag, PCI_COMMAND_STATUS_REG, 699 0xffff0000); 700 secondary = 0; 701 subordinate = 0; 702 }; 703 704 /* 705 ** allocate bus descriptor for bus behind the bridge 706 */ 707 link = &pcicb->pcicb_down; 708 while (*link && (*link)->pcicb_bus < secondary) 709 link = &(*link)->pcicb_next; 710 711 this = malloc (sizeof (*this), M_DEVBUF, M_WAITOK); 712 713 /* 714 ** Initialize this descriptor so far. 715 ** (the initialization is completed just before 716 ** scanning the bus behind the bridge. 717 */ 718 bzero (this, sizeof(*this)); 719 this->pcicb_next = *link; 720 this->pcicb_up = pcicb; 721 this->pcicb_bridge = tag; 722 this->pcicb_bus = secondary; 723 this->pcicb_subordinate = subordinate; 724 725 command = pci_conf_read(tag,PCI_COMMAND_STATUS_REG); 726 727 if (command & PCI_COMMAND_IO_ENABLE){ 728 /* 729 ** Bridge was configured by the bios. 730 ** Read out the mapped io region. 731 */ 732 u_int reg, data, mask; 733 734 reg = pci_conf_read (tag, 735 PCI_PCI_BRIDGE_IO_REG); 736 pci_conf_write(tag, 737 PCI_PCI_BRIDGE_IO_REG, 0xFFFF); 738 data = pci_conf_read (tag, 739 PCI_PCI_BRIDGE_IO_REG); 740 pci_conf_write(tag, 741 PCI_PCI_BRIDGE_IO_REG, reg & 0xffff); 742 743 mask = (0xFF00 ^ (data & 0xFF00)) | 0xFF; 744 745 this->pcicb_iobase = 746 PCI_PPB_IOBASE_EXTRACT (reg); 747 this->pcicb_iolimit = 748 PCI_PPB_IOLIMIT_EXTRACT(reg) | mask; 749 750 /* 751 ** Note the used io space. 752 */ 753 pci_register_io (pcicb, this->pcicb_iobase, 754 this->pcicb_iolimit); 755 756 }; 757 758 if (command & PCI_COMMAND_MEM_ENABLE) { 759 /* 760 ** Bridge was configured by the bios. 761 ** Read out the mapped memory regions. 762 */ 763 u_int reg, data, mask; 764 765 /* 766 ** non prefetchable memory 767 */ 768 reg = pci_conf_read (tag, 769 PCI_PCI_BRIDGE_MEM_REG); 770 pci_conf_write(tag, 771 PCI_PCI_BRIDGE_MEM_REG, 0xFFFFFFFF); 772 data = pci_conf_read (tag, 773 PCI_PCI_BRIDGE_MEM_REG); 774 pci_conf_write(tag, 775 PCI_PCI_BRIDGE_MEM_REG, reg); 776 777 mask = 0xFFFFFFFF ^ (data & 0xFFFF0000); 778 this->pcicb_membase = 779 PCI_PPB_MEMBASE_EXTRACT (reg); 780 this->pcicb_memlimit = 781 PCI_PPB_MEMLIMIT_EXTRACT(reg) | mask; 782 783 /* 784 ** Register used memory space. 785 */ 786 pci_register_memory (pcicb, 787 this->pcicb_membase, 788 this->pcicb_memlimit); 789 790 /* 791 ** prefetchable memory 792 */ 793 reg = pci_conf_read (tag, 794 PCI_PCI_BRIDGE_PMEM_REG); 795 pci_conf_write(tag, 796 PCI_PCI_BRIDGE_PMEM_REG, 0xFFFFFFFF); 797 data = pci_conf_read (tag, 798 PCI_PCI_BRIDGE_PMEM_REG); 799 pci_conf_write(tag, 800 PCI_PCI_BRIDGE_PMEM_REG, reg); 801 802 mask = 0xFFFFFFFF ^ (data & 0xFFFF0000); 803 this->pcicb_p_membase= 804 PCI_PPB_MEMBASE_EXTRACT (reg); 805 this->pcicb_p_memlimit= 806 PCI_PPB_MEMLIMIT_EXTRACT(reg) | mask; 807 808 /* 809 ** Register used memory space. 810 */ 811 pci_register_memory (pcicb, 812 this->pcicb_p_membase, 813 this->pcicb_p_memlimit); 814 } 815 816 /* 817 ** Link it in chain. 818 */ 819 *link=this; 820 821 /* 822 ** Update mapping info of parent bus. 823 */ 824 if (!pcicb->pcicb_bfrom||secondary< pcicb->pcicb_bfrom) 825 pcicb->pcicb_bfrom = secondary; 826 if (subordinate > pcicb->pcicb_bupto) 827 pcicb->pcicb_bupto = subordinate; 828 829 break; 830 } 831 } 832 } 833 834 #ifndef PCI_QUIET 835 if (bootverbose) { 836 if (pcicb->pcicb_mamount) 837 printf ("%s%d: uses %d bytes of memory from %x upto %x.\n", 838 pcibus->pb_name, bus_no, 839 pcicb->pcicb_mamount, 840 pcicb->pcicb_mfrom, pcicb->pcicb_mupto); 841 if (pcicb->pcicb_pamount) 842 printf ("%s%d: uses %d bytes of I/O space from %x upto %x.\n", 843 pcibus->pb_name, bus_no, 844 pcicb->pcicb_pamount, 845 pcicb->pcicb_pfrom, pcicb->pcicb_pupto); 846 if (pcicb->pcicb_bfrom) 847 printf ("%s%d: subordinate busses from %x upto %x.\n", 848 pcibus->pb_name, bus_no, 849 pcicb->pcicb_bfrom, pcicb->pcicb_bupto); 850 } 851 #endif 852 } 853 854 /*======================================================== 855 ** 856 ** pci_configure () 857 ** 858 ** Autoconfiguration of pci devices. 859 ** 860 ** May be called more than once. 861 ** Any device is attached only once. 862 ** 863 ** Has to take care of mirrored devices, which are 864 ** entailed by incomplete decoding of pci address lines. 865 ** 866 **======================================================== 867 */ 868 869 void pci_configure() 870 { 871 struct pcibus **pbp = (struct pcibus**) pcibus_set.ls_items; 872 873 /* 874 ** check pci bus present 875 */ 876 877 while (!pci_maxdevice && (pcibus = *pbp++)) { 878 (*pcibus->pb_setup)(); 879 } 880 881 if (!pci_maxdevice) return; 882 883 /* 884 ** hello world .. 885 */ 886 887 pciroots = 1; 888 while (pciroots--) { 889 890 pcicb = malloc (sizeof (struct pcicb), M_DEVBUF, M_WAITOK); 891 if (pcicb == NULL) { 892 return; 893 } 894 bzero (pcicb, sizeof (struct pcicb)); 895 pcicb->pcicb_bus = pcibusmax; 896 pcicb->pcicb_iolimit = 0xffff; 897 pcicb->pcicb_membase = 0x02000000; 898 pcicb->pcicb_p_membase = 0x02000000; 899 pcicb->pcicb_memlimit = 0xffffffff; 900 pcicb->pcicb_p_memlimit = 0xffffffff; 901 902 while (pcicb != NULL) { 903 pci_bus_config (); 904 905 if (pcibusmax < pcicb->pcicb_bus) 906 (pcibusmax = pcicb->pcicb_bus); 907 908 if (pcicb->pcicb_down) { 909 pcicb = pcicb->pcicb_down; 910 continue; 911 }; 912 913 while (pcicb && !pcicb->pcicb_next) 914 pcicb = pcicb->pcicb_up; 915 916 if (pcicb) 917 pcicb = pcicb->pcicb_next; 918 } 919 pcibusmax++; 920 } 921 pci_conf_count++; 922 } 923 924 /*----------------------------------------------------------------------- 925 ** 926 ** Map device into port space. 927 ** 928 ** Actually the device should have been mapped by the bios. 929 ** This function only reads and verifies the value. 930 ** 931 ** PCI-Specification: 6.2.5.1: address maps 932 ** 933 **----------------------------------------------------------------------- 934 */ 935 936 int pci_map_port (pcici_t tag, u_long reg, u_short* pa) 937 { 938 unsigned data, ioaddr, iosize; 939 struct pcicb *link = pcicb; 940 941 /* 942 ** sanity check 943 */ 944 945 if (reg < PCI_MAP_REG_START || reg >= PCI_MAP_REG_END || (reg & 3)) { 946 printf ("pci_map_port failed: bad register=0x%x\n", 947 (unsigned)reg); 948 return (0); 949 }; 950 951 /*if (pcicb->pcicb_flags & PCICB_NOIOSET) { 952 printf ("pci_map_port failed: pci%d has not been configured for I/O access\n", 953 pcicb->pcicb_bus); 954 return (0); 955 }*/ 956 957 /* 958 ** get size and type of port 959 ** 960 ** type is in the lowest two bits. 961 ** If device requires 2^n bytes, the next 962 ** n-2 bits are hardwired as 0. 963 */ 964 965 ioaddr = pci_conf_read (tag, reg) & PCI_MAP_IO_ADDRESS_MASK; 966 if (!ioaddr) { 967 printf ("pci_map_port failed: not configured by bios.\n"); 968 return (0); 969 }; 970 971 pci_conf_write (tag, reg, 0xfffffffful); 972 data = pci_conf_read (tag, reg); 973 pci_conf_write (tag, reg, ioaddr); 974 975 if ((data & 0x03) != PCI_MAP_IO) { 976 printf ("pci_map_port failed: bad port type=0x%x\n", 977 (unsigned) data); 978 return (0); 979 }; 980 iosize = -(data & PCI_MAP_IO_ADDRESS_MASK); 981 iosize &= ~(ioaddr ^ -ioaddr); 982 if (ioaddr < pcicb->pcicb_iobase 983 || ioaddr + iosize -1 > pcicb->pcicb_iolimit) { 984 printf ("pci_map_port failed: device's iorange 0x%x-0x%x " 985 "is incompatible with its bridge's range 0x%x-0x%x\n", 986 (unsigned) ioaddr, (unsigned) ioaddr + iosize - 1, 987 (unsigned) pcicb->pcicb_iobase, 988 (unsigned) pcicb->pcicb_iolimit); 989 return (0); 990 } 991 992 #ifndef PCI_QUIET 993 if (bootverbose) 994 printf ("\treg%d: ioaddr=0x%x size=0x%x\n", 995 (unsigned) reg, (unsigned) ioaddr, (unsigned) iosize); 996 #endif 997 /* 998 ** set the configuration register of and 999 ** return the address to the driver. 1000 ** Make sure to enable each upstream bridge 1001 ** so I/O and DMA can go all the way. 1002 */ 1003 1004 for (;;) { 1005 data = pci_conf_read (tag, PCI_COMMAND_STATUS_REG) & 0xffff; 1006 data |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 1007 (void) pci_conf_write(tag, PCI_COMMAND_STATUS_REG, data); 1008 if ((link = link->pcicb_up) == NULL) 1009 break; 1010 tag = link->pcicb_bridge; 1011 } 1012 1013 *pa = ioaddr; 1014 1015 return (1); 1016 } 1017 1018 /*----------------------------------------------------------------------- 1019 ** 1020 ** Map device into virtual and physical space 1021 ** 1022 ** Actually the device should have been mapped by the bios. 1023 ** This function only reads and verifies the value. 1024 ** 1025 ** PCI-Specification: 6.2.5.1: address maps 1026 ** 1027 **----------------------------------------------------------------------- 1028 */ 1029 1030 int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa) 1031 { 1032 struct pcicb *link = pcicb; 1033 unsigned data ,paddr; 1034 vm_size_t psize, poffs; 1035 vm_offset_t vaddr; 1036 1037 /* 1038 ** sanity check 1039 */ 1040 1041 if (reg < PCI_MAP_REG_START || reg >= PCI_MAP_REG_END || (reg & 3)) { 1042 printf ("pci_map_mem failed: bad register=0x%x\n", 1043 (unsigned)reg); 1044 return (0); 1045 }; 1046 1047 /* 1048 ** save old mapping, get size and type of memory 1049 ** 1050 ** type is in the lowest four bits. 1051 ** If device requires 2^n bytes, the next 1052 ** n-4 bits are read as 0. 1053 */ 1054 1055 paddr = pci_conf_read (tag, reg) & PCI_MAP_MEMORY_ADDRESS_MASK; 1056 pci_conf_write (tag, reg, 0xfffffffful); 1057 data = pci_conf_read (tag, reg); 1058 pci_conf_write (tag, reg, paddr); 1059 1060 /* 1061 ** check the type 1062 */ 1063 1064 if (!((data & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_32BIT_1M 1065 && (paddr & ~0xfffff) == 0) 1066 && (data & PCI_MAP_MEMORY_TYPE_MASK) != PCI_MAP_MEMORY_TYPE_32BIT){ 1067 printf ("pci_map_mem failed: bad memory type=0x%x\n", 1068 (unsigned) data); 1069 return (0); 1070 }; 1071 1072 /* 1073 ** get the size. 1074 */ 1075 1076 psize = -(data & PCI_MAP_MEMORY_ADDRESS_MASK); 1077 1078 if (!paddr || paddr == PCI_MAP_MEMORY_ADDRESS_MASK) { 1079 paddr = pci_memalloc (pcicb, 0, psize); 1080 if (!paddr) { 1081 printf ("pci_map_mem: not configured by bios.\n"); 1082 return (0); 1083 }; 1084 pci_register_memory (pcicb, paddr, paddr+psize-1); 1085 }; 1086 1087 if (paddr < pcicb->pcicb_membase || 1088 paddr + psize - 1 > pcicb->pcicb_memlimit) { 1089 printf ("pci_map_mem failed: device's memrange 0x%x-0x%x is " 1090 "incompatible with its bridge's memrange 0x%x-0x%x\n", 1091 (unsigned) paddr, 1092 (unsigned) (paddr + psize - 1), 1093 (unsigned) pcicb->pcicb_membase, 1094 (unsigned) pcicb->pcicb_memlimit); 1095 /* return (0);*/ 1096 /* ACHTUNG: Ist der Code richtig, wenn eine PCI-PCI-Bridge fuer 1097 * die PCI-Slots verwendet wird, aber die Onboard-Devices direkt 1098 * an der CPU-PCI-Bridge haengen (Siehe Compaq Prolinea Problem) ??? 1099 */ 1100 } 1101 pci_conf_write (tag, reg, paddr); 1102 1103 /* 1104 ** Truncate paddr to page boundary. 1105 ** (Or does pmap_mapdev the job?) 1106 */ 1107 1108 poffs = paddr - trunc_page (paddr); 1109 vaddr = (vm_offset_t) pmap_mapdev (paddr-poffs, psize+poffs); 1110 1111 if (!vaddr) return (0); 1112 1113 vaddr += poffs; 1114 1115 #ifndef PCI_QUIET 1116 /* 1117 ** display values. 1118 */ 1119 1120 if (bootverbose) 1121 printf ("\treg%d: virtual=0x%lx physical=0x%lx size=0x%lx\n", 1122 (unsigned) reg, (u_long)vaddr, (u_long)paddr, (u_long)psize); 1123 #endif 1124 /* 1125 ** set the configuration register and 1126 ** return the address to the driver 1127 ** Make sure to enable each upstream bridge 1128 ** so memory and DMA can go all the way. 1129 */ 1130 1131 for (;;) { 1132 data = pci_conf_read (tag, PCI_COMMAND_STATUS_REG) & 0xffff; 1133 data |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 1134 (void) pci_conf_write(tag, PCI_COMMAND_STATUS_REG, data); 1135 if ((link = link->pcicb_up) == NULL) 1136 break; 1137 tag = link->pcicb_bridge; 1138 } 1139 1140 *va = vaddr; 1141 *pa = paddr; 1142 1143 return (1); 1144 } 1145 1146 /*----------------------------------------------------------------------- 1147 ** 1148 ** Pci meta interrupt handler 1149 ** 1150 ** This handler assumes level triggered interrupts. 1151 ** It's possible to build a kernel which handles shared 1152 ** edge triggered interrupts by the options "PCI_EDGE_INT". 1153 ** But there is a performance penalty. 1154 ** 1155 ** (Of course you can delete the #ifdef PCI_EDGE_INT bracketed 1156 ** code at all :-) :-) :-) 1157 ** 1158 **----------------------------------------------------------------------- 1159 */ 1160 1161 static struct pci_int_desc* 1162 pci_int_desc [PCI_MAX_IRQ]; 1163 1164 #ifndef NO_SHARED_IRQ 1165 1166 static inline unsigned 1167 splq (unsigned mask) 1168 { 1169 unsigned temp=cpl; 1170 cpl |= mask; 1171 return temp; 1172 } 1173 1174 static void 1175 pci_int (int irq) 1176 { 1177 struct pci_int_desc * p; 1178 int s; 1179 1180 if (irq<0 || irq >= PCI_MAX_IRQ) { 1181 printf ("pci_int: irq %d out of range, ignored\n", irq); 1182 return; 1183 }; 1184 for (p = pci_int_desc[irq]; p!=NULL; p=p->pcid_next) { 1185 s = splq (*p->pcid_maskptr); 1186 (*p->pcid_handler) (p->pcid_argument); 1187 p-> pcid_tally++; 1188 splx (s); 1189 #if 0 1190 if (p->pcid_tally<20) 1191 printf ("PCI_INT: irq=%d h=%p cpl o=%x n=%x val=%d\n", 1192 irq, p->pcid_handler, s, cpl, c); 1193 #endif 1194 }; 1195 } 1196 #endif 1197 1198 /*----------------------------------------------------------------------- 1199 ** 1200 ** Auxiliary function for interrupt (un)mapping. 1201 ** 1202 **----------------------------------------------------------------------- 1203 */ 1204 1205 static u_int 1206 getirq (pcici_t tag) 1207 { 1208 u_int irq; 1209 1210 irq = PCI_INTERRUPT_LINE_EXTRACT( 1211 pci_conf_read (tag, PCI_INTERRUPT_REG)); 1212 1213 if (irq <= 0) { 1214 printf ("\tint line register not set by bios\n"); 1215 return (0); 1216 } 1217 1218 if (irq >= pcibus->pb_maxirq || irq >= PCI_MAX_IRQ) { 1219 printf ("\tirq %d invalid.\n", irq); 1220 return (0); 1221 } 1222 1223 return (irq); 1224 } 1225 1226 static struct pci_int_desc ** 1227 getintdescbytag (u_int irq, pcici_t tag) 1228 { 1229 struct pci_int_desc *p, **pp; 1230 1231 pp=&pci_int_desc[irq]; 1232 while (((p=*pp)) && !sametag(p->pcid_tag,tag)) 1233 pp=&p->pcid_next; 1234 1235 if (!p) return (NULL); 1236 1237 return (pp); 1238 } 1239 1240 static struct pci_int_desc * 1241 getintdescbymptr (u_int irq, unsigned * mptr) 1242 { 1243 struct pci_int_desc *p; 1244 1245 for (p=pci_int_desc[irq];p;p=p->pcid_next) 1246 if (p->pcid_maskptr == mptr) break; 1247 return (p); 1248 } 1249 1250 /*----------------------------------------------------------------------- 1251 ** 1252 ** Map pci interrupt. 1253 ** 1254 **----------------------------------------------------------------------- 1255 */ 1256 1257 static unsigned pci_mask0 = 0; 1258 1259 int pci_map_int (pcici_t tag, pci_inthand_t *func, void *arg, unsigned *maskptr) 1260 { 1261 u_int irq; 1262 int result, oldspl; 1263 unsigned mask; 1264 struct pci_int_desc *tail, *mdp=NULL, *new=NULL; 1265 1266 /* 1267 ** Get irq line from configuration space, 1268 ** and check for consistency. 1269 */ 1270 1271 irq = getirq (tag); 1272 if (irq >= PCI_MAX_IRQ) { 1273 printf ("\tillegal irq %d.\n", irq); 1274 return (0); 1275 }; 1276 mask= 1ul << irq; 1277 1278 /* 1279 ** disable this interrupt. 1280 */ 1281 1282 oldspl = splq (mask); 1283 1284 /* 1285 ** If handler for this tag already installed, 1286 ** remove it first. 1287 */ 1288 1289 if (getintdescbytag (irq, tag) != NULL) 1290 pci_unmap_int (tag); 1291 1292 /* 1293 ** If this irq not yet included in the mask, include it. 1294 */ 1295 1296 mdp = getintdescbymptr (irq, maskptr); 1297 if (!mdp) { 1298 result = pcibus->pb_imaskinc (irq, maskptr); 1299 if (result) 1300 goto conflict; 1301 }; 1302 1303 /* 1304 ** Allocate descriptor and initialize it. 1305 */ 1306 1307 tail = pci_int_desc[irq]; 1308 1309 new = malloc (sizeof (*new), M_DEVBUF, M_WAITOK); 1310 bzero (new, sizeof (*new)); 1311 1312 new->pcid_next = tail; 1313 new->pcid_tag = tag; 1314 new->pcid_handler = func; 1315 new->pcid_argument = arg; 1316 new->pcid_maskptr = maskptr; 1317 new->pcid_tally = 0; 1318 new->pcid_mask = mask; 1319 1320 /* 1321 ** If first handler: install it. 1322 ** If second handler: install shared-int-handler. 1323 */ 1324 1325 if (!tail) { 1326 /* 1327 ** first handler for this irq. 1328 */ 1329 1330 result = pcibus->pb_iattach 1331 /* 1332 * XXX if we get here, then `func' must be pci_int 1333 * so the bogus casts are almost OK since they just 1334 * undo the bogus casts that were needed to pass 1335 * pci_int and its arg to pci_map_int(). 1336 */ 1337 (irq, (inthand2_t *) func, (int) arg, maskptr); 1338 if (result) goto conflict; 1339 1340 #ifdef NO_SHARED_IRQ 1341 } else goto conflict; 1342 #else 1343 } else if (!tail->pcid_next) { 1344 /* 1345 ** Second handler for this irq. 1346 */ 1347 1348 if (bootverbose) 1349 printf ("\tusing shared irq %d.\n", irq); 1350 1351 /* 1352 ** replace old handler by shared-int-handler. 1353 */ 1354 1355 result = pcibus->pb_idetach (irq, 1356 (inthand2_t *) tail->pcid_handler); 1357 if (result) 1358 printf ("\tCANNOT DETACH INT HANDLER.\n"); 1359 1360 result = pcibus->pb_iattach (irq, pci_int, irq, &pci_mask0); 1361 if (result) { 1362 printf ("\tCANNOT ATTACH SHARED INT HANDLER.\n"); 1363 goto fail; 1364 }; 1365 } 1366 #endif 1367 /* 1368 ** Link new descriptor, reenable ints and done. 1369 */ 1370 1371 pci_int_desc[irq] = new; 1372 splx (oldspl); 1373 return (1); 1374 1375 /* 1376 ** Handle some problems. 1377 */ 1378 1379 conflict: 1380 printf ("\tirq %d already in use.\n", irq); 1381 fail: 1382 /* 1383 ** If descriptor allocated, free it. 1384 ** If included in mask, remove it. 1385 */ 1386 1387 if (new) free(new, M_DEVBUF); 1388 if (!mdp) (void) pcibus->pb_imaskexc (irq, maskptr); 1389 splx (oldspl); 1390 return (0); 1391 } 1392 1393 /*----------------------------------------------------------------------- 1394 ** 1395 ** Unmap pci interrupt. 1396 ** 1397 **----------------------------------------------------------------------- 1398 */ 1399 1400 int pci_unmap_int (pcici_t tag) 1401 { 1402 int result, oldspl; 1403 struct pci_int_desc *this, **hook, *tail; 1404 unsigned irq; 1405 1406 /* 1407 ** Get irq line from configuration space, 1408 ** and check for consistency. 1409 */ 1410 1411 irq = getirq (tag); 1412 if (irq >= PCI_MAX_IRQ) { 1413 printf ("\tillegal irq %d.\n", irq); 1414 return (0); 1415 }; 1416 1417 /* 1418 ** Search and unlink interrupt descriptor. 1419 */ 1420 1421 hook = getintdescbytag (irq, tag); 1422 if (hook == NULL) { 1423 printf ("\tno irq %d handler for pci %x\n", 1424 irq, tag.tag); 1425 return (0); 1426 }; 1427 1428 this = *hook; 1429 *hook= this->pcid_next; 1430 1431 /* 1432 ** Message 1433 */ 1434 1435 printf ("\tirq %d handler %p(%p) unmapped for pci %x after %d ints.\n", 1436 irq, this->pcid_handler, this->pcid_argument, 1437 this->pcid_tag.tag, this->pcid_tally); 1438 1439 /* 1440 ** If this irq no longer included in the mask, remove it. 1441 */ 1442 1443 if (!getintdescbymptr (irq, this->pcid_maskptr)) 1444 (void) pcibus->pb_imaskexc (irq, this->pcid_maskptr); 1445 1446 tail = pci_int_desc[irq]; 1447 1448 if (tail == NULL) { 1449 1450 /* 1451 ** Remove the old handler. 1452 */ 1453 1454 result = pcibus->pb_idetach (irq, 1455 (inthand2_t *) this->pcid_handler); 1456 if (result) 1457 printf ("\tirq %d: cannot remove handler.\n", irq); 1458 1459 } else if (tail->pcid_next == NULL) { 1460 1461 /* 1462 ** Remove the shared int handler. 1463 ** Install the last remaining handler. 1464 */ 1465 1466 oldspl = splq (1ul << irq); 1467 1468 result = pcibus->pb_idetach (irq, pci_int); 1469 if (result) 1470 printf ("\tirq %d: cannot remove handler.\n", irq); 1471 1472 result = pcibus->pb_iattach (irq, 1473 (inthand2_t *) tail->pcid_handler, 1474 (int) tail->pcid_argument, 1475 tail->pcid_maskptr); 1476 1477 if (result) 1478 printf ("\tirq %d: cannot install handler.\n", irq); 1479 1480 splx (oldspl); 1481 }; 1482 1483 free (this, M_DEVBUF); 1484 return (1); 1485 } 1486 1487 /*----------------------------------------------------------- 1488 ** 1489 ** Display of unknown devices. 1490 ** 1491 **----------------------------------------------------------- 1492 */ 1493 struct vt { 1494 u_short ident; 1495 char* name; 1496 }; 1497 1498 static struct vt VendorTable[] = { 1499 {0x0e11, "Compaq"}, 1500 {0x1000, "NCR/Symbios"}, 1501 {0x1002, "ATI Technologies Inc."}, 1502 {0x1004, "VLSI"}, 1503 {0x100B, "National Semiconductor"}, 1504 {0x100E, "Weitek"}, 1505 {0x1011, "Digital Equipment Corporation"}, 1506 {0x1013, "Cirrus Logic"}, 1507 {0x101A, "NCR"}, 1508 {0x1022, "AMD"}, 1509 {0x102B, "Matrox"}, 1510 {0x102C, "Chips & Technologies"}, 1511 {0x1039, "Silicon Integrated Systems"}, 1512 {0x1042, "SMC"}, 1513 {0x1044, "DPT"}, 1514 {0x1045, "OPTI"}, 1515 {0x104B, "Bus Logic"}, 1516 {0x1060, "UMC"}, 1517 {0x1080, "Contaq"}, 1518 {0x1095, "CMD"}, 1519 {0x10b9, "ACER Labs"}, 1520 {0x1106, "VIA Technologies"}, 1521 {0x5333, "S3 Inc."}, 1522 {0x8086, "Intel Corporation"}, 1523 {0x9004, "Adaptec"}, 1524 {0,0} 1525 }; 1526 1527 typedef struct { 1528 const int subclass; 1529 const char *name; 1530 } subclass_name; 1531 1532 /* 0x00 prehistoric subclasses */ 1533 static const subclass_name old_subclasses[] = 1534 { 1535 { 0x00, "misc" }, 1536 { 0x01, "vga" }, 1537 { 0x00, NULL } 1538 }; 1539 1540 /* 0x01 mass storage subclasses */ 1541 static const subclass_name storage_subclasses[] = 1542 { 1543 { 0x00, "scsi" }, 1544 { 0x01, "ide" }, 1545 { 0x02, "floppy"}, 1546 { 0x03, "ipi" }, 1547 { 0x80, "misc" }, 1548 { 0x00, NULL } 1549 }; 1550 1551 /* 0x02 network subclasses */ 1552 static const subclass_name network_subclasses[] = 1553 { 1554 { 0x00, "ethernet" }, 1555 { 0x01, "tokenring" }, 1556 { 0x02, "fddi" }, 1557 { 0x80, "misc" }, 1558 { 0x00, NULL } 1559 }; 1560 1561 /* 0x03 display subclasses */ 1562 static const subclass_name display_subclasses[] = 1563 { 1564 { 0x00, "vga" }, 1565 { 0x01, "xga" }, 1566 { 0x80, "misc" }, 1567 { 0x00, NULL } 1568 }; 1569 1570 /* 0x04 multimedia subclasses */ 1571 static const subclass_name multimedia_subclasses[] = 1572 { 1573 { 0x00, "video" }, 1574 { 0x01, "audio" }, 1575 { 0x80, "misc" }, 1576 { 0x00, NULL } 1577 }; 1578 1579 /* 0x05 memory subclasses */ 1580 static const subclass_name memory_subclasses[] = 1581 { 1582 { 0x00, "ram" }, 1583 { 0x01, "flash" }, 1584 { 0x80, "misc" }, 1585 { 0x00, NULL } 1586 }; 1587 1588 /* 0x06 bridge subclasses */ 1589 static const subclass_name bridge_subclasses[] = 1590 { 1591 { 0x00, "host" }, 1592 { 0x01, "isa" }, 1593 { 0x02, "eisa" }, 1594 { 0x03, "mc" }, 1595 { 0x04, "pci" }, 1596 { 0x05, "pcmcia"}, 1597 { 0x80, "misc" }, 1598 { 0x00, NULL } 1599 }; 1600 1601 static const subclass_name *const subclasses[] = { 1602 old_subclasses, 1603 storage_subclasses, 1604 network_subclasses, 1605 display_subclasses, 1606 multimedia_subclasses, 1607 memory_subclasses, 1608 bridge_subclasses, 1609 }; 1610 1611 static const char *const majclasses[] = { 1612 "old", 1613 "storage", 1614 "network", 1615 "display", 1616 "multimedia", 1617 "memory", 1618 "bridge" 1619 }; 1620 1621 1622 void not_supported (pcici_t tag, u_long type) 1623 { 1624 u_long reg; 1625 u_long data; 1626 u_char class; 1627 u_char subclass; 1628 struct vt * vp; 1629 int pciint; 1630 int irq; 1631 1632 /* 1633 ** lookup the names. 1634 */ 1635 1636 for (vp=VendorTable; vp->ident; vp++) 1637 if (vp->ident == (type & 0xffff)) 1638 break; 1639 1640 /* 1641 ** and display them. 1642 */ 1643 1644 if (vp->ident) printf (vp->name); 1645 else printf ("vendor=0x%04lx", type & 0xffff); 1646 1647 printf (", device=0x%04lx", type >> 16); 1648 1649 data = pci_conf_read(tag, PCI_CLASS_REG); 1650 class = (data >> 24) & 0xff; 1651 subclass = (data >> 16) & 0xff; 1652 1653 if (class < sizeof(majclasses) / sizeof(majclasses[0])) { 1654 printf(", class=%s", majclasses[class]); 1655 } else { 1656 printf(", class=0x%02x", class); 1657 } 1658 1659 if (class < sizeof(subclasses) / sizeof(subclasses[0])) { 1660 const subclass_name *p = subclasses[class]; 1661 while (p->name && (p->subclass != subclass)) 1662 p++; 1663 if (p->name) { 1664 printf(" (%s)", p->name); 1665 } else { 1666 printf(" (unknown subclass 0x%02lx)", subclass); 1667 } 1668 } else { 1669 printf(", subclass=0x%02x", subclass); 1670 } 1671 1672 data = pci_conf_read (tag, PCI_INTERRUPT_REG); 1673 pciint = PCI_INTERRUPT_PIN_EXTRACT(data); 1674 1675 if (pciint) { 1676 1677 printf (" int %c irq ", 0x60+pciint); 1678 1679 irq = PCI_INTERRUPT_LINE_EXTRACT(data); 1680 1681 /* 1682 ** If it's zero, the isa irq number is unknown, 1683 ** and we cannot bind the pci interrupt. 1684 */ 1685 1686 if (irq && (irq != 0xff)) 1687 printf ("%d", irq); 1688 else 1689 printf ("??"); 1690 }; 1691 1692 if (class != (PCI_CLASS_BRIDGE >> 24)) 1693 printf (" [no driver assigned]"); 1694 printf ("\n"); 1695 1696 if (bootverbose) { 1697 if (class == (PCI_CLASS_BRIDGE >> 24)) { 1698 printf ("configuration space registers:"); 1699 for (reg = 0; reg < 0x100; reg+=4) { 1700 if ((reg & 0x0f) == 0) printf ("\n%02x:\t", reg); 1701 printf ("%08x ", pci_conf_read (tag, reg)); 1702 } 1703 printf ("\n"); 1704 } else { 1705 for (reg=PCI_MAP_REG_START; reg<PCI_MAP_REG_END; reg+=4) { 1706 data = pci_conf_read (tag, reg); 1707 if ((data&~7)==0) continue; 1708 switch (data&7) { 1709 1710 case 1: 1711 case 5: 1712 printf ("\tmap(%x): io(%04lx)\n", 1713 reg, data & ~3); 1714 break; 1715 case 0: 1716 printf ("\tmap(%x): mem32(%08lx)\n", 1717 reg, data & ~7); 1718 break; 1719 case 2: 1720 printf ("\tmap(%x): mem20(%05lx)\n", 1721 reg, data & ~7); 1722 break; 1723 case 4: 1724 printf ("\tmap(%x): mem64(%08x%08lx)\n", 1725 reg, pci_conf_read (tag, reg +4), data & ~7); 1726 reg += 4; 1727 break; 1728 } 1729 } 1730 } 1731 } 1732 } 1733 1734 /* 1735 * This is the user interface to the PCI configuration space. 1736 */ 1737 static struct pci_conf *pci_dev_list; 1738 static unsigned pci_dev_list_count; 1739 static unsigned pci_dev_list_size; 1740 1741 static void 1742 pci_remember(int bus, int dev, int func) 1743 { 1744 struct pci_conf *p; 1745 pcici_t tag; 1746 1747 if (++pci_dev_list_count > pci_dev_list_size) { 1748 struct pci_conf *new; 1749 1750 pci_dev_list_size += 8; 1751 MALLOC(new, struct pci_conf *, pci_dev_list_size * sizeof *new, 1752 M_DEVL, M_NOWAIT); 1753 if (!new) { 1754 pci_dev_list_size -= 8; 1755 pci_dev_list_count--; 1756 return; 1757 } 1758 1759 if (pci_dev_list) { 1760 bcopy(pci_dev_list, new, ((pci_dev_list_size - 8) * 1761 sizeof *new)); 1762 FREE(pci_dev_list, M_DEVL); 1763 } 1764 pci_dev_list = new; 1765 } 1766 1767 p = &pci_dev_list[pci_dev_list_count - 1]; 1768 p->pc_sel.pc_bus = bus; 1769 p->pc_sel.pc_dev = dev; 1770 p->pc_sel.pc_func = func; 1771 tag = pcibus->pb_tag (bus, dev, func); 1772 p->pc_devid = pci_conf_read(tag, PCI_ID_REG); 1773 p->pc_subid = pci_conf_read(tag, PCI_SUBID_REG); 1774 p->pc_class = pci_conf_read(tag, PCI_CLASS_REG); 1775 } 1776 1777 static int 1778 pci_open(dev_t dev, int oflags, int devtype, struct proc *p) 1779 { 1780 if ((oflags & FWRITE) && securelevel > 0) { 1781 return EPERM; 1782 } 1783 1784 return 0; 1785 } 1786 1787 static int 1788 pci_close(dev_t dev, int flag, int devtype, struct proc *p) 1789 { 1790 return 0; 1791 } 1792 1793 static int 1794 pci_ioctl(dev_t dev, int cmd, caddr_t data, int flag, struct proc *p) 1795 { 1796 struct pci_conf_io *cio; 1797 struct pci_io *io; 1798 size_t iolen; 1799 int error; 1800 pcici_t tag; 1801 1802 if (cmd != PCIOCGETCONF && !(flag & FWRITE)) 1803 return EPERM; 1804 1805 switch(cmd) { 1806 case PCIOCGETCONF: 1807 cio = (struct pci_conf_io *)data; 1808 iolen = min(cio->pci_len, 1809 pci_dev_list_count * sizeof(struct pci_conf)); 1810 cio->pci_len = pci_dev_list_count * sizeof(struct pci_conf); 1811 1812 error = copyout(pci_dev_list, cio->pci_buf, iolen); 1813 break; 1814 1815 case PCIOCREAD: 1816 io = (struct pci_io *)data; 1817 switch(io->pi_width) { 1818 case 4: 1819 tag = pcibus->pb_tag (io->pi_sel.pc_bus, 1820 io->pi_sel.pc_dev, 1821 io->pi_sel.pc_func); 1822 io->pi_data = pci_conf_read(tag, io->pi_reg); 1823 error = 0; 1824 break; 1825 case 2: 1826 case 1: 1827 default: 1828 error = ENODEV; 1829 break; 1830 } 1831 break; 1832 1833 case PCIOCWRITE: 1834 io = (struct pci_io *)data; 1835 switch(io->pi_width) { 1836 case 4: 1837 tag = pcibus->pb_tag (io->pi_sel.pc_bus, 1838 io->pi_sel.pc_dev, 1839 io->pi_sel.pc_func); 1840 pci_conf_write(tag, io->pi_reg, io->pi_data); 1841 error = 0; 1842 break; 1843 case 2: 1844 case 1: 1845 default: 1846 error = ENODEV; 1847 break; 1848 } 1849 break; 1850 1851 default: 1852 error = ENOTTY; 1853 break; 1854 } 1855 1856 return (error); 1857 } 1858 1859 #define PCI_CDEV 78 1860 1861 static struct cdevsw pcicdev = { 1862 pci_open, pci_close, noread, nowrite, pci_ioctl, nostop, noreset, 1863 nodevtotty, noselect, nommap, nostrategy, "pci", 0, PCI_CDEV 1864 }; 1865 1866 #ifdef DEVFS 1867 static void *pci_devfs_token; 1868 #endif 1869 1870 static void 1871 pci_cdevinit(void *dummy) 1872 { 1873 dev_t dev; 1874 1875 dev = makedev(PCI_CDEV, 0); 1876 cdevsw_add(&dev, &pcicdev, NULL); 1877 #ifdef DEVFS 1878 pci_devfs_token = devfs_add_devswf(&pcicdev, 0, DV_CHR, 1879 UID_ROOT, GID_WHEEL, 0644, "pci"); 1880 #endif 1881 } 1882 1883 SYSINIT(pcidev, SI_SUB_DRIVERS, SI_ORDER_MIDDLE+PCI_CDEV, pci_cdevinit, NULL); 1884 1885 #endif /* NPCI */ 1886