1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 5 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000, BSDi 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice unmodified, this list of conditions, and the following 14 * disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 #include "opt_acpi.h" 33 #include "opt_iommu.h" 34 #include "opt_bus.h" 35 36 #include <sys/param.h> 37 #include <sys/conf.h> 38 #include <sys/endian.h> 39 #include <sys/eventhandler.h> 40 #include <sys/fcntl.h> 41 #include <sys/kernel.h> 42 #include <sys/limits.h> 43 #include <sys/linker.h> 44 #include <sys/malloc.h> 45 #include <sys/module.h> 46 #include <sys/queue.h> 47 #include <sys/sbuf.h> 48 #include <sys/sysctl.h> 49 #include <sys/systm.h> 50 #include <sys/taskqueue.h> 51 #include <sys/tree.h> 52 53 #include <vm/vm.h> 54 #include <vm/pmap.h> 55 #include <vm/vm_extern.h> 56 57 #include <sys/bus.h> 58 #include <machine/bus.h> 59 #include <sys/rman.h> 60 #include <machine/resource.h> 61 #include <machine/stdarg.h> 62 63 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 64 #include <machine/intr_machdep.h> 65 #endif 66 67 #include <sys/pciio.h> 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pci_private.h> 71 72 #ifdef PCI_IOV 73 #include <sys/nv.h> 74 #include <dev/pci/pci_iov_private.h> 75 #endif 76 77 #include <dev/usb/controller/xhcireg.h> 78 #include <dev/usb/controller/ehcireg.h> 79 #include <dev/usb/controller/ohcireg.h> 80 #include <dev/usb/controller/uhcireg.h> 81 82 #include <dev/iommu/iommu.h> 83 84 #include "pcib_if.h" 85 #include "pci_if.h" 86 87 #define PCIR_IS_BIOS(cfg, reg) \ 88 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \ 89 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1)) 90 91 static device_probe_t pci_probe; 92 93 static bus_reset_post_t pci_reset_post; 94 static bus_reset_prepare_t pci_reset_prepare; 95 static bus_reset_child_t pci_reset_child; 96 static bus_hint_device_unit_t pci_hint_device_unit; 97 static bus_remap_intr_t pci_remap_intr_method; 98 99 static pci_get_id_t pci_get_id_method; 100 101 static int pci_has_quirk(uint32_t devid, int quirk); 102 static pci_addr_t pci_mapbase(uint64_t mapreg); 103 static const char *pci_maptype(uint64_t mapreg); 104 static int pci_maprange(uint64_t mapreg); 105 static pci_addr_t pci_rombase(uint64_t mapreg); 106 static int pci_romsize(uint64_t testval); 107 static void pci_fixancient(pcicfgregs *cfg); 108 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...); 109 110 static int pci_porten(device_t dev); 111 static int pci_memen(device_t dev); 112 static void pci_assign_interrupt(device_t bus, device_t dev, 113 int force_route); 114 static int pci_add_map(device_t bus, device_t dev, int reg, 115 struct resource_list *rl, int force, int prefetch); 116 static void pci_load_vendor_data(void); 117 static int pci_describe_parse_line(char **ptr, int *vendor, 118 int *device, char **desc); 119 static char *pci_describe_device(device_t dev); 120 static int pci_modevent(module_t mod, int what, void *arg); 121 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 122 pcicfgregs *cfg); 123 static void pci_read_cap(device_t pcib, pcicfgregs *cfg); 124 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 125 int reg, uint32_t *data); 126 #if 0 127 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 128 int reg, uint32_t data); 129 #endif 130 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 131 static void pci_mask_msix(device_t dev, u_int index); 132 static void pci_unmask_msix(device_t dev, u_int index); 133 static int pci_msi_blacklisted(void); 134 static int pci_msix_blacklisted(void); 135 static void pci_resume_msi(device_t dev); 136 static void pci_resume_msix(device_t dev); 137 static struct pci_devinfo * pci_fill_devinfo(device_t pcib, device_t bus, int d, 138 int b, int s, int f, uint16_t vid, uint16_t did); 139 140 static device_method_t pci_methods[] = { 141 /* Device interface */ 142 DEVMETHOD(device_probe, pci_probe), 143 DEVMETHOD(device_attach, pci_attach), 144 DEVMETHOD(device_detach, pci_detach), 145 DEVMETHOD(device_shutdown, bus_generic_shutdown), 146 DEVMETHOD(device_suspend, bus_generic_suspend), 147 DEVMETHOD(device_resume, pci_resume), 148 149 /* Bus interface */ 150 DEVMETHOD(bus_print_child, pci_print_child), 151 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 152 DEVMETHOD(bus_read_ivar, pci_read_ivar), 153 DEVMETHOD(bus_write_ivar, pci_write_ivar), 154 DEVMETHOD(bus_driver_added, pci_driver_added), 155 DEVMETHOD(bus_setup_intr, pci_setup_intr), 156 DEVMETHOD(bus_teardown_intr, pci_teardown_intr), 157 DEVMETHOD(bus_reset_prepare, pci_reset_prepare), 158 DEVMETHOD(bus_reset_post, pci_reset_post), 159 DEVMETHOD(bus_reset_child, pci_reset_child), 160 161 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag), 162 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 163 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 164 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 165 DEVMETHOD(bus_delete_resource, pci_delete_resource), 166 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 167 DEVMETHOD(bus_adjust_resource, pci_adjust_resource), 168 DEVMETHOD(bus_release_resource, pci_release_resource), 169 DEVMETHOD(bus_activate_resource, pci_activate_resource), 170 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource), 171 DEVMETHOD(bus_map_resource, pci_map_resource), 172 DEVMETHOD(bus_unmap_resource, pci_unmap_resource), 173 DEVMETHOD(bus_child_deleted, pci_child_deleted), 174 DEVMETHOD(bus_child_detached, pci_child_detached), 175 DEVMETHOD(bus_child_pnpinfo, pci_child_pnpinfo_method), 176 DEVMETHOD(bus_child_location, pci_child_location_method), 177 DEVMETHOD(bus_get_device_path, pci_get_device_path_method), 178 DEVMETHOD(bus_hint_device_unit, pci_hint_device_unit), 179 DEVMETHOD(bus_remap_intr, pci_remap_intr_method), 180 DEVMETHOD(bus_suspend_child, pci_suspend_child), 181 DEVMETHOD(bus_resume_child, pci_resume_child), 182 DEVMETHOD(bus_rescan, pci_rescan_method), 183 184 /* PCI interface */ 185 DEVMETHOD(pci_read_config, pci_read_config_method), 186 DEVMETHOD(pci_write_config, pci_write_config_method), 187 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 188 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 189 DEVMETHOD(pci_enable_io, pci_enable_io_method), 190 DEVMETHOD(pci_disable_io, pci_disable_io_method), 191 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 192 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 193 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 194 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 195 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 196 DEVMETHOD(pci_find_cap, pci_find_cap_method), 197 DEVMETHOD(pci_find_next_cap, pci_find_next_cap_method), 198 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 199 DEVMETHOD(pci_find_next_extcap, pci_find_next_extcap_method), 200 DEVMETHOD(pci_find_htcap, pci_find_htcap_method), 201 DEVMETHOD(pci_find_next_htcap, pci_find_next_htcap_method), 202 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method), 203 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method), 204 DEVMETHOD(pci_enable_msi, pci_enable_msi_method), 205 DEVMETHOD(pci_enable_msix, pci_enable_msix_method), 206 DEVMETHOD(pci_disable_msi, pci_disable_msi_method), 207 DEVMETHOD(pci_remap_msix, pci_remap_msix_method), 208 DEVMETHOD(pci_release_msi, pci_release_msi_method), 209 DEVMETHOD(pci_msi_count, pci_msi_count_method), 210 DEVMETHOD(pci_msix_count, pci_msix_count_method), 211 DEVMETHOD(pci_msix_pba_bar, pci_msix_pba_bar_method), 212 DEVMETHOD(pci_msix_table_bar, pci_msix_table_bar_method), 213 DEVMETHOD(pci_get_id, pci_get_id_method), 214 DEVMETHOD(pci_alloc_devinfo, pci_alloc_devinfo_method), 215 DEVMETHOD(pci_child_added, pci_child_added_method), 216 #ifdef PCI_IOV 217 DEVMETHOD(pci_iov_attach, pci_iov_attach_method), 218 DEVMETHOD(pci_iov_detach, pci_iov_detach_method), 219 DEVMETHOD(pci_create_iov_child, pci_create_iov_child_method), 220 #endif 221 222 DEVMETHOD_END 223 }; 224 225 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc)); 226 227 EARLY_DRIVER_MODULE(pci, pcib, pci_driver, pci_modevent, NULL, BUS_PASS_BUS); 228 MODULE_VERSION(pci, 1); 229 230 static char *pci_vendordata; 231 static size_t pci_vendordata_size; 232 233 struct pci_quirk { 234 uint32_t devid; /* Vendor/device of the card */ 235 int type; 236 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 237 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */ 238 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */ 239 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */ 240 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */ 241 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */ 242 #define PCI_QUIRK_REALLOC_BAR 7 /* Can't allocate memory at the default address */ 243 int arg1; 244 int arg2; 245 }; 246 247 static const struct pci_quirk pci_quirks[] = { 248 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */ 249 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 250 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 251 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 252 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 253 254 /* 255 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge 256 * or the CMIC-SL (AKA ServerWorks GC_LE). 257 */ 258 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 259 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 260 261 /* 262 * MSI doesn't work on earlier Intel chipsets including 263 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855. 264 */ 265 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 266 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 267 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 268 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 269 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 270 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 271 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 272 273 /* 274 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX 275 * bridge. 276 */ 277 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 }, 278 279 /* 280 * Some virtualization environments emulate an older chipset 281 * but support MSI just fine. QEMU uses the Intel 82440. 282 */ 283 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 }, 284 285 /* 286 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus 287 * controller depending on SoftPciRst register (PM_IO 0x55 [7]). 288 * It prevents us from attaching hpet(4) when the bit is unset. 289 * Note this quirk only affects SB600 revision A13 and earlier. 290 * For SB600 A21 and later, firmware must set the bit to hide it. 291 * For SB700 and later, it is unused and hardcoded to zero. 292 */ 293 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 }, 294 295 /* 296 * Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have 297 * a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit 298 * of the command register is set. 299 */ 300 { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 301 { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 302 { 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 303 { 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 304 { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, 305 306 /* 307 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't 308 * issue MSI interrupts with PCIM_CMD_INTxDIS set either. 309 */ 310 { 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */ 311 { 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */ 312 { 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */ 313 { 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */ 314 { 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */ 315 { 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */ 316 317 /* 318 * HPE Gen 10 VGA has a memory range that can't be allocated in the 319 * expected place. 320 */ 321 { 0x98741002, PCI_QUIRK_REALLOC_BAR, 0, 0 }, 322 { 0 } 323 }; 324 325 /* map register information */ 326 #define PCI_MAPMEM 0x01 /* memory map */ 327 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 328 #define PCI_MAPPORT 0x04 /* port map */ 329 330 struct devlist pci_devq; 331 uint32_t pci_generation; 332 uint32_t pci_numdevs = 0; 333 static int pcie_chipset, pcix_chipset; 334 335 /* sysctl vars */ 336 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 337 "PCI bus tuning parameters"); 338 339 static int pci_enable_io_modes = 1; 340 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RWTUN, 341 &pci_enable_io_modes, 1, 342 "Enable I/O and memory bits in the config register. Some BIOSes do not" 343 " enable these bits correctly. We'd like to do this all the time, but" 344 " there are some peripherals that this causes problems with."); 345 346 static int pci_do_realloc_bars = 1; 347 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RWTUN, 348 &pci_do_realloc_bars, 0, 349 "Attempt to allocate a new range for any BARs whose original " 350 "firmware-assigned ranges fail to allocate during the initial device scan."); 351 352 static int pci_do_power_nodriver = 0; 353 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RWTUN, 354 &pci_do_power_nodriver, 0, 355 "Place a function into D3 state when no driver attaches to it. 0 means" 356 " disable. 1 means conservatively place function into D3 state. 2 means" 357 " aggressively place function into D3 state. 3 means put absolutely" 358 " everything in D3 state."); 359 360 int pci_do_power_resume = 1; 361 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RWTUN, 362 &pci_do_power_resume, 1, 363 "Transition from D3 -> D0 on resume."); 364 365 int pci_do_power_suspend = 1; 366 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RWTUN, 367 &pci_do_power_suspend, 1, 368 "Transition from D0 -> D3 on suspend."); 369 370 static int pci_do_msi = 1; 371 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RWTUN, &pci_do_msi, 1, 372 "Enable support for MSI interrupts"); 373 374 static int pci_do_msix = 1; 375 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RWTUN, &pci_do_msix, 1, 376 "Enable support for MSI-X interrupts"); 377 378 static int pci_msix_rewrite_table = 0; 379 SYSCTL_INT(_hw_pci, OID_AUTO, msix_rewrite_table, CTLFLAG_RWTUN, 380 &pci_msix_rewrite_table, 0, 381 "Rewrite entire MSI-X table when updating MSI-X entries"); 382 383 static int pci_honor_msi_blacklist = 1; 384 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RDTUN, 385 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X"); 386 387 #if defined(__i386__) || defined(__amd64__) 388 static int pci_usb_takeover = 1; 389 #else 390 static int pci_usb_takeover = 0; 391 #endif 392 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN, 393 &pci_usb_takeover, 1, 394 "Enable early takeover of USB controllers. Disable this if you depend on" 395 " BIOS emulation of USB devices, that is you use USB devices (like" 396 " keyboard or mouse) but do not load USB drivers"); 397 398 static int pci_clear_bars; 399 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0, 400 "Ignore firmware-assigned resources for BARs."); 401 402 static int pci_clear_buses; 403 SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0, 404 "Ignore firmware-assigned bus numbers."); 405 406 static int pci_enable_ari = 1; 407 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari, 408 0, "Enable support for PCIe Alternative RID Interpretation"); 409 410 /* 411 * Some x86 firmware only enables PCIe hotplug if we claim to support aspm, 412 * however enabling it breaks some arm64 firmware as it powers off devices. 413 */ 414 #if defined(__i386__) || defined(__amd64__) 415 int pci_enable_aspm = 1; 416 #else 417 int pci_enable_aspm = 0; 418 #endif 419 SYSCTL_INT(_hw_pci, OID_AUTO, enable_aspm, CTLFLAG_RDTUN, &pci_enable_aspm, 420 0, "Enable support for PCIe Active State Power Management"); 421 422 static int pci_clear_aer_on_attach = 0; 423 SYSCTL_INT(_hw_pci, OID_AUTO, clear_aer_on_attach, CTLFLAG_RWTUN, 424 &pci_clear_aer_on_attach, 0, 425 "Clear port and device AER state on driver attach"); 426 427 static bool pci_enable_mps_tune = true; 428 SYSCTL_BOOL(_hw_pci, OID_AUTO, enable_mps_tune, CTLFLAG_RWTUN, 429 &pci_enable_mps_tune, 1, 430 "Enable tuning of MPS(maximum payload size)." ); 431 432 static bool pci_intx_reroute = true; 433 SYSCTL_BOOL(_hw_pci, OID_AUTO, intx_reroute, CTLFLAG_RWTUN, 434 &pci_intx_reroute, 0, "Re-route INTx interrupts when scanning devices"); 435 436 static int 437 pci_has_quirk(uint32_t devid, int quirk) 438 { 439 const struct pci_quirk *q; 440 441 for (q = &pci_quirks[0]; q->devid; q++) { 442 if (q->devid == devid && q->type == quirk) 443 return (1); 444 } 445 return (0); 446 } 447 448 /* Find a device_t by bus/slot/function in domain 0 */ 449 450 device_t 451 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 452 { 453 454 return (pci_find_dbsf(0, bus, slot, func)); 455 } 456 457 /* Find a device_t by domain/bus/slot/function */ 458 459 device_t 460 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func) 461 { 462 struct pci_devinfo *dinfo = NULL; 463 464 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 465 if ((dinfo->cfg.domain == domain) && 466 (dinfo->cfg.bus == bus) && 467 (dinfo->cfg.slot == slot) && 468 (dinfo->cfg.func == func)) { 469 break; 470 } 471 } 472 473 return (dinfo != NULL ? dinfo->cfg.dev : NULL); 474 } 475 476 /* Find a device_t by vendor/device ID */ 477 478 device_t 479 pci_find_device(uint16_t vendor, uint16_t device) 480 { 481 struct pci_devinfo *dinfo; 482 483 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 484 if ((dinfo->cfg.vendor == vendor) && 485 (dinfo->cfg.device == device)) { 486 return (dinfo->cfg.dev); 487 } 488 } 489 490 return (NULL); 491 } 492 493 device_t 494 pci_find_class(uint8_t class, uint8_t subclass) 495 { 496 struct pci_devinfo *dinfo; 497 498 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 499 if (dinfo->cfg.baseclass == class && 500 dinfo->cfg.subclass == subclass) { 501 return (dinfo->cfg.dev); 502 } 503 } 504 505 return (NULL); 506 } 507 508 device_t 509 pci_find_class_from(uint8_t class, uint8_t subclass, device_t from) 510 { 511 struct pci_devinfo *dinfo; 512 bool found = false; 513 514 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 515 if (from != NULL && found == false) { 516 if (from != dinfo->cfg.dev) 517 continue; 518 found = true; 519 continue; 520 } 521 if (dinfo->cfg.baseclass == class && 522 dinfo->cfg.subclass == subclass) { 523 return (dinfo->cfg.dev); 524 } 525 } 526 527 return (NULL); 528 } 529 530 device_t 531 pci_find_base_class_from(uint8_t class, device_t from) 532 { 533 struct pci_devinfo *dinfo; 534 bool found = false; 535 536 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 537 if (from != NULL && found == false) { 538 if (from != dinfo->cfg.dev) 539 continue; 540 found = true; 541 continue; 542 } 543 if (dinfo->cfg.baseclass == class) { 544 return (dinfo->cfg.dev); 545 } 546 } 547 548 return (NULL); 549 } 550 551 static int 552 pci_printf(pcicfgregs *cfg, const char *fmt, ...) 553 { 554 va_list ap; 555 int retval; 556 557 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot, 558 cfg->func); 559 va_start(ap, fmt); 560 retval += vprintf(fmt, ap); 561 va_end(ap); 562 return (retval); 563 } 564 565 /* return base address of memory or port map */ 566 567 static pci_addr_t 568 pci_mapbase(uint64_t mapreg) 569 { 570 571 if (PCI_BAR_MEM(mapreg)) 572 return (mapreg & PCIM_BAR_MEM_BASE); 573 else 574 return (mapreg & PCIM_BAR_IO_BASE); 575 } 576 577 /* return map type of memory or port map */ 578 579 static const char * 580 pci_maptype(uint64_t mapreg) 581 { 582 583 if (PCI_BAR_IO(mapreg)) 584 return ("I/O Port"); 585 if (mapreg & PCIM_BAR_MEM_PREFETCH) 586 return ("Prefetchable Memory"); 587 return ("Memory"); 588 } 589 590 /* return log2 of map size decoded for memory or port map */ 591 592 int 593 pci_mapsize(uint64_t testval) 594 { 595 int ln2size; 596 597 testval = pci_mapbase(testval); 598 ln2size = 0; 599 if (testval != 0) { 600 while ((testval & 1) == 0) 601 { 602 ln2size++; 603 testval >>= 1; 604 } 605 } 606 return (ln2size); 607 } 608 609 /* return base address of device ROM */ 610 611 static pci_addr_t 612 pci_rombase(uint64_t mapreg) 613 { 614 615 return (mapreg & PCIM_BIOS_ADDR_MASK); 616 } 617 618 /* return log2 of map size decided for device ROM */ 619 620 static int 621 pci_romsize(uint64_t testval) 622 { 623 int ln2size; 624 625 testval = pci_rombase(testval); 626 ln2size = 0; 627 if (testval != 0) { 628 while ((testval & 1) == 0) 629 { 630 ln2size++; 631 testval >>= 1; 632 } 633 } 634 return (ln2size); 635 } 636 637 /* return log2 of address range supported by map register */ 638 639 static int 640 pci_maprange(uint64_t mapreg) 641 { 642 int ln2range = 0; 643 644 if (PCI_BAR_IO(mapreg)) 645 ln2range = 32; 646 else 647 switch (mapreg & PCIM_BAR_MEM_TYPE) { 648 case PCIM_BAR_MEM_32: 649 ln2range = 32; 650 break; 651 case PCIM_BAR_MEM_1MB: 652 ln2range = 20; 653 break; 654 case PCIM_BAR_MEM_64: 655 ln2range = 64; 656 break; 657 } 658 return (ln2range); 659 } 660 661 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 662 663 static void 664 pci_fixancient(pcicfgregs *cfg) 665 { 666 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL) 667 return; 668 669 /* PCI to PCI bridges use header type 1 */ 670 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 671 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE; 672 } 673 674 /* extract header type specific config data */ 675 676 static void 677 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 678 { 679 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 680 switch (cfg->hdrtype & PCIM_HDRTYPE) { 681 case PCIM_HDRTYPE_NORMAL: 682 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 683 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 684 cfg->mingnt = REG(PCIR_MINGNT, 1); 685 cfg->maxlat = REG(PCIR_MAXLAT, 1); 686 cfg->nummaps = PCI_MAXMAPS_0; 687 break; 688 case PCIM_HDRTYPE_BRIDGE: 689 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1); 690 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1); 691 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1); 692 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1); 693 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2); 694 cfg->nummaps = PCI_MAXMAPS_1; 695 break; 696 case PCIM_HDRTYPE_CARDBUS: 697 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1); 698 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1); 699 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1); 700 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1); 701 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2); 702 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 703 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 704 cfg->nummaps = PCI_MAXMAPS_2; 705 break; 706 } 707 #undef REG 708 } 709 710 /* read configuration header into pcicfgregs structure */ 711 struct pci_devinfo * 712 pci_read_device(device_t pcib, device_t bus, int d, int b, int s, int f) 713 { 714 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 715 uint16_t vid, did; 716 717 vid = REG(PCIR_VENDOR, 2); 718 if (vid == PCIV_INVALID) 719 return (NULL); 720 721 did = REG(PCIR_DEVICE, 2); 722 723 return (pci_fill_devinfo(pcib, bus, d, b, s, f, vid, did)); 724 } 725 726 struct pci_devinfo * 727 pci_alloc_devinfo_method(device_t dev) 728 { 729 730 return (malloc(sizeof(struct pci_devinfo), M_DEVBUF, 731 M_WAITOK | M_ZERO)); 732 } 733 734 static struct pci_devinfo * 735 pci_fill_devinfo(device_t pcib, device_t bus, int d, int b, int s, int f, 736 uint16_t vid, uint16_t did) 737 { 738 struct pci_devinfo *devlist_entry; 739 pcicfgregs *cfg; 740 741 devlist_entry = PCI_ALLOC_DEVINFO(bus); 742 743 cfg = &devlist_entry->cfg; 744 745 cfg->domain = d; 746 cfg->bus = b; 747 cfg->slot = s; 748 cfg->func = f; 749 cfg->vendor = vid; 750 cfg->device = did; 751 cfg->cmdreg = REG(PCIR_COMMAND, 2); 752 cfg->statreg = REG(PCIR_STATUS, 2); 753 cfg->baseclass = REG(PCIR_CLASS, 1); 754 cfg->subclass = REG(PCIR_SUBCLASS, 1); 755 cfg->progif = REG(PCIR_PROGIF, 1); 756 cfg->revid = REG(PCIR_REVID, 1); 757 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 758 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 759 cfg->lattimer = REG(PCIR_LATTIMER, 1); 760 cfg->intpin = REG(PCIR_INTPIN, 1); 761 cfg->intline = REG(PCIR_INTLINE, 1); 762 763 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 764 cfg->hdrtype &= ~PCIM_MFDEV; 765 STAILQ_INIT(&cfg->maps); 766 767 cfg->iov = NULL; 768 769 pci_fixancient(cfg); 770 pci_hdrtypedata(pcib, b, s, f, cfg); 771 772 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 773 pci_read_cap(pcib, cfg); 774 775 STAILQ_INSERT_TAIL(&pci_devq, devlist_entry, pci_links); 776 777 devlist_entry->conf.pc_sel.pc_domain = cfg->domain; 778 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 779 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 780 devlist_entry->conf.pc_sel.pc_func = cfg->func; 781 devlist_entry->conf.pc_hdr = cfg->hdrtype; 782 783 devlist_entry->conf.pc_subvendor = cfg->subvendor; 784 devlist_entry->conf.pc_subdevice = cfg->subdevice; 785 devlist_entry->conf.pc_vendor = cfg->vendor; 786 devlist_entry->conf.pc_device = cfg->device; 787 788 devlist_entry->conf.pc_class = cfg->baseclass; 789 devlist_entry->conf.pc_subclass = cfg->subclass; 790 devlist_entry->conf.pc_progif = cfg->progif; 791 devlist_entry->conf.pc_revid = cfg->revid; 792 793 pci_numdevs++; 794 pci_generation++; 795 796 return (devlist_entry); 797 } 798 #undef REG 799 800 static void 801 pci_ea_fill_info(device_t pcib, pcicfgregs *cfg) 802 { 803 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \ 804 cfg->ea.ea_location + (n), w) 805 int num_ent; 806 int ptr; 807 int a, b; 808 uint32_t val; 809 int ent_size; 810 uint32_t dw[4]; 811 uint64_t base, max_offset; 812 struct pci_ea_entry *eae; 813 814 if (cfg->ea.ea_location == 0) 815 return; 816 817 STAILQ_INIT(&cfg->ea.ea_entries); 818 819 /* Determine the number of entries */ 820 num_ent = REG(PCIR_EA_NUM_ENT, 2); 821 num_ent &= PCIM_EA_NUM_ENT_MASK; 822 823 /* Find the first entry to care of */ 824 ptr = PCIR_EA_FIRST_ENT; 825 826 /* Skip DWORD 2 for type 1 functions */ 827 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) 828 ptr += 4; 829 830 for (a = 0; a < num_ent; a++) { 831 eae = malloc(sizeof(*eae), M_DEVBUF, M_WAITOK | M_ZERO); 832 eae->eae_cfg_offset = cfg->ea.ea_location + ptr; 833 834 /* Read a number of dwords in the entry */ 835 val = REG(ptr, 4); 836 ptr += 4; 837 ent_size = (val & PCIM_EA_ES); 838 839 for (b = 0; b < ent_size; b++) { 840 dw[b] = REG(ptr, 4); 841 ptr += 4; 842 } 843 844 eae->eae_flags = val; 845 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 846 847 base = dw[0] & PCIM_EA_FIELD_MASK; 848 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 849 b = 2; 850 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 851 base |= (uint64_t)dw[b] << 32UL; 852 b++; 853 } 854 if (((dw[1] & PCIM_EA_IS_64) != 0) 855 && (b < ent_size)) { 856 max_offset |= (uint64_t)dw[b] << 32UL; 857 b++; 858 } 859 860 eae->eae_base = base; 861 eae->eae_max_offset = max_offset; 862 863 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link); 864 865 if (bootverbose) { 866 printf("PCI(EA) dev %04x:%04x, bei %d, flags #%x, base #%jx, max_offset #%jx\n", 867 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags, 868 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset); 869 } 870 } 871 } 872 #undef REG 873 874 static void 875 pci_read_cap(device_t pcib, pcicfgregs *cfg) 876 { 877 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 878 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 879 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 880 uint64_t addr; 881 #endif 882 uint32_t val; 883 int ptr, nextptr, ptrptr; 884 885 switch (cfg->hdrtype & PCIM_HDRTYPE) { 886 case PCIM_HDRTYPE_NORMAL: 887 case PCIM_HDRTYPE_BRIDGE: 888 ptrptr = PCIR_CAP_PTR; 889 break; 890 case PCIM_HDRTYPE_CARDBUS: 891 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 892 break; 893 default: 894 return; /* no extended capabilities support */ 895 } 896 nextptr = REG(ptrptr, 1); /* sanity check? */ 897 898 /* 899 * Read capability entries. 900 */ 901 while (nextptr != 0) { 902 /* Sanity check */ 903 if (nextptr > 255) { 904 printf("illegal PCI extended capability offset %d\n", 905 nextptr); 906 return; 907 } 908 /* Find the next entry */ 909 ptr = nextptr; 910 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 911 912 /* Process this entry */ 913 switch (REG(ptr + PCICAP_ID, 1)) { 914 case PCIY_PMG: /* PCI power management */ 915 cfg->pp.pp_location = ptr; 916 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 917 break; 918 case PCIY_HT: /* HyperTransport */ 919 /* Determine HT-specific capability type. */ 920 val = REG(ptr + PCIR_HT_COMMAND, 2); 921 922 if ((val & 0xe000) == PCIM_HTCAP_SLAVE) 923 cfg->ht.ht_slave = ptr; 924 925 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__) 926 switch (val & PCIM_HTCMD_CAP_MASK) { 927 case PCIM_HTCAP_MSI_MAPPING: 928 if (!(val & PCIM_HTCMD_MSI_FIXED)) { 929 /* Sanity check the mapping window. */ 930 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 931 4); 932 addr <<= 32; 933 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 934 4); 935 if (addr != MSI_INTEL_ADDR_BASE) 936 device_printf(pcib, 937 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n", 938 cfg->domain, cfg->bus, 939 cfg->slot, cfg->func, 940 (long long)addr); 941 } else 942 addr = MSI_INTEL_ADDR_BASE; 943 944 cfg->ht.ht_msimap = ptr; 945 cfg->ht.ht_msictrl = val; 946 cfg->ht.ht_msiaddr = addr; 947 break; 948 } 949 #endif 950 break; 951 case PCIY_MSI: /* PCI MSI */ 952 cfg->msi.msi_location = ptr; 953 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 954 break; 955 case PCIY_MSIX: /* PCI MSI-X */ 956 cfg->msix.msix_location = ptr; 957 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); 958 val = REG(ptr + PCIR_MSIX_TABLE, 4); 959 cfg->msix.msix_table_bar = PCIR_BAR(val & 960 PCIM_MSIX_BIR_MASK); 961 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; 962 val = REG(ptr + PCIR_MSIX_PBA, 4); 963 cfg->msix.msix_pba_bar = PCIR_BAR(val & 964 PCIM_MSIX_BIR_MASK); 965 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; 966 break; 967 case PCIY_VPD: /* PCI Vital Product Data */ 968 cfg->vpd.vpd_reg = ptr; 969 break; 970 case PCIY_SUBVENDOR: 971 /* Should always be true. */ 972 if ((cfg->hdrtype & PCIM_HDRTYPE) == 973 PCIM_HDRTYPE_BRIDGE) { 974 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4); 975 cfg->subvendor = val & 0xffff; 976 cfg->subdevice = val >> 16; 977 } 978 break; 979 case PCIY_PCIX: /* PCI-X */ 980 /* 981 * Assume we have a PCI-X chipset if we have 982 * at least one PCI-PCI bridge with a PCI-X 983 * capability. Note that some systems with 984 * PCI-express or HT chipsets might match on 985 * this check as well. 986 */ 987 if ((cfg->hdrtype & PCIM_HDRTYPE) == 988 PCIM_HDRTYPE_BRIDGE) 989 pcix_chipset = 1; 990 cfg->pcix.pcix_location = ptr; 991 break; 992 case PCIY_EXPRESS: /* PCI-express */ 993 /* 994 * Assume we have a PCI-express chipset if we have 995 * at least one PCI-express device. 996 */ 997 pcie_chipset = 1; 998 cfg->pcie.pcie_location = ptr; 999 val = REG(ptr + PCIER_FLAGS, 2); 1000 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; 1001 break; 1002 case PCIY_EA: /* Enhanced Allocation */ 1003 cfg->ea.ea_location = ptr; 1004 pci_ea_fill_info(pcib, cfg); 1005 break; 1006 default: 1007 break; 1008 } 1009 } 1010 1011 #if defined(__powerpc__) 1012 /* 1013 * Enable the MSI mapping window for all HyperTransport 1014 * slaves. PCI-PCI bridges have their windows enabled via 1015 * PCIB_MAP_MSI(). 1016 */ 1017 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 && 1018 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) { 1019 device_printf(pcib, 1020 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n", 1021 cfg->domain, cfg->bus, cfg->slot, cfg->func); 1022 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 1023 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl, 1024 2); 1025 } 1026 #endif 1027 /* REG and WREG use carry through to next functions */ 1028 } 1029 1030 /* 1031 * PCI Vital Product Data 1032 */ 1033 1034 #define PCI_VPD_TIMEOUT 1000000 1035 1036 static int 1037 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data) 1038 { 1039 int count = PCI_VPD_TIMEOUT; 1040 1041 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1042 1043 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2); 1044 1045 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) { 1046 if (--count < 0) 1047 return (ENXIO); 1048 DELAY(1); /* limit looping */ 1049 } 1050 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4)); 1051 1052 return (0); 1053 } 1054 1055 #if 0 1056 static int 1057 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 1058 { 1059 int count = PCI_VPD_TIMEOUT; 1060 1061 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 1062 1063 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4); 1064 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2); 1065 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) { 1066 if (--count < 0) 1067 return (ENXIO); 1068 DELAY(1); /* limit looping */ 1069 } 1070 1071 return (0); 1072 } 1073 #endif 1074 1075 #undef PCI_VPD_TIMEOUT 1076 1077 struct vpd_readstate { 1078 device_t pcib; 1079 pcicfgregs *cfg; 1080 uint32_t val; 1081 int bytesinval; 1082 int off; 1083 uint8_t cksum; 1084 }; 1085 1086 /* return 0 and one byte in *data if no read error, -1 else */ 1087 static int 1088 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data) 1089 { 1090 uint32_t reg; 1091 uint8_t byte; 1092 1093 if (vrs->bytesinval == 0) { 1094 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®)) 1095 return (-1); 1096 vrs->val = le32toh(reg); 1097 vrs->off += 4; 1098 byte = vrs->val & 0xff; 1099 vrs->bytesinval = 3; 1100 } else { 1101 vrs->val = vrs->val >> 8; 1102 byte = vrs->val & 0xff; 1103 vrs->bytesinval--; 1104 } 1105 1106 vrs->cksum += byte; 1107 *data = byte; 1108 return (0); 1109 } 1110 1111 /* return 0 on match, -1 and "unget" byte on no match */ 1112 static int 1113 vpd_expectbyte(struct vpd_readstate *vrs, uint8_t expected) 1114 { 1115 uint8_t data; 1116 1117 if (vpd_nextbyte(vrs, &data) != 0) 1118 return (-1); 1119 1120 if (data == expected) 1121 return (0); 1122 1123 vrs->cksum -= data; 1124 vrs->val = (vrs->val << 8) + data; 1125 vrs->bytesinval++; 1126 return (-1); 1127 } 1128 1129 /* return size if tag matches, -1 on no match, -2 on read error */ 1130 static int 1131 vpd_read_tag_size(struct vpd_readstate *vrs, uint8_t vpd_tag) 1132 { 1133 uint8_t byte1, byte2; 1134 1135 if (vpd_expectbyte(vrs, vpd_tag) != 0) 1136 return (-1); 1137 1138 if ((vpd_tag & 0x80) == 0) 1139 return (vpd_tag & 0x07); 1140 1141 if (vpd_nextbyte(vrs, &byte1) != 0) 1142 return (-2); 1143 if (vpd_nextbyte(vrs, &byte2) != 0) 1144 return (-2); 1145 1146 return ((byte2 << 8) + byte1); 1147 } 1148 1149 /* (re)allocate buffer in multiples of 8 elements */ 1150 static void* 1151 alloc_buffer(void* buffer, size_t element_size, int needed) 1152 { 1153 int alloc, new_alloc; 1154 1155 alloc = roundup2(needed, 8); 1156 new_alloc = roundup2(needed + 1, 8); 1157 if (alloc != new_alloc) { 1158 buffer = reallocf(buffer, 1159 new_alloc * element_size, M_DEVBUF, M_WAITOK | M_ZERO); 1160 } 1161 1162 return (buffer); 1163 } 1164 1165 /* read VPD keyword and return element size, return -1 on read error */ 1166 static int 1167 vpd_read_elem_head(struct vpd_readstate *vrs, char keyword[2]) 1168 { 1169 uint8_t data; 1170 1171 if (vpd_nextbyte(vrs, &keyword[0]) != 0) 1172 return (-1); 1173 if (vpd_nextbyte(vrs, &keyword[1]) != 0) 1174 return (-1); 1175 if (vpd_nextbyte(vrs, &data) != 0) 1176 return (-1); 1177 1178 return (data); 1179 } 1180 1181 /* read VPD data element of given size into allocated buffer */ 1182 static char * 1183 vpd_read_value(struct vpd_readstate *vrs, int size) 1184 { 1185 int i; 1186 char char1; 1187 char *value; 1188 1189 value = malloc(size + 1, M_DEVBUF, M_WAITOK); 1190 for (i = 0; i < size; i++) { 1191 if (vpd_nextbyte(vrs, &char1) != 0) { 1192 free(value, M_DEVBUF); 1193 return (NULL); 1194 } 1195 value[i] = char1; 1196 } 1197 value[size] = '\0'; 1198 1199 return (value); 1200 } 1201 1202 /* read VPD into *keyword and *value, return length of data element */ 1203 static int 1204 vpd_read_elem_data(struct vpd_readstate *vrs, char keyword[2], char **value, int maxlen) 1205 { 1206 int len; 1207 1208 len = vpd_read_elem_head(vrs, keyword); 1209 if (len < 0 || len > maxlen) 1210 return (-1); 1211 *value = vpd_read_value(vrs, len); 1212 1213 return (len); 1214 } 1215 1216 /* subtract all data following first byte from checksum of RV element */ 1217 static void 1218 vpd_fixup_cksum(struct vpd_readstate *vrs, char *rvstring, int len) 1219 { 1220 int i; 1221 uint8_t fixup; 1222 1223 fixup = 0; 1224 for (i = 1; i < len; i++) 1225 fixup += rvstring[i]; 1226 vrs->cksum -= fixup; 1227 } 1228 1229 /* fetch one read-only element and return size of heading + data */ 1230 static int 1231 next_vpd_ro_elem(struct vpd_readstate *vrs, int maxsize) 1232 { 1233 struct pcicfg_vpd *vpd; 1234 pcicfgregs *cfg; 1235 struct vpd_readonly *vpd_ros; 1236 int len; 1237 1238 cfg = vrs->cfg; 1239 vpd = &cfg->vpd; 1240 1241 if (maxsize < 3) 1242 return (-1); 1243 vpd->vpd_ros = alloc_buffer(vpd->vpd_ros, sizeof(*vpd->vpd_ros), vpd->vpd_rocnt); 1244 vpd_ros = &vpd->vpd_ros[vpd->vpd_rocnt]; 1245 maxsize -= 3; 1246 len = vpd_read_elem_data(vrs, vpd_ros->keyword, &vpd_ros->value, maxsize); 1247 if (vpd_ros->value == NULL) 1248 return (-1); 1249 vpd_ros->len = len; 1250 if (vpd_ros->keyword[0] == 'R' && vpd_ros->keyword[1] == 'V') { 1251 vpd_fixup_cksum(vrs, vpd_ros->value, len); 1252 if (vrs->cksum != 0) { 1253 pci_printf(cfg, 1254 "invalid VPD checksum %#hhx\n", vrs->cksum); 1255 return (-1); 1256 } 1257 } 1258 vpd->vpd_rocnt++; 1259 1260 return (len + 3); 1261 } 1262 1263 /* fetch one writable element and return size of heading + data */ 1264 static int 1265 next_vpd_rw_elem(struct vpd_readstate *vrs, int maxsize) 1266 { 1267 struct pcicfg_vpd *vpd; 1268 pcicfgregs *cfg; 1269 struct vpd_write *vpd_w; 1270 int len; 1271 1272 cfg = vrs->cfg; 1273 vpd = &cfg->vpd; 1274 1275 if (maxsize < 3) 1276 return (-1); 1277 vpd->vpd_w = alloc_buffer(vpd->vpd_w, sizeof(*vpd->vpd_w), vpd->vpd_wcnt); 1278 if (vpd->vpd_w == NULL) { 1279 pci_printf(cfg, "out of memory"); 1280 return (-1); 1281 } 1282 vpd_w = &vpd->vpd_w[vpd->vpd_wcnt]; 1283 maxsize -= 3; 1284 vpd_w->start = vrs->off + 3 - vrs->bytesinval; 1285 len = vpd_read_elem_data(vrs, vpd_w->keyword, &vpd_w->value, maxsize); 1286 if (vpd_w->value == NULL) 1287 return (-1); 1288 vpd_w->len = len; 1289 vpd->vpd_wcnt++; 1290 1291 return (len + 3); 1292 } 1293 1294 /* free all memory allocated for VPD data */ 1295 static void 1296 vpd_free(struct pcicfg_vpd *vpd) 1297 { 1298 int i; 1299 1300 free(vpd->vpd_ident, M_DEVBUF); 1301 for (i = 0; i < vpd->vpd_rocnt; i++) 1302 free(vpd->vpd_ros[i].value, M_DEVBUF); 1303 free(vpd->vpd_ros, M_DEVBUF); 1304 vpd->vpd_rocnt = 0; 1305 for (i = 0; i < vpd->vpd_wcnt; i++) 1306 free(vpd->vpd_w[i].value, M_DEVBUF); 1307 free(vpd->vpd_w, M_DEVBUF); 1308 vpd->vpd_wcnt = 0; 1309 } 1310 1311 #define VPD_TAG_END ((0x0f << 3) | 0) /* small tag, len == 0 */ 1312 #define VPD_TAG_IDENT (0x02 | 0x80) /* large tag */ 1313 #define VPD_TAG_RO (0x10 | 0x80) /* large tag */ 1314 #define VPD_TAG_RW (0x11 | 0x80) /* large tag */ 1315 1316 static int 1317 pci_parse_vpd(device_t pcib, pcicfgregs *cfg) 1318 { 1319 struct vpd_readstate vrs; 1320 int cksumvalid; 1321 int size, elem_size; 1322 1323 /* init vpd reader */ 1324 vrs.bytesinval = 0; 1325 vrs.off = 0; 1326 vrs.pcib = pcib; 1327 vrs.cfg = cfg; 1328 vrs.cksum = 0; 1329 1330 /* read VPD ident element - mandatory */ 1331 size = vpd_read_tag_size(&vrs, VPD_TAG_IDENT); 1332 if (size <= 0) { 1333 pci_printf(cfg, "no VPD ident found\n"); 1334 return (0); 1335 } 1336 cfg->vpd.vpd_ident = vpd_read_value(&vrs, size); 1337 if (cfg->vpd.vpd_ident == NULL) { 1338 pci_printf(cfg, "error accessing VPD ident data\n"); 1339 return (0); 1340 } 1341 1342 /* read VPD RO elements - mandatory */ 1343 size = vpd_read_tag_size(&vrs, VPD_TAG_RO); 1344 if (size <= 0) { 1345 pci_printf(cfg, "no read-only VPD data found\n"); 1346 return (0); 1347 } 1348 while (size > 0) { 1349 elem_size = next_vpd_ro_elem(&vrs, size); 1350 if (elem_size < 0) { 1351 pci_printf(cfg, "error accessing read-only VPD data\n"); 1352 return (-1); 1353 } 1354 size -= elem_size; 1355 } 1356 cksumvalid = (vrs.cksum == 0); 1357 if (!cksumvalid) 1358 return (-1); 1359 1360 /* read VPD RW elements - optional */ 1361 size = vpd_read_tag_size(&vrs, VPD_TAG_RW); 1362 if (size == -2) 1363 return (-1); 1364 while (size > 0) { 1365 elem_size = next_vpd_rw_elem(&vrs, size); 1366 if (elem_size < 0) { 1367 pci_printf(cfg, "error accessing writeable VPD data\n"); 1368 return (-1); 1369 } 1370 size -= elem_size; 1371 } 1372 1373 /* read empty END tag - mandatory */ 1374 size = vpd_read_tag_size(&vrs, VPD_TAG_END); 1375 if (size != 0) { 1376 pci_printf(cfg, "No valid VPD end tag found\n"); 1377 } 1378 return (0); 1379 } 1380 1381 static void 1382 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 1383 { 1384 int status; 1385 1386 status = pci_parse_vpd(pcib, cfg); 1387 if (status < 0) 1388 vpd_free(&cfg->vpd); 1389 cfg->vpd.vpd_cached = 1; 1390 #undef REG 1391 #undef WREG 1392 } 1393 1394 int 1395 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 1396 { 1397 struct pci_devinfo *dinfo = device_get_ivars(child); 1398 pcicfgregs *cfg = &dinfo->cfg; 1399 1400 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1401 pci_read_vpd(device_get_parent(dev), cfg); 1402 1403 *identptr = cfg->vpd.vpd_ident; 1404 1405 if (*identptr == NULL) 1406 return (ENXIO); 1407 1408 return (0); 1409 } 1410 1411 int 1412 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 1413 const char **vptr) 1414 { 1415 struct pci_devinfo *dinfo = device_get_ivars(child); 1416 pcicfgregs *cfg = &dinfo->cfg; 1417 int i; 1418 1419 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1420 pci_read_vpd(device_get_parent(dev), cfg); 1421 1422 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 1423 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 1424 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) { 1425 *vptr = cfg->vpd.vpd_ros[i].value; 1426 return (0); 1427 } 1428 1429 *vptr = NULL; 1430 return (ENXIO); 1431 } 1432 1433 struct pcicfg_vpd * 1434 pci_fetch_vpd_list(device_t dev) 1435 { 1436 struct pci_devinfo *dinfo = device_get_ivars(dev); 1437 pcicfgregs *cfg = &dinfo->cfg; 1438 1439 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0) 1440 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg); 1441 return (&cfg->vpd); 1442 } 1443 1444 /* 1445 * Find the requested HyperTransport capability and return the offset 1446 * in configuration space via the pointer provided. The function 1447 * returns 0 on success and an error code otherwise. 1448 */ 1449 int 1450 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg) 1451 { 1452 int ptr, error; 1453 uint16_t val; 1454 1455 error = pci_find_cap(child, PCIY_HT, &ptr); 1456 if (error) 1457 return (error); 1458 1459 /* 1460 * Traverse the capabilities list checking each HT capability 1461 * to see if it matches the requested HT capability. 1462 */ 1463 for (;;) { 1464 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1465 if (capability == PCIM_HTCAP_SLAVE || 1466 capability == PCIM_HTCAP_HOST) 1467 val &= 0xe000; 1468 else 1469 val &= PCIM_HTCMD_CAP_MASK; 1470 if (val == capability) { 1471 if (capreg != NULL) 1472 *capreg = ptr; 1473 return (0); 1474 } 1475 1476 /* Skip to the next HT capability. */ 1477 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1478 break; 1479 } 1480 1481 return (ENOENT); 1482 } 1483 1484 /* 1485 * Find the next requested HyperTransport capability after start and return 1486 * the offset in configuration space via the pointer provided. The function 1487 * returns 0 on success and an error code otherwise. 1488 */ 1489 int 1490 pci_find_next_htcap_method(device_t dev, device_t child, int capability, 1491 int start, int *capreg) 1492 { 1493 int ptr; 1494 uint16_t val; 1495 1496 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == PCIY_HT, 1497 ("start capability is not HyperTransport capability")); 1498 ptr = start; 1499 1500 /* 1501 * Traverse the capabilities list checking each HT capability 1502 * to see if it matches the requested HT capability. 1503 */ 1504 for (;;) { 1505 /* Skip to the next HT capability. */ 1506 if (pci_find_next_cap(child, PCIY_HT, ptr, &ptr) != 0) 1507 break; 1508 1509 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2); 1510 if (capability == PCIM_HTCAP_SLAVE || 1511 capability == PCIM_HTCAP_HOST) 1512 val &= 0xe000; 1513 else 1514 val &= PCIM_HTCMD_CAP_MASK; 1515 if (val == capability) { 1516 if (capreg != NULL) 1517 *capreg = ptr; 1518 return (0); 1519 } 1520 } 1521 1522 return (ENOENT); 1523 } 1524 1525 /* 1526 * Find the requested capability and return the offset in 1527 * configuration space via the pointer provided. The function returns 1528 * 0 on success and an error code otherwise. 1529 */ 1530 int 1531 pci_find_cap_method(device_t dev, device_t child, int capability, 1532 int *capreg) 1533 { 1534 struct pci_devinfo *dinfo = device_get_ivars(child); 1535 pcicfgregs *cfg = &dinfo->cfg; 1536 uint32_t status; 1537 uint8_t ptr; 1538 int cnt; 1539 1540 /* 1541 * Check the CAP_LIST bit of the PCI status register first. 1542 */ 1543 status = pci_read_config(child, PCIR_STATUS, 2); 1544 if (!(status & PCIM_STATUS_CAPPRESENT)) 1545 return (ENXIO); 1546 1547 /* 1548 * Determine the start pointer of the capabilities list. 1549 */ 1550 switch (cfg->hdrtype & PCIM_HDRTYPE) { 1551 case PCIM_HDRTYPE_NORMAL: 1552 case PCIM_HDRTYPE_BRIDGE: 1553 ptr = PCIR_CAP_PTR; 1554 break; 1555 case PCIM_HDRTYPE_CARDBUS: 1556 ptr = PCIR_CAP_PTR_2; 1557 break; 1558 default: 1559 /* XXX: panic? */ 1560 return (ENXIO); /* no extended capabilities support */ 1561 } 1562 ptr = pci_read_config(child, ptr, 1); 1563 1564 /* 1565 * Traverse the capabilities list. Limit by total theoretical 1566 * maximum number of caps: capability needs at least id and 1567 * next registers, and any type X header cannot contain caps. 1568 */ 1569 for (cnt = 0; ptr != 0 && cnt < (PCIE_REGMAX - 0x40) / 2; cnt++) { 1570 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1571 if (capreg != NULL) 1572 *capreg = ptr; 1573 return (0); 1574 } 1575 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1576 } 1577 1578 return (ENOENT); 1579 } 1580 1581 /* 1582 * Find the next requested capability after start and return the offset in 1583 * configuration space via the pointer provided. The function returns 1584 * 0 on success and an error code otherwise. 1585 */ 1586 int 1587 pci_find_next_cap_method(device_t dev, device_t child, int capability, 1588 int start, int *capreg) 1589 { 1590 uint8_t ptr; 1591 1592 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == capability, 1593 ("start capability is not expected capability")); 1594 1595 ptr = pci_read_config(child, start + PCICAP_NEXTPTR, 1); 1596 while (ptr != 0) { 1597 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 1598 if (capreg != NULL) 1599 *capreg = ptr; 1600 return (0); 1601 } 1602 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 1603 } 1604 1605 return (ENOENT); 1606 } 1607 1608 /* 1609 * Find the requested extended capability and return the offset in 1610 * configuration space via the pointer provided. The function returns 1611 * 0 on success and an error code otherwise. 1612 */ 1613 int 1614 pci_find_extcap_method(device_t dev, device_t child, int capability, 1615 int *capreg) 1616 { 1617 struct pci_devinfo *dinfo = device_get_ivars(child); 1618 pcicfgregs *cfg = &dinfo->cfg; 1619 uint32_t ecap; 1620 uint16_t ptr; 1621 1622 /* Only supported for PCI-express devices. */ 1623 if (cfg->pcie.pcie_location == 0) 1624 return (ENXIO); 1625 1626 ptr = PCIR_EXTCAP; 1627 ecap = pci_read_config(child, ptr, 4); 1628 if (ecap == 0xffffffff || ecap == 0) 1629 return (ENOENT); 1630 for (;;) { 1631 if (PCI_EXTCAP_ID(ecap) == capability) { 1632 if (capreg != NULL) 1633 *capreg = ptr; 1634 return (0); 1635 } 1636 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1637 if (ptr == 0) 1638 break; 1639 ecap = pci_read_config(child, ptr, 4); 1640 } 1641 1642 return (ENOENT); 1643 } 1644 1645 /* 1646 * Find the next requested extended capability after start and return the 1647 * offset in configuration space via the pointer provided. The function 1648 * returns 0 on success and an error code otherwise. 1649 */ 1650 int 1651 pci_find_next_extcap_method(device_t dev, device_t child, int capability, 1652 int start, int *capreg) 1653 { 1654 struct pci_devinfo *dinfo = device_get_ivars(child); 1655 pcicfgregs *cfg = &dinfo->cfg; 1656 uint32_t ecap; 1657 uint16_t ptr; 1658 1659 /* Only supported for PCI-express devices. */ 1660 if (cfg->pcie.pcie_location == 0) 1661 return (ENXIO); 1662 1663 ecap = pci_read_config(child, start, 4); 1664 KASSERT(PCI_EXTCAP_ID(ecap) == capability, 1665 ("start extended capability is not expected capability")); 1666 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1667 while (ptr != 0) { 1668 ecap = pci_read_config(child, ptr, 4); 1669 if (PCI_EXTCAP_ID(ecap) == capability) { 1670 if (capreg != NULL) 1671 *capreg = ptr; 1672 return (0); 1673 } 1674 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1675 } 1676 1677 return (ENOENT); 1678 } 1679 1680 /* 1681 * Support for MSI-X message interrupts. 1682 */ 1683 static void 1684 pci_write_msix_entry(device_t dev, u_int index, uint64_t address, uint32_t data) 1685 { 1686 struct pci_devinfo *dinfo = device_get_ivars(dev); 1687 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1688 uint32_t offset; 1689 1690 KASSERT(msix->msix_table_len > index, ("bogus index")); 1691 offset = msix->msix_table_offset + index * 16; 1692 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); 1693 bus_write_4(msix->msix_table_res, offset + 4, address >> 32); 1694 bus_write_4(msix->msix_table_res, offset + 8, data); 1695 } 1696 1697 void 1698 pci_enable_msix_method(device_t dev, device_t child, u_int index, 1699 uint64_t address, uint32_t data) 1700 { 1701 1702 if (pci_msix_rewrite_table) { 1703 struct pci_devinfo *dinfo = device_get_ivars(child); 1704 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1705 1706 /* 1707 * Some VM hosts require MSIX to be disabled in the 1708 * control register before updating the MSIX table 1709 * entries are allowed. It is not enough to only 1710 * disable MSIX while updating a single entry. MSIX 1711 * must be disabled while updating all entries in the 1712 * table. 1713 */ 1714 pci_write_config(child, 1715 msix->msix_location + PCIR_MSIX_CTRL, 1716 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2); 1717 pci_resume_msix(child); 1718 } else 1719 pci_write_msix_entry(child, index, address, data); 1720 1721 /* Enable MSI -> HT mapping. */ 1722 pci_ht_map_msi(child, address); 1723 } 1724 1725 void 1726 pci_mask_msix(device_t dev, u_int index) 1727 { 1728 struct pci_devinfo *dinfo = device_get_ivars(dev); 1729 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1730 uint32_t offset, val; 1731 1732 KASSERT(PCI_MSIX_MSGNUM(msix->msix_ctrl) > index, ("bogus index")); 1733 offset = msix->msix_table_offset + index * 16 + 12; 1734 val = bus_read_4(msix->msix_table_res, offset); 1735 val |= PCIM_MSIX_VCTRL_MASK; 1736 1737 /* 1738 * Some devices (e.g. Samsung PM961) do not support reads of this 1739 * register, so always write the new value. 1740 */ 1741 bus_write_4(msix->msix_table_res, offset, val); 1742 } 1743 1744 void 1745 pci_unmask_msix(device_t dev, u_int index) 1746 { 1747 struct pci_devinfo *dinfo = device_get_ivars(dev); 1748 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1749 uint32_t offset, val; 1750 1751 KASSERT(PCI_MSIX_MSGNUM(msix->msix_ctrl) > index, ("bogus index")); 1752 offset = msix->msix_table_offset + index * 16 + 12; 1753 val = bus_read_4(msix->msix_table_res, offset); 1754 val &= ~PCIM_MSIX_VCTRL_MASK; 1755 1756 /* 1757 * Some devices (e.g. Samsung PM961) do not support reads of this 1758 * register, so always write the new value. 1759 */ 1760 bus_write_4(msix->msix_table_res, offset, val); 1761 } 1762 1763 int 1764 pci_pending_msix(device_t dev, u_int index) 1765 { 1766 struct pci_devinfo *dinfo = device_get_ivars(dev); 1767 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1768 uint32_t offset, bit; 1769 1770 KASSERT(msix->msix_table_len > index, ("bogus index")); 1771 offset = msix->msix_pba_offset + (index / 32) * 4; 1772 bit = 1 << index % 32; 1773 return (bus_read_4(msix->msix_pba_res, offset) & bit); 1774 } 1775 1776 /* 1777 * Restore MSI-X registers and table during resume. If MSI-X is 1778 * enabled then walk the virtual table to restore the actual MSI-X 1779 * table. 1780 */ 1781 static void 1782 pci_resume_msix(device_t dev) 1783 { 1784 struct pci_devinfo *dinfo = device_get_ivars(dev); 1785 struct pcicfg_msix *msix = &dinfo->cfg.msix; 1786 struct msix_table_entry *mte; 1787 struct msix_vector *mv; 1788 u_int i, msgnum; 1789 1790 if (msix->msix_alloc > 0) { 1791 msgnum = PCI_MSIX_MSGNUM(msix->msix_ctrl); 1792 1793 /* First, mask all vectors. */ 1794 for (i = 0; i < msgnum; i++) 1795 pci_mask_msix(dev, i); 1796 1797 /* Second, program any messages with at least one handler. */ 1798 for (i = 0; i < msix->msix_table_len; i++) { 1799 mte = &msix->msix_table[i]; 1800 if (mte->mte_vector == 0 || mte->mte_handlers == 0) 1801 continue; 1802 mv = &msix->msix_vectors[mte->mte_vector - 1]; 1803 pci_write_msix_entry(dev, i, mv->mv_address, 1804 mv->mv_data); 1805 pci_unmask_msix(dev, i); 1806 } 1807 } 1808 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL, 1809 msix->msix_ctrl, 2); 1810 } 1811 1812 /* 1813 * Attempt to allocate *count MSI-X messages. The actual number allocated is 1814 * returned in *count. After this function returns, each message will be 1815 * available to the driver as SYS_RES_IRQ resources starting at rid 1. 1816 */ 1817 int 1818 pci_alloc_msix_method(device_t dev, device_t child, int *count) 1819 { 1820 struct pci_devinfo *dinfo = device_get_ivars(child); 1821 pcicfgregs *cfg = &dinfo->cfg; 1822 struct resource_list_entry *rle; 1823 u_int actual, i, max; 1824 int error, irq; 1825 uint16_t ctrl, msgnum; 1826 1827 /* Don't let count == 0 get us into trouble. */ 1828 if (*count < 1) 1829 return (EINVAL); 1830 1831 /* If rid 0 is allocated, then fail. */ 1832 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 1833 if (rle != NULL && rle->res != NULL) 1834 return (ENXIO); 1835 1836 /* Already have allocated messages? */ 1837 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 1838 return (ENXIO); 1839 1840 /* If MSI-X is blacklisted for this system, fail. */ 1841 if (pci_msix_blacklisted()) 1842 return (ENXIO); 1843 1844 /* MSI-X capability present? */ 1845 if (cfg->msix.msix_location == 0 || !pci_do_msix) 1846 return (ENODEV); 1847 1848 /* Make sure the appropriate BARs are mapped. */ 1849 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1850 cfg->msix.msix_table_bar); 1851 if (rle == NULL || rle->res == NULL || 1852 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1853 return (ENXIO); 1854 cfg->msix.msix_table_res = rle->res; 1855 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) { 1856 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, 1857 cfg->msix.msix_pba_bar); 1858 if (rle == NULL || rle->res == NULL || 1859 !(rman_get_flags(rle->res) & RF_ACTIVE)) 1860 return (ENXIO); 1861 } 1862 cfg->msix.msix_pba_res = rle->res; 1863 1864 ctrl = pci_read_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1865 2); 1866 msgnum = PCI_MSIX_MSGNUM(ctrl); 1867 if (bootverbose) 1868 device_printf(child, 1869 "attempting to allocate %d MSI-X vectors (%d supported)\n", 1870 *count, msgnum); 1871 max = min(*count, msgnum); 1872 for (i = 0; i < max; i++) { 1873 /* Allocate a message. */ 1874 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq); 1875 if (error) { 1876 if (i == 0) 1877 return (error); 1878 break; 1879 } 1880 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 1881 irq, 1); 1882 } 1883 actual = i; 1884 1885 if (bootverbose) { 1886 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1); 1887 if (actual == 1) 1888 device_printf(child, "using IRQ %ju for MSI-X\n", 1889 rle->start); 1890 else { 1891 bool run; 1892 1893 /* 1894 * Be fancy and try to print contiguous runs of 1895 * IRQ values as ranges. 'irq' is the previous IRQ. 1896 * 'run' is true if we are in a range. 1897 */ 1898 device_printf(child, "using IRQs %ju", rle->start); 1899 irq = rle->start; 1900 run = false; 1901 for (i = 1; i < actual; i++) { 1902 rle = resource_list_find(&dinfo->resources, 1903 SYS_RES_IRQ, i + 1); 1904 1905 /* Still in a run? */ 1906 if (rle->start == irq + 1) { 1907 run = true; 1908 irq++; 1909 continue; 1910 } 1911 1912 /* Finish previous range. */ 1913 if (run) { 1914 printf("-%d", irq); 1915 run = false; 1916 } 1917 1918 /* Start new range. */ 1919 printf(",%ju", rle->start); 1920 irq = rle->start; 1921 } 1922 1923 /* Unfinished range? */ 1924 if (run) 1925 printf("-%d", irq); 1926 printf(" for MSI-X\n"); 1927 } 1928 } 1929 1930 /* Mask all vectors. */ 1931 for (i = 0; i < msgnum; i++) 1932 pci_mask_msix(child, i); 1933 1934 /* Allocate and initialize vector data and virtual table. */ 1935 cfg->msix.msix_vectors = mallocarray(actual, sizeof(struct msix_vector), 1936 M_DEVBUF, M_WAITOK | M_ZERO); 1937 cfg->msix.msix_table = mallocarray(actual, 1938 sizeof(struct msix_table_entry), M_DEVBUF, M_WAITOK | M_ZERO); 1939 for (i = 0; i < actual; i++) { 1940 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 1941 cfg->msix.msix_vectors[i].mv_irq = rle->start; 1942 cfg->msix.msix_table[i].mte_vector = i + 1; 1943 } 1944 1945 /* Update control register to enable MSI-X. */ 1946 ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; 1947 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL, 1948 ctrl, 2); 1949 cfg->msix.msix_ctrl = ctrl; 1950 1951 /* Update counts of alloc'd messages. */ 1952 cfg->msix.msix_alloc = actual; 1953 cfg->msix.msix_table_len = actual; 1954 *count = actual; 1955 return (0); 1956 } 1957 1958 /* 1959 * By default, pci_alloc_msix() will assign the allocated IRQ 1960 * resources consecutively to the first N messages in the MSI-X table. 1961 * However, device drivers may want to use different layouts if they 1962 * either receive fewer messages than they asked for, or they wish to 1963 * populate the MSI-X table sparsely. This method allows the driver 1964 * to specify what layout it wants. It must be called after a 1965 * successful pci_alloc_msix() but before any of the associated 1966 * SYS_RES_IRQ resources are allocated via bus_alloc_resource(). 1967 * 1968 * The 'vectors' array contains 'count' message vectors. The array 1969 * maps directly to the MSI-X table in that index 0 in the array 1970 * specifies the vector for the first message in the MSI-X table, etc. 1971 * The vector value in each array index can either be 0 to indicate 1972 * that no vector should be assigned to a message slot, or it can be a 1973 * number from 1 to N (where N is the count returned from a 1974 * succcessful call to pci_alloc_msix()) to indicate which message 1975 * vector (IRQ) to be used for the corresponding message. 1976 * 1977 * On successful return, each message with a non-zero vector will have 1978 * an associated SYS_RES_IRQ whose rid is equal to the array index + 1979 * 1. Additionally, if any of the IRQs allocated via the previous 1980 * call to pci_alloc_msix() are not used in the mapping, those IRQs 1981 * will be freed back to the system automatically. 1982 * 1983 * For example, suppose a driver has a MSI-X table with 6 messages and 1984 * asks for 6 messages, but pci_alloc_msix() only returns a count of 1985 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and 1986 * C. After the call to pci_alloc_msix(), the device will be setup to 1987 * have an MSI-X table of ABC--- (where - means no vector assigned). 1988 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 }, 1989 * then the MSI-X table will look like A-AB-B, and the 'C' vector will 1990 * be freed back to the system. This device will also have valid 1991 * SYS_RES_IRQ rids of 1, 3, 4, and 6. 1992 * 1993 * In any case, the SYS_RES_IRQ rid X will always map to the message 1994 * at MSI-X table index X - 1 and will only be valid if a vector is 1995 * assigned to that table entry. 1996 */ 1997 int 1998 pci_remap_msix_method(device_t dev, device_t child, int count, 1999 const u_int *vectors) 2000 { 2001 struct pci_devinfo *dinfo = device_get_ivars(child); 2002 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2003 struct resource_list_entry *rle; 2004 u_int i, irq, j; 2005 bool *used; 2006 2007 /* 2008 * Have to have at least one message in the table but the 2009 * table can't be bigger than the actual MSI-X table in the 2010 * device. 2011 */ 2012 if (count < 1 || count > PCI_MSIX_MSGNUM(msix->msix_ctrl)) 2013 return (EINVAL); 2014 2015 /* Sanity check the vectors. */ 2016 for (i = 0; i < count; i++) 2017 if (vectors[i] > msix->msix_alloc) 2018 return (EINVAL); 2019 2020 /* 2021 * Make sure there aren't any holes in the vectors to be used. 2022 * It's a big pain to support it, and it doesn't really make 2023 * sense anyway. Also, at least one vector must be used. 2024 */ 2025 used = mallocarray(msix->msix_alloc, sizeof(*used), M_DEVBUF, M_WAITOK | 2026 M_ZERO); 2027 for (i = 0; i < count; i++) 2028 if (vectors[i] != 0) 2029 used[vectors[i] - 1] = true; 2030 for (i = 0; i < msix->msix_alloc - 1; i++) 2031 if (!used[i] && used[i + 1]) { 2032 free(used, M_DEVBUF); 2033 return (EINVAL); 2034 } 2035 if (!used[0]) { 2036 free(used, M_DEVBUF); 2037 return (EINVAL); 2038 } 2039 2040 /* Make sure none of the resources are allocated. */ 2041 for (i = 0; i < msix->msix_table_len; i++) { 2042 if (msix->msix_table[i].mte_vector == 0) 2043 continue; 2044 if (msix->msix_table[i].mte_handlers > 0) { 2045 free(used, M_DEVBUF); 2046 return (EBUSY); 2047 } 2048 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2049 KASSERT(rle != NULL, ("missing resource")); 2050 if (rle->res != NULL) { 2051 free(used, M_DEVBUF); 2052 return (EBUSY); 2053 } 2054 } 2055 2056 /* Free the existing resource list entries. */ 2057 for (i = 0; i < msix->msix_table_len; i++) { 2058 if (msix->msix_table[i].mte_vector == 0) 2059 continue; 2060 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2061 } 2062 2063 /* 2064 * Build the new virtual table keeping track of which vectors are 2065 * used. 2066 */ 2067 free(msix->msix_table, M_DEVBUF); 2068 msix->msix_table = mallocarray(count, sizeof(struct msix_table_entry), 2069 M_DEVBUF, M_WAITOK | M_ZERO); 2070 for (i = 0; i < count; i++) 2071 msix->msix_table[i].mte_vector = vectors[i]; 2072 msix->msix_table_len = count; 2073 2074 /* Free any unused IRQs and resize the vectors array if necessary. */ 2075 j = msix->msix_alloc - 1; 2076 if (!used[j]) { 2077 struct msix_vector *vec; 2078 2079 while (!used[j]) { 2080 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2081 msix->msix_vectors[j].mv_irq); 2082 j--; 2083 } 2084 vec = mallocarray(j + 1, sizeof(struct msix_vector), M_DEVBUF, 2085 M_WAITOK); 2086 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) * 2087 (j + 1)); 2088 free(msix->msix_vectors, M_DEVBUF); 2089 msix->msix_vectors = vec; 2090 msix->msix_alloc = j + 1; 2091 } 2092 free(used, M_DEVBUF); 2093 2094 /* Map the IRQs onto the rids. */ 2095 for (i = 0; i < count; i++) { 2096 if (vectors[i] == 0) 2097 continue; 2098 irq = msix->msix_vectors[vectors[i] - 1].mv_irq; 2099 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq, 2100 irq, 1); 2101 } 2102 2103 if (bootverbose) { 2104 device_printf(child, "Remapped MSI-X IRQs as: "); 2105 for (i = 0; i < count; i++) { 2106 if (i != 0) 2107 printf(", "); 2108 if (vectors[i] == 0) 2109 printf("---"); 2110 else 2111 printf("%d", 2112 msix->msix_vectors[vectors[i] - 1].mv_irq); 2113 } 2114 printf("\n"); 2115 } 2116 2117 return (0); 2118 } 2119 2120 static int 2121 pci_release_msix(device_t dev, device_t child) 2122 { 2123 struct pci_devinfo *dinfo = device_get_ivars(child); 2124 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2125 struct resource_list_entry *rle; 2126 u_int i; 2127 2128 /* Do we have any messages to release? */ 2129 if (msix->msix_alloc == 0) 2130 return (ENODEV); 2131 2132 /* Make sure none of the resources are allocated. */ 2133 for (i = 0; i < msix->msix_table_len; i++) { 2134 if (msix->msix_table[i].mte_vector == 0) 2135 continue; 2136 if (msix->msix_table[i].mte_handlers > 0) 2137 return (EBUSY); 2138 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2139 KASSERT(rle != NULL, ("missing resource")); 2140 if (rle->res != NULL) 2141 return (EBUSY); 2142 } 2143 2144 /* Update control register to disable MSI-X. */ 2145 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE; 2146 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL, 2147 msix->msix_ctrl, 2); 2148 2149 /* Free the resource list entries. */ 2150 for (i = 0; i < msix->msix_table_len; i++) { 2151 if (msix->msix_table[i].mte_vector == 0) 2152 continue; 2153 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2154 } 2155 free(msix->msix_table, M_DEVBUF); 2156 msix->msix_table_len = 0; 2157 2158 /* Release the IRQs. */ 2159 for (i = 0; i < msix->msix_alloc; i++) 2160 PCIB_RELEASE_MSIX(device_get_parent(dev), child, 2161 msix->msix_vectors[i].mv_irq); 2162 free(msix->msix_vectors, M_DEVBUF); 2163 msix->msix_alloc = 0; 2164 return (0); 2165 } 2166 2167 /* 2168 * Return the max supported MSI-X messages this device supports. 2169 * Basically, assuming the MD code can alloc messages, this function 2170 * should return the maximum value that pci_alloc_msix() can return. 2171 * Thus, it is subject to the tunables, etc. 2172 */ 2173 int 2174 pci_msix_count_method(device_t dev, device_t child) 2175 { 2176 struct pci_devinfo *dinfo = device_get_ivars(child); 2177 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2178 uint16_t ctrl; 2179 2180 if (pci_do_msix && msix->msix_location != 0) { 2181 ctrl = pci_read_config(child, msix->msix_location + 2182 PCIR_MSI_CTRL, 2); 2183 return (PCI_MSIX_MSGNUM(ctrl)); 2184 } 2185 return (0); 2186 } 2187 2188 int 2189 pci_msix_pba_bar_method(device_t dev, device_t child) 2190 { 2191 struct pci_devinfo *dinfo = device_get_ivars(child); 2192 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2193 2194 if (pci_do_msix && msix->msix_location != 0) 2195 return (msix->msix_pba_bar); 2196 return (-1); 2197 } 2198 2199 int 2200 pci_msix_table_bar_method(device_t dev, device_t child) 2201 { 2202 struct pci_devinfo *dinfo = device_get_ivars(child); 2203 struct pcicfg_msix *msix = &dinfo->cfg.msix; 2204 2205 if (pci_do_msix && msix->msix_location != 0) 2206 return (msix->msix_table_bar); 2207 return (-1); 2208 } 2209 2210 /* 2211 * HyperTransport MSI mapping control 2212 */ 2213 void 2214 pci_ht_map_msi(device_t dev, uint64_t addr) 2215 { 2216 struct pci_devinfo *dinfo = device_get_ivars(dev); 2217 struct pcicfg_ht *ht = &dinfo->cfg.ht; 2218 2219 if (!ht->ht_msimap) 2220 return; 2221 2222 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) && 2223 ht->ht_msiaddr >> 20 == addr >> 20) { 2224 /* Enable MSI -> HT mapping. */ 2225 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE; 2226 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2227 ht->ht_msictrl, 2); 2228 } 2229 2230 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) { 2231 /* Disable MSI -> HT mapping. */ 2232 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE; 2233 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND, 2234 ht->ht_msictrl, 2); 2235 } 2236 } 2237 2238 int 2239 pci_get_relaxed_ordering_enabled(device_t dev) 2240 { 2241 struct pci_devinfo *dinfo = device_get_ivars(dev); 2242 int cap; 2243 uint16_t val; 2244 2245 cap = dinfo->cfg.pcie.pcie_location; 2246 if (cap == 0) 2247 return (0); 2248 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2249 val &= PCIEM_CTL_RELAXED_ORD_ENABLE; 2250 return (val != 0); 2251 } 2252 2253 int 2254 pci_get_max_payload(device_t dev) 2255 { 2256 struct pci_devinfo *dinfo = device_get_ivars(dev); 2257 int cap; 2258 uint16_t val; 2259 2260 cap = dinfo->cfg.pcie.pcie_location; 2261 if (cap == 0) 2262 return (0); 2263 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2264 val &= PCIEM_CTL_MAX_PAYLOAD; 2265 val >>= 5; 2266 return (1 << (val + 7)); 2267 } 2268 2269 int 2270 pci_get_max_read_req(device_t dev) 2271 { 2272 struct pci_devinfo *dinfo = device_get_ivars(dev); 2273 int cap; 2274 uint16_t val; 2275 2276 cap = dinfo->cfg.pcie.pcie_location; 2277 if (cap == 0) 2278 return (0); 2279 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2280 val &= PCIEM_CTL_MAX_READ_REQUEST; 2281 val >>= 12; 2282 return (1 << (val + 7)); 2283 } 2284 2285 int 2286 pci_set_max_read_req(device_t dev, int size) 2287 { 2288 struct pci_devinfo *dinfo = device_get_ivars(dev); 2289 int cap; 2290 uint16_t val; 2291 2292 cap = dinfo->cfg.pcie.pcie_location; 2293 if (cap == 0) 2294 return (0); 2295 if (size < 128) 2296 size = 128; 2297 if (size > 4096) 2298 size = 4096; 2299 size = (1 << (fls(size) - 1)); 2300 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 2301 val &= ~PCIEM_CTL_MAX_READ_REQUEST; 2302 val |= (fls(size) - 8) << 12; 2303 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2); 2304 return (size); 2305 } 2306 2307 uint32_t 2308 pcie_read_config(device_t dev, int reg, int width) 2309 { 2310 struct pci_devinfo *dinfo = device_get_ivars(dev); 2311 int cap; 2312 2313 cap = dinfo->cfg.pcie.pcie_location; 2314 if (cap == 0) { 2315 if (width == 2) 2316 return (0xffff); 2317 return (0xffffffff); 2318 } 2319 2320 return (pci_read_config(dev, cap + reg, width)); 2321 } 2322 2323 void 2324 pcie_write_config(device_t dev, int reg, uint32_t value, int width) 2325 { 2326 struct pci_devinfo *dinfo = device_get_ivars(dev); 2327 int cap; 2328 2329 cap = dinfo->cfg.pcie.pcie_location; 2330 if (cap == 0) 2331 return; 2332 pci_write_config(dev, cap + reg, value, width); 2333 } 2334 2335 /* 2336 * Adjusts a PCI-e capability register by clearing the bits in mask 2337 * and setting the bits in (value & mask). Bits not set in mask are 2338 * not adjusted. 2339 * 2340 * Returns the old value on success or all ones on failure. 2341 */ 2342 uint32_t 2343 pcie_adjust_config(device_t dev, int reg, uint32_t mask, uint32_t value, 2344 int width) 2345 { 2346 struct pci_devinfo *dinfo = device_get_ivars(dev); 2347 uint32_t old, new; 2348 int cap; 2349 2350 cap = dinfo->cfg.pcie.pcie_location; 2351 if (cap == 0) { 2352 if (width == 2) 2353 return (0xffff); 2354 return (0xffffffff); 2355 } 2356 2357 old = pci_read_config(dev, cap + reg, width); 2358 new = old & ~mask; 2359 new |= (value & mask); 2360 pci_write_config(dev, cap + reg, new, width); 2361 return (old); 2362 } 2363 2364 /* 2365 * Support for MSI message signalled interrupts. 2366 */ 2367 void 2368 pci_enable_msi_method(device_t dev, device_t child, uint64_t address, 2369 uint16_t data) 2370 { 2371 struct pci_devinfo *dinfo = device_get_ivars(child); 2372 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2373 2374 /* Write data and address values. */ 2375 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR, 2376 address & 0xffffffff, 4); 2377 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2378 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH, 2379 address >> 32, 4); 2380 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT, 2381 data, 2); 2382 } else 2383 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data, 2384 2); 2385 2386 /* Enable MSI in the control register. */ 2387 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE; 2388 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2389 msi->msi_ctrl, 2); 2390 2391 /* Enable MSI -> HT mapping. */ 2392 pci_ht_map_msi(child, address); 2393 } 2394 2395 void 2396 pci_disable_msi_method(device_t dev, device_t child) 2397 { 2398 struct pci_devinfo *dinfo = device_get_ivars(child); 2399 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2400 2401 /* Disable MSI -> HT mapping. */ 2402 pci_ht_map_msi(child, 0); 2403 2404 /* Disable MSI in the control register. */ 2405 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE; 2406 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2407 msi->msi_ctrl, 2); 2408 } 2409 2410 /* 2411 * Restore MSI registers during resume. If MSI is enabled then 2412 * restore the data and address registers in addition to the control 2413 * register. 2414 */ 2415 static void 2416 pci_resume_msi(device_t dev) 2417 { 2418 struct pci_devinfo *dinfo = device_get_ivars(dev); 2419 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2420 uint64_t address; 2421 uint16_t data; 2422 2423 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) { 2424 address = msi->msi_addr; 2425 data = msi->msi_data; 2426 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR, 2427 address & 0xffffffff, 4); 2428 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) { 2429 pci_write_config(dev, msi->msi_location + 2430 PCIR_MSI_ADDR_HIGH, address >> 32, 4); 2431 pci_write_config(dev, msi->msi_location + 2432 PCIR_MSI_DATA_64BIT, data, 2); 2433 } else 2434 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, 2435 data, 2); 2436 } 2437 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl, 2438 2); 2439 } 2440 2441 static int 2442 pci_remap_intr_method(device_t bus, device_t dev, u_int irq) 2443 { 2444 struct pci_devinfo *dinfo = device_get_ivars(dev); 2445 pcicfgregs *cfg = &dinfo->cfg; 2446 struct resource_list_entry *rle; 2447 struct msix_table_entry *mte; 2448 struct msix_vector *mv; 2449 uint64_t addr; 2450 uint32_t data; 2451 u_int i, j; 2452 int error; 2453 2454 /* 2455 * Handle MSI first. We try to find this IRQ among our list 2456 * of MSI IRQs. If we find it, we request updated address and 2457 * data registers and apply the results. 2458 */ 2459 if (cfg->msi.msi_alloc > 0) { 2460 /* If we don't have any active handlers, nothing to do. */ 2461 if (cfg->msi.msi_handlers == 0) 2462 return (0); 2463 for (i = 0; i < cfg->msi.msi_alloc; i++) { 2464 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 2465 i + 1); 2466 if (rle->start == irq) { 2467 error = PCIB_MAP_MSI(device_get_parent(bus), 2468 dev, irq, &addr, &data); 2469 if (error) 2470 return (error); 2471 pci_disable_msi(dev); 2472 dinfo->cfg.msi.msi_addr = addr; 2473 dinfo->cfg.msi.msi_data = data; 2474 pci_enable_msi(dev, addr, data); 2475 return (0); 2476 } 2477 } 2478 return (ENOENT); 2479 } 2480 2481 /* 2482 * For MSI-X, we check to see if we have this IRQ. If we do, 2483 * we request the updated mapping info. If that works, we go 2484 * through all the slots that use this IRQ and update them. 2485 */ 2486 if (cfg->msix.msix_alloc > 0) { 2487 bool found = false; 2488 2489 for (i = 0; i < cfg->msix.msix_alloc; i++) { 2490 mv = &cfg->msix.msix_vectors[i]; 2491 if (mv->mv_irq == irq) { 2492 error = PCIB_MAP_MSI(device_get_parent(bus), 2493 dev, irq, &addr, &data); 2494 if (error) 2495 return (error); 2496 mv->mv_address = addr; 2497 mv->mv_data = data; 2498 for (j = 0; j < cfg->msix.msix_table_len; j++) { 2499 mte = &cfg->msix.msix_table[j]; 2500 if (mte->mte_vector != i + 1) 2501 continue; 2502 if (mte->mte_handlers == 0) 2503 continue; 2504 pci_mask_msix(dev, j); 2505 pci_enable_msix(dev, j, addr, data); 2506 pci_unmask_msix(dev, j); 2507 } 2508 found = true; 2509 } 2510 } 2511 return (found ? 0 : ENOENT); 2512 } 2513 2514 return (ENOENT); 2515 } 2516 2517 /* 2518 * Returns true if the specified device is blacklisted because MSI 2519 * doesn't work. 2520 */ 2521 int 2522 pci_msi_device_blacklisted(device_t dev) 2523 { 2524 2525 if (!pci_honor_msi_blacklist) 2526 return (0); 2527 2528 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI)); 2529 } 2530 2531 /* 2532 * Determine if MSI is blacklisted globally on this system. Currently, 2533 * we just check for blacklisted chipsets as represented by the 2534 * host-PCI bridge at device 0:0:0. In the future, it may become 2535 * necessary to check other system attributes, such as the kenv values 2536 * that give the motherboard manufacturer and model number. 2537 */ 2538 static int 2539 pci_msi_blacklisted(void) 2540 { 2541 device_t dev; 2542 2543 if (!pci_honor_msi_blacklist) 2544 return (0); 2545 2546 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */ 2547 if (!(pcie_chipset || pcix_chipset)) { 2548 if (vm_guest != VM_GUEST_NO) { 2549 /* 2550 * Whitelist older chipsets in virtual 2551 * machines known to support MSI. 2552 */ 2553 dev = pci_find_bsf(0, 0, 0); 2554 if (dev != NULL) 2555 return (!pci_has_quirk(pci_get_devid(dev), 2556 PCI_QUIRK_ENABLE_MSI_VM)); 2557 } 2558 return (1); 2559 } 2560 2561 dev = pci_find_bsf(0, 0, 0); 2562 if (dev != NULL) 2563 return (pci_msi_device_blacklisted(dev)); 2564 return (0); 2565 } 2566 2567 /* 2568 * Returns true if the specified device is blacklisted because MSI-X 2569 * doesn't work. Note that this assumes that if MSI doesn't work, 2570 * MSI-X doesn't either. 2571 */ 2572 int 2573 pci_msix_device_blacklisted(device_t dev) 2574 { 2575 2576 if (!pci_honor_msi_blacklist) 2577 return (0); 2578 2579 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX)) 2580 return (1); 2581 2582 return (pci_msi_device_blacklisted(dev)); 2583 } 2584 2585 /* 2586 * Determine if MSI-X is blacklisted globally on this system. If MSI 2587 * is blacklisted, assume that MSI-X is as well. Check for additional 2588 * chipsets where MSI works but MSI-X does not. 2589 */ 2590 static int 2591 pci_msix_blacklisted(void) 2592 { 2593 device_t dev; 2594 2595 if (!pci_honor_msi_blacklist) 2596 return (0); 2597 2598 dev = pci_find_bsf(0, 0, 0); 2599 if (dev != NULL && pci_has_quirk(pci_get_devid(dev), 2600 PCI_QUIRK_DISABLE_MSIX)) 2601 return (1); 2602 2603 return (pci_msi_blacklisted()); 2604 } 2605 2606 /* 2607 * Attempt to allocate *count MSI messages. The actual number allocated is 2608 * returned in *count. After this function returns, each message will be 2609 * available to the driver as SYS_RES_IRQ resources starting at a rid 1. 2610 */ 2611 int 2612 pci_alloc_msi_method(device_t dev, device_t child, int *count) 2613 { 2614 struct pci_devinfo *dinfo = device_get_ivars(child); 2615 pcicfgregs *cfg = &dinfo->cfg; 2616 struct resource_list_entry *rle; 2617 u_int actual, i; 2618 int error, irqs[32]; 2619 uint16_t ctrl, msgnum; 2620 2621 /* Don't let count == 0 get us into trouble. */ 2622 if (*count < 1) 2623 return (EINVAL); 2624 2625 /* If rid 0 is allocated, then fail. */ 2626 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 2627 if (rle != NULL && rle->res != NULL) 2628 return (ENXIO); 2629 2630 /* Already have allocated messages? */ 2631 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0) 2632 return (ENXIO); 2633 2634 /* If MSI is blacklisted for this system, fail. */ 2635 if (pci_msi_blacklisted()) 2636 return (ENXIO); 2637 2638 /* MSI capability present? */ 2639 if (cfg->msi.msi_location == 0 || !pci_do_msi) 2640 return (ENODEV); 2641 2642 ctrl = pci_read_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, 2); 2643 msgnum = PCI_MSI_MSGNUM(ctrl); 2644 if (bootverbose) 2645 device_printf(child, 2646 "attempting to allocate %d MSI vectors (%u supported)\n", 2647 *count, msgnum); 2648 2649 /* Don't ask for more than the device supports. */ 2650 actual = min(*count, msgnum); 2651 2652 /* Don't ask for more than 32 messages. */ 2653 actual = min(actual, 32); 2654 2655 /* MSI requires power of 2 number of messages. */ 2656 if (!powerof2(actual)) 2657 return (EINVAL); 2658 2659 for (;;) { 2660 /* Try to allocate N messages. */ 2661 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual, 2662 actual, irqs); 2663 if (error == 0) 2664 break; 2665 if (actual == 1) 2666 return (error); 2667 2668 /* Try N / 2. */ 2669 actual >>= 1; 2670 } 2671 2672 /* 2673 * We now have N actual messages mapped onto SYS_RES_IRQ 2674 * resources in the irqs[] array, so add new resources 2675 * starting at rid 1. 2676 */ 2677 for (i = 0; i < actual; i++) 2678 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, 2679 irqs[i], irqs[i], 1); 2680 2681 if (bootverbose) { 2682 if (actual == 1) 2683 device_printf(child, "using IRQ %d for MSI\n", irqs[0]); 2684 else { 2685 bool run; 2686 2687 /* 2688 * Be fancy and try to print contiguous runs 2689 * of IRQ values as ranges. 'run' is true if 2690 * we are in a range. 2691 */ 2692 device_printf(child, "using IRQs %d", irqs[0]); 2693 run = false; 2694 for (i = 1; i < actual; i++) { 2695 /* Still in a run? */ 2696 if (irqs[i] == irqs[i - 1] + 1) { 2697 run = true; 2698 continue; 2699 } 2700 2701 /* Finish previous range. */ 2702 if (run) { 2703 printf("-%d", irqs[i - 1]); 2704 run = false; 2705 } 2706 2707 /* Start new range. */ 2708 printf(",%d", irqs[i]); 2709 } 2710 2711 /* Unfinished range? */ 2712 if (run) 2713 printf("-%d", irqs[actual - 1]); 2714 printf(" for MSI\n"); 2715 } 2716 } 2717 2718 /* Update control register with actual count. */ 2719 ctrl &= ~PCIM_MSICTRL_MME_MASK; 2720 ctrl |= (ffs(actual) - 1) << 4; 2721 cfg->msi.msi_ctrl = ctrl; 2722 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2); 2723 2724 /* Update counts of alloc'd messages. */ 2725 cfg->msi.msi_alloc = actual; 2726 cfg->msi.msi_handlers = 0; 2727 *count = actual; 2728 return (0); 2729 } 2730 2731 /* Release the MSI messages associated with this device. */ 2732 int 2733 pci_release_msi_method(device_t dev, device_t child) 2734 { 2735 struct pci_devinfo *dinfo = device_get_ivars(child); 2736 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2737 struct resource_list_entry *rle; 2738 u_int i, irqs[32]; 2739 int error; 2740 2741 /* Try MSI-X first. */ 2742 error = pci_release_msix(dev, child); 2743 if (error != ENODEV) 2744 return (error); 2745 2746 /* Do we have any messages to release? */ 2747 if (msi->msi_alloc == 0) 2748 return (ENODEV); 2749 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages")); 2750 2751 /* Make sure none of the resources are allocated. */ 2752 if (msi->msi_handlers > 0) 2753 return (EBUSY); 2754 for (i = 0; i < msi->msi_alloc; i++) { 2755 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1); 2756 KASSERT(rle != NULL, ("missing MSI resource")); 2757 if (rle->res != NULL) 2758 return (EBUSY); 2759 irqs[i] = rle->start; 2760 } 2761 2762 /* Update control register with 0 count. */ 2763 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE), 2764 ("%s: MSI still enabled", __func__)); 2765 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK; 2766 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL, 2767 msi->msi_ctrl, 2); 2768 2769 /* Release the messages. */ 2770 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs); 2771 for (i = 0; i < msi->msi_alloc; i++) 2772 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1); 2773 2774 /* Update alloc count. */ 2775 msi->msi_alloc = 0; 2776 msi->msi_addr = 0; 2777 msi->msi_data = 0; 2778 return (0); 2779 } 2780 2781 /* 2782 * Return the max supported MSI messages this device supports. 2783 * Basically, assuming the MD code can alloc messages, this function 2784 * should return the maximum value that pci_alloc_msi() can return. 2785 * Thus, it is subject to the tunables, etc. 2786 */ 2787 int 2788 pci_msi_count_method(device_t dev, device_t child) 2789 { 2790 struct pci_devinfo *dinfo = device_get_ivars(child); 2791 struct pcicfg_msi *msi = &dinfo->cfg.msi; 2792 uint16_t ctrl; 2793 2794 if (pci_do_msi && msi->msi_location != 0) { 2795 ctrl = pci_read_config(child, msi->msi_location + PCIR_MSI_CTRL, 2796 2); 2797 return (PCI_MSI_MSGNUM(ctrl)); 2798 } 2799 return (0); 2800 } 2801 2802 /* free pcicfgregs structure and all depending data structures */ 2803 2804 int 2805 pci_freecfg(struct pci_devinfo *dinfo) 2806 { 2807 struct devlist *devlist_head; 2808 struct pci_map *pm, *next; 2809 2810 devlist_head = &pci_devq; 2811 2812 if (dinfo->cfg.vpd.vpd_reg) 2813 vpd_free(&dinfo->cfg.vpd); 2814 2815 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) { 2816 free(pm, M_DEVBUF); 2817 } 2818 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 2819 free(dinfo, M_DEVBUF); 2820 2821 /* increment the generation count */ 2822 pci_generation++; 2823 2824 /* we're losing one device */ 2825 pci_numdevs--; 2826 return (0); 2827 } 2828 2829 /* 2830 * PCI power manangement 2831 */ 2832 int 2833 pci_set_powerstate_method(device_t dev, device_t child, int state) 2834 { 2835 struct pci_devinfo *dinfo = device_get_ivars(child); 2836 pcicfgregs *cfg = &dinfo->cfg; 2837 uint16_t status; 2838 int oldstate, highest, delay; 2839 2840 if (cfg->pp.pp_location == 0) 2841 return (EOPNOTSUPP); 2842 2843 /* 2844 * Optimize a no state change request away. While it would be OK to 2845 * write to the hardware in theory, some devices have shown odd 2846 * behavior when going from D3 -> D3. 2847 */ 2848 oldstate = pci_get_powerstate(child); 2849 if (oldstate == state) 2850 return (0); 2851 2852 /* 2853 * The PCI power management specification states that after a state 2854 * transition between PCI power states, system software must 2855 * guarantee a minimal delay before the function accesses the device. 2856 * Compute the worst case delay that we need to guarantee before we 2857 * access the device. Many devices will be responsive much more 2858 * quickly than this delay, but there are some that don't respond 2859 * instantly to state changes. Transitions to/from D3 state require 2860 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 2861 * is done below with DELAY rather than a sleeper function because 2862 * this function can be called from contexts where we cannot sleep. 2863 */ 2864 highest = (oldstate > state) ? oldstate : state; 2865 if (highest == PCI_POWERSTATE_D3) 2866 delay = 10000; 2867 else if (highest == PCI_POWERSTATE_D2) 2868 delay = 200; 2869 else 2870 delay = 0; 2871 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_location + 2872 PCIR_POWER_STATUS, 2) & ~PCIM_PSTAT_DMASK; 2873 switch (state) { 2874 case PCI_POWERSTATE_D0: 2875 status |= PCIM_PSTAT_D0; 2876 break; 2877 case PCI_POWERSTATE_D1: 2878 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 2879 return (EOPNOTSUPP); 2880 status |= PCIM_PSTAT_D1; 2881 break; 2882 case PCI_POWERSTATE_D2: 2883 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 2884 return (EOPNOTSUPP); 2885 status |= PCIM_PSTAT_D2; 2886 break; 2887 case PCI_POWERSTATE_D3: 2888 status |= PCIM_PSTAT_D3; 2889 break; 2890 default: 2891 return (EINVAL); 2892 } 2893 2894 if (bootverbose) 2895 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate, 2896 state); 2897 2898 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_location + PCIR_POWER_STATUS, 2899 status, 2); 2900 if (delay) 2901 DELAY(delay); 2902 return (0); 2903 } 2904 2905 int 2906 pci_get_powerstate_method(device_t dev, device_t child) 2907 { 2908 struct pci_devinfo *dinfo = device_get_ivars(child); 2909 pcicfgregs *cfg = &dinfo->cfg; 2910 uint16_t status; 2911 int result; 2912 2913 if (cfg->pp.pp_location != 0) { 2914 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_location + 2915 PCIR_POWER_STATUS, 2); 2916 switch (status & PCIM_PSTAT_DMASK) { 2917 case PCIM_PSTAT_D0: 2918 result = PCI_POWERSTATE_D0; 2919 break; 2920 case PCIM_PSTAT_D1: 2921 result = PCI_POWERSTATE_D1; 2922 break; 2923 case PCIM_PSTAT_D2: 2924 result = PCI_POWERSTATE_D2; 2925 break; 2926 case PCIM_PSTAT_D3: 2927 result = PCI_POWERSTATE_D3; 2928 break; 2929 default: 2930 result = PCI_POWERSTATE_UNKNOWN; 2931 break; 2932 } 2933 } else { 2934 /* No support, device is always at D0 */ 2935 result = PCI_POWERSTATE_D0; 2936 } 2937 return (result); 2938 } 2939 2940 /* Clear any active PME# and disable PME# generation. */ 2941 void 2942 pci_clear_pme(device_t dev) 2943 { 2944 struct pci_devinfo *dinfo = device_get_ivars(dev); 2945 pcicfgregs *cfg = &dinfo->cfg; 2946 uint16_t status; 2947 2948 if (cfg->pp.pp_location != 0) { 2949 status = pci_read_config(dev, dinfo->cfg.pp.pp_location + 2950 PCIR_POWER_STATUS, 2); 2951 status &= ~PCIM_PSTAT_PMEENABLE; 2952 status |= PCIM_PSTAT_PME; 2953 pci_write_config(dev, dinfo->cfg.pp.pp_location + 2954 PCIR_POWER_STATUS, status, 2); 2955 } 2956 } 2957 2958 /* Clear any active PME# and enable PME# generation. */ 2959 void 2960 pci_enable_pme(device_t dev) 2961 { 2962 struct pci_devinfo *dinfo = device_get_ivars(dev); 2963 pcicfgregs *cfg = &dinfo->cfg; 2964 uint16_t status; 2965 2966 if (cfg->pp.pp_location != 0) { 2967 status = pci_read_config(dev, dinfo->cfg.pp.pp_location + 2968 PCIR_POWER_STATUS, 2); 2969 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2970 pci_write_config(dev, dinfo->cfg.pp.pp_location + 2971 PCIR_POWER_STATUS, status, 2); 2972 } 2973 } 2974 2975 bool 2976 pci_has_pm(device_t dev) 2977 { 2978 struct pci_devinfo *dinfo = device_get_ivars(dev); 2979 pcicfgregs *cfg = &dinfo->cfg; 2980 2981 return (cfg->pp.pp_location != 0); 2982 } 2983 2984 /* 2985 * Some convenience functions for PCI device drivers. 2986 */ 2987 2988 static __inline void 2989 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 2990 { 2991 uint16_t command; 2992 2993 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 2994 command |= bit; 2995 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 2996 } 2997 2998 static __inline void 2999 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 3000 { 3001 uint16_t command; 3002 3003 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 3004 command &= ~bit; 3005 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 3006 } 3007 3008 int 3009 pci_enable_busmaster_method(device_t dev, device_t child) 3010 { 3011 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 3012 return (0); 3013 } 3014 3015 int 3016 pci_disable_busmaster_method(device_t dev, device_t child) 3017 { 3018 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 3019 return (0); 3020 } 3021 3022 int 3023 pci_enable_io_method(device_t dev, device_t child, int space) 3024 { 3025 uint16_t bit; 3026 3027 switch(space) { 3028 case SYS_RES_IOPORT: 3029 bit = PCIM_CMD_PORTEN; 3030 break; 3031 case SYS_RES_MEMORY: 3032 bit = PCIM_CMD_MEMEN; 3033 break; 3034 default: 3035 return (EINVAL); 3036 } 3037 pci_set_command_bit(dev, child, bit); 3038 return (0); 3039 } 3040 3041 int 3042 pci_disable_io_method(device_t dev, device_t child, int space) 3043 { 3044 uint16_t bit; 3045 3046 switch(space) { 3047 case SYS_RES_IOPORT: 3048 bit = PCIM_CMD_PORTEN; 3049 break; 3050 case SYS_RES_MEMORY: 3051 bit = PCIM_CMD_MEMEN; 3052 break; 3053 default: 3054 return (EINVAL); 3055 } 3056 pci_clear_command_bit(dev, child, bit); 3057 return (0); 3058 } 3059 3060 /* 3061 * New style pci driver. Parent device is either a pci-host-bridge or a 3062 * pci-pci-bridge. Both kinds are represented by instances of pcib. 3063 */ 3064 3065 void 3066 pci_print_verbose(struct pci_devinfo *dinfo) 3067 { 3068 3069 if (bootverbose) { 3070 pcicfgregs *cfg = &dinfo->cfg; 3071 3072 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 3073 cfg->vendor, cfg->device, cfg->revid); 3074 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n", 3075 cfg->domain, cfg->bus, cfg->slot, cfg->func); 3076 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 3077 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 3078 cfg->mfdev); 3079 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 3080 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 3081 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 3082 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 3083 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 3084 if (cfg->intpin > 0) 3085 printf("\tintpin=%c, irq=%d\n", 3086 cfg->intpin +'a' -1, cfg->intline); 3087 if (cfg->pp.pp_location) { 3088 uint16_t status; 3089 3090 status = pci_read_config(cfg->dev, cfg->pp.pp_location + 3091 PCIR_POWER_STATUS, 2); 3092 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 3093 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 3094 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 3095 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 3096 status & PCIM_PSTAT_DMASK); 3097 } 3098 if (cfg->msi.msi_location) { 3099 uint16_t ctrl, msgnum; 3100 3101 ctrl = cfg->msi.msi_ctrl; 3102 msgnum = PCI_MSI_MSGNUM(ctrl); 3103 printf("\tMSI supports %d message%s%s%s\n", 3104 msgnum, (msgnum == 1) ? "" : "s", 3105 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 3106 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 3107 } 3108 if (cfg->msix.msix_location) { 3109 uint16_t msgnum; 3110 3111 msgnum = PCI_MSIX_MSGNUM(cfg->msix.msix_ctrl); 3112 printf("\tMSI-X supports %d message%s ", 3113 msgnum, (msgnum == 1) ? "" : "s"); 3114 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar) 3115 printf("in map 0x%x\n", 3116 cfg->msix.msix_table_bar); 3117 else 3118 printf("in maps 0x%x and 0x%x\n", 3119 cfg->msix.msix_table_bar, 3120 cfg->msix.msix_pba_bar); 3121 } 3122 } 3123 } 3124 3125 static int 3126 pci_porten(device_t dev) 3127 { 3128 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0; 3129 } 3130 3131 static int 3132 pci_memen(device_t dev) 3133 { 3134 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0; 3135 } 3136 3137 void 3138 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp, 3139 int *bar64) 3140 { 3141 struct pci_devinfo *dinfo; 3142 pci_addr_t map, testval; 3143 int ln2range; 3144 uint16_t cmd; 3145 3146 /* 3147 * The device ROM BAR is special. It is always a 32-bit 3148 * memory BAR. Bit 0 is special and should not be set when 3149 * sizing the BAR. 3150 */ 3151 dinfo = device_get_ivars(dev); 3152 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) { 3153 map = pci_read_config(dev, reg, 4); 3154 pci_write_config(dev, reg, 0xfffffffe, 4); 3155 testval = pci_read_config(dev, reg, 4); 3156 pci_write_config(dev, reg, map, 4); 3157 *mapp = map; 3158 *testvalp = testval; 3159 if (bar64 != NULL) 3160 *bar64 = 0; 3161 return; 3162 } 3163 3164 map = pci_read_config(dev, reg, 4); 3165 ln2range = pci_maprange(map); 3166 if (ln2range == 64) 3167 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3168 3169 /* 3170 * Disable decoding via the command register before 3171 * determining the BAR's length since we will be placing it in 3172 * a weird state. 3173 */ 3174 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3175 pci_write_config(dev, PCIR_COMMAND, 3176 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 3177 3178 /* 3179 * Determine the BAR's length by writing all 1's. The bottom 3180 * log_2(size) bits of the BAR will stick as 0 when we read 3181 * the value back. 3182 * 3183 * NB: according to the PCI Local Bus Specification, rev. 3.0: 3184 * "Software writes 0FFFFFFFFh to both registers, reads them back, 3185 * and combines the result into a 64-bit value." (section 6.2.5.1) 3186 * 3187 * Writes to both registers must be performed before attempting to 3188 * read back the size value. 3189 */ 3190 testval = 0; 3191 pci_write_config(dev, reg, 0xffffffff, 4); 3192 if (ln2range == 64) { 3193 pci_write_config(dev, reg + 4, 0xffffffff, 4); 3194 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32; 3195 } 3196 testval |= pci_read_config(dev, reg, 4); 3197 3198 /* 3199 * Restore the original value of the BAR. We may have reprogrammed 3200 * the BAR of the low-level console device and when booting verbose, 3201 * we need the console device addressable. 3202 */ 3203 pci_write_config(dev, reg, map, 4); 3204 if (ln2range == 64) 3205 pci_write_config(dev, reg + 4, map >> 32, 4); 3206 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3207 3208 *mapp = map; 3209 *testvalp = testval; 3210 if (bar64 != NULL) 3211 *bar64 = (ln2range == 64); 3212 } 3213 3214 static void 3215 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base) 3216 { 3217 struct pci_devinfo *dinfo; 3218 int ln2range; 3219 3220 /* The device ROM BAR is always a 32-bit memory BAR. */ 3221 dinfo = device_get_ivars(dev); 3222 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3223 ln2range = 32; 3224 else 3225 ln2range = pci_maprange(pm->pm_value); 3226 pci_write_config(dev, pm->pm_reg, base, 4); 3227 if (ln2range == 64) 3228 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4); 3229 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4); 3230 if (ln2range == 64) 3231 pm->pm_value |= (pci_addr_t)pci_read_config(dev, 3232 pm->pm_reg + 4, 4) << 32; 3233 } 3234 3235 struct pci_map * 3236 pci_find_bar(device_t dev, int reg) 3237 { 3238 struct pci_devinfo *dinfo; 3239 struct pci_map *pm; 3240 3241 dinfo = device_get_ivars(dev); 3242 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3243 if (pm->pm_reg == reg) 3244 return (pm); 3245 } 3246 return (NULL); 3247 } 3248 3249 struct pci_map * 3250 pci_first_bar(device_t dev) 3251 { 3252 struct pci_devinfo *dinfo; 3253 3254 dinfo = device_get_ivars(dev); 3255 return (STAILQ_FIRST(&dinfo->cfg.maps)); 3256 } 3257 3258 struct pci_map * 3259 pci_next_bar(struct pci_map *pm) 3260 { 3261 return (STAILQ_NEXT(pm, pm_link)); 3262 } 3263 3264 int 3265 pci_bar_enabled(device_t dev, struct pci_map *pm) 3266 { 3267 struct pci_devinfo *dinfo; 3268 uint16_t cmd; 3269 3270 dinfo = device_get_ivars(dev); 3271 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) && 3272 !(pm->pm_value & PCIM_BIOS_ENABLE)) 3273 return (0); 3274 #ifdef PCI_IOV 3275 if ((dinfo->cfg.flags & PCICFG_VF) != 0) { 3276 struct pcicfg_iov *iov; 3277 3278 iov = dinfo->cfg.iov; 3279 cmd = pci_read_config(iov->iov_pf, 3280 iov->iov_pos + PCIR_SRIOV_CTL, 2); 3281 return ((cmd & PCIM_SRIOV_VF_MSE) != 0); 3282 } 3283 #endif 3284 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3285 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value)) 3286 return ((cmd & PCIM_CMD_MEMEN) != 0); 3287 else 3288 return ((cmd & PCIM_CMD_PORTEN) != 0); 3289 } 3290 3291 struct pci_map * 3292 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size) 3293 { 3294 struct pci_devinfo *dinfo; 3295 struct pci_map *pm, *prev; 3296 3297 dinfo = device_get_ivars(dev); 3298 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO); 3299 pm->pm_reg = reg; 3300 pm->pm_value = value; 3301 pm->pm_size = size; 3302 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) { 3303 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x", 3304 reg)); 3305 if (STAILQ_NEXT(prev, pm_link) == NULL || 3306 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg) 3307 break; 3308 } 3309 if (prev != NULL) 3310 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link); 3311 else 3312 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link); 3313 return (pm); 3314 } 3315 3316 static void 3317 pci_restore_bars(device_t dev) 3318 { 3319 struct pci_devinfo *dinfo; 3320 struct pci_map *pm; 3321 int ln2range; 3322 3323 dinfo = device_get_ivars(dev); 3324 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) { 3325 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg)) 3326 ln2range = 32; 3327 else 3328 ln2range = pci_maprange(pm->pm_value); 3329 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4); 3330 if (ln2range == 64) 3331 pci_write_config(dev, pm->pm_reg + 4, 3332 pm->pm_value >> 32, 4); 3333 } 3334 } 3335 3336 /* 3337 * Add a resource based on a pci map register. Return 1 if the map 3338 * register is a 32bit map register or 2 if it is a 64bit register. 3339 */ 3340 static int 3341 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl, 3342 int force, int prefetch) 3343 { 3344 struct pci_map *pm; 3345 pci_addr_t base, map, testval; 3346 pci_addr_t start, end, count; 3347 int barlen, basezero, flags, maprange, mapsize, type; 3348 uint16_t cmd; 3349 struct resource *res; 3350 3351 /* 3352 * The BAR may already exist if the device is a CardBus card 3353 * whose CIS is stored in this BAR. 3354 */ 3355 pm = pci_find_bar(dev, reg); 3356 if (pm != NULL) { 3357 maprange = pci_maprange(pm->pm_value); 3358 barlen = maprange == 64 ? 2 : 1; 3359 return (barlen); 3360 } 3361 3362 pci_read_bar(dev, reg, &map, &testval, NULL); 3363 if (PCI_BAR_MEM(map)) { 3364 type = SYS_RES_MEMORY; 3365 if (map & PCIM_BAR_MEM_PREFETCH) 3366 prefetch = 1; 3367 } else 3368 type = SYS_RES_IOPORT; 3369 mapsize = pci_mapsize(testval); 3370 base = pci_mapbase(map); 3371 #ifdef __PCI_BAR_ZERO_VALID 3372 basezero = 0; 3373 #else 3374 basezero = base == 0; 3375 #endif 3376 maprange = pci_maprange(map); 3377 barlen = maprange == 64 ? 2 : 1; 3378 3379 /* 3380 * For I/O registers, if bottom bit is set, and the next bit up 3381 * isn't clear, we know we have a BAR that doesn't conform to the 3382 * spec, so ignore it. Also, sanity check the size of the data 3383 * areas to the type of memory involved. Memory must be at least 3384 * 16 bytes in size, while I/O ranges must be at least 4. 3385 */ 3386 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0) 3387 return (barlen); 3388 if ((type == SYS_RES_MEMORY && mapsize < 4) || 3389 (type == SYS_RES_IOPORT && mapsize < 2)) 3390 return (barlen); 3391 3392 /* Save a record of this BAR. */ 3393 pm = pci_add_bar(dev, reg, map, mapsize); 3394 if (bootverbose) { 3395 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d", 3396 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize); 3397 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3398 printf(", port disabled\n"); 3399 else if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3400 printf(", memory disabled\n"); 3401 else 3402 printf(", enabled\n"); 3403 } 3404 3405 /* 3406 * If base is 0, then we have problems if this architecture does 3407 * not allow that. It is best to ignore such entries for the 3408 * moment. These will be allocated later if the driver specifically 3409 * requests them. However, some removable buses look better when 3410 * all resources are allocated, so allow '0' to be overridden. 3411 * 3412 * Similarly treat maps whose values is the same as the test value 3413 * read back. These maps have had all f's written to them by the 3414 * BIOS in an attempt to disable the resources. 3415 */ 3416 if (!force && (basezero || map == testval)) 3417 return (barlen); 3418 if ((u_long)base != base) { 3419 device_printf(bus, 3420 "pci%d:%d:%d:%d bar %#x too many address bits", 3421 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev), 3422 pci_get_function(dev), reg); 3423 return (barlen); 3424 } 3425 3426 /* 3427 * This code theoretically does the right thing, but has 3428 * undesirable side effects in some cases where peripherals 3429 * respond oddly to having these bits enabled. Let the user 3430 * be able to turn them off (since pci_enable_io_modes is 1 by 3431 * default). 3432 */ 3433 if (pci_enable_io_modes) { 3434 /* Turn on resources that have been left off by a lazy BIOS */ 3435 if (type == SYS_RES_IOPORT && !pci_porten(dev)) { 3436 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3437 cmd |= PCIM_CMD_PORTEN; 3438 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3439 } 3440 if (type == SYS_RES_MEMORY && !pci_memen(dev)) { 3441 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 3442 cmd |= PCIM_CMD_MEMEN; 3443 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 3444 } 3445 } else { 3446 if (type == SYS_RES_IOPORT && !pci_porten(dev)) 3447 return (barlen); 3448 if (type == SYS_RES_MEMORY && !pci_memen(dev)) 3449 return (barlen); 3450 } 3451 3452 count = (pci_addr_t)1 << mapsize; 3453 flags = RF_ALIGNMENT_LOG2(mapsize); 3454 if (prefetch) 3455 flags |= RF_PREFETCHABLE; 3456 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) { 3457 start = 0; /* Let the parent decide. */ 3458 end = ~0; 3459 } else { 3460 start = base; 3461 end = base + count - 1; 3462 } 3463 resource_list_add(rl, type, reg, start, end, count); 3464 3465 /* 3466 * Try to allocate the resource for this BAR from our parent 3467 * so that this resource range is already reserved. The 3468 * driver for this device will later inherit this resource in 3469 * pci_alloc_resource(). 3470 */ 3471 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count, 3472 flags); 3473 if ((pci_do_realloc_bars 3474 || pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_REALLOC_BAR)) 3475 && res == NULL && (start != 0 || end != ~0)) { 3476 /* 3477 * If the allocation fails, try to allocate a resource for 3478 * this BAR using any available range. The firmware felt 3479 * it was important enough to assign a resource, so don't 3480 * disable decoding if we can help it. 3481 */ 3482 resource_list_delete(rl, type, reg); 3483 resource_list_add(rl, type, reg, 0, ~0, count); 3484 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0, 3485 count, flags); 3486 } 3487 if (res == NULL) { 3488 /* 3489 * If the allocation fails, delete the resource list entry 3490 * and disable decoding for this device. 3491 * 3492 * If the driver requests this resource in the future, 3493 * pci_reserve_map() will try to allocate a fresh 3494 * resource range. 3495 */ 3496 resource_list_delete(rl, type, reg); 3497 pci_disable_io(dev, type); 3498 if (bootverbose) 3499 device_printf(bus, 3500 "pci%d:%d:%d:%d bar %#x failed to allocate\n", 3501 pci_get_domain(dev), pci_get_bus(dev), 3502 pci_get_slot(dev), pci_get_function(dev), reg); 3503 } else { 3504 start = rman_get_start(res); 3505 pci_write_bar(dev, pm, start); 3506 } 3507 return (barlen); 3508 } 3509 3510 /* 3511 * For ATA devices we need to decide early what addressing mode to use. 3512 * Legacy demands that the primary and secondary ATA ports sits on the 3513 * same addresses that old ISA hardware did. This dictates that we use 3514 * those addresses and ignore the BAR's if we cannot set PCI native 3515 * addressing mode. 3516 */ 3517 static void 3518 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force, 3519 uint32_t prefetchmask) 3520 { 3521 int rid, type, progif; 3522 #if 0 3523 /* if this device supports PCI native addressing use it */ 3524 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3525 if ((progif & 0x8a) == 0x8a) { 3526 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 3527 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 3528 printf("Trying ATA native PCI addressing mode\n"); 3529 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 3530 } 3531 } 3532 #endif 3533 progif = pci_read_config(dev, PCIR_PROGIF, 1); 3534 type = SYS_RES_IOPORT; 3535 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 3536 pci_add_map(bus, dev, PCIR_BAR(0), rl, force, 3537 prefetchmask & (1 << 0)); 3538 pci_add_map(bus, dev, PCIR_BAR(1), rl, force, 3539 prefetchmask & (1 << 1)); 3540 } else { 3541 rid = PCIR_BAR(0); 3542 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 3543 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0, 3544 0x1f7, 8, 0); 3545 rid = PCIR_BAR(1); 3546 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 3547 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6, 3548 0x3f6, 1, 0); 3549 } 3550 if (progif & PCIP_STORAGE_IDE_MODESEC) { 3551 pci_add_map(bus, dev, PCIR_BAR(2), rl, force, 3552 prefetchmask & (1 << 2)); 3553 pci_add_map(bus, dev, PCIR_BAR(3), rl, force, 3554 prefetchmask & (1 << 3)); 3555 } else { 3556 rid = PCIR_BAR(2); 3557 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 3558 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x170, 3559 0x177, 8, 0); 3560 rid = PCIR_BAR(3); 3561 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 3562 (void)resource_list_reserve(rl, bus, dev, type, &rid, 0x376, 3563 0x376, 1, 0); 3564 } 3565 pci_add_map(bus, dev, PCIR_BAR(4), rl, force, 3566 prefetchmask & (1 << 4)); 3567 pci_add_map(bus, dev, PCIR_BAR(5), rl, force, 3568 prefetchmask & (1 << 5)); 3569 } 3570 3571 static void 3572 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 3573 { 3574 struct pci_devinfo *dinfo = device_get_ivars(dev); 3575 pcicfgregs *cfg = &dinfo->cfg; 3576 char tunable_name[64]; 3577 int irq; 3578 3579 /* Has to have an intpin to have an interrupt. */ 3580 if (cfg->intpin == 0) 3581 return; 3582 3583 /* Let the user override the IRQ with a tunable. */ 3584 irq = PCI_INVALID_IRQ; 3585 snprintf(tunable_name, sizeof(tunable_name), 3586 "hw.pci%d.%d.%d.INT%c.irq", 3587 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 3588 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 3589 irq = PCI_INVALID_IRQ; 3590 3591 /* 3592 * If we didn't get an IRQ via the tunable, then we either use the 3593 * IRQ value in the intline register or we ask the bus to route an 3594 * interrupt for us. If force_route is true, then we only use the 3595 * value in the intline register if the bus was unable to assign an 3596 * IRQ. 3597 */ 3598 if (!PCI_INTERRUPT_VALID(irq)) { 3599 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 3600 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 3601 if (!PCI_INTERRUPT_VALID(irq)) 3602 irq = cfg->intline; 3603 } 3604 3605 /* If after all that we don't have an IRQ, just bail. */ 3606 if (!PCI_INTERRUPT_VALID(irq)) 3607 return; 3608 3609 /* Update the config register if it changed. */ 3610 if (irq != cfg->intline) { 3611 cfg->intline = irq; 3612 pci_write_config(dev, PCIR_INTLINE, irq, 1); 3613 } 3614 3615 /* Add this IRQ as rid 0 interrupt resource. */ 3616 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 3617 } 3618 3619 /* Perform early OHCI takeover from SMM. */ 3620 static void 3621 ohci_early_takeover(device_t self) 3622 { 3623 struct resource *res; 3624 uint32_t ctl; 3625 int rid; 3626 int i; 3627 3628 rid = PCIR_BAR(0); 3629 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3630 if (res == NULL) 3631 return; 3632 3633 ctl = bus_read_4(res, OHCI_CONTROL); 3634 if (ctl & OHCI_IR) { 3635 if (bootverbose) 3636 printf("ohci early: " 3637 "SMM active, request owner change\n"); 3638 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR); 3639 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 3640 DELAY(1000); 3641 ctl = bus_read_4(res, OHCI_CONTROL); 3642 } 3643 if (ctl & OHCI_IR) { 3644 if (bootverbose) 3645 printf("ohci early: " 3646 "SMM does not respond, resetting\n"); 3647 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET); 3648 } 3649 /* Disable interrupts */ 3650 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 3651 } 3652 3653 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3654 } 3655 3656 /* Perform early UHCI takeover from SMM. */ 3657 static void 3658 uhci_early_takeover(device_t self) 3659 { 3660 struct resource *res; 3661 int rid; 3662 3663 /* 3664 * Set the PIRQD enable bit and switch off all the others. We don't 3665 * want legacy support to interfere with us XXX Does this also mean 3666 * that the BIOS won't touch the keyboard anymore if it is connected 3667 * to the ports of the root hub? 3668 */ 3669 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2); 3670 3671 /* Disable interrupts */ 3672 rid = PCI_UHCI_BASE_REG; 3673 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE); 3674 if (res != NULL) { 3675 bus_write_2(res, UHCI_INTR, 0); 3676 bus_release_resource(self, SYS_RES_IOPORT, rid, res); 3677 } 3678 } 3679 3680 /* Perform early EHCI takeover from SMM. */ 3681 static void 3682 ehci_early_takeover(device_t self) 3683 { 3684 struct resource *res; 3685 uint32_t cparams; 3686 uint32_t eec; 3687 uint8_t eecp; 3688 uint8_t bios_sem; 3689 uint8_t offs; 3690 int rid; 3691 int i; 3692 3693 rid = PCIR_BAR(0); 3694 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3695 if (res == NULL) 3696 return; 3697 3698 cparams = bus_read_4(res, EHCI_HCCPARAMS); 3699 3700 /* Synchronise with the BIOS if it owns the controller. */ 3701 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0; 3702 eecp = EHCI_EECP_NEXT(eec)) { 3703 eec = pci_read_config(self, eecp, 4); 3704 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) { 3705 continue; 3706 } 3707 bios_sem = pci_read_config(self, eecp + 3708 EHCI_LEGSUP_BIOS_SEM, 1); 3709 if (bios_sem == 0) { 3710 continue; 3711 } 3712 if (bootverbose) 3713 printf("ehci early: " 3714 "SMM active, request owner change\n"); 3715 3716 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1); 3717 3718 for (i = 0; (i < 100) && (bios_sem != 0); i++) { 3719 DELAY(1000); 3720 bios_sem = pci_read_config(self, eecp + 3721 EHCI_LEGSUP_BIOS_SEM, 1); 3722 } 3723 3724 if (bios_sem != 0) { 3725 if (bootverbose) 3726 printf("ehci early: " 3727 "SMM does not respond\n"); 3728 } 3729 /* Disable interrupts */ 3730 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION)); 3731 bus_write_4(res, offs + EHCI_USBINTR, 0); 3732 } 3733 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3734 } 3735 3736 /* Perform early XHCI takeover from SMM. */ 3737 static void 3738 xhci_early_takeover(device_t self) 3739 { 3740 struct resource *res; 3741 uint32_t cparams; 3742 uint32_t eec; 3743 uint8_t eecp; 3744 uint8_t bios_sem; 3745 uint8_t offs; 3746 int rid; 3747 int i; 3748 3749 rid = PCIR_BAR(0); 3750 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); 3751 if (res == NULL) 3752 return; 3753 3754 cparams = bus_read_4(res, XHCI_HCSPARAMS0); 3755 3756 eec = -1; 3757 3758 /* Synchronise with the BIOS if it owns the controller. */ 3759 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 3760 eecp += XHCI_XECP_NEXT(eec) << 2) { 3761 eec = bus_read_4(res, eecp); 3762 3763 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 3764 continue; 3765 3766 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM); 3767 if (bios_sem == 0) 3768 continue; 3769 3770 if (bootverbose) 3771 printf("xhci early: " 3772 "SMM active, request owner change\n"); 3773 3774 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1); 3775 3776 /* wait a maximum of 5 second */ 3777 3778 for (i = 0; (i < 5000) && (bios_sem != 0); i++) { 3779 DELAY(1000); 3780 bios_sem = bus_read_1(res, eecp + 3781 XHCI_XECP_BIOS_SEM); 3782 } 3783 3784 if (bios_sem != 0) { 3785 if (bootverbose) 3786 printf("xhci early: " 3787 "SMM does not respond\n"); 3788 } 3789 3790 /* Disable interrupts */ 3791 offs = bus_read_1(res, XHCI_CAPLENGTH); 3792 bus_write_4(res, offs + XHCI_USBCMD, 0); 3793 bus_read_4(res, offs + XHCI_USBSTS); 3794 } 3795 bus_release_resource(self, SYS_RES_MEMORY, rid, res); 3796 } 3797 3798 static void 3799 pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg, 3800 struct resource_list *rl) 3801 { 3802 struct resource *res; 3803 char *cp; 3804 rman_res_t start, end, count; 3805 int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus; 3806 3807 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3808 case PCIM_HDRTYPE_BRIDGE: 3809 sec_reg = PCIR_SECBUS_1; 3810 sub_reg = PCIR_SUBBUS_1; 3811 break; 3812 case PCIM_HDRTYPE_CARDBUS: 3813 sec_reg = PCIR_SECBUS_2; 3814 sub_reg = PCIR_SUBBUS_2; 3815 break; 3816 default: 3817 return; 3818 } 3819 3820 /* 3821 * If the existing bus range is valid, attempt to reserve it 3822 * from our parent. If this fails for any reason, clear the 3823 * secbus and subbus registers. 3824 * 3825 * XXX: Should we reset sub_bus to sec_bus if it is < sec_bus? 3826 * This would at least preserve the existing sec_bus if it is 3827 * valid. 3828 */ 3829 sec_bus = PCI_READ_CONFIG(bus, dev, sec_reg, 1); 3830 sub_bus = PCI_READ_CONFIG(bus, dev, sub_reg, 1); 3831 3832 /* Quirk handling. */ 3833 switch (pci_get_devid(dev)) { 3834 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 3835 sup_bus = pci_read_config(dev, 0x41, 1); 3836 if (sup_bus != 0xff) { 3837 sec_bus = sup_bus + 1; 3838 sub_bus = sup_bus + 1; 3839 PCI_WRITE_CONFIG(bus, dev, sec_reg, sec_bus, 1); 3840 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3841 } 3842 break; 3843 3844 case 0x00dd10de: 3845 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 3846 if ((cp = kern_getenv("smbios.planar.maker")) == NULL) 3847 break; 3848 if (strncmp(cp, "Compal", 6) != 0) { 3849 freeenv(cp); 3850 break; 3851 } 3852 freeenv(cp); 3853 if ((cp = kern_getenv("smbios.planar.product")) == NULL) 3854 break; 3855 if (strncmp(cp, "08A0", 4) != 0) { 3856 freeenv(cp); 3857 break; 3858 } 3859 freeenv(cp); 3860 if (sub_bus < 0xa) { 3861 sub_bus = 0xa; 3862 PCI_WRITE_CONFIG(bus, dev, sub_reg, sub_bus, 1); 3863 } 3864 break; 3865 } 3866 3867 if (bootverbose) 3868 printf("\tsecbus=%d, subbus=%d\n", sec_bus, sub_bus); 3869 if (sec_bus > 0 && sub_bus >= sec_bus) { 3870 start = sec_bus; 3871 end = sub_bus; 3872 count = end - start + 1; 3873 3874 resource_list_add(rl, PCI_RES_BUS, 0, 0, ~0, count); 3875 3876 /* 3877 * If requested, clear secondary bus registers in 3878 * bridge devices to force a complete renumbering 3879 * rather than reserving the existing range. However, 3880 * preserve the existing size. 3881 */ 3882 if (pci_clear_buses) 3883 goto clear; 3884 3885 rid = 0; 3886 res = resource_list_reserve(rl, bus, dev, PCI_RES_BUS, &rid, 3887 start, end, count, 0); 3888 if (res != NULL) 3889 return; 3890 3891 if (bootverbose) 3892 device_printf(bus, 3893 "pci%d:%d:%d:%d secbus failed to allocate\n", 3894 pci_get_domain(dev), pci_get_bus(dev), 3895 pci_get_slot(dev), pci_get_function(dev)); 3896 } 3897 3898 clear: 3899 PCI_WRITE_CONFIG(bus, dev, sec_reg, 0, 1); 3900 PCI_WRITE_CONFIG(bus, dev, sub_reg, 0, 1); 3901 } 3902 3903 static struct resource * 3904 pci_alloc_secbus(device_t dev, device_t child, int *rid, rman_res_t start, 3905 rman_res_t end, rman_res_t count, u_int flags) 3906 { 3907 struct pci_devinfo *dinfo; 3908 pcicfgregs *cfg; 3909 struct resource_list *rl; 3910 struct resource *res; 3911 int sec_reg, sub_reg; 3912 3913 dinfo = device_get_ivars(child); 3914 cfg = &dinfo->cfg; 3915 rl = &dinfo->resources; 3916 switch (cfg->hdrtype & PCIM_HDRTYPE) { 3917 case PCIM_HDRTYPE_BRIDGE: 3918 sec_reg = PCIR_SECBUS_1; 3919 sub_reg = PCIR_SUBBUS_1; 3920 break; 3921 case PCIM_HDRTYPE_CARDBUS: 3922 sec_reg = PCIR_SECBUS_2; 3923 sub_reg = PCIR_SUBBUS_2; 3924 break; 3925 default: 3926 return (NULL); 3927 } 3928 3929 if (*rid != 0) 3930 return (NULL); 3931 3932 if (resource_list_find(rl, PCI_RES_BUS, *rid) == NULL) 3933 resource_list_add(rl, PCI_RES_BUS, *rid, start, end, count); 3934 if (!resource_list_reserved(rl, PCI_RES_BUS, *rid)) { 3935 res = resource_list_reserve(rl, dev, child, PCI_RES_BUS, rid, 3936 start, end, count, flags & ~RF_ACTIVE); 3937 if (res == NULL) { 3938 resource_list_delete(rl, PCI_RES_BUS, *rid); 3939 device_printf(child, "allocating %ju bus%s failed\n", 3940 count, count == 1 ? "" : "es"); 3941 return (NULL); 3942 } 3943 if (bootverbose) 3944 device_printf(child, 3945 "Lazy allocation of %ju bus%s at %ju\n", count, 3946 count == 1 ? "" : "es", rman_get_start(res)); 3947 PCI_WRITE_CONFIG(dev, child, sec_reg, rman_get_start(res), 1); 3948 PCI_WRITE_CONFIG(dev, child, sub_reg, rman_get_end(res), 1); 3949 } 3950 return (resource_list_alloc(rl, dev, child, PCI_RES_BUS, rid, start, 3951 end, count, flags)); 3952 } 3953 3954 static int 3955 pci_ea_bei_to_rid(device_t dev, int bei) 3956 { 3957 #ifdef PCI_IOV 3958 struct pci_devinfo *dinfo; 3959 int iov_pos; 3960 struct pcicfg_iov *iov; 3961 3962 dinfo = device_get_ivars(dev); 3963 iov = dinfo->cfg.iov; 3964 if (iov != NULL) 3965 iov_pos = iov->iov_pos; 3966 else 3967 iov_pos = 0; 3968 #endif 3969 3970 /* Check if matches BAR */ 3971 if ((bei >= PCIM_EA_BEI_BAR_0) && 3972 (bei <= PCIM_EA_BEI_BAR_5)) 3973 return (PCIR_BAR(bei)); 3974 3975 /* Check ROM */ 3976 if (bei == PCIM_EA_BEI_ROM) 3977 return (PCIR_BIOS); 3978 3979 #ifdef PCI_IOV 3980 /* Check if matches VF_BAR */ 3981 if ((iov != NULL) && (bei >= PCIM_EA_BEI_VF_BAR_0) && 3982 (bei <= PCIM_EA_BEI_VF_BAR_5)) 3983 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) + 3984 iov_pos); 3985 #endif 3986 3987 return (-1); 3988 } 3989 3990 int 3991 pci_ea_is_enabled(device_t dev, int rid) 3992 { 3993 struct pci_ea_entry *ea; 3994 struct pci_devinfo *dinfo; 3995 3996 dinfo = device_get_ivars(dev); 3997 3998 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 3999 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid) 4000 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0); 4001 } 4002 4003 return (0); 4004 } 4005 4006 void 4007 pci_add_resources_ea(device_t bus, device_t dev, int alloc_iov) 4008 { 4009 struct pci_ea_entry *ea; 4010 struct pci_devinfo *dinfo; 4011 pci_addr_t start, end, count; 4012 struct resource_list *rl; 4013 int type, flags, rid; 4014 struct resource *res; 4015 uint32_t tmp; 4016 #ifdef PCI_IOV 4017 struct pcicfg_iov *iov; 4018 #endif 4019 4020 dinfo = device_get_ivars(dev); 4021 rl = &dinfo->resources; 4022 flags = 0; 4023 4024 #ifdef PCI_IOV 4025 iov = dinfo->cfg.iov; 4026 #endif 4027 4028 if (dinfo->cfg.ea.ea_location == 0) 4029 return; 4030 4031 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) { 4032 /* 4033 * TODO: Ignore EA-BAR if is not enabled. 4034 * Currently the EA implementation supports 4035 * only situation, where EA structure contains 4036 * predefined entries. In case they are not enabled 4037 * leave them unallocated and proceed with 4038 * a legacy-BAR mechanism. 4039 */ 4040 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0) 4041 continue; 4042 4043 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) { 4044 case PCIM_EA_P_MEM_PREFETCH: 4045 case PCIM_EA_P_VF_MEM_PREFETCH: 4046 flags = RF_PREFETCHABLE; 4047 /* FALLTHROUGH */ 4048 case PCIM_EA_P_VF_MEM: 4049 case PCIM_EA_P_MEM: 4050 type = SYS_RES_MEMORY; 4051 break; 4052 case PCIM_EA_P_IO: 4053 type = SYS_RES_IOPORT; 4054 break; 4055 default: 4056 continue; 4057 } 4058 4059 if (alloc_iov != 0) { 4060 #ifdef PCI_IOV 4061 /* Allocating IOV, confirm BEI matches */ 4062 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) || 4063 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5)) 4064 continue; 4065 #else 4066 continue; 4067 #endif 4068 } else { 4069 /* Allocating BAR, confirm BEI matches */ 4070 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) || 4071 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) && 4072 (ea->eae_bei != PCIM_EA_BEI_ROM)) 4073 continue; 4074 } 4075 4076 rid = pci_ea_bei_to_rid(dev, ea->eae_bei); 4077 if (rid < 0) 4078 continue; 4079 4080 /* Skip resources already allocated by EA */ 4081 if ((resource_list_find(rl, SYS_RES_MEMORY, rid) != NULL) || 4082 (resource_list_find(rl, SYS_RES_IOPORT, rid) != NULL)) 4083 continue; 4084 4085 start = ea->eae_base; 4086 count = ea->eae_max_offset + 1; 4087 #ifdef PCI_IOV 4088 if (iov != NULL) 4089 count = count * iov->iov_num_vfs; 4090 #endif 4091 end = start + count - 1; 4092 if (count == 0) 4093 continue; 4094 4095 resource_list_add(rl, type, rid, start, end, count); 4096 res = resource_list_reserve(rl, bus, dev, type, &rid, start, end, count, 4097 flags); 4098 if (res == NULL) { 4099 resource_list_delete(rl, type, rid); 4100 4101 /* 4102 * Failed to allocate using EA, disable entry. 4103 * Another attempt to allocation will be performed 4104 * further, but this time using legacy BAR registers 4105 */ 4106 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4); 4107 tmp &= ~PCIM_EA_ENABLE; 4108 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4); 4109 4110 /* 4111 * Disabling entry might fail in case it is hardwired. 4112 * Read flags again to match current status. 4113 */ 4114 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4); 4115 4116 continue; 4117 } 4118 4119 /* As per specification, fill BAR with zeros */ 4120 pci_write_config(dev, rid, 0, 4); 4121 } 4122 } 4123 4124 void 4125 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 4126 { 4127 struct pci_devinfo *dinfo; 4128 pcicfgregs *cfg; 4129 struct resource_list *rl; 4130 const struct pci_quirk *q; 4131 uint32_t devid; 4132 int i; 4133 4134 dinfo = device_get_ivars(dev); 4135 cfg = &dinfo->cfg; 4136 rl = &dinfo->resources; 4137 devid = (cfg->device << 16) | cfg->vendor; 4138 4139 /* Allocate resources using Enhanced Allocation */ 4140 pci_add_resources_ea(bus, dev, 0); 4141 4142 /* ATA devices needs special map treatment */ 4143 if ((pci_get_class(dev) == PCIC_STORAGE) && 4144 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 4145 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) || 4146 (!pci_read_config(dev, PCIR_BAR(0), 4) && 4147 !pci_read_config(dev, PCIR_BAR(2), 4))) ) 4148 pci_ata_maps(bus, dev, rl, force, prefetchmask); 4149 else 4150 for (i = 0; i < cfg->nummaps;) { 4151 /* Skip resources already managed by EA */ 4152 if ((resource_list_find(rl, SYS_RES_MEMORY, PCIR_BAR(i)) != NULL) || 4153 (resource_list_find(rl, SYS_RES_IOPORT, PCIR_BAR(i)) != NULL) || 4154 pci_ea_is_enabled(dev, PCIR_BAR(i))) { 4155 i++; 4156 continue; 4157 } 4158 4159 /* 4160 * Skip quirked resources. 4161 */ 4162 for (q = &pci_quirks[0]; q->devid != 0; q++) 4163 if (q->devid == devid && 4164 q->type == PCI_QUIRK_UNMAP_REG && 4165 q->arg1 == PCIR_BAR(i)) 4166 break; 4167 if (q->devid != 0) { 4168 i++; 4169 continue; 4170 } 4171 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force, 4172 prefetchmask & (1 << i)); 4173 } 4174 4175 /* 4176 * Add additional, quirked resources. 4177 */ 4178 for (q = &pci_quirks[0]; q->devid != 0; q++) 4179 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG) 4180 pci_add_map(bus, dev, q->arg1, rl, force, 0); 4181 4182 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline) && 4183 pci_intx_reroute) { 4184 /* 4185 * Try to re-route interrupts. Sometimes the BIOS or 4186 * firmware may leave bogus values in these registers. 4187 * If the re-route fails, then just stick with what we 4188 * have. 4189 */ 4190 pci_assign_interrupt(bus, dev, 1); 4191 } 4192 4193 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS && 4194 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) { 4195 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI) 4196 xhci_early_takeover(dev); 4197 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI) 4198 ehci_early_takeover(dev); 4199 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI) 4200 ohci_early_takeover(dev); 4201 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI) 4202 uhci_early_takeover(dev); 4203 } 4204 4205 /* 4206 * Reserve resources for secondary bus ranges behind bridge 4207 * devices. 4208 */ 4209 pci_reserve_secbus(bus, dev, cfg, rl); 4210 } 4211 4212 static struct pci_devinfo * 4213 pci_identify_function(device_t pcib, device_t dev, int domain, int busno, 4214 int slot, int func) 4215 { 4216 struct pci_devinfo *dinfo; 4217 4218 dinfo = pci_read_device(pcib, dev, domain, busno, slot, func); 4219 if (dinfo != NULL) 4220 pci_add_child(dev, dinfo); 4221 4222 return (dinfo); 4223 } 4224 4225 void 4226 pci_add_children(device_t dev, int domain, int busno) 4227 { 4228 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4229 device_t pcib = device_get_parent(dev); 4230 struct pci_devinfo *dinfo; 4231 int maxslots; 4232 int s, f, pcifunchigh; 4233 uint8_t hdrtype; 4234 int first_func; 4235 4236 /* 4237 * Try to detect a device at slot 0, function 0. If it exists, try to 4238 * enable ARI. We must enable ARI before detecting the rest of the 4239 * functions on this bus as ARI changes the set of slots and functions 4240 * that are legal on this bus. 4241 */ 4242 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0); 4243 if (dinfo != NULL && pci_enable_ari) 4244 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev); 4245 4246 /* 4247 * Start looking for new devices on slot 0 at function 1 because we 4248 * just identified the device at slot 0, function 0. 4249 */ 4250 first_func = 1; 4251 4252 maxslots = PCIB_MAXSLOTS(pcib); 4253 for (s = 0; s <= maxslots; s++, first_func = 0) { 4254 pcifunchigh = 0; 4255 f = 0; 4256 DELAY(1); 4257 4258 /* If function 0 is not present, skip to the next slot. */ 4259 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4260 continue; 4261 hdrtype = REG(PCIR_HDRTYPE, 1); 4262 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4263 continue; 4264 if (hdrtype & PCIM_MFDEV) 4265 pcifunchigh = PCIB_MAXFUNCS(pcib); 4266 for (f = first_func; f <= pcifunchigh; f++) 4267 pci_identify_function(pcib, dev, domain, busno, s, f); 4268 } 4269 #undef REG 4270 } 4271 4272 int 4273 pci_rescan_method(device_t dev) 4274 { 4275 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 4276 device_t pcib = device_get_parent(dev); 4277 device_t child, *devlist, *unchanged; 4278 int devcount, error, i, j, maxslots, oldcount; 4279 int busno, domain, s, f, pcifunchigh; 4280 uint8_t hdrtype; 4281 4282 /* No need to check for ARI on a rescan. */ 4283 error = device_get_children(dev, &devlist, &devcount); 4284 if (error) 4285 return (error); 4286 if (devcount != 0) { 4287 unchanged = malloc(devcount * sizeof(device_t), M_TEMP, 4288 M_NOWAIT | M_ZERO); 4289 if (unchanged == NULL) { 4290 free(devlist, M_TEMP); 4291 return (ENOMEM); 4292 } 4293 } else 4294 unchanged = NULL; 4295 4296 domain = pcib_get_domain(dev); 4297 busno = pcib_get_bus(dev); 4298 maxslots = PCIB_MAXSLOTS(pcib); 4299 for (s = 0; s <= maxslots; s++) { 4300 /* If function 0 is not present, skip to the next slot. */ 4301 f = 0; 4302 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4303 continue; 4304 pcifunchigh = 0; 4305 hdrtype = REG(PCIR_HDRTYPE, 1); 4306 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 4307 continue; 4308 if (hdrtype & PCIM_MFDEV) 4309 pcifunchigh = PCIB_MAXFUNCS(pcib); 4310 for (f = 0; f <= pcifunchigh; f++) { 4311 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID) 4312 continue; 4313 4314 /* 4315 * Found a valid function. Check if a 4316 * device_t for this device already exists. 4317 */ 4318 for (i = 0; i < devcount; i++) { 4319 child = devlist[i]; 4320 if (child == NULL) 4321 continue; 4322 if (pci_get_slot(child) == s && 4323 pci_get_function(child) == f) { 4324 unchanged[i] = child; 4325 goto next_func; 4326 } 4327 } 4328 4329 pci_identify_function(pcib, dev, domain, busno, s, f); 4330 next_func:; 4331 } 4332 } 4333 4334 /* Remove devices that are no longer present. */ 4335 for (i = 0; i < devcount; i++) { 4336 if (unchanged[i] != NULL) 4337 continue; 4338 device_delete_child(dev, devlist[i]); 4339 } 4340 4341 free(devlist, M_TEMP); 4342 oldcount = devcount; 4343 4344 /* Try to attach the devices just added. */ 4345 error = device_get_children(dev, &devlist, &devcount); 4346 if (error) { 4347 free(unchanged, M_TEMP); 4348 return (error); 4349 } 4350 4351 for (i = 0; i < devcount; i++) { 4352 for (j = 0; j < oldcount; j++) { 4353 if (devlist[i] == unchanged[j]) 4354 goto next_device; 4355 } 4356 4357 device_probe_and_attach(devlist[i]); 4358 next_device:; 4359 } 4360 4361 free(unchanged, M_TEMP); 4362 free(devlist, M_TEMP); 4363 return (0); 4364 #undef REG 4365 } 4366 4367 #ifdef PCI_IOV 4368 device_t 4369 pci_add_iov_child(device_t bus, device_t pf, uint16_t rid, uint16_t vid, 4370 uint16_t did) 4371 { 4372 struct pci_devinfo *vf_dinfo; 4373 device_t pcib; 4374 int busno, slot, func; 4375 4376 pcib = device_get_parent(bus); 4377 4378 PCIB_DECODE_RID(pcib, rid, &busno, &slot, &func); 4379 4380 vf_dinfo = pci_fill_devinfo(pcib, bus, pci_get_domain(pcib), busno, 4381 slot, func, vid, did); 4382 4383 vf_dinfo->cfg.flags |= PCICFG_VF; 4384 pci_add_child(bus, vf_dinfo); 4385 4386 return (vf_dinfo->cfg.dev); 4387 } 4388 4389 device_t 4390 pci_create_iov_child_method(device_t bus, device_t pf, uint16_t rid, 4391 uint16_t vid, uint16_t did) 4392 { 4393 4394 return (pci_add_iov_child(bus, pf, rid, vid, did)); 4395 } 4396 #endif 4397 4398 /* 4399 * For PCIe device set Max_Payload_Size to match PCIe root's. 4400 */ 4401 static void 4402 pcie_setup_mps(device_t dev) 4403 { 4404 struct pci_devinfo *dinfo = device_get_ivars(dev); 4405 device_t root; 4406 uint16_t rmps, mmps, mps; 4407 4408 if (dinfo->cfg.pcie.pcie_location == 0) 4409 return; 4410 root = pci_find_pcie_root_port(dev); 4411 if (root == NULL) 4412 return; 4413 /* Check whether the MPS is already configured. */ 4414 rmps = pcie_read_config(root, PCIER_DEVICE_CTL, 2) & 4415 PCIEM_CTL_MAX_PAYLOAD; 4416 mps = pcie_read_config(dev, PCIER_DEVICE_CTL, 2) & 4417 PCIEM_CTL_MAX_PAYLOAD; 4418 if (mps == rmps) 4419 return; 4420 /* Check whether the device is capable of the root's MPS. */ 4421 mmps = (pcie_read_config(dev, PCIER_DEVICE_CAP, 2) & 4422 PCIEM_CAP_MAX_PAYLOAD) << 5; 4423 if (rmps > mmps) { 4424 /* 4425 * The device is unable to handle root's MPS. Limit root. 4426 * XXX: We should traverse through all the tree, applying 4427 * it to all the devices. 4428 */ 4429 pcie_adjust_config(root, PCIER_DEVICE_CTL, 4430 PCIEM_CTL_MAX_PAYLOAD, mmps, 2); 4431 } else { 4432 pcie_adjust_config(dev, PCIER_DEVICE_CTL, 4433 PCIEM_CTL_MAX_PAYLOAD, rmps, 2); 4434 } 4435 } 4436 4437 static void 4438 pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo) 4439 { 4440 int aer; 4441 uint32_t r; 4442 uint16_t r2; 4443 4444 if (dinfo->cfg.pcie.pcie_location != 0 && 4445 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) { 4446 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4447 PCIER_ROOT_CTL, 2); 4448 r2 &= ~(PCIEM_ROOT_CTL_SERR_CORR | 4449 PCIEM_ROOT_CTL_SERR_NONFATAL | PCIEM_ROOT_CTL_SERR_FATAL); 4450 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4451 PCIER_ROOT_CTL, r2, 2); 4452 } 4453 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 4454 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 4455 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 4456 if (r != 0 && bootverbose) { 4457 pci_printf(&dinfo->cfg, 4458 "clearing AER UC 0x%08x -> 0x%08x\n", 4459 r, pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4460 4)); 4461 } 4462 4463 r = pci_read_config(dev, aer + PCIR_AER_UC_MASK, 4); 4464 r &= ~(PCIM_AER_UC_TRAINING_ERROR | 4465 PCIM_AER_UC_DL_PROTOCOL_ERROR | 4466 PCIM_AER_UC_SURPRISE_LINK_DOWN | 4467 PCIM_AER_UC_POISONED_TLP | 4468 PCIM_AER_UC_FC_PROTOCOL_ERROR | 4469 PCIM_AER_UC_COMPLETION_TIMEOUT | 4470 PCIM_AER_UC_COMPLETER_ABORT | 4471 PCIM_AER_UC_UNEXPECTED_COMPLETION | 4472 PCIM_AER_UC_RECEIVER_OVERFLOW | 4473 PCIM_AER_UC_MALFORMED_TLP | 4474 PCIM_AER_UC_ECRC_ERROR | 4475 PCIM_AER_UC_UNSUPPORTED_REQUEST | 4476 PCIM_AER_UC_ACS_VIOLATION | 4477 PCIM_AER_UC_INTERNAL_ERROR | 4478 PCIM_AER_UC_MC_BLOCKED_TLP | 4479 PCIM_AER_UC_ATOMIC_EGRESS_BLK | 4480 PCIM_AER_UC_TLP_PREFIX_BLOCKED); 4481 pci_write_config(dev, aer + PCIR_AER_UC_MASK, r, 4); 4482 4483 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 4484 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 4485 if (r != 0 && bootverbose) { 4486 pci_printf(&dinfo->cfg, 4487 "clearing AER COR 0x%08x -> 0x%08x\n", 4488 r, pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4489 4)); 4490 } 4491 4492 r = pci_read_config(dev, aer + PCIR_AER_COR_MASK, 4); 4493 r &= ~(PCIM_AER_COR_RECEIVER_ERROR | 4494 PCIM_AER_COR_BAD_TLP | 4495 PCIM_AER_COR_BAD_DLLP | 4496 PCIM_AER_COR_REPLAY_ROLLOVER | 4497 PCIM_AER_COR_REPLAY_TIMEOUT | 4498 PCIM_AER_COR_ADVISORY_NF_ERROR | 4499 PCIM_AER_COR_INTERNAL_ERROR | 4500 PCIM_AER_COR_HEADER_LOG_OVFLOW); 4501 pci_write_config(dev, aer + PCIR_AER_COR_MASK, r, 4); 4502 4503 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 4504 PCIER_DEVICE_CTL, 2); 4505 r |= PCIEM_CTL_COR_ENABLE | PCIEM_CTL_NFER_ENABLE | 4506 PCIEM_CTL_FER_ENABLE | PCIEM_CTL_URR_ENABLE; 4507 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 4508 PCIER_DEVICE_CTL, r, 2); 4509 } 4510 } 4511 4512 void 4513 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 4514 { 4515 device_t dev; 4516 4517 dinfo->cfg.dev = dev = device_add_child(bus, NULL, DEVICE_UNIT_ANY); 4518 device_set_ivars(dev, dinfo); 4519 resource_list_init(&dinfo->resources); 4520 pci_cfg_save(dev, dinfo, 0); 4521 pci_cfg_restore(dev, dinfo); 4522 pci_clear_pme(dev); 4523 pci_print_verbose(dinfo); 4524 pci_add_resources(bus, dev, 0, 0); 4525 if (pci_enable_mps_tune) 4526 pcie_setup_mps(dev); 4527 pci_child_added(dinfo->cfg.dev); 4528 4529 if (pci_clear_aer_on_attach) 4530 pci_add_child_clear_aer(dev, dinfo); 4531 4532 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev); 4533 } 4534 4535 void 4536 pci_child_added_method(device_t dev, device_t child) 4537 { 4538 4539 } 4540 4541 static int 4542 pci_probe(device_t dev) 4543 { 4544 4545 device_set_desc(dev, "PCI bus"); 4546 4547 /* Allow other subclasses to override this driver. */ 4548 return (BUS_PROBE_GENERIC); 4549 } 4550 4551 int 4552 pci_attach_common(device_t dev) 4553 { 4554 struct pci_softc *sc; 4555 int busno, domain; 4556 int rid; 4557 4558 sc = device_get_softc(dev); 4559 domain = pcib_get_domain(dev); 4560 busno = pcib_get_bus(dev); 4561 rid = 0; 4562 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno, 4563 1, 0); 4564 if (sc->sc_bus == NULL) { 4565 device_printf(dev, "failed to allocate bus number\n"); 4566 return (ENXIO); 4567 } 4568 if (bootverbose) 4569 device_printf(dev, "domain=%d, physical bus=%d\n", 4570 domain, busno); 4571 sc->sc_dma_tag = bus_get_dma_tag(dev); 4572 return (0); 4573 } 4574 4575 int 4576 pci_attach(device_t dev) 4577 { 4578 int busno, domain, error; 4579 4580 error = pci_attach_common(dev); 4581 if (error) 4582 return (error); 4583 4584 /* 4585 * Since there can be multiple independently numbered PCI 4586 * buses on systems with multiple PCI domains, we can't use 4587 * the unit number to decide which bus we are probing. We ask 4588 * the parent pcib what our domain and bus numbers are. 4589 */ 4590 domain = pcib_get_domain(dev); 4591 busno = pcib_get_bus(dev); 4592 pci_add_children(dev, domain, busno); 4593 bus_attach_children(dev); 4594 return (0); 4595 } 4596 4597 int 4598 pci_detach(device_t dev) 4599 { 4600 struct pci_softc *sc; 4601 int error; 4602 4603 error = bus_generic_detach(dev); 4604 if (error) 4605 return (error); 4606 sc = device_get_softc(dev); 4607 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus); 4608 return (error); 4609 } 4610 4611 static void 4612 pci_hint_device_unit(device_t dev, device_t child, const char *name, int *unitp) 4613 { 4614 int line, unit; 4615 const char *at; 4616 char me1[24], me2[32]; 4617 uint8_t b, s, f; 4618 uint32_t d; 4619 device_location_cache_t *cache; 4620 4621 d = pci_get_domain(child); 4622 b = pci_get_bus(child); 4623 s = pci_get_slot(child); 4624 f = pci_get_function(child); 4625 snprintf(me1, sizeof(me1), "pci%u:%u:%u", b, s, f); 4626 snprintf(me2, sizeof(me2), "pci%u:%u:%u:%u", d, b, s, f); 4627 line = 0; 4628 cache = dev_wired_cache_init(); 4629 while (resource_find_dev(&line, name, &unit, "at", NULL) == 0) { 4630 resource_string_value(name, unit, "at", &at); 4631 if (strcmp(at, me1) == 0 || strcmp(at, me2) == 0) { 4632 *unitp = unit; 4633 break; 4634 } 4635 if (dev_wired_cache_match(cache, child, at)) { 4636 *unitp = unit; 4637 break; 4638 } 4639 } 4640 dev_wired_cache_fini(cache); 4641 } 4642 4643 static void 4644 pci_set_power_child(device_t dev, device_t child, int state) 4645 { 4646 device_t pcib; 4647 int dstate; 4648 4649 /* 4650 * Set the device to the given state. If the firmware suggests 4651 * a different power state, use it instead. If power management 4652 * is not present, the firmware is responsible for managing 4653 * device power. Skip children who aren't attached since they 4654 * are handled separately. 4655 */ 4656 pcib = device_get_parent(dev); 4657 dstate = state; 4658 if (device_is_attached(child) && 4659 PCIB_POWER_FOR_SLEEP(pcib, child, &dstate) == 0) 4660 pci_set_powerstate(child, dstate); 4661 } 4662 4663 int 4664 pci_suspend_child(device_t dev, device_t child) 4665 { 4666 struct pci_devinfo *dinfo; 4667 struct resource_list_entry *rle; 4668 int error; 4669 4670 dinfo = device_get_ivars(child); 4671 4672 /* 4673 * Save the PCI configuration space for the child and set the 4674 * device in the appropriate power state for this sleep state. 4675 */ 4676 pci_cfg_save(child, dinfo, 0); 4677 4678 /* Suspend devices before potentially powering them down. */ 4679 error = bus_generic_suspend_child(dev, child); 4680 4681 if (error) 4682 return (error); 4683 4684 if (pci_do_power_suspend) { 4685 /* 4686 * Make sure this device's interrupt handler is not invoked 4687 * in the case the device uses a shared interrupt that can 4688 * be raised by some other device. 4689 * This is applicable only to regular (legacy) PCI interrupts 4690 * as MSI/MSI-X interrupts are never shared. 4691 */ 4692 rle = resource_list_find(&dinfo->resources, 4693 SYS_RES_IRQ, 0); 4694 if (rle != NULL && rle->res != NULL) 4695 (void)bus_suspend_intr(child, rle->res); 4696 pci_set_power_child(dev, child, PCI_POWERSTATE_D3); 4697 } 4698 4699 return (0); 4700 } 4701 4702 int 4703 pci_resume_child(device_t dev, device_t child) 4704 { 4705 struct pci_devinfo *dinfo; 4706 struct resource_list_entry *rle; 4707 4708 if (pci_do_power_resume) 4709 pci_set_power_child(dev, child, PCI_POWERSTATE_D0); 4710 4711 dinfo = device_get_ivars(child); 4712 pci_cfg_restore(child, dinfo); 4713 pci_clear_pme(child); 4714 if (!device_is_attached(child)) 4715 pci_cfg_save(child, dinfo, 1); 4716 4717 bus_generic_resume_child(dev, child); 4718 4719 /* 4720 * Allow interrupts only after fully resuming the driver and hardware. 4721 */ 4722 if (pci_do_power_suspend) { 4723 /* See pci_suspend_child for details. */ 4724 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0); 4725 if (rle != NULL && rle->res != NULL) 4726 (void)bus_resume_intr(child, rle->res); 4727 } 4728 4729 return (0); 4730 } 4731 4732 int 4733 pci_resume(device_t dev) 4734 { 4735 device_t child, *devlist; 4736 int error, i, numdevs; 4737 4738 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0) 4739 return (error); 4740 4741 /* 4742 * Resume critical devices first, then everything else later. 4743 */ 4744 for (i = 0; i < numdevs; i++) { 4745 child = devlist[i]; 4746 switch (pci_get_class(child)) { 4747 case PCIC_DISPLAY: 4748 case PCIC_MEMORY: 4749 case PCIC_BRIDGE: 4750 case PCIC_BASEPERIPH: 4751 BUS_RESUME_CHILD(dev, child); 4752 break; 4753 } 4754 } 4755 for (i = 0; i < numdevs; i++) { 4756 child = devlist[i]; 4757 switch (pci_get_class(child)) { 4758 case PCIC_DISPLAY: 4759 case PCIC_MEMORY: 4760 case PCIC_BRIDGE: 4761 case PCIC_BASEPERIPH: 4762 break; 4763 default: 4764 BUS_RESUME_CHILD(dev, child); 4765 } 4766 } 4767 free(devlist, M_TEMP); 4768 return (0); 4769 } 4770 4771 static void 4772 pci_load_vendor_data(void) 4773 { 4774 caddr_t data; 4775 void *ptr; 4776 size_t sz; 4777 4778 data = preload_search_by_type("pci_vendor_data"); 4779 if (data != NULL) { 4780 ptr = preload_fetch_addr(data); 4781 sz = preload_fetch_size(data); 4782 if (ptr != NULL && sz != 0) { 4783 pci_vendordata = ptr; 4784 pci_vendordata_size = sz; 4785 /* terminate the database */ 4786 pci_vendordata[pci_vendordata_size] = '\n'; 4787 } 4788 } 4789 } 4790 4791 void 4792 pci_driver_added(device_t dev, driver_t *driver) 4793 { 4794 int numdevs; 4795 device_t *devlist; 4796 device_t child; 4797 struct pci_devinfo *dinfo; 4798 int i; 4799 4800 if (bootverbose) 4801 device_printf(dev, "driver added\n"); 4802 DEVICE_IDENTIFY(driver, dev); 4803 if (device_get_children(dev, &devlist, &numdevs) != 0) 4804 return; 4805 for (i = 0; i < numdevs; i++) { 4806 child = devlist[i]; 4807 if (device_get_state(child) != DS_NOTPRESENT) 4808 continue; 4809 dinfo = device_get_ivars(child); 4810 pci_print_verbose(dinfo); 4811 if (bootverbose) 4812 pci_printf(&dinfo->cfg, "reprobing on driver added\n"); 4813 pci_cfg_restore(child, dinfo); 4814 if (device_probe_and_attach(child) != 0) 4815 pci_child_detached(dev, child); 4816 } 4817 free(devlist, M_TEMP); 4818 } 4819 4820 int 4821 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, 4822 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep) 4823 { 4824 struct pci_devinfo *dinfo; 4825 struct msix_table_entry *mte; 4826 struct msix_vector *mv; 4827 uint64_t addr; 4828 uint32_t data; 4829 void *cookie; 4830 int error, rid; 4831 4832 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr, 4833 arg, &cookie); 4834 if (error) 4835 return (error); 4836 4837 /* If this is not a direct child, just bail out. */ 4838 if (device_get_parent(child) != dev) { 4839 *cookiep = cookie; 4840 return(0); 4841 } 4842 4843 rid = rman_get_rid(irq); 4844 if (rid == 0) { 4845 /* Make sure that INTx is enabled */ 4846 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4847 } else { 4848 /* 4849 * Check to see if the interrupt is MSI or MSI-X. 4850 * Ask our parent to map the MSI and give 4851 * us the address and data register values. 4852 * If we fail for some reason, teardown the 4853 * interrupt handler. 4854 */ 4855 dinfo = device_get_ivars(child); 4856 if (dinfo->cfg.msi.msi_alloc > 0) { 4857 if (dinfo->cfg.msi.msi_addr == 0) { 4858 KASSERT(dinfo->cfg.msi.msi_handlers == 0, 4859 ("MSI has handlers, but vectors not mapped")); 4860 error = PCIB_MAP_MSI(device_get_parent(dev), 4861 child, rman_get_start(irq), &addr, &data); 4862 if (error) 4863 goto bad; 4864 dinfo->cfg.msi.msi_addr = addr; 4865 dinfo->cfg.msi.msi_data = data; 4866 } 4867 if (dinfo->cfg.msi.msi_handlers == 0) 4868 pci_enable_msi(child, dinfo->cfg.msi.msi_addr, 4869 dinfo->cfg.msi.msi_data); 4870 dinfo->cfg.msi.msi_handlers++; 4871 } else { 4872 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4873 ("No MSI or MSI-X interrupts allocated")); 4874 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4875 ("MSI-X index too high")); 4876 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4877 KASSERT(mte->mte_vector != 0, ("no message vector")); 4878 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1]; 4879 KASSERT(mv->mv_irq == rman_get_start(irq), 4880 ("IRQ mismatch")); 4881 if (mv->mv_address == 0) { 4882 KASSERT(mte->mte_handlers == 0, 4883 ("MSI-X table entry has handlers, but vector not mapped")); 4884 error = PCIB_MAP_MSI(device_get_parent(dev), 4885 child, rman_get_start(irq), &addr, &data); 4886 if (error) 4887 goto bad; 4888 mv->mv_address = addr; 4889 mv->mv_data = data; 4890 } 4891 4892 /* 4893 * The MSIX table entry must be made valid by 4894 * incrementing the mte_handlers before 4895 * calling pci_enable_msix() and 4896 * pci_resume_msix(). Else the MSIX rewrite 4897 * table quirk will not work as expected. 4898 */ 4899 mte->mte_handlers++; 4900 if (mte->mte_handlers == 1) { 4901 pci_enable_msix(child, rid - 1, mv->mv_address, 4902 mv->mv_data); 4903 pci_unmask_msix(child, rid - 1); 4904 } 4905 } 4906 4907 /* 4908 * Make sure that INTx is disabled if we are using MSI/MSI-X, 4909 * unless the device is affected by PCI_QUIRK_MSI_INTX_BUG, 4910 * in which case we "enable" INTx so MSI/MSI-X actually works. 4911 */ 4912 if (!pci_has_quirk(pci_get_devid(child), 4913 PCI_QUIRK_MSI_INTX_BUG)) 4914 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4915 else 4916 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS); 4917 bad: 4918 if (error) { 4919 (void)bus_generic_teardown_intr(dev, child, irq, 4920 cookie); 4921 return (error); 4922 } 4923 } 4924 *cookiep = cookie; 4925 return (0); 4926 } 4927 4928 int 4929 pci_teardown_intr(device_t dev, device_t child, struct resource *irq, 4930 void *cookie) 4931 { 4932 struct msix_table_entry *mte; 4933 struct resource_list_entry *rle; 4934 struct pci_devinfo *dinfo; 4935 int error, rid; 4936 4937 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE)) 4938 return (EINVAL); 4939 4940 /* If this isn't a direct child, just bail out */ 4941 if (device_get_parent(child) != dev) 4942 return(bus_generic_teardown_intr(dev, child, irq, cookie)); 4943 4944 rid = rman_get_rid(irq); 4945 if (rid == 0) { 4946 /* Mask INTx */ 4947 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); 4948 } else { 4949 /* 4950 * Check to see if the interrupt is MSI or MSI-X. If so, 4951 * decrement the appropriate handlers count and mask the 4952 * MSI-X message, or disable MSI messages if the count 4953 * drops to 0. 4954 */ 4955 dinfo = device_get_ivars(child); 4956 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid); 4957 if (rle->res != irq) 4958 return (EINVAL); 4959 if (dinfo->cfg.msi.msi_alloc > 0) { 4960 KASSERT(rid <= dinfo->cfg.msi.msi_alloc, 4961 ("MSI-X index too high")); 4962 if (dinfo->cfg.msi.msi_handlers == 0) 4963 return (EINVAL); 4964 dinfo->cfg.msi.msi_handlers--; 4965 if (dinfo->cfg.msi.msi_handlers == 0) 4966 pci_disable_msi(child); 4967 } else { 4968 KASSERT(dinfo->cfg.msix.msix_alloc > 0, 4969 ("No MSI or MSI-X interrupts allocated")); 4970 KASSERT(rid <= dinfo->cfg.msix.msix_table_len, 4971 ("MSI-X index too high")); 4972 mte = &dinfo->cfg.msix.msix_table[rid - 1]; 4973 if (mte->mte_handlers == 0) 4974 return (EINVAL); 4975 mte->mte_handlers--; 4976 if (mte->mte_handlers == 0) 4977 pci_mask_msix(child, rid - 1); 4978 } 4979 } 4980 error = bus_generic_teardown_intr(dev, child, irq, cookie); 4981 if (rid > 0) 4982 KASSERT(error == 0, 4983 ("%s: generic teardown failed for MSI/MSI-X", __func__)); 4984 return (error); 4985 } 4986 4987 int 4988 pci_print_child(device_t dev, device_t child) 4989 { 4990 struct pci_devinfo *dinfo; 4991 struct resource_list *rl; 4992 int retval = 0; 4993 4994 dinfo = device_get_ivars(child); 4995 rl = &dinfo->resources; 4996 4997 retval += bus_print_child_header(dev, child); 4998 4999 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#jx"); 5000 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 5001 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 5002 if (device_get_flags(dev)) 5003 retval += printf(" flags %#x", device_get_flags(dev)); 5004 5005 retval += printf(" at device %d.%d", pci_get_slot(child), 5006 pci_get_function(child)); 5007 5008 retval += bus_print_child_domain(dev, child); 5009 retval += bus_print_child_footer(dev, child); 5010 5011 return (retval); 5012 } 5013 5014 static const struct 5015 { 5016 int class; 5017 int subclass; 5018 int report; /* 0 = bootverbose, 1 = always */ 5019 const char *desc; 5020 } pci_nomatch_tab[] = { 5021 {PCIC_OLD, -1, 1, "old"}, 5022 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"}, 5023 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"}, 5024 {PCIC_STORAGE, -1, 1, "mass storage"}, 5025 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"}, 5026 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"}, 5027 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"}, 5028 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"}, 5029 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"}, 5030 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"}, 5031 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"}, 5032 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"}, 5033 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"}, 5034 {PCIC_NETWORK, -1, 1, "network"}, 5035 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"}, 5036 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"}, 5037 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"}, 5038 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"}, 5039 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"}, 5040 {PCIC_DISPLAY, -1, 1, "display"}, 5041 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"}, 5042 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"}, 5043 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"}, 5044 {PCIC_MULTIMEDIA, -1, 1, "multimedia"}, 5045 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"}, 5046 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"}, 5047 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"}, 5048 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"}, 5049 {PCIC_MEMORY, -1, 1, "memory"}, 5050 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"}, 5051 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"}, 5052 {PCIC_BRIDGE, -1, 1, "bridge"}, 5053 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"}, 5054 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"}, 5055 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"}, 5056 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"}, 5057 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"}, 5058 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"}, 5059 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"}, 5060 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"}, 5061 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"}, 5062 {PCIC_SIMPLECOMM, -1, 1, "simple comms"}, 5063 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */ 5064 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"}, 5065 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"}, 5066 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"}, 5067 {PCIC_BASEPERIPH, -1, 0, "base peripheral"}, 5068 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"}, 5069 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"}, 5070 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"}, 5071 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"}, 5072 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"}, 5073 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"}, 5074 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"}, 5075 {PCIC_INPUTDEV, -1, 1, "input device"}, 5076 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"}, 5077 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"}, 5078 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"}, 5079 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"}, 5080 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"}, 5081 {PCIC_DOCKING, -1, 1, "docking station"}, 5082 {PCIC_PROCESSOR, -1, 1, "processor"}, 5083 {PCIC_SERIALBUS, -1, 1, "serial bus"}, 5084 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"}, 5085 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"}, 5086 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"}, 5087 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"}, 5088 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"}, 5089 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"}, 5090 {PCIC_WIRELESS, -1, 1, "wireless controller"}, 5091 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"}, 5092 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"}, 5093 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"}, 5094 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"}, 5095 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"}, 5096 {PCIC_SATCOM, -1, 1, "satellite communication"}, 5097 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"}, 5098 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"}, 5099 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"}, 5100 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"}, 5101 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"}, 5102 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"}, 5103 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"}, 5104 {PCIC_DASP, -1, 0, "dasp"}, 5105 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"}, 5106 {PCIC_DASP, PCIS_DASP_PERFCNTRS, 1, "performance counters"}, 5107 {PCIC_DASP, PCIS_DASP_COMM_SYNC, 1, "communication synchronizer"}, 5108 {PCIC_DASP, PCIS_DASP_MGMT_CARD, 1, "signal processing management"}, 5109 {PCIC_INSTRUMENT, -1, 0, "non-essential instrumentation"}, 5110 {0, 0, 0, NULL} 5111 }; 5112 5113 void 5114 pci_probe_nomatch(device_t dev, device_t child) 5115 { 5116 int i, report; 5117 const char *cp, *scp; 5118 char *device; 5119 5120 /* 5121 * Look for a listing for this device in a loaded device database. 5122 */ 5123 report = 1; 5124 if ((device = pci_describe_device(child)) != NULL) { 5125 device_printf(dev, "<%s>", device); 5126 free(device, M_DEVBUF); 5127 } else { 5128 /* 5129 * Scan the class/subclass descriptions for a general 5130 * description. 5131 */ 5132 cp = "unknown"; 5133 scp = NULL; 5134 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 5135 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 5136 if (pci_nomatch_tab[i].subclass == -1) { 5137 cp = pci_nomatch_tab[i].desc; 5138 report = pci_nomatch_tab[i].report; 5139 } else if (pci_nomatch_tab[i].subclass == 5140 pci_get_subclass(child)) { 5141 scp = pci_nomatch_tab[i].desc; 5142 report = pci_nomatch_tab[i].report; 5143 } 5144 } 5145 } 5146 if (report || bootverbose) { 5147 device_printf(dev, "<%s%s%s>", 5148 cp ? cp : "", 5149 ((cp != NULL) && (scp != NULL)) ? ", " : "", 5150 scp ? scp : ""); 5151 } 5152 } 5153 if (report || bootverbose) { 5154 printf(" at device %d.%d (no driver attached)\n", 5155 pci_get_slot(child), pci_get_function(child)); 5156 } 5157 pci_cfg_save(child, device_get_ivars(child), 1); 5158 } 5159 5160 void 5161 pci_child_detached(device_t dev, device_t child) 5162 { 5163 struct pci_devinfo *dinfo; 5164 struct resource_list *rl; 5165 5166 dinfo = device_get_ivars(child); 5167 rl = &dinfo->resources; 5168 5169 /* 5170 * Have to deallocate IRQs before releasing any MSI messages and 5171 * have to release MSI messages before deallocating any memory 5172 * BARs. 5173 */ 5174 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0) 5175 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n"); 5176 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) { 5177 if (dinfo->cfg.msi.msi_alloc != 0) 5178 pci_printf(&dinfo->cfg, "Device leaked %d MSI " 5179 "vectors\n", dinfo->cfg.msi.msi_alloc); 5180 else 5181 pci_printf(&dinfo->cfg, "Device leaked %d MSI-X " 5182 "vectors\n", dinfo->cfg.msix.msix_alloc); 5183 (void)pci_release_msi(child); 5184 } 5185 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0) 5186 pci_printf(&dinfo->cfg, "Device leaked memory resources\n"); 5187 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0) 5188 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n"); 5189 if (resource_list_release_active(rl, dev, child, PCI_RES_BUS) != 0) 5190 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n"); 5191 5192 pci_cfg_save(child, dinfo, 1); 5193 } 5194 5195 /* 5196 * Parse the PCI device database, if loaded, and return a pointer to a 5197 * description of the device. 5198 * 5199 * The database is flat text formatted as follows: 5200 * 5201 * Any line not in a valid format is ignored. 5202 * Lines are terminated with newline '\n' characters. 5203 * 5204 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 5205 * the vendor name. 5206 * 5207 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 5208 * - devices cannot be listed without a corresponding VENDOR line. 5209 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 5210 * another TAB, then the device name. 5211 */ 5212 5213 /* 5214 * Assuming (ptr) points to the beginning of a line in the database, 5215 * return the vendor or device and description of the next entry. 5216 * The value of (vendor) or (device) inappropriate for the entry type 5217 * is set to -1. Returns nonzero at the end of the database. 5218 * 5219 * Note that this is slightly unrobust in the face of corrupt data; 5220 * we attempt to safeguard against this by spamming the end of the 5221 * database with a newline when we initialise. 5222 */ 5223 static int 5224 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 5225 { 5226 char *cp = *ptr; 5227 int left; 5228 5229 *device = -1; 5230 *vendor = -1; 5231 **desc = '\0'; 5232 for (;;) { 5233 left = pci_vendordata_size - (cp - pci_vendordata); 5234 if (left <= 0) { 5235 *ptr = cp; 5236 return(1); 5237 } 5238 5239 /* vendor entry? */ 5240 if (*cp != '\t' && 5241 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 5242 break; 5243 /* device entry? */ 5244 if (*cp == '\t' && 5245 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 5246 break; 5247 5248 /* skip to next line */ 5249 while (*cp != '\n' && left > 0) { 5250 cp++; 5251 left--; 5252 } 5253 if (*cp == '\n') { 5254 cp++; 5255 left--; 5256 } 5257 } 5258 /* skip to next line */ 5259 while (*cp != '\n' && left > 0) { 5260 cp++; 5261 left--; 5262 } 5263 if (*cp == '\n' && left > 0) 5264 cp++; 5265 *ptr = cp; 5266 return(0); 5267 } 5268 5269 static char * 5270 pci_describe_device(device_t dev) 5271 { 5272 int vendor, device; 5273 char *desc, *vp, *dp, *line; 5274 5275 desc = vp = dp = NULL; 5276 5277 /* 5278 * If we have no vendor data, we can't do anything. 5279 */ 5280 if (pci_vendordata == NULL) 5281 goto out; 5282 5283 /* 5284 * Scan the vendor data looking for this device 5285 */ 5286 line = pci_vendordata; 5287 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5288 goto out; 5289 for (;;) { 5290 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 5291 goto out; 5292 if (vendor == pci_get_vendor(dev)) 5293 break; 5294 } 5295 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 5296 goto out; 5297 for (;;) { 5298 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 5299 *dp = 0; 5300 break; 5301 } 5302 if (vendor != -1) { 5303 *dp = 0; 5304 break; 5305 } 5306 if (device == pci_get_device(dev)) 5307 break; 5308 } 5309 if (dp[0] == '\0') 5310 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 5311 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 5312 NULL) 5313 sprintf(desc, "%s, %s", vp, dp); 5314 out: 5315 if (vp != NULL) 5316 free(vp, M_DEVBUF); 5317 if (dp != NULL) 5318 free(dp, M_DEVBUF); 5319 return(desc); 5320 } 5321 5322 int 5323 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 5324 { 5325 struct pci_devinfo *dinfo; 5326 pcicfgregs *cfg; 5327 5328 dinfo = device_get_ivars(child); 5329 cfg = &dinfo->cfg; 5330 5331 switch (which) { 5332 case PCI_IVAR_ETHADDR: 5333 /* 5334 * The generic accessor doesn't deal with failure, so 5335 * we set the return value, then return an error. 5336 */ 5337 *((uint8_t **) result) = NULL; 5338 return (EINVAL); 5339 case PCI_IVAR_SUBVENDOR: 5340 *result = cfg->subvendor; 5341 break; 5342 case PCI_IVAR_SUBDEVICE: 5343 *result = cfg->subdevice; 5344 break; 5345 case PCI_IVAR_VENDOR: 5346 *result = cfg->vendor; 5347 break; 5348 case PCI_IVAR_DEVICE: 5349 *result = cfg->device; 5350 break; 5351 case PCI_IVAR_DEVID: 5352 *result = (cfg->device << 16) | cfg->vendor; 5353 break; 5354 case PCI_IVAR_CLASS: 5355 *result = cfg->baseclass; 5356 break; 5357 case PCI_IVAR_SUBCLASS: 5358 *result = cfg->subclass; 5359 break; 5360 case PCI_IVAR_PROGIF: 5361 *result = cfg->progif; 5362 break; 5363 case PCI_IVAR_REVID: 5364 *result = cfg->revid; 5365 break; 5366 case PCI_IVAR_INTPIN: 5367 *result = cfg->intpin; 5368 break; 5369 case PCI_IVAR_IRQ: 5370 *result = cfg->intline; 5371 break; 5372 case PCI_IVAR_DOMAIN: 5373 *result = cfg->domain; 5374 break; 5375 case PCI_IVAR_BUS: 5376 *result = cfg->bus; 5377 break; 5378 case PCI_IVAR_SLOT: 5379 *result = cfg->slot; 5380 break; 5381 case PCI_IVAR_FUNCTION: 5382 *result = cfg->func; 5383 break; 5384 case PCI_IVAR_CMDREG: 5385 *result = cfg->cmdreg; 5386 break; 5387 case PCI_IVAR_CACHELNSZ: 5388 *result = cfg->cachelnsz; 5389 break; 5390 case PCI_IVAR_MINGNT: 5391 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5392 *result = -1; 5393 return (EINVAL); 5394 } 5395 *result = cfg->mingnt; 5396 break; 5397 case PCI_IVAR_MAXLAT: 5398 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) { 5399 *result = -1; 5400 return (EINVAL); 5401 } 5402 *result = cfg->maxlat; 5403 break; 5404 case PCI_IVAR_LATTIMER: 5405 *result = cfg->lattimer; 5406 break; 5407 default: 5408 return (ENOENT); 5409 } 5410 return (0); 5411 } 5412 5413 int 5414 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 5415 { 5416 struct pci_devinfo *dinfo; 5417 5418 dinfo = device_get_ivars(child); 5419 5420 switch (which) { 5421 case PCI_IVAR_INTPIN: 5422 dinfo->cfg.intpin = value; 5423 return (0); 5424 case PCI_IVAR_ETHADDR: 5425 case PCI_IVAR_SUBVENDOR: 5426 case PCI_IVAR_SUBDEVICE: 5427 case PCI_IVAR_VENDOR: 5428 case PCI_IVAR_DEVICE: 5429 case PCI_IVAR_DEVID: 5430 case PCI_IVAR_CLASS: 5431 case PCI_IVAR_SUBCLASS: 5432 case PCI_IVAR_PROGIF: 5433 case PCI_IVAR_REVID: 5434 case PCI_IVAR_IRQ: 5435 case PCI_IVAR_DOMAIN: 5436 case PCI_IVAR_BUS: 5437 case PCI_IVAR_SLOT: 5438 case PCI_IVAR_FUNCTION: 5439 return (EINVAL); /* disallow for now */ 5440 5441 default: 5442 return (ENOENT); 5443 } 5444 } 5445 5446 #include "opt_ddb.h" 5447 #ifdef DDB 5448 #include <ddb/ddb.h> 5449 #include <sys/cons.h> 5450 5451 /* 5452 * List resources based on pci map registers, used for within ddb 5453 */ 5454 5455 DB_SHOW_COMMAND_FLAGS(pciregs, db_pci_dump, DB_CMD_MEMSAFE) 5456 { 5457 struct pci_devinfo *dinfo; 5458 struct devlist *devlist_head; 5459 struct pci_conf *p; 5460 const char *name; 5461 int i, error, none_count; 5462 5463 none_count = 0; 5464 /* get the head of the device queue */ 5465 devlist_head = &pci_devq; 5466 5467 /* 5468 * Go through the list of devices and print out devices 5469 */ 5470 for (error = 0, i = 0, 5471 dinfo = STAILQ_FIRST(devlist_head); 5472 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 5473 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 5474 /* Populate pd_name and pd_unit */ 5475 name = NULL; 5476 if (dinfo->cfg.dev) 5477 name = device_get_name(dinfo->cfg.dev); 5478 5479 p = &dinfo->conf; 5480 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x " 5481 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 5482 (name && *name) ? name : "none", 5483 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 5484 none_count++, 5485 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev, 5486 p->pc_sel.pc_func, (p->pc_class << 16) | 5487 (p->pc_subclass << 8) | p->pc_progif, 5488 (p->pc_subdevice << 16) | p->pc_subvendor, 5489 (p->pc_device << 16) | p->pc_vendor, 5490 p->pc_revid, p->pc_hdr); 5491 } 5492 } 5493 #endif /* DDB */ 5494 5495 struct resource * 5496 pci_reserve_map(device_t dev, device_t child, int type, int *rid, 5497 rman_res_t start, rman_res_t end, rman_res_t count, u_int num, 5498 u_int flags) 5499 { 5500 struct pci_devinfo *dinfo = device_get_ivars(child); 5501 struct resource_list *rl = &dinfo->resources; 5502 struct resource *res; 5503 struct pci_map *pm; 5504 uint16_t cmd; 5505 pci_addr_t map, testval; 5506 int mapsize; 5507 5508 res = NULL; 5509 5510 /* If rid is managed by EA, ignore it */ 5511 if (pci_ea_is_enabled(child, *rid)) 5512 goto out; 5513 5514 pm = pci_find_bar(child, *rid); 5515 if (pm != NULL) { 5516 /* This is a BAR that we failed to allocate earlier. */ 5517 mapsize = pm->pm_size; 5518 map = pm->pm_value; 5519 } else { 5520 /* 5521 * Weed out the bogons, and figure out how large the 5522 * BAR/map is. BARs that read back 0 here are bogus 5523 * and unimplemented. Note: atapci in legacy mode are 5524 * special and handled elsewhere in the code. If you 5525 * have a atapci device in legacy mode and it fails 5526 * here, that other code is broken. 5527 */ 5528 pci_read_bar(child, *rid, &map, &testval, NULL); 5529 5530 /* 5531 * Determine the size of the BAR and ignore BARs with a size 5532 * of 0. Device ROM BARs use a different mask value. 5533 */ 5534 if (PCIR_IS_BIOS(&dinfo->cfg, *rid)) 5535 mapsize = pci_romsize(testval); 5536 else 5537 mapsize = pci_mapsize(testval); 5538 if (mapsize == 0) 5539 goto out; 5540 pm = pci_add_bar(child, *rid, map, mapsize); 5541 } 5542 5543 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) { 5544 if (type != SYS_RES_MEMORY) { 5545 if (bootverbose) 5546 device_printf(dev, 5547 "child %s requested type %d for rid %#x," 5548 " but the BAR says it is an memio\n", 5549 device_get_nameunit(child), type, *rid); 5550 goto out; 5551 } 5552 } else { 5553 if (type != SYS_RES_IOPORT) { 5554 if (bootverbose) 5555 device_printf(dev, 5556 "child %s requested type %d for rid %#x," 5557 " but the BAR says it is an ioport\n", 5558 device_get_nameunit(child), type, *rid); 5559 goto out; 5560 } 5561 } 5562 5563 /* 5564 * For real BARs, we need to override the size that 5565 * the driver requests, because that's what the BAR 5566 * actually uses and we would otherwise have a 5567 * situation where we might allocate the excess to 5568 * another driver, which won't work. 5569 */ 5570 count = ((pci_addr_t)1 << mapsize) * num; 5571 if (RF_ALIGNMENT(flags) < mapsize) 5572 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 5573 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH)) 5574 flags |= RF_PREFETCHABLE; 5575 5576 /* 5577 * Allocate enough resource, and then write back the 5578 * appropriate BAR for that resource. 5579 */ 5580 resource_list_add(rl, type, *rid, start, end, count); 5581 res = resource_list_reserve(rl, dev, child, type, rid, start, end, 5582 count, flags & ~RF_ACTIVE); 5583 if (res == NULL) { 5584 resource_list_delete(rl, type, *rid); 5585 device_printf(child, 5586 "%#jx bytes of rid %#x res %d failed (%#jx, %#jx).\n", 5587 count, *rid, type, start, end); 5588 goto out; 5589 } 5590 if (bootverbose) 5591 device_printf(child, 5592 "Lazy allocation of %#jx bytes rid %#x type %d at %#jx\n", 5593 count, *rid, type, rman_get_start(res)); 5594 5595 /* Disable decoding via the CMD register before updating the BAR */ 5596 cmd = pci_read_config(child, PCIR_COMMAND, 2); 5597 pci_write_config(child, PCIR_COMMAND, 5598 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2); 5599 5600 map = rman_get_start(res); 5601 pci_write_bar(child, pm, map); 5602 5603 /* Restore the original value of the CMD register */ 5604 pci_write_config(child, PCIR_COMMAND, cmd, 2); 5605 out: 5606 return (res); 5607 } 5608 5609 struct resource * 5610 pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid, 5611 rman_res_t start, rman_res_t end, rman_res_t count, u_long num, 5612 u_int flags) 5613 { 5614 struct pci_devinfo *dinfo; 5615 struct resource_list *rl; 5616 struct resource_list_entry *rle; 5617 struct resource *res; 5618 pcicfgregs *cfg; 5619 5620 /* 5621 * Perform lazy resource allocation 5622 */ 5623 dinfo = device_get_ivars(child); 5624 rl = &dinfo->resources; 5625 cfg = &dinfo->cfg; 5626 switch (type) { 5627 case PCI_RES_BUS: 5628 return (pci_alloc_secbus(dev, child, rid, start, end, count, 5629 flags)); 5630 case SYS_RES_IRQ: 5631 /* 5632 * Can't alloc legacy interrupt once MSI messages have 5633 * been allocated. 5634 */ 5635 if (*rid == 0 && (cfg->msi.msi_alloc > 0 || 5636 cfg->msix.msix_alloc > 0)) 5637 return (NULL); 5638 5639 /* 5640 * If the child device doesn't have an interrupt 5641 * routed and is deserving of an interrupt, try to 5642 * assign it one. 5643 */ 5644 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) && 5645 (cfg->intpin != 0)) 5646 pci_assign_interrupt(dev, child, 0); 5647 break; 5648 case SYS_RES_IOPORT: 5649 case SYS_RES_MEMORY: 5650 /* 5651 * PCI-PCI bridge I/O window resources are not BARs. 5652 * For those allocations just pass the request up the 5653 * tree. 5654 */ 5655 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) { 5656 switch (*rid) { 5657 case PCIR_IOBASEL_1: 5658 case PCIR_MEMBASE_1: 5659 case PCIR_PMBASEL_1: 5660 /* 5661 * XXX: Should we bother creating a resource 5662 * list entry? 5663 */ 5664 return (bus_generic_alloc_resource(dev, child, 5665 type, rid, start, end, count, flags)); 5666 } 5667 } 5668 /* Reserve resources for this BAR if needed. */ 5669 rle = resource_list_find(rl, type, *rid); 5670 if (rle == NULL) { 5671 res = pci_reserve_map(dev, child, type, rid, start, end, 5672 count, num, flags); 5673 if (res == NULL) 5674 return (NULL); 5675 } 5676 } 5677 return (resource_list_alloc(rl, dev, child, type, rid, 5678 start, end, count, flags)); 5679 } 5680 5681 struct resource * 5682 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 5683 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 5684 { 5685 #ifdef PCI_IOV 5686 struct pci_devinfo *dinfo; 5687 #endif 5688 5689 if (device_get_parent(child) != dev) 5690 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 5691 type, rid, start, end, count, flags)); 5692 5693 #ifdef PCI_IOV 5694 dinfo = device_get_ivars(child); 5695 if (dinfo->cfg.flags & PCICFG_VF) { 5696 switch (type) { 5697 /* VFs can't have I/O BARs. */ 5698 case SYS_RES_IOPORT: 5699 return (NULL); 5700 case SYS_RES_MEMORY: 5701 return (pci_vf_alloc_mem_resource(dev, child, rid, 5702 start, end, count, flags)); 5703 } 5704 5705 /* Fall through for other types of resource allocations. */ 5706 } 5707 #endif 5708 5709 return (pci_alloc_multi_resource(dev, child, type, rid, start, end, 5710 count, 1, flags)); 5711 } 5712 5713 int 5714 pci_release_resource(device_t dev, device_t child, struct resource *r) 5715 { 5716 struct pci_devinfo *dinfo; 5717 struct resource_list *rl; 5718 pcicfgregs *cfg __unused; 5719 5720 if (device_get_parent(child) != dev) 5721 return (bus_generic_release_resource(dev, child, r)); 5722 5723 dinfo = device_get_ivars(child); 5724 cfg = &dinfo->cfg; 5725 5726 #ifdef PCI_IOV 5727 if (cfg->flags & PCICFG_VF) { 5728 switch (rman_get_type(r)) { 5729 /* VFs can't have I/O BARs. */ 5730 case SYS_RES_IOPORT: 5731 return (EDOOFUS); 5732 case SYS_RES_MEMORY: 5733 return (pci_vf_release_mem_resource(dev, child, r)); 5734 } 5735 5736 /* Fall through for other types of resource allocations. */ 5737 } 5738 #endif 5739 5740 /* 5741 * PCI-PCI bridge I/O window resources are not BARs. For 5742 * those allocations just pass the request up the tree. 5743 */ 5744 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE && 5745 (rman_get_type(r) == SYS_RES_IOPORT || 5746 rman_get_type(r) == SYS_RES_MEMORY)) { 5747 switch (rman_get_rid(r)) { 5748 case PCIR_IOBASEL_1: 5749 case PCIR_MEMBASE_1: 5750 case PCIR_PMBASEL_1: 5751 return (bus_generic_release_resource(dev, child, r)); 5752 } 5753 } 5754 5755 rl = &dinfo->resources; 5756 return (resource_list_release(rl, dev, child, r)); 5757 } 5758 5759 int 5760 pci_activate_resource(device_t dev, device_t child, struct resource *r) 5761 { 5762 struct pci_devinfo *dinfo; 5763 int error, rid, type; 5764 5765 if (device_get_parent(child) != dev) 5766 return (bus_generic_activate_resource(dev, child, r)); 5767 5768 dinfo = device_get_ivars(child); 5769 #ifdef PCI_IOV 5770 if (dinfo->cfg.flags & PCICFG_VF) { 5771 switch (rman_get_type(r)) { 5772 /* VFs can't have I/O BARs. */ 5773 case SYS_RES_IOPORT: 5774 error = EINVAL; 5775 break; 5776 case SYS_RES_MEMORY: 5777 error = pci_vf_activate_mem_resource(dev, child, r); 5778 break; 5779 default: 5780 error = bus_generic_activate_resource(dev, child, r); 5781 break; 5782 } 5783 } else 5784 #endif 5785 error = bus_generic_activate_resource(dev, child, r); 5786 if (error) 5787 return (error); 5788 5789 rid = rman_get_rid(r); 5790 type = rman_get_type(r); 5791 5792 /* Device ROMs need their decoding explicitly enabled. */ 5793 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5794 pci_write_bar(child, pci_find_bar(child, rid), 5795 rman_get_start(r) | PCIM_BIOS_ENABLE); 5796 5797 /* Enable decoding in the command register when activating BARs. */ 5798 switch (type) { 5799 case SYS_RES_IOPORT: 5800 case SYS_RES_MEMORY: 5801 error = PCI_ENABLE_IO(dev, child, type); 5802 break; 5803 } 5804 return (error); 5805 } 5806 5807 int 5808 pci_deactivate_resource(device_t dev, device_t child, struct resource *r) 5809 { 5810 struct pci_devinfo *dinfo; 5811 int error, rid, type; 5812 5813 if (device_get_parent(child) != dev) 5814 return (bus_generic_deactivate_resource(dev, child, r)); 5815 5816 dinfo = device_get_ivars(child); 5817 #ifdef PCI_IOV 5818 if (dinfo->cfg.flags & PCICFG_VF) { 5819 switch (rman_get_type(r)) { 5820 /* VFs can't have I/O BARs. */ 5821 case SYS_RES_IOPORT: 5822 error = EINVAL; 5823 break; 5824 case SYS_RES_MEMORY: 5825 error = pci_vf_deactivate_mem_resource(dev, child, r); 5826 break; 5827 default: 5828 error = bus_generic_deactivate_resource(dev, child, r); 5829 break; 5830 } 5831 } else 5832 #endif 5833 error = bus_generic_deactivate_resource(dev, child, r); 5834 if (error) 5835 return (error); 5836 5837 /* Disable decoding for device ROMs. */ 5838 rid = rman_get_rid(r); 5839 type = rman_get_type(r); 5840 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid)) 5841 pci_write_bar(child, pci_find_bar(child, rid), 5842 rman_get_start(r)); 5843 return (0); 5844 } 5845 5846 int 5847 pci_adjust_resource(device_t dev, device_t child, struct resource *r, 5848 rman_res_t start, rman_res_t end) 5849 { 5850 #ifdef PCI_IOV 5851 struct pci_devinfo *dinfo; 5852 5853 if (device_get_parent(child) != dev) 5854 return (bus_generic_adjust_resource(dev, child, r, start, 5855 end)); 5856 5857 dinfo = device_get_ivars(child); 5858 if (dinfo->cfg.flags & PCICFG_VF) { 5859 switch (rman_get_type(r)) { 5860 /* VFs can't have I/O BARs. */ 5861 case SYS_RES_IOPORT: 5862 return (EINVAL); 5863 case SYS_RES_MEMORY: 5864 return (pci_vf_adjust_mem_resource(dev, child, r, 5865 start, end)); 5866 } 5867 5868 /* Fall through for other types of resource allocations. */ 5869 } 5870 #endif 5871 5872 return (bus_generic_adjust_resource(dev, child, r, start, end)); 5873 } 5874 5875 int 5876 pci_map_resource(device_t dev, device_t child, struct resource *r, 5877 struct resource_map_request *argsp, struct resource_map *map) 5878 { 5879 #ifdef PCI_IOV 5880 struct pci_devinfo *dinfo; 5881 5882 if (device_get_parent(child) != dev) 5883 return (bus_generic_map_resource(dev, child, r, argsp, 5884 map)); 5885 5886 dinfo = device_get_ivars(child); 5887 if (dinfo->cfg.flags & PCICFG_VF) { 5888 switch (rman_get_type(r)) { 5889 /* VFs can't have I/O BARs. */ 5890 case SYS_RES_IOPORT: 5891 return (EINVAL); 5892 case SYS_RES_MEMORY: 5893 return (pci_vf_map_mem_resource(dev, child, r, argsp, 5894 map)); 5895 } 5896 5897 /* Fall through for other types of resource allocations. */ 5898 } 5899 #endif 5900 5901 return (bus_generic_map_resource(dev, child, r, argsp, map)); 5902 } 5903 5904 int 5905 pci_unmap_resource(device_t dev, device_t child, struct resource *r, 5906 struct resource_map *map) 5907 { 5908 #ifdef PCI_IOV 5909 struct pci_devinfo *dinfo; 5910 5911 if (device_get_parent(child) != dev) 5912 return (bus_generic_unmap_resource(dev, child, r, map)); 5913 5914 dinfo = device_get_ivars(child); 5915 if (dinfo->cfg.flags & PCICFG_VF) { 5916 switch (rman_get_type(r)) { 5917 /* VFs can't have I/O BARs. */ 5918 case SYS_RES_IOPORT: 5919 return (EINVAL); 5920 case SYS_RES_MEMORY: 5921 return (pci_vf_unmap_mem_resource(dev, child, r, map)); 5922 } 5923 5924 /* Fall through for other types of resource allocations. */ 5925 } 5926 #endif 5927 5928 return (bus_generic_unmap_resource(dev, child, r, map)); 5929 } 5930 5931 void 5932 pci_child_deleted(device_t dev, device_t child) 5933 { 5934 struct resource_list_entry *rle; 5935 struct resource_list *rl; 5936 struct pci_devinfo *dinfo; 5937 5938 dinfo = device_get_ivars(child); 5939 rl = &dinfo->resources; 5940 5941 EVENTHANDLER_INVOKE(pci_delete_device, child); 5942 5943 /* Turn off access to resources we're about to free */ 5944 if (bus_child_present(child) != 0) { 5945 pci_write_config(child, PCIR_COMMAND, pci_read_config(child, 5946 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2); 5947 5948 pci_disable_busmaster(child); 5949 } 5950 5951 /* Free all allocated resources */ 5952 STAILQ_FOREACH(rle, rl, link) { 5953 if (rle->res) { 5954 if (rman_get_flags(rle->res) & RF_ACTIVE || 5955 resource_list_busy(rl, rle->type, rle->rid)) { 5956 pci_printf(&dinfo->cfg, 5957 "Resource still owned, oops. " 5958 "(type=%d, rid=%d, addr=%lx)\n", 5959 rle->type, rle->rid, 5960 rman_get_start(rle->res)); 5961 bus_release_resource(child, rle->type, rle->rid, 5962 rle->res); 5963 } 5964 resource_list_unreserve(rl, dev, child, rle->type, 5965 rle->rid); 5966 } 5967 } 5968 resource_list_free(rl); 5969 5970 pci_freecfg(dinfo); 5971 } 5972 5973 void 5974 pci_delete_resource(device_t dev, device_t child, int type, int rid) 5975 { 5976 struct pci_devinfo *dinfo; 5977 struct resource_list *rl; 5978 struct resource_list_entry *rle; 5979 5980 if (device_get_parent(child) != dev) 5981 return; 5982 5983 dinfo = device_get_ivars(child); 5984 rl = &dinfo->resources; 5985 rle = resource_list_find(rl, type, rid); 5986 if (rle == NULL) 5987 return; 5988 5989 if (rle->res) { 5990 if (rman_get_flags(rle->res) & RF_ACTIVE || 5991 resource_list_busy(rl, type, rid)) { 5992 device_printf(dev, "delete_resource: " 5993 "Resource still owned by child, oops. " 5994 "(type=%d, rid=%d, addr=%jx)\n", 5995 type, rid, rman_get_start(rle->res)); 5996 return; 5997 } 5998 resource_list_unreserve(rl, dev, child, type, rid); 5999 } 6000 resource_list_delete(rl, type, rid); 6001 } 6002 6003 struct resource_list * 6004 pci_get_resource_list (device_t dev, device_t child) 6005 { 6006 struct pci_devinfo *dinfo = device_get_ivars(child); 6007 6008 return (&dinfo->resources); 6009 } 6010 6011 #ifdef IOMMU 6012 bus_dma_tag_t 6013 pci_get_dma_tag(device_t bus, device_t dev) 6014 { 6015 bus_dma_tag_t tag; 6016 struct pci_softc *sc; 6017 6018 if (device_get_parent(dev) == bus) { 6019 /* try iommu and return if it works */ 6020 tag = iommu_get_dma_tag(bus, dev); 6021 } else 6022 tag = NULL; 6023 if (tag == NULL) { 6024 sc = device_get_softc(bus); 6025 tag = sc->sc_dma_tag; 6026 } 6027 return (tag); 6028 } 6029 #else 6030 bus_dma_tag_t 6031 pci_get_dma_tag(device_t bus, device_t dev) 6032 { 6033 struct pci_softc *sc = device_get_softc(bus); 6034 6035 return (sc->sc_dma_tag); 6036 } 6037 #endif 6038 6039 uint32_t 6040 pci_read_config_method(device_t dev, device_t child, int reg, int width) 6041 { 6042 struct pci_devinfo *dinfo = device_get_ivars(child); 6043 pcicfgregs *cfg = &dinfo->cfg; 6044 6045 #ifdef PCI_IOV 6046 /* 6047 * SR-IOV VFs don't implement the VID or DID registers, so we have to 6048 * emulate them here. 6049 */ 6050 if (cfg->flags & PCICFG_VF) { 6051 if (reg == PCIR_VENDOR) { 6052 switch (width) { 6053 case 4: 6054 return (cfg->device << 16 | cfg->vendor); 6055 case 2: 6056 return (cfg->vendor); 6057 case 1: 6058 return (cfg->vendor & 0xff); 6059 default: 6060 return (0xffffffff); 6061 } 6062 } else if (reg == PCIR_DEVICE) { 6063 switch (width) { 6064 /* Note that an unaligned 4-byte read is an error. */ 6065 case 2: 6066 return (cfg->device); 6067 case 1: 6068 return (cfg->device & 0xff); 6069 default: 6070 return (0xffffffff); 6071 } 6072 } 6073 } 6074 #endif 6075 6076 return (PCIB_READ_CONFIG(device_get_parent(dev), 6077 cfg->bus, cfg->slot, cfg->func, reg, width)); 6078 } 6079 6080 void 6081 pci_write_config_method(device_t dev, device_t child, int reg, 6082 uint32_t val, int width) 6083 { 6084 struct pci_devinfo *dinfo = device_get_ivars(child); 6085 pcicfgregs *cfg = &dinfo->cfg; 6086 6087 PCIB_WRITE_CONFIG(device_get_parent(dev), 6088 cfg->bus, cfg->slot, cfg->func, reg, val, width); 6089 } 6090 6091 int 6092 pci_child_location_method(device_t dev, device_t child, struct sbuf *sb) 6093 { 6094 6095 sbuf_printf(sb, "slot=%d function=%d dbsf=pci%d:%d:%d:%d", 6096 pci_get_slot(child), pci_get_function(child), pci_get_domain(child), 6097 pci_get_bus(child), pci_get_slot(child), pci_get_function(child)); 6098 return (0); 6099 } 6100 6101 int 6102 pci_child_pnpinfo_method(device_t dev, device_t child, struct sbuf *sb) 6103 { 6104 struct pci_devinfo *dinfo; 6105 pcicfgregs *cfg; 6106 6107 dinfo = device_get_ivars(child); 6108 cfg = &dinfo->cfg; 6109 sbuf_printf(sb, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 6110 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 6111 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 6112 cfg->progif); 6113 return (0); 6114 } 6115 6116 int 6117 pci_get_device_path_method(device_t bus, device_t child, const char *locator, 6118 struct sbuf *sb) 6119 { 6120 device_t parent = device_get_parent(bus); 6121 int rv; 6122 6123 if (strcmp(locator, BUS_LOCATOR_UEFI) == 0) { 6124 rv = bus_generic_get_device_path(parent, bus, locator, sb); 6125 if (rv == 0) { 6126 sbuf_printf(sb, "/Pci(0x%x,0x%x)", pci_get_slot(child), 6127 pci_get_function(child)); 6128 } 6129 return (0); 6130 } 6131 return (bus_generic_get_device_path(bus, child, locator, sb)); 6132 } 6133 6134 int 6135 pci_assign_interrupt_method(device_t dev, device_t child) 6136 { 6137 struct pci_devinfo *dinfo = device_get_ivars(child); 6138 pcicfgregs *cfg = &dinfo->cfg; 6139 6140 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 6141 cfg->intpin)); 6142 } 6143 6144 static void 6145 pci_lookup(void *arg, const char *name, device_t *dev) 6146 { 6147 long val; 6148 char *end; 6149 int domain, bus, slot, func; 6150 6151 if (*dev != NULL) 6152 return; 6153 6154 /* 6155 * Accept pciconf-style selectors of either pciD:B:S:F or 6156 * pciB:S:F. In the latter case, the domain is assumed to 6157 * be zero. 6158 */ 6159 if (strncmp(name, "pci", 3) != 0) 6160 return; 6161 val = strtol(name + 3, &end, 10); 6162 if (val < 0 || val > INT_MAX || *end != ':') 6163 return; 6164 domain = val; 6165 val = strtol(end + 1, &end, 10); 6166 if (val < 0 || val > INT_MAX || *end != ':') 6167 return; 6168 bus = val; 6169 val = strtol(end + 1, &end, 10); 6170 if (val < 0 || val > INT_MAX) 6171 return; 6172 slot = val; 6173 if (*end == ':') { 6174 val = strtol(end + 1, &end, 10); 6175 if (val < 0 || val > INT_MAX || *end != '\0') 6176 return; 6177 func = val; 6178 } else if (*end == '\0') { 6179 func = slot; 6180 slot = bus; 6181 bus = domain; 6182 domain = 0; 6183 } else 6184 return; 6185 6186 if (domain > PCI_DOMAINMAX || bus > PCI_BUSMAX || slot > PCI_SLOTMAX || 6187 func > PCIE_ARI_FUNCMAX || (slot != 0 && func > PCI_FUNCMAX)) 6188 return; 6189 6190 *dev = pci_find_dbsf(domain, bus, slot, func); 6191 } 6192 6193 static int 6194 pci_modevent(module_t mod, int what, void *arg) 6195 { 6196 static struct cdev *pci_cdev; 6197 static eventhandler_tag tag; 6198 6199 switch (what) { 6200 case MOD_LOAD: 6201 STAILQ_INIT(&pci_devq); 6202 pci_generation = 0; 6203 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 6204 "pci"); 6205 pci_load_vendor_data(); 6206 tag = EVENTHANDLER_REGISTER(dev_lookup, pci_lookup, NULL, 6207 1000); 6208 break; 6209 6210 case MOD_UNLOAD: 6211 if (tag != NULL) 6212 EVENTHANDLER_DEREGISTER(dev_lookup, tag); 6213 destroy_dev(pci_cdev); 6214 break; 6215 } 6216 6217 return (0); 6218 } 6219 6220 static void 6221 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo) 6222 { 6223 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2) 6224 struct pcicfg_pcie *cfg; 6225 int version, pos; 6226 6227 cfg = &dinfo->cfg.pcie; 6228 pos = cfg->pcie_location; 6229 6230 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6231 6232 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); 6233 6234 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6235 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6236 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6237 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); 6238 6239 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6240 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6241 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6242 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); 6243 6244 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6245 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6246 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); 6247 6248 if (version > 1) { 6249 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); 6250 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); 6251 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); 6252 } 6253 #undef WREG 6254 } 6255 6256 static void 6257 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo) 6258 { 6259 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 6260 dinfo->cfg.pcix.pcix_command, 2); 6261 } 6262 6263 void 6264 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 6265 { 6266 6267 /* 6268 * Restore the device to full power mode. We must do this 6269 * before we restore the registers because moving from D3 to 6270 * D0 will cause the chip's BARs and some other registers to 6271 * be reset to some unknown power on reset values. Cut down 6272 * the noise on boot by doing nothing if we are already in 6273 * state D0. 6274 */ 6275 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) 6276 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6277 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 6278 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 6279 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 6280 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 6281 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 6282 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 6283 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6284 case PCIM_HDRTYPE_NORMAL: 6285 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 6286 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 6287 break; 6288 case PCIM_HDRTYPE_BRIDGE: 6289 pci_write_config(dev, PCIR_SECLAT_1, 6290 dinfo->cfg.bridge.br_seclat, 1); 6291 pci_write_config(dev, PCIR_SUBBUS_1, 6292 dinfo->cfg.bridge.br_subbus, 1); 6293 pci_write_config(dev, PCIR_SECBUS_1, 6294 dinfo->cfg.bridge.br_secbus, 1); 6295 pci_write_config(dev, PCIR_PRIBUS_1, 6296 dinfo->cfg.bridge.br_pribus, 1); 6297 pci_write_config(dev, PCIR_BRIDGECTL_1, 6298 dinfo->cfg.bridge.br_control, 2); 6299 break; 6300 case PCIM_HDRTYPE_CARDBUS: 6301 pci_write_config(dev, PCIR_SECLAT_2, 6302 dinfo->cfg.bridge.br_seclat, 1); 6303 pci_write_config(dev, PCIR_SUBBUS_2, 6304 dinfo->cfg.bridge.br_subbus, 1); 6305 pci_write_config(dev, PCIR_SECBUS_2, 6306 dinfo->cfg.bridge.br_secbus, 1); 6307 pci_write_config(dev, PCIR_PRIBUS_2, 6308 dinfo->cfg.bridge.br_pribus, 1); 6309 pci_write_config(dev, PCIR_BRIDGECTL_2, 6310 dinfo->cfg.bridge.br_control, 2); 6311 break; 6312 } 6313 pci_restore_bars(dev); 6314 6315 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE) 6316 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 6317 6318 /* 6319 * Restore extended capabilities for PCI-Express and PCI-X 6320 */ 6321 if (dinfo->cfg.pcie.pcie_location != 0) 6322 pci_cfg_restore_pcie(dev, dinfo); 6323 if (dinfo->cfg.pcix.pcix_location != 0) 6324 pci_cfg_restore_pcix(dev, dinfo); 6325 6326 /* Restore MSI and MSI-X configurations if they are present. */ 6327 if (dinfo->cfg.msi.msi_location != 0) 6328 pci_resume_msi(dev); 6329 if (dinfo->cfg.msix.msix_location != 0) 6330 pci_resume_msix(dev); 6331 6332 #ifdef PCI_IOV 6333 if (dinfo->cfg.iov != NULL) 6334 pci_iov_cfg_restore(dev, dinfo); 6335 #endif 6336 } 6337 6338 static void 6339 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo) 6340 { 6341 #define RREG(n) pci_read_config(dev, pos + (n), 2) 6342 struct pcicfg_pcie *cfg; 6343 int version, pos; 6344 6345 cfg = &dinfo->cfg.pcie; 6346 pos = cfg->pcie_location; 6347 6348 cfg->pcie_flags = RREG(PCIER_FLAGS); 6349 6350 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; 6351 6352 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); 6353 6354 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6355 cfg->pcie_type == PCIEM_TYPE_ENDPOINT || 6356 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) 6357 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); 6358 6359 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6360 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && 6361 (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) 6362 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); 6363 6364 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || 6365 cfg->pcie_type == PCIEM_TYPE_ROOT_EC) 6366 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); 6367 6368 if (version > 1) { 6369 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); 6370 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); 6371 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); 6372 } 6373 #undef RREG 6374 } 6375 6376 static void 6377 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo) 6378 { 6379 dinfo->cfg.pcix.pcix_command = pci_read_config(dev, 6380 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2); 6381 } 6382 6383 void 6384 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 6385 { 6386 uint32_t cls; 6387 int ps; 6388 6389 /* 6390 * Some drivers apparently write to these registers w/o updating our 6391 * cached copy. No harm happens if we update the copy, so do so here 6392 * so we can restore them. The COMMAND register is modified by the 6393 * bus w/o updating the cache. This should represent the normally 6394 * writable portion of the 'defined' part of type 0/1/2 headers. 6395 */ 6396 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 6397 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 6398 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 6399 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 6400 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 6401 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 6402 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 6403 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 6404 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 6405 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 6406 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 6407 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) { 6408 case PCIM_HDRTYPE_NORMAL: 6409 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 6410 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 6411 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 6412 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 6413 break; 6414 case PCIM_HDRTYPE_BRIDGE: 6415 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6416 PCIR_SECLAT_1, 1); 6417 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6418 PCIR_SUBBUS_1, 1); 6419 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6420 PCIR_SECBUS_1, 1); 6421 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6422 PCIR_PRIBUS_1, 1); 6423 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6424 PCIR_BRIDGECTL_1, 2); 6425 break; 6426 case PCIM_HDRTYPE_CARDBUS: 6427 dinfo->cfg.bridge.br_seclat = pci_read_config(dev, 6428 PCIR_SECLAT_2, 1); 6429 dinfo->cfg.bridge.br_subbus = pci_read_config(dev, 6430 PCIR_SUBBUS_2, 1); 6431 dinfo->cfg.bridge.br_secbus = pci_read_config(dev, 6432 PCIR_SECBUS_2, 1); 6433 dinfo->cfg.bridge.br_pribus = pci_read_config(dev, 6434 PCIR_PRIBUS_2, 1); 6435 dinfo->cfg.bridge.br_control = pci_read_config(dev, 6436 PCIR_BRIDGECTL_2, 2); 6437 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2); 6438 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2); 6439 break; 6440 } 6441 6442 if (dinfo->cfg.pcie.pcie_location != 0) 6443 pci_cfg_save_pcie(dev, dinfo); 6444 6445 if (dinfo->cfg.pcix.pcix_location != 0) 6446 pci_cfg_save_pcix(dev, dinfo); 6447 6448 #ifdef PCI_IOV 6449 if (dinfo->cfg.iov != NULL) 6450 pci_iov_cfg_save(dev, dinfo); 6451 #endif 6452 6453 /* 6454 * don't set the state for display devices, base peripherals and 6455 * memory devices since bad things happen when they are powered down. 6456 * We should (a) have drivers that can easily detach and (b) use 6457 * generic drivers for these devices so that some device actually 6458 * attaches. We need to make sure that when we implement (a) we don't 6459 * power the device down on a reattach. 6460 */ 6461 cls = pci_get_class(dev); 6462 if (!setstate) 6463 return; 6464 switch (pci_do_power_nodriver) 6465 { 6466 case 0: /* NO powerdown at all */ 6467 return; 6468 case 1: /* Conservative about what to power down */ 6469 if (cls == PCIC_STORAGE) 6470 return; 6471 /*FALLTHROUGH*/ 6472 case 2: /* Aggressive about what to power down */ 6473 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 6474 cls == PCIC_BASEPERIPH) 6475 return; 6476 /*FALLTHROUGH*/ 6477 case 3: /* Power down everything */ 6478 break; 6479 } 6480 /* 6481 * PCI spec says we can only go into D3 state from D0 state. 6482 * Transition from D[12] into D0 before going to D3 state. 6483 */ 6484 ps = pci_get_powerstate(dev); 6485 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6486 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6487 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 6488 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6489 } 6490 6491 /* Wrapper APIs suitable for device driver use. */ 6492 void 6493 pci_save_state(device_t dev) 6494 { 6495 struct pci_devinfo *dinfo; 6496 6497 dinfo = device_get_ivars(dev); 6498 pci_cfg_save(dev, dinfo, 0); 6499 } 6500 6501 void 6502 pci_restore_state(device_t dev) 6503 { 6504 struct pci_devinfo *dinfo; 6505 6506 dinfo = device_get_ivars(dev); 6507 pci_cfg_restore(dev, dinfo); 6508 } 6509 6510 static int 6511 pci_get_id_method(device_t dev, device_t child, enum pci_id_type type, 6512 uintptr_t *id) 6513 { 6514 6515 return (PCIB_GET_ID(device_get_parent(dev), child, type, id)); 6516 } 6517 6518 /* Find the upstream port of a given PCI device in a root complex. */ 6519 device_t 6520 pci_find_pcie_root_port(device_t dev) 6521 { 6522 struct pci_devinfo *dinfo; 6523 devclass_t pci_class; 6524 device_t pcib, bus; 6525 6526 pci_class = devclass_find("pci"); 6527 KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class, 6528 ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); 6529 6530 /* 6531 * Walk the bridge hierarchy until we find a PCI-e root 6532 * port or a non-PCI device. 6533 */ 6534 for (;;) { 6535 bus = device_get_parent(dev); 6536 KASSERT(bus != NULL, ("%s: null parent of %s", __func__, 6537 device_get_nameunit(dev))); 6538 6539 pcib = device_get_parent(bus); 6540 KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__, 6541 device_get_nameunit(bus))); 6542 6543 /* 6544 * pcib's parent must be a PCI bus for this to be a 6545 * PCI-PCI bridge. 6546 */ 6547 if (device_get_devclass(device_get_parent(pcib)) != pci_class) 6548 return (NULL); 6549 6550 dinfo = device_get_ivars(pcib); 6551 if (dinfo->cfg.pcie.pcie_location != 0 && 6552 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) 6553 return (pcib); 6554 6555 dev = pcib; 6556 } 6557 } 6558 6559 /* 6560 * Wait for pending transactions to complete on a PCI-express function. 6561 * 6562 * The maximum delay is specified in milliseconds in max_delay. Note 6563 * that this function may sleep. 6564 * 6565 * Returns true if the function is idle and false if the timeout is 6566 * exceeded. If dev is not a PCI-express function, this returns true. 6567 */ 6568 bool 6569 pcie_wait_for_pending_transactions(device_t dev, u_int max_delay) 6570 { 6571 struct pci_devinfo *dinfo = device_get_ivars(dev); 6572 uint16_t sta; 6573 int cap; 6574 6575 cap = dinfo->cfg.pcie.pcie_location; 6576 if (cap == 0) 6577 return (true); 6578 6579 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6580 while (sta & PCIEM_STA_TRANSACTION_PND) { 6581 if (max_delay == 0) 6582 return (false); 6583 6584 /* Poll once every 100 milliseconds up to the timeout. */ 6585 if (max_delay > 100) { 6586 pause_sbt("pcietp", 100 * SBT_1MS, 0, C_HARDCLOCK); 6587 max_delay -= 100; 6588 } else { 6589 pause_sbt("pcietp", max_delay * SBT_1MS, 0, 6590 C_HARDCLOCK); 6591 max_delay = 0; 6592 } 6593 sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2); 6594 } 6595 6596 return (true); 6597 } 6598 6599 /* 6600 * Determine the maximum Completion Timeout in microseconds. 6601 * 6602 * For non-PCI-express functions this returns 0. 6603 */ 6604 int 6605 pcie_get_max_completion_timeout(device_t dev) 6606 { 6607 struct pci_devinfo *dinfo = device_get_ivars(dev); 6608 int cap; 6609 6610 cap = dinfo->cfg.pcie.pcie_location; 6611 if (cap == 0) 6612 return (0); 6613 6614 /* 6615 * Functions using the 1.x spec use the default timeout range of 6616 * 50 microseconds to 50 milliseconds. Functions that do not 6617 * support programmable timeouts also use this range. 6618 */ 6619 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 || 6620 (pci_read_config(dev, cap + PCIER_DEVICE_CAP2, 4) & 6621 PCIEM_CAP2_COMP_TIMO_RANGES) == 0) 6622 return (50 * 1000); 6623 6624 switch (pci_read_config(dev, cap + PCIER_DEVICE_CTL2, 2) & 6625 PCIEM_CTL2_COMP_TIMO_VAL) { 6626 case PCIEM_CTL2_COMP_TIMO_100US: 6627 return (100); 6628 case PCIEM_CTL2_COMP_TIMO_10MS: 6629 return (10 * 1000); 6630 case PCIEM_CTL2_COMP_TIMO_55MS: 6631 return (55 * 1000); 6632 case PCIEM_CTL2_COMP_TIMO_210MS: 6633 return (210 * 1000); 6634 case PCIEM_CTL2_COMP_TIMO_900MS: 6635 return (900 * 1000); 6636 case PCIEM_CTL2_COMP_TIMO_3500MS: 6637 return (3500 * 1000); 6638 case PCIEM_CTL2_COMP_TIMO_13S: 6639 return (13 * 1000 * 1000); 6640 case PCIEM_CTL2_COMP_TIMO_64S: 6641 return (64 * 1000 * 1000); 6642 default: 6643 return (50 * 1000); 6644 } 6645 } 6646 6647 void 6648 pcie_apei_error(device_t dev, int sev, uint8_t *aerp) 6649 { 6650 struct pci_devinfo *dinfo = device_get_ivars(dev); 6651 const char *s; 6652 int aer; 6653 uint32_t r, r1; 6654 uint16_t rs; 6655 6656 if (sev == PCIEM_STA_CORRECTABLE_ERROR) 6657 s = "Correctable"; 6658 else if (sev == PCIEM_STA_NON_FATAL_ERROR) 6659 s = "Uncorrectable (Non-Fatal)"; 6660 else 6661 s = "Uncorrectable (Fatal)"; 6662 device_printf(dev, "%s PCIe error reported by APEI\n", s); 6663 if (aerp) { 6664 if (sev == PCIEM_STA_CORRECTABLE_ERROR) { 6665 r = le32dec(aerp + PCIR_AER_COR_STATUS); 6666 r1 = le32dec(aerp + PCIR_AER_COR_MASK); 6667 } else { 6668 r = le32dec(aerp + PCIR_AER_UC_STATUS); 6669 r1 = le32dec(aerp + PCIR_AER_UC_MASK); 6670 } 6671 device_printf(dev, "status 0x%08x mask 0x%08x", r, r1); 6672 if (sev != PCIEM_STA_CORRECTABLE_ERROR) { 6673 r = le32dec(aerp + PCIR_AER_UC_SEVERITY); 6674 rs = le16dec(aerp + PCIR_AER_CAP_CONTROL); 6675 printf(" severity 0x%08x first %d\n", 6676 r, rs & 0x1f); 6677 } else 6678 printf("\n"); 6679 } 6680 6681 /* As kind of recovery just report and clear the error statuses. */ 6682 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6683 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6684 if (r != 0) { 6685 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 6686 device_printf(dev, "Clearing UC AER errors 0x%08x\n", r); 6687 } 6688 6689 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6690 if (r != 0) { 6691 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 6692 device_printf(dev, "Clearing COR AER errors 0x%08x\n", r); 6693 } 6694 } 6695 if (dinfo->cfg.pcie.pcie_location != 0) { 6696 rs = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6697 PCIER_DEVICE_STA, 2); 6698 if ((rs & (PCIEM_STA_CORRECTABLE_ERROR | 6699 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6700 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6701 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6702 PCIER_DEVICE_STA, rs, 2); 6703 device_printf(dev, "Clearing PCIe errors 0x%04x\n", rs); 6704 } 6705 } 6706 } 6707 6708 /* 6709 * Perform a Function Level Reset (FLR) on a device. 6710 * 6711 * This function first waits for any pending transactions to complete 6712 * within the timeout specified by max_delay. If transactions are 6713 * still pending, the function will return false without attempting a 6714 * reset. 6715 * 6716 * If dev is not a PCI-express function or does not support FLR, this 6717 * function returns false. 6718 * 6719 * Note that no registers are saved or restored. The caller is 6720 * responsible for saving and restoring any registers including 6721 * PCI-standard registers via pci_save_state() and 6722 * pci_restore_state(). 6723 */ 6724 bool 6725 pcie_flr(device_t dev, u_int max_delay, bool force) 6726 { 6727 struct pci_devinfo *dinfo = device_get_ivars(dev); 6728 uint16_t cmd, ctl; 6729 int compl_delay; 6730 int cap; 6731 6732 cap = dinfo->cfg.pcie.pcie_location; 6733 if (cap == 0) 6734 return (false); 6735 6736 if (!(pci_read_config(dev, cap + PCIER_DEVICE_CAP, 4) & PCIEM_CAP_FLR)) 6737 return (false); 6738 6739 /* 6740 * Disable busmastering to prevent generation of new 6741 * transactions while waiting for the device to go idle. If 6742 * the idle timeout fails, the command register is restored 6743 * which will re-enable busmastering. 6744 */ 6745 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 6746 pci_write_config(dev, PCIR_COMMAND, cmd & ~(PCIM_CMD_BUSMASTEREN), 2); 6747 if (!pcie_wait_for_pending_transactions(dev, max_delay)) { 6748 if (!force) { 6749 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 6750 return (false); 6751 } 6752 pci_printf(&dinfo->cfg, 6753 "Resetting with transactions pending after %d ms\n", 6754 max_delay); 6755 6756 /* 6757 * Extend the post-FLR delay to cover the maximum 6758 * Completion Timeout delay of anything in flight 6759 * during the FLR delay. Enforce a minimum delay of 6760 * at least 10ms. 6761 */ 6762 compl_delay = pcie_get_max_completion_timeout(dev) / 1000; 6763 if (compl_delay < 10) 6764 compl_delay = 10; 6765 } else 6766 compl_delay = 0; 6767 6768 /* Initiate the reset. */ 6769 ctl = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); 6770 pci_write_config(dev, cap + PCIER_DEVICE_CTL, ctl | 6771 PCIEM_CTL_INITIATE_FLR, 2); 6772 6773 /* Wait for 100ms. */ 6774 pause_sbt("pcieflr", (100 + compl_delay) * SBT_1MS, 0, C_HARDCLOCK); 6775 6776 if (pci_read_config(dev, cap + PCIER_DEVICE_STA, 2) & 6777 PCIEM_STA_TRANSACTION_PND) 6778 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n"); 6779 return (true); 6780 } 6781 6782 /* 6783 * Attempt a power-management reset by cycling the device in/out of D3 6784 * state. PCI spec says we can only go into D3 state from D0 state. 6785 * Transition from D[12] into D0 before going to D3 state. 6786 */ 6787 int 6788 pci_power_reset(device_t dev) 6789 { 6790 int ps; 6791 6792 ps = pci_get_powerstate(dev); 6793 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 6794 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 6795 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 6796 pci_set_powerstate(dev, ps); 6797 return (0); 6798 } 6799 6800 /* 6801 * Try link drop and retrain of the downstream port of upstream 6802 * switch, for PCIe. According to the PCIe 3.0 spec 6.6.1, this must 6803 * cause Conventional Hot reset of the device in the slot. 6804 * Alternative, for PCIe, could be the secondary bus reset initiatied 6805 * on the upstream switch PCIR_BRIDGECTL_1, bit 6. 6806 */ 6807 int 6808 pcie_link_reset(device_t port, int pcie_location) 6809 { 6810 uint16_t v; 6811 6812 v = pci_read_config(port, pcie_location + PCIER_LINK_CTL, 2); 6813 v |= PCIEM_LINK_CTL_LINK_DIS; 6814 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6815 pause_sbt("pcier1", mstosbt(20), 0, 0); 6816 v &= ~PCIEM_LINK_CTL_LINK_DIS; 6817 v |= PCIEM_LINK_CTL_RETRAIN_LINK; 6818 pci_write_config(port, pcie_location + PCIER_LINK_CTL, v, 2); 6819 pause_sbt("pcier2", mstosbt(100), 0, 0); /* 100 ms */ 6820 v = pci_read_config(port, pcie_location + PCIER_LINK_STA, 2); 6821 return ((v & PCIEM_LINK_STA_TRAINING) != 0 ? ETIMEDOUT : 0); 6822 } 6823 6824 static int 6825 pci_reset_post(device_t dev, device_t child) 6826 { 6827 6828 if (dev == device_get_parent(child)) 6829 pci_restore_state(child); 6830 return (0); 6831 } 6832 6833 static int 6834 pci_reset_prepare(device_t dev, device_t child) 6835 { 6836 6837 if (dev == device_get_parent(child)) 6838 pci_save_state(child); 6839 return (0); 6840 } 6841 6842 static int 6843 pci_reset_child(device_t dev, device_t child, int flags) 6844 { 6845 int error; 6846 6847 if (dev == NULL || device_get_parent(child) != dev) 6848 return (0); 6849 if ((flags & DEVF_RESET_DETACH) != 0) { 6850 error = device_get_state(child) == DS_ATTACHED ? 6851 device_detach(child) : 0; 6852 } else { 6853 error = BUS_SUSPEND_CHILD(dev, child); 6854 } 6855 if (error == 0) { 6856 if (!pcie_flr(child, 1000, false)) { 6857 error = BUS_RESET_PREPARE(dev, child); 6858 if (error == 0) 6859 pci_power_reset(child); 6860 BUS_RESET_POST(dev, child); 6861 } 6862 if ((flags & DEVF_RESET_DETACH) != 0) 6863 device_probe_and_attach(child); 6864 else 6865 BUS_RESUME_CHILD(dev, child); 6866 } 6867 return (error); 6868 } 6869 6870 const struct pci_device_table * 6871 pci_match_device(device_t child, const struct pci_device_table *id, size_t nelt) 6872 { 6873 bool match; 6874 uint16_t vendor, device, subvendor, subdevice, class, subclass, revid; 6875 6876 vendor = pci_get_vendor(child); 6877 device = pci_get_device(child); 6878 subvendor = pci_get_subvendor(child); 6879 subdevice = pci_get_subdevice(child); 6880 class = pci_get_class(child); 6881 subclass = pci_get_subclass(child); 6882 revid = pci_get_revid(child); 6883 while (nelt-- > 0) { 6884 match = true; 6885 if (id->match_flag_vendor) 6886 match &= vendor == id->vendor; 6887 if (id->match_flag_device) 6888 match &= device == id->device; 6889 if (id->match_flag_subvendor) 6890 match &= subvendor == id->subvendor; 6891 if (id->match_flag_subdevice) 6892 match &= subdevice == id->subdevice; 6893 if (id->match_flag_class) 6894 match &= class == id->class_id; 6895 if (id->match_flag_subclass) 6896 match &= subclass == id->subclass; 6897 if (id->match_flag_revid) 6898 match &= revid == id->revid; 6899 if (match) 6900 return (id); 6901 id++; 6902 } 6903 return (NULL); 6904 } 6905 6906 static void 6907 pci_print_faulted_dev_name(const struct pci_devinfo *dinfo) 6908 { 6909 const char *dev_name; 6910 device_t dev; 6911 6912 dev = dinfo->cfg.dev; 6913 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus, 6914 dinfo->cfg.slot, dinfo->cfg.func); 6915 dev_name = device_get_name(dev); 6916 if (dev_name != NULL) 6917 printf(" (%s%d)", dev_name, device_get_unit(dev)); 6918 } 6919 6920 void 6921 pci_print_faulted_dev(void) 6922 { 6923 struct pci_devinfo *dinfo; 6924 device_t dev; 6925 int aer, i; 6926 uint32_t r1, r2; 6927 uint16_t status; 6928 6929 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 6930 dev = dinfo->cfg.dev; 6931 status = pci_read_config(dev, PCIR_STATUS, 2); 6932 status &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 6933 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 6934 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 6935 if (status != 0) { 6936 pci_print_faulted_dev_name(dinfo); 6937 printf(" error 0x%04x\n", status); 6938 } 6939 if (dinfo->cfg.pcie.pcie_location != 0) { 6940 status = pci_read_config(dev, 6941 dinfo->cfg.pcie.pcie_location + 6942 PCIER_DEVICE_STA, 2); 6943 if ((status & (PCIEM_STA_CORRECTABLE_ERROR | 6944 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 6945 PCIEM_STA_UNSUPPORTED_REQ)) != 0) { 6946 pci_print_faulted_dev_name(dinfo); 6947 printf(" PCIe DEVCTL 0x%04x DEVSTA 0x%04x\n", 6948 pci_read_config(dev, 6949 dinfo->cfg.pcie.pcie_location + 6950 PCIER_DEVICE_CTL, 2), 6951 status); 6952 } 6953 } 6954 if (pci_find_extcap(dev, PCIZ_AER, &aer) == 0) { 6955 r1 = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 6956 r2 = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 6957 if (r1 != 0 || r2 != 0) { 6958 pci_print_faulted_dev_name(dinfo); 6959 printf(" AER UC 0x%08x Mask 0x%08x Svr 0x%08x\n" 6960 " COR 0x%08x Mask 0x%08x Ctl 0x%08x\n", 6961 r1, pci_read_config(dev, aer + 6962 PCIR_AER_UC_MASK, 4), 6963 pci_read_config(dev, aer + 6964 PCIR_AER_UC_SEVERITY, 4), 6965 r2, pci_read_config(dev, aer + 6966 PCIR_AER_COR_MASK, 4), 6967 pci_read_config(dev, aer + 6968 PCIR_AER_CAP_CONTROL, 4)); 6969 for (i = 0; i < 4; i++) { 6970 r1 = pci_read_config(dev, aer + 6971 PCIR_AER_HEADER_LOG + i * 4, 4); 6972 printf(" HL%d: 0x%08x\n", i, r1); 6973 } 6974 } 6975 } 6976 } 6977 } 6978 6979 #ifdef DDB 6980 DB_SHOW_COMMAND_FLAGS(pcierr, pci_print_faulted_dev_db, DB_CMD_MEMSAFE) 6981 { 6982 6983 pci_print_faulted_dev(); 6984 } 6985 6986 static void 6987 db_clear_pcie_errors(const struct pci_devinfo *dinfo) 6988 { 6989 device_t dev; 6990 int aer; 6991 uint32_t r; 6992 6993 dev = dinfo->cfg.dev; 6994 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location + 6995 PCIER_DEVICE_STA, 2); 6996 pci_write_config(dev, dinfo->cfg.pcie.pcie_location + 6997 PCIER_DEVICE_STA, r, 2); 6998 6999 if (pci_find_extcap(dev, PCIZ_AER, &aer) != 0) 7000 return; 7001 r = pci_read_config(dev, aer + PCIR_AER_UC_STATUS, 4); 7002 if (r != 0) 7003 pci_write_config(dev, aer + PCIR_AER_UC_STATUS, r, 4); 7004 r = pci_read_config(dev, aer + PCIR_AER_COR_STATUS, 4); 7005 if (r != 0) 7006 pci_write_config(dev, aer + PCIR_AER_COR_STATUS, r, 4); 7007 } 7008 7009 DB_COMMAND_FLAGS(pci_clearerr, db_pci_clearerr, DB_CMD_MEMSAFE) 7010 { 7011 struct pci_devinfo *dinfo; 7012 device_t dev; 7013 uint16_t status, status1; 7014 7015 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 7016 dev = dinfo->cfg.dev; 7017 status1 = status = pci_read_config(dev, PCIR_STATUS, 2); 7018 status1 &= PCIM_STATUS_MDPERR | PCIM_STATUS_STABORT | 7019 PCIM_STATUS_RTABORT | PCIM_STATUS_RMABORT | 7020 PCIM_STATUS_SERR | PCIM_STATUS_PERR; 7021 if (status1 != 0) { 7022 status &= ~status1; 7023 pci_write_config(dev, PCIR_STATUS, status, 2); 7024 } 7025 if (dinfo->cfg.pcie.pcie_location != 0) 7026 db_clear_pcie_errors(dinfo); 7027 } 7028 } 7029 #endif 7030