1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/linker.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/sysctl.h> 44 #include <sys/endian.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 55 #include <sys/pciio.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pci_private.h> 59 60 #include "pcib_if.h" 61 #include "pci_if.h" 62 63 #ifdef __HAVE_ACPI 64 #include <contrib/dev/acpica/acpi.h> 65 #include "acpi_if.h" 66 #else 67 #define ACPI_PWR_FOR_SLEEP(x, y, z) 68 #endif 69 70 static uint32_t pci_mapbase(unsigned mapreg); 71 static int pci_maptype(unsigned mapreg); 72 static int pci_mapsize(unsigned testval); 73 static int pci_maprange(unsigned mapreg); 74 static void pci_fixancient(pcicfgregs *cfg); 75 76 static int pci_porten(device_t pcib, int b, int s, int f); 77 static int pci_memen(device_t pcib, int b, int s, int f); 78 static void pci_assign_interrupt(device_t bus, device_t dev, 79 int force_route); 80 static int pci_add_map(device_t pcib, device_t bus, device_t dev, 81 int b, int s, int f, int reg, 82 struct resource_list *rl, int force, int prefetch); 83 static int pci_probe(device_t dev); 84 static int pci_attach(device_t dev); 85 static void pci_load_vendor_data(void); 86 static int pci_describe_parse_line(char **ptr, int *vendor, 87 int *device, char **desc); 88 static char *pci_describe_device(device_t dev); 89 static int pci_modevent(module_t mod, int what, void *arg); 90 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 91 pcicfgregs *cfg); 92 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 93 static uint32_t pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 94 int reg); 95 #if 0 96 static void pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 97 int reg, uint32_t data); 98 #endif 99 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 100 101 static device_method_t pci_methods[] = { 102 /* Device interface */ 103 DEVMETHOD(device_probe, pci_probe), 104 DEVMETHOD(device_attach, pci_attach), 105 DEVMETHOD(device_detach, bus_generic_detach), 106 DEVMETHOD(device_shutdown, bus_generic_shutdown), 107 DEVMETHOD(device_suspend, pci_suspend), 108 DEVMETHOD(device_resume, pci_resume), 109 110 /* Bus interface */ 111 DEVMETHOD(bus_print_child, pci_print_child), 112 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 113 DEVMETHOD(bus_read_ivar, pci_read_ivar), 114 DEVMETHOD(bus_write_ivar, pci_write_ivar), 115 DEVMETHOD(bus_driver_added, pci_driver_added), 116 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 117 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 118 119 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 120 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 121 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 122 DEVMETHOD(bus_delete_resource, pci_delete_resource), 123 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 124 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 125 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 126 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 127 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 128 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 129 130 /* PCI interface */ 131 DEVMETHOD(pci_read_config, pci_read_config_method), 132 DEVMETHOD(pci_write_config, pci_write_config_method), 133 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 134 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 135 DEVMETHOD(pci_enable_io, pci_enable_io_method), 136 DEVMETHOD(pci_disable_io, pci_disable_io_method), 137 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 138 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 139 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 140 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 141 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 142 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 143 144 { 0, 0 } 145 }; 146 147 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 148 149 static devclass_t pci_devclass; 150 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 151 MODULE_VERSION(pci, 1); 152 153 static char *pci_vendordata; 154 static size_t pci_vendordata_size; 155 156 157 struct pci_quirk { 158 uint32_t devid; /* Vendor/device of the card */ 159 int type; 160 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 161 int arg1; 162 int arg2; 163 }; 164 165 struct pci_quirk pci_quirks[] = { 166 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 167 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 168 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 169 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 170 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 171 172 { 0 } 173 }; 174 175 /* map register information */ 176 #define PCI_MAPMEM 0x01 /* memory map */ 177 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 178 #define PCI_MAPPORT 0x04 /* port map */ 179 180 struct devlist pci_devq; 181 uint32_t pci_generation; 182 uint32_t pci_numdevs = 0; 183 184 /* sysctl vars */ 185 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 186 187 static int pci_enable_io_modes = 1; 188 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 189 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 190 &pci_enable_io_modes, 1, 191 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 192 enable these bits correctly. We'd like to do this all the time, but there\n\ 193 are some peripherals that this causes problems with."); 194 195 static int pci_do_power_nodriver = 0; 196 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver); 197 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW, 198 &pci_do_power_nodriver, 0, 199 "Place a function into D3 state when no driver attaches to it. 0 means\n\ 200 disable. 1 means conservatively place devices into D3 state. 2 means\n\ 201 agressively place devices into D3 state. 3 means put absolutely everything\n\ 202 in D3 state."); 203 204 static int pci_do_power_resume = 1; 205 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume); 206 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW, 207 &pci_do_power_resume, 1, 208 "Transition from D3 -> D0 on resume."); 209 210 /* Find a device_t by bus/slot/function */ 211 212 device_t 213 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 214 { 215 struct pci_devinfo *dinfo; 216 217 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 218 if ((dinfo->cfg.bus == bus) && 219 (dinfo->cfg.slot == slot) && 220 (dinfo->cfg.func == func)) { 221 return (dinfo->cfg.dev); 222 } 223 } 224 225 return (NULL); 226 } 227 228 /* Find a device_t by vendor/device ID */ 229 230 device_t 231 pci_find_device(uint16_t vendor, uint16_t device) 232 { 233 struct pci_devinfo *dinfo; 234 235 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 236 if ((dinfo->cfg.vendor == vendor) && 237 (dinfo->cfg.device == device)) { 238 return (dinfo->cfg.dev); 239 } 240 } 241 242 return (NULL); 243 } 244 245 /* return base address of memory or port map */ 246 247 static uint32_t 248 pci_mapbase(unsigned mapreg) 249 { 250 int mask = 0x03; 251 if ((mapreg & 0x01) == 0) 252 mask = 0x0f; 253 return (mapreg & ~mask); 254 } 255 256 /* return map type of memory or port map */ 257 258 static int 259 pci_maptype(unsigned mapreg) 260 { 261 static uint8_t maptype[0x10] = { 262 PCI_MAPMEM, PCI_MAPPORT, 263 PCI_MAPMEM, 0, 264 PCI_MAPMEM, PCI_MAPPORT, 265 0, 0, 266 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 267 PCI_MAPMEM|PCI_MAPMEMP, 0, 268 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 269 0, 0, 270 }; 271 272 return maptype[mapreg & 0x0f]; 273 } 274 275 /* return log2 of map size decoded for memory or port map */ 276 277 static int 278 pci_mapsize(unsigned testval) 279 { 280 int ln2size; 281 282 testval = pci_mapbase(testval); 283 ln2size = 0; 284 if (testval != 0) { 285 while ((testval & 1) == 0) 286 { 287 ln2size++; 288 testval >>= 1; 289 } 290 } 291 return (ln2size); 292 } 293 294 /* return log2 of address range supported by map register */ 295 296 static int 297 pci_maprange(unsigned mapreg) 298 { 299 int ln2range = 0; 300 switch (mapreg & 0x07) { 301 case 0x00: 302 case 0x01: 303 case 0x05: 304 ln2range = 32; 305 break; 306 case 0x02: 307 ln2range = 20; 308 break; 309 case 0x04: 310 ln2range = 64; 311 break; 312 } 313 return (ln2range); 314 } 315 316 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 317 318 static void 319 pci_fixancient(pcicfgregs *cfg) 320 { 321 if (cfg->hdrtype != 0) 322 return; 323 324 /* PCI to PCI bridges use header type 1 */ 325 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 326 cfg->hdrtype = 1; 327 } 328 329 /* extract header type specific config data */ 330 331 static void 332 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 333 { 334 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 335 switch (cfg->hdrtype) { 336 case 0: 337 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 338 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 339 cfg->nummaps = PCI_MAXMAPS_0; 340 break; 341 case 1: 342 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 343 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 344 cfg->nummaps = PCI_MAXMAPS_1; 345 break; 346 case 2: 347 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 348 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 349 cfg->nummaps = PCI_MAXMAPS_2; 350 break; 351 } 352 #undef REG 353 } 354 355 /* read configuration header into pcicfgregs structure */ 356 struct pci_devinfo * 357 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 358 { 359 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 360 pcicfgregs *cfg = NULL; 361 struct pci_devinfo *devlist_entry; 362 struct devlist *devlist_head; 363 364 devlist_head = &pci_devq; 365 366 devlist_entry = NULL; 367 368 if (REG(PCIR_DEVVENDOR, 4) != -1) { 369 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 370 if (devlist_entry == NULL) 371 return (NULL); 372 373 cfg = &devlist_entry->cfg; 374 375 cfg->bus = b; 376 cfg->slot = s; 377 cfg->func = f; 378 cfg->vendor = REG(PCIR_VENDOR, 2); 379 cfg->device = REG(PCIR_DEVICE, 2); 380 cfg->cmdreg = REG(PCIR_COMMAND, 2); 381 cfg->statreg = REG(PCIR_STATUS, 2); 382 cfg->baseclass = REG(PCIR_CLASS, 1); 383 cfg->subclass = REG(PCIR_SUBCLASS, 1); 384 cfg->progif = REG(PCIR_PROGIF, 1); 385 cfg->revid = REG(PCIR_REVID, 1); 386 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 387 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 388 cfg->lattimer = REG(PCIR_LATTIMER, 1); 389 cfg->intpin = REG(PCIR_INTPIN, 1); 390 cfg->intline = REG(PCIR_INTLINE, 1); 391 392 cfg->mingnt = REG(PCIR_MINGNT, 1); 393 cfg->maxlat = REG(PCIR_MAXLAT, 1); 394 395 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 396 cfg->hdrtype &= ~PCIM_MFDEV; 397 398 pci_fixancient(cfg); 399 pci_hdrtypedata(pcib, b, s, f, cfg); 400 401 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 402 pci_read_extcap(pcib, cfg); 403 404 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 405 406 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 407 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 408 devlist_entry->conf.pc_sel.pc_func = cfg->func; 409 devlist_entry->conf.pc_hdr = cfg->hdrtype; 410 411 devlist_entry->conf.pc_subvendor = cfg->subvendor; 412 devlist_entry->conf.pc_subdevice = cfg->subdevice; 413 devlist_entry->conf.pc_vendor = cfg->vendor; 414 devlist_entry->conf.pc_device = cfg->device; 415 416 devlist_entry->conf.pc_class = cfg->baseclass; 417 devlist_entry->conf.pc_subclass = cfg->subclass; 418 devlist_entry->conf.pc_progif = cfg->progif; 419 devlist_entry->conf.pc_revid = cfg->revid; 420 421 pci_numdevs++; 422 pci_generation++; 423 } 424 return (devlist_entry); 425 #undef REG 426 } 427 428 static void 429 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 430 { 431 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 432 int ptr, nextptr, ptrptr; 433 434 switch (cfg->hdrtype & PCIM_HDRTYPE) { 435 case 0: 436 ptrptr = PCIR_CAP_PTR; 437 break; 438 case 2: 439 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 440 break; 441 default: 442 return; /* no extended capabilities support */ 443 } 444 nextptr = REG(ptrptr, 1); /* sanity check? */ 445 446 /* 447 * Read capability entries. 448 */ 449 while (nextptr != 0) { 450 /* Sanity check */ 451 if (nextptr > 255) { 452 printf("illegal PCI extended capability offset %d\n", 453 nextptr); 454 return; 455 } 456 /* Find the next entry */ 457 ptr = nextptr; 458 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 459 460 /* Process this entry */ 461 switch (REG(ptr + PCICAP_ID, 1)) { 462 case PCIY_PMG: /* PCI power management */ 463 if (cfg->pp.pp_cap == 0) { 464 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 465 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 466 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 467 if ((nextptr - ptr) > PCIR_POWER_DATA) 468 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 469 } 470 break; 471 case PCIY_MSI: /* PCI MSI */ 472 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 473 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 474 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 475 else 476 cfg->msi.msi_data = PCIR_MSI_DATA; 477 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 478 PCIM_MSICTRL_MMC_MASK)>>1); 479 break; 480 case PCIY_VPD: /* PCI Vital Product Data */ 481 cfg->vpd.vpd_reg = ptr; 482 pci_read_vpd(pcib, cfg); 483 break; 484 default: 485 break; 486 } 487 } 488 /* REG use carry through to next functions */ 489 } 490 491 /* 492 * PCI Vital Product Data 493 */ 494 static uint32_t 495 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg) 496 { 497 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 498 499 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 500 501 WREG(cfg->vpd.vpd_reg + 2, reg, 2); 502 while ((REG(cfg->vpd.vpd_reg + 2, 2) & 0x8000) != 0x8000) 503 DELAY(1); /* limit looping */ 504 505 return REG(cfg->vpd.vpd_reg + 4, 4); 506 } 507 508 #if 0 509 static void 510 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 511 { 512 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 513 514 WREG(cfg->vpd.vpd_reg + 4, data, 4); 515 WREG(cfg->vpd.vpd_reg + 2, reg | 0x8000, 2); 516 while ((REG(cfg->vpd.vpd_reg + 2, 2) & 0x8000) == 0x8000) 517 DELAY(1); /* limit looping */ 518 519 return; 520 } 521 #endif 522 #undef WREG 523 524 struct vpd_readstate { 525 device_t pcib; 526 pcicfgregs *cfg; 527 uint32_t val; 528 int bytesinval; 529 int off; 530 uint8_t cksum; 531 }; 532 533 static uint8_t 534 vpd_nextbyte(struct vpd_readstate *vrs) 535 { 536 uint8_t byte; 537 538 if (vrs->bytesinval == 0) { 539 vrs->val = le32toh(pci_read_vpd_reg(vrs->pcib, vrs->cfg, 540 vrs->off)); 541 vrs->off += 4; 542 byte = vrs->val & 0xff; 543 vrs->bytesinval = 3; 544 } else { 545 vrs->val = vrs->val >> 8; 546 byte = vrs->val & 0xff; 547 vrs->bytesinval--; 548 } 549 550 vrs->cksum += byte; 551 return byte; 552 } 553 554 static void 555 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 556 { 557 struct vpd_readstate vrs; 558 int state; 559 int name; 560 int remain; 561 int end; 562 int i; 563 uint8_t byte; 564 int alloc, off; /* alloc/off for RO/W arrays */ 565 int cksumvalid; 566 int dflen; 567 568 /* init vpd reader */ 569 vrs.bytesinval = 0; 570 vrs.off = 0; 571 vrs.pcib = pcib; 572 vrs.cfg = cfg; 573 vrs.cksum = 0; 574 575 state = 0; 576 name = remain = i = 0; /* shut up stupid gcc */ 577 alloc = off = 0; /* shut up stupid gcc */ 578 dflen = 0; /* shut up stupid gcc */ 579 end = 0; 580 cksumvalid = -1; 581 for (; !end;) { 582 byte = vpd_nextbyte(&vrs); 583 #if 0 584 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \ 585 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val, 586 vrs.off, vrs.bytesinval, byte, state, remain, name, i); 587 #endif 588 switch (state) { 589 case 0: /* item name */ 590 if (byte & 0x80) { 591 remain = vpd_nextbyte(&vrs); 592 remain |= vpd_nextbyte(&vrs) << 8; 593 if (remain > (0x7f*4 - vrs.off)) { 594 end = 1; 595 printf( 596 "pci%d:%d:%d: invalid vpd data, remain %#x\n", 597 cfg->bus, cfg->slot, cfg->func, 598 remain); 599 } 600 name = byte & 0x7f; 601 } else { 602 remain = byte & 0x7; 603 name = (byte >> 3) & 0xf; 604 } 605 switch (name) { 606 case 0x2: /* String */ 607 cfg->vpd.vpd_ident = malloc(remain + 1, 608 M_DEVBUF, M_WAITOK); 609 i = 0; 610 state = 1; 611 break; 612 case 0xf: /* End */ 613 end = 1; 614 state = -1; 615 break; 616 case 0x10: /* VPD-R */ 617 alloc = 8; 618 off = 0; 619 cfg->vpd.vpd_ros = malloc(alloc * 620 sizeof *cfg->vpd.vpd_ros, M_DEVBUF, 621 M_WAITOK); 622 state = 2; 623 break; 624 case 0x11: /* VPD-W */ 625 alloc = 8; 626 off = 0; 627 cfg->vpd.vpd_w = malloc(alloc * 628 sizeof *cfg->vpd.vpd_w, M_DEVBUF, 629 M_WAITOK); 630 state = 5; 631 break; 632 default: /* XXX - unimplemented */ 633 state = 4; 634 break; 635 } 636 break; 637 638 case 1: /* Identifier String */ 639 cfg->vpd.vpd_ident[i++] = byte; 640 remain--; 641 if (remain == 0) { 642 cfg->vpd.vpd_ident[i] = '\0'; 643 state = 0; 644 } 645 break; 646 647 case 2: /* VPD-R Keyword Header */ 648 if (off == alloc) { 649 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 650 (alloc *= 2) * sizeof *cfg->vpd.vpd_ros, 651 M_DEVBUF, M_WAITOK); 652 } 653 cfg->vpd.vpd_ros[off].keyword[0] = byte; 654 cfg->vpd.vpd_ros[off].keyword[1] = vpd_nextbyte(&vrs); 655 dflen = vpd_nextbyte(&vrs); 656 if (dflen == 0 && 657 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV", 658 2) == 0) { 659 /* 660 * if this happens, we can't trust the rest 661 * of the VPD. 662 */ 663 printf("pci%d:%d:%d: bad keyword length: %d\n", 664 cfg->bus, cfg->slot, cfg->func, dflen); 665 cksumvalid = 0; 666 end = 1; 667 break; 668 } else if (dflen == 0) { 669 cfg->vpd.vpd_ros[off].value = malloc(1 * 670 sizeof *cfg->vpd.vpd_ros[off].value, 671 M_DEVBUF, M_WAITOK); 672 cfg->vpd.vpd_ros[off].value[0] = '\x00'; 673 } else 674 cfg->vpd.vpd_ros[off].value = malloc( 675 (dflen + 1) * 676 sizeof *cfg->vpd.vpd_ros[off].value, 677 M_DEVBUF, M_WAITOK); 678 remain -= 3; 679 i = 0; 680 /* keep in sync w/ state 3's transistions */ 681 if (dflen == 0 && remain == 0) 682 state = 0; 683 else if (dflen == 0) 684 state = 2; 685 else 686 state = 3; 687 break; 688 689 case 3: /* VPD-R Keyword Value */ 690 cfg->vpd.vpd_ros[off].value[i++] = byte; 691 if (strncmp(cfg->vpd.vpd_ros[off].keyword, 692 "RV", 2) == 0 && cksumvalid == -1) { 693 if (vrs.cksum == 0) 694 cksumvalid = 1; 695 else { 696 printf( 697 "pci%d:%d:%d: bad VPD cksum, remain %hhu\n", 698 cfg->bus, cfg->slot, cfg->func, 699 vrs.cksum); 700 cksumvalid = 0; 701 end = 1; 702 break; 703 } 704 } 705 dflen--; 706 remain--; 707 /* keep in sync w/ state 2's transistions */ 708 if (dflen == 0) 709 cfg->vpd.vpd_ros[off++].value[i++] = '\0'; 710 if (dflen == 0 && remain == 0) { 711 cfg->vpd.vpd_rocnt = off; 712 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 713 off * sizeof *cfg->vpd.vpd_ros, 714 M_DEVBUF, M_WAITOK); 715 state = 0; 716 } else if (dflen == 0) 717 state = 2; 718 break; 719 720 case 4: 721 remain--; 722 if (remain == 0) 723 state = 0; 724 break; 725 726 case 5: /* VPD-W Keyword Header */ 727 if (off == alloc) { 728 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 729 (alloc *= 2) * sizeof *cfg->vpd.vpd_w, 730 M_DEVBUF, M_WAITOK); 731 } 732 cfg->vpd.vpd_w[off].keyword[0] = byte; 733 cfg->vpd.vpd_w[off].keyword[1] = vpd_nextbyte(&vrs); 734 cfg->vpd.vpd_w[off].len = dflen = vpd_nextbyte(&vrs); 735 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval; 736 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) * 737 sizeof *cfg->vpd.vpd_w[off].value, 738 M_DEVBUF, M_WAITOK); 739 remain -= 3; 740 i = 0; 741 /* keep in sync w/ state 6's transistions */ 742 if (dflen == 0 && remain == 0) 743 state = 0; 744 else if (dflen == 0) 745 state = 5; 746 else 747 state = 6; 748 break; 749 750 case 6: /* VPD-W Keyword Value */ 751 cfg->vpd.vpd_w[off].value[i++] = byte; 752 dflen--; 753 remain--; 754 /* keep in sync w/ state 5's transistions */ 755 if (dflen == 0) 756 cfg->vpd.vpd_w[off++].value[i++] = '\0'; 757 if (dflen == 0 && remain == 0) { 758 cfg->vpd.vpd_wcnt = off; 759 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 760 off * sizeof *cfg->vpd.vpd_w, 761 M_DEVBUF, M_WAITOK); 762 state = 0; 763 } else if (dflen == 0) 764 state = 5; 765 break; 766 767 default: 768 printf("pci%d:%d:%d: invalid state: %d\n", 769 cfg->bus, cfg->slot, cfg->func, state); 770 end = 1; 771 break; 772 } 773 } 774 775 if (cksumvalid == 0) { 776 /* read-only data bad, clean up */ 777 for (; off; off--) 778 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF); 779 780 free(cfg->vpd.vpd_ros, M_DEVBUF); 781 cfg->vpd.vpd_ros = NULL; 782 } 783 #undef REG 784 } 785 786 int 787 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 788 { 789 struct pci_devinfo *dinfo = device_get_ivars(child); 790 pcicfgregs *cfg = &dinfo->cfg; 791 792 *identptr = cfg->vpd.vpd_ident; 793 794 if (*identptr == NULL) 795 return ENXIO; 796 797 return 0; 798 } 799 800 int 801 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 802 const char **vptr) 803 { 804 struct pci_devinfo *dinfo = device_get_ivars(child); 805 pcicfgregs *cfg = &dinfo->cfg; 806 int i; 807 808 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 809 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 810 sizeof cfg->vpd.vpd_ros[i].keyword) == 0) { 811 *vptr = cfg->vpd.vpd_ros[i].value; 812 } 813 814 if (i != cfg->vpd.vpd_rocnt) 815 return 0; 816 817 *vptr = NULL; 818 return ENXIO; 819 } 820 821 /* 822 * Return the offset in configuration space of the requested extended 823 * capability entry or 0 if the specified capability was not found. 824 */ 825 int 826 pci_find_extcap_method(device_t dev, device_t child, int capability, 827 int *capreg) 828 { 829 struct pci_devinfo *dinfo = device_get_ivars(child); 830 pcicfgregs *cfg = &dinfo->cfg; 831 u_int32_t status; 832 u_int8_t ptr; 833 834 /* 835 * Check the CAP_LIST bit of the PCI status register first. 836 */ 837 status = pci_read_config(child, PCIR_STATUS, 2); 838 if (!(status & PCIM_STATUS_CAPPRESENT)) 839 return (ENXIO); 840 841 /* 842 * Determine the start pointer of the capabilities list. 843 */ 844 switch (cfg->hdrtype & PCIM_HDRTYPE) { 845 case 0: 846 ptr = PCIR_CAP_PTR; 847 break; 848 case 2: 849 ptr = PCIR_CAP_PTR_2; 850 break; 851 default: 852 /* XXX: panic? */ 853 return (ENXIO); /* no extended capabilities support */ 854 } 855 ptr = pci_read_config(child, ptr, 1); 856 857 /* 858 * Traverse the capabilities list. 859 */ 860 while (ptr != 0) { 861 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 862 if (capreg != NULL) 863 *capreg = ptr; 864 return (0); 865 } 866 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 867 } 868 869 return (ENOENT); 870 } 871 872 /* free pcicfgregs structure and all depending data structures */ 873 874 int 875 pci_freecfg(struct pci_devinfo *dinfo) 876 { 877 struct devlist *devlist_head; 878 int i; 879 880 devlist_head = &pci_devq; 881 882 if (dinfo->cfg.vpd.vpd_reg) { 883 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF); 884 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++) 885 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF); 886 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF); 887 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++) 888 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF); 889 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF); 890 } 891 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 892 free(dinfo, M_DEVBUF); 893 894 /* increment the generation count */ 895 pci_generation++; 896 897 /* we're losing one device */ 898 pci_numdevs--; 899 return (0); 900 } 901 902 /* 903 * PCI power manangement 904 */ 905 int 906 pci_set_powerstate_method(device_t dev, device_t child, int state) 907 { 908 struct pci_devinfo *dinfo = device_get_ivars(child); 909 pcicfgregs *cfg = &dinfo->cfg; 910 uint16_t status; 911 int result, oldstate, highest, delay; 912 913 if (cfg->pp.pp_cap == 0) 914 return (EOPNOTSUPP); 915 916 /* 917 * Optimize a no state change request away. While it would be OK to 918 * write to the hardware in theory, some devices have shown odd 919 * behavior when going from D3 -> D3. 920 */ 921 oldstate = pci_get_powerstate(child); 922 if (oldstate == state) 923 return (0); 924 925 /* 926 * The PCI power management specification states that after a state 927 * transition between PCI power states, system software must 928 * guarantee a minimal delay before the function accesses the device. 929 * Compute the worst case delay that we need to guarantee before we 930 * access the device. Many devices will be responsive much more 931 * quickly than this delay, but there are some that don't respond 932 * instantly to state changes. Transitions to/from D3 state require 933 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 934 * is done below with DELAY rather than a sleeper function because 935 * this function can be called from contexts where we cannot sleep. 936 */ 937 highest = (oldstate > state) ? oldstate : state; 938 if (highest == PCI_POWERSTATE_D3) 939 delay = 10000; 940 else if (highest == PCI_POWERSTATE_D2) 941 delay = 200; 942 else 943 delay = 0; 944 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 945 & ~PCIM_PSTAT_DMASK; 946 result = 0; 947 switch (state) { 948 case PCI_POWERSTATE_D0: 949 status |= PCIM_PSTAT_D0; 950 break; 951 case PCI_POWERSTATE_D1: 952 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 953 return (EOPNOTSUPP); 954 status |= PCIM_PSTAT_D1; 955 break; 956 case PCI_POWERSTATE_D2: 957 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 958 return (EOPNOTSUPP); 959 status |= PCIM_PSTAT_D2; 960 break; 961 case PCI_POWERSTATE_D3: 962 status |= PCIM_PSTAT_D3; 963 break; 964 default: 965 return (EINVAL); 966 } 967 968 if (bootverbose) 969 printf( 970 "pci%d:%d:%d: Transition from D%d to D%d\n", 971 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 972 oldstate, state); 973 974 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 975 if (delay) 976 DELAY(delay); 977 return (0); 978 } 979 980 int 981 pci_get_powerstate_method(device_t dev, device_t child) 982 { 983 struct pci_devinfo *dinfo = device_get_ivars(child); 984 pcicfgregs *cfg = &dinfo->cfg; 985 uint16_t status; 986 int result; 987 988 if (cfg->pp.pp_cap != 0) { 989 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 990 switch (status & PCIM_PSTAT_DMASK) { 991 case PCIM_PSTAT_D0: 992 result = PCI_POWERSTATE_D0; 993 break; 994 case PCIM_PSTAT_D1: 995 result = PCI_POWERSTATE_D1; 996 break; 997 case PCIM_PSTAT_D2: 998 result = PCI_POWERSTATE_D2; 999 break; 1000 case PCIM_PSTAT_D3: 1001 result = PCI_POWERSTATE_D3; 1002 break; 1003 default: 1004 result = PCI_POWERSTATE_UNKNOWN; 1005 break; 1006 } 1007 } else { 1008 /* No support, device is always at D0 */ 1009 result = PCI_POWERSTATE_D0; 1010 } 1011 return (result); 1012 } 1013 1014 /* 1015 * Some convenience functions for PCI device drivers. 1016 */ 1017 1018 static __inline void 1019 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 1020 { 1021 uint16_t command; 1022 1023 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1024 command |= bit; 1025 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 1026 } 1027 1028 static __inline void 1029 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 1030 { 1031 uint16_t command; 1032 1033 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1034 command &= ~bit; 1035 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 1036 } 1037 1038 int 1039 pci_enable_busmaster_method(device_t dev, device_t child) 1040 { 1041 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 1042 return (0); 1043 } 1044 1045 int 1046 pci_disable_busmaster_method(device_t dev, device_t child) 1047 { 1048 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 1049 return (0); 1050 } 1051 1052 int 1053 pci_enable_io_method(device_t dev, device_t child, int space) 1054 { 1055 uint16_t command; 1056 uint16_t bit; 1057 char *error; 1058 1059 bit = 0; 1060 error = NULL; 1061 1062 switch(space) { 1063 case SYS_RES_IOPORT: 1064 bit = PCIM_CMD_PORTEN; 1065 error = "port"; 1066 break; 1067 case SYS_RES_MEMORY: 1068 bit = PCIM_CMD_MEMEN; 1069 error = "memory"; 1070 break; 1071 default: 1072 return (EINVAL); 1073 } 1074 pci_set_command_bit(dev, child, bit); 1075 /* Some devices seem to need a brief stall here, what do to? */ 1076 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1077 if (command & bit) 1078 return (0); 1079 device_printf(child, "failed to enable %s mapping!\n", error); 1080 return (ENXIO); 1081 } 1082 1083 int 1084 pci_disable_io_method(device_t dev, device_t child, int space) 1085 { 1086 uint16_t command; 1087 uint16_t bit; 1088 char *error; 1089 1090 bit = 0; 1091 error = NULL; 1092 1093 switch(space) { 1094 case SYS_RES_IOPORT: 1095 bit = PCIM_CMD_PORTEN; 1096 error = "port"; 1097 break; 1098 case SYS_RES_MEMORY: 1099 bit = PCIM_CMD_MEMEN; 1100 error = "memory"; 1101 break; 1102 default: 1103 return (EINVAL); 1104 } 1105 pci_clear_command_bit(dev, child, bit); 1106 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1107 if (command & bit) { 1108 device_printf(child, "failed to disable %s mapping!\n", error); 1109 return (ENXIO); 1110 } 1111 return (0); 1112 } 1113 1114 /* 1115 * New style pci driver. Parent device is either a pci-host-bridge or a 1116 * pci-pci-bridge. Both kinds are represented by instances of pcib. 1117 */ 1118 1119 void 1120 pci_print_verbose(struct pci_devinfo *dinfo) 1121 { 1122 int i; 1123 1124 if (bootverbose) { 1125 pcicfgregs *cfg = &dinfo->cfg; 1126 1127 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 1128 cfg->vendor, cfg->device, cfg->revid); 1129 printf("\tbus=%d, slot=%d, func=%d\n", 1130 cfg->bus, cfg->slot, cfg->func); 1131 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 1132 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 1133 cfg->mfdev); 1134 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 1135 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 1136 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 1137 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 1138 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 1139 if (cfg->intpin > 0) 1140 printf("\tintpin=%c, irq=%d\n", 1141 cfg->intpin +'a' -1, cfg->intline); 1142 if (cfg->pp.pp_cap) { 1143 uint16_t status; 1144 1145 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 1146 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 1147 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 1148 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 1149 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 1150 status & PCIM_PSTAT_DMASK); 1151 } 1152 if (cfg->vpd.vpd_reg) { 1153 printf("\tVPD Ident: %s\n", cfg->vpd.vpd_ident); 1154 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) { 1155 struct vpd_readonly *vrop; 1156 vrop = &cfg->vpd.vpd_ros[i]; 1157 if (strncmp("CP", vrop->keyword, 2) == 0) 1158 printf("\tCP: id %d, BAR%d, off %#x\n", 1159 vrop->value[0], vrop->value[1], 1160 le16toh( 1161 *(uint16_t *)&vrop->value[2])); 1162 else if (strncmp("RV", vrop->keyword, 2) == 0) 1163 printf("\tRV: %#hhx\n", vrop->value[0]); 1164 else 1165 printf("\t%.2s: %s\n", vrop->keyword, 1166 vrop->value); 1167 } 1168 for (i = 0; i < cfg->vpd.vpd_wcnt; i++) { 1169 struct vpd_write *vwp; 1170 vwp = &cfg->vpd.vpd_w[i]; 1171 if (strncmp("RW", vwp->keyword, 2) != 0) 1172 printf("\t%.2s(%#x-%#x): %s\n", 1173 vwp->keyword, vwp->start, 1174 vwp->start + vwp->len, vwp->value); 1175 } 1176 } 1177 if (cfg->msi.msi_data) { 1178 int ctrl; 1179 1180 ctrl = cfg->msi.msi_ctrl; 1181 printf("\tMSI supports %d message%s%s%s\n", 1182 cfg->msi.msi_msgnum, 1183 (cfg->msi.msi_msgnum == 1) ? "" : "s", 1184 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 1185 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 1186 } 1187 } 1188 } 1189 1190 static int 1191 pci_porten(device_t pcib, int b, int s, int f) 1192 { 1193 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1194 & PCIM_CMD_PORTEN) != 0; 1195 } 1196 1197 static int 1198 pci_memen(device_t pcib, int b, int s, int f) 1199 { 1200 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1201 & PCIM_CMD_MEMEN) != 0; 1202 } 1203 1204 /* 1205 * Add a resource based on a pci map register. Return 1 if the map 1206 * register is a 32bit map register or 2 if it is a 64bit register. 1207 */ 1208 static int 1209 pci_add_map(device_t pcib, device_t bus, device_t dev, 1210 int b, int s, int f, int reg, struct resource_list *rl, int force, 1211 int prefetch) 1212 { 1213 uint32_t map; 1214 uint64_t base; 1215 uint64_t start, end, count; 1216 uint8_t ln2size; 1217 uint8_t ln2range; 1218 uint32_t testval; 1219 uint16_t cmd; 1220 int type; 1221 int barlen; 1222 struct resource *res; 1223 1224 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1225 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 1226 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1227 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 1228 1229 if (pci_maptype(map) & PCI_MAPMEM) 1230 type = SYS_RES_MEMORY; 1231 else 1232 type = SYS_RES_IOPORT; 1233 ln2size = pci_mapsize(testval); 1234 ln2range = pci_maprange(testval); 1235 base = pci_mapbase(map); 1236 barlen = ln2range == 64 ? 2 : 1; 1237 1238 /* 1239 * For I/O registers, if bottom bit is set, and the next bit up 1240 * isn't clear, we know we have a BAR that doesn't conform to the 1241 * spec, so ignore it. Also, sanity check the size of the data 1242 * areas to the type of memory involved. Memory must be at least 1243 * 16 bytes in size, while I/O ranges must be at least 4. 1244 */ 1245 if ((testval & 0x1) == 0x1 && 1246 (testval & 0x2) != 0) 1247 return (barlen); 1248 if ((type == SYS_RES_MEMORY && ln2size < 4) || 1249 (type == SYS_RES_IOPORT && ln2size < 2)) 1250 return (barlen); 1251 1252 if (ln2range == 64) 1253 /* Read the other half of a 64bit map register */ 1254 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 1255 1256 if (bootverbose) { 1257 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 1258 reg, pci_maptype(map), ln2range, 1259 (unsigned int) base, ln2size); 1260 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1261 printf(", port disabled\n"); 1262 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1263 printf(", memory disabled\n"); 1264 else 1265 printf(", enabled\n"); 1266 } 1267 1268 /* 1269 * If base is 0, then we have problems. It is best to ignore 1270 * such entries for the moment. These will be allocated later if 1271 * the driver specifically requests them. However, some 1272 * removable busses look better when all resources are allocated, 1273 * so allow '0' to be overriden. 1274 * 1275 * Similarly treat maps whose values is the same as the test value 1276 * read back. These maps have had all f's written to them by the 1277 * BIOS in an attempt to disable the resources. 1278 */ 1279 if (!force && (base == 0 || map == testval)) 1280 return (barlen); 1281 1282 /* 1283 * This code theoretically does the right thing, but has 1284 * undesirable side effects in some cases where peripherals 1285 * respond oddly to having these bits enabled. Let the user 1286 * be able to turn them off (since pci_enable_io_modes is 1 by 1287 * default). 1288 */ 1289 if (pci_enable_io_modes) { 1290 /* Turn on resources that have been left off by a lazy BIOS */ 1291 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 1292 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1293 cmd |= PCIM_CMD_PORTEN; 1294 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1295 } 1296 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 1297 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1298 cmd |= PCIM_CMD_MEMEN; 1299 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1300 } 1301 } else { 1302 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1303 return (barlen); 1304 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1305 return (barlen); 1306 } 1307 1308 count = 1 << ln2size; 1309 if (base == 0 || base == pci_mapbase(testval)) { 1310 start = 0; /* Let the parent deside */ 1311 end = ~0ULL; 1312 } else { 1313 start = base; 1314 end = base + (1 << ln2size) - 1; 1315 } 1316 resource_list_add(rl, type, reg, start, end, count); 1317 1318 /* 1319 * Not quite sure what to do on failure of allocating the resource 1320 * since I can postulate several right answers. 1321 */ 1322 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 1323 prefetch ? RF_PREFETCHABLE : 0); 1324 if (res != NULL) 1325 pci_write_config(dev, reg, rman_get_start(res), 4); 1326 return (barlen); 1327 } 1328 1329 /* 1330 * For ATA devices we need to decide early what addressing mode to use. 1331 * Legacy demands that the primary and secondary ATA ports sits on the 1332 * same addresses that old ISA hardware did. This dictates that we use 1333 * those addresses and ignore the BAR's if we cannot set PCI native 1334 * addressing mode. 1335 */ 1336 static void 1337 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 1338 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask) 1339 { 1340 int rid, type, progif; 1341 #if 0 1342 /* if this device supports PCI native addressing use it */ 1343 progif = pci_read_config(dev, PCIR_PROGIF, 1); 1344 if ((progif & 0x8a) == 0x8a) { 1345 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 1346 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 1347 printf("Trying ATA native PCI addressing mode\n"); 1348 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 1349 } 1350 } 1351 #endif 1352 progif = pci_read_config(dev, PCIR_PROGIF, 1); 1353 type = SYS_RES_IOPORT; 1354 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 1355 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force, 1356 prefetchmask & (1 << 0)); 1357 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force, 1358 prefetchmask & (1 << 1)); 1359 } else { 1360 rid = PCIR_BAR(0); 1361 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 1362 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8, 1363 0); 1364 rid = PCIR_BAR(1); 1365 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 1366 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1, 1367 0); 1368 } 1369 if (progif & PCIP_STORAGE_IDE_MODESEC) { 1370 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force, 1371 prefetchmask & (1 << 2)); 1372 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force, 1373 prefetchmask & (1 << 3)); 1374 } else { 1375 rid = PCIR_BAR(2); 1376 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 1377 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8, 1378 0); 1379 rid = PCIR_BAR(3); 1380 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 1381 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1, 1382 0); 1383 } 1384 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force, 1385 prefetchmask & (1 << 4)); 1386 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force, 1387 prefetchmask & (1 << 5)); 1388 } 1389 1390 static void 1391 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 1392 { 1393 struct pci_devinfo *dinfo = device_get_ivars(dev); 1394 pcicfgregs *cfg = &dinfo->cfg; 1395 char tunable_name[64]; 1396 int irq; 1397 1398 /* Has to have an intpin to have an interrupt. */ 1399 if (cfg->intpin == 0) 1400 return; 1401 1402 /* Let the user override the IRQ with a tunable. */ 1403 irq = PCI_INVALID_IRQ; 1404 snprintf(tunable_name, sizeof(tunable_name), "hw.pci%d.%d.INT%c.irq", 1405 cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 1406 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 1407 irq = PCI_INVALID_IRQ; 1408 1409 /* 1410 * If we didn't get an IRQ via the tunable, then we either use the 1411 * IRQ value in the intline register or we ask the bus to route an 1412 * interrupt for us. If force_route is true, then we only use the 1413 * value in the intline register if the bus was unable to assign an 1414 * IRQ. 1415 */ 1416 if (!PCI_INTERRUPT_VALID(irq)) { 1417 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 1418 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 1419 if (!PCI_INTERRUPT_VALID(irq)) 1420 irq = cfg->intline; 1421 } 1422 1423 /* If after all that we don't have an IRQ, just bail. */ 1424 if (!PCI_INTERRUPT_VALID(irq)) 1425 return; 1426 1427 /* Update the config register if it changed. */ 1428 if (irq != cfg->intline) { 1429 cfg->intline = irq; 1430 pci_write_config(dev, PCIR_INTLINE, irq, 1); 1431 } 1432 1433 /* Add this IRQ as rid 0 interrupt resource. */ 1434 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 1435 } 1436 1437 void 1438 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 1439 { 1440 device_t pcib; 1441 struct pci_devinfo *dinfo = device_get_ivars(dev); 1442 pcicfgregs *cfg = &dinfo->cfg; 1443 struct resource_list *rl = &dinfo->resources; 1444 struct pci_quirk *q; 1445 int b, i, f, s; 1446 1447 pcib = device_get_parent(bus); 1448 1449 b = cfg->bus; 1450 s = cfg->slot; 1451 f = cfg->func; 1452 1453 /* ATA devices needs special map treatment */ 1454 if ((pci_get_class(dev) == PCIC_STORAGE) && 1455 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 1456 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 1457 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask); 1458 else 1459 for (i = 0; i < cfg->nummaps;) 1460 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 1461 rl, force, prefetchmask & (1 << i)); 1462 1463 /* 1464 * Add additional, quirked resources. 1465 */ 1466 for (q = &pci_quirks[0]; q->devid; q++) { 1467 if (q->devid == ((cfg->device << 16) | cfg->vendor) 1468 && q->type == PCI_QUIRK_MAP_REG) 1469 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl, 1470 force, 0); 1471 } 1472 1473 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 1474 #ifdef __PCI_REROUTE_INTERRUPT 1475 /* 1476 * Try to re-route interrupts. Sometimes the BIOS or 1477 * firmware may leave bogus values in these registers. 1478 * If the re-route fails, then just stick with what we 1479 * have. 1480 */ 1481 pci_assign_interrupt(bus, dev, 1); 1482 #else 1483 pci_assign_interrupt(bus, dev, 0); 1484 #endif 1485 } 1486 } 1487 1488 void 1489 pci_add_children(device_t dev, int busno, size_t dinfo_size) 1490 { 1491 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 1492 device_t pcib = device_get_parent(dev); 1493 struct pci_devinfo *dinfo; 1494 int maxslots; 1495 int s, f, pcifunchigh; 1496 uint8_t hdrtype; 1497 1498 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 1499 ("dinfo_size too small")); 1500 maxslots = PCIB_MAXSLOTS(pcib); 1501 for (s = 0; s <= maxslots; s++) { 1502 pcifunchigh = 0; 1503 f = 0; 1504 DELAY(1); 1505 hdrtype = REG(PCIR_HDRTYPE, 1); 1506 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 1507 continue; 1508 if (hdrtype & PCIM_MFDEV) 1509 pcifunchigh = PCI_FUNCMAX; 1510 for (f = 0; f <= pcifunchigh; f++) { 1511 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 1512 if (dinfo != NULL) { 1513 pci_add_child(dev, dinfo); 1514 } 1515 } 1516 } 1517 #undef REG 1518 } 1519 1520 void 1521 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1522 { 1523 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1524 device_set_ivars(dinfo->cfg.dev, dinfo); 1525 resource_list_init(&dinfo->resources); 1526 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 1527 pci_cfg_restore(dinfo->cfg.dev, dinfo); 1528 pci_print_verbose(dinfo); 1529 pci_add_resources(bus, dinfo->cfg.dev, 0, 0); 1530 } 1531 1532 static int 1533 pci_probe(device_t dev) 1534 { 1535 1536 device_set_desc(dev, "PCI bus"); 1537 1538 /* Allow other subclasses to override this driver. */ 1539 return (-1000); 1540 } 1541 1542 static int 1543 pci_attach(device_t dev) 1544 { 1545 int busno; 1546 1547 /* 1548 * Since there can be multiple independantly numbered PCI 1549 * busses on systems with multiple PCI domains, we can't use 1550 * the unit number to decide which bus we are probing. We ask 1551 * the parent pcib what our bus number is. 1552 */ 1553 busno = pcib_get_bus(dev); 1554 if (bootverbose) 1555 device_printf(dev, "physical bus=%d\n", busno); 1556 1557 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1558 1559 return (bus_generic_attach(dev)); 1560 } 1561 1562 int 1563 pci_suspend(device_t dev) 1564 { 1565 int dstate, error, i, numdevs; 1566 device_t acpi_dev, child, *devlist; 1567 struct pci_devinfo *dinfo; 1568 1569 /* 1570 * Save the PCI configuration space for each child and set the 1571 * device in the appropriate power state for this sleep state. 1572 */ 1573 acpi_dev = NULL; 1574 if (pci_do_power_resume) 1575 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1576 device_get_children(dev, &devlist, &numdevs); 1577 for (i = 0; i < numdevs; i++) { 1578 child = devlist[i]; 1579 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1580 pci_cfg_save(child, dinfo, 0); 1581 } 1582 1583 /* Suspend devices before potentially powering them down. */ 1584 error = bus_generic_suspend(dev); 1585 if (error) { 1586 free(devlist, M_TEMP); 1587 return (error); 1588 } 1589 1590 /* 1591 * Always set the device to D3. If ACPI suggests a different 1592 * power state, use it instead. If ACPI is not present, the 1593 * firmware is responsible for managing device power. Skip 1594 * children who aren't attached since they are powered down 1595 * separately. Only manage type 0 devices for now. 1596 */ 1597 for (i = 0; acpi_dev && i < numdevs; i++) { 1598 child = devlist[i]; 1599 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1600 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 1601 dstate = PCI_POWERSTATE_D3; 1602 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 1603 pci_set_powerstate(child, dstate); 1604 } 1605 } 1606 free(devlist, M_TEMP); 1607 return (0); 1608 } 1609 1610 int 1611 pci_resume(device_t dev) 1612 { 1613 int i, numdevs; 1614 device_t acpi_dev, child, *devlist; 1615 struct pci_devinfo *dinfo; 1616 1617 /* 1618 * Set each child to D0 and restore its PCI configuration space. 1619 */ 1620 acpi_dev = NULL; 1621 if (pci_do_power_resume) 1622 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1623 device_get_children(dev, &devlist, &numdevs); 1624 for (i = 0; i < numdevs; i++) { 1625 /* 1626 * Notify ACPI we're going to D0 but ignore the result. If 1627 * ACPI is not present, the firmware is responsible for 1628 * managing device power. Only manage type 0 devices for now. 1629 */ 1630 child = devlist[i]; 1631 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1632 if (acpi_dev && device_is_attached(child) && 1633 dinfo->cfg.hdrtype == 0) { 1634 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 1635 pci_set_powerstate(child, PCI_POWERSTATE_D0); 1636 } 1637 1638 /* Now the device is powered up, restore its config space. */ 1639 pci_cfg_restore(child, dinfo); 1640 } 1641 free(devlist, M_TEMP); 1642 return (bus_generic_resume(dev)); 1643 } 1644 1645 static void 1646 pci_load_vendor_data(void) 1647 { 1648 caddr_t vendordata, info; 1649 1650 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1651 info = preload_search_info(vendordata, MODINFO_ADDR); 1652 pci_vendordata = *(char **)info; 1653 info = preload_search_info(vendordata, MODINFO_SIZE); 1654 pci_vendordata_size = *(size_t *)info; 1655 /* terminate the database */ 1656 pci_vendordata[pci_vendordata_size] = '\n'; 1657 } 1658 } 1659 1660 void 1661 pci_driver_added(device_t dev, driver_t *driver) 1662 { 1663 int numdevs; 1664 device_t *devlist; 1665 device_t child; 1666 struct pci_devinfo *dinfo; 1667 int i; 1668 1669 if (bootverbose) 1670 device_printf(dev, "driver added\n"); 1671 DEVICE_IDENTIFY(driver, dev); 1672 device_get_children(dev, &devlist, &numdevs); 1673 for (i = 0; i < numdevs; i++) { 1674 child = devlist[i]; 1675 if (device_get_state(child) != DS_NOTPRESENT) 1676 continue; 1677 dinfo = device_get_ivars(child); 1678 pci_print_verbose(dinfo); 1679 if (bootverbose) 1680 printf("pci%d:%d:%d: reprobing on driver added\n", 1681 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1682 pci_cfg_restore(child, dinfo); 1683 if (device_probe_and_attach(child) != 0) 1684 pci_cfg_save(child, dinfo, 1); 1685 } 1686 free(devlist, M_TEMP); 1687 } 1688 1689 int 1690 pci_print_child(device_t dev, device_t child) 1691 { 1692 struct pci_devinfo *dinfo; 1693 struct resource_list *rl; 1694 int retval = 0; 1695 1696 dinfo = device_get_ivars(child); 1697 rl = &dinfo->resources; 1698 1699 retval += bus_print_child_header(dev, child); 1700 1701 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1702 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1703 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1704 if (device_get_flags(dev)) 1705 retval += printf(" flags %#x", device_get_flags(dev)); 1706 1707 retval += printf(" at device %d.%d", pci_get_slot(child), 1708 pci_get_function(child)); 1709 1710 retval += bus_print_child_footer(dev, child); 1711 1712 return (retval); 1713 } 1714 1715 static struct 1716 { 1717 int class; 1718 int subclass; 1719 char *desc; 1720 } pci_nomatch_tab[] = { 1721 {PCIC_OLD, -1, "old"}, 1722 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1723 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1724 {PCIC_STORAGE, -1, "mass storage"}, 1725 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1726 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1727 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1728 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1729 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1730 {PCIC_NETWORK, -1, "network"}, 1731 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1732 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1733 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1734 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1735 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"}, 1736 {PCIC_DISPLAY, -1, "display"}, 1737 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1738 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1739 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"}, 1740 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1741 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1742 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1743 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"}, 1744 {PCIC_MEMORY, -1, "memory"}, 1745 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1746 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1747 {PCIC_BRIDGE, -1, "bridge"}, 1748 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1749 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1750 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1751 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1752 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1753 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1754 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1755 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1756 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"}, 1757 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1758 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1759 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1760 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"}, 1761 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"}, 1762 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1763 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1764 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1765 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1766 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1767 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"}, 1768 {PCIC_INPUTDEV, -1, "input device"}, 1769 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1770 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1771 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1772 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"}, 1773 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"}, 1774 {PCIC_DOCKING, -1, "docking station"}, 1775 {PCIC_PROCESSOR, -1, "processor"}, 1776 {PCIC_SERIALBUS, -1, "serial bus"}, 1777 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1778 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1779 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1780 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1781 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1782 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1783 {PCIC_WIRELESS, -1, "wireless controller"}, 1784 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"}, 1785 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"}, 1786 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"}, 1787 {PCIC_INTELLIIO, -1, "intelligent I/O controller"}, 1788 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"}, 1789 {PCIC_SATCOM, -1, "satellite communication"}, 1790 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"}, 1791 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"}, 1792 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"}, 1793 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"}, 1794 {PCIC_CRYPTO, -1, "encrypt/decrypt"}, 1795 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"}, 1796 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"}, 1797 {PCIC_DASP, -1, "dasp"}, 1798 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"}, 1799 {0, 0, NULL} 1800 }; 1801 1802 void 1803 pci_probe_nomatch(device_t dev, device_t child) 1804 { 1805 int i; 1806 char *cp, *scp, *device; 1807 1808 /* 1809 * Look for a listing for this device in a loaded device database. 1810 */ 1811 if ((device = pci_describe_device(child)) != NULL) { 1812 device_printf(dev, "<%s>", device); 1813 free(device, M_DEVBUF); 1814 } else { 1815 /* 1816 * Scan the class/subclass descriptions for a general 1817 * description. 1818 */ 1819 cp = "unknown"; 1820 scp = NULL; 1821 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1822 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1823 if (pci_nomatch_tab[i].subclass == -1) { 1824 cp = pci_nomatch_tab[i].desc; 1825 } else if (pci_nomatch_tab[i].subclass == 1826 pci_get_subclass(child)) { 1827 scp = pci_nomatch_tab[i].desc; 1828 } 1829 } 1830 } 1831 device_printf(dev, "<%s%s%s>", 1832 cp ? cp : "", 1833 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1834 scp ? scp : ""); 1835 } 1836 printf(" at device %d.%d (no driver attached)\n", 1837 pci_get_slot(child), pci_get_function(child)); 1838 if (pci_do_power_nodriver) 1839 pci_cfg_save(child, 1840 (struct pci_devinfo *) device_get_ivars(child), 1); 1841 return; 1842 } 1843 1844 /* 1845 * Parse the PCI device database, if loaded, and return a pointer to a 1846 * description of the device. 1847 * 1848 * The database is flat text formatted as follows: 1849 * 1850 * Any line not in a valid format is ignored. 1851 * Lines are terminated with newline '\n' characters. 1852 * 1853 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1854 * the vendor name. 1855 * 1856 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1857 * - devices cannot be listed without a corresponding VENDOR line. 1858 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1859 * another TAB, then the device name. 1860 */ 1861 1862 /* 1863 * Assuming (ptr) points to the beginning of a line in the database, 1864 * return the vendor or device and description of the next entry. 1865 * The value of (vendor) or (device) inappropriate for the entry type 1866 * is set to -1. Returns nonzero at the end of the database. 1867 * 1868 * Note that this is slightly unrobust in the face of corrupt data; 1869 * we attempt to safeguard against this by spamming the end of the 1870 * database with a newline when we initialise. 1871 */ 1872 static int 1873 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1874 { 1875 char *cp = *ptr; 1876 int left; 1877 1878 *device = -1; 1879 *vendor = -1; 1880 **desc = '\0'; 1881 for (;;) { 1882 left = pci_vendordata_size - (cp - pci_vendordata); 1883 if (left <= 0) { 1884 *ptr = cp; 1885 return(1); 1886 } 1887 1888 /* vendor entry? */ 1889 if (*cp != '\t' && 1890 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1891 break; 1892 /* device entry? */ 1893 if (*cp == '\t' && 1894 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1895 break; 1896 1897 /* skip to next line */ 1898 while (*cp != '\n' && left > 0) { 1899 cp++; 1900 left--; 1901 } 1902 if (*cp == '\n') { 1903 cp++; 1904 left--; 1905 } 1906 } 1907 /* skip to next line */ 1908 while (*cp != '\n' && left > 0) { 1909 cp++; 1910 left--; 1911 } 1912 if (*cp == '\n' && left > 0) 1913 cp++; 1914 *ptr = cp; 1915 return(0); 1916 } 1917 1918 static char * 1919 pci_describe_device(device_t dev) 1920 { 1921 int vendor, device; 1922 char *desc, *vp, *dp, *line; 1923 1924 desc = vp = dp = NULL; 1925 1926 /* 1927 * If we have no vendor data, we can't do anything. 1928 */ 1929 if (pci_vendordata == NULL) 1930 goto out; 1931 1932 /* 1933 * Scan the vendor data looking for this device 1934 */ 1935 line = pci_vendordata; 1936 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1937 goto out; 1938 for (;;) { 1939 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1940 goto out; 1941 if (vendor == pci_get_vendor(dev)) 1942 break; 1943 } 1944 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1945 goto out; 1946 for (;;) { 1947 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1948 *dp = 0; 1949 break; 1950 } 1951 if (vendor != -1) { 1952 *dp = 0; 1953 break; 1954 } 1955 if (device == pci_get_device(dev)) 1956 break; 1957 } 1958 if (dp[0] == '\0') 1959 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1960 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1961 NULL) 1962 sprintf(desc, "%s, %s", vp, dp); 1963 out: 1964 if (vp != NULL) 1965 free(vp, M_DEVBUF); 1966 if (dp != NULL) 1967 free(dp, M_DEVBUF); 1968 return(desc); 1969 } 1970 1971 int 1972 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1973 { 1974 struct pci_devinfo *dinfo; 1975 pcicfgregs *cfg; 1976 1977 dinfo = device_get_ivars(child); 1978 cfg = &dinfo->cfg; 1979 1980 switch (which) { 1981 case PCI_IVAR_ETHADDR: 1982 /* 1983 * The generic accessor doesn't deal with failure, so 1984 * we set the return value, then return an error. 1985 */ 1986 *((uint8_t **) result) = NULL; 1987 return (EINVAL); 1988 case PCI_IVAR_SUBVENDOR: 1989 *result = cfg->subvendor; 1990 break; 1991 case PCI_IVAR_SUBDEVICE: 1992 *result = cfg->subdevice; 1993 break; 1994 case PCI_IVAR_VENDOR: 1995 *result = cfg->vendor; 1996 break; 1997 case PCI_IVAR_DEVICE: 1998 *result = cfg->device; 1999 break; 2000 case PCI_IVAR_DEVID: 2001 *result = (cfg->device << 16) | cfg->vendor; 2002 break; 2003 case PCI_IVAR_CLASS: 2004 *result = cfg->baseclass; 2005 break; 2006 case PCI_IVAR_SUBCLASS: 2007 *result = cfg->subclass; 2008 break; 2009 case PCI_IVAR_PROGIF: 2010 *result = cfg->progif; 2011 break; 2012 case PCI_IVAR_REVID: 2013 *result = cfg->revid; 2014 break; 2015 case PCI_IVAR_INTPIN: 2016 *result = cfg->intpin; 2017 break; 2018 case PCI_IVAR_IRQ: 2019 *result = cfg->intline; 2020 break; 2021 case PCI_IVAR_BUS: 2022 *result = cfg->bus; 2023 break; 2024 case PCI_IVAR_SLOT: 2025 *result = cfg->slot; 2026 break; 2027 case PCI_IVAR_FUNCTION: 2028 *result = cfg->func; 2029 break; 2030 case PCI_IVAR_CMDREG: 2031 *result = cfg->cmdreg; 2032 break; 2033 case PCI_IVAR_CACHELNSZ: 2034 *result = cfg->cachelnsz; 2035 break; 2036 case PCI_IVAR_MINGNT: 2037 *result = cfg->mingnt; 2038 break; 2039 case PCI_IVAR_MAXLAT: 2040 *result = cfg->maxlat; 2041 break; 2042 case PCI_IVAR_LATTIMER: 2043 *result = cfg->lattimer; 2044 break; 2045 default: 2046 return (ENOENT); 2047 } 2048 return (0); 2049 } 2050 2051 int 2052 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 2053 { 2054 struct pci_devinfo *dinfo; 2055 2056 dinfo = device_get_ivars(child); 2057 2058 switch (which) { 2059 case PCI_IVAR_INTPIN: 2060 dinfo->cfg.intpin = value; 2061 return (0); 2062 case PCI_IVAR_ETHADDR: 2063 case PCI_IVAR_SUBVENDOR: 2064 case PCI_IVAR_SUBDEVICE: 2065 case PCI_IVAR_VENDOR: 2066 case PCI_IVAR_DEVICE: 2067 case PCI_IVAR_DEVID: 2068 case PCI_IVAR_CLASS: 2069 case PCI_IVAR_SUBCLASS: 2070 case PCI_IVAR_PROGIF: 2071 case PCI_IVAR_REVID: 2072 case PCI_IVAR_IRQ: 2073 case PCI_IVAR_BUS: 2074 case PCI_IVAR_SLOT: 2075 case PCI_IVAR_FUNCTION: 2076 return (EINVAL); /* disallow for now */ 2077 2078 default: 2079 return (ENOENT); 2080 } 2081 } 2082 2083 2084 #include "opt_ddb.h" 2085 #ifdef DDB 2086 #include <ddb/ddb.h> 2087 #include <sys/cons.h> 2088 2089 /* 2090 * List resources based on pci map registers, used for within ddb 2091 */ 2092 2093 DB_SHOW_COMMAND(pciregs, db_pci_dump) 2094 { 2095 struct pci_devinfo *dinfo; 2096 struct devlist *devlist_head; 2097 struct pci_conf *p; 2098 const char *name; 2099 int i, error, none_count; 2100 2101 none_count = 0; 2102 /* get the head of the device queue */ 2103 devlist_head = &pci_devq; 2104 2105 /* 2106 * Go through the list of devices and print out devices 2107 */ 2108 for (error = 0, i = 0, 2109 dinfo = STAILQ_FIRST(devlist_head); 2110 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 2111 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 2112 2113 /* Populate pd_name and pd_unit */ 2114 name = NULL; 2115 if (dinfo->cfg.dev) 2116 name = device_get_name(dinfo->cfg.dev); 2117 2118 p = &dinfo->conf; 2119 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 2120 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 2121 (name && *name) ? name : "none", 2122 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 2123 none_count++, 2124 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 2125 p->pc_sel.pc_func, (p->pc_class << 16) | 2126 (p->pc_subclass << 8) | p->pc_progif, 2127 (p->pc_subdevice << 16) | p->pc_subvendor, 2128 (p->pc_device << 16) | p->pc_vendor, 2129 p->pc_revid, p->pc_hdr); 2130 } 2131 } 2132 #endif /* DDB */ 2133 2134 static struct resource * 2135 pci_alloc_map(device_t dev, device_t child, int type, int *rid, 2136 u_long start, u_long end, u_long count, u_int flags) 2137 { 2138 struct pci_devinfo *dinfo = device_get_ivars(child); 2139 struct resource_list *rl = &dinfo->resources; 2140 struct resource_list_entry *rle; 2141 struct resource *res; 2142 uint32_t map, testval; 2143 int mapsize; 2144 2145 /* 2146 * Weed out the bogons, and figure out how large the BAR/map 2147 * is. Bars that read back 0 here are bogus and unimplemented. 2148 * Note: atapci in legacy mode are special and handled elsewhere 2149 * in the code. If you have a atapci device in legacy mode and 2150 * it fails here, that other code is broken. 2151 */ 2152 res = NULL; 2153 map = pci_read_config(child, *rid, 4); 2154 pci_write_config(child, *rid, 0xffffffff, 4); 2155 testval = pci_read_config(child, *rid, 4); 2156 if (pci_mapbase(testval) == 0) 2157 goto out; 2158 if (pci_maptype(testval) & PCI_MAPMEM) { 2159 if (type != SYS_RES_MEMORY) { 2160 if (bootverbose) 2161 device_printf(dev, 2162 "child %s requested type %d for rid %#x," 2163 " but the BAR says it is an memio\n", 2164 device_get_nameunit(child), type, *rid); 2165 goto out; 2166 } 2167 } else { 2168 if (type != SYS_RES_IOPORT) { 2169 if (bootverbose) 2170 device_printf(dev, 2171 "child %s requested type %d for rid %#x," 2172 " but the BAR says it is an ioport\n", 2173 device_get_nameunit(child), type, *rid); 2174 goto out; 2175 } 2176 } 2177 /* 2178 * For real BARs, we need to override the size that 2179 * the driver requests, because that's what the BAR 2180 * actually uses and we would otherwise have a 2181 * situation where we might allocate the excess to 2182 * another driver, which won't work. 2183 */ 2184 mapsize = pci_mapsize(testval); 2185 count = 1 << mapsize; 2186 if (RF_ALIGNMENT(flags) < mapsize) 2187 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 2188 2189 /* 2190 * Allocate enough resource, and then write back the 2191 * appropriate bar for that resource. 2192 */ 2193 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 2194 start, end, count, flags); 2195 if (res == NULL) { 2196 device_printf(child, 2197 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n", 2198 count, *rid, type, start, end); 2199 goto out; 2200 } 2201 resource_list_add(rl, type, *rid, start, end, count); 2202 rle = resource_list_find(rl, type, *rid); 2203 if (rle == NULL) 2204 panic("pci_alloc_map: unexpectedly can't find resource."); 2205 rle->res = res; 2206 rle->start = rman_get_start(res); 2207 rle->end = rman_get_end(res); 2208 rle->count = count; 2209 if (bootverbose) 2210 device_printf(child, 2211 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 2212 count, *rid, type, rman_get_start(res)); 2213 map = rman_get_start(res); 2214 out:; 2215 pci_write_config(child, *rid, map, 4); 2216 return (res); 2217 } 2218 2219 2220 struct resource * 2221 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 2222 u_long start, u_long end, u_long count, u_int flags) 2223 { 2224 struct pci_devinfo *dinfo = device_get_ivars(child); 2225 struct resource_list *rl = &dinfo->resources; 2226 struct resource_list_entry *rle; 2227 pcicfgregs *cfg = &dinfo->cfg; 2228 2229 /* 2230 * Perform lazy resource allocation 2231 */ 2232 if (device_get_parent(child) == dev) { 2233 switch (type) { 2234 case SYS_RES_IRQ: 2235 /* 2236 * If the child device doesn't have an 2237 * interrupt routed and is deserving of an 2238 * interrupt, try to assign it one. 2239 */ 2240 if (!PCI_INTERRUPT_VALID(cfg->intline) && 2241 (cfg->intpin != 0)) 2242 pci_assign_interrupt(dev, child, 0); 2243 break; 2244 case SYS_RES_IOPORT: 2245 case SYS_RES_MEMORY: 2246 if (*rid < PCIR_BAR(cfg->nummaps)) { 2247 /* 2248 * Enable the I/O mode. We should 2249 * also be assigning resources too 2250 * when none are present. The 2251 * resource_list_alloc kind of sorta does 2252 * this... 2253 */ 2254 if (PCI_ENABLE_IO(dev, child, type)) 2255 return (NULL); 2256 } 2257 rle = resource_list_find(rl, type, *rid); 2258 if (rle == NULL) 2259 return (pci_alloc_map(dev, child, type, rid, 2260 start, end, count, flags)); 2261 break; 2262 } 2263 /* 2264 * If we've already allocated the resource, then 2265 * return it now. But first we may need to activate 2266 * it, since we don't allocate the resource as active 2267 * above. Normally this would be done down in the 2268 * nexus, but since we short-circuit that path we have 2269 * to do its job here. Not sure if we should free the 2270 * resource if it fails to activate. 2271 */ 2272 rle = resource_list_find(rl, type, *rid); 2273 if (rle != NULL && rle->res != NULL) { 2274 if (bootverbose) 2275 device_printf(child, 2276 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 2277 rman_get_size(rle->res), *rid, type, 2278 rman_get_start(rle->res)); 2279 if ((flags & RF_ACTIVE) && 2280 bus_generic_activate_resource(dev, child, type, 2281 *rid, rle->res) != 0) 2282 return NULL; 2283 return (rle->res); 2284 } 2285 } 2286 return (resource_list_alloc(rl, dev, child, type, rid, 2287 start, end, count, flags)); 2288 } 2289 2290 void 2291 pci_delete_resource(device_t dev, device_t child, int type, int rid) 2292 { 2293 struct pci_devinfo *dinfo; 2294 struct resource_list *rl; 2295 struct resource_list_entry *rle; 2296 2297 if (device_get_parent(child) != dev) 2298 return; 2299 2300 dinfo = device_get_ivars(child); 2301 rl = &dinfo->resources; 2302 rle = resource_list_find(rl, type, rid); 2303 if (rle) { 2304 if (rle->res) { 2305 if (rman_get_device(rle->res) != dev || 2306 rman_get_flags(rle->res) & RF_ACTIVE) { 2307 device_printf(dev, "delete_resource: " 2308 "Resource still owned by child, oops. " 2309 "(type=%d, rid=%d, addr=%lx)\n", 2310 rle->type, rle->rid, 2311 rman_get_start(rle->res)); 2312 return; 2313 } 2314 bus_release_resource(dev, type, rid, rle->res); 2315 } 2316 resource_list_delete(rl, type, rid); 2317 } 2318 /* 2319 * Why do we turn off the PCI configuration BAR when we delete a 2320 * resource? -- imp 2321 */ 2322 pci_write_config(child, rid, 0, 4); 2323 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 2324 } 2325 2326 struct resource_list * 2327 pci_get_resource_list (device_t dev, device_t child) 2328 { 2329 struct pci_devinfo *dinfo = device_get_ivars(child); 2330 2331 return (&dinfo->resources); 2332 } 2333 2334 uint32_t 2335 pci_read_config_method(device_t dev, device_t child, int reg, int width) 2336 { 2337 struct pci_devinfo *dinfo = device_get_ivars(child); 2338 pcicfgregs *cfg = &dinfo->cfg; 2339 2340 return (PCIB_READ_CONFIG(device_get_parent(dev), 2341 cfg->bus, cfg->slot, cfg->func, reg, width)); 2342 } 2343 2344 void 2345 pci_write_config_method(device_t dev, device_t child, int reg, 2346 uint32_t val, int width) 2347 { 2348 struct pci_devinfo *dinfo = device_get_ivars(child); 2349 pcicfgregs *cfg = &dinfo->cfg; 2350 2351 PCIB_WRITE_CONFIG(device_get_parent(dev), 2352 cfg->bus, cfg->slot, cfg->func, reg, val, width); 2353 } 2354 2355 int 2356 pci_child_location_str_method(device_t dev, device_t child, char *buf, 2357 size_t buflen) 2358 { 2359 2360 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 2361 pci_get_function(child)); 2362 return (0); 2363 } 2364 2365 int 2366 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 2367 size_t buflen) 2368 { 2369 struct pci_devinfo *dinfo; 2370 pcicfgregs *cfg; 2371 2372 dinfo = device_get_ivars(child); 2373 cfg = &dinfo->cfg; 2374 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 2375 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 2376 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 2377 cfg->progif); 2378 return (0); 2379 } 2380 2381 int 2382 pci_assign_interrupt_method(device_t dev, device_t child) 2383 { 2384 struct pci_devinfo *dinfo = device_get_ivars(child); 2385 pcicfgregs *cfg = &dinfo->cfg; 2386 2387 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 2388 cfg->intpin)); 2389 } 2390 2391 static int 2392 pci_modevent(module_t mod, int what, void *arg) 2393 { 2394 static struct cdev *pci_cdev; 2395 2396 switch (what) { 2397 case MOD_LOAD: 2398 STAILQ_INIT(&pci_devq); 2399 pci_generation = 0; 2400 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 2401 "pci"); 2402 pci_load_vendor_data(); 2403 break; 2404 2405 case MOD_UNLOAD: 2406 destroy_dev(pci_cdev); 2407 break; 2408 } 2409 2410 return (0); 2411 } 2412 2413 void 2414 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 2415 { 2416 int i; 2417 2418 /* 2419 * Only do header type 0 devices. Type 1 devices are bridges, 2420 * which we know need special treatment. Type 2 devices are 2421 * cardbus bridges which also require special treatment. 2422 * Other types are unknown, and we err on the side of safety 2423 * by ignoring them. 2424 */ 2425 if (dinfo->cfg.hdrtype != 0) 2426 return; 2427 2428 /* 2429 * Restore the device to full power mode. We must do this 2430 * before we restore the registers because moving from D3 to 2431 * D0 will cause the chip's BARs and some other registers to 2432 * be reset to some unknown power on reset values. Cut down 2433 * the noise on boot by doing nothing if we are already in 2434 * state D0. 2435 */ 2436 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 2437 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2438 } 2439 for (i = 0; i < dinfo->cfg.nummaps; i++) 2440 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 2441 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 2442 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 2443 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 2444 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 2445 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 2446 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 2447 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 2448 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 2449 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 2450 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 2451 } 2452 2453 void 2454 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 2455 { 2456 int i; 2457 uint32_t cls; 2458 int ps; 2459 2460 /* 2461 * Only do header type 0 devices. Type 1 devices are bridges, which 2462 * we know need special treatment. Type 2 devices are cardbus bridges 2463 * which also require special treatment. Other types are unknown, and 2464 * we err on the side of safety by ignoring them. Powering down 2465 * bridges should not be undertaken lightly. 2466 */ 2467 if (dinfo->cfg.hdrtype != 0) 2468 return; 2469 for (i = 0; i < dinfo->cfg.nummaps; i++) 2470 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 2471 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 2472 2473 /* 2474 * Some drivers apparently write to these registers w/o updating our 2475 * cached copy. No harm happens if we update the copy, so do so here 2476 * so we can restore them. The COMMAND register is modified by the 2477 * bus w/o updating the cache. This should represent the normally 2478 * writable portion of the 'defined' part of type 0 headers. In 2479 * theory we also need to save/restore the PCI capability structures 2480 * we know about, but apart from power we don't know any that are 2481 * writable. 2482 */ 2483 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 2484 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 2485 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 2486 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 2487 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 2488 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 2489 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 2490 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 2491 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 2492 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2493 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2494 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 2495 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 2496 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 2497 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 2498 2499 /* 2500 * don't set the state for display devices, base peripherals and 2501 * memory devices since bad things happen when they are powered down. 2502 * We should (a) have drivers that can easily detach and (b) use 2503 * generic drivers for these devices so that some device actually 2504 * attaches. We need to make sure that when we implement (a) we don't 2505 * power the device down on a reattach. 2506 */ 2507 cls = pci_get_class(dev); 2508 if (!setstate) 2509 return; 2510 switch (pci_do_power_nodriver) 2511 { 2512 case 0: /* NO powerdown at all */ 2513 return; 2514 case 1: /* Conservative about what to power down */ 2515 if (cls == PCIC_STORAGE) 2516 return; 2517 /*FALLTHROUGH*/ 2518 case 2: /* Agressive about what to power down */ 2519 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 2520 cls == PCIC_BASEPERIPH) 2521 return; 2522 /*FALLTHROUGH*/ 2523 case 3: /* Power down everything */ 2524 break; 2525 } 2526 /* 2527 * PCI spec says we can only go into D3 state from D0 state. 2528 * Transition from D[12] into D0 before going to D3 state. 2529 */ 2530 ps = pci_get_powerstate(dev); 2531 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 2532 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2533 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 2534 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 2535 } 2536