1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/linker.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/sysctl.h> 44 #include <sys/types.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 55 #include <sys/pciio.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pci_private.h> 59 60 #include "pcib_if.h" 61 #include "pci_if.h" 62 63 #ifdef __HAVE_ACPI 64 #include <contrib/dev/acpica/acpi.h> 65 #include "acpi_if.h" 66 #else 67 #define ACPI_PWR_FOR_SLEEP(x, y, z) 68 #endif 69 70 static uint32_t pci_mapbase(unsigned mapreg); 71 static int pci_maptype(unsigned mapreg); 72 static int pci_mapsize(unsigned testval); 73 static int pci_maprange(unsigned mapreg); 74 static void pci_fixancient(pcicfgregs *cfg); 75 76 static int pci_porten(device_t pcib, int b, int s, int f); 77 static int pci_memen(device_t pcib, int b, int s, int f); 78 static void pci_assign_interrupt(device_t bus, device_t dev, 79 int force_route); 80 static int pci_add_map(device_t pcib, device_t bus, device_t dev, 81 int b, int s, int f, int reg, 82 struct resource_list *rl, int force, int prefetch); 83 static int pci_probe(device_t dev); 84 static int pci_attach(device_t dev); 85 static void pci_load_vendor_data(void); 86 static int pci_describe_parse_line(char **ptr, int *vendor, 87 int *device, char **desc); 88 static char *pci_describe_device(device_t dev); 89 static int pci_modevent(module_t mod, int what, void *arg); 90 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 91 pcicfgregs *cfg); 92 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 93 94 static device_method_t pci_methods[] = { 95 /* Device interface */ 96 DEVMETHOD(device_probe, pci_probe), 97 DEVMETHOD(device_attach, pci_attach), 98 DEVMETHOD(device_detach, bus_generic_detach), 99 DEVMETHOD(device_shutdown, bus_generic_shutdown), 100 DEVMETHOD(device_suspend, pci_suspend), 101 DEVMETHOD(device_resume, pci_resume), 102 103 /* Bus interface */ 104 DEVMETHOD(bus_print_child, pci_print_child), 105 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 106 DEVMETHOD(bus_read_ivar, pci_read_ivar), 107 DEVMETHOD(bus_write_ivar, pci_write_ivar), 108 DEVMETHOD(bus_driver_added, pci_driver_added), 109 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 110 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 111 112 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 113 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 114 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 115 DEVMETHOD(bus_delete_resource, pci_delete_resource), 116 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 117 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 118 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 119 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 120 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 121 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 122 123 /* PCI interface */ 124 DEVMETHOD(pci_read_config, pci_read_config_method), 125 DEVMETHOD(pci_write_config, pci_write_config_method), 126 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 127 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 128 DEVMETHOD(pci_enable_io, pci_enable_io_method), 129 DEVMETHOD(pci_disable_io, pci_disable_io_method), 130 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 131 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 132 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 133 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 134 135 { 0, 0 } 136 }; 137 138 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 139 140 static devclass_t pci_devclass; 141 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 142 MODULE_VERSION(pci, 1); 143 144 static char *pci_vendordata; 145 static size_t pci_vendordata_size; 146 147 148 struct pci_quirk { 149 uint32_t devid; /* Vendor/device of the card */ 150 int type; 151 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 152 int arg1; 153 int arg2; 154 }; 155 156 struct pci_quirk pci_quirks[] = { 157 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 158 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 159 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 160 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 161 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 162 163 { 0 } 164 }; 165 166 /* map register information */ 167 #define PCI_MAPMEM 0x01 /* memory map */ 168 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 169 #define PCI_MAPPORT 0x04 /* port map */ 170 171 struct devlist pci_devq; 172 uint32_t pci_generation; 173 uint32_t pci_numdevs = 0; 174 175 /* sysctl vars */ 176 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 177 178 static int pci_enable_io_modes = 1; 179 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 180 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 181 &pci_enable_io_modes, 1, 182 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 183 enable these bits correctly. We'd like to do this all the time, but there\n\ 184 are some peripherals that this causes problems with."); 185 186 static int pci_do_power_nodriver = 0; 187 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver); 188 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW, 189 &pci_do_power_nodriver, 0, 190 "Place a function into D3 state when no driver attaches to it. 0 means\n\ 191 disable. 1 means conservatively place devices into D3 state. 2 means\n\ 192 agressively place devices into D3 state. 3 means put absolutely everything\n\ 193 in D3 state."); 194 195 static int pci_do_power_resume = 1; 196 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume); 197 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW, 198 &pci_do_power_resume, 1, 199 "Transition from D3 -> D0 on resume."); 200 201 /* Find a device_t by bus/slot/function */ 202 203 device_t 204 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 205 { 206 struct pci_devinfo *dinfo; 207 208 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 209 if ((dinfo->cfg.bus == bus) && 210 (dinfo->cfg.slot == slot) && 211 (dinfo->cfg.func == func)) { 212 return (dinfo->cfg.dev); 213 } 214 } 215 216 return (NULL); 217 } 218 219 /* Find a device_t by vendor/device ID */ 220 221 device_t 222 pci_find_device(uint16_t vendor, uint16_t device) 223 { 224 struct pci_devinfo *dinfo; 225 226 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 227 if ((dinfo->cfg.vendor == vendor) && 228 (dinfo->cfg.device == device)) { 229 return (dinfo->cfg.dev); 230 } 231 } 232 233 return (NULL); 234 } 235 236 /* return base address of memory or port map */ 237 238 static uint32_t 239 pci_mapbase(unsigned mapreg) 240 { 241 int mask = 0x03; 242 if ((mapreg & 0x01) == 0) 243 mask = 0x0f; 244 return (mapreg & ~mask); 245 } 246 247 /* return map type of memory or port map */ 248 249 static int 250 pci_maptype(unsigned mapreg) 251 { 252 static uint8_t maptype[0x10] = { 253 PCI_MAPMEM, PCI_MAPPORT, 254 PCI_MAPMEM, 0, 255 PCI_MAPMEM, PCI_MAPPORT, 256 0, 0, 257 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 258 PCI_MAPMEM|PCI_MAPMEMP, 0, 259 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 260 0, 0, 261 }; 262 263 return maptype[mapreg & 0x0f]; 264 } 265 266 /* return log2 of map size decoded for memory or port map */ 267 268 static int 269 pci_mapsize(unsigned testval) 270 { 271 int ln2size; 272 273 testval = pci_mapbase(testval); 274 ln2size = 0; 275 if (testval != 0) { 276 while ((testval & 1) == 0) 277 { 278 ln2size++; 279 testval >>= 1; 280 } 281 } 282 return (ln2size); 283 } 284 285 /* return log2 of address range supported by map register */ 286 287 static int 288 pci_maprange(unsigned mapreg) 289 { 290 int ln2range = 0; 291 switch (mapreg & 0x07) { 292 case 0x00: 293 case 0x01: 294 case 0x05: 295 ln2range = 32; 296 break; 297 case 0x02: 298 ln2range = 20; 299 break; 300 case 0x04: 301 ln2range = 64; 302 break; 303 } 304 return (ln2range); 305 } 306 307 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 308 309 static void 310 pci_fixancient(pcicfgregs *cfg) 311 { 312 if (cfg->hdrtype != 0) 313 return; 314 315 /* PCI to PCI bridges use header type 1 */ 316 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 317 cfg->hdrtype = 1; 318 } 319 320 /* extract header type specific config data */ 321 322 static void 323 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 324 { 325 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 326 switch (cfg->hdrtype) { 327 case 0: 328 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 329 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 330 cfg->nummaps = PCI_MAXMAPS_0; 331 break; 332 case 1: 333 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 334 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 335 cfg->nummaps = PCI_MAXMAPS_1; 336 break; 337 case 2: 338 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 339 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 340 cfg->nummaps = PCI_MAXMAPS_2; 341 break; 342 } 343 #undef REG 344 } 345 346 /* read configuration header into pcicfgregs structure */ 347 348 struct pci_devinfo * 349 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 350 { 351 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 352 pcicfgregs *cfg = NULL; 353 struct pci_devinfo *devlist_entry; 354 struct devlist *devlist_head; 355 356 devlist_head = &pci_devq; 357 358 devlist_entry = NULL; 359 360 if (REG(PCIR_DEVVENDOR, 4) != -1) { 361 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 362 if (devlist_entry == NULL) 363 return (NULL); 364 365 cfg = &devlist_entry->cfg; 366 367 cfg->bus = b; 368 cfg->slot = s; 369 cfg->func = f; 370 cfg->vendor = REG(PCIR_VENDOR, 2); 371 cfg->device = REG(PCIR_DEVICE, 2); 372 cfg->cmdreg = REG(PCIR_COMMAND, 2); 373 cfg->statreg = REG(PCIR_STATUS, 2); 374 cfg->baseclass = REG(PCIR_CLASS, 1); 375 cfg->subclass = REG(PCIR_SUBCLASS, 1); 376 cfg->progif = REG(PCIR_PROGIF, 1); 377 cfg->revid = REG(PCIR_REVID, 1); 378 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 379 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 380 cfg->lattimer = REG(PCIR_LATTIMER, 1); 381 cfg->intpin = REG(PCIR_INTPIN, 1); 382 cfg->intline = REG(PCIR_INTLINE, 1); 383 384 cfg->mingnt = REG(PCIR_MINGNT, 1); 385 cfg->maxlat = REG(PCIR_MAXLAT, 1); 386 387 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 388 cfg->hdrtype &= ~PCIM_MFDEV; 389 390 pci_fixancient(cfg); 391 pci_hdrtypedata(pcib, b, s, f, cfg); 392 393 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 394 pci_read_extcap(pcib, cfg); 395 396 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 397 398 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 399 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 400 devlist_entry->conf.pc_sel.pc_func = cfg->func; 401 devlist_entry->conf.pc_hdr = cfg->hdrtype; 402 403 devlist_entry->conf.pc_subvendor = cfg->subvendor; 404 devlist_entry->conf.pc_subdevice = cfg->subdevice; 405 devlist_entry->conf.pc_vendor = cfg->vendor; 406 devlist_entry->conf.pc_device = cfg->device; 407 408 devlist_entry->conf.pc_class = cfg->baseclass; 409 devlist_entry->conf.pc_subclass = cfg->subclass; 410 devlist_entry->conf.pc_progif = cfg->progif; 411 devlist_entry->conf.pc_revid = cfg->revid; 412 413 pci_numdevs++; 414 pci_generation++; 415 } 416 return (devlist_entry); 417 #undef REG 418 } 419 420 static void 421 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 422 { 423 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 424 int ptr, nextptr, ptrptr; 425 426 switch (cfg->hdrtype & PCIM_HDRTYPE) { 427 case 0: 428 ptrptr = PCIR_CAP_PTR; 429 break; 430 case 2: 431 ptrptr = PCIR_CAP_PTR_2; 432 break; 433 default: 434 return; /* no extended capabilities support */ 435 } 436 nextptr = REG(ptrptr, 1); /* sanity check? */ 437 438 /* 439 * Read capability entries. 440 */ 441 while (nextptr != 0) { 442 /* Sanity check */ 443 if (nextptr > 255) { 444 printf("illegal PCI extended capability offset %d\n", 445 nextptr); 446 return; 447 } 448 /* Find the next entry */ 449 ptr = nextptr; 450 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 451 452 /* Process this entry */ 453 switch (REG(ptr + PCICAP_ID, 1)) { 454 case PCIY_PMG: /* PCI power management */ 455 if (cfg->pp.pp_cap == 0) { 456 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 457 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 458 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 459 if ((nextptr - ptr) > PCIR_POWER_DATA) 460 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 461 } 462 break; 463 case PCIY_MSI: /* PCI MSI */ 464 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 465 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 466 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 467 else 468 cfg->msi.msi_data = PCIR_MSI_DATA; 469 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 470 PCIM_MSICTRL_MMC_MASK)>>1); 471 default: 472 break; 473 } 474 } 475 #undef REG 476 } 477 478 /* 479 * Return the offset in configuration space of the requested extended 480 * capability entry or 0 if the specified capability was not found. 481 */ 482 int 483 pci_find_extcap_method(device_t dev, device_t child, int capability, 484 int *capreg) 485 { 486 struct pci_devinfo *dinfo = device_get_ivars(child); 487 pcicfgregs *cfg = &dinfo->cfg; 488 u_int32_t status; 489 u_int8_t ptr; 490 491 /* 492 * Check the CAP_LIST bit of the PCI status register first. 493 */ 494 status = pci_read_config(child, PCIR_STATUS, 2); 495 if (!(status & PCIM_STATUS_CAPPRESENT)) 496 return (ENXIO); 497 498 /* 499 * Determine the start pointer of the capabilities list. 500 */ 501 switch (cfg->hdrtype & PCIM_HDRTYPE) { 502 case 0: 503 ptr = PCIR_CAP_PTR; 504 break; 505 case 2: 506 ptr = PCIR_CAP_PTR_2; 507 break; 508 default: 509 /* XXX: panic? */ 510 return (ENXIO); /* no extended capabilities support */ 511 } 512 ptr = pci_read_config(child, ptr, 1); 513 514 /* 515 * Traverse the capabilities list. 516 */ 517 while (ptr != 0) { 518 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 519 if (capreg != NULL) 520 *capreg = ptr; 521 return (0); 522 } 523 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 524 } 525 526 return (ENOENT); 527 } 528 529 /* free pcicfgregs structure and all depending data structures */ 530 531 int 532 pci_freecfg(struct pci_devinfo *dinfo) 533 { 534 struct devlist *devlist_head; 535 536 devlist_head = &pci_devq; 537 538 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 539 free(dinfo, M_DEVBUF); 540 541 /* increment the generation count */ 542 pci_generation++; 543 544 /* we're losing one device */ 545 pci_numdevs--; 546 return (0); 547 } 548 549 /* 550 * PCI power manangement 551 */ 552 int 553 pci_set_powerstate_method(device_t dev, device_t child, int state) 554 { 555 struct pci_devinfo *dinfo = device_get_ivars(child); 556 pcicfgregs *cfg = &dinfo->cfg; 557 uint16_t status; 558 int result, oldstate, highest, delay; 559 560 if (cfg->pp.pp_cap == 0) 561 return (EOPNOTSUPP); 562 563 /* 564 * Optimize a no state change request away. While it would be OK to 565 * write to the hardware in theory, some devices have shown odd 566 * behavior when going from D3 -> D3. 567 */ 568 oldstate = pci_get_powerstate(child); 569 if (oldstate == state) 570 return (0); 571 572 /* 573 * The PCI power management specification states that after a state 574 * transition between PCI power states, system software must 575 * guarantee a minimal delay before the function accesses the device. 576 * Compute the worst case delay that we need to guarantee before we 577 * access the device. Many devices will be responsive much more 578 * quickly than this delay, but there are some that don't respond 579 * instantly to state changes. Transitions to/from D3 state require 580 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 581 * is done below with DELAY rather than a sleeper function because 582 * this function can be called from contexts where we cannot sleep. 583 */ 584 highest = (oldstate > state) ? oldstate : state; 585 if (highest == PCI_POWERSTATE_D3) 586 delay = 10000; 587 else if (highest == PCI_POWERSTATE_D2) 588 delay = 200; 589 else 590 delay = 0; 591 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 592 & ~PCIM_PSTAT_DMASK; 593 result = 0; 594 switch (state) { 595 case PCI_POWERSTATE_D0: 596 status |= PCIM_PSTAT_D0; 597 break; 598 case PCI_POWERSTATE_D1: 599 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 600 return (EOPNOTSUPP); 601 status |= PCIM_PSTAT_D1; 602 break; 603 case PCI_POWERSTATE_D2: 604 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 605 return (EOPNOTSUPP); 606 status |= PCIM_PSTAT_D2; 607 break; 608 case PCI_POWERSTATE_D3: 609 status |= PCIM_PSTAT_D3; 610 break; 611 default: 612 return (EINVAL); 613 } 614 615 if (bootverbose) 616 printf( 617 "pci%d:%d:%d: Transition from D%d to D%d\n", 618 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 619 oldstate, state); 620 621 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 622 if (delay) 623 DELAY(delay); 624 return (0); 625 } 626 627 int 628 pci_get_powerstate_method(device_t dev, device_t child) 629 { 630 struct pci_devinfo *dinfo = device_get_ivars(child); 631 pcicfgregs *cfg = &dinfo->cfg; 632 uint16_t status; 633 int result; 634 635 if (cfg->pp.pp_cap != 0) { 636 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 637 switch (status & PCIM_PSTAT_DMASK) { 638 case PCIM_PSTAT_D0: 639 result = PCI_POWERSTATE_D0; 640 break; 641 case PCIM_PSTAT_D1: 642 result = PCI_POWERSTATE_D1; 643 break; 644 case PCIM_PSTAT_D2: 645 result = PCI_POWERSTATE_D2; 646 break; 647 case PCIM_PSTAT_D3: 648 result = PCI_POWERSTATE_D3; 649 break; 650 default: 651 result = PCI_POWERSTATE_UNKNOWN; 652 break; 653 } 654 } else { 655 /* No support, device is always at D0 */ 656 result = PCI_POWERSTATE_D0; 657 } 658 return (result); 659 } 660 661 /* 662 * Some convenience functions for PCI device drivers. 663 */ 664 665 static __inline void 666 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 667 { 668 uint16_t command; 669 670 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 671 command |= bit; 672 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 673 } 674 675 static __inline void 676 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 677 { 678 uint16_t command; 679 680 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 681 command &= ~bit; 682 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 683 } 684 685 int 686 pci_enable_busmaster_method(device_t dev, device_t child) 687 { 688 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 689 return (0); 690 } 691 692 int 693 pci_disable_busmaster_method(device_t dev, device_t child) 694 { 695 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 696 return (0); 697 } 698 699 int 700 pci_enable_io_method(device_t dev, device_t child, int space) 701 { 702 uint16_t command; 703 uint16_t bit; 704 char *error; 705 706 bit = 0; 707 error = NULL; 708 709 switch(space) { 710 case SYS_RES_IOPORT: 711 bit = PCIM_CMD_PORTEN; 712 error = "port"; 713 break; 714 case SYS_RES_MEMORY: 715 bit = PCIM_CMD_MEMEN; 716 error = "memory"; 717 break; 718 default: 719 return (EINVAL); 720 } 721 pci_set_command_bit(dev, child, bit); 722 /* Some devices seem to need a brief stall here, what do to? */ 723 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 724 if (command & bit) 725 return (0); 726 device_printf(child, "failed to enable %s mapping!\n", error); 727 return (ENXIO); 728 } 729 730 int 731 pci_disable_io_method(device_t dev, device_t child, int space) 732 { 733 uint16_t command; 734 uint16_t bit; 735 char *error; 736 737 bit = 0; 738 error = NULL; 739 740 switch(space) { 741 case SYS_RES_IOPORT: 742 bit = PCIM_CMD_PORTEN; 743 error = "port"; 744 break; 745 case SYS_RES_MEMORY: 746 bit = PCIM_CMD_MEMEN; 747 error = "memory"; 748 break; 749 default: 750 return (EINVAL); 751 } 752 pci_clear_command_bit(dev, child, bit); 753 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 754 if (command & bit) { 755 device_printf(child, "failed to disable %s mapping!\n", error); 756 return (ENXIO); 757 } 758 return (0); 759 } 760 761 /* 762 * New style pci driver. Parent device is either a pci-host-bridge or a 763 * pci-pci-bridge. Both kinds are represented by instances of pcib. 764 */ 765 766 void 767 pci_print_verbose(struct pci_devinfo *dinfo) 768 { 769 if (bootverbose) { 770 pcicfgregs *cfg = &dinfo->cfg; 771 772 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 773 cfg->vendor, cfg->device, cfg->revid); 774 printf("\tbus=%d, slot=%d, func=%d\n", 775 cfg->bus, cfg->slot, cfg->func); 776 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 777 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 778 cfg->mfdev); 779 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 780 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 781 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 782 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 783 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 784 if (cfg->intpin > 0) 785 printf("\tintpin=%c, irq=%d\n", 786 cfg->intpin +'a' -1, cfg->intline); 787 if (cfg->pp.pp_cap) { 788 uint16_t status; 789 790 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 791 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 792 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 793 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 794 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 795 status & PCIM_PSTAT_DMASK); 796 } 797 if (cfg->msi.msi_data) { 798 int ctrl; 799 800 ctrl = cfg->msi.msi_ctrl; 801 printf("\tMSI supports %d message%s%s%s\n", 802 cfg->msi.msi_msgnum, 803 (cfg->msi.msi_msgnum == 1) ? "" : "s", 804 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 805 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 806 } 807 } 808 } 809 810 static int 811 pci_porten(device_t pcib, int b, int s, int f) 812 { 813 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 814 & PCIM_CMD_PORTEN) != 0; 815 } 816 817 static int 818 pci_memen(device_t pcib, int b, int s, int f) 819 { 820 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 821 & PCIM_CMD_MEMEN) != 0; 822 } 823 824 /* 825 * Add a resource based on a pci map register. Return 1 if the map 826 * register is a 32bit map register or 2 if it is a 64bit register. 827 */ 828 static int 829 pci_add_map(device_t pcib, device_t bus, device_t dev, 830 int b, int s, int f, int reg, struct resource_list *rl, int force, 831 int prefetch) 832 { 833 uint32_t map; 834 uint64_t base; 835 uint64_t start, end, count; 836 uint8_t ln2size; 837 uint8_t ln2range; 838 uint32_t testval; 839 uint16_t cmd; 840 int type; 841 int barlen; 842 struct resource *res; 843 844 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 845 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 846 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 847 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 848 849 if (pci_maptype(map) & PCI_MAPMEM) 850 type = SYS_RES_MEMORY; 851 else 852 type = SYS_RES_IOPORT; 853 ln2size = pci_mapsize(testval); 854 ln2range = pci_maprange(testval); 855 base = pci_mapbase(map); 856 barlen = ln2range == 64 ? 2 : 1; 857 858 /* 859 * For I/O registers, if bottom bit is set, and the next bit up 860 * isn't clear, we know we have a BAR that doesn't conform to the 861 * spec, so ignore it. Also, sanity check the size of the data 862 * areas to the type of memory involved. Memory must be at least 863 * 32 bytes in size, while I/O ranges must be at least 4. 864 */ 865 if ((testval & 0x1) == 0x1 && 866 (testval & 0x2) != 0) 867 return (barlen); 868 if ((type == SYS_RES_MEMORY && ln2size < 5) || 869 (type == SYS_RES_IOPORT && ln2size < 2)) 870 return (barlen); 871 872 if (ln2range == 64) 873 /* Read the other half of a 64bit map register */ 874 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 875 876 if (bootverbose) { 877 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 878 reg, pci_maptype(map), ln2range, 879 (unsigned int) base, ln2size); 880 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 881 printf(", port disabled\n"); 882 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 883 printf(", memory disabled\n"); 884 else 885 printf(", enabled\n"); 886 } 887 888 /* 889 * If base is 0, then we have problems. It is best to ignore 890 * such entries for the moment. These will be allocated later if 891 * the driver specifically requests them. However, some 892 * removable busses look better when all resources are allocated, 893 * so allow '0' to be overriden. 894 * 895 * Similarly treat maps whose values is the same as the test value 896 * read back. These maps have had all f's written to them by the 897 * BIOS in an attempt to disable the resources. 898 */ 899 if (!force && (base == 0 || map == testval)) 900 return (barlen); 901 902 /* 903 * This code theoretically does the right thing, but has 904 * undesirable side effects in some cases where peripherals 905 * respond oddly to having these bits enabled. Let the user 906 * be able to turn them off (since pci_enable_io_modes is 1 by 907 * default). 908 */ 909 if (pci_enable_io_modes) { 910 /* Turn on resources that have been left off by a lazy BIOS */ 911 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 912 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 913 cmd |= PCIM_CMD_PORTEN; 914 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 915 } 916 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 917 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 918 cmd |= PCIM_CMD_MEMEN; 919 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 920 } 921 } else { 922 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 923 return (barlen); 924 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 925 return (barlen); 926 } 927 928 count = 1 << ln2size; 929 if (base == 0 || base == pci_mapbase(testval)) { 930 start = 0; /* Let the parent deside */ 931 end = ~0ULL; 932 } else { 933 start = base; 934 end = base + (1 << ln2size) - 1; 935 } 936 resource_list_add(rl, type, reg, start, end, count); 937 938 /* 939 * Not quite sure what to do on failure of allocating the resource 940 * since I can postulate several right answers. 941 */ 942 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 943 prefetch ? RF_PREFETCHABLE : 0); 944 if (res != NULL) 945 pci_write_config(dev, reg, rman_get_start(res), 4); 946 return (barlen); 947 } 948 949 /* 950 * For ATA devices we need to decide early what addressing mode to use. 951 * Legacy demands that the primary and secondary ATA ports sits on the 952 * same addresses that old ISA hardware did. This dictates that we use 953 * those addresses and ignore the BAR's if we cannot set PCI native 954 * addressing mode. 955 */ 956 static void 957 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 958 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask) 959 { 960 int rid, type, progif; 961 #if 0 962 /* if this device supports PCI native addressing use it */ 963 progif = pci_read_config(dev, PCIR_PROGIF, 1); 964 if ((progif & 0x8a) == 0x8a) { 965 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 966 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 967 printf("Trying ATA native PCI addressing mode\n"); 968 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 969 } 970 } 971 #endif 972 progif = pci_read_config(dev, PCIR_PROGIF, 1); 973 type = SYS_RES_IOPORT; 974 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 975 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force, 976 prefetchmask & (1 << 0)); 977 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force, 978 prefetchmask & (1 << 1)); 979 } else { 980 rid = PCIR_BAR(0); 981 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 982 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8, 983 0); 984 rid = PCIR_BAR(1); 985 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 986 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1, 987 0); 988 } 989 if (progif & PCIP_STORAGE_IDE_MODESEC) { 990 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force, 991 prefetchmask & (1 << 2)); 992 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force, 993 prefetchmask & (1 << 3)); 994 } else { 995 rid = PCIR_BAR(2); 996 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 997 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8, 998 0); 999 rid = PCIR_BAR(3); 1000 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 1001 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1, 1002 0); 1003 } 1004 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force, 1005 prefetchmask & (1 << 4)); 1006 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force, 1007 prefetchmask & (1 << 5)); 1008 } 1009 1010 static void 1011 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 1012 { 1013 struct pci_devinfo *dinfo = device_get_ivars(dev); 1014 pcicfgregs *cfg = &dinfo->cfg; 1015 char tunable_name[64]; 1016 int irq; 1017 1018 /* Has to have an intpin to have an interrupt. */ 1019 if (cfg->intpin == 0) 1020 return; 1021 1022 /* Let the user override the IRQ with a tunable. */ 1023 irq = PCI_INVALID_IRQ; 1024 snprintf(tunable_name, sizeof(tunable_name), "hw.pci%d.%d.INT%c.irq", 1025 cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 1026 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 1027 irq = PCI_INVALID_IRQ; 1028 1029 /* 1030 * If we didn't get an IRQ via the tunable, then we either use the 1031 * IRQ value in the intline register or we ask the bus to route an 1032 * interrupt for us. If force_route is true, then we only use the 1033 * value in the intline register if the bus was unable to assign an 1034 * IRQ. 1035 */ 1036 if (!PCI_INTERRUPT_VALID(irq)) { 1037 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 1038 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 1039 if (!PCI_INTERRUPT_VALID(irq)) 1040 irq = cfg->intline; 1041 } 1042 1043 /* If after all that we don't have an IRQ, just bail. */ 1044 if (!PCI_INTERRUPT_VALID(irq)) 1045 return; 1046 1047 /* Update the config register if it changed. */ 1048 if (irq != cfg->intline) { 1049 cfg->intline = irq; 1050 pci_write_config(dev, PCIR_INTLINE, irq, 1); 1051 } 1052 1053 /* Add this IRQ as rid 0 interrupt resource. */ 1054 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 1055 } 1056 1057 void 1058 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 1059 { 1060 device_t pcib; 1061 struct pci_devinfo *dinfo = device_get_ivars(dev); 1062 pcicfgregs *cfg = &dinfo->cfg; 1063 struct resource_list *rl = &dinfo->resources; 1064 struct pci_quirk *q; 1065 int b, i, f, s; 1066 1067 pcib = device_get_parent(bus); 1068 1069 b = cfg->bus; 1070 s = cfg->slot; 1071 f = cfg->func; 1072 1073 /* ATA devices needs special map treatment */ 1074 if ((pci_get_class(dev) == PCIC_STORAGE) && 1075 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 1076 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 1077 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask); 1078 else 1079 for (i = 0; i < cfg->nummaps;) 1080 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 1081 rl, force, prefetchmask & (1 << i)); 1082 1083 /* 1084 * Add additional, quirked resources. 1085 */ 1086 for (q = &pci_quirks[0]; q->devid; q++) { 1087 if (q->devid == ((cfg->device << 16) | cfg->vendor) 1088 && q->type == PCI_QUIRK_MAP_REG) 1089 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl, 1090 force, 0); 1091 } 1092 1093 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 1094 #ifdef __PCI_REROUTE_INTERRUPT 1095 /* 1096 * Try to re-route interrupts. Sometimes the BIOS or 1097 * firmware may leave bogus values in these registers. 1098 * If the re-route fails, then just stick with what we 1099 * have. 1100 */ 1101 pci_assign_interrupt(bus, dev, 1); 1102 #else 1103 pci_assign_interrupt(bus, dev, 0); 1104 #endif 1105 } 1106 } 1107 1108 void 1109 pci_add_children(device_t dev, int busno, size_t dinfo_size) 1110 { 1111 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 1112 device_t pcib = device_get_parent(dev); 1113 struct pci_devinfo *dinfo; 1114 int maxslots; 1115 int s, f, pcifunchigh; 1116 uint8_t hdrtype; 1117 1118 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 1119 ("dinfo_size too small")); 1120 maxslots = PCIB_MAXSLOTS(pcib); 1121 for (s = 0; s <= maxslots; s++) { 1122 pcifunchigh = 0; 1123 f = 0; 1124 DELAY(1); 1125 hdrtype = REG(PCIR_HDRTYPE, 1); 1126 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 1127 continue; 1128 if (hdrtype & PCIM_MFDEV) 1129 pcifunchigh = PCI_FUNCMAX; 1130 for (f = 0; f <= pcifunchigh; f++) { 1131 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 1132 if (dinfo != NULL) { 1133 pci_add_child(dev, dinfo); 1134 } 1135 } 1136 } 1137 #undef REG 1138 } 1139 1140 void 1141 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1142 { 1143 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1144 device_set_ivars(dinfo->cfg.dev, dinfo); 1145 resource_list_init(&dinfo->resources); 1146 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 1147 pci_cfg_restore(dinfo->cfg.dev, dinfo); 1148 pci_print_verbose(dinfo); 1149 pci_add_resources(bus, dinfo->cfg.dev, 0, 0); 1150 } 1151 1152 static int 1153 pci_probe(device_t dev) 1154 { 1155 1156 device_set_desc(dev, "PCI bus"); 1157 1158 /* Allow other subclasses to override this driver. */ 1159 return (-1000); 1160 } 1161 1162 static int 1163 pci_attach(device_t dev) 1164 { 1165 int busno; 1166 1167 /* 1168 * Since there can be multiple independantly numbered PCI 1169 * busses on some large alpha systems, we can't use the unit 1170 * number to decide what bus we are probing. We ask the parent 1171 * pcib what our bus number is. 1172 */ 1173 busno = pcib_get_bus(dev); 1174 if (bootverbose) 1175 device_printf(dev, "physical bus=%d\n", busno); 1176 1177 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1178 1179 return (bus_generic_attach(dev)); 1180 } 1181 1182 int 1183 pci_suspend(device_t dev) 1184 { 1185 int dstate, error, i, numdevs; 1186 device_t acpi_dev, child, *devlist; 1187 struct pci_devinfo *dinfo; 1188 1189 /* 1190 * Save the PCI configuration space for each child and set the 1191 * device in the appropriate power state for this sleep state. 1192 */ 1193 acpi_dev = NULL; 1194 if (pci_do_power_resume) 1195 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1196 device_get_children(dev, &devlist, &numdevs); 1197 for (i = 0; i < numdevs; i++) { 1198 child = devlist[i]; 1199 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1200 pci_cfg_save(child, dinfo, 0); 1201 } 1202 1203 /* Suspend devices before potentially powering them down. */ 1204 error = bus_generic_suspend(dev); 1205 if (error) { 1206 free(devlist, M_TEMP); 1207 return (error); 1208 } 1209 1210 /* 1211 * Always set the device to D3. If ACPI suggests a different 1212 * power state, use it instead. If ACPI is not present, the 1213 * firmware is responsible for managing device power. Skip 1214 * children who aren't attached since they are powered down 1215 * separately. Only manage type 0 devices for now. 1216 */ 1217 for (i = 0; acpi_dev && i < numdevs; i++) { 1218 child = devlist[i]; 1219 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1220 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 1221 dstate = PCI_POWERSTATE_D3; 1222 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 1223 pci_set_powerstate(child, dstate); 1224 } 1225 } 1226 free(devlist, M_TEMP); 1227 return (0); 1228 } 1229 1230 int 1231 pci_resume(device_t dev) 1232 { 1233 int i, numdevs; 1234 device_t acpi_dev, child, *devlist; 1235 struct pci_devinfo *dinfo; 1236 1237 /* 1238 * Set each child to D0 and restore its PCI configuration space. 1239 */ 1240 acpi_dev = NULL; 1241 if (pci_do_power_resume) 1242 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1243 device_get_children(dev, &devlist, &numdevs); 1244 for (i = 0; i < numdevs; i++) { 1245 /* 1246 * Notify ACPI we're going to D0 but ignore the result. If 1247 * ACPI is not present, the firmware is responsible for 1248 * managing device power. Only manage type 0 devices for now. 1249 */ 1250 child = devlist[i]; 1251 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1252 if (acpi_dev && device_is_attached(child) && 1253 dinfo->cfg.hdrtype == 0) { 1254 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 1255 pci_set_powerstate(child, PCI_POWERSTATE_D0); 1256 } 1257 1258 /* Now the device is powered up, restore its config space. */ 1259 pci_cfg_restore(child, dinfo); 1260 } 1261 free(devlist, M_TEMP); 1262 return (bus_generic_resume(dev)); 1263 } 1264 1265 static void 1266 pci_load_vendor_data(void) 1267 { 1268 caddr_t vendordata, info; 1269 1270 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1271 info = preload_search_info(vendordata, MODINFO_ADDR); 1272 pci_vendordata = *(char **)info; 1273 info = preload_search_info(vendordata, MODINFO_SIZE); 1274 pci_vendordata_size = *(size_t *)info; 1275 /* terminate the database */ 1276 pci_vendordata[pci_vendordata_size] = '\n'; 1277 } 1278 } 1279 1280 void 1281 pci_driver_added(device_t dev, driver_t *driver) 1282 { 1283 int numdevs; 1284 device_t *devlist; 1285 device_t child; 1286 struct pci_devinfo *dinfo; 1287 int i; 1288 1289 if (bootverbose) 1290 device_printf(dev, "driver added\n"); 1291 DEVICE_IDENTIFY(driver, dev); 1292 device_get_children(dev, &devlist, &numdevs); 1293 for (i = 0; i < numdevs; i++) { 1294 child = devlist[i]; 1295 if (device_get_state(child) != DS_NOTPRESENT) 1296 continue; 1297 dinfo = device_get_ivars(child); 1298 pci_print_verbose(dinfo); 1299 if (bootverbose) 1300 printf("pci%d:%d:%d: reprobing on driver added\n", 1301 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1302 pci_cfg_restore(child, dinfo); 1303 if (device_probe_and_attach(child) != 0) 1304 pci_cfg_save(child, dinfo, 1); 1305 } 1306 free(devlist, M_TEMP); 1307 } 1308 1309 int 1310 pci_print_child(device_t dev, device_t child) 1311 { 1312 struct pci_devinfo *dinfo; 1313 struct resource_list *rl; 1314 int retval = 0; 1315 1316 dinfo = device_get_ivars(child); 1317 rl = &dinfo->resources; 1318 1319 retval += bus_print_child_header(dev, child); 1320 1321 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1322 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1323 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1324 if (device_get_flags(dev)) 1325 retval += printf(" flags %#x", device_get_flags(dev)); 1326 1327 retval += printf(" at device %d.%d", pci_get_slot(child), 1328 pci_get_function(child)); 1329 1330 retval += bus_print_child_footer(dev, child); 1331 1332 return (retval); 1333 } 1334 1335 static struct 1336 { 1337 int class; 1338 int subclass; 1339 char *desc; 1340 } pci_nomatch_tab[] = { 1341 {PCIC_OLD, -1, "old"}, 1342 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1343 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1344 {PCIC_STORAGE, -1, "mass storage"}, 1345 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1346 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1347 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1348 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1349 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1350 {PCIC_NETWORK, -1, "network"}, 1351 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1352 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1353 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1354 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1355 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"}, 1356 {PCIC_DISPLAY, -1, "display"}, 1357 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1358 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1359 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"}, 1360 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1361 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1362 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1363 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"}, 1364 {PCIC_MEMORY, -1, "memory"}, 1365 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1366 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1367 {PCIC_BRIDGE, -1, "bridge"}, 1368 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1369 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1370 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1371 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1372 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1373 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1374 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1375 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1376 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"}, 1377 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1378 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1379 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1380 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"}, 1381 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"}, 1382 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1383 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1384 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1385 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1386 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1387 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"}, 1388 {PCIC_INPUTDEV, -1, "input device"}, 1389 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1390 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1391 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1392 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"}, 1393 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"}, 1394 {PCIC_DOCKING, -1, "docking station"}, 1395 {PCIC_PROCESSOR, -1, "processor"}, 1396 {PCIC_SERIALBUS, -1, "serial bus"}, 1397 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1398 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1399 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1400 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1401 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1402 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1403 {PCIC_WIRELESS, -1, "wireless controller"}, 1404 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"}, 1405 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"}, 1406 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"}, 1407 {PCIC_INTELLIIO, -1, "intelligent I/O controller"}, 1408 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"}, 1409 {PCIC_SATCOM, -1, "satellite communication"}, 1410 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"}, 1411 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"}, 1412 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"}, 1413 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"}, 1414 {PCIC_CRYPTO, -1, "encrypt/decrypt"}, 1415 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"}, 1416 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "entertainment crypto"}, 1417 {PCIC_DASP, -1, "dasp"}, 1418 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"}, 1419 {0, 0, NULL} 1420 }; 1421 1422 void 1423 pci_probe_nomatch(device_t dev, device_t child) 1424 { 1425 int i; 1426 char *cp, *scp, *device; 1427 1428 /* 1429 * Look for a listing for this device in a loaded device database. 1430 */ 1431 if ((device = pci_describe_device(child)) != NULL) { 1432 device_printf(dev, "<%s>", device); 1433 free(device, M_DEVBUF); 1434 } else { 1435 /* 1436 * Scan the class/subclass descriptions for a general 1437 * description. 1438 */ 1439 cp = "unknown"; 1440 scp = NULL; 1441 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1442 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1443 if (pci_nomatch_tab[i].subclass == -1) { 1444 cp = pci_nomatch_tab[i].desc; 1445 } else if (pci_nomatch_tab[i].subclass == 1446 pci_get_subclass(child)) { 1447 scp = pci_nomatch_tab[i].desc; 1448 } 1449 } 1450 } 1451 device_printf(dev, "<%s%s%s>", 1452 cp ? cp : "", 1453 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1454 scp ? scp : ""); 1455 } 1456 printf(" at device %d.%d (no driver attached)\n", 1457 pci_get_slot(child), pci_get_function(child)); 1458 if (pci_do_power_nodriver) 1459 pci_cfg_save(child, 1460 (struct pci_devinfo *) device_get_ivars(child), 1); 1461 return; 1462 } 1463 1464 /* 1465 * Parse the PCI device database, if loaded, and return a pointer to a 1466 * description of the device. 1467 * 1468 * The database is flat text formatted as follows: 1469 * 1470 * Any line not in a valid format is ignored. 1471 * Lines are terminated with newline '\n' characters. 1472 * 1473 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1474 * the vendor name. 1475 * 1476 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1477 * - devices cannot be listed without a corresponding VENDOR line. 1478 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1479 * another TAB, then the device name. 1480 */ 1481 1482 /* 1483 * Assuming (ptr) points to the beginning of a line in the database, 1484 * return the vendor or device and description of the next entry. 1485 * The value of (vendor) or (device) inappropriate for the entry type 1486 * is set to -1. Returns nonzero at the end of the database. 1487 * 1488 * Note that this is slightly unrobust in the face of corrupt data; 1489 * we attempt to safeguard against this by spamming the end of the 1490 * database with a newline when we initialise. 1491 */ 1492 static int 1493 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1494 { 1495 char *cp = *ptr; 1496 int left; 1497 1498 *device = -1; 1499 *vendor = -1; 1500 **desc = '\0'; 1501 for (;;) { 1502 left = pci_vendordata_size - (cp - pci_vendordata); 1503 if (left <= 0) { 1504 *ptr = cp; 1505 return(1); 1506 } 1507 1508 /* vendor entry? */ 1509 if (*cp != '\t' && 1510 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1511 break; 1512 /* device entry? */ 1513 if (*cp == '\t' && 1514 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1515 break; 1516 1517 /* skip to next line */ 1518 while (*cp != '\n' && left > 0) { 1519 cp++; 1520 left--; 1521 } 1522 if (*cp == '\n') { 1523 cp++; 1524 left--; 1525 } 1526 } 1527 /* skip to next line */ 1528 while (*cp != '\n' && left > 0) { 1529 cp++; 1530 left--; 1531 } 1532 if (*cp == '\n' && left > 0) 1533 cp++; 1534 *ptr = cp; 1535 return(0); 1536 } 1537 1538 static char * 1539 pci_describe_device(device_t dev) 1540 { 1541 int vendor, device; 1542 char *desc, *vp, *dp, *line; 1543 1544 desc = vp = dp = NULL; 1545 1546 /* 1547 * If we have no vendor data, we can't do anything. 1548 */ 1549 if (pci_vendordata == NULL) 1550 goto out; 1551 1552 /* 1553 * Scan the vendor data looking for this device 1554 */ 1555 line = pci_vendordata; 1556 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1557 goto out; 1558 for (;;) { 1559 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1560 goto out; 1561 if (vendor == pci_get_vendor(dev)) 1562 break; 1563 } 1564 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1565 goto out; 1566 for (;;) { 1567 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1568 *dp = 0; 1569 break; 1570 } 1571 if (vendor != -1) { 1572 *dp = 0; 1573 break; 1574 } 1575 if (device == pci_get_device(dev)) 1576 break; 1577 } 1578 if (dp[0] == '\0') 1579 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1580 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1581 NULL) 1582 sprintf(desc, "%s, %s", vp, dp); 1583 out: 1584 if (vp != NULL) 1585 free(vp, M_DEVBUF); 1586 if (dp != NULL) 1587 free(dp, M_DEVBUF); 1588 return(desc); 1589 } 1590 1591 int 1592 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1593 { 1594 struct pci_devinfo *dinfo; 1595 pcicfgregs *cfg; 1596 1597 dinfo = device_get_ivars(child); 1598 cfg = &dinfo->cfg; 1599 1600 switch (which) { 1601 case PCI_IVAR_ETHADDR: 1602 /* 1603 * The generic accessor doesn't deal with failure, so 1604 * we set the return value, then return an error. 1605 */ 1606 *((uint8_t **) result) = NULL; 1607 return (EINVAL); 1608 case PCI_IVAR_SUBVENDOR: 1609 *result = cfg->subvendor; 1610 break; 1611 case PCI_IVAR_SUBDEVICE: 1612 *result = cfg->subdevice; 1613 break; 1614 case PCI_IVAR_VENDOR: 1615 *result = cfg->vendor; 1616 break; 1617 case PCI_IVAR_DEVICE: 1618 *result = cfg->device; 1619 break; 1620 case PCI_IVAR_DEVID: 1621 *result = (cfg->device << 16) | cfg->vendor; 1622 break; 1623 case PCI_IVAR_CLASS: 1624 *result = cfg->baseclass; 1625 break; 1626 case PCI_IVAR_SUBCLASS: 1627 *result = cfg->subclass; 1628 break; 1629 case PCI_IVAR_PROGIF: 1630 *result = cfg->progif; 1631 break; 1632 case PCI_IVAR_REVID: 1633 *result = cfg->revid; 1634 break; 1635 case PCI_IVAR_INTPIN: 1636 *result = cfg->intpin; 1637 break; 1638 case PCI_IVAR_IRQ: 1639 *result = cfg->intline; 1640 break; 1641 case PCI_IVAR_BUS: 1642 *result = cfg->bus; 1643 break; 1644 case PCI_IVAR_SLOT: 1645 *result = cfg->slot; 1646 break; 1647 case PCI_IVAR_FUNCTION: 1648 *result = cfg->func; 1649 break; 1650 case PCI_IVAR_CMDREG: 1651 *result = cfg->cmdreg; 1652 break; 1653 case PCI_IVAR_CACHELNSZ: 1654 *result = cfg->cachelnsz; 1655 break; 1656 case PCI_IVAR_MINGNT: 1657 *result = cfg->mingnt; 1658 break; 1659 case PCI_IVAR_MAXLAT: 1660 *result = cfg->maxlat; 1661 break; 1662 case PCI_IVAR_LATTIMER: 1663 *result = cfg->lattimer; 1664 break; 1665 default: 1666 return (ENOENT); 1667 } 1668 return (0); 1669 } 1670 1671 int 1672 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1673 { 1674 struct pci_devinfo *dinfo; 1675 1676 dinfo = device_get_ivars(child); 1677 1678 switch (which) { 1679 case PCI_IVAR_INTPIN: 1680 dinfo->cfg.intpin = value; 1681 return (0); 1682 case PCI_IVAR_ETHADDR: 1683 case PCI_IVAR_SUBVENDOR: 1684 case PCI_IVAR_SUBDEVICE: 1685 case PCI_IVAR_VENDOR: 1686 case PCI_IVAR_DEVICE: 1687 case PCI_IVAR_DEVID: 1688 case PCI_IVAR_CLASS: 1689 case PCI_IVAR_SUBCLASS: 1690 case PCI_IVAR_PROGIF: 1691 case PCI_IVAR_REVID: 1692 case PCI_IVAR_IRQ: 1693 case PCI_IVAR_BUS: 1694 case PCI_IVAR_SLOT: 1695 case PCI_IVAR_FUNCTION: 1696 return (EINVAL); /* disallow for now */ 1697 1698 default: 1699 return (ENOENT); 1700 } 1701 } 1702 1703 1704 #include "opt_ddb.h" 1705 #ifdef DDB 1706 #include <ddb/ddb.h> 1707 #include <sys/cons.h> 1708 1709 /* 1710 * List resources based on pci map registers, used for within ddb 1711 */ 1712 1713 DB_SHOW_COMMAND(pciregs, db_pci_dump) 1714 { 1715 struct pci_devinfo *dinfo; 1716 struct devlist *devlist_head; 1717 struct pci_conf *p; 1718 const char *name; 1719 int i, error, none_count, quit; 1720 1721 none_count = 0; 1722 /* get the head of the device queue */ 1723 devlist_head = &pci_devq; 1724 1725 /* 1726 * Go through the list of devices and print out devices 1727 */ 1728 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 1729 for (error = 0, i = 0, quit = 0, 1730 dinfo = STAILQ_FIRST(devlist_head); 1731 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !quit; 1732 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 1733 1734 /* Populate pd_name and pd_unit */ 1735 name = NULL; 1736 if (dinfo->cfg.dev) 1737 name = device_get_name(dinfo->cfg.dev); 1738 1739 p = &dinfo->conf; 1740 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 1741 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 1742 (name && *name) ? name : "none", 1743 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 1744 none_count++, 1745 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 1746 p->pc_sel.pc_func, (p->pc_class << 16) | 1747 (p->pc_subclass << 8) | p->pc_progif, 1748 (p->pc_subdevice << 16) | p->pc_subvendor, 1749 (p->pc_device << 16) | p->pc_vendor, 1750 p->pc_revid, p->pc_hdr); 1751 } 1752 } 1753 #endif /* DDB */ 1754 1755 static struct resource * 1756 pci_alloc_map(device_t dev, device_t child, int type, int *rid, 1757 u_long start, u_long end, u_long count, u_int flags) 1758 { 1759 struct pci_devinfo *dinfo = device_get_ivars(child); 1760 struct resource_list *rl = &dinfo->resources; 1761 struct resource_list_entry *rle; 1762 struct resource *res; 1763 uint32_t map, testval; 1764 int mapsize; 1765 1766 /* 1767 * Weed out the bogons, and figure out how large the BAR/map 1768 * is. Bars that read back 0 here are bogus and unimplemented. 1769 * Note: atapci in legacy mode are special and handled elsewhere 1770 * in the code. If you have a atapci device in legacy mode and 1771 * it fails here, that other code is broken. 1772 */ 1773 res = NULL; 1774 map = pci_read_config(child, *rid, 4); 1775 pci_write_config(child, *rid, 0xffffffff, 4); 1776 testval = pci_read_config(child, *rid, 4); 1777 if (pci_mapbase(testval) == 0) 1778 goto out; 1779 if (pci_maptype(testval) & PCI_MAPMEM) { 1780 if (type != SYS_RES_MEMORY) { 1781 if (bootverbose) 1782 device_printf(dev, 1783 "child %s requested type %d for rid %#x," 1784 " but the BAR says it is an memio\n", 1785 device_get_nameunit(child), type, *rid); 1786 goto out; 1787 } 1788 } else { 1789 if (type != SYS_RES_IOPORT) { 1790 if (bootverbose) 1791 device_printf(dev, 1792 "child %s requested type %d for rid %#x," 1793 " but the BAR says it is an ioport\n", 1794 device_get_nameunit(child), type, *rid); 1795 goto out; 1796 } 1797 } 1798 /* 1799 * For real BARs, we need to override the size that 1800 * the driver requests, because that's what the BAR 1801 * actually uses and we would otherwise have a 1802 * situation where we might allocate the excess to 1803 * another driver, which won't work. 1804 */ 1805 mapsize = pci_mapsize(testval); 1806 count = 1 << mapsize; 1807 if (RF_ALIGNMENT(flags) < mapsize) 1808 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 1809 1810 /* 1811 * Allocate enough resource, and then write back the 1812 * appropriate bar for that resource. 1813 */ 1814 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 1815 start, end, count, flags); 1816 if (res == NULL) { 1817 device_printf(child, 1818 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n", 1819 count, *rid, type, start, end); 1820 goto out; 1821 } 1822 resource_list_add(rl, type, *rid, start, end, count); 1823 rle = resource_list_find(rl, type, *rid); 1824 if (rle == NULL) 1825 panic("pci_alloc_map: unexpectedly can't find resource."); 1826 rle->res = res; 1827 rle->start = rman_get_start(res); 1828 rle->end = rman_get_end(res); 1829 rle->count = count; 1830 if (bootverbose) 1831 device_printf(child, 1832 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 1833 count, *rid, type, rman_get_start(res)); 1834 map = rman_get_start(res); 1835 out:; 1836 pci_write_config(child, *rid, map, 4); 1837 return (res); 1838 } 1839 1840 1841 struct resource * 1842 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1843 u_long start, u_long end, u_long count, u_int flags) 1844 { 1845 struct pci_devinfo *dinfo = device_get_ivars(child); 1846 struct resource_list *rl = &dinfo->resources; 1847 struct resource_list_entry *rle; 1848 pcicfgregs *cfg = &dinfo->cfg; 1849 1850 /* 1851 * Perform lazy resource allocation 1852 */ 1853 if (device_get_parent(child) == dev) { 1854 switch (type) { 1855 case SYS_RES_IRQ: 1856 /* 1857 * If the child device doesn't have an 1858 * interrupt routed and is deserving of an 1859 * interrupt, try to assign it one. 1860 */ 1861 if (!PCI_INTERRUPT_VALID(cfg->intline) && 1862 (cfg->intpin != 0)) 1863 pci_assign_interrupt(dev, child, 0); 1864 break; 1865 case SYS_RES_IOPORT: 1866 case SYS_RES_MEMORY: 1867 if (*rid < PCIR_BAR(cfg->nummaps)) { 1868 /* 1869 * Enable the I/O mode. We should 1870 * also be assigning resources too 1871 * when none are present. The 1872 * resource_list_alloc kind of sorta does 1873 * this... 1874 */ 1875 if (PCI_ENABLE_IO(dev, child, type)) 1876 return (NULL); 1877 } 1878 rle = resource_list_find(rl, type, *rid); 1879 if (rle == NULL) 1880 return (pci_alloc_map(dev, child, type, rid, 1881 start, end, count, flags)); 1882 break; 1883 } 1884 /* 1885 * If we've already allocated the resource, then 1886 * return it now. But first we may need to activate 1887 * it, since we don't allocate the resource as active 1888 * above. Normally this would be done down in the 1889 * nexus, but since we short-circuit that path we have 1890 * to do its job here. Not sure if we should free the 1891 * resource if it fails to activate. 1892 */ 1893 rle = resource_list_find(rl, type, *rid); 1894 if (rle != NULL && rle->res != NULL) { 1895 if (bootverbose) 1896 device_printf(child, 1897 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 1898 rman_get_size(rle->res), *rid, type, 1899 rman_get_start(rle->res)); 1900 if ((flags & RF_ACTIVE) && 1901 bus_generic_activate_resource(dev, child, type, 1902 *rid, rle->res) != 0) 1903 return NULL; 1904 return (rle->res); 1905 } 1906 } 1907 return (resource_list_alloc(rl, dev, child, type, rid, 1908 start, end, count, flags)); 1909 } 1910 1911 void 1912 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1913 { 1914 struct pci_devinfo *dinfo; 1915 struct resource_list *rl; 1916 struct resource_list_entry *rle; 1917 1918 if (device_get_parent(child) != dev) 1919 return; 1920 1921 dinfo = device_get_ivars(child); 1922 rl = &dinfo->resources; 1923 rle = resource_list_find(rl, type, rid); 1924 if (rle) { 1925 if (rle->res) { 1926 if (rman_get_device(rle->res) != dev || 1927 rman_get_flags(rle->res) & RF_ACTIVE) { 1928 device_printf(dev, "delete_resource: " 1929 "Resource still owned by child, oops. " 1930 "(type=%d, rid=%d, addr=%lx)\n", 1931 rle->type, rle->rid, 1932 rman_get_start(rle->res)); 1933 return; 1934 } 1935 bus_release_resource(dev, type, rid, rle->res); 1936 } 1937 resource_list_delete(rl, type, rid); 1938 } 1939 /* 1940 * Why do we turn off the PCI configuration BAR when we delete a 1941 * resource? -- imp 1942 */ 1943 pci_write_config(child, rid, 0, 4); 1944 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 1945 } 1946 1947 struct resource_list * 1948 pci_get_resource_list (device_t dev, device_t child) 1949 { 1950 struct pci_devinfo *dinfo = device_get_ivars(child); 1951 1952 return (&dinfo->resources); 1953 } 1954 1955 uint32_t 1956 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1957 { 1958 struct pci_devinfo *dinfo = device_get_ivars(child); 1959 pcicfgregs *cfg = &dinfo->cfg; 1960 1961 return (PCIB_READ_CONFIG(device_get_parent(dev), 1962 cfg->bus, cfg->slot, cfg->func, reg, width)); 1963 } 1964 1965 void 1966 pci_write_config_method(device_t dev, device_t child, int reg, 1967 uint32_t val, int width) 1968 { 1969 struct pci_devinfo *dinfo = device_get_ivars(child); 1970 pcicfgregs *cfg = &dinfo->cfg; 1971 1972 PCIB_WRITE_CONFIG(device_get_parent(dev), 1973 cfg->bus, cfg->slot, cfg->func, reg, val, width); 1974 } 1975 1976 int 1977 pci_child_location_str_method(device_t dev, device_t child, char *buf, 1978 size_t buflen) 1979 { 1980 1981 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 1982 pci_get_function(child)); 1983 return (0); 1984 } 1985 1986 int 1987 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1988 size_t buflen) 1989 { 1990 struct pci_devinfo *dinfo; 1991 pcicfgregs *cfg; 1992 1993 dinfo = device_get_ivars(child); 1994 cfg = &dinfo->cfg; 1995 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 1996 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 1997 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 1998 cfg->progif); 1999 return (0); 2000 } 2001 2002 int 2003 pci_assign_interrupt_method(device_t dev, device_t child) 2004 { 2005 struct pci_devinfo *dinfo = device_get_ivars(child); 2006 pcicfgregs *cfg = &dinfo->cfg; 2007 2008 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 2009 cfg->intpin)); 2010 } 2011 2012 static int 2013 pci_modevent(module_t mod, int what, void *arg) 2014 { 2015 static struct cdev *pci_cdev; 2016 2017 switch (what) { 2018 case MOD_LOAD: 2019 STAILQ_INIT(&pci_devq); 2020 pci_generation = 0; 2021 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 2022 "pci"); 2023 pci_load_vendor_data(); 2024 break; 2025 2026 case MOD_UNLOAD: 2027 destroy_dev(pci_cdev); 2028 break; 2029 } 2030 2031 return (0); 2032 } 2033 2034 void 2035 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 2036 { 2037 int i; 2038 2039 /* 2040 * Only do header type 0 devices. Type 1 devices are bridges, 2041 * which we know need special treatment. Type 2 devices are 2042 * cardbus bridges which also require special treatment. 2043 * Other types are unknown, and we err on the side of safety 2044 * by ignoring them. 2045 */ 2046 if (dinfo->cfg.hdrtype != 0) 2047 return; 2048 2049 /* 2050 * Restore the device to full power mode. We must do this 2051 * before we restore the registers because moving from D3 to 2052 * D0 will cause the chip's BARs and some other registers to 2053 * be reset to some unknown power on reset values. Cut down 2054 * the noise on boot by doing nothing if we are already in 2055 * state D0. 2056 */ 2057 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 2058 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2059 } 2060 for (i = 0; i < dinfo->cfg.nummaps; i++) 2061 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 2062 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 2063 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 2064 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 2065 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 2066 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 2067 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 2068 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 2069 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 2070 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 2071 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 2072 } 2073 2074 void 2075 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 2076 { 2077 int i; 2078 uint32_t cls; 2079 int ps; 2080 2081 /* 2082 * Only do header type 0 devices. Type 1 devices are bridges, which 2083 * we know need special treatment. Type 2 devices are cardbus bridges 2084 * which also require special treatment. Other types are unknown, and 2085 * we err on the side of safety by ignoring them. Powering down 2086 * bridges should not be undertaken lightly. 2087 */ 2088 if (dinfo->cfg.hdrtype != 0) 2089 return; 2090 for (i = 0; i < dinfo->cfg.nummaps; i++) 2091 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 2092 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 2093 2094 /* 2095 * Some drivers apparently write to these registers w/o updating our 2096 * cached copy. No harm happens if we update the copy, so do so here 2097 * so we can restore them. The COMMAND register is modified by the 2098 * bus w/o updating the cache. This should represent the normally 2099 * writable portion of the 'defined' part of type 0 headers. In 2100 * theory we also need to save/restore the PCI capability structures 2101 * we know about, but apart from power we don't know any that are 2102 * writable. 2103 */ 2104 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 2105 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 2106 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 2107 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 2108 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 2109 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 2110 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 2111 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 2112 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 2113 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2114 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2115 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 2116 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 2117 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 2118 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 2119 2120 /* 2121 * don't set the state for display devices, base peripherals and 2122 * memory devices since bad things happen when they are powered down. 2123 * We should (a) have drivers that can easily detach and (b) use 2124 * generic drivers for these devices so that some device actually 2125 * attaches. We need to make sure that when we implement (a) we don't 2126 * power the device down on a reattach. 2127 */ 2128 cls = pci_get_class(dev); 2129 if (!setstate) 2130 return; 2131 switch (pci_do_power_nodriver) 2132 { 2133 case 0: /* NO powerdown at all */ 2134 return; 2135 case 1: /* Conservative about what to power down */ 2136 if (cls == PCIC_STORAGE) 2137 return; 2138 /*FALLTHROUGH*/ 2139 case 2: /* Agressive about what to power down */ 2140 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 2141 cls == PCIC_BASEPERIPH) 2142 return; 2143 /*FALLTHROUGH*/ 2144 case 3: /* Power down everything */ 2145 break; 2146 } 2147 /* 2148 * PCI spec says we can only go into D3 state from D0 state. 2149 * Transition from D[12] into D0 before going to D3 state. 2150 */ 2151 ps = pci_get_powerstate(dev); 2152 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 2153 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2154 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 2155 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 2156 } 2157