1 /*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_bus.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/linker.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/sysctl.h> 44 #include <sys/endian.h> 45 46 #include <vm/vm.h> 47 #include <vm/pmap.h> 48 #include <vm/vm_extern.h> 49 50 #include <sys/bus.h> 51 #include <machine/bus.h> 52 #include <sys/rman.h> 53 #include <machine/resource.h> 54 55 #include <sys/pciio.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pci_private.h> 59 60 #include "pcib_if.h" 61 #include "pci_if.h" 62 63 #ifdef __HAVE_ACPI 64 #include <contrib/dev/acpica/acpi.h> 65 #include "acpi_if.h" 66 #else 67 #define ACPI_PWR_FOR_SLEEP(x, y, z) 68 #endif 69 70 static uint32_t pci_mapbase(unsigned mapreg); 71 static int pci_maptype(unsigned mapreg); 72 static int pci_mapsize(unsigned testval); 73 static int pci_maprange(unsigned mapreg); 74 static void pci_fixancient(pcicfgregs *cfg); 75 76 static int pci_porten(device_t pcib, int b, int s, int f); 77 static int pci_memen(device_t pcib, int b, int s, int f); 78 static void pci_assign_interrupt(device_t bus, device_t dev, 79 int force_route); 80 static int pci_add_map(device_t pcib, device_t bus, device_t dev, 81 int b, int s, int f, int reg, 82 struct resource_list *rl, int force, int prefetch); 83 static int pci_probe(device_t dev); 84 static int pci_attach(device_t dev); 85 static void pci_load_vendor_data(void); 86 static int pci_describe_parse_line(char **ptr, int *vendor, 87 int *device, char **desc); 88 static char *pci_describe_device(device_t dev); 89 static int pci_modevent(module_t mod, int what, void *arg); 90 static void pci_hdrtypedata(device_t pcib, int b, int s, int f, 91 pcicfgregs *cfg); 92 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg); 93 static uint32_t pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, 94 int reg); 95 #if 0 96 static void pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, 97 int reg, uint32_t data); 98 #endif 99 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg); 100 101 static device_method_t pci_methods[] = { 102 /* Device interface */ 103 DEVMETHOD(device_probe, pci_probe), 104 DEVMETHOD(device_attach, pci_attach), 105 DEVMETHOD(device_detach, bus_generic_detach), 106 DEVMETHOD(device_shutdown, bus_generic_shutdown), 107 DEVMETHOD(device_suspend, pci_suspend), 108 DEVMETHOD(device_resume, pci_resume), 109 110 /* Bus interface */ 111 DEVMETHOD(bus_print_child, pci_print_child), 112 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 113 DEVMETHOD(bus_read_ivar, pci_read_ivar), 114 DEVMETHOD(bus_write_ivar, pci_write_ivar), 115 DEVMETHOD(bus_driver_added, pci_driver_added), 116 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 117 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 118 119 DEVMETHOD(bus_get_resource_list,pci_get_resource_list), 120 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 121 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 122 DEVMETHOD(bus_delete_resource, pci_delete_resource), 123 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 124 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 125 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 126 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 127 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method), 128 DEVMETHOD(bus_child_location_str, pci_child_location_str_method), 129 130 /* PCI interface */ 131 DEVMETHOD(pci_read_config, pci_read_config_method), 132 DEVMETHOD(pci_write_config, pci_write_config_method), 133 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method), 134 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method), 135 DEVMETHOD(pci_enable_io, pci_enable_io_method), 136 DEVMETHOD(pci_disable_io, pci_disable_io_method), 137 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method), 138 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method), 139 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method), 140 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method), 141 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method), 142 DEVMETHOD(pci_find_extcap, pci_find_extcap_method), 143 144 { 0, 0 } 145 }; 146 147 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0); 148 149 static devclass_t pci_devclass; 150 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 151 MODULE_VERSION(pci, 1); 152 153 static char *pci_vendordata; 154 static size_t pci_vendordata_size; 155 156 157 struct pci_quirk { 158 uint32_t devid; /* Vendor/device of the card */ 159 int type; 160 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ 161 int arg1; 162 int arg2; 163 }; 164 165 struct pci_quirk pci_quirks[] = { 166 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ 167 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 168 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 169 /* As does the Serverworks OSB4 (the SMBus mapping register) */ 170 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, 171 172 { 0 } 173 }; 174 175 /* map register information */ 176 #define PCI_MAPMEM 0x01 /* memory map */ 177 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 178 #define PCI_MAPPORT 0x04 /* port map */ 179 180 struct devlist pci_devq; 181 uint32_t pci_generation; 182 uint32_t pci_numdevs = 0; 183 184 /* sysctl vars */ 185 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters"); 186 187 static int pci_enable_io_modes = 1; 188 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes); 189 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW, 190 &pci_enable_io_modes, 1, 191 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\ 192 enable these bits correctly. We'd like to do this all the time, but there\n\ 193 are some peripherals that this causes problems with."); 194 195 static int pci_do_power_nodriver = 0; 196 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver); 197 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW, 198 &pci_do_power_nodriver, 0, 199 "Place a function into D3 state when no driver attaches to it. 0 means\n\ 200 disable. 1 means conservatively place devices into D3 state. 2 means\n\ 201 agressively place devices into D3 state. 3 means put absolutely everything\n\ 202 in D3 state."); 203 204 static int pci_do_power_resume = 1; 205 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume); 206 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW, 207 &pci_do_power_resume, 1, 208 "Transition from D3 -> D0 on resume."); 209 210 /* Find a device_t by bus/slot/function */ 211 212 device_t 213 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func) 214 { 215 struct pci_devinfo *dinfo; 216 217 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 218 if ((dinfo->cfg.bus == bus) && 219 (dinfo->cfg.slot == slot) && 220 (dinfo->cfg.func == func)) { 221 return (dinfo->cfg.dev); 222 } 223 } 224 225 return (NULL); 226 } 227 228 /* Find a device_t by vendor/device ID */ 229 230 device_t 231 pci_find_device(uint16_t vendor, uint16_t device) 232 { 233 struct pci_devinfo *dinfo; 234 235 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) { 236 if ((dinfo->cfg.vendor == vendor) && 237 (dinfo->cfg.device == device)) { 238 return (dinfo->cfg.dev); 239 } 240 } 241 242 return (NULL); 243 } 244 245 /* return base address of memory or port map */ 246 247 static uint32_t 248 pci_mapbase(unsigned mapreg) 249 { 250 int mask = 0x03; 251 if ((mapreg & 0x01) == 0) 252 mask = 0x0f; 253 return (mapreg & ~mask); 254 } 255 256 /* return map type of memory or port map */ 257 258 static int 259 pci_maptype(unsigned mapreg) 260 { 261 static uint8_t maptype[0x10] = { 262 PCI_MAPMEM, PCI_MAPPORT, 263 PCI_MAPMEM, 0, 264 PCI_MAPMEM, PCI_MAPPORT, 265 0, 0, 266 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 267 PCI_MAPMEM|PCI_MAPMEMP, 0, 268 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 269 0, 0, 270 }; 271 272 return maptype[mapreg & 0x0f]; 273 } 274 275 /* return log2 of map size decoded for memory or port map */ 276 277 static int 278 pci_mapsize(unsigned testval) 279 { 280 int ln2size; 281 282 testval = pci_mapbase(testval); 283 ln2size = 0; 284 if (testval != 0) { 285 while ((testval & 1) == 0) 286 { 287 ln2size++; 288 testval >>= 1; 289 } 290 } 291 return (ln2size); 292 } 293 294 /* return log2 of address range supported by map register */ 295 296 static int 297 pci_maprange(unsigned mapreg) 298 { 299 int ln2range = 0; 300 switch (mapreg & 0x07) { 301 case 0x00: 302 case 0x01: 303 case 0x05: 304 ln2range = 32; 305 break; 306 case 0x02: 307 ln2range = 20; 308 break; 309 case 0x04: 310 ln2range = 64; 311 break; 312 } 313 return (ln2range); 314 } 315 316 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 317 318 static void 319 pci_fixancient(pcicfgregs *cfg) 320 { 321 if (cfg->hdrtype != 0) 322 return; 323 324 /* PCI to PCI bridges use header type 1 */ 325 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 326 cfg->hdrtype = 1; 327 } 328 329 /* extract header type specific config data */ 330 331 static void 332 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 333 { 334 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 335 switch (cfg->hdrtype) { 336 case 0: 337 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 338 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 339 cfg->nummaps = PCI_MAXMAPS_0; 340 break; 341 case 1: 342 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 343 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 344 cfg->nummaps = PCI_MAXMAPS_1; 345 break; 346 case 2: 347 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 348 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 349 cfg->nummaps = PCI_MAXMAPS_2; 350 break; 351 } 352 #undef REG 353 } 354 355 /* read configuration header into pcicfgregs structure */ 356 struct pci_devinfo * 357 pci_read_device(device_t pcib, int b, int s, int f, size_t size) 358 { 359 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 360 pcicfgregs *cfg = NULL; 361 struct pci_devinfo *devlist_entry; 362 struct devlist *devlist_head; 363 364 devlist_head = &pci_devq; 365 366 devlist_entry = NULL; 367 368 if (REG(PCIR_DEVVENDOR, 4) != -1) { 369 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); 370 if (devlist_entry == NULL) 371 return (NULL); 372 373 cfg = &devlist_entry->cfg; 374 375 cfg->bus = b; 376 cfg->slot = s; 377 cfg->func = f; 378 cfg->vendor = REG(PCIR_VENDOR, 2); 379 cfg->device = REG(PCIR_DEVICE, 2); 380 cfg->cmdreg = REG(PCIR_COMMAND, 2); 381 cfg->statreg = REG(PCIR_STATUS, 2); 382 cfg->baseclass = REG(PCIR_CLASS, 1); 383 cfg->subclass = REG(PCIR_SUBCLASS, 1); 384 cfg->progif = REG(PCIR_PROGIF, 1); 385 cfg->revid = REG(PCIR_REVID, 1); 386 cfg->hdrtype = REG(PCIR_HDRTYPE, 1); 387 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 388 cfg->lattimer = REG(PCIR_LATTIMER, 1); 389 cfg->intpin = REG(PCIR_INTPIN, 1); 390 cfg->intline = REG(PCIR_INTLINE, 1); 391 392 cfg->mingnt = REG(PCIR_MINGNT, 1); 393 cfg->maxlat = REG(PCIR_MAXLAT, 1); 394 395 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 396 cfg->hdrtype &= ~PCIM_MFDEV; 397 398 pci_fixancient(cfg); 399 pci_hdrtypedata(pcib, b, s, f, cfg); 400 401 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) 402 pci_read_extcap(pcib, cfg); 403 404 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 405 406 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 407 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 408 devlist_entry->conf.pc_sel.pc_func = cfg->func; 409 devlist_entry->conf.pc_hdr = cfg->hdrtype; 410 411 devlist_entry->conf.pc_subvendor = cfg->subvendor; 412 devlist_entry->conf.pc_subdevice = cfg->subdevice; 413 devlist_entry->conf.pc_vendor = cfg->vendor; 414 devlist_entry->conf.pc_device = cfg->device; 415 416 devlist_entry->conf.pc_class = cfg->baseclass; 417 devlist_entry->conf.pc_subclass = cfg->subclass; 418 devlist_entry->conf.pc_progif = cfg->progif; 419 devlist_entry->conf.pc_revid = cfg->revid; 420 421 pci_numdevs++; 422 pci_generation++; 423 } 424 return (devlist_entry); 425 #undef REG 426 } 427 428 static void 429 pci_read_extcap(device_t pcib, pcicfgregs *cfg) 430 { 431 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w) 432 int ptr, nextptr, ptrptr; 433 434 switch (cfg->hdrtype & PCIM_HDRTYPE) { 435 case 0: 436 ptrptr = PCIR_CAP_PTR; 437 break; 438 case 2: 439 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */ 440 break; 441 default: 442 return; /* no extended capabilities support */ 443 } 444 nextptr = REG(ptrptr, 1); /* sanity check? */ 445 446 /* 447 * Read capability entries. 448 */ 449 while (nextptr != 0) { 450 /* Sanity check */ 451 if (nextptr > 255) { 452 printf("illegal PCI extended capability offset %d\n", 453 nextptr); 454 return; 455 } 456 /* Find the next entry */ 457 ptr = nextptr; 458 nextptr = REG(ptr + PCICAP_NEXTPTR, 1); 459 460 /* Process this entry */ 461 switch (REG(ptr + PCICAP_ID, 1)) { 462 case PCIY_PMG: /* PCI power management */ 463 if (cfg->pp.pp_cap == 0) { 464 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2); 465 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS; 466 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR; 467 if ((nextptr - ptr) > PCIR_POWER_DATA) 468 cfg->pp.pp_data = ptr + PCIR_POWER_DATA; 469 } 470 break; 471 case PCIY_MSI: /* PCI MSI */ 472 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2); 473 if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) 474 cfg->msi.msi_data = PCIR_MSI_DATA_64BIT; 475 else 476 cfg->msi.msi_data = PCIR_MSI_DATA; 477 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl & 478 PCIM_MSICTRL_MMC_MASK)>>1); 479 break; 480 case PCIY_VPD: /* PCI Vital Product Data */ 481 cfg->vpd.vpd_reg = ptr; 482 pci_read_vpd(pcib, cfg); 483 break; 484 default: 485 break; 486 } 487 } 488 /* REG use carry through to next functions */ 489 } 490 491 /* 492 * PCI Vital Product Data 493 */ 494 static uint32_t 495 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg) 496 { 497 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w) 498 499 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 500 501 WREG(cfg->vpd.vpd_reg + 2, reg, 2); 502 while ((REG(cfg->vpd.vpd_reg + 2, 2) & 0x8000) != 0x8000) 503 DELAY(1); /* limit looping */ 504 505 return REG(cfg->vpd.vpd_reg + 4, 4); 506 } 507 508 #if 0 509 static void 510 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data) 511 { 512 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned")); 513 514 WREG(cfg->vpd.vpd_reg + 4, data, 4); 515 WREG(cfg->vpd.vpd_reg + 2, reg | 0x8000, 2); 516 while ((REG(cfg->vpd.vpd_reg + 2, 2) & 0x8000) == 0x8000) 517 DELAY(1); /* limit looping */ 518 519 return; 520 } 521 #endif 522 #undef WREG 523 524 struct vpd_readstate { 525 device_t pcib; 526 pcicfgregs *cfg; 527 uint32_t val; 528 int bytesinval; 529 int off; 530 uint8_t cksum; 531 }; 532 533 static uint8_t 534 vpd_nextbyte(struct vpd_readstate *vrs) 535 { 536 uint8_t byte; 537 538 if (vrs->bytesinval == 0) { 539 vrs->val = le32toh(pci_read_vpd_reg(vrs->pcib, vrs->cfg, 540 vrs->off)); 541 vrs->off += 4; 542 byte = vrs->val & 0xff; 543 vrs->bytesinval = 3; 544 } else { 545 vrs->val = vrs->val >> 8; 546 byte = vrs->val & 0xff; 547 vrs->bytesinval--; 548 } 549 550 vrs->cksum += byte; 551 return byte; 552 } 553 554 static void 555 pci_read_vpd(device_t pcib, pcicfgregs *cfg) 556 { 557 struct vpd_readstate vrs; 558 int state; 559 int name; 560 int remain; 561 int end; 562 int i; 563 uint8_t byte; 564 int alloc, off; /* alloc/off for RO/W arrays */ 565 int cksumvalid; 566 int dflen; 567 568 /* init vpd reader */ 569 vrs.bytesinval = 0; 570 vrs.off = 0; 571 vrs.pcib = pcib; 572 vrs.cfg = cfg; 573 vrs.cksum = 0; 574 575 state = 0; 576 name = remain = i = 0; /* shut up stupid gcc */ 577 alloc = off = 0; /* shut up stupid gcc */ 578 dflen = 0; /* shut up stupid gcc */ 579 end = 0; 580 cksumvalid = -1; 581 for (; !end;) { 582 byte = vpd_nextbyte(&vrs); 583 #if 0 584 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \ 585 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val, 586 vrs.off, vrs.bytesinval, byte, state, remain, name, i); 587 #endif 588 switch (state) { 589 case 0: /* item name */ 590 if (byte & 0x80) { 591 remain = vpd_nextbyte(&vrs); 592 remain |= vpd_nextbyte(&vrs) << 8; 593 if (remain > (0x7f*4 - vrs.off)) { 594 end = 1; 595 printf( 596 "pci%d:%d:%d: invalid vpd data, remain %#x\n", 597 cfg->bus, cfg->slot, cfg->func, 598 remain); 599 } 600 name = byte & 0x7f; 601 } else { 602 remain = byte & 0x7; 603 name = (byte >> 3) & 0xf; 604 } 605 switch (name) { 606 case 0x2: /* String */ 607 cfg->vpd.vpd_ident = malloc(remain + 1, 608 M_DEVBUF, M_WAITOK); 609 i = 0; 610 state = 1; 611 break; 612 case 0xf: /* End */ 613 end = 1; 614 state = -1; 615 break; 616 case 0x10: /* VPD-R */ 617 alloc = 8; 618 off = 0; 619 cfg->vpd.vpd_ros = malloc(alloc * 620 sizeof *cfg->vpd.vpd_ros, M_DEVBUF, 621 M_WAITOK); 622 state = 2; 623 break; 624 case 0x11: /* VPD-W */ 625 alloc = 8; 626 off = 0; 627 cfg->vpd.vpd_w = malloc(alloc * 628 sizeof *cfg->vpd.vpd_w, M_DEVBUF, 629 M_WAITOK); 630 state = 5; 631 break; 632 default: /* XXX - unimplemented */ 633 state = 4; 634 break; 635 } 636 break; 637 638 case 1: /* Identifier String */ 639 cfg->vpd.vpd_ident[i++] = byte; 640 remain--; 641 if (remain == 0) { 642 cfg->vpd.vpd_ident[i] = '\0'; 643 state = 0; 644 } 645 break; 646 647 case 2: /* VPD-R Keyword Header */ 648 if (off == alloc) { 649 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 650 (alloc *= 2) * sizeof *cfg->vpd.vpd_ros, 651 M_DEVBUF, M_WAITOK); 652 } 653 cfg->vpd.vpd_ros[off].keyword[0] = byte; 654 cfg->vpd.vpd_ros[off].keyword[1] = vpd_nextbyte(&vrs); 655 dflen = vpd_nextbyte(&vrs); 656 cfg->vpd.vpd_ros[off].value = malloc((dflen + 1) * 657 sizeof *cfg->vpd.vpd_ros[off].value, 658 M_DEVBUF, M_WAITOK); 659 remain -= 3; 660 i = 0; 661 state = 3; 662 break; 663 664 case 3: /* VPD-R Keyword Value */ 665 cfg->vpd.vpd_ros[off].value[i++] = byte; 666 if (strncmp(cfg->vpd.vpd_ros[off].keyword, 667 "RV", 2) == 0 && cksumvalid == -1) { 668 if (vrs.cksum == 0) 669 cksumvalid = 1; 670 else { 671 printf( 672 "pci%d:%d:%d: bad VPD cksum, remain %hhu\n", 673 cfg->bus, cfg->slot, cfg->func, 674 vrs.cksum); 675 cksumvalid = 0; 676 } 677 } 678 dflen--; 679 remain--; 680 if (dflen == 0) 681 cfg->vpd.vpd_ros[off++].value[i++] = '\0'; 682 if (dflen == 0 && remain == 0) { 683 cfg->vpd.vpd_rocnt = off; 684 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros, 685 off * sizeof *cfg->vpd.vpd_ros, 686 M_DEVBUF, M_WAITOK); 687 state = 0; 688 } else if (dflen == 0) 689 state = 2; 690 break; 691 692 case 4: 693 remain--; 694 if (remain == 0) 695 state = 0; 696 break; 697 698 case 5: /* VPD-W Keyword Header */ 699 if (off == alloc) { 700 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 701 (alloc *= 2) * sizeof *cfg->vpd.vpd_w, 702 M_DEVBUF, M_WAITOK); 703 } 704 cfg->vpd.vpd_w[off].keyword[0] = byte; 705 cfg->vpd.vpd_w[off].keyword[1] = vpd_nextbyte(&vrs); 706 cfg->vpd.vpd_w[off].len = dflen = vpd_nextbyte(&vrs); 707 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval; 708 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) * 709 sizeof *cfg->vpd.vpd_w[off].value, 710 M_DEVBUF, M_WAITOK); 711 remain -= 3; 712 i = 0; 713 state = 6; 714 break; 715 716 case 6: /* VPD-W Keyword Value */ 717 cfg->vpd.vpd_w[off].value[i++] = byte; 718 dflen--; 719 remain--; 720 if (dflen == 0) 721 cfg->vpd.vpd_w[off++].value[i++] = '\0'; 722 if (dflen == 0 && remain == 0) { 723 cfg->vpd.vpd_wcnt = off; 724 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w, 725 off * sizeof *cfg->vpd.vpd_w, 726 M_DEVBUF, M_WAITOK); 727 state = 0; 728 } else if (dflen == 0) 729 state = 5; 730 break; 731 732 default: 733 printf("pci%d:%d:%d: invalid state: %d\n", 734 cfg->bus, cfg->slot, cfg->func, state); 735 end = 1; 736 break; 737 } 738 } 739 #undef REG 740 } 741 742 int 743 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr) 744 { 745 struct pci_devinfo *dinfo = device_get_ivars(child); 746 pcicfgregs *cfg = &dinfo->cfg; 747 748 *identptr = cfg->vpd.vpd_ident; 749 750 if (*identptr == NULL) 751 return ENXIO; 752 753 return 0; 754 } 755 756 int 757 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw, 758 const char **vptr) 759 { 760 struct pci_devinfo *dinfo = device_get_ivars(child); 761 pcicfgregs *cfg = &dinfo->cfg; 762 int i; 763 764 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) 765 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword, 766 sizeof cfg->vpd.vpd_ros[i].keyword) == 0) { 767 *vptr = cfg->vpd.vpd_ros[i].value; 768 } 769 770 if (i != cfg->vpd.vpd_rocnt) 771 return 0; 772 773 *vptr = NULL; 774 return ENXIO; 775 } 776 777 /* 778 * Return the offset in configuration space of the requested extended 779 * capability entry or 0 if the specified capability was not found. 780 */ 781 int 782 pci_find_extcap_method(device_t dev, device_t child, int capability, 783 int *capreg) 784 { 785 struct pci_devinfo *dinfo = device_get_ivars(child); 786 pcicfgregs *cfg = &dinfo->cfg; 787 u_int32_t status; 788 u_int8_t ptr; 789 790 /* 791 * Check the CAP_LIST bit of the PCI status register first. 792 */ 793 status = pci_read_config(child, PCIR_STATUS, 2); 794 if (!(status & PCIM_STATUS_CAPPRESENT)) 795 return (ENXIO); 796 797 /* 798 * Determine the start pointer of the capabilities list. 799 */ 800 switch (cfg->hdrtype & PCIM_HDRTYPE) { 801 case 0: 802 ptr = PCIR_CAP_PTR; 803 break; 804 case 2: 805 ptr = PCIR_CAP_PTR_2; 806 break; 807 default: 808 /* XXX: panic? */ 809 return (ENXIO); /* no extended capabilities support */ 810 } 811 ptr = pci_read_config(child, ptr, 1); 812 813 /* 814 * Traverse the capabilities list. 815 */ 816 while (ptr != 0) { 817 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) { 818 if (capreg != NULL) 819 *capreg = ptr; 820 return (0); 821 } 822 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1); 823 } 824 825 return (ENOENT); 826 } 827 828 /* free pcicfgregs structure and all depending data structures */ 829 830 int 831 pci_freecfg(struct pci_devinfo *dinfo) 832 { 833 struct devlist *devlist_head; 834 int i; 835 836 devlist_head = &pci_devq; 837 838 if (dinfo->cfg.vpd.vpd_reg) { 839 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF); 840 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++) 841 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF); 842 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF); 843 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++) 844 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF); 845 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF); 846 } 847 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 848 free(dinfo, M_DEVBUF); 849 850 /* increment the generation count */ 851 pci_generation++; 852 853 /* we're losing one device */ 854 pci_numdevs--; 855 return (0); 856 } 857 858 /* 859 * PCI power manangement 860 */ 861 int 862 pci_set_powerstate_method(device_t dev, device_t child, int state) 863 { 864 struct pci_devinfo *dinfo = device_get_ivars(child); 865 pcicfgregs *cfg = &dinfo->cfg; 866 uint16_t status; 867 int result, oldstate, highest, delay; 868 869 if (cfg->pp.pp_cap == 0) 870 return (EOPNOTSUPP); 871 872 /* 873 * Optimize a no state change request away. While it would be OK to 874 * write to the hardware in theory, some devices have shown odd 875 * behavior when going from D3 -> D3. 876 */ 877 oldstate = pci_get_powerstate(child); 878 if (oldstate == state) 879 return (0); 880 881 /* 882 * The PCI power management specification states that after a state 883 * transition between PCI power states, system software must 884 * guarantee a minimal delay before the function accesses the device. 885 * Compute the worst case delay that we need to guarantee before we 886 * access the device. Many devices will be responsive much more 887 * quickly than this delay, but there are some that don't respond 888 * instantly to state changes. Transitions to/from D3 state require 889 * 10ms, while D2 requires 200us, and D0/1 require none. The delay 890 * is done below with DELAY rather than a sleeper function because 891 * this function can be called from contexts where we cannot sleep. 892 */ 893 highest = (oldstate > state) ? oldstate : state; 894 if (highest == PCI_POWERSTATE_D3) 895 delay = 10000; 896 else if (highest == PCI_POWERSTATE_D2) 897 delay = 200; 898 else 899 delay = 0; 900 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2) 901 & ~PCIM_PSTAT_DMASK; 902 result = 0; 903 switch (state) { 904 case PCI_POWERSTATE_D0: 905 status |= PCIM_PSTAT_D0; 906 break; 907 case PCI_POWERSTATE_D1: 908 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0) 909 return (EOPNOTSUPP); 910 status |= PCIM_PSTAT_D1; 911 break; 912 case PCI_POWERSTATE_D2: 913 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0) 914 return (EOPNOTSUPP); 915 status |= PCIM_PSTAT_D2; 916 break; 917 case PCI_POWERSTATE_D3: 918 status |= PCIM_PSTAT_D3; 919 break; 920 default: 921 return (EINVAL); 922 } 923 924 if (bootverbose) 925 printf( 926 "pci%d:%d:%d: Transition from D%d to D%d\n", 927 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func, 928 oldstate, state); 929 930 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2); 931 if (delay) 932 DELAY(delay); 933 return (0); 934 } 935 936 int 937 pci_get_powerstate_method(device_t dev, device_t child) 938 { 939 struct pci_devinfo *dinfo = device_get_ivars(child); 940 pcicfgregs *cfg = &dinfo->cfg; 941 uint16_t status; 942 int result; 943 944 if (cfg->pp.pp_cap != 0) { 945 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2); 946 switch (status & PCIM_PSTAT_DMASK) { 947 case PCIM_PSTAT_D0: 948 result = PCI_POWERSTATE_D0; 949 break; 950 case PCIM_PSTAT_D1: 951 result = PCI_POWERSTATE_D1; 952 break; 953 case PCIM_PSTAT_D2: 954 result = PCI_POWERSTATE_D2; 955 break; 956 case PCIM_PSTAT_D3: 957 result = PCI_POWERSTATE_D3; 958 break; 959 default: 960 result = PCI_POWERSTATE_UNKNOWN; 961 break; 962 } 963 } else { 964 /* No support, device is always at D0 */ 965 result = PCI_POWERSTATE_D0; 966 } 967 return (result); 968 } 969 970 /* 971 * Some convenience functions for PCI device drivers. 972 */ 973 974 static __inline void 975 pci_set_command_bit(device_t dev, device_t child, uint16_t bit) 976 { 977 uint16_t command; 978 979 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 980 command |= bit; 981 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 982 } 983 984 static __inline void 985 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit) 986 { 987 uint16_t command; 988 989 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 990 command &= ~bit; 991 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2); 992 } 993 994 int 995 pci_enable_busmaster_method(device_t dev, device_t child) 996 { 997 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 998 return (0); 999 } 1000 1001 int 1002 pci_disable_busmaster_method(device_t dev, device_t child) 1003 { 1004 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN); 1005 return (0); 1006 } 1007 1008 int 1009 pci_enable_io_method(device_t dev, device_t child, int space) 1010 { 1011 uint16_t command; 1012 uint16_t bit; 1013 char *error; 1014 1015 bit = 0; 1016 error = NULL; 1017 1018 switch(space) { 1019 case SYS_RES_IOPORT: 1020 bit = PCIM_CMD_PORTEN; 1021 error = "port"; 1022 break; 1023 case SYS_RES_MEMORY: 1024 bit = PCIM_CMD_MEMEN; 1025 error = "memory"; 1026 break; 1027 default: 1028 return (EINVAL); 1029 } 1030 pci_set_command_bit(dev, child, bit); 1031 /* Some devices seem to need a brief stall here, what do to? */ 1032 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1033 if (command & bit) 1034 return (0); 1035 device_printf(child, "failed to enable %s mapping!\n", error); 1036 return (ENXIO); 1037 } 1038 1039 int 1040 pci_disable_io_method(device_t dev, device_t child, int space) 1041 { 1042 uint16_t command; 1043 uint16_t bit; 1044 char *error; 1045 1046 bit = 0; 1047 error = NULL; 1048 1049 switch(space) { 1050 case SYS_RES_IOPORT: 1051 bit = PCIM_CMD_PORTEN; 1052 error = "port"; 1053 break; 1054 case SYS_RES_MEMORY: 1055 bit = PCIM_CMD_MEMEN; 1056 error = "memory"; 1057 break; 1058 default: 1059 return (EINVAL); 1060 } 1061 pci_clear_command_bit(dev, child, bit); 1062 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2); 1063 if (command & bit) { 1064 device_printf(child, "failed to disable %s mapping!\n", error); 1065 return (ENXIO); 1066 } 1067 return (0); 1068 } 1069 1070 /* 1071 * New style pci driver. Parent device is either a pci-host-bridge or a 1072 * pci-pci-bridge. Both kinds are represented by instances of pcib. 1073 */ 1074 1075 void 1076 pci_print_verbose(struct pci_devinfo *dinfo) 1077 { 1078 int i; 1079 1080 if (bootverbose) { 1081 pcicfgregs *cfg = &dinfo->cfg; 1082 1083 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 1084 cfg->vendor, cfg->device, cfg->revid); 1085 printf("\tbus=%d, slot=%d, func=%d\n", 1086 cfg->bus, cfg->slot, cfg->func); 1087 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 1088 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype, 1089 cfg->mfdev); 1090 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 1091 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 1092 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 1093 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt, 1094 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 1095 if (cfg->intpin > 0) 1096 printf("\tintpin=%c, irq=%d\n", 1097 cfg->intpin +'a' -1, cfg->intline); 1098 if (cfg->pp.pp_cap) { 1099 uint16_t status; 1100 1101 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2); 1102 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n", 1103 cfg->pp.pp_cap & PCIM_PCAP_SPEC, 1104 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "", 1105 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "", 1106 status & PCIM_PSTAT_DMASK); 1107 } 1108 if (cfg->vpd.vpd_reg) { 1109 printf("\tVPD Ident: %s\n", cfg->vpd.vpd_ident); 1110 for (i = 0; i < cfg->vpd.vpd_rocnt; i++) { 1111 struct vpd_readonly *vrop; 1112 vrop = &cfg->vpd.vpd_ros[i]; 1113 if (strncmp("CP", vrop->keyword, 2) == 0) 1114 printf("CP: id %d, BAR%d, off %#x\n", 1115 vrop->value[0], vrop->value[1], 1116 le16toh( 1117 *(uint16_t *)&vrop->value[2])); 1118 else if (strncmp("RV", vrop->keyword, 2) == 0) 1119 printf("RV: %#hhx\n", vrop->value[0]); 1120 else 1121 printf("\t%.2s: %s\n", vrop->keyword, 1122 vrop->value); 1123 } 1124 for (i = 0; i < cfg->vpd.vpd_wcnt; i++) { 1125 struct vpd_write *vwp; 1126 vwp = &cfg->vpd.vpd_w[i]; 1127 if (strncmp("RW", vwp->keyword, 2) != 0) 1128 printf("\t%.2s(%#x-%#x): %s\n", 1129 vwp->keyword, vwp->start, 1130 vwp->start + vwp->len, vwp->value); 1131 } 1132 } 1133 if (cfg->msi.msi_data) { 1134 int ctrl; 1135 1136 ctrl = cfg->msi.msi_ctrl; 1137 printf("\tMSI supports %d message%s%s%s\n", 1138 cfg->msi.msi_msgnum, 1139 (cfg->msi.msi_msgnum == 1) ? "" : "s", 1140 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 1141 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":""); 1142 } 1143 } 1144 } 1145 1146 static int 1147 pci_porten(device_t pcib, int b, int s, int f) 1148 { 1149 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1150 & PCIM_CMD_PORTEN) != 0; 1151 } 1152 1153 static int 1154 pci_memen(device_t pcib, int b, int s, int f) 1155 { 1156 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 1157 & PCIM_CMD_MEMEN) != 0; 1158 } 1159 1160 /* 1161 * Add a resource based on a pci map register. Return 1 if the map 1162 * register is a 32bit map register or 2 if it is a 64bit register. 1163 */ 1164 static int 1165 pci_add_map(device_t pcib, device_t bus, device_t dev, 1166 int b, int s, int f, int reg, struct resource_list *rl, int force, 1167 int prefetch) 1168 { 1169 uint32_t map; 1170 uint64_t base; 1171 uint64_t start, end, count; 1172 uint8_t ln2size; 1173 uint8_t ln2range; 1174 uint32_t testval; 1175 uint16_t cmd; 1176 int type; 1177 int barlen; 1178 struct resource *res; 1179 1180 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1181 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 1182 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 1183 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 1184 1185 if (pci_maptype(map) & PCI_MAPMEM) 1186 type = SYS_RES_MEMORY; 1187 else 1188 type = SYS_RES_IOPORT; 1189 ln2size = pci_mapsize(testval); 1190 ln2range = pci_maprange(testval); 1191 base = pci_mapbase(map); 1192 barlen = ln2range == 64 ? 2 : 1; 1193 1194 /* 1195 * For I/O registers, if bottom bit is set, and the next bit up 1196 * isn't clear, we know we have a BAR that doesn't conform to the 1197 * spec, so ignore it. Also, sanity check the size of the data 1198 * areas to the type of memory involved. Memory must be at least 1199 * 16 bytes in size, while I/O ranges must be at least 4. 1200 */ 1201 if ((testval & 0x1) == 0x1 && 1202 (testval & 0x2) != 0) 1203 return (barlen); 1204 if ((type == SYS_RES_MEMORY && ln2size < 4) || 1205 (type == SYS_RES_IOPORT && ln2size < 2)) 1206 return (barlen); 1207 1208 if (ln2range == 64) 1209 /* Read the other half of a 64bit map register */ 1210 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 1211 1212 if (bootverbose) { 1213 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 1214 reg, pci_maptype(map), ln2range, 1215 (unsigned int) base, ln2size); 1216 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1217 printf(", port disabled\n"); 1218 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1219 printf(", memory disabled\n"); 1220 else 1221 printf(", enabled\n"); 1222 } 1223 1224 /* 1225 * If base is 0, then we have problems. It is best to ignore 1226 * such entries for the moment. These will be allocated later if 1227 * the driver specifically requests them. However, some 1228 * removable busses look better when all resources are allocated, 1229 * so allow '0' to be overriden. 1230 * 1231 * Similarly treat maps whose values is the same as the test value 1232 * read back. These maps have had all f's written to them by the 1233 * BIOS in an attempt to disable the resources. 1234 */ 1235 if (!force && (base == 0 || map == testval)) 1236 return (barlen); 1237 1238 /* 1239 * This code theoretically does the right thing, but has 1240 * undesirable side effects in some cases where peripherals 1241 * respond oddly to having these bits enabled. Let the user 1242 * be able to turn them off (since pci_enable_io_modes is 1 by 1243 * default). 1244 */ 1245 if (pci_enable_io_modes) { 1246 /* Turn on resources that have been left off by a lazy BIOS */ 1247 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 1248 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1249 cmd |= PCIM_CMD_PORTEN; 1250 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1251 } 1252 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 1253 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1254 cmd |= PCIM_CMD_MEMEN; 1255 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1256 } 1257 } else { 1258 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1259 return (barlen); 1260 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1261 return (barlen); 1262 } 1263 1264 count = 1 << ln2size; 1265 if (base == 0 || base == pci_mapbase(testval)) { 1266 start = 0; /* Let the parent deside */ 1267 end = ~0ULL; 1268 } else { 1269 start = base; 1270 end = base + (1 << ln2size) - 1; 1271 } 1272 resource_list_add(rl, type, reg, start, end, count); 1273 1274 /* 1275 * Not quite sure what to do on failure of allocating the resource 1276 * since I can postulate several right answers. 1277 */ 1278 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count, 1279 prefetch ? RF_PREFETCHABLE : 0); 1280 if (res != NULL) 1281 pci_write_config(dev, reg, rman_get_start(res), 4); 1282 return (barlen); 1283 } 1284 1285 /* 1286 * For ATA devices we need to decide early what addressing mode to use. 1287 * Legacy demands that the primary and secondary ATA ports sits on the 1288 * same addresses that old ISA hardware did. This dictates that we use 1289 * those addresses and ignore the BAR's if we cannot set PCI native 1290 * addressing mode. 1291 */ 1292 static void 1293 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, 1294 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask) 1295 { 1296 int rid, type, progif; 1297 #if 0 1298 /* if this device supports PCI native addressing use it */ 1299 progif = pci_read_config(dev, PCIR_PROGIF, 1); 1300 if ((progif & 0x8a) == 0x8a) { 1301 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) && 1302 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) { 1303 printf("Trying ATA native PCI addressing mode\n"); 1304 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1); 1305 } 1306 } 1307 #endif 1308 progif = pci_read_config(dev, PCIR_PROGIF, 1); 1309 type = SYS_RES_IOPORT; 1310 if (progif & PCIP_STORAGE_IDE_MODEPRIM) { 1311 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force, 1312 prefetchmask & (1 << 0)); 1313 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force, 1314 prefetchmask & (1 << 1)); 1315 } else { 1316 rid = PCIR_BAR(0); 1317 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8); 1318 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8, 1319 0); 1320 rid = PCIR_BAR(1); 1321 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1); 1322 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1, 1323 0); 1324 } 1325 if (progif & PCIP_STORAGE_IDE_MODESEC) { 1326 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force, 1327 prefetchmask & (1 << 2)); 1328 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force, 1329 prefetchmask & (1 << 3)); 1330 } else { 1331 rid = PCIR_BAR(2); 1332 resource_list_add(rl, type, rid, 0x170, 0x177, 8); 1333 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8, 1334 0); 1335 rid = PCIR_BAR(3); 1336 resource_list_add(rl, type, rid, 0x376, 0x376, 1); 1337 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1, 1338 0); 1339 } 1340 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force, 1341 prefetchmask & (1 << 4)); 1342 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force, 1343 prefetchmask & (1 << 5)); 1344 } 1345 1346 static void 1347 pci_assign_interrupt(device_t bus, device_t dev, int force_route) 1348 { 1349 struct pci_devinfo *dinfo = device_get_ivars(dev); 1350 pcicfgregs *cfg = &dinfo->cfg; 1351 char tunable_name[64]; 1352 int irq; 1353 1354 /* Has to have an intpin to have an interrupt. */ 1355 if (cfg->intpin == 0) 1356 return; 1357 1358 /* Let the user override the IRQ with a tunable. */ 1359 irq = PCI_INVALID_IRQ; 1360 snprintf(tunable_name, sizeof(tunable_name), "hw.pci%d.%d.INT%c.irq", 1361 cfg->bus, cfg->slot, cfg->intpin + 'A' - 1); 1362 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0)) 1363 irq = PCI_INVALID_IRQ; 1364 1365 /* 1366 * If we didn't get an IRQ via the tunable, then we either use the 1367 * IRQ value in the intline register or we ask the bus to route an 1368 * interrupt for us. If force_route is true, then we only use the 1369 * value in the intline register if the bus was unable to assign an 1370 * IRQ. 1371 */ 1372 if (!PCI_INTERRUPT_VALID(irq)) { 1373 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route) 1374 irq = PCI_ASSIGN_INTERRUPT(bus, dev); 1375 if (!PCI_INTERRUPT_VALID(irq)) 1376 irq = cfg->intline; 1377 } 1378 1379 /* If after all that we don't have an IRQ, just bail. */ 1380 if (!PCI_INTERRUPT_VALID(irq)) 1381 return; 1382 1383 /* Update the config register if it changed. */ 1384 if (irq != cfg->intline) { 1385 cfg->intline = irq; 1386 pci_write_config(dev, PCIR_INTLINE, irq, 1); 1387 } 1388 1389 /* Add this IRQ as rid 0 interrupt resource. */ 1390 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1); 1391 } 1392 1393 void 1394 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask) 1395 { 1396 device_t pcib; 1397 struct pci_devinfo *dinfo = device_get_ivars(dev); 1398 pcicfgregs *cfg = &dinfo->cfg; 1399 struct resource_list *rl = &dinfo->resources; 1400 struct pci_quirk *q; 1401 int b, i, f, s; 1402 1403 pcib = device_get_parent(bus); 1404 1405 b = cfg->bus; 1406 s = cfg->slot; 1407 f = cfg->func; 1408 1409 /* ATA devices needs special map treatment */ 1410 if ((pci_get_class(dev) == PCIC_STORAGE) && 1411 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) && 1412 (pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV)) 1413 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask); 1414 else 1415 for (i = 0; i < cfg->nummaps;) 1416 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), 1417 rl, force, prefetchmask & (1 << i)); 1418 1419 /* 1420 * Add additional, quirked resources. 1421 */ 1422 for (q = &pci_quirks[0]; q->devid; q++) { 1423 if (q->devid == ((cfg->device << 16) | cfg->vendor) 1424 && q->type == PCI_QUIRK_MAP_REG) 1425 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl, 1426 force, 0); 1427 } 1428 1429 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { 1430 #ifdef __PCI_REROUTE_INTERRUPT 1431 /* 1432 * Try to re-route interrupts. Sometimes the BIOS or 1433 * firmware may leave bogus values in these registers. 1434 * If the re-route fails, then just stick with what we 1435 * have. 1436 */ 1437 pci_assign_interrupt(bus, dev, 1); 1438 #else 1439 pci_assign_interrupt(bus, dev, 0); 1440 #endif 1441 } 1442 } 1443 1444 void 1445 pci_add_children(device_t dev, int busno, size_t dinfo_size) 1446 { 1447 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w) 1448 device_t pcib = device_get_parent(dev); 1449 struct pci_devinfo *dinfo; 1450 int maxslots; 1451 int s, f, pcifunchigh; 1452 uint8_t hdrtype; 1453 1454 KASSERT(dinfo_size >= sizeof(struct pci_devinfo), 1455 ("dinfo_size too small")); 1456 maxslots = PCIB_MAXSLOTS(pcib); 1457 for (s = 0; s <= maxslots; s++) { 1458 pcifunchigh = 0; 1459 f = 0; 1460 DELAY(1); 1461 hdrtype = REG(PCIR_HDRTYPE, 1); 1462 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 1463 continue; 1464 if (hdrtype & PCIM_MFDEV) 1465 pcifunchigh = PCI_FUNCMAX; 1466 for (f = 0; f <= pcifunchigh; f++) { 1467 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size); 1468 if (dinfo != NULL) { 1469 pci_add_child(dev, dinfo); 1470 } 1471 } 1472 } 1473 #undef REG 1474 } 1475 1476 void 1477 pci_add_child(device_t bus, struct pci_devinfo *dinfo) 1478 { 1479 dinfo->cfg.dev = device_add_child(bus, NULL, -1); 1480 device_set_ivars(dinfo->cfg.dev, dinfo); 1481 resource_list_init(&dinfo->resources); 1482 pci_cfg_save(dinfo->cfg.dev, dinfo, 0); 1483 pci_cfg_restore(dinfo->cfg.dev, dinfo); 1484 pci_print_verbose(dinfo); 1485 pci_add_resources(bus, dinfo->cfg.dev, 0, 0); 1486 } 1487 1488 static int 1489 pci_probe(device_t dev) 1490 { 1491 1492 device_set_desc(dev, "PCI bus"); 1493 1494 /* Allow other subclasses to override this driver. */ 1495 return (-1000); 1496 } 1497 1498 static int 1499 pci_attach(device_t dev) 1500 { 1501 int busno; 1502 1503 /* 1504 * Since there can be multiple independantly numbered PCI 1505 * busses on systems with multiple PCI domains, we can't use 1506 * the unit number to decide which bus we are probing. We ask 1507 * the parent pcib what our bus number is. 1508 */ 1509 busno = pcib_get_bus(dev); 1510 if (bootverbose) 1511 device_printf(dev, "physical bus=%d\n", busno); 1512 1513 pci_add_children(dev, busno, sizeof(struct pci_devinfo)); 1514 1515 return (bus_generic_attach(dev)); 1516 } 1517 1518 int 1519 pci_suspend(device_t dev) 1520 { 1521 int dstate, error, i, numdevs; 1522 device_t acpi_dev, child, *devlist; 1523 struct pci_devinfo *dinfo; 1524 1525 /* 1526 * Save the PCI configuration space for each child and set the 1527 * device in the appropriate power state for this sleep state. 1528 */ 1529 acpi_dev = NULL; 1530 if (pci_do_power_resume) 1531 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1532 device_get_children(dev, &devlist, &numdevs); 1533 for (i = 0; i < numdevs; i++) { 1534 child = devlist[i]; 1535 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1536 pci_cfg_save(child, dinfo, 0); 1537 } 1538 1539 /* Suspend devices before potentially powering them down. */ 1540 error = bus_generic_suspend(dev); 1541 if (error) { 1542 free(devlist, M_TEMP); 1543 return (error); 1544 } 1545 1546 /* 1547 * Always set the device to D3. If ACPI suggests a different 1548 * power state, use it instead. If ACPI is not present, the 1549 * firmware is responsible for managing device power. Skip 1550 * children who aren't attached since they are powered down 1551 * separately. Only manage type 0 devices for now. 1552 */ 1553 for (i = 0; acpi_dev && i < numdevs; i++) { 1554 child = devlist[i]; 1555 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1556 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) { 1557 dstate = PCI_POWERSTATE_D3; 1558 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate); 1559 pci_set_powerstate(child, dstate); 1560 } 1561 } 1562 free(devlist, M_TEMP); 1563 return (0); 1564 } 1565 1566 int 1567 pci_resume(device_t dev) 1568 { 1569 int i, numdevs; 1570 device_t acpi_dev, child, *devlist; 1571 struct pci_devinfo *dinfo; 1572 1573 /* 1574 * Set each child to D0 and restore its PCI configuration space. 1575 */ 1576 acpi_dev = NULL; 1577 if (pci_do_power_resume) 1578 acpi_dev = devclass_get_device(devclass_find("acpi"), 0); 1579 device_get_children(dev, &devlist, &numdevs); 1580 for (i = 0; i < numdevs; i++) { 1581 /* 1582 * Notify ACPI we're going to D0 but ignore the result. If 1583 * ACPI is not present, the firmware is responsible for 1584 * managing device power. Only manage type 0 devices for now. 1585 */ 1586 child = devlist[i]; 1587 dinfo = (struct pci_devinfo *) device_get_ivars(child); 1588 if (acpi_dev && device_is_attached(child) && 1589 dinfo->cfg.hdrtype == 0) { 1590 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL); 1591 pci_set_powerstate(child, PCI_POWERSTATE_D0); 1592 } 1593 1594 /* Now the device is powered up, restore its config space. */ 1595 pci_cfg_restore(child, dinfo); 1596 } 1597 free(devlist, M_TEMP); 1598 return (bus_generic_resume(dev)); 1599 } 1600 1601 static void 1602 pci_load_vendor_data(void) 1603 { 1604 caddr_t vendordata, info; 1605 1606 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) { 1607 info = preload_search_info(vendordata, MODINFO_ADDR); 1608 pci_vendordata = *(char **)info; 1609 info = preload_search_info(vendordata, MODINFO_SIZE); 1610 pci_vendordata_size = *(size_t *)info; 1611 /* terminate the database */ 1612 pci_vendordata[pci_vendordata_size] = '\n'; 1613 } 1614 } 1615 1616 void 1617 pci_driver_added(device_t dev, driver_t *driver) 1618 { 1619 int numdevs; 1620 device_t *devlist; 1621 device_t child; 1622 struct pci_devinfo *dinfo; 1623 int i; 1624 1625 if (bootverbose) 1626 device_printf(dev, "driver added\n"); 1627 DEVICE_IDENTIFY(driver, dev); 1628 device_get_children(dev, &devlist, &numdevs); 1629 for (i = 0; i < numdevs; i++) { 1630 child = devlist[i]; 1631 if (device_get_state(child) != DS_NOTPRESENT) 1632 continue; 1633 dinfo = device_get_ivars(child); 1634 pci_print_verbose(dinfo); 1635 if (bootverbose) 1636 printf("pci%d:%d:%d: reprobing on driver added\n", 1637 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func); 1638 pci_cfg_restore(child, dinfo); 1639 if (device_probe_and_attach(child) != 0) 1640 pci_cfg_save(child, dinfo, 1); 1641 } 1642 free(devlist, M_TEMP); 1643 } 1644 1645 int 1646 pci_print_child(device_t dev, device_t child) 1647 { 1648 struct pci_devinfo *dinfo; 1649 struct resource_list *rl; 1650 int retval = 0; 1651 1652 dinfo = device_get_ivars(child); 1653 rl = &dinfo->resources; 1654 1655 retval += bus_print_child_header(dev, child); 1656 1657 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx"); 1658 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1659 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 1660 if (device_get_flags(dev)) 1661 retval += printf(" flags %#x", device_get_flags(dev)); 1662 1663 retval += printf(" at device %d.%d", pci_get_slot(child), 1664 pci_get_function(child)); 1665 1666 retval += bus_print_child_footer(dev, child); 1667 1668 return (retval); 1669 } 1670 1671 static struct 1672 { 1673 int class; 1674 int subclass; 1675 char *desc; 1676 } pci_nomatch_tab[] = { 1677 {PCIC_OLD, -1, "old"}, 1678 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"}, 1679 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"}, 1680 {PCIC_STORAGE, -1, "mass storage"}, 1681 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"}, 1682 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"}, 1683 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"}, 1684 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"}, 1685 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"}, 1686 {PCIC_NETWORK, -1, "network"}, 1687 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"}, 1688 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"}, 1689 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"}, 1690 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"}, 1691 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"}, 1692 {PCIC_DISPLAY, -1, "display"}, 1693 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"}, 1694 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"}, 1695 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"}, 1696 {PCIC_MULTIMEDIA, -1, "multimedia"}, 1697 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"}, 1698 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"}, 1699 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"}, 1700 {PCIC_MEMORY, -1, "memory"}, 1701 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"}, 1702 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"}, 1703 {PCIC_BRIDGE, -1, "bridge"}, 1704 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"}, 1705 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"}, 1706 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"}, 1707 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"}, 1708 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"}, 1709 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"}, 1710 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"}, 1711 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"}, 1712 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"}, 1713 {PCIC_SIMPLECOMM, -1, "simple comms"}, 1714 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */ 1715 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"}, 1716 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"}, 1717 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"}, 1718 {PCIC_BASEPERIPH, -1, "base peripheral"}, 1719 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"}, 1720 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"}, 1721 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"}, 1722 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"}, 1723 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"}, 1724 {PCIC_INPUTDEV, -1, "input device"}, 1725 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"}, 1726 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"}, 1727 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"}, 1728 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"}, 1729 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"}, 1730 {PCIC_DOCKING, -1, "docking station"}, 1731 {PCIC_PROCESSOR, -1, "processor"}, 1732 {PCIC_SERIALBUS, -1, "serial bus"}, 1733 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"}, 1734 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"}, 1735 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"}, 1736 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"}, 1737 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"}, 1738 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"}, 1739 {PCIC_WIRELESS, -1, "wireless controller"}, 1740 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"}, 1741 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"}, 1742 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"}, 1743 {PCIC_INTELLIIO, -1, "intelligent I/O controller"}, 1744 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"}, 1745 {PCIC_SATCOM, -1, "satellite communication"}, 1746 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"}, 1747 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"}, 1748 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"}, 1749 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"}, 1750 {PCIC_CRYPTO, -1, "encrypt/decrypt"}, 1751 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"}, 1752 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"}, 1753 {PCIC_DASP, -1, "dasp"}, 1754 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"}, 1755 {0, 0, NULL} 1756 }; 1757 1758 void 1759 pci_probe_nomatch(device_t dev, device_t child) 1760 { 1761 int i; 1762 char *cp, *scp, *device; 1763 1764 /* 1765 * Look for a listing for this device in a loaded device database. 1766 */ 1767 if ((device = pci_describe_device(child)) != NULL) { 1768 device_printf(dev, "<%s>", device); 1769 free(device, M_DEVBUF); 1770 } else { 1771 /* 1772 * Scan the class/subclass descriptions for a general 1773 * description. 1774 */ 1775 cp = "unknown"; 1776 scp = NULL; 1777 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) { 1778 if (pci_nomatch_tab[i].class == pci_get_class(child)) { 1779 if (pci_nomatch_tab[i].subclass == -1) { 1780 cp = pci_nomatch_tab[i].desc; 1781 } else if (pci_nomatch_tab[i].subclass == 1782 pci_get_subclass(child)) { 1783 scp = pci_nomatch_tab[i].desc; 1784 } 1785 } 1786 } 1787 device_printf(dev, "<%s%s%s>", 1788 cp ? cp : "", 1789 ((cp != NULL) && (scp != NULL)) ? ", " : "", 1790 scp ? scp : ""); 1791 } 1792 printf(" at device %d.%d (no driver attached)\n", 1793 pci_get_slot(child), pci_get_function(child)); 1794 if (pci_do_power_nodriver) 1795 pci_cfg_save(child, 1796 (struct pci_devinfo *) device_get_ivars(child), 1); 1797 return; 1798 } 1799 1800 /* 1801 * Parse the PCI device database, if loaded, and return a pointer to a 1802 * description of the device. 1803 * 1804 * The database is flat text formatted as follows: 1805 * 1806 * Any line not in a valid format is ignored. 1807 * Lines are terminated with newline '\n' characters. 1808 * 1809 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then 1810 * the vendor name. 1811 * 1812 * A DEVICE line is entered immediately below the corresponding VENDOR ID. 1813 * - devices cannot be listed without a corresponding VENDOR line. 1814 * A DEVICE line consists of a TAB, the 4 digit (hex) device code, 1815 * another TAB, then the device name. 1816 */ 1817 1818 /* 1819 * Assuming (ptr) points to the beginning of a line in the database, 1820 * return the vendor or device and description of the next entry. 1821 * The value of (vendor) or (device) inappropriate for the entry type 1822 * is set to -1. Returns nonzero at the end of the database. 1823 * 1824 * Note that this is slightly unrobust in the face of corrupt data; 1825 * we attempt to safeguard against this by spamming the end of the 1826 * database with a newline when we initialise. 1827 */ 1828 static int 1829 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc) 1830 { 1831 char *cp = *ptr; 1832 int left; 1833 1834 *device = -1; 1835 *vendor = -1; 1836 **desc = '\0'; 1837 for (;;) { 1838 left = pci_vendordata_size - (cp - pci_vendordata); 1839 if (left <= 0) { 1840 *ptr = cp; 1841 return(1); 1842 } 1843 1844 /* vendor entry? */ 1845 if (*cp != '\t' && 1846 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2) 1847 break; 1848 /* device entry? */ 1849 if (*cp == '\t' && 1850 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2) 1851 break; 1852 1853 /* skip to next line */ 1854 while (*cp != '\n' && left > 0) { 1855 cp++; 1856 left--; 1857 } 1858 if (*cp == '\n') { 1859 cp++; 1860 left--; 1861 } 1862 } 1863 /* skip to next line */ 1864 while (*cp != '\n' && left > 0) { 1865 cp++; 1866 left--; 1867 } 1868 if (*cp == '\n' && left > 0) 1869 cp++; 1870 *ptr = cp; 1871 return(0); 1872 } 1873 1874 static char * 1875 pci_describe_device(device_t dev) 1876 { 1877 int vendor, device; 1878 char *desc, *vp, *dp, *line; 1879 1880 desc = vp = dp = NULL; 1881 1882 /* 1883 * If we have no vendor data, we can't do anything. 1884 */ 1885 if (pci_vendordata == NULL) 1886 goto out; 1887 1888 /* 1889 * Scan the vendor data looking for this device 1890 */ 1891 line = pci_vendordata; 1892 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1893 goto out; 1894 for (;;) { 1895 if (pci_describe_parse_line(&line, &vendor, &device, &vp)) 1896 goto out; 1897 if (vendor == pci_get_vendor(dev)) 1898 break; 1899 } 1900 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL) 1901 goto out; 1902 for (;;) { 1903 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) { 1904 *dp = 0; 1905 break; 1906 } 1907 if (vendor != -1) { 1908 *dp = 0; 1909 break; 1910 } 1911 if (device == pci_get_device(dev)) 1912 break; 1913 } 1914 if (dp[0] == '\0') 1915 snprintf(dp, 80, "0x%x", pci_get_device(dev)); 1916 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) != 1917 NULL) 1918 sprintf(desc, "%s, %s", vp, dp); 1919 out: 1920 if (vp != NULL) 1921 free(vp, M_DEVBUF); 1922 if (dp != NULL) 1923 free(dp, M_DEVBUF); 1924 return(desc); 1925 } 1926 1927 int 1928 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1929 { 1930 struct pci_devinfo *dinfo; 1931 pcicfgregs *cfg; 1932 1933 dinfo = device_get_ivars(child); 1934 cfg = &dinfo->cfg; 1935 1936 switch (which) { 1937 case PCI_IVAR_ETHADDR: 1938 /* 1939 * The generic accessor doesn't deal with failure, so 1940 * we set the return value, then return an error. 1941 */ 1942 *((uint8_t **) result) = NULL; 1943 return (EINVAL); 1944 case PCI_IVAR_SUBVENDOR: 1945 *result = cfg->subvendor; 1946 break; 1947 case PCI_IVAR_SUBDEVICE: 1948 *result = cfg->subdevice; 1949 break; 1950 case PCI_IVAR_VENDOR: 1951 *result = cfg->vendor; 1952 break; 1953 case PCI_IVAR_DEVICE: 1954 *result = cfg->device; 1955 break; 1956 case PCI_IVAR_DEVID: 1957 *result = (cfg->device << 16) | cfg->vendor; 1958 break; 1959 case PCI_IVAR_CLASS: 1960 *result = cfg->baseclass; 1961 break; 1962 case PCI_IVAR_SUBCLASS: 1963 *result = cfg->subclass; 1964 break; 1965 case PCI_IVAR_PROGIF: 1966 *result = cfg->progif; 1967 break; 1968 case PCI_IVAR_REVID: 1969 *result = cfg->revid; 1970 break; 1971 case PCI_IVAR_INTPIN: 1972 *result = cfg->intpin; 1973 break; 1974 case PCI_IVAR_IRQ: 1975 *result = cfg->intline; 1976 break; 1977 case PCI_IVAR_BUS: 1978 *result = cfg->bus; 1979 break; 1980 case PCI_IVAR_SLOT: 1981 *result = cfg->slot; 1982 break; 1983 case PCI_IVAR_FUNCTION: 1984 *result = cfg->func; 1985 break; 1986 case PCI_IVAR_CMDREG: 1987 *result = cfg->cmdreg; 1988 break; 1989 case PCI_IVAR_CACHELNSZ: 1990 *result = cfg->cachelnsz; 1991 break; 1992 case PCI_IVAR_MINGNT: 1993 *result = cfg->mingnt; 1994 break; 1995 case PCI_IVAR_MAXLAT: 1996 *result = cfg->maxlat; 1997 break; 1998 case PCI_IVAR_LATTIMER: 1999 *result = cfg->lattimer; 2000 break; 2001 default: 2002 return (ENOENT); 2003 } 2004 return (0); 2005 } 2006 2007 int 2008 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 2009 { 2010 struct pci_devinfo *dinfo; 2011 2012 dinfo = device_get_ivars(child); 2013 2014 switch (which) { 2015 case PCI_IVAR_INTPIN: 2016 dinfo->cfg.intpin = value; 2017 return (0); 2018 case PCI_IVAR_ETHADDR: 2019 case PCI_IVAR_SUBVENDOR: 2020 case PCI_IVAR_SUBDEVICE: 2021 case PCI_IVAR_VENDOR: 2022 case PCI_IVAR_DEVICE: 2023 case PCI_IVAR_DEVID: 2024 case PCI_IVAR_CLASS: 2025 case PCI_IVAR_SUBCLASS: 2026 case PCI_IVAR_PROGIF: 2027 case PCI_IVAR_REVID: 2028 case PCI_IVAR_IRQ: 2029 case PCI_IVAR_BUS: 2030 case PCI_IVAR_SLOT: 2031 case PCI_IVAR_FUNCTION: 2032 return (EINVAL); /* disallow for now */ 2033 2034 default: 2035 return (ENOENT); 2036 } 2037 } 2038 2039 2040 #include "opt_ddb.h" 2041 #ifdef DDB 2042 #include <ddb/ddb.h> 2043 #include <sys/cons.h> 2044 2045 /* 2046 * List resources based on pci map registers, used for within ddb 2047 */ 2048 2049 DB_SHOW_COMMAND(pciregs, db_pci_dump) 2050 { 2051 struct pci_devinfo *dinfo; 2052 struct devlist *devlist_head; 2053 struct pci_conf *p; 2054 const char *name; 2055 int i, error, none_count; 2056 2057 none_count = 0; 2058 /* get the head of the device queue */ 2059 devlist_head = &pci_devq; 2060 2061 /* 2062 * Go through the list of devices and print out devices 2063 */ 2064 for (error = 0, i = 0, 2065 dinfo = STAILQ_FIRST(devlist_head); 2066 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit; 2067 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 2068 2069 /* Populate pd_name and pd_unit */ 2070 name = NULL; 2071 if (dinfo->cfg.dev) 2072 name = device_get_name(dinfo->cfg.dev); 2073 2074 p = &dinfo->conf; 2075 db_printf("%s%d@pci%d:%d:%d:\tclass=0x%06x card=0x%08x " 2076 "chip=0x%08x rev=0x%02x hdr=0x%02x\n", 2077 (name && *name) ? name : "none", 2078 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) : 2079 none_count++, 2080 p->pc_sel.pc_bus, p->pc_sel.pc_dev, 2081 p->pc_sel.pc_func, (p->pc_class << 16) | 2082 (p->pc_subclass << 8) | p->pc_progif, 2083 (p->pc_subdevice << 16) | p->pc_subvendor, 2084 (p->pc_device << 16) | p->pc_vendor, 2085 p->pc_revid, p->pc_hdr); 2086 } 2087 } 2088 #endif /* DDB */ 2089 2090 static struct resource * 2091 pci_alloc_map(device_t dev, device_t child, int type, int *rid, 2092 u_long start, u_long end, u_long count, u_int flags) 2093 { 2094 struct pci_devinfo *dinfo = device_get_ivars(child); 2095 struct resource_list *rl = &dinfo->resources; 2096 struct resource_list_entry *rle; 2097 struct resource *res; 2098 uint32_t map, testval; 2099 int mapsize; 2100 2101 /* 2102 * Weed out the bogons, and figure out how large the BAR/map 2103 * is. Bars that read back 0 here are bogus and unimplemented. 2104 * Note: atapci in legacy mode are special and handled elsewhere 2105 * in the code. If you have a atapci device in legacy mode and 2106 * it fails here, that other code is broken. 2107 */ 2108 res = NULL; 2109 map = pci_read_config(child, *rid, 4); 2110 pci_write_config(child, *rid, 0xffffffff, 4); 2111 testval = pci_read_config(child, *rid, 4); 2112 if (pci_mapbase(testval) == 0) 2113 goto out; 2114 if (pci_maptype(testval) & PCI_MAPMEM) { 2115 if (type != SYS_RES_MEMORY) { 2116 if (bootverbose) 2117 device_printf(dev, 2118 "child %s requested type %d for rid %#x," 2119 " but the BAR says it is an memio\n", 2120 device_get_nameunit(child), type, *rid); 2121 goto out; 2122 } 2123 } else { 2124 if (type != SYS_RES_IOPORT) { 2125 if (bootverbose) 2126 device_printf(dev, 2127 "child %s requested type %d for rid %#x," 2128 " but the BAR says it is an ioport\n", 2129 device_get_nameunit(child), type, *rid); 2130 goto out; 2131 } 2132 } 2133 /* 2134 * For real BARs, we need to override the size that 2135 * the driver requests, because that's what the BAR 2136 * actually uses and we would otherwise have a 2137 * situation where we might allocate the excess to 2138 * another driver, which won't work. 2139 */ 2140 mapsize = pci_mapsize(testval); 2141 count = 1 << mapsize; 2142 if (RF_ALIGNMENT(flags) < mapsize) 2143 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize); 2144 2145 /* 2146 * Allocate enough resource, and then write back the 2147 * appropriate bar for that resource. 2148 */ 2149 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid, 2150 start, end, count, flags); 2151 if (res == NULL) { 2152 device_printf(child, 2153 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n", 2154 count, *rid, type, start, end); 2155 goto out; 2156 } 2157 resource_list_add(rl, type, *rid, start, end, count); 2158 rle = resource_list_find(rl, type, *rid); 2159 if (rle == NULL) 2160 panic("pci_alloc_map: unexpectedly can't find resource."); 2161 rle->res = res; 2162 rle->start = rman_get_start(res); 2163 rle->end = rman_get_end(res); 2164 rle->count = count; 2165 if (bootverbose) 2166 device_printf(child, 2167 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n", 2168 count, *rid, type, rman_get_start(res)); 2169 map = rman_get_start(res); 2170 out:; 2171 pci_write_config(child, *rid, map, 4); 2172 return (res); 2173 } 2174 2175 2176 struct resource * 2177 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 2178 u_long start, u_long end, u_long count, u_int flags) 2179 { 2180 struct pci_devinfo *dinfo = device_get_ivars(child); 2181 struct resource_list *rl = &dinfo->resources; 2182 struct resource_list_entry *rle; 2183 pcicfgregs *cfg = &dinfo->cfg; 2184 2185 /* 2186 * Perform lazy resource allocation 2187 */ 2188 if (device_get_parent(child) == dev) { 2189 switch (type) { 2190 case SYS_RES_IRQ: 2191 /* 2192 * If the child device doesn't have an 2193 * interrupt routed and is deserving of an 2194 * interrupt, try to assign it one. 2195 */ 2196 if (!PCI_INTERRUPT_VALID(cfg->intline) && 2197 (cfg->intpin != 0)) 2198 pci_assign_interrupt(dev, child, 0); 2199 break; 2200 case SYS_RES_IOPORT: 2201 case SYS_RES_MEMORY: 2202 if (*rid < PCIR_BAR(cfg->nummaps)) { 2203 /* 2204 * Enable the I/O mode. We should 2205 * also be assigning resources too 2206 * when none are present. The 2207 * resource_list_alloc kind of sorta does 2208 * this... 2209 */ 2210 if (PCI_ENABLE_IO(dev, child, type)) 2211 return (NULL); 2212 } 2213 rle = resource_list_find(rl, type, *rid); 2214 if (rle == NULL) 2215 return (pci_alloc_map(dev, child, type, rid, 2216 start, end, count, flags)); 2217 break; 2218 } 2219 /* 2220 * If we've already allocated the resource, then 2221 * return it now. But first we may need to activate 2222 * it, since we don't allocate the resource as active 2223 * above. Normally this would be done down in the 2224 * nexus, but since we short-circuit that path we have 2225 * to do its job here. Not sure if we should free the 2226 * resource if it fails to activate. 2227 */ 2228 rle = resource_list_find(rl, type, *rid); 2229 if (rle != NULL && rle->res != NULL) { 2230 if (bootverbose) 2231 device_printf(child, 2232 "Reserved %#lx bytes for rid %#x type %d at %#lx\n", 2233 rman_get_size(rle->res), *rid, type, 2234 rman_get_start(rle->res)); 2235 if ((flags & RF_ACTIVE) && 2236 bus_generic_activate_resource(dev, child, type, 2237 *rid, rle->res) != 0) 2238 return NULL; 2239 return (rle->res); 2240 } 2241 } 2242 return (resource_list_alloc(rl, dev, child, type, rid, 2243 start, end, count, flags)); 2244 } 2245 2246 void 2247 pci_delete_resource(device_t dev, device_t child, int type, int rid) 2248 { 2249 struct pci_devinfo *dinfo; 2250 struct resource_list *rl; 2251 struct resource_list_entry *rle; 2252 2253 if (device_get_parent(child) != dev) 2254 return; 2255 2256 dinfo = device_get_ivars(child); 2257 rl = &dinfo->resources; 2258 rle = resource_list_find(rl, type, rid); 2259 if (rle) { 2260 if (rle->res) { 2261 if (rman_get_device(rle->res) != dev || 2262 rman_get_flags(rle->res) & RF_ACTIVE) { 2263 device_printf(dev, "delete_resource: " 2264 "Resource still owned by child, oops. " 2265 "(type=%d, rid=%d, addr=%lx)\n", 2266 rle->type, rle->rid, 2267 rman_get_start(rle->res)); 2268 return; 2269 } 2270 bus_release_resource(dev, type, rid, rle->res); 2271 } 2272 resource_list_delete(rl, type, rid); 2273 } 2274 /* 2275 * Why do we turn off the PCI configuration BAR when we delete a 2276 * resource? -- imp 2277 */ 2278 pci_write_config(child, rid, 0, 4); 2279 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid); 2280 } 2281 2282 struct resource_list * 2283 pci_get_resource_list (device_t dev, device_t child) 2284 { 2285 struct pci_devinfo *dinfo = device_get_ivars(child); 2286 2287 return (&dinfo->resources); 2288 } 2289 2290 uint32_t 2291 pci_read_config_method(device_t dev, device_t child, int reg, int width) 2292 { 2293 struct pci_devinfo *dinfo = device_get_ivars(child); 2294 pcicfgregs *cfg = &dinfo->cfg; 2295 2296 return (PCIB_READ_CONFIG(device_get_parent(dev), 2297 cfg->bus, cfg->slot, cfg->func, reg, width)); 2298 } 2299 2300 void 2301 pci_write_config_method(device_t dev, device_t child, int reg, 2302 uint32_t val, int width) 2303 { 2304 struct pci_devinfo *dinfo = device_get_ivars(child); 2305 pcicfgregs *cfg = &dinfo->cfg; 2306 2307 PCIB_WRITE_CONFIG(device_get_parent(dev), 2308 cfg->bus, cfg->slot, cfg->func, reg, val, width); 2309 } 2310 2311 int 2312 pci_child_location_str_method(device_t dev, device_t child, char *buf, 2313 size_t buflen) 2314 { 2315 2316 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child), 2317 pci_get_function(child)); 2318 return (0); 2319 } 2320 2321 int 2322 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 2323 size_t buflen) 2324 { 2325 struct pci_devinfo *dinfo; 2326 pcicfgregs *cfg; 2327 2328 dinfo = device_get_ivars(child); 2329 cfg = &dinfo->cfg; 2330 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x " 2331 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device, 2332 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass, 2333 cfg->progif); 2334 return (0); 2335 } 2336 2337 int 2338 pci_assign_interrupt_method(device_t dev, device_t child) 2339 { 2340 struct pci_devinfo *dinfo = device_get_ivars(child); 2341 pcicfgregs *cfg = &dinfo->cfg; 2342 2343 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, 2344 cfg->intpin)); 2345 } 2346 2347 static int 2348 pci_modevent(module_t mod, int what, void *arg) 2349 { 2350 static struct cdev *pci_cdev; 2351 2352 switch (what) { 2353 case MOD_LOAD: 2354 STAILQ_INIT(&pci_devq); 2355 pci_generation = 0; 2356 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, 2357 "pci"); 2358 pci_load_vendor_data(); 2359 break; 2360 2361 case MOD_UNLOAD: 2362 destroy_dev(pci_cdev); 2363 break; 2364 } 2365 2366 return (0); 2367 } 2368 2369 void 2370 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo) 2371 { 2372 int i; 2373 2374 /* 2375 * Only do header type 0 devices. Type 1 devices are bridges, 2376 * which we know need special treatment. Type 2 devices are 2377 * cardbus bridges which also require special treatment. 2378 * Other types are unknown, and we err on the side of safety 2379 * by ignoring them. 2380 */ 2381 if (dinfo->cfg.hdrtype != 0) 2382 return; 2383 2384 /* 2385 * Restore the device to full power mode. We must do this 2386 * before we restore the registers because moving from D3 to 2387 * D0 will cause the chip's BARs and some other registers to 2388 * be reset to some unknown power on reset values. Cut down 2389 * the noise on boot by doing nothing if we are already in 2390 * state D0. 2391 */ 2392 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 2393 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2394 } 2395 for (i = 0; i < dinfo->cfg.nummaps; i++) 2396 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4); 2397 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4); 2398 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2); 2399 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1); 2400 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1); 2401 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1); 2402 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1); 2403 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1); 2404 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1); 2405 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1); 2406 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1); 2407 } 2408 2409 void 2410 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate) 2411 { 2412 int i; 2413 uint32_t cls; 2414 int ps; 2415 2416 /* 2417 * Only do header type 0 devices. Type 1 devices are bridges, which 2418 * we know need special treatment. Type 2 devices are cardbus bridges 2419 * which also require special treatment. Other types are unknown, and 2420 * we err on the side of safety by ignoring them. Powering down 2421 * bridges should not be undertaken lightly. 2422 */ 2423 if (dinfo->cfg.hdrtype != 0) 2424 return; 2425 for (i = 0; i < dinfo->cfg.nummaps; i++) 2426 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4); 2427 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4); 2428 2429 /* 2430 * Some drivers apparently write to these registers w/o updating our 2431 * cached copy. No harm happens if we update the copy, so do so here 2432 * so we can restore them. The COMMAND register is modified by the 2433 * bus w/o updating the cache. This should represent the normally 2434 * writable portion of the 'defined' part of type 0 headers. In 2435 * theory we also need to save/restore the PCI capability structures 2436 * we know about, but apart from power we don't know any that are 2437 * writable. 2438 */ 2439 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2); 2440 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2); 2441 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2); 2442 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2); 2443 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2); 2444 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1); 2445 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1); 2446 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1); 2447 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1); 2448 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2449 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2450 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1); 2451 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1); 2452 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1); 2453 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1); 2454 2455 /* 2456 * don't set the state for display devices, base peripherals and 2457 * memory devices since bad things happen when they are powered down. 2458 * We should (a) have drivers that can easily detach and (b) use 2459 * generic drivers for these devices so that some device actually 2460 * attaches. We need to make sure that when we implement (a) we don't 2461 * power the device down on a reattach. 2462 */ 2463 cls = pci_get_class(dev); 2464 if (!setstate) 2465 return; 2466 switch (pci_do_power_nodriver) 2467 { 2468 case 0: /* NO powerdown at all */ 2469 return; 2470 case 1: /* Conservative about what to power down */ 2471 if (cls == PCIC_STORAGE) 2472 return; 2473 /*FALLTHROUGH*/ 2474 case 2: /* Agressive about what to power down */ 2475 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY || 2476 cls == PCIC_BASEPERIPH) 2477 return; 2478 /*FALLTHROUGH*/ 2479 case 3: /* Power down everything */ 2480 break; 2481 } 2482 /* 2483 * PCI spec says we can only go into D3 state from D0 state. 2484 * Transition from D[12] into D0 before going to D3 state. 2485 */ 2486 ps = pci_get_powerstate(dev); 2487 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3) 2488 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 2489 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3) 2490 pci_set_powerstate(dev, PCI_POWERSTATE_D3); 2491 } 2492