1 /* 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #include "opt_bus.h" 31 32 #include "opt_simos.h" 33 #include "opt_compat_oldpci.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/fcntl.h> 40 #include <sys/conf.h> 41 #include <sys/kernel.h> 42 #include <sys/queue.h> 43 #include <sys/types.h> 44 45 #include <vm/vm.h> 46 #include <vm/pmap.h> 47 #include <vm/vm_extern.h> 48 49 #include <sys/bus.h> 50 #include <machine/bus.h> 51 #include <sys/rman.h> 52 #include <machine/resource.h> 53 #include <machine/md_var.h> /* For the Alpha */ 54 55 #include <sys/pciio.h> 56 #include <pci/pcireg.h> 57 #include <pci/pcivar.h> 58 59 #include "pcib_if.h" 60 61 #ifdef __alpha__ 62 #include <machine/rpb.h> 63 #endif 64 65 #ifdef APIC_IO 66 #include <machine/smp.h> 67 #endif /* APIC_IO */ 68 69 static devclass_t pci_devclass; 70 71 struct pci_quirk { 72 u_int32_t devid; /* Vendor/device of the card */ 73 int type; 74 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in wierd place */ 75 int arg1; 76 int arg2; 77 }; 78 79 struct pci_quirk pci_quirks[] = { 80 /* 81 * The Intel 82371AB has a map register at offset 0x90. 82 */ 83 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, 84 85 { 0 } 86 }; 87 88 /* map register information */ 89 #define PCI_MAPMEM 0x01 /* memory map */ 90 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */ 91 #define PCI_MAPPORT 0x04 /* port map */ 92 93 static STAILQ_HEAD(devlist, pci_devinfo) pci_devq; 94 u_int32_t pci_numdevs = 0; 95 static u_int32_t pci_generation = 0; 96 97 /* return base address of memory or port map */ 98 99 static u_int32_t 100 pci_mapbase(unsigned mapreg) 101 { 102 int mask = 0x03; 103 if ((mapreg & 0x01) == 0) 104 mask = 0x0f; 105 return (mapreg & ~mask); 106 } 107 108 /* return map type of memory or port map */ 109 110 static int 111 pci_maptype(unsigned mapreg) 112 { 113 static u_int8_t maptype[0x10] = { 114 PCI_MAPMEM, PCI_MAPPORT, 115 PCI_MAPMEM, 0, 116 PCI_MAPMEM, PCI_MAPPORT, 117 0, 0, 118 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 119 PCI_MAPMEM|PCI_MAPMEMP, 0, 120 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT, 121 0, 0, 122 }; 123 124 return maptype[mapreg & 0x0f]; 125 } 126 127 /* return log2 of map size decoded for memory or port map */ 128 129 static int 130 pci_mapsize(unsigned testval) 131 { 132 int ln2size; 133 134 testval = pci_mapbase(testval); 135 ln2size = 0; 136 if (testval != 0) { 137 while ((testval & 1) == 0) 138 { 139 ln2size++; 140 testval >>= 1; 141 } 142 } 143 return (ln2size); 144 } 145 146 /* return log2 of address range supported by map register */ 147 148 static int 149 pci_maprange(unsigned mapreg) 150 { 151 int ln2range = 0; 152 switch (mapreg & 0x07) { 153 case 0x00: 154 case 0x01: 155 case 0x05: 156 ln2range = 32; 157 break; 158 case 0x02: 159 ln2range = 20; 160 break; 161 case 0x04: 162 ln2range = 64; 163 break; 164 } 165 return (ln2range); 166 } 167 168 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */ 169 170 static void 171 pci_fixancient(pcicfgregs *cfg) 172 { 173 if (cfg->hdrtype != 0) 174 return; 175 176 /* PCI to PCI bridges use header type 1 */ 177 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI) 178 cfg->hdrtype = 1; 179 } 180 181 /* read config data specific to header type 1 device (PCI to PCI bridge) */ 182 183 static void * 184 pci_readppb(device_t pcib, int b, int s, int f) 185 { 186 pcih1cfgregs *p; 187 188 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK); 189 if (p == NULL) 190 return (NULL); 191 192 bzero(p, sizeof *p); 193 194 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2); 195 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2); 196 197 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1); 198 199 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f, 200 PCIR_IOBASEH_1, 2), 201 PCIB_READ_CONFIG(pcib, b, s, f, 202 PCIR_IOBASEL_1, 1)); 203 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f, 204 PCIR_IOLIMITH_1, 2), 205 PCIB_READ_CONFIG(pcib, b, s, f, 206 PCIR_IOLIMITL_1, 1)); 207 208 p->membase = PCI_PPBMEMBASE (0, 209 PCIB_READ_CONFIG(pcib, b, s, f, 210 PCIR_MEMBASE_1, 2)); 211 p->memlimit = PCI_PPBMEMLIMIT (0, 212 PCIB_READ_CONFIG(pcib, b, s, f, 213 PCIR_MEMLIMIT_1, 2)); 214 215 p->pmembase = PCI_PPBMEMBASE ( 216 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4), 217 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2)); 218 219 p->pmemlimit = PCI_PPBMEMLIMIT ( 220 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, 221 PCIR_PMLIMITH_1, 4), 222 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2)); 223 224 return (p); 225 } 226 227 /* read config data specific to header type 2 device (PCI to CardBus bridge) */ 228 229 static void * 230 pci_readpcb(device_t pcib, int b, int s, int f) 231 { 232 pcih2cfgregs *p; 233 234 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK); 235 if (p == NULL) 236 return (NULL); 237 238 bzero(p, sizeof *p); 239 240 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2); 241 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2); 242 243 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1); 244 245 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4); 246 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4); 247 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4); 248 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4); 249 250 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4); 251 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4); 252 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4); 253 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4); 254 255 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4); 256 return p; 257 } 258 259 /* extract header type specific config data */ 260 261 static void 262 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg) 263 { 264 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 265 switch (cfg->hdrtype) { 266 case 0: 267 cfg->subvendor = REG(PCIR_SUBVEND_0, 2); 268 cfg->subdevice = REG(PCIR_SUBDEV_0, 2); 269 cfg->nummaps = PCI_MAXMAPS_0; 270 break; 271 case 1: 272 cfg->subvendor = REG(PCIR_SUBVEND_1, 2); 273 cfg->subdevice = REG(PCIR_SUBDEV_1, 2); 274 cfg->secondarybus = REG(PCIR_SECBUS_1, 1); 275 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1); 276 cfg->nummaps = PCI_MAXMAPS_1; 277 cfg->hdrspec = pci_readppb(pcib, b, s, f); 278 break; 279 case 2: 280 cfg->subvendor = REG(PCIR_SUBVEND_2, 2); 281 cfg->subdevice = REG(PCIR_SUBDEV_2, 2); 282 cfg->secondarybus = REG(PCIR_SECBUS_2, 1); 283 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1); 284 cfg->nummaps = PCI_MAXMAPS_2; 285 cfg->hdrspec = pci_readpcb(pcib, b, s, f); 286 break; 287 } 288 #undef REG 289 } 290 291 /* read configuration header into pcicfgrect structure */ 292 293 static struct pci_devinfo * 294 pci_read_device(device_t pcib, int b, int s, int f) 295 { 296 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w) 297 pcicfgregs *cfg = NULL; 298 struct pci_devinfo *devlist_entry; 299 struct devlist *devlist_head; 300 301 devlist_head = &pci_devq; 302 303 devlist_entry = NULL; 304 305 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) { 306 devlist_entry = malloc(sizeof(struct pci_devinfo), 307 M_DEVBUF, M_WAITOK); 308 if (devlist_entry == NULL) 309 return (NULL); 310 bzero(devlist_entry, sizeof *devlist_entry); 311 312 cfg = &devlist_entry->cfg; 313 314 cfg->bus = b; 315 cfg->slot = s; 316 cfg->func = f; 317 cfg->vendor = REG(PCIR_VENDOR, 2); 318 cfg->device = REG(PCIR_DEVICE, 2); 319 cfg->cmdreg = REG(PCIR_COMMAND, 2); 320 cfg->statreg = REG(PCIR_STATUS, 2); 321 cfg->baseclass = REG(PCIR_CLASS, 1); 322 cfg->subclass = REG(PCIR_SUBCLASS, 1); 323 cfg->progif = REG(PCIR_PROGIF, 1); 324 cfg->revid = REG(PCIR_REVID, 1); 325 cfg->hdrtype = REG(PCIR_HEADERTYPE, 1); 326 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1); 327 cfg->lattimer = REG(PCIR_LATTIMER, 1); 328 cfg->intpin = REG(PCIR_INTPIN, 1); 329 cfg->intline = REG(PCIR_INTLINE, 1); 330 #ifdef __alpha__ 331 alpha_platform_assign_pciintr(cfg); 332 #endif 333 334 #ifdef APIC_IO 335 if (cfg->intpin != 0) { 336 int airq; 337 338 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin); 339 if (airq >= 0) { 340 /* PCI specific entry found in MP table */ 341 if (airq != cfg->intline) { 342 undirect_pci_irq(cfg->intline); 343 cfg->intline = airq; 344 } 345 } else { 346 /* 347 * PCI interrupts might be redirected to the 348 * ISA bus according to some MP tables. Use the 349 * same methods as used by the ISA devices 350 * devices to find the proper IOAPIC int pin. 351 */ 352 airq = isa_apic_irq(cfg->intline); 353 if ((airq >= 0) && (airq != cfg->intline)) { 354 /* XXX: undirect_pci_irq() ? */ 355 undirect_isa_irq(cfg->intline); 356 cfg->intline = airq; 357 } 358 } 359 } 360 #endif /* APIC_IO */ 361 362 cfg->mingnt = REG(PCIR_MINGNT, 1); 363 cfg->maxlat = REG(PCIR_MAXLAT, 1); 364 365 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0; 366 cfg->hdrtype &= ~PCIM_MFDEV; 367 368 pci_fixancient(cfg); 369 pci_hdrtypedata(pcib, b, s, f, cfg); 370 371 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links); 372 373 devlist_entry->conf.pc_sel.pc_bus = cfg->bus; 374 devlist_entry->conf.pc_sel.pc_dev = cfg->slot; 375 devlist_entry->conf.pc_sel.pc_func = cfg->func; 376 devlist_entry->conf.pc_hdr = cfg->hdrtype; 377 378 devlist_entry->conf.pc_subvendor = cfg->subvendor; 379 devlist_entry->conf.pc_subdevice = cfg->subdevice; 380 devlist_entry->conf.pc_vendor = cfg->vendor; 381 devlist_entry->conf.pc_device = cfg->device; 382 383 devlist_entry->conf.pc_class = cfg->baseclass; 384 devlist_entry->conf.pc_subclass = cfg->subclass; 385 devlist_entry->conf.pc_progif = cfg->progif; 386 devlist_entry->conf.pc_revid = cfg->revid; 387 388 pci_numdevs++; 389 pci_generation++; 390 } 391 return (devlist_entry); 392 #undef REG 393 } 394 395 #if 0 396 /* free pcicfgregs structure and all depending data structures */ 397 398 static int 399 pci_freecfg(struct pci_devinfo *dinfo) 400 { 401 struct devlist *devlist_head; 402 403 devlist_head = &pci_devq; 404 405 if (dinfo->cfg.hdrspec != NULL) 406 free(dinfo->cfg.hdrspec, M_DEVBUF); 407 if (dinfo->cfg.map != NULL) 408 free(dinfo->cfg.map, M_DEVBUF); 409 /* XXX this hasn't been tested */ 410 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links); 411 free(dinfo, M_DEVBUF); 412 413 /* increment the generation count */ 414 pci_generation++; 415 416 /* we're losing one device */ 417 pci_numdevs--; 418 return (0); 419 } 420 #endif 421 422 423 /* 424 * This is the user interface to PCI configuration space. 425 */ 426 427 static int 428 pci_open(dev_t dev, int oflags, int devtype, struct proc *p) 429 { 430 if ((oflags & FWRITE) && securelevel > 0) { 431 return EPERM; 432 } 433 return 0; 434 } 435 436 static int 437 pci_close(dev_t dev, int flag, int devtype, struct proc *p) 438 { 439 return 0; 440 } 441 442 /* 443 * Match a single pci_conf structure against an array of pci_match_conf 444 * structures. The first argument, 'matches', is an array of num_matches 445 * pci_match_conf structures. match_buf is a pointer to the pci_conf 446 * structure that will be compared to every entry in the matches array. 447 * This function returns 1 on failure, 0 on success. 448 */ 449 static int 450 pci_conf_match(struct pci_match_conf *matches, int num_matches, 451 struct pci_conf *match_buf) 452 { 453 int i; 454 455 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0)) 456 return(1); 457 458 for (i = 0; i < num_matches; i++) { 459 /* 460 * I'm not sure why someone would do this...but... 461 */ 462 if (matches[i].flags == PCI_GETCONF_NO_MATCH) 463 continue; 464 465 /* 466 * Look at each of the match flags. If it's set, do the 467 * comparison. If the comparison fails, we don't have a 468 * match, go on to the next item if there is one. 469 */ 470 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0) 471 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus)) 472 continue; 473 474 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0) 475 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev)) 476 continue; 477 478 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0) 479 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func)) 480 continue; 481 482 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0) 483 && (match_buf->pc_vendor != matches[i].pc_vendor)) 484 continue; 485 486 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0) 487 && (match_buf->pc_device != matches[i].pc_device)) 488 continue; 489 490 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0) 491 && (match_buf->pc_class != matches[i].pc_class)) 492 continue; 493 494 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0) 495 && (match_buf->pd_unit != matches[i].pd_unit)) 496 continue; 497 498 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0) 499 && (strncmp(matches[i].pd_name, match_buf->pd_name, 500 sizeof(match_buf->pd_name)) != 0)) 501 continue; 502 503 return(0); 504 } 505 506 return(1); 507 } 508 509 /* 510 * Locate the parent of a PCI device by scanning the PCI devlist 511 * and return the entry for the parent. 512 * For devices on PCI Bus 0 (the host bus), this is the PCI Host. 513 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge. 514 */ 515 516 pcicfgregs * 517 pci_devlist_get_parent(pcicfgregs *cfg) 518 { 519 struct devlist *devlist_head; 520 struct pci_devinfo *dinfo; 521 pcicfgregs *bridge_cfg; 522 int i; 523 524 dinfo = STAILQ_FIRST(devlist_head = &pci_devq); 525 526 /* If the device is on PCI bus 0, look for the host */ 527 if (cfg->bus == 0) { 528 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 529 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 530 bridge_cfg = &dinfo->cfg; 531 if (bridge_cfg->baseclass == PCIC_BRIDGE 532 && bridge_cfg->subclass == PCIS_BRIDGE_HOST 533 && bridge_cfg->bus == cfg->bus) { 534 return bridge_cfg; 535 } 536 } 537 } 538 539 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */ 540 if (cfg->bus > 0) { 541 for (i = 0; (dinfo != NULL) && (i < pci_numdevs); 542 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 543 bridge_cfg = &dinfo->cfg; 544 if (bridge_cfg->baseclass == PCIC_BRIDGE 545 && bridge_cfg->subclass == PCIS_BRIDGE_PCI 546 && bridge_cfg->secondarybus == cfg->bus) { 547 return bridge_cfg; 548 } 549 } 550 } 551 552 return NULL; 553 } 554 555 static int 556 pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 557 { 558 device_t pci, pcib; 559 struct pci_io *io; 560 const char *name; 561 int error; 562 563 if (!(flag & FWRITE)) 564 return EPERM; 565 566 567 switch(cmd) { 568 case PCIOCGETCONF: 569 { 570 struct pci_devinfo *dinfo; 571 struct pci_conf_io *cio; 572 struct devlist *devlist_head; 573 struct pci_match_conf *pattern_buf; 574 int num_patterns; 575 size_t iolen; 576 int ionum, i; 577 578 cio = (struct pci_conf_io *)data; 579 580 num_patterns = 0; 581 dinfo = NULL; 582 583 /* 584 * Hopefully the user won't pass in a null pointer, but it 585 * can't hurt to check. 586 */ 587 if (cio == NULL) { 588 error = EINVAL; 589 break; 590 } 591 592 /* 593 * If the user specified an offset into the device list, 594 * but the list has changed since they last called this 595 * ioctl, tell them that the list has changed. They will 596 * have to get the list from the beginning. 597 */ 598 if ((cio->offset != 0) 599 && (cio->generation != pci_generation)){ 600 cio->num_matches = 0; 601 cio->status = PCI_GETCONF_LIST_CHANGED; 602 error = 0; 603 break; 604 } 605 606 /* 607 * Check to see whether the user has asked for an offset 608 * past the end of our list. 609 */ 610 if (cio->offset >= pci_numdevs) { 611 cio->num_matches = 0; 612 cio->status = PCI_GETCONF_LAST_DEVICE; 613 error = 0; 614 break; 615 } 616 617 /* get the head of the device queue */ 618 devlist_head = &pci_devq; 619 620 /* 621 * Determine how much room we have for pci_conf structures. 622 * Round the user's buffer size down to the nearest 623 * multiple of sizeof(struct pci_conf) in case the user 624 * didn't specify a multiple of that size. 625 */ 626 iolen = min(cio->match_buf_len - 627 (cio->match_buf_len % sizeof(struct pci_conf)), 628 pci_numdevs * sizeof(struct pci_conf)); 629 630 /* 631 * Since we know that iolen is a multiple of the size of 632 * the pciconf union, it's okay to do this. 633 */ 634 ionum = iolen / sizeof(struct pci_conf); 635 636 /* 637 * If this test is true, the user wants the pci_conf 638 * structures returned to match the supplied entries. 639 */ 640 if ((cio->num_patterns > 0) 641 && (cio->pat_buf_len > 0)) { 642 /* 643 * pat_buf_len needs to be: 644 * num_patterns * sizeof(struct pci_match_conf) 645 * While it is certainly possible the user just 646 * allocated a large buffer, but set the number of 647 * matches correctly, it is far more likely that 648 * their kernel doesn't match the userland utility 649 * they're using. It's also possible that the user 650 * forgot to initialize some variables. Yes, this 651 * may be overly picky, but I hazard to guess that 652 * it's far more likely to just catch folks that 653 * updated their kernel but not their userland. 654 */ 655 if ((cio->num_patterns * 656 sizeof(struct pci_match_conf)) != cio->pat_buf_len){ 657 /* The user made a mistake, return an error*/ 658 cio->status = PCI_GETCONF_ERROR; 659 printf("pci_ioctl: pat_buf_len %d != " 660 "num_patterns (%d) * sizeof(struct " 661 "pci_match_conf) (%d)\npci_ioctl: " 662 "pat_buf_len should be = %d\n", 663 cio->pat_buf_len, cio->num_patterns, 664 (int)sizeof(struct pci_match_conf), 665 (int)sizeof(struct pci_match_conf) * 666 cio->num_patterns); 667 printf("pci_ioctl: do your headers match your " 668 "kernel?\n"); 669 cio->num_matches = 0; 670 error = EINVAL; 671 break; 672 } 673 674 /* 675 * Check the user's buffer to make sure it's readable. 676 */ 677 if (!useracc((caddr_t)cio->patterns, 678 cio->pat_buf_len, VM_PROT_READ)) { 679 printf("pci_ioctl: pattern buffer %p, " 680 "length %u isn't user accessible for" 681 " READ\n", cio->patterns, 682 cio->pat_buf_len); 683 error = EACCES; 684 break; 685 } 686 /* 687 * Allocate a buffer to hold the patterns. 688 */ 689 pattern_buf = malloc(cio->pat_buf_len, M_TEMP, 690 M_WAITOK); 691 error = copyin(cio->patterns, pattern_buf, 692 cio->pat_buf_len); 693 if (error != 0) 694 break; 695 num_patterns = cio->num_patterns; 696 697 } else if ((cio->num_patterns > 0) 698 || (cio->pat_buf_len > 0)) { 699 /* 700 * The user made a mistake, spit out an error. 701 */ 702 cio->status = PCI_GETCONF_ERROR; 703 cio->num_matches = 0; 704 printf("pci_ioctl: invalid GETCONF arguments\n"); 705 error = EINVAL; 706 break; 707 } else 708 pattern_buf = NULL; 709 710 /* 711 * Make sure we can write to the match buffer. 712 */ 713 if (!useracc((caddr_t)cio->matches, 714 cio->match_buf_len, VM_PROT_WRITE)) { 715 printf("pci_ioctl: match buffer %p, length %u " 716 "isn't user accessible for WRITE\n", 717 cio->matches, cio->match_buf_len); 718 error = EACCES; 719 break; 720 } 721 722 /* 723 * Go through the list of devices and copy out the devices 724 * that match the user's criteria. 725 */ 726 for (cio->num_matches = 0, error = 0, i = 0, 727 dinfo = STAILQ_FIRST(devlist_head); 728 (dinfo != NULL) && (cio->num_matches < ionum) 729 && (error == 0) && (i < pci_numdevs); 730 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) { 731 732 if (i < cio->offset) 733 continue; 734 735 /* Populate pd_name and pd_unit */ 736 name = NULL; 737 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0') 738 name = device_get_name(dinfo->cfg.dev); 739 if (name) { 740 strncpy(dinfo->conf.pd_name, name, 741 sizeof(dinfo->conf.pd_name)); 742 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0; 743 dinfo->conf.pd_unit = 744 device_get_unit(dinfo->cfg.dev); 745 } 746 747 if ((pattern_buf == NULL) || 748 (pci_conf_match(pattern_buf, num_patterns, 749 &dinfo->conf) == 0)) { 750 751 /* 752 * If we've filled up the user's buffer, 753 * break out at this point. Since we've 754 * got a match here, we'll pick right back 755 * up at the matching entry. We can also 756 * tell the user that there are more matches 757 * left. 758 */ 759 if (cio->num_matches >= ionum) 760 break; 761 762 error = copyout(&dinfo->conf, 763 &cio->matches[cio->num_matches], 764 sizeof(struct pci_conf)); 765 cio->num_matches++; 766 } 767 } 768 769 /* 770 * Set the pointer into the list, so if the user is getting 771 * n records at a time, where n < pci_numdevs, 772 */ 773 cio->offset = i; 774 775 /* 776 * Set the generation, the user will need this if they make 777 * another ioctl call with offset != 0. 778 */ 779 cio->generation = pci_generation; 780 781 /* 782 * If this is the last device, inform the user so he won't 783 * bother asking for more devices. If dinfo isn't NULL, we 784 * know that there are more matches in the list because of 785 * the way the traversal is done. 786 */ 787 if (dinfo == NULL) 788 cio->status = PCI_GETCONF_LAST_DEVICE; 789 else 790 cio->status = PCI_GETCONF_MORE_DEVS; 791 792 if (pattern_buf != NULL) 793 free(pattern_buf, M_TEMP); 794 795 break; 796 } 797 case PCIOCREAD: 798 io = (struct pci_io *)data; 799 switch(io->pi_width) { 800 case 4: 801 case 2: 802 case 1: 803 /* 804 * Assume that the user-level bus number is 805 * actually the pciN instance number. We map 806 * from that to the real pcib+bus combination. 807 */ 808 pci = devclass_get_device(pci_devclass, 809 io->pi_sel.pc_bus); 810 if (pci) { 811 int b = pcib_get_bus(pci); 812 pcib = device_get_parent(pci); 813 io->pi_data = 814 PCIB_READ_CONFIG(pcib, 815 b, 816 io->pi_sel.pc_dev, 817 io->pi_sel.pc_func, 818 io->pi_reg, 819 io->pi_width); 820 error = 0; 821 } else { 822 error = ENODEV; 823 } 824 break; 825 default: 826 error = ENODEV; 827 break; 828 } 829 break; 830 831 case PCIOCWRITE: 832 io = (struct pci_io *)data; 833 switch(io->pi_width) { 834 case 4: 835 case 2: 836 case 1: 837 /* 838 * Assume that the user-level bus number is 839 * actually the pciN instance number. We map 840 * from that to the real pcib+bus combination. 841 */ 842 pci = devclass_get_device(pci_devclass, 843 io->pi_sel.pc_bus); 844 if (pci) { 845 int b = pcib_get_bus(pci); 846 pcib = device_get_parent(pci); 847 PCIB_WRITE_CONFIG(pcib, 848 b, 849 io->pi_sel.pc_dev, 850 io->pi_sel.pc_func, 851 io->pi_reg, 852 io->pi_data, 853 io->pi_width); 854 error = 0; 855 } else { 856 error = ENODEV; 857 } 858 break; 859 default: 860 error = ENODEV; 861 break; 862 } 863 break; 864 865 default: 866 error = ENOTTY; 867 break; 868 } 869 870 return (error); 871 } 872 873 #define PCI_CDEV 78 874 875 static struct cdevsw pcicdev = { 876 /* open */ pci_open, 877 /* close */ pci_close, 878 /* read */ noread, 879 /* write */ nowrite, 880 /* ioctl */ pci_ioctl, 881 /* poll */ nopoll, 882 /* mmap */ nommap, 883 /* strategy */ nostrategy, 884 /* name */ "pci", 885 /* maj */ PCI_CDEV, 886 /* dump */ nodump, 887 /* psize */ nopsize, 888 /* flags */ 0, 889 /* bmaj */ -1 890 }; 891 892 #include "pci_if.h" 893 894 /* 895 * New style pci driver. Parent device is either a pci-host-bridge or a 896 * pci-pci-bridge. Both kinds are represented by instances of pcib. 897 */ 898 899 static void 900 pci_print_verbose(struct pci_devinfo *dinfo) 901 { 902 if (bootverbose) { 903 pcicfgregs *cfg = &dinfo->cfg; 904 905 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n", 906 cfg->vendor, cfg->device, cfg->revid); 907 printf("\tbus=%d, slot=%d, func=%d\n", 908 cfg->bus, cfg->slot, cfg->func); 909 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n", 910 cfg->baseclass, cfg->subclass, cfg->progif, 911 cfg->hdrtype, cfg->mfdev); 912 printf("\tsubordinatebus=%x \tsecondarybus=%x\n", 913 cfg->subordinatebus, cfg->secondarybus); 914 #ifdef PCI_DEBUG 915 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n", 916 cfg->cmdreg, cfg->statreg, cfg->cachelnsz); 917 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n", 918 cfg->lattimer, cfg->lattimer * 30, 919 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250); 920 #endif /* PCI_DEBUG */ 921 if (cfg->intpin > 0) 922 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline); 923 } 924 } 925 926 static int 927 pci_porten(device_t pcib, int b, int s, int f) 928 { 929 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 930 & PCIM_CMD_PORTEN) != 0; 931 } 932 933 static int 934 pci_memen(device_t pcib, int b, int s, int f) 935 { 936 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2) 937 & PCIM_CMD_MEMEN) != 0; 938 } 939 940 /* 941 * Add a resource based on a pci map register. Return 1 if the map 942 * register is a 32bit map register or 2 if it is a 64bit register. 943 */ 944 static int 945 pci_add_map(device_t pcib, int b, int s, int f, int reg, 946 struct resource_list *rl) 947 { 948 u_int32_t map; 949 u_int64_t base; 950 u_int8_t ln2size; 951 u_int8_t ln2range; 952 u_int32_t testval; 953 #ifdef PCI_ENABLE_IO_MODES 954 u_int16_t cmd; 955 #endif 956 int type; 957 958 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 959 960 if (map == 0 || map == 0xffffffff) 961 return 1; /* skip invalid entry */ 962 963 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4); 964 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4); 965 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4); 966 967 base = pci_mapbase(map); 968 if (pci_maptype(map) & PCI_MAPMEM) 969 type = SYS_RES_MEMORY; 970 else 971 type = SYS_RES_IOPORT; 972 ln2size = pci_mapsize(testval); 973 ln2range = pci_maprange(testval); 974 if (ln2range == 64) { 975 /* Read the other half of a 64bit map register */ 976 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32; 977 } 978 979 if (bootverbose) { 980 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d", 981 reg, pci_maptype(map), ln2range, 982 (unsigned int) base, ln2size); 983 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 984 printf(", port disabled\n"); 985 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 986 printf(", memory disabled\n"); 987 else 988 printf(", enabled\n"); 989 } 990 991 /* 992 * This code theoretically does the right thing, but has 993 * undesirable side effects in some cases where 994 * peripherals respond oddly to having these bits 995 * enabled. Leave them alone by default. 996 */ 997 #ifdef PCI_ENABLE_IO_MODES 998 /* Turn on resources that have been left off by a lazy BIOS */ 999 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) { 1000 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1001 cmd |= PCIM_CMD_PORTEN; 1002 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1003 } 1004 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) { 1005 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2); 1006 cmd |= PCIM_CMD_MEMEN; 1007 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2); 1008 } 1009 #else 1010 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) 1011 return 1; 1012 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) 1013 return 1; 1014 #endif 1015 1016 resource_list_add(rl, type, reg, 1017 base, base + (1 << ln2size) - 1, 1018 (1 << ln2size)); 1019 1020 return (ln2range == 64) ? 2 : 1; 1021 } 1022 1023 static void 1024 pci_add_resources(device_t pcib, int b, int s, int f, device_t dev) 1025 { 1026 struct pci_devinfo *dinfo = device_get_ivars(dev); 1027 pcicfgregs *cfg = &dinfo->cfg; 1028 struct resource_list *rl = &dinfo->resources; 1029 struct pci_quirk *q; 1030 int i; 1031 1032 for (i = 0; i < cfg->nummaps;) { 1033 i += pci_add_map(pcib, b, s, f, PCIR_MAPS + i*4, rl); 1034 } 1035 1036 for (q = &pci_quirks[0]; q->devid; q++) { 1037 if (q->devid == ((cfg->device << 16) | cfg->vendor) 1038 && q->type == PCI_QUIRK_MAP_REG) 1039 pci_add_map(pcib, b, s, f, q->arg1, rl); 1040 } 1041 1042 if (cfg->intpin > 0 && cfg->intline != 255) 1043 resource_list_add(rl, SYS_RES_IRQ, 0, 1044 cfg->intline, cfg->intline, 1); 1045 } 1046 1047 static void 1048 pci_add_children(device_t dev, int busno) 1049 { 1050 device_t pcib = device_get_parent(dev); 1051 int maxslots; 1052 int s, f; 1053 1054 maxslots = PCIB_MAXSLOTS(pcib); 1055 1056 for (s = 0; s <= maxslots; s++) { 1057 int pcifunchigh = 0; 1058 for (f = 0; f <= pcifunchigh; f++) { 1059 struct pci_devinfo *dinfo = 1060 pci_read_device(pcib, busno, s, f); 1061 if (dinfo != NULL) { 1062 if (dinfo->cfg.mfdev) 1063 pcifunchigh = 7; 1064 1065 pci_print_verbose(dinfo); 1066 dinfo->cfg.dev = device_add_child(dev, NULL, -1); 1067 device_set_ivars(dinfo->cfg.dev, dinfo); 1068 pci_add_resources(pcib, busno, s, f, 1069 dinfo->cfg.dev); 1070 } 1071 } 1072 } 1073 } 1074 1075 static int 1076 pci_probe(device_t dev) 1077 { 1078 static int once, busno; 1079 1080 device_set_desc(dev, "PCI bus"); 1081 1082 if (bootverbose) 1083 device_printf(dev, "physical bus=%d\n", pcib_get_bus(dev)); 1084 1085 /* 1086 * Since there can be multiple independantly numbered PCI 1087 * busses on some large alpha systems, we can't use the unit 1088 * number to decide what bus we are probing. We ask the parent 1089 * pcib what our bus number is. 1090 */ 1091 busno = pcib_get_bus(dev); 1092 if (busno < 0) 1093 return ENXIO; 1094 pci_add_children(dev, busno); 1095 1096 if (!once) { 1097 make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, "pci"); 1098 once++; 1099 } 1100 1101 return 0; 1102 } 1103 1104 static int 1105 pci_print_resources(struct resource_list *rl, const char *name, int type, 1106 const char *format) 1107 { 1108 struct resource_list_entry *rle; 1109 int printed, retval; 1110 1111 printed = 0; 1112 retval = 0; 1113 /* Yes, this is kinda cheating */ 1114 SLIST_FOREACH(rle, rl, link) { 1115 if (rle->type == type) { 1116 if (printed == 0) 1117 retval += printf(" %s ", name); 1118 else if (printed > 0) 1119 retval += printf(","); 1120 printed++; 1121 retval += printf(format, rle->start); 1122 if (rle->count > 1) { 1123 retval += printf("-"); 1124 retval += printf(format, rle->start + 1125 rle->count - 1); 1126 } 1127 } 1128 } 1129 return retval; 1130 } 1131 1132 static int 1133 pci_print_child(device_t dev, device_t child) 1134 { 1135 struct pci_devinfo *dinfo; 1136 struct resource_list *rl; 1137 pcicfgregs *cfg; 1138 int retval = 0; 1139 1140 dinfo = device_get_ivars(child); 1141 cfg = &dinfo->cfg; 1142 rl = &dinfo->resources; 1143 1144 retval += bus_print_child_header(dev, child); 1145 1146 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx"); 1147 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx"); 1148 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld"); 1149 if (device_get_flags(dev)) 1150 retval += printf(" flags %#x", device_get_flags(dev)); 1151 1152 retval += printf(" at device %d.%d", pci_get_slot(child), 1153 pci_get_function(child)); 1154 1155 retval += bus_print_child_footer(dev, child); 1156 1157 return (retval); 1158 } 1159 1160 static void 1161 pci_probe_nomatch(device_t dev, device_t child) 1162 { 1163 struct pci_devinfo *dinfo; 1164 pcicfgregs *cfg; 1165 const char *desc; 1166 int unknown; 1167 1168 unknown = 0; 1169 dinfo = device_get_ivars(child); 1170 cfg = &dinfo->cfg; 1171 desc = pci_ata_match(child); 1172 if (!desc) desc = pci_usb_match(child); 1173 if (!desc) desc = pci_vga_match(child); 1174 if (!desc) desc = pci_chip_match(child); 1175 if (!desc) { 1176 desc = "unknown card"; 1177 unknown++; 1178 } 1179 device_printf(dev, "<%s>", desc); 1180 if (bootverbose || unknown) { 1181 printf(" (vendor=0x%04x, dev=0x%04x)", 1182 cfg->vendor, 1183 cfg->device); 1184 } 1185 printf(" at %d.%d", 1186 pci_get_slot(child), 1187 pci_get_function(child)); 1188 if (cfg->intpin > 0 && cfg->intline != 255) { 1189 printf(" irq %d", cfg->intline); 1190 } 1191 printf("\n"); 1192 1193 return; 1194 } 1195 1196 static int 1197 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1198 { 1199 struct pci_devinfo *dinfo; 1200 pcicfgregs *cfg; 1201 1202 dinfo = device_get_ivars(child); 1203 cfg = &dinfo->cfg; 1204 1205 switch (which) { 1206 case PCI_IVAR_SUBVENDOR: 1207 *result = cfg->subvendor; 1208 break; 1209 case PCI_IVAR_SUBDEVICE: 1210 *result = cfg->subdevice; 1211 break; 1212 case PCI_IVAR_VENDOR: 1213 *result = cfg->vendor; 1214 break; 1215 case PCI_IVAR_DEVICE: 1216 *result = cfg->device; 1217 break; 1218 case PCI_IVAR_DEVID: 1219 *result = (cfg->device << 16) | cfg->vendor; 1220 break; 1221 case PCI_IVAR_CLASS: 1222 *result = cfg->baseclass; 1223 break; 1224 case PCI_IVAR_SUBCLASS: 1225 *result = cfg->subclass; 1226 break; 1227 case PCI_IVAR_PROGIF: 1228 *result = cfg->progif; 1229 break; 1230 case PCI_IVAR_REVID: 1231 *result = cfg->revid; 1232 break; 1233 case PCI_IVAR_INTPIN: 1234 *result = cfg->intpin; 1235 break; 1236 case PCI_IVAR_IRQ: 1237 *result = cfg->intline; 1238 break; 1239 case PCI_IVAR_BUS: 1240 *result = cfg->bus; 1241 break; 1242 case PCI_IVAR_SLOT: 1243 *result = cfg->slot; 1244 break; 1245 case PCI_IVAR_FUNCTION: 1246 *result = cfg->func; 1247 break; 1248 case PCI_IVAR_SECONDARYBUS: 1249 *result = cfg->secondarybus; 1250 break; 1251 case PCI_IVAR_SUBORDINATEBUS: 1252 *result = cfg->subordinatebus; 1253 break; 1254 default: 1255 return ENOENT; 1256 } 1257 return 0; 1258 } 1259 1260 static int 1261 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1262 { 1263 struct pci_devinfo *dinfo; 1264 pcicfgregs *cfg; 1265 1266 dinfo = device_get_ivars(child); 1267 cfg = &dinfo->cfg; 1268 1269 switch (which) { 1270 case PCI_IVAR_SUBVENDOR: 1271 case PCI_IVAR_SUBDEVICE: 1272 case PCI_IVAR_VENDOR: 1273 case PCI_IVAR_DEVICE: 1274 case PCI_IVAR_DEVID: 1275 case PCI_IVAR_CLASS: 1276 case PCI_IVAR_SUBCLASS: 1277 case PCI_IVAR_PROGIF: 1278 case PCI_IVAR_REVID: 1279 case PCI_IVAR_INTPIN: 1280 case PCI_IVAR_IRQ: 1281 case PCI_IVAR_BUS: 1282 case PCI_IVAR_SLOT: 1283 case PCI_IVAR_FUNCTION: 1284 return EINVAL; /* disallow for now */ 1285 1286 case PCI_IVAR_SECONDARYBUS: 1287 cfg->secondarybus = value; 1288 break; 1289 case PCI_IVAR_SUBORDINATEBUS: 1290 cfg->subordinatebus = value; 1291 break; 1292 default: 1293 return ENOENT; 1294 } 1295 return 0; 1296 } 1297 1298 static struct resource * 1299 pci_alloc_resource(device_t dev, device_t child, int type, int *rid, 1300 u_long start, u_long end, u_long count, u_int flags) 1301 { 1302 struct pci_devinfo *dinfo = device_get_ivars(child); 1303 struct resource_list *rl = &dinfo->resources; 1304 pcicfgregs *cfg = &dinfo->cfg; 1305 1306 /* 1307 * Perform lazy resource allocation 1308 * 1309 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY 1310 */ 1311 if (device_get_parent(child) == dev) { 1312 if ((type == SYS_RES_IRQ) && (cfg->intline == 255)) { 1313 #ifdef __i386__ 1314 cfg->intline = PCIB_ROUTE_INTERRUPT( 1315 device_get_parent(dev), pci_get_slot(child), 1316 cfg->intpin); 1317 #endif /* __i386__ */ 1318 if (cfg->intline != 255) { 1319 pci_write_config(child, PCIR_INTLINE, cfg->intline, 1); 1320 resource_list_add(rl, SYS_RES_IRQ, 0, 1321 cfg->intline, cfg->intline, 1); 1322 } 1323 } 1324 } 1325 1326 return resource_list_alloc(rl, dev, child, type, rid, 1327 start, end, count, flags); 1328 } 1329 1330 static int 1331 pci_release_resource(device_t dev, device_t child, int type, int rid, 1332 struct resource *r) 1333 { 1334 struct pci_devinfo *dinfo = device_get_ivars(child); 1335 struct resource_list *rl = &dinfo->resources; 1336 1337 return resource_list_release(rl, dev, child, type, rid, r); 1338 } 1339 1340 static int 1341 pci_set_resource(device_t dev, device_t child, int type, int rid, 1342 u_long start, u_long count) 1343 { 1344 struct pci_devinfo *dinfo = device_get_ivars(child); 1345 struct resource_list *rl = &dinfo->resources; 1346 1347 resource_list_add(rl, type, rid, start, start + count - 1, count); 1348 return 0; 1349 } 1350 1351 static int 1352 pci_get_resource(device_t dev, device_t child, int type, int rid, 1353 u_long *startp, u_long *countp) 1354 { 1355 struct pci_devinfo *dinfo = device_get_ivars(child); 1356 struct resource_list *rl = &dinfo->resources; 1357 struct resource_list_entry *rle; 1358 1359 rle = resource_list_find(rl, type, rid); 1360 if (!rle) 1361 return ENOENT; 1362 1363 if (startp) 1364 *startp = rle->start; 1365 if (countp) 1366 *countp = rle->count; 1367 1368 return 0; 1369 } 1370 1371 static void 1372 pci_delete_resource(device_t dev, device_t child, int type, int rid) 1373 { 1374 printf("pci_delete_resource: PCI resources can not be deleted\n"); 1375 } 1376 1377 static u_int32_t 1378 pci_read_config_method(device_t dev, device_t child, int reg, int width) 1379 { 1380 struct pci_devinfo *dinfo = device_get_ivars(child); 1381 pcicfgregs *cfg = &dinfo->cfg; 1382 1383 return PCIB_READ_CONFIG(device_get_parent(dev), 1384 cfg->bus, cfg->slot, cfg->func, 1385 reg, width); 1386 } 1387 1388 static void 1389 pci_write_config_method(device_t dev, device_t child, int reg, 1390 u_int32_t val, int width) 1391 { 1392 struct pci_devinfo *dinfo = device_get_ivars(child); 1393 pcicfgregs *cfg = &dinfo->cfg; 1394 1395 PCIB_WRITE_CONFIG(device_get_parent(dev), 1396 cfg->bus, cfg->slot, cfg->func, 1397 reg, val, width); 1398 } 1399 1400 static int 1401 pci_modevent(module_t mod, int what, void *arg) 1402 { 1403 switch (what) { 1404 case MOD_LOAD: 1405 STAILQ_INIT(&pci_devq); 1406 break; 1407 1408 case MOD_UNLOAD: 1409 break; 1410 } 1411 1412 return 0; 1413 } 1414 1415 static device_method_t pci_methods[] = { 1416 /* Device interface */ 1417 DEVMETHOD(device_probe, pci_probe), 1418 DEVMETHOD(device_attach, bus_generic_attach), 1419 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1420 DEVMETHOD(device_suspend, bus_generic_suspend), 1421 DEVMETHOD(device_resume, bus_generic_resume), 1422 1423 /* Bus interface */ 1424 DEVMETHOD(bus_print_child, pci_print_child), 1425 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch), 1426 DEVMETHOD(bus_read_ivar, pci_read_ivar), 1427 DEVMETHOD(bus_write_ivar, pci_write_ivar), 1428 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 1429 DEVMETHOD(bus_alloc_resource, pci_alloc_resource), 1430 DEVMETHOD(bus_release_resource, pci_release_resource), 1431 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1432 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 1433 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1434 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1435 DEVMETHOD(bus_set_resource, pci_set_resource), 1436 DEVMETHOD(bus_get_resource, pci_get_resource), 1437 DEVMETHOD(bus_delete_resource, pci_delete_resource), 1438 1439 /* PCI interface */ 1440 DEVMETHOD(pci_read_config, pci_read_config_method), 1441 DEVMETHOD(pci_write_config, pci_write_config_method), 1442 1443 { 0, 0 } 1444 }; 1445 1446 static driver_t pci_driver = { 1447 "pci", 1448 pci_methods, 1449 1, /* no softc */ 1450 }; 1451 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0); 1452 DRIVER_MODULE(pci, acpi_pcib, pci_driver, pci_devclass, pci_modevent, 0); 1453